[ { "path": ".github/scripts/breakpoint.sh", "content": "#!/bin/bash\n# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\nset -ex\n\n# Invoke GDB\n${GCC_PREFIX}-gdb -n --batch -x breakpoint.gdb >gdb.log\n# Parse the log\ncat gdb.log | grep 'Breakpoint 1,' >breakpoint.txt\n\n# Compare the dumps\ndiff -E -y breakpoint.txt breakpoint_golden.txt || true\n\n" }, { "path": ".github/scripts/common.inc.sh", "content": "#!/bin/bash\n\nset -e -u -o pipefail\n\nCOLOR_CLEAR=\"\\033[0m\"\nCOLOR_RED=\"\\033[0;31m\"\nCOLOR_GREEN=\"\\033[1;32m\"\nCOLOR_YELLOW=\"\\033[1;33m\"\nCOLOR_WHITE=\"\\033[1;37m\"\n\ncheck_args_count(){\n # Check argument count function is meant to be used to check if\n # the number of received arguments is equal to the expected.\n # If they are unequal, the function returns with error\n # Args:\n # argc_got - Number of received arguments, e.g.: $#\n # argc_expected - Number of expected arguments, e.g.: 2\n argc_got=$1\n argc_expected=$2\n if [ ${argc_got} -ne ${argc_expected} ]; then\n echo -e \"${COLOR_WHITE}Expected ${argc_expected} arguments, but received ${argc_got} ${COLOR_RED}FAIL${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE}Caller:${COLOR_CLEAR}\" `caller`\n exit 1\n fi\n}\n" }, { "path": ".github/scripts/convert_dat.sh", "content": "#!/bin/bash\n\nDAT_FILE=\"${1}\"\nINFO_FILE=\"${2}\"\n\nverilator_coverage --skip-toggle --write-info \"${INFO_FILE}_branch.info\" \"${DAT_FILE}\"\nverilator_coverage --toggle-only --write-info \"${INFO_FILE}_toggle.info\" \"${DAT_FILE}\"\n" }, { "path": ".github/scripts/create_merged_package.sh", "content": "#!/bin/bash\n\nset -eux\nset -o pipefail\n\n# The script needs to be run with V package prepared in data_v\n# and Verilator package prepared in data_verilator.\n\n# Note that config.json will contain output of this script.\n# It will be basically data_v/config.json with \"datasets\" key removed\n# so that it's regenerated by info-process with minor other modifications.\npython3 <config.json\nimport json\n\nwith open('data_v/config.json') as f:\n config = json.load(f)\n\nwith open('data_verilator/config.json') as f:\n verilator_config = json.load(f)\n\ndb_count_v = config['additional'].pop('db_count')\nconfig['additional']['db_count_verilator'] = verilator_config['additional']['db_count']\nconfig['additional']['db_count_v'] = db_count_v\n\nconfig['timestamp'] = '`date +\"%Y-%m-%dT%H:%M:%S.%3N%z\"`'\n\ndel config['datasets']\n\nprint(json.dumps(config, indent=2))\nEND\n\n_out_dir=data_both\n\n# The order of INFO files influences order of datasets that will be\n# generated based on passed INFO files and added to config.json.\ninfo-process pack --output $_out_dir --config config.json \\\n --coverage-files data_v/*.info data_verilator/*.info \\\n --description-files data_verilator/*.desc data_v/*.desc \\\n --extra-files data_v/logo.svg\n\ncat $_out_dir/config.json\n\necho \"Merged coverage data ready to be packaged in $PWD/$_out_dir\"\n" }, { "path": ".github/scripts/gdb_test.sh", "content": "#!/bin/bash\n# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\n# This script runs Verilator RTL simulation and OpenOCD in background, invokes\n# the supplied test command and shuts everything down.\n\nSIM_LOG=`realpath sim.log`\nOPENOCD_LOG=`realpath openocd.log`\nGDB_LOG=`realpath gdb.log`\n\nif [ -z $GCC_PREFIX ]; then\n GCC_PREFIX=riscv64-unknown-elf\nfi\n\n# Ensure that RISC-V toolchain is installed\nif ! which ${GCC_PREFIX}-gcc >/dev/null; then\n GCC_PREFIX=riscv32-unknown-elf\nfi\nif ! which ${GCC_PREFIX}-gcc >/dev/null; then\n echo \"RISC-V toolchain not found, please refer to https://github.com/chipsalliance/caliptra-rtl?tab=readme-ov-file#riscv-toolchain-installation for more details.\"\n exit 1\nfi\nexport GCC_PREFIX\n\nset +e\n\n# Utils\nsource `dirname ${BASH_SOURCE[0]}`/utils.sh\n\nterminate_all () {\n terminate ${OPENOCD_PID}\n echo \"waiting for the simulation to end: $SIM_PID\"\n wait ${SIM_PID}\n # terminate ${SIM_PID}\n}\n\nprint_logs () {\n echo -e \"${COLOR_WHITE}======== OpenOCD log ========${COLOR_OFF}\"\n cat ${OPENOCD_LOG} || true\n echo -e \"${COLOR_WHITE}======== Simulation log ========${COLOR_OFF}\"\n cat ${SIM_LOG} || true\n echo -e \"${COLOR_WHITE}======== GDB log ========${COLOR_OFF}\"\n cat ${GDB_LOG} || true\n}\n\necho -e \"${COLOR_WHITE}======== Launching interactive simulation ========${COLOR_OFF}\"\n\n# Start the simulation\necho -e \"Starting simulation...\"\nif [ -f obj_dir/Vtb_top ]; then\n SIM_START_STRING=\"VerilatorTB: Start of sim\"\n obj_dir/Vtb_top >\"${SIM_LOG}\" 2>&1 &\nelif [ -f ./simv ]; then\n SIM_START_STRING=\" remote_bitbang_port 5000\"\n ./simv +vcs+lic+wait -cm line+cond+fsm+tgl+branch >\"${SIM_LOG}\" 2>&1 &\nelse\n echo \"No simulation binary found, exiting\"\n exit 1\nfi\nSIM_PID=$!\n\n# Wait\nwait_for_phrase \"${SIM_LOG}\" \"${SIM_START_STRING}\"\nsleep 1s\nretcode=$?\nif [ $retcode -ne 0 ]; then\n echo -e \"${COLOR_RED}Failed to start the simulation: $retcode ${COLOR_OFF}\"\n print_logs\n terminate_all; exit -1\nfi\necho -e \"Simulation running and ready (pid=${SIM_PID})\"\n\n# Launch OpenOCD\necho -e \"Launching OpenOCD...\"\nWORKDIR=$PWD\ncd ${RV_ROOT}/.github/scripts/openocd\nopenocd -d2 --file board/caliptra-verilator.cfg > ${OPENOCD_LOG} 2>&1 &\nOPENOCD_PID=$!\ncd $WORKDIR\n\n# Wait\nwait_for_phrase \"${OPENOCD_LOG}\" \"Listening on port 3333 for gdb connections\"\nif [ $? -ne 0 ]; then\n echo -e \"${COLOR_RED}Failed to start OpenOCD!${COLOR_OFF}\"\n print_logs\n terminate_all; exit -1\nfi\necho -e \"OpenOCD running and ready (pid=${OPENOCD_PID})\"\n\n# Wait a bit\nsleep 1s\n\n# Run the test\necho -e \"${COLOR_WHITE}======== Running GDB script test.gdb ========${COLOR_OFF}\"\n\n${GCC_PREFIX}-gdb -n --batch -x ${RV_ROOT}/.github/scripts/test.gdb > \"${GDB_LOG}\" &\nGDB_PID=$!\n\n# The simulation must end naturally in order to produce coverage data.\nwait ${SIM_PID}\n\n# OpenOCD waits endlessly for the target (Vtb_top) to reconnect.\n# Kill OpenoCD and GDB in case they're stuck\nkill -s SIGKILL ${OPENOCD_PID} || true\nkill -s SIGKILL ${GDB_PID} || true\n\n# Display logs\nprint_logs\n\n# Parse the log, extract register values. Skip those which change as the\n# program executes since we don't know at which point we tap in.\ngrep -E '^ra |^sp |^gp |^tp |^t[01256] |^s[0-9]+ |^a[0-9]+ |^\\$[0-9]+ |^\\$ |^Hardware |^Breakpoint' \"${GDB_LOG}\" > gdb_test_dump.txt\n\ngdb_output_golden=${RV_ROOT}/.github/scripts/gdb_test_golden.txt\ngrep -q \"TEST_PASSED\" \"${SIM_LOG}\"\ntb_passed=$?\n# Compare the dumps\ndiff -E -y ${gdb_output_golden} gdb_test_dump.txt\ngdb_output_match=$?\n\nif [ \"$tb_passed\" -ne 0 ]; then\n echo \"Testbench failed. The test did not write 0xff to the mailbox to indicate success.\"\n exit 1\nfi\necho \"Testbench passed.\"\n\nif [ \"$gdb_output_match\" -ne 0 ]; then \n echo \"The output from GDB doesn't match the golden reference. See ${gdb_output_golden}\"\n exit 1\nfi\necho \"The output from GDB matches the golden reference.\"\necho \"TEST PASSED\"\n" }, { "path": ".github/scripts/gdb_test_golden.txt", "content": "ra 0x5f555555\t0x5f555555\nsp 0x0\t0x0\ngp 0x4\t0x4\ntp 0x0\t0x0\nt0 0x0\t0\nt1 0x0\t0\nt2 0x0\t0\ns1 0x0\t0\na0 0x0\t0\na1 0x0\t0\na2 0x0\t0\na3 0x0\t0\na4 0x0\t0\na5 0x0\t0\na6 0x0\t0\na7 0x0\t0\ns2 0x0\t0\ns3 0x0\t0\ns4 0x0\t0\ns5 0x0\t0\ns6 0x0\t0\ns7 0x0\t0\ns8 0x0\t0\ns9 0x0\t0\ns10 0x0\t0\ns11 0x0\t0\nt5 0x0\t0\nt6 0x0\t0\n$1 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$2 = 0x55555555\n$3 = 0xaaaaaaaa\n$4 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$5 = 0x55555555\n$6 = 0xaaaaaaaa\n$7 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$8 = 0x55555555\n$9 = 0xaaaaaaaa\n$10 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$11 = 0x55555555\n$12 = 0xaaaaaaaa\n$13 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$14 = 0x55555555\n$15 = 0xaaaaaaaa\n$16 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$17 = 0x55555555\n$18 = 0xaaaaaaaa\n$19 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$20 = 0x55555555\n$21 = 0xaaaaaaaa\n$22 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$23 = 0x55555555\n$24 = 0xaaaaaaaa\n$25 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$26 = 0x55555555\n$27 = 0xaaaaaaaa\n$28 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$29 = 0x55555555\n$30 = 0xaaaaaaaa\n$31 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$32 = 0x55555555\n$33 = 0xaaaaaaaa\n$34 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}\n$35 = 0x55555555\n$36 = 0xaaaaaaaa\nHardware assisted breakpoint 1 at 0x1c\nBreakpoint 1, 0x0000001c in ?? ()\n" }, { "path": ".github/scripts/get_code_hash.sh", "content": "#!/bin/bash\n# This script is responsible for computing hash for RISCV-DV generated programs\n# cache.\n\nHASHES=()\nHASHES+=($(git submodule status third_party/riscv-dv | cut -d\\ -f2))\nHASHES+=($(sha256sum tools/riscv-dv/code_fixup.py | cut -d\\ -f1))\nHASHES+=($(sha256sum tools/riscv-dv/testlist.yaml | cut -d\\ -f1))\nHASHES+=($(sha256sum tools/riscv-dv/riscv_core_setting.sv | cut -d\\ -f1))\nHASHES+=($(sha256sum tools/riscv-dv/Makefile | cut -d\\ -f1))\nHASHES+=($(sha256sum tools/riscv-dv/user_extension.svh | cut -d\\ -f1))\nHASHES+=($(sha256sum tools/riscv-dv/veer_directed_instr_lib.sv | cut -d\\ -f1))\n\necho ${HASHES[@]} | sha256sum | cut -d\\ -f1\n" }, { "path": ".github/scripts/indexgen/.gitignore", "content": "build\nsource\n" }, { "path": ".github/scripts/indexgen/Makefile", "content": "SPHINXOPTS ?=\nSPHINXBUILD ?= sphinx-build\nSOURCEDIR = source.template\nGENDIR = source\nBUILDDIR ?= build\nROOTDIR ?= work\n\nall: clean html\n\n# Sources\nSOURCES = $(wildcard $(SOURCEDIR)/*.md)\n\n# Generate sources\n$(GENDIR):\n\t@mkdir -p $@\n\n$(GENDIR)/index.md: $(SOURCES) generate.py | $(GENDIR)\n\t@rm -rf $(GENDIR)/*\n\t@python3 generate.py --template \"$(SOURCEDIR)\" --root \"$(ROOTDIR)/html\" --output \"$(GENDIR)\"\n\n# Build the final webpage. Pass the 'html' target to sphinx, copy report pages\nhtml: Makefile $(GENDIR)/index.md\n\t@$(SPHINXBUILD) -M $@ \"$(GENDIR)\" \"$(BUILDDIR)\" $(SPHINXOPTS) $(O)\n\t@rsync -avrm --include=\"*/\" --include=\"coverage_dashboard/***\" --include=\"verification_dashboard/***\" --include=\"docs_rendered/***\" --exclude=\"*\" \"$(ROOTDIR)/\" \"$(BUILDDIR)/\"\n\t@bash update_styles.sh \"$(BUILDDIR)\"\n\nclean:\n\t@rm -rf $(BUILDDIR)\n\t@rm -rf $(GENDIR)\n\n.PHONY: all clean html\n" }, { "path": ".github/scripts/indexgen/dashboard-styles/gcov.css", "content": "/* All views: initial background and text color */\n@import url('https://fonts.googleapis.com/css2?family=Roboto:wght@400;700&display=swap');\n\nbody\n{\n color: #E9EBFA;\n background-color: #0E1116;\n padding: 0;\n margin: 0;\n font-family: 'Roboto', sans-serif;\n box-sizing: border-box;\n}\n\n/* * {\n\n} */\n\n/* All views: standard link format*/\na:link\n{\n color: #00D0C9;\n text-decoration: underline;\n font-family: 'Roboto', sans-serif;\n}\n\n/* All views: standard link - visited format */\na:visited\n{\n color: #E9EBFA;\n text-decoration: underline;\n}\n\n/* All views: standard link - activated format */\na:active\n{\n color: #00D0C9;\n color: #E9EBFA;\n text-decoration: underline;\n}\n\nth {\n border: 1px solid;\n}\n\ntd {\n color: #E9EBFA;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3)\n{\nheight: 300px;\n}\n\nbody > center > table td:not(.coverBarOutline){\n border: 1px solid #31363C;\n}\n\nbody > center > table > tbody > tr:nth-child(1) {\n display: none;\n}\n\nbody>table:nth-child(1)>tbody>tr:nth-child(3) {\n display: flex;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td {\nalign-self: center;\npadding: 0 95px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(1) > td.headerValue {\n font-size: 35px;\n}\n\nbody>table:nth-child(1)>tbody>tr:nth-child(3)>td>table>tbody>tr:nth-child(1)>td.headerItem {\n font-weight: 300;\n font-size: 35px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(1) > td.headerValue {\n font-size: 35px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(2) > td.headerItem {\n font-size: 22px;\n font-weight: 300;\n}\n\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(2) > td.headerValue {\n font-size: 22px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(3) > td.headerItem {\n font-size: 22px;\n font-weight: 300;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(3) > td.headerValue {\n font-size: 22px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(1) {\n position: relative;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(1) > td::before {\n content: url(../../../_static/white.svg);\n position: absolute;\n left: 95px;\n transform: translateY(-15%);\n}\n\ntable {\n border-collapse: collapse;\n width: 100%;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody {\n padding: 0 50px;\n}\n\nbody > center > table > tbody tr {\n width: 19px;\n}\n\n/* All views: main title format */\ntd.title\n{\n background-color: #25292E;\n color: #DFE1F1;\n text-align: center;\n padding-bottom: 10px;\n font-size: 20px;\n font-weight: bold;\n padding: 20px 0;\n}\n\n/* All views: header item format */\ntd.headerItem\n{\n text-align: right;\n padding-right: 6px;\n\n font-weight: bold;\n white-space: nowrap;\n}\n\n/* All views: header item value format */\ntd.headerValue\n{\n text-align: left;\n color: #00D0C9;\n\n font-weight: bold;\n white-space: nowrap;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(1) > td:nth-child(5)::after {\n content: ' ';\n width: 10px;\n}\n\n/* All views: header item coverage table heading */\ntd.headerCovTableHead\n{\n color: #DFE1F1;\n text-align: center;\n padding-right: 6px;\n padding-left: 6px;\n padding-bottom: 0px;\n font-size: 14px;\n white-space: nowrap;\n}\n\n/* All views: header item coverage table entry */\ntd.headerCovTableEntry\n{\n text-align: right;\n color: #DFE1F1;\n text-align: center;\n background-color: #31363C;\n font-weight: bold;\n white-space: nowrap;\n padding-left: 12px;\n padding-right: 4px;\n}\n\n/* All views: header item coverage table entry for high coverage rate */\ntd.headerCovTableEntryHi\n{\n text-align: right;\n color: #000000;\n\n font-weight: bold;\n white-space: nowrap;\n padding-left: 12px;\n padding-right: 4px;\n background-color: #2FC36E;\n}\n\n/* All views: header item coverage table entry for medium coverage rate */\ntd.headerCovTableEntryMed\n{\n text-align: right;\n color: #000000;\n\n font-weight: bold;\n white-space: nowrap;\n padding-left: 12px;\n padding-right: 4px;\n background-color: #EFAC0A;\n}\n\n/* All views: header item coverage table entry for ow coverage rate */\ntd.headerCovTableEntryLo\n{\n text-align: right;\n color: #DFE1F1;\n text-align: center;\n font-weight: bold;\n white-space: nowrap;\n padding-left: 12px;\n padding-right: 4px;\n background-color: #F21E08;\n}\n\n/* All views: header legend value for legend entry */\ntd.headerValueLeg\n{\n text-align: left;\n color: #000000;\n\n font-size: 80%;\n white-space: nowrap;\n padding-top: 4px;\n}\n\nbody>table:nth-child(1)>tbody>tr:nth-child(2)>td {\n display: none;\n}\n\n/* All views: color of horizontal ruler */\ntd.ruler > img\n{\n height: 1px ;\n width: 100% ;\n background-color: rgba(255, 255, 255, 0.3);\n aspect-ratio: 1 / 1;\n}\n\n/* All views: version string format */\ntd.versionInfo\n{\n text-align: center;\n padding-top: 35px;\n font-style: italic;\n}\n\ntd.versionInfo > a\n{\n color: #00D0C9;\n}\n\n/* Directory view/File view (all)/Test case descriptions:\n table headline format */\ntd.tableHead\n{\n text-align: center;\n color: #ffffff;\n background-color: #0E1116;\n\n font-size: 16px;\n font-weight: bold;\n white-space: nowrap;\n padding-left: 4px;\n padding-right: 4px;\n}\n\nspan.tableHeadSort\n{\n padding-right: 4px;\n}\n\ntd\n{\n align-items: center;\n}\n\ncenter {\n padding: 95px;\n}\n\n/* Directory view/File view (all): filename entry format */\ntd.coverFile\n{\n text-align: left;\n padding-left: 10px;\n padding-right: 20px;\n color: #E9EBFA;\n background-color: #0E1116;\n font-family: monospace;\n}\n\n/* Directory view/File view (all): bar-graph entry format*/\ntd.coverBar\n{\n background-color: #0E1116;\n}\n\n/* Directory view/File view (all): bar-graph outline color */\ntd.coverBarOutline\n{\n background-color: #0E1116;\n display: flex;\n justify-content: center;\n}\n\n/* Directory view/File view (all): percentage entry for files with\n high coverage rate */\ntd.coverPerHi\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #0E1116;\n color: #2FC36E;\n font-weight: bold;\n\n}\n\n/* Directory view/File view (all): line count entry for files with\n high coverage rate */\ntd.coverNumHi\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #0E1116;\n white-space: nowrap;\n\n}\n\n/* Directory view/File view (all): percentage entry for files with\n medium coverage rate */\ntd.coverPerMed\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n color: #EFAC0A;\n background-color: #0E1116;\n font-weight: bold;\n\n}\n\n/* Directory view/File view (all): line count entry for files with\n medium coverage rate */\ntd.coverNumMed\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #0E1116;\n white-space: nowrap;\n\n}\n\n/* Directory view/File view (all): percentage entry for files with\n low coverage rate */\ntd.coverPerLo\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n color: #F21E08;\n background-color: #0E1116;\n font-weight: bold;\n\n}\n\n/* Directory view/File view (all): line count entry for files with\n low coverage rate */\ntd.coverNumLo\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #0E1116;\n white-space: nowrap;\n\n}\n\n/* File view (all): \"show/hide details\" link format */\na.detail:link\n{\n color: #B8D0FF;\n font-size:80%;\n}\n\n/* File view (all): \"show/hide details\" link - visited format */\na.detail:visited\n{\n color: #B8D0FF;\n font-size:80%;\n}\n\n/* File view (all): \"show/hide details\" link - activated format */\na.detail:active\n{\n color: #ffffff;\n font-size:80%;\n}\n\n/* File view (detail): test name entry */\ntd.testName\n{\n text-align: right;\n padding-right: 10px;\n background-color: #dae7fe;\n\n}\n\n/* File view (detail): test percentage entry */\ntd.testPer\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #dae7fe;\n\n}\n\n/* File view (detail): test lines count entry */\ntd.testNum\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #dae7fe;\n\n}\n\n/* Test case descriptions: test name format*/\ndt\n{\n\n font-weight: bold;\n}\n\n/* Test case descriptions: description table body */\ntd.testDescription\n{\n padding-top: 10px;\n padding-left: 30px;\n padding-bottom: 10px;\n padding-right: 30px;\n background-color: #dae7fe;\n}\n\n/* Source code view: function entry */\ntd.coverFn\n{\n text-align: left;\n padding-left: 10px;\n padding-right: 20px;\n color: #284fa8;\n background-color: #dae7fe;\n font-family: monospace;\n}\n\n/* Source code view: function entry zero count*/\ntd.coverFnLo\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #ff0000;\n font-weight: bold;\n\n}\n\n/* Source code view: function entry nonzero count*/\ntd.coverFnHi\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #dae7fe;\n font-weight: bold;\n\n}\n\n/* Source code view: source code format */\npre.source\n{\n font-family: monospace;\n white-space: pre;\n margin-top: 2px;\n}\n\n/* Source code view: line number format */\nspan.lineNum\n{\n background-color: #efe383;\n}\n\n/* Source code view: format for lines which were executed */\ntd.lineCov,\nspan.lineCov\n{\n background-color: #cad7fe;\n}\n\n/* Source code view: format for Cov legend */\nspan.coverLegendCov\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-bottom: 2px;\n background-color: #cad7fe;\n}\n\n/* Source code view: format for lines which were not executed */\ntd.lineNoCov,\nspan.lineNoCov\n{\n background-color: #ff6230;\n}\n\n/* Source code view: format for NoCov legend */\nspan.coverLegendNoCov\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-bottom: 2px;\n background-color: #ff6230;\n}\n\n/* Source code view (function table): standard link - visited format */\ntd.lineNoCov > a:visited,\ntd.lineCov > a:visited\n{\n color: #000000;\n text-decoration: underline;\n}\n\n/* Source code view: format for lines which were executed only in a\n previous version */\nspan.lineDiffCov\n{\n background-color: #b5f7af;\n}\n\n/* Source code view: format for branches which were executed\n * and taken */\nspan.branchCov\n{\n background-color: #cad7fe;\n}\n\n/* Source code view: format for branches which were executed\n * but not taken */\nspan.branchNoCov\n{\n background-color: #ff6230;\n}\n\n/* Source code view: format for branches which were not executed */\nspan.branchNoExec\n{\n background-color: #ff6230;\n}\n\n/* Source code view: format for the source code heading line */\npre.sourceHeading\n{\n white-space: pre;\n font-family: monospace;\n font-weight: bold;\n margin: 0px;\n}\n\n/* All views: header legend value for low rate */\ntd.headerValueLegL\n{\n\n text-align: center;\n white-space: nowrap;\n padding-left: 4px;\n padding-right: 2px;\n background-color: #ff0000;\n font-size: 80%;\n}\n\n/* All views: header legend value for med rate */\ntd.headerValueLegM\n{\n\n text-align: center;\n white-space: nowrap;\n padding-left: 2px;\n padding-right: 2px;\n background-color: #ffea20;\n font-size: 80%;\n}\n\n/* All views: header legend value for hi rate */\ntd.headerValueLegH\n{\n\n text-align: center;\n white-space: nowrap;\n padding-left: 2px;\n padding-right: 4px;\n background-color: #a7fc9d;\n font-size: 80%;\n}\n\n/* All views except source code view: legend format for low coverage */\nspan.coverLegendCovLo\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-top: 2px;\n background-color: #ff0000;\n}\n\n/* All views except source code view: legend format for med coverage */\nspan.coverLegendCovMed\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-top: 2px;\n background-color: #ffea20;\n}\n\n/* All views except source code view: legend format for hi coverage */\nspan.coverLegendCovHi\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-top: 2px;\n background-color: #a7fc9d;\n}" }, { "path": ".github/scripts/indexgen/dashboard-styles/main.css", "content": "[data-md-color-scheme=\"slate\"] {\n --md-hue: 218;\n --md-default-bg-color: hsla(var(--md-hue), 22%, 7%, 1);\n}\n\n[data-md-color-primary=\"teal\"] {\n --md-primary-fg-color: #25292e;\n}\n\n[data-md-color-scheme=\"slate\"][data-md-color-primary=\"teal\"] {\n --md-typeset-a-color: #00d0c9;\n}\n\n.md-social {\n display: none;\n}\n\n.md-header__option {\n display: none;\n}" }, { "path": ".github/scripts/indexgen/generate.py", "content": "#!/usr/bin/env python3\nimport argparse\nimport os\nimport shutil\nimport logging\nimport jinja2\n\n# ==============================================================================\n\n\ndef render_template(src, dst, **kwargs):\n \"\"\"\n Renders a jinja2 template file to another file\n \"\"\"\n with open(src, \"r\") as fp:\n tpl = jinja2.Template(fp.read())\n with open(dst, \"w\") as fp:\n fp.write(tpl.render(**kwargs))\n\n# ==============================================================================\n\n\ndef make_coverage_report_index(branch, root, output, templates):\n \"\"\"\n Prepares coverage report index page\n \"\"\"\n logging.debug(\"=== make_coverage_report_index\")\n logging.debug(f\"branch = {branch}\")\n logging.debug(f\"root = {root}\")\n logging.debug(f\"output = {output}\")\n logging.debug(f\"templates = {templates}\")\n logging.debug(\"===\")\n keys = [\"all\", \"branch\", \"toggle\", \"functional\"]\n path = os.path.join(root, \"coverage_dashboard\")\n\n # Collect summary reports\n summary = {k: None for k in keys}\n for key in keys:\n file = key\n fname = os.path.join(path, file)\n if os.path.isdir(fname):\n summary[key] = file\n\n # Collect individual test reports\n individual = {k: dict() for k in keys}\n for key in keys:\n pfx = key + \"_\"\n\n if not os.path.isdir(path):\n continue\n\n for file in sorted(os.listdir(path)):\n fname = os.path.join(path, file)\n if not os.path.isdir(fname):\n continue\n if not file.startswith(pfx):\n continue\n\n # Extract test name\n test_name = file[len(pfx):]\n\n # Append the report\n individual[key][test_name] = file\n\n # Render the template\n params = {\n \"ref\": branch + \"_coverage_dashboard\",\n \"summary\": summary,\n \"individual\": individual,\n }\n\n os.makedirs(output, exist_ok=True)\n render_template(\n os.path.join(templates, \"coverage_dashboard.md\"),\n os.path.join(output, \"coverage_dashboard.md\"),\n **params\n )\n\n\ndef make_verification_report_index(branch, root, output, templates):\n \"\"\"\n Prepares verification tests report index page\n \"\"\"\n logging.debug(\"=== make_verification_report_index\")\n logging.debug(f\"branch = {branch}\")\n logging.debug(f\"root = {root}\")\n logging.debug(f\"output = {output}\")\n logging.debug(f\"templates = {templates}\")\n logging.debug(\"===\")\n path = os.path.join(root, \"verification_dashboard\")\n\n # Collect tests\n tests = set()\n\n if os.path.isdir(path):\n for file in sorted(os.listdir(path)):\n if not file.startswith(\"webpage_\"):\n continue\n\n test_name = file.replace(\"webpage_\", \"\")\n tests.add(test_name)\n\n # Render the template\n params = {\n \"ref\": branch + \"_verification_dashboard\",\n \"tests\": tests,\n }\n\n os.makedirs(output, exist_ok=True)\n render_template(\n os.path.join(templates, \"verification_dashboard.md\"),\n os.path.join(output, \"verification_dashboard.md\"),\n **params\n )\n\n\ndef make_dev_index(branches, output, templates):\n \"\"\"\n Prepares the branch/pr index page\n \"\"\"\n logging.debug(\"=== make_dev_index\")\n logging.debug(f\"branches = {branches}\")\n logging.debug(f\"output = {output}\")\n logging.debug(f\"templates = {templates}\")\n logging.debug(\"===\")\n params = {\n \"branches\": branches,\n }\n\n render_template(\n os.path.join(templates, \"dev.md\"),\n os.path.join(output, \"dev.md\"),\n **params\n )\n\n# ==============================================================================\n\n\ndef main():\n logging.basicConfig(encoding=\"utf-8\", level=logging.DEBUG)\n\n # Parse args\n parser = argparse.ArgumentParser()\n parser.add_argument(\n \"--template\",\n type=str,\n required=True,\n help=\"Templates path\",\n )\n parser.add_argument(\n \"--root\",\n type=str,\n default=None,\n help=\"Existing webpage root path\",\n )\n parser.add_argument(\n \"--output\",\n type=str,\n required=True,\n help=\"Output path\",\n )\n\n args = parser.parse_args()\n\n # Check\n if os.path.abspath(args.root) == os.path.abspath(args.output):\n print(\"Error: Existing webpage root and output paths mustn't be the same\")\n exit(-1)\n\n # Reports for the main branch\n make_coverage_report_index(\n \"main\",\n os.path.join(args.root, \"main\"),\n os.path.join(args.output, \"main\"),\n args.template\n )\n\n make_verification_report_index(\n \"main\",\n os.path.join(args.root, \"main\"),\n os.path.join(args.output, \"main\"),\n args.template\n )\n\n # Reports for development branches / pull requests\n branches = []\n\n path = os.path.join(args.root, \"dev\")\n\n if os.path.isdir(path):\n for file in os.listdir(path):\n if not os.path.isdir(os.path.join(path, file)):\n continue\n branches.append(file)\n\n make_coverage_report_index(\n file,\n os.path.join(args.root, \"dev\", file),\n os.path.join(args.output, \"dev\", file),\n args.template\n )\n\n make_verification_report_index(\n file,\n os.path.join(args.root, \"dev\", file),\n os.path.join(args.output, \"dev\", file),\n args.template\n )\n\n # Prepare the branch/pr index page\n make_dev_index(branches, args.output, args.template)\n\n # Copy other files/pages\n files = [\n \"conf.py\",\n \"main.md\",\n \"index.md\",\n ]\n for file in files:\n shutil.copy(\n os.path.join(args.template, file),\n os.path.join(args.output, file),\n )\n\n\nif __name__ == \"__main__\":\n main()\n" }, { "path": ".github/scripts/indexgen/index_redirect/index.html", "content": "\n\n \n \n \n \n \n\n" }, { "path": ".github/scripts/indexgen/requirements.txt", "content": "myst-parser\nsphinx\nsphinx_tabs\nsphinxcontrib-mermaid\n\nhttps://github.com/antmicro/sphinx-immaterial/releases/download/tip/sphinx_immaterial-0.0.post1.tip-py3-none-any.whl\nhttps://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip\n\njinja2\n" }, { "path": ".github/scripts/indexgen/source.template/conf.py", "content": "# -*- coding: utf-8 -*-\n#\n# This file is execfile()d with the current directory set to its containing dir.\n#\n# Note that not all possible configuration values are present in this file.\n#\n# All configuration values have a default; values that are commented out\n# serve to show the default.\n#\n# Updated documentation of the configuration options is available at\n# https://www.sphinx-doc.org/en/master/usage/configuration.html\n\nfrom datetime import datetime\n\nfrom antmicro_sphinx_utils.defaults import (\n numfig_format,\n extensions as default_extensions,\n myst_enable_extensions as default_myst_enable_extensions,\n antmicro_html,\n)\n\n# If extensions (or modules to document with autodoc) are in another directory,\n# add these directories to sys.path here. If the directory is relative to the\n# documentation root, use os.path.abspath to make it absolute, like shown here.\n#sys.path.insert(0, os.path.abspath('.'))\n\n# -- General configuration -----------------------------------------------------\n\n# General information about the project.\nproject = u'RISC-V VeeR-EL2 Core'\nbasic_filename = u'veer-test-reports'\nauthors = u'CHIPS Alliance'\ncopyright = f'{authors}, {datetime.now().year}'\n\n# The short X.Y version.\nversion = ''\n# The full version, including alpha/beta/rc tags.\nrelease = ''\n\n# This is temporary before the clash between myst-parser and immaterial is fixed\nsphinx_immaterial_override_builtin_admonitions = False\n\nnumfig = True\n\n# If you need to add extensions just add to those lists\nextensions = default_extensions\nmyst_enable_extensions = default_myst_enable_extensions\n\nmyst_substitutions = {\n \"project\": project\n}\n\nmyst_url_schemes = {\n \"http\": None,\n \"https\": None,\n \"external\": \"{{path}}\",\n}\n\ntoday_fmt = '%Y-%m-%d'\n\ntodo_include_todos=False\n\n# -- Options for HTML output ---------------------------------------------------\n\nhtml_theme = 'sphinx_immaterial'\n\nhtml_last_updated_fmt = today_fmt\n\nhtml_show_sphinx = False\n\n(\n html_logo,\n html_theme_options,\n html_context\n) = antmicro_html()\n\n\nhtml_theme_options[\"palette\"][0].update({\n \"scheme\": \"slate\",\n \"primary\": \"teal\",\n \"accent\": \"white\",\n})\n\n# # Disable toggle theme button\n# html_theme_options = {\n# \"palette\": []\n# }\n\nhtml_title = project\n\ndef setup(app):\n app.add_css_file('main.css')\n" }, { "path": ".github/scripts/indexgen/source.template/coverage_dashboard.md", "content": "({{ ref }})=\n# Coverage dashboard\n\n## Summary reports (all tests)\n\n{%- for coverage in summary %}\n{%- if summary[coverage] %}\n * [{{ coverage }} coverage](external:coverage_dashboard/{{ summary[coverage] }}/index.html)\n{%- else %}\n * {{ coverage }} coverage (no data)\n{%- endif %}\n{%- endfor %}\n\n## Individual test reports\n\n{%- for coverage in individual %}\n### {{ coverage }} coverage\n{%- if individual[coverage] %}\n{%- for test in individual[coverage] %}\n * [{{ test }}](external:coverage_dashboard/{{ individual[coverage][test] }}/index.html)\n{%- endfor %}\n{%- else %}\nno data\n{%- endif %}\n{%- endfor %}\n" }, { "path": ".github/scripts/indexgen/source.template/dev.md", "content": "# Active pull requests\n\n{%- for branch in branches %}\n * {{ branch }}\n * [Coverage]({{ branch }}_coverage_dashboard)\n * [Verification tests]({{ branch }}_verification_dashboard)\n * [Documentation](external:dev/{{ branch }}/docs_rendered/html/index.html)\n{%- endfor %}\n" }, { "path": ".github/scripts/indexgen/source.template/index.md", "content": "# {{ project }}\n\n```{toctree}\n:maxdepth: 2\n\nmain\ndev\n```\n" }, { "path": ".github/scripts/indexgen/source.template/main.md", "content": "# Main branch\n\n * [Coverage](main_coverage_dashboard)\n * [Verification tests](main_verification_dashboard)\n * [Documentation](external:main/docs_rendered/html/index.html)\n" }, { "path": ".github/scripts/indexgen/source.template/verification_dashboard.md", "content": "({{ ref }})=\n# Verification tests dashboard\n\n## Test reports\n\n{%- for test in tests %}\n * [{{ test }}](external:verification_dashboard/webpage_{{ test }}/{{ test }}.html)\n{%- endfor %}\n * [RISCOF tests report](external:verification_dashboard/riscof/report.html)\n" }, { "path": ".github/scripts/indexgen/update_styles.sh", "content": "#!/bin/bash\n\nSELF_DIR=\"$(dirname $(readlink -f ${BASH_SOURCE[0]}))\"\n. ${SELF_DIR}/../common.inc.sh\n\nupdate_styles(){\n # Update styles for sphinx theme and LCOV reports\n # Args:\n # BUILDDIR - path to where the webpage is made\n BUILD_DIR=$1\n echo -e \"${COLOR_WHITE}========== Update styles =========${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} BUILD_DIR = ${BUILD_DIR}${COLOR_CLEAR}\"\n\n # Replace styles for sphinx build\n cp dashboard-styles/main.css ${BUILD_DIR}/html/_static/\n\n # Add CHIPs logo\n cp dashboard-styles/assets/chips-alliance-logo-mono.svg ${BUILD_DIR}/html/_static/white.svg\n\n # Replace undesired CSS and progress bar sprites with desired style for LCOV reports\n copy_files(){\n check_args_count $# 2\n SOURCE=$1\n SEARCH=$2\n FILES=`find ${BUILD_DIR}/ -name ${SEARCH}`\n\n for FILE in ${FILES}; do\n echo \"Copy ${SOURCE} to ${FILE}\"\n cp $SOURCE $FILE\n done\n }\n\n CHIPS_GCOV_CSS=dashboard-styles/gcov.css\n AMBER=dashboard-styles/assets/amber.png\n RUBY=dashboard-styles/assets/ruby.png\n SNOW=dashboard-styles/assets/snow.png\n EMERALD=dashboard-styles/assets/emerald.png\n\n for ASSET in $CHIPS_GCOV_CSS $AMBER $RUBY $SNOW $EMERALD; do\n echo -e \"${COLOR_WHITE}========== $ASSET =========${COLOR_CLEAR}\"\n copy_files $ASSET $(basename \"$ASSET\")\n done\n echo -e \"${COLOR_WHITE}Update styles ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE}==========================${COLOR_CLEAR}\"\n}\n\n# Example usage\n# BUILD_DIR=./build\n# update_styles.sh $BUILD_DIR\n\ncheck_args_count $# 1\nupdate_styles \"$@\"" }, { "path": ".github/scripts/info_process_setup.sh", "content": "#!/bin/bash\n\nset -ex\n\napt update\napt install -y git pipx\n\n# By default pipx uses `/root/.local/bin` which isn't in PATH.\nexport PIPX_BIN_DIR=/usr/local/bin\npipx install git+https://github.com/antmicro/info-process@1d1fa64f\n" }, { "path": ".github/scripts/mapfile", "content": "map el2_exu_alu_ctl el2_exu_alu_ctl_wrapper.alu tb_top.rvtop_wrapper.rvtop.veer.exu.i_alu\nmap el2_exu_mul_ctl el2_exu_mul_ctl_wrapper.mul tb_top.rvtop_wrapper.rvtop.veer.exu.i_mul\nmap el2_exu_div_ctl el2_exu_div_ctl_wrapper.div tb_top.rvtop_wrapper.rvtop.veer.exu.i_div\n\nmap dmi_jtag_to_core_sync dmi_test_wrapper.wrapper.i_dmi_jtag_to_core_sync tb_top.rvtop_wrapper.rvtop.dmi_wrapper.i_dmi_jtag_to_core_sync\n\nmap rvjtag_tap dmi_test_wrapper.wrapper.i_jtag_tap tb_top.rvtop_wrapper.rvtop.dmi_wrapper.i_jtag_tap\n\nmap el2_ifu_iccm_mem el2_ifu_iccm_mem_wrapper.mem tb_top.rvtop_wrapper.rvtop.mem.iccm.iccm\nmap el2_lsu_dccm_mem el2_lsu_dccm_mem_wrapper.mem tb_top.rvtop_wrapper.rvtop.mem.Gen_dccm_enable.dccm\nmap el2_ifu_compress_ctl el2_ifu_compress_ctl tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0\n\nmap el2_pic_ctrl el2_pic_ctrl tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst\nmap el2_pmp el2_pmp_wrapper.pmp tb_top.rvtop_wrapper.rvtop.veer.pmp\nmap el2_dec_ib_ctl el2_dec_ib_ctl_wrapper.tu tb_top.rvtop_wrapper.rvtop.veer.dec.instbuff\nmap el2_dec_trigger el2_dec_trigger_wrapper.tu tb_top.rvtop_wrapper.rvtop.veer.dec.dec_trigger\nmap el2_dma_ctrl el2_dma_ctrl tb_top.rvtop_wrapper.rvtop.veer.dma_ctrl\n\nmap dmi_mux dmi_test_wrapper.mux tb_top.rvtop_wrapper.rvtop.dmi_mux\nmap dmi_wrapper dmi_test_wrapper.wrapper tb_top.rvtop_wrapper.rvtop.dmi_wrapper\n\nmap el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[0].GW[1].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[0].GW[1].gw_inst'\nmap el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[0].GW[2].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[0].GW[2].gw_inst'\nmap el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[0].GW[3].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[0].GW[3].gw_inst'\nmap el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[1].GW[0].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[1].GW[0].gw_inst'\nmap el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[1].GW[1].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[1].GW[1].gw_inst'\nmap el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[1].GW[2].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[1].GW[2].gw_inst'\nmap el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[1].GW[3].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[1].GW[3].gw_inst'\n\nmap el2_cmp_and_mux 'el2_pic_ctrl.genblock.LEVEL[0].COMPARE[0].cmp_l1' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.genblock.LEVEL[0].COMPARE[0].cmp_l1'\nmap el2_cmp_and_mux 'el2_pic_ctrl.genblock.LEVEL[0].COMPARE[1].cmp_l1' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.genblock.LEVEL[0].COMPARE[1].cmp_l1'\n\n" }, { "path": ".github/scripts/openocd/board/caliptra-verilator-rst.cfg", "content": "source [find sim-jtagdpi.cfg]\nsource [find veer-el2-rst.cfg]\n\n# Increase timeouts in simulation\nriscv set_command_timeout_sec 300\n" }, { "path": ".github/scripts/openocd/board/caliptra-verilator.cfg", "content": "source [find sim-jtagdpi.cfg]\nsource [find veer-el2.cfg]\n\n# Increase timeouts in simulation\nriscv set_command_timeout_sec 300\n" }, { "path": ".github/scripts/openocd/sim-jtagdpi.cfg", "content": "# Copyright lowRISC contributors.\n# Licensed under the Apache License, Version 2.0, see LICENSE for details.\n# SPDX-License-Identifier: Apache-2.0\n\n# \"JTAG adapter\" for simulation, exposed to OpenOCD through a TCP socket\n# speaking the remote_bitbang protocol. The adapter is implemented as\n# SystemVerilog DPI module.\n\nadapter driver remote_bitbang\nremote_bitbang port 5000\nremote_bitbang host localhost\n" }, { "path": ".github/scripts/openocd/veer-el2-rst.cfg", "content": "if { [info exists CHIPNAME] } {\n set _CHIPNAME $CHIPNAME\n} else {\n set _CHIPNAME riscv\n}\n\njtag newtap $_CHIPNAME tap -irlen 5\nset _TARGETNAME $_CHIPNAME.tap\ntarget create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread\n\n# Configure work area in on-chip SRAM\n$_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0\n\n# Mem access mode\nriscv set_mem_access sysbus\n\n# The following commands disable target examination and set explicitly the\n# core parameters read from CSRs. These required a modified version of\n# OpenOCD from https://github.com/antmicro/openocd/tree/riscv-nohalt\nriscv set_nohalt on\nriscv set_xlen 32\nriscv set_misa 0x40001104\n\n# Be verbose about GDB errors\ngdb_report_data_abort enable\ngdb_report_register_access_error enable\n\n# Always use hardware breakpoints.\ngdb_breakpoint_override hard\n" }, { "path": ".github/scripts/openocd/veer-el2.cfg", "content": "if { [info exists CHIPNAME] } {\n set _CHIPNAME $CHIPNAME\n} else {\n set _CHIPNAME riscv\n}\n\njtag newtap $_CHIPNAME tap -irlen 5\nset _TARGETNAME $_CHIPNAME.tap\ntarget create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread\n\n# Configure work area in on-chip SRAM\n$_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0\n\n$_TARGETNAME.0 configure -event gdb-detach {\n resume\n}\n\n$_TARGETNAME.0 riscv expose_csrs 1968=dcsr\n$_TARGETNAME.0 riscv expose_csrs 1969=dpc\n$_TARGETNAME.0 riscv expose_csrs 1988=dmst\n$_TARGETNAME.0 riscv expose_csrs 1992=dicawics\n$_TARGETNAME.0 riscv expose_csrs 1996=dicad0h\n$_TARGETNAME.0 riscv expose_csrs 1993=dicad0\n$_TARGETNAME.0 riscv expose_csrs 1994=dicad1\n$_TARGETNAME.0 riscv expose_csrs 1995=dicago\n\nproc write_icache_line {dicawics_ dicad0_ dicad0h_ dicad1_} {\n # 1. Write dicawics\n reg csr_dicawics $dicawics_\n # 2. Write instruction data to dicad0 and dicad0h, and parity to dicad1\n reg csr_dicad0 $dicad0_\n reg csr_dicad0h $dicad0h_\n reg csr_dicad1 $dicad1_\n # 3. Write 1 to dicago to trigger Icache write operation\n reg csr_dicago 1\n}\n\nproc read_icache_line {dicawics_} {\n # 1. Write dicawics\n reg csr_dicawics $dicawics_\n # 2. Read to dicago to trigger Icache read operation\n reg csr_dicago\n # 3. get line chunk from dicad0 and dicad0h, and parity from dicad1\n reg csr_dicad0\n reg csr_dicad0h\n reg csr_dicad1\n}\n\nproc write_icache_tag {dicawics_ dicad0_ dicad1_} {\n # 1. Write dicawics\n reg csr_dicawics $dicawics_\n # 2. Write tag, valid, LRU information to dicad0, and parity to dicad1\n reg csr_dicad0 $dicad0_\n reg csr_dicad1 $dicad1_\n # 3. Write 1 to dicago to trigger Icache write operation\n reg csr_dicago 1\n}\n\nproc read_icache_tag {dicawics_} {\n # 1. Write dicawics\n reg csr_dicawics $dicawics_\n # 2. Read to dicago to trigger Icache read operation\n reg csr_dicago\n # 3. get tag from dicad0, and parity from dicad1\n reg csr_dicad0\n reg csr_dicad1\n}\n\n$_TARGETNAME.0 configure -event halted {\n echo \"Starting ICache line read\"\n # dicawics: array=0 way=1 index=1\n set dicawics_value [expr {(0 << 24) | (1 << 20) | (1 << 5)}]\n read_icache_line $dicawics_value\n\n echo \"Starting ICache line write\"\n # Write instruction data to dicad0 and dicad0h\n set dicad0_value 0x30c00\n set dicad0h_value 0xc00c0\n # Write wrong parity to trigger error\n set dicad1_value 0xffffaaaa\n # iterate to perform write for many values of index\n for {set index 0} {$index < 5} {incr index} {\n # dicawics: array=0 way=1\n set dicawics_value [expr {(0 << 24) | (1 << 20) | ($index << 5)}]\n write_icache_line $dicawics_value $dicad0_value $dicad0h_value $dicad1_value\n }\n\n echo \"Starting ICache tag and status read\"\n read_icache_tag $dicawics_value\n\n echo \"Starting ICache tag and status write\"\n # Write tag, valid, LRU information are in dicad0, parity is in dicad1\n set dicad0_value 0xfcb\n set dicad1_value 0xffffffff\n for {set index 0} {$index < 5} {incr index} {\n # dicawics: array=1 way=1\n set dicawics_value [expr {(1 << 24) | (1 << 20) | ($index << 5)}]\n write_icache_tag $dicawics_value $dicad0_value $dicad1_value\n }\n echo \"ICache test done.\"\n}\n\n# Mem access mode\nriscv set_mem_access abstract\n\n# Be verbose about GDB errors\ngdb_report_data_abort enable\ngdb_report_register_access_error enable\n\n# Always use hardware breakpoints.\ngdb_breakpoint_override hard\n" }, { "path": ".github/scripts/openocd_test.sh", "content": "#!/bin/bash\n# SPDX-License-Identifier: Apache-2.0\n# Copyright 2024 Antmicro \n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\n# This script runs Verilator RTL simulation in background and invokes OpenOCD\n# to perform JTAG access test\n\nSIM_LOG=`realpath sim.log`\nOPENOCD_LOG=`realpath openocd.log`\n\nset +e\n\nif [ \"$#\" -lt 1 ]; then\n echo \"Usage: openocd_test.sh [openocd args ...]\"\n exit 1\nfi\nOPENOCD_ARGS=$@\n\n# Utils\nsource `dirname ${BASH_SOURCE[0]}`/utils.sh\n\nprint_logs () {\n echo -e \"${COLOR_WHITE}======== Simulation log ========${COLOR_OFF}\"\n cat ${SIM_LOG} || true\n echo -e \"${COLOR_WHITE}======== OpenOCD log ========${COLOR_OFF}\"\n cat ${OPENOCD_LOG} || true\n}\n\necho -e \"${COLOR_WHITE}======== Launching interactive simulation ========${COLOR_OFF}\"\n\n# Start the simulation\necho -e \"Starting simulation...\"\nif [ -f obj_dir/Vtb_top ]; then\n SIM_START_STRING=\"VerilatorTB: Start of sim\"\n obj_dir/Vtb_top >\"${SIM_LOG}\" 2>&1 &\nelif [ -f ./simv ]; then\n SIM_START_STRING=\" remote_bitbang_port 5000\"\n ./simv +vcs+lic+wait -cm line+cond+fsm+tgl+branch >\"${SIM_LOG}\" 2>&1 &\nelse\n echo \"No simulation binary found, exiting\"\n exit 1\nfi\nSIM_PID=$!\n\n# Wait\nwait_for_phrase \"${SIM_LOG}\" \"${SIM_START_STRING}\"\nif [ $? -ne 0 ]; then\n echo -e \"${COLOR_RED}Failed to start the simulation!${COLOR_OFF}\"\n print_logs\n terminate ${SIM_PID}; exit -1\nfi\necho -e \"Simulation running and ready (pid=${SIM_PID})\"\n\n# Wait a bit\nsleep 2s\n\n# Run the test\necho -e \"${COLOR_WHITE}======== Running OpenOCD test '$@' ========${COLOR_OFF}\"\ncd ${RV_ROOT}/testbench/openocd_scripts && openocd -d2 ${OPENOCD_ARGS} >\"${OPENOCD_LOG}\" 2>&1\nEXITCODE=$?\n\nif [ ${EXITCODE} -eq 0 ]; then\n echo -e \"${COLOR_GREEN}[PASSED]${COLOR_OFF}\"\nelse\n echo -e \"${COLOR_RED}[FAILED]${COLOR_OFF}\"\nfi\n\n# Display logs\nprint_logs\n\nwait $SIM_PID\n\n# Honor the exitcode\nexit ${EXITCODE}\n\n" }, { "path": ".github/scripts/peripheral_access.tcl", "content": "# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\ninit\n\nset script_dir [file dirname [info script]]\nsource [file join $script_dir common.tcl]\n\n# Manually read dmstatus and check if the core is actually held in external\n# reset. In the expected state bits anyunavail allrunning anyrunning allhalted \n# and anyhalted should be cleared.\nset val [riscv dmi_read $dmstatus_addr]\nputs \"dmstatus: $val\"\n\nif { ($val & 0x00000F00) != 0 } {\n echo \"The core is not held in reset!\"\n shutdown error\n}\n\necho \"Accessing ECC...\"\nset golden { 0x63707365 0x38342d33 0x3030312e 0x0 }\nset actual [ read_memory 0x10008000 32 4 phys ]\nif {[compare $actual $golden] != 0} {\n shutdown error\n}\n\necho \"Accessing HMAC...\"\nset golden { 0x6163686d 0x61327368 0x3030322e 0x0 }\nset actual [ read_memory 0x10010000 32 4 phys ]\nif {[compare $actual $golden] != 0} {\n shutdown error\n}\n\necho \"Accessing SHA512...\"\nset golden { 0x61327368 0x31322d35 0x3830302e 0x0 }\nset actual [ read_memory 0x10020000 32 4 phys ]\nif {[compare $actual $golden] != 0} {\n shutdown error\n}\n\necho \"Accessing SHA256...\"\nset golden { 0x61327368 0x35362d32 0x3830312e 0x0 }\nset actual [ read_memory 0x10028000 32 4 phys ]\nif {[compare $actual $golden] != 0} {\n shutdown error\n}\n\necho \"Writing and reading DOE IV...\"\nset golden { 0xCAFEBABA 0xDEADBEEF 0xD0ED0E00 }\nwrite_memory 0x10000000 32 $golden phys\nset actual [ read_memory 0x10000000 32 3 phys ]\nif {[compare $actual $golden] != 0} {\n shutdown error\n}\n\n# Success\nshutdown\n" }, { "path": ".github/scripts/prepare_coverage_data.sh", "content": "#!/bin/bash\n\nset -eu\nset -o pipefail\n\nif [ -v CI ]\nthen\n set -x\n\n apt update\n apt install -y xz-utils\n\n # XZ compresses .info files A LOT better than GZIP, e.g., 9.4MB vs 175MB.\n tar acf ${SIM}_coverage_single_data.tar.xz info_files_$SIM\n ls info_files_$SIM\nfi\n\nDB_COUNT=`ls info_files_$SIM | sed 's#_[^_]*.info##' | sort | uniq | wc -l`\n\n# Filter out lockstep and el2_regfile_if modules if DCLS tests are not enabled\nif [ -v DCLS_ENABLE ]\nthen\n _filter_out=''\nelse\n _filter_out='--filter-out (lockstep|el2_regfile_if)'\nfi\n\n# Source path transformations are needed before merging to have matching paths in `.desc` files.\nfind info_files_$SIM -name '*.info' -exec info-process transform \\\n --strip-file-prefix '.*Cores-VeeR-EL2/' \\\n --filter 'design/' $_filter_out \\\n {} \\;\n\nif [ $SIM = verilator ]\nthen\n # Split branch and line before merging to have correct data in `.desc` files.\n for FILE in info_files_$SIM/*_branch.info\n do\n info-process extract --coverage-type line --output ${FILE%%_branch.info}_line.info $FILE\n info-process extract --coverage-type cond --output ${FILE%%_branch.info}_cond.info $FILE\n # Extract branch coverage last, so that it can happen in-place\n info-process extract --coverage-type branch --output $FILE $FILE\n done\nfi\n\nfor TYPE in branch line toggle cond\ndo\n _sort_opt=''\n _transform_extra_opts=''\n if [ $SIM = verilator ] && [ $TYPE = toggle ]\n then\n _sort_opt=--sort-brda-names\n _transform_extra_opts='--set-block-ids --add-two-way-toggles --add-missing-brda-entries'\n fi\n\n info-process merge --output coverage_${TYPE}_$SIM.info $_sort_opt \\\n --test-list tests_${TYPE}_$SIM.desc --test-list-strip coverage_,_$TYPE.info \\\n info_files_$SIM/*_$TYPE.info\n\n info-process transform --normalize-hit-counts $_transform_extra_opts coverage_${TYPE}_$SIM.info\ndone\n\nrm -rf info_files_$SIM\n\nif [ -z \"${GITHUB_HEAD_REF}\" ]; then\n # We're in merge triggered run\n export BRANCH=$GITHUB_REF_NAME\nelse\n # We're in PR triggered run\n export BRANCH=$GITHUB_HEAD_REF\nfi\nexport COMMIT=$GITHUB_SHA\n\n# Add config.json template, \"datasets\" will be generated by info-process.\ncat <config.json\n{\n \"title\": \"VeeR EL2 coverage dashboard\",\n \"commit\": \"$COMMIT\",\n \"branch\": \"$BRANCH\",\n \"repo\": \"cores-veer-el2\",\n \"timestamp\": \"`date +\"%Y-%m-%dT%H:%M:%S.%3N%z\"`\",\n \"additional\": {\n \"db_count\": \"$DB_COUNT\",\n \"run_id\": \"$GITHUB_RUN_ID\"\n }\n}\nEND\n\n_out_dir=data_$SIM\ninfo-process pack --output $_out_dir --config config.json \\\n --coverage-files *_$SIM.info --description-files *_$SIM.desc\nrm config.json *_$SIM.info *_$SIM.desc\n\n# add logo\ncp docs/dashboard-styles/assets/chips-alliance-logo-mono.svg $_out_dir/logo.svg\n\ncat $_out_dir/config.json\n\necho \"Coverage data ready to be packaged in $PWD/$_out_dir\"\n" }, { "path": ".github/scripts/pytest/bar.html", "content": "\n
\n \n \"back\"\n \n \n \"chips-alliance-logo\"\n \n test_pyuvm_branch.html\n
\n" }, { "path": ".github/scripts/pytest/css/styles.css", "content": "@import url(\"https://fonts.googleapis.com/css2?family=Roboto:wght@400;500;700&display=swap\");\n\nbody {\n background-color: #0e1116;\n font-family: \"Roboto\", sans-serif;\n margin: 0;\n padding: 0;\n}\n\nbody > *:not(:nth-child(3)) {\n max-width: 1520px;\n margin-left: auto;\n margin-right: auto;\n}\n\nbody > input:first-of-type {\n margin-left: max(0px, (100% - 1520px) / 2);\n}\n\nh1,\nh2,\nspan,\np {\n color: #dfe1f1;\n font-size: 16px;\n}\n\nh1,\nh2 {\n font-size: 24px;\n font-weight: 500;\n margin-top: 75px;\n}\n\na {\n color: #00d0c9;\n}\n\n.passed {\n color: #2fc36e;\n font-size: 14px;\n margin-left: 5px !important;\n}\n\n.xfailed,\n.skipped {\n color: #efac0a;\n font-size: 14px;\n margin-left: 5px !important;\n}\n\n.failed,\n.error,\n.xpassed {\n color: #f21e08;\n font-size: 14px;\n margin-left: 5px !important;\n}\n\n.col-name,\n.col-duration {\n color: #dfe1f1;\n font-size: 14px;\n}\n\n.sortable {\n color: #dfe1f1;\n font-size: 16px;\n}\n\n.log {\n background-color: #31363c;\n color: #dfe1f1;\n overflow: auto;\n}\n\n.bar {\n display: inline-flex;\n width: 100%;\n padding: 20px;\n align-items: center;\n background-color: #25292e;\n box-sizing: border-box;\n}\n\n.bar > .arrow {\n width: 30px;\n height: 30px;\n cursor: pointer;\n}\n\n.bar > .chip-alliance-link {\n position: absolute;\n left: max(150px, (100% - 1520px) / 2);\n}\n\n.bar > .title {\n position: absolute;\n left: 50%;\n transform: translateX(-50%);\n font-size: 20px;\n font-weight: 700;\n}\n\n#environment {\n color: #dfe1f1;\n width: 100%;\n}\n\n#environment tr:nth-child(odd) {\n background: none;\n}\n\n#environment td:first-child {\n width: 25%;\n}\n\n#results-table {\n color: #dfe1f1;\n}\n\n#yaml-table {\n color: #dfe1f1;\n}\n" }, { "path": ".github/scripts/pytest/script/script.js", "content": "function previousPage() {\n\twindow.history.back()\n}\n" }, { "path": ".github/scripts/pytest/style_pytest_report.sh", "content": "#!/bin/bash\n\nSELF_DIR=\"$(dirname $(readlink -f ${BASH_SOURCE[0]}))\"\n. ${SELF_DIR}/../common.inc.sh\n\nstyle_pytest_report(){\n check_args_count $# 3\n SRC_DIR=$1\n DST_DIR=$2\n HTML_FILE=$3\n echo -e \"${COLOR_WHITE}========== style_pytest_report =========${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} SRC_DIR = ${SRC_DIR}${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} DST_DIR = ${DST_DIR}${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} HTML_FILE = ${HTML_FILE}${COLOR_CLEAR}\"\n\n # Copy assets\n\n mkdir -p ${DST_DIR}/assets\n cp ${SRC_DIR}/assets/* ${DST_DIR}/assets/\n\n # Add bar above h1.title\n\n SEARCH=\"

\"\n REPLACE=`cat ${SRC_DIR}/bar.html | tr '\\n' ' '`\n REPLACE=\"$REPLACE $SEARCH\"\n filename=\"${DST_DIR}/${HTML_FILE}\"\n\n sed -i \"s@$SEARCH@$REPLACE@\" $filename\n\n # Copy JS script to build dir\n\n mkdir -p ${DST_DIR}/script\n cp -r ${SRC_DIR}/script/* ${DST_DIR}/script/\n\n echo -e \"${COLOR_WHITE}Style pytest report ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE}========== style_pytest_report =========${COLOR_CLEAR}\"\n}\n\ncheck_args_count $# 3\nstyle_pytest_report \"$@\"\n" }, { "path": ".github/scripts/requirements-coverage.txt", "content": "git+https://github.com/antmicro/sitespawner@abff708256a15a5db7c498ff7f484c78cf18d4e3\n" }, { "path": ".github/scripts/riscv_dv_matrix_include.py", "content": "from yaml import load, Loader\nfrom json import dumps\nfrom itertools import product\nimport sys\n\nRISCV_DV_TESTS = ['riscv_arithmetic_basic_test']\n\n\nif __name__ == \"__main__\":\n arg1 = sys.argv[1].strip()\n\n # Entries with pyflow for every RISCV_DV_TESTS.\n # These are included in `generate` job matrix but it's also a base for `run*` jobs.\n entries = [{\n \"test\": test,\n \"version\": \"pyflow\",\n } for test in RISCV_DV_TESTS]\n\n # The argument passed needs to match the job name as variants are generated based on its matrix.\n if arg1.startswith('run'):\n with open('.github/workflows/test-riscv-dv.yml', 'rb') as fd:\n run_tests = load(fd, Loader=Loader)['jobs'][arg1]\n job_matrix = run_tests['strategy']['matrix']\n\n # Replicate matrix entries for all variants based on the job's matrix keys and values.\n #\n # For example, if the matrix only has `test`, `version` and `iss` keys, and `iss` values\n # are `renode` and `spike`, then `entries` will be doubled after `key=iss` iteration as\n # each entry will be replaced by two entries: one with additional `iss: renode` argument\n # and the other with additional `iss: spike`.\n for key in job_matrix.keys():\n if key in ['test', 'version', 'include', 'exclude']:\n continue\n entries = [{**entry, key: value} for entry, value in product(entries, job_matrix[key])]\n print(dumps(entries))\n elif arg1 == 'generate':\n print(dumps(entries))\n else:\n exit(1)\n" }, { "path": ".github/scripts/riscv_dv_parse_testlist.py", "content": "import sys\nimport os\nfrom json import dumps\nfrom yaml import load, Loader\nfrom typing import Generator\n\nRISCV_DV_HOME = \"third_party/riscv-dv/\"\n\n\ndef parse_yaml(path: str) -> Generator[str, None, None]:\n with open(path, 'rb') as fd:\n tests = load(fd, Loader=Loader)\n for test in tests:\n if 'import' in test:\n import_path = test['import'].split('/', 1)[1]\n yield from parse_yaml(RISCV_DV_HOME + import_path)\n elif 'test' in test:\n yield test['test']\n\n\nif __name__ == \"__main__\":\n if len(sys.argv) == 2:\n testlist = RISCV_DV_HOME + f'target/{sys.argv[1]}/testlist.yaml'\n\n # check if testlist.yaml is provided by RISCV-DV; if not - it's a\n # custom testlist file not provided by RISCV-DV by default; treat the\n # script argument as full a path\n if not os.path.isdir(testlist):\n testlist = sys.argv[1]\n\n testlist = parse_yaml(testlist)\n else:\n testlist = parse_yaml(RISCV_DV_HOME + 'yaml/base_testlist.yaml')\n testlist = list(testlist)\n # remove, will cause incomplete sim, need customized RTL\n testlist.remove(\"riscv_csr_test\")\n print(dumps(testlist))\n" }, { "path": ".github/scripts/run_regression_test.sh", "content": "#!/bin/bash\n\nSELF_DIR=\"$(dirname $(readlink -f ${BASH_SOURCE[0]}))\"\n. ${SELF_DIR}/common.inc.sh\n\ntrap report_status EXIT\n\nreport_status(){\n rc=$?\n if [ $rc != 0 ]; then\n echo -e \"${COLOR_WHITE}Test '${NAME}' ${COLOR_RED}FAILED${COLOR_CLEAR}\"\n else\n mv ${DIR}/coverage.dat ${RESULTS_DIR}/\n echo -e \"${COLOR_WHITE}Test '${NAME}' ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}\"\n fi\n exit $rc\n}\n\nrun_regression_test(){\n # Run a regression test with coverage collection enabled\n # Args:\n # RESULTS_DIR -\n # BUS -\n # NAME -\n # COVERAGE -\n # USER_MODE - '1' for user mode, '0' for without user mode\n # CACHE WAYPACK -\n check_args_count $# 6\n RESULTS_DIR=$1\n BUS=$2\n NAME=$3\n COVERAGE=$4\n USER_MODE=$5\n ICACHE_WAYPACK=$6\n echo -e \"${COLOR_WHITE}========== running test '${NAME}' =========${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} RESULTS_DIR = ${RESULTS_DIR}${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} SYSTEM BUS = ${BUS}${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} NAME = ${NAME}${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} COVERAGE = ${COVERAGE}${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} USER_MODE = ${USER_MODE}${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} ICACHE_WAYPACK = ${ICACHE_WAYPACK}${COLOR_CLEAR}\"\n\n COMMON_PARAMS=\"-set bitmanip_zba -set bitmanip_zbb -set bitmanip_zbc -set bitmanip_zbe -set bitmanip_zbf -set bitmanip_zbp -set bitmanip_zbr -set bitmanip_zbs -set=fpga_optimize=0\"\n\n if [[ \"${USER_MODE}\" == \"1\" ]]; then\n COMMON_PARAMS=\"-set=user_mode=1 -set=smepmp=1 ${COMMON_PARAMS}\"\n fi\n\n # DLCS_ENABLE may not be set\n set +u\n if [[ -z \"${DCLS_ENABLE}\" ]]; then\n DCLS_ENABLE=\"0\"\n fi\n set -u\n\n if [[ \"${DCLS_ENABLE}\" == \"1\" ]]; then\n COMMON_PARAMS=\"-set lockstep_enable=1 -set lockstep_regfile_enable=1 ${COMMON_PARAMS}\"\n fi\n\n COMMON_PARAMS=\"-set=icache_waypack=${ICACHE_WAYPACK} ${COMMON_PARAMS}\"\n\n if [[ \"${BUS}\" == \"axi\" ]]; then\n PARAMS=\"-set build_axi4 ${COMMON_PARAMS}\"\n elif [[ \"${BUS}\" == \"ahb\" ]]; then\n PARAMS=\"-set build_ahb_lite ${COMMON_PARAMS}\"\n else\n echo -e \"${COLOR_RED}Unknown system bus type '${BUS}'${COLOR_CLEAR}\"\n exit 1\n fi\n\n echo -e \"${COLOR_WHITE} CONF PARAMS = ${PARAMS}${COLOR_CLEAR}\"\n\n mkdir -p ${RESULTS_DIR}\n LOG=\"${RESULTS_DIR}/test_${NAME}_${COVERAGE}_${USER_MODE}.log\"\n touch ${LOG}\n DIR=\"run_${NAME}_${COVERAGE}_${USER_MODE}\"\n\n if [ \"$NAME\" = \"pmp_random\" ]; then\n EXTRA_ARGS='TB_MAX_CYCLES=8000000'\n else\n EXTRA_ARGS=\n fi\n\n # Run the test\n mkdir -p ${DIR}\n make -j`nproc` -C ${DIR} -f $RV_ROOT/tools/Makefile verilator $EXTRA_ARGS CONF_PARAMS=\"${PARAMS}\" TEST=${NAME} COVERAGE=${COVERAGE} 2>&1 | tee ${LOG}\n}\n\n# Example usage\n# RESULTS_DIR=results\n# BUS=axi\n# NAME=hello_world\n# COVERAGE=branch\n# USER_MODE=1\n# run_regression_test.sh $RESULTS_DIR $BUS $NAME $COVERAGE $USER_MODE\n\ncheck_args_count $# 6\nrun_regression_test \"$@\"\n" }, { "path": ".github/scripts/run_regression_tests.sh", "content": "#!/bin/bash\nCOLOR_CLEAR=\"\\033[0m\"\nCOLOR_WHITE=\"\\033[1;37m\"\nCOLOR_RED=\"\\033[0;31m\"\nCOLOR_GREEN=\"\\033[1;32m\"\n\nRESULTS_DIR=\"results\"\n\nmkdir -p ${RESULTS_DIR}\n\n# Configure VeeR\necho -e \"${COLOR_WHITE}==================== Configuring VeeR-EL2 core ====================${COLOR_CLEAR}\"\n$RV_ROOT/configs/veer.config\nif [ $? -ne 0 ]; then\n echo \"Failed to configure VeeR-EL2 core\"\n exit -1\nfi\n\n# Run regression tests with coverage collection enabled\nEXITCODE=0\nTESTS=($TESTS)\nfor NAME in ${TESTS[@]}; do\n echo -e \"${COLOR_WHITE}==================== running test '${NAME}' ====================${COLOR_CLEAR}\"\n\n for COVERAGE in branch toggle functional; do\n\n echo -e \"${COLOR_WHITE}========== ${COVERAGE} coverage ==========${COLOR_CLEAR}\"\n LOG=\"${RESULTS_DIR}/test_${NAME}_${COVERAGE}.log\"\n DIR=\"run_${NAME}_${COVERAGE}\"\n\n # Run the test\n mkdir -p ${DIR}\n make -j`nproc` -C ${DIR} -f $RV_ROOT/tools/Makefile verilator TEST=${NAME} COVERAGE=${COVERAGE} 2>&1 | tee ${LOG}\n RES=${PIPESTATUS[0]}\n if [ ${RES} -ne 0 ] || ! [ -f \"${DIR}/coverage.dat\" ]; then\n EXITCODE=-1\n echo -e \"${COLOR_WHITE}Test '${NAME}' ${COLOR_RED}FAILED${COLOR_CLEAR}\"\n else\n\n # Copy and convert coverage data\n cp ${DIR}/coverage.dat ${RESULTS_DIR}/coverage_${NAME}_${COVERAGE}.dat\n verilator_coverage --write-info ${RESULTS_DIR}/coverage_${NAME}_${COVERAGE}.info ${RESULTS_DIR}/coverage_${NAME}_${COVERAGE}.dat\n\n echo -e \"${COLOR_WHITE}Test '${NAME}' ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}\"\n fi\n done\ndone\n\nexit ${EXITCODE}\n" }, { "path": ".github/scripts/secrets_version", "content": "3\n" }, { "path": ".github/scripts/test.gdb", "content": "# SPDX-License-Identifier: Apache-2.0\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\necho Connecting to OpenOCD...\\n\nset architecture riscv:rv32\nset remotetimeout 360\ntarget extended-remote :3333\n\necho Dumping registers...\\n\ninfo registers\n\necho Accessing region at 0x20000000...\\n\nset *(0x20000000) = 0x01234567\nset *(0x20000004) = 0x89ABCDEF\nset *(0x20000008) = 0x55555555\nset *(0x2000000C) = 0xAAAAAAAA\nset *(0x25555550) = 0x55555555\nset *(0x2aaaaaa0) = 0xAAAAAAAA\nprint/x *0x20000000@4\nprint/x *0x25555550\nprint/x *0x2aaaaaa0\n\necho Accessing region at 0x30000000...\\n\nset *(0x30000000) = 0x01234567\nset *(0x30000004) = 0x89ABCDEF\nset *(0x30000008) = 0x55555555\nset *(0x3000000C) = 0xAAAAAAAA\nset *(0x35555550) = 0x55555555\nset *(0x3aaaaaa0) = 0xAAAAAAAA\nprint/x *0x30000000@4\nprint/x *0x35555550\nprint/x *0x3aaaaaa0\n\necho Accessing region at 0x40000000...\\n\nset *(0x40000000) = 0x01234567\nset *(0x40000004) = 0x89ABCDEF\nset *(0x40000008) = 0x55555555\nset *(0x4000000C) = 0xAAAAAAAA\nset *(0x45555550) = 0x55555555\nset *(0x4aaaaaa0) = 0xAAAAAAAA\nprint/x *0x40000000@4\nprint/x *0x45555550\nprint/x *0x4aaaaaa0\n\necho Accessing region at 0x50000000...\\n\nset *(0x50000000) = 0x01234567\nset *(0x50000004) = 0x89ABCDEF\nset *(0x50000008) = 0x55555555\nset *(0x5000000C) = 0xAAAAAAAA\nset *(0x55555550) = 0x55555555\nset *(0x5aaaaaa0) = 0xAAAAAAAA\nprint/x *0x50000000@4\nprint/x *0x55555550\nprint/x *0x5aaaaaa0\n\necho Accessing region at 0x60000000...\\n\nset *(0x60000000) = 0x01234567\nset *(0x60000004) = 0x89ABCDEF\nset *(0x60000008) = 0x55555555\nset *(0x6000000C) = 0xAAAAAAAA\nset *(0x65555550) = 0x55555555\nset *(0x6aaaaaa0) = 0xAAAAAAAA\nprint/x *0x60000000@4\nprint/x *0x65555550\nprint/x *0x6aaaaaa0\n\necho Accessing region at 0x70000000...\\n\nset *(0x70000000) = 0x01234567\nset *(0x70000004) = 0x89ABCDEF\nset *(0x70000008) = 0x55555555\nset *(0x7000000C) = 0xAAAAAAAA\nset *(0x75555550) = 0x55555555\nset *(0x7aaaaaa0) = 0xAAAAAAAA\nprint/x *0x70000000@4\nprint/x *0x75555550\nprint/x *0x7aaaaaa0\n\necho Accessing region at 0x80000000...\\n\nset *(0x80000000) = 0x01234567\nset *(0x80000004) = 0x89ABCDEF\nset *(0x80000008) = 0x55555555\nset *(0x8000000C) = 0xAAAAAAAA\nset *(0x85555550) = 0x55555555\nset *(0x8aaaaaa0) = 0xAAAAAAAA\nprint/x *0x80000000@4\nprint/x *0x85555550\nprint/x *0x8aaaaaa0\n\necho Accessing region at 0x90000000...\\n\nset *(0x90000000) = 0x01234567\nset *(0x90000004) = 0x89ABCDEF\nset *(0x90000008) = 0x55555555\nset *(0x9000000C) = 0xAAAAAAAA\nset *(0x95555550) = 0x55555555\nset *(0x9aaaaaa0) = 0xAAAAAAAA\nprint/x *0x90000000@4\nprint/x *0x95555550\nprint/x *0x9aaaaaa0\n\necho Accessing region at 0xa0000000...\\n\nset *(0xa0000000) = 0x01234567\nset *(0xa0000004) = 0x89ABCDEF\nset *(0xa0000008) = 0x55555555\nset *(0xa000000C) = 0xAAAAAAAA\nset *(0xa5555550) = 0x55555555\nset *(0xaaaaaaa0) = 0xAAAAAAAA\nprint/x *0xa0000000@4\nprint/x *0xa5555550\nprint/x *0xaaaaaaa0\n\necho Accessing region at 0xb0000000...\\n\nset *(0xb0000000) = 0x01234567\nset *(0xb0000004) = 0x89ABCDEF\nset *(0xb0000008) = 0x55555555\nset *(0xb000000C) = 0xAAAAAAAA\nset *(0xb5555550) = 0x55555555\nset *(0xbaaaaaa0) = 0xAAAAAAAA\nprint/x *0xb0000000@4\nprint/x *0xb5555550\nprint/x *0xbaaaaaa0\n\necho Accessing region at 0xc0000000...\\n\nset *(0xc0000000) = 0x01234567\nset *(0xc0000004) = 0x89ABCDEF\nset *(0xc0000008) = 0x55555555\nset *(0xc000000C) = 0xAAAAAAAA\nset *(0xc5555550) = 0x55555555\nset *(0xcaaaaaa0) = 0xAAAAAAAA\nprint/x *0xc0000000@4\nprint/x *0xc5555550\nprint/x *0xcaaaaaa0\n\necho Accessing region at 0xd0000000...\\n\nset *(0xd0000000) = 0x01234567\nset *(0xd0000004) = 0x89ABCDEF\nset *(0xd0000008) = 0x55555555\nset *(0xd000000C) = 0xAAAAAAAA\nset *(0xd5555550) = 0x55555555\nset *(0xdaaaaaa0) = 0xAAAAAAAA\nprint/x *0xd0000000@4\nprint/x *0xd5555550\nprint/x *0xdaaaaaa0\n\necho Setting Breakpoint 1...\\n\nhbreak *0x1c\n\necho Continuing...\\n\ncontinue\n\ndelete\n\n# end the simulation gracefully\nset *(volatile unsigned char*)0xd0580000 = 0xff\n" }, { "path": ".github/scripts/utils.sh", "content": "#!/bin/bash\n# SPDX-License-Identifier: Apache-2.0\n# Copyright 2024 Antmicro \n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\n\n# Colors\nCOLOR_OFF='\\033[0m'\nCOLOR_RED='\\033[31m'\nCOLOR_GREEN='\\033[32m'\nCOLOR_WHITE='\\033[1;37m'\n\n# Waits until the given phrase appears in a log file (actively written to)\n# Usage: wait_for_phrase \nwait_for_phrase () {\n\n # Check if the log exists\n sleep 1s\n if ! [ -f \"$1\" ]; then\n echo -e \"${COLOR_RED}Log file '$1' not found!${COLOR_OFF}\"\n return -1\n fi\n\n # Wait for the phrase\n DEADLINE=$(($(date +%s) + 30))\n while [ $(date +%s) -lt ${DEADLINE} ]\n do\n # Check for the phrase\n grep \"$2\" \"$1\" >/dev/null\n if [ $? -eq 0 ]; then\n return 0\n fi\n\n # Sleep and retry\n sleep 1s\n done\n\n # Timeout\n return -1\n}\n\n# Terminates a process. First via SIGINT and if this doesn't work after 10s\n# retries with SIGKILL\n# Usage: terminate \nterminate () {\n\n local PID=$1\n\n # Gently interrupt, wait some time and then kill\n /bin/kill -s SIGINT ${PID} || true\n sleep 10s\n /bin/kill -s SIGKILL ${PID} || true\n}\n" }, { "path": ".github/workflows/build-docs.yml", "content": "name: Documentation build\n\non:\n workflow_call:\n\njobs:\n build:\n name: Build\n runs-on: ubuntu-24.04\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n steps:\n - name: Install dependencies\n run: |\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n python3 python3-pip\n - name: Setup repository\n uses: actions/checkout@v4\n - name: Build Docs\n run: |\n pushd docs\n pip3 install -r requirements.txt\n TZ=UTC make html\n popd\n ls -lah docs/build\n - name: Pack artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: docs\n path: ./docs/build\n" }, { "path": ".github/workflows/ci.yml", "content": "name: VeeR-EL2 CI\n\non:\n push:\n branches: [\"main\"]\n pull_request:\n workflow_dispatch:\n schedule:\n - cron: '0 2 * * *' # run daily at 02:00 am (UTC)\n\njobs:\n\n Test-DCLS:\n name: Test-DCLS-Regression\n uses: ./.github/workflows/test-regression-dcls.yml\n\n Test-Regression-Cache-Waypack-0-num-ways-2:\n name: Test-Regression Cache Waypack 0 Num Ways 2\n uses: ./.github/workflows/test-regression-cache-waypack.yml\n with:\n waypack: 0\n num_ways: 2\n\n Test-Regression-Cache-Waypack-0-num-ways-4:\n name: Test-Regression Cache Waypack 0 Num Ways 4\n uses: ./.github/workflows/test-regression-cache-waypack.yml\n with:\n waypack: 0\n num_ways: 4\n\n Test-Regression-Cache-Waypack-1-num-ways-2:\n name: Test-Regression Cache Waypack 1 Num Ways 2\n uses: ./.github/workflows/test-regression-cache-waypack.yml\n with:\n waypack: 1\n num_ways: 2\n\n Test-Regression-Cache-Waypack-1-num-ways-4:\n name: Test-Regression Cache Waypack 1 Num Ways 4\n uses: ./.github/workflows/test-regression-cache-waypack.yml\n with:\n waypack: 1\n num_ways: 4\n\n Test-Exceptions-Regression:\n name: Test-Exceptions-Regression\n uses: ./.github/workflows/test-regression-exceptions.yml\n\n Test-Verification:\n name: Test-Verification\n uses: ./.github/workflows/test-verification.yml\n\n Test-Microarchitectural:\n name: Test-Microarchitectural\n uses: ./.github/workflows/test-uarch.yml\n\n Test-RISCV-DV:\n name: Test-RISCV-DV\n uses: ./.github/workflows/test-riscv-dv.yml\n\n Test-RISCOF:\n name: Test-RISCOF\n uses: ./.github/workflows/test-riscof.yml\n\n Test-UVM:\n name: Test-UVM\n uses: ./.github/workflows/test-uvm.yml\n\n Test-Renode:\n name: Test-Renode\n uses: ./.github/workflows/test-renode.yml\n\n Test-OpenOCD:\n name: Test-OpenOCD\n uses: ./.github/workflows/test-openocd.yml\n\n Report-Coverage:\n name: Report-Coverage\n needs: [\n Test-DCLS,\n Test-Regression-Cache-Waypack-0-num-ways-2,\n Test-Regression-Cache-Waypack-0-num-ways-4,\n Test-Regression-Cache-Waypack-1-num-ways-2,\n Test-Regression-Cache-Waypack-1-num-ways-4,\n Test-Exceptions-Regression,\n Test-Verification,\n Test-Microarchitectural,\n Test-RISCV-DV,\n Test-RISCOF,\n Test-OpenOCD\n ]\n uses: ./.github/workflows/report-coverage.yml\n\n Build-Docs:\n name: Build-Docs\n uses: ./.github/workflows/build-docs.yml\n\n Publish-to-GH-Pages:\n concurrency:\n group: concurrency-group-${{ github.repository }}-publish\n cancel-in-progress: false\n permissions:\n actions: write\n contents: write\n name: Publish-to-GH-Pages\n needs: [Report-Coverage, Build-Docs]\n uses: ./.github/workflows/publish-webpage.yml\n" }, { "path": ".github/workflows/custom-lint.yml", "content": "name: Custom lint\n\non:\n push:\n branches:\n - main\n pull_request:\n\njobs:\n run-lint:\n name: Run lint\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: centos:8\n env:\n GHA_EXTERNAL_DISK: additional-tools-all\n GHA_SA: gh-sa-veer-uploader\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Run lint\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_lint\n" }, { "path": ".github/workflows/gh-pages-pr-closed.yml", "content": "name: GH-Pages PR Remove\n\non:\n pull_request:\n types:\n - closed\n\njobs:\n build:\n name: PR Remove\n concurrency:\n group: gh-pages\n runs-on: ubuntu-24.04\n permissions:\n contents: write\n steps:\n\n - name: Save PR number\n run: |\n echo \"number=${{ github.event.number }}\" >> delete_pr_number.txt\n\n - name: Upload artifacts\n uses: actions/upload-artifact@v4\n with:\n name: delete_pr_number\n path: ./delete_pr_number.txt" }, { "path": ".github/workflows/gh-pages-pr-comment.yml", "content": "name: GH-Pages PR Comment\n\non:\n workflow_run:\n workflows: [\"VeeR-EL2 CI\"]\n types:\n - completed\n\nenv:\n WEB_URL: 'https://chipsalliance.github.io/Cores-VeeR-EL2/'\n\njobs:\n comment:\n name: PR Comment\n runs-on: ubuntu-24.04\n permissions:\n pull-requests: write\n if: ${{ github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success' }}\n steps:\n\n - name: Download artifact\n id: download-artifact\n uses: dawidd6/action-download-artifact@v6\n with:\n name: pr_number\n path: ./\n run_id: ${{ github.event.workflow_run.id }}\n\n - name: Extract PR number\n id: PR\n run: |\n cat pr_number.txt | tee \"$GITHUB_OUTPUT\"\n\n - uses: actions/github-script@v6\n with:\n script: |\n github.rest.issues.createComment({\n issue_number: ${{ steps.PR.outputs.number }},\n owner: context.repo.owner,\n repo: context.repo.repo,\n body: 'Coverage report for this PR is available at ${{ env.WEB_URL }}/html/dev/${{ steps.PR.outputs.number }}/coverage_dashboard/all, documentation is available at ${{ env.WEB_URL }}/html/dev/${{ steps.PR.outputs.number }}/docs_rendered/html'\n })\n" }, { "path": ".github/workflows/gh-pages-pr-remove.yml", "content": "name: GH-Pages PR Remove Deploy\n\non:\n workflow_run:\n workflows: [\"GH-Pages PR Remove\"]\n types:\n - completed\n\nenv:\n ROOT_DIR: './public.new'\n\njobs:\n remove:\n name: PR Remove Deploy\n concurrency:\n group: gh-pages\n runs-on: ubuntu-24.04\n permissions:\n contents: write\n steps:\n - name: Setup repository\n uses: actions/checkout@v4\n\n - name: Install coverage dependencies\n run: |\n python3 -m venv .venv\n source .venv/bin/activate\n pip install -r .github/scripts/requirements-coverage.txt\n echo \"PATH=$PATH\" >> $GITHUB_ENV\n\n - name: Download deployment\n uses: actions/checkout@v4\n with:\n ref: gh-pages\n path: ${{ env.ROOT_DIR }}\n\n - name: Download artifact\n id: download-artifact\n uses: dawidd6/action-download-artifact@v6\n with:\n name: delete_pr_number\n path: ./\n run_id: ${{ github.event.workflow_run.id }}\n\n - name: Extract PR number\n id: PR\n run: |\n cat delete_pr_number.txt | tee \"$GITHUB_OUTPUT\"\n rm -rf delete_pr_number.txt\n\n - name: Update the webpage\n run: |\n rm -rf ${{ env.ROOT_DIR }}/html/dev/${{ steps.PR.outputs.number }}\n rm -rf ${{ env.ROOT_DIR }}/doctrees/dev/${{ steps.PR.outputs.number }}\n\n - name: Add redirect index page\n run: |\n cp .github/scripts/indexgen/index_redirect/index.html ./public.new/\n\n - name: Deploy\n uses: peaceiris/actions-gh-pages@v4\n with:\n github_token: ${{ secrets.GITHUB_TOKEN }}\n publish_dir: ./public.new\n commit_message: \"Remove reports from PR#${{ steps.PR.outputs.number }}\"\n force_orphan: true\n" }, { "path": ".github/workflows/publish-webpage.yml", "content": "name: GH-Pages Build and Main Deploy\n\non:\n workflow_call:\n\njobs:\n build:\n name: Build and Main Deploy\n concurrency:\n group: gh-pages\n runs-on: ubuntu-24.04\n container:\n image: debian:trixie\n permissions:\n contents: write\n steps:\n - name: Setup repository\n uses: actions/checkout@v4\n\n - name: Print metadata\n run: |\n run_information=\"Repository: ${{ github.repository }} Commit SHA:${{ github.sha }} Workflow: ${{ github.workflow }} Run:${{ github.run_id }}\"\n echo $run_information\n\n - name: Download coverage reports\n uses: actions/download-artifact@v4\n with:\n name: data_verilator\n path: data_verilator/\n\n - name: Download coverage reports merged\n uses: actions/download-artifact@v4\n with:\n name: data_both\n path: data_both/\n\n - name: Download docs\n uses: actions/download-artifact@v4\n with:\n name: docs\n path: ./docs_rendered\n\n - name: Download verification reports\n uses: actions/download-artifact@v4\n with:\n pattern: verification_dashboard*\n merge-multiple: true\n path: ./verification_dashboard\n\n - name: Download RISCOF report\n uses: actions/download-artifact@v4\n with:\n pattern: riscof-report*\n merge-multiple: true\n path: ./riscof_dashboard\n\n - name: Checkout gh-pages\n uses: actions/checkout@v4\n with:\n ref: gh-pages\n path: ./public.checkout\n\n - name: Preserve only valid items\n run: |\n mkdir -p ./public.new\n mv ./public.checkout/doctrees ./public.new/ | true\n mv ./public.checkout/html ./public.new/ | true\n\n - name: Update webpage\n run: |\n set -eux\n set -o pipefail\n\n apt -y update\n apt -y install nodejs npm python3 zip git\n\n echo \"Event: $GITHUB_EVENT_NAME, ref: $GITHUB_REF_NAME)\"\n if [ \"$GITHUB_EVENT_NAME\" = pull_request ]\n then\n TARGET_DIR=\"${PWD}/public.new/html/dev/${{ github.event.number }}\"\n elif [ \"$GITHUB_REF_NAME\" = main ]\n then\n TARGET_DIR=\"${PWD}/public.new/html/main\"\n else\n # Currently deploying is only possible in PRs and on main but let's\n # better keep things safe in case that's changed in the future by\n # using another target dir in other cases.\n TARGET_DIR=\"${PWD}/public.new/html/other\"\n fi\n\n mkdir -p $TARGET_DIR\n\n # data\n cd data_verilator\n zip $TARGET_DIR/data.zip *\n cd ../data_both\n zip $TARGET_DIR/data_both.zip *\n cd ..\n\n # get coverview\n git clone https://github.com/antmicro/coverview\n cd coverview\n npm install\n npm run build\n python3 embed.py --inject-data $TARGET_DIR/data_both.zip\n cd ..\n\n # dashboard\n rm -rf $TARGET_DIR/coverage_dashboard*\n mkdir -p $TARGET_DIR/coverage_dashboard/all\n cp -a coverview/dist/* $TARGET_DIR/coverage_dashboard/all\n\n # docs\n rm -rf $TARGET_DIR/docs_rendered\n mkdir -p $TARGET_DIR/docs_rendered\n mv ./docs_rendered/* $TARGET_DIR/docs_rendered\n\n echo ${GITHUB_RUN_ID} > $TARGET_DIR/run_id\n tar -acf webpage.tar.gz public.new\n\n - name: Add redirect index page\n run: |\n cp .github/scripts/indexgen/index_redirect/index.html ./public.new/\n\n - name: Deploy\n uses: peaceiris/actions-gh-pages@v4\n if: ${{ github.ref == 'refs/heads/main' || github.event_name == 'pull_request' }}\n with:\n github_token: ${{ secrets.GITHUB_TOKEN }}\n publish_dir: ./public.new\n force_orphan: true\n\n - name: Save PR number\n if: github.event_name == 'pull_request'\n run: |\n echo \"number=${{ github.event.number }}\" >> pr_number.txt\n\n - name: Upload artifacts\n uses: actions/upload-artifact@v4\n if: github.event_name == 'pull_request'\n with:\n name: pr_number\n path: ./pr_number.txt\n\n - name: Pack webpage as an artifact\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: webpage\n path: ./webpage.tar.gz\n" }, { "path": ".github/workflows/report-coverage.yml", "content": "name: Coverage report\n\non:\n workflow_call:\n\ndefaults:\n run:\n shell: bash\n\njobs:\n merge-verilator-reports:\n name: Merge Verilator info data\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Download coverage reports\n uses: actions/download-artifact@v4\n with:\n pattern: \"*coverage_data*\"\n merge-multiple: true\n path: ./\n\n - name: Setup info-process\n run: .github/scripts/info_process_setup.sh\n\n - name: Merge data\n run: |\n mkdir info_files_verilator\n mv *.info info_files_verilator/\n export SIM=verilator\n .github/scripts/prepare_coverage_data.sh\n\n - name: Pack artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: verilator_coverage_single_data\n path: verilator_coverage_single_data.tar.xz\n\n - name: Pack artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: data_verilator\n path: data_verilator/*\n\n custom-coverage-reports:\n name: Custom coverage reports\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: centos:8\n env:\n GHA_EXTERNAL_DISK: additional-tools\n GHA_SA: gh-sa-veer-uploader\n\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Prepare Environment\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_prepare_env\n\n - name: Generate custom reports\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_custom_report\n\n - name: Pack artifacts\n uses: actions/upload-artifact@v4\n with:\n name: info_files_v_mapped\n path: info_files_v/*\n\n both-coverage-reports:\n name: Coverage reports merger\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: debian:trixie\n needs: [merge-verilator-reports, custom-coverage-reports]\n env:\n DEBIAN_FRONTEND: noninteractive\n GHA_EXTERNAL_DISK: additional-tools\n GHA_SA: gh-sa-veer-uploader\n\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Extract custom coverage\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_extract_custom_coverage\n\n - name: Setup info-process\n run: .github/scripts/info_process_setup.sh\n\n - name: Prepare custom coverage\n run: |\n export SIM=v\n .github/scripts/prepare_coverage_data.sh\n # info_files_v_mapped uses the same dir.\n rm -rf info_files_v\n\n - name: Pack artifacts\n uses: actions/upload-artifact@v4\n with:\n name: v_coverage_single_data\n path: v_coverage_single_data.tar.xz\n\n - name: Pack artifacts\n uses: actions/upload-artifact@v4\n with:\n name: data_v\n path: data_v/*\n\n - name: Download Verilator data\n uses: actions/download-artifact@v4\n with:\n name: data_verilator\n path: data_verilator/\n\n - name: Compare tests\n run: |\n cat data_v/*.desc | grep '^TEST:' | sed 's#.*,##' | sed 's#;#\\n#g' | sort | uniq >tests_v\n cat data_verilator/*.desc | grep '^TEST:' | sed 's#.*,##' | sed 's#;#\\n#g' | sort | uniq >tests_verilator\n # `|| true` because it's only needed for informational purposes, a difference is not a reason to fail.\n diff -yt tests_v tests_verilator || true\n\n - name: Create merged package\n run: |\n .github/scripts/create_merged_package.sh\n rm -rf data_verilator\n rm -rf data_v\n\n - name: Pack artifacts\n uses: actions/upload-artifact@v4\n with:\n name: data_both\n path: data_both/*\n\n - name: Download V mapped info files\n uses: actions/download-artifact@v4\n with:\n name: info_files_v_mapped\n path: info_files_v\n\n - name: Prepare custom coverage\n run: |\n export SIM=v\n .github/scripts/prepare_coverage_data.sh\n\n - name: Pack artifacts\n uses: actions/upload-artifact@v4\n with:\n name: data_v_mapped\n path: data_v/*\n" }, { "path": ".github/workflows/test-openocd.yml", "content": "name: Test-OpenOCD\n\non:\n workflow_call:\n\ndefaults:\n run:\n shell: bash\n\njobs:\n tests:\n name: Run OpenOCD tests\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n strategy:\n fail-fast: false\n matrix:\n coverage: [\"all\"]\n bus: [\"axi4\", \"ahb_lite\"]\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n CCACHE_DIR: \"/opt/openocd-tests/.cache/\"\n\n steps:\n - name: Install utils\n run: |\n echo \"deb http://archive.ubuntu.com/ubuntu/ noble main universe\" | sudo tee -a /etc/apt/sources.list > /dev/null\n echo \"debconf debconf/frontend select Noninteractive\" | sudo debconf-set-selections\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n ccache ninja-build gcc-riscv64-unknown-elf\n pip3 install meson\n wget https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz\n tar -xzf riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz\n mv riscv /opt/\n\n - name: Setup Cache Metadata\n id: cache_metadata\n run: |\n date=$(date +\"%Y_%m_%d\")\n time=$(date +\"%Y%m%d_%H%M%S_%N\")\n cache_test_restore_key=${{ matrix.coverage }}_\n cache_test_key=${cache_test_restore_key}${time}\n echo \"date=$date\" | tee -a \"$GITHUB_ENV\"\n echo \"time=$time\" | tee -a \"$GITHUB_ENV\"\n echo \"cache_test_restore_key=$cache_test_restore_key\" | tee -a \"$GITHUB_ENV\"\n echo \"cache_test_key=$cache_test_key\" | tee -a \"$GITHUB_ENV\"\n\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install coverage dependencies\n run: |\n python3 -m venv .venv\n source .venv/bin/activate\n pip install -r .github/scripts/requirements-coverage.txt\n echo \"PATH=$PATH\" >> $GITHUB_ENV\n\n - name: Build verilated simulation\n run: |\n export PATH=/opt/verilator/bin:/opt/openocd/bin:$PATH\n export RV_ROOT=$(pwd)\n mkdir run\n make -C run -f ${RV_ROOT}/tools/Makefile verilator-build program.hex TEST=infinite_loop \\\n CONF_PARAMS=\"-set build_${{ matrix.bus }} -set openocd_test\" COVERAGE=${{ matrix.coverage }} -j$(nproc)\n cd run\n ${RV_ROOT}/.github/scripts/openocd_test.sh \\\n -f ${RV_ROOT}/testbench/openocd_scripts/verilator-rst.cfg \\\n -f ${RV_ROOT}/testbench/openocd_scripts/jtag_cg.tcl\n pkill openocd || true\n\n - name: Test with GDB-test (register access, memory access, breakpoints)\n run: |\n # TODO GDB is in /opt/riscv and a separate toolchain is installed with apt. Make this better.\n export PATH=/opt/riscv/bin:/opt/verilator/bin:/opt/openocd/bin:$PATH\n export RV_ROOT=$(pwd)\n mkdir gdb_test\n make -C gdb_test -f ${RV_ROOT}/tools/Makefile verilator-build program.hex TEST=infinite_loop \\\n CONF_PARAMS=\"-set build_${{ matrix.bus }} -set openocd_test\" COVERAGE=${{ matrix.coverage }} -j$(nproc)\n cd gdb_test\n ${RV_ROOT}/.github/scripts/gdb_test.sh\n pkill openocd || true\n\n - name: Prepare coverage data\n run: |\n export PATH=/opt/verilator/bin:$PATH\n export RV_ROOT=$(pwd)\n\n mkdir -p results\n\n if [ ${{ matrix.bus }} = axi4 ]; then\n BUS_NAME=axi\n elif [ ${{ matrix.bus }} = ahb_lite ]; then\n BUS_NAME=ahb\n fi\n\n .github/scripts/convert_dat.sh ${RV_ROOT}/run/coverage.dat \\\n results/coverage_${BUS_NAME}-openocd\n .github/scripts/convert_dat.sh ${RV_ROOT}/gdb_test/coverage.dat \\\n results/coverage_${BUS_NAME}-openocd-gdb\n\n - name: Pack artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: openocd_coverage_data_${{ matrix.bus }}_${{ matrix.coverage }}\n path: results/*.info\n\n custom-openocd-tests:\n name: Run Custom OpenOCD tests\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: centos:8\n strategy:\n fail-fast: false\n matrix:\n bus: [\"axi4\"]\n env:\n GHA_EXTERNAL_DISK: additional-tools\n GHA_SA: gh-sa-veer-uploader\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Run tests\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_custom_openocd_tests\n BUS: ${{ matrix.bus }}\n" }, { "path": ".github/workflows/test-regression-cache-waypack.yml", "content": "name: Regression tests cache waypack\n\non:\n workflow_call:\n inputs:\n waypack:\n required: true\n type: number\n num_ways:\n required: true\n type: number\n\ndefaults:\n run:\n shell: bash\n\nenv:\n WAYPACK: ${{ inputs.waypack }}\n NUM_WAYS: ${{ inputs.num_ways }}\n\njobs:\n regression-tests:\n name: Regression tests\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n strategy:\n matrix:\n bus: [\"axi\", \"ahb\"]\n test: [\"hello_world\", \"hello_world_dccm\", \"hello_world_iccm\", \"cmark\", \"cmark_dccm\", \"cmark_iccm\", \"dhry\", \"ecc\",\n \"csr_misa\", \"csr_access\", \"csr_mstatus\", \"csr_mseccfg\", \"modesw\", \"insns\", \"irq\", \"perf_counters\",\n \"pmp\", \"pmp_random\", \"write_unaligned\", \"icache\", \"bitmanip\", \"read_after_read\"]\n coverage: [\"all\"]\n priv: [\"0\", \"1\"]\n tb_extra_args: [\"--test-halt\"] # hello_world_iccm will also have --test-lsu-clk-ratio\n exclude:\n # These tests require user mode\n - priv: \"0\"\n test: \"csr_mseccfg\"\n - priv: \"0\"\n test: \"csr_access\"\n - priv: \"0\"\n test: \"csr_mstatus\"\n - priv: \"0\"\n test: \"modesw\"\n - priv: \"0\"\n test: \"insns\"\n - priv: \"0\"\n test: \"perf_counters\"\n # end tests which require user mode\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n CCACHE_DIR: \"/opt/regression/.cache/\"\n\n steps:\n - name: Install utils\n run: |\n echo \"deb http://archive.ubuntu.com/ubuntu/ noble main universe\" | sudo tee -a /etc/apt/sources.list > /dev/null\n echo \"debconf debconf/frontend select Noninteractive\" | sudo debconf-set-selections\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n git python3 python3-pip build-essential ninja-build ccache \\\n gcc-riscv64-unknown-elf\n pip3 install meson --break-system-packages\n\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install coverage dependencies\n run: |\n python3 -m venv .venv\n source .venv/bin/activate\n pip install -r .github/scripts/requirements-coverage.txt\n echo \"PATH=$PATH\" >> $GITHUB_ENV\n\n - name: Setup environment\n run: |\n echo \"/opt/verilator/bin\" >> $GITHUB_PATH\n RV_ROOT=`pwd`\n echo \"RV_ROOT=$RV_ROOT\" >> $GITHUB_ENV\n PYTHONUNBUFFERED=1\n echo \"PYTHONUNBUFFERED=$PYTHONUNBUFFERED\" >> $GITHUB_ENV\n TEST_PATH=$RV_ROOT/test_results\n echo \"TEST_PATH=$TEST_PATH\" >> $GITHUB_ENV\n echo \"FULL_NAME=${{ matrix.bus }}-${{ matrix.test }}-${{ matrix.priv == 0 && 'm' || 'mu' }}-waypack${WAYPACK}-num-ways${NUM_WAYS}\" >> $GITHUB_ENV\n\n - name: Run tests\n run: |\n export PATH=/opt/verilator/bin:$PATH\n export RV_ROOT=`pwd`\n export TB_EXTRA_ARGS=\"${{ matrix.tb_extra_args }}\"\n # Use hello_world_iccm for testing '--test-lsu-clk-ratio'\n if [ ${{ matrix.test }} = hello_world_iccm ]; then\n export TB_EXTRA_ARGS=\"$TB_EXTRA_ARGS --test-lsu-clk-ratio\"\n fi\n .github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.bus }} ${{ matrix.test}} ${{ matrix.coverage }} ${{ matrix.priv }} $WAYPACK\n\n - name: Prepare coverage data\n run: |\n source .venv/bin/activate\n mkdir -p results\n .github/scripts/convert_dat.sh ${TEST_PATH}/coverage.dat results/coverage_${FULL_NAME}\n\n - name: Pack artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: regression_tests_coverage_data_cache_waypack_${{ env.FULL_NAME }}_${{ matrix.coverage }}\n path: results/*.info\n\n custom-regression-tests:\n name: Custom regression tests\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: centos:8\n strategy:\n matrix:\n bus: [\"axi\", \"ahb\"]\n test: [\"hello_world\", \"hello_world_dccm\", \"hello_world_iccm\", \"cmark\", \"cmark_dccm\", \"cmark_iccm\", \"dhry\", \"ecc\",\n \"csr_misa\", \"csr_access\", \"csr_mstatus\", \"csr_mseccfg\", \"modesw\", \"insns\", \"irq\", \"perf_counters\", \"pmp\", \"write_unaligned\",\n \"icache\", \"bitmanip\", \"read_after_read\"]\n priv: [\"0\", \"1\"]\n ecc: [\"0\", \"1\"]\n exclude:\n # These tests require user mode\n - priv: \"0\"\n test: \"csr_mseccfg\"\n - priv: \"0\"\n test: \"csr_access\"\n - priv: \"0\"\n test: \"csr_mstatus\"\n - priv: \"0\"\n test: \"modesw\"\n - priv: \"0\"\n test: \"insns\"\n - priv: \"0\"\n test: \"perf_counters\"\n # end tests which require user mode\n # These tests require AHB bus\n - bus: \"axi\"\n test: \"read_after_read\"\n # end tests which require AHB bus\n env:\n GHA_EXTERNAL_DISK: additional-tools\n GHA_SA: gh-sa-veer-uploader\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Run tests\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_custom_regression_tests_waypack\n TEST: ${{ matrix.test }}\n BUS: ${{ matrix.bus }}\n PRIV: ${{ matrix.priv }}\n ECC: ${{ matrix.ecc }}\n" }, { "path": ".github/workflows/test-regression-dcls.yml", "content": "name: Regression tests DCLS\n\non:\n workflow_call:\n\ndefaults:\n run:\n shell: bash\n\njobs:\n regression-tests:\n name: Regression tests\n runs-on: ubuntu-latest\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n strategy:\n matrix:\n bus: [\"axi\", \"ahb\"]\n # run some subset of regression tests on DCLS configutation\n test: [\"hello_world\", \"hello_world_dccm\", \"dhry\", \"ecc\",\n \"csr_misa\", \"csr_access\", \"csr_mstatus\", \"csr_mseccfg\", \"perf_counters\",\n \"icache\", \"bitmanip\"]\n coverage: [\"branch\"]\n priv: [\"0\", \"1\"]\n tb_extra_args: [\"--test-halt\"]\n exclude:\n # These tests require user mode\n - priv: \"0\"\n test: \"csr_mseccfg\"\n - priv: \"0\"\n test: \"csr_access\"\n - priv: \"0\"\n test: \"csr_mstatus\"\n - priv: \"0\"\n test: \"modesw\"\n - priv: \"0\"\n test: \"insns\"\n - priv: \"0\"\n test: \"perf_counters\"\n # end tests which require user mode\n include:\n # Use hello_world_iccm for testing '--test-lsu-clk-ratio'\n - test: \"hello_world_iccm\"\n bus: \"axi\"\n coverage: \"branch\"\n priv: \"0\"\n tb_extra_args: \"--test-halt --test-lsu-clk-ratio\"\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n CCACHE_DIR: \"/opt/regression/.cache/\"\n DCLS_ENABLE: \"1\"\n\n steps:\n - name: Install utils\n run: |\n echo \"deb http://archive.ubuntu.com/ubuntu/ noble main universe\" | sudo tee -a /etc/apt/sources.list > /dev/null\n echo \"debconf debconf/frontend select Noninteractive\" | sudo debconf-set-selections\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n git python3 python3-pip build-essential ninja-build ccache \\\n gcc-riscv64-unknown-elf\n pip3 install meson --break-system-packages\n\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install coverage dependencies\n run: |\n python3 -m venv .venv\n source .venv/bin/activate\n pip install -r .github/scripts/requirements-coverage.txt\n echo \"PATH=$PATH\" >> $GITHUB_ENV\n\n - name: Setup environment\n run: |\n echo \"/opt/verilator/bin\" >> $GITHUB_PATH\n RV_ROOT=`pwd`\n echo \"RV_ROOT=$RV_ROOT\" >> $GITHUB_ENV\n PYTHONUNBUFFERED=1\n echo \"PYTHONUNBUFFERED=$PYTHONUNBUFFERED\" >> $GITHUB_ENV\n TEST_PATH=$RV_ROOT/test_results\n echo \"TEST_PATH=$TEST_PATH\" >> $GITHUB_ENV\n\n - name: Run tests\n run: |\n export PATH=/opt/verilator/bin:$PATH\n export RV_ROOT=`pwd`\n export TB_EXTRA_ARGS=\"${{ matrix.tb_extra_args }}\"\n .github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.bus }} ${{ matrix.test}} ${{ matrix.coverage }} ${{ matrix.priv }} 0\n\n custom-regression-tests:\n name: Custom regression tests\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: centos:8\n strategy:\n matrix:\n bus: [\"axi\", \"ahb\"]\n # run some subset of regression tests on DCLS configutation\n test: [\"hello_world\", \"hello_world_dccm\", \"dhry\", \"ecc\",\n \"csr_misa\", \"csr_access\", \"csr_mstatus\", \"csr_mseccfg\", \"perf_counters\",\n \"icache\", \"bitmanip\"]\n priv: [\"0\", \"1\"]\n exclude:\n # These tests require user mode\n - priv: \"0\"\n test: \"csr_mseccfg\"\n - priv: \"0\"\n test: \"csr_access\"\n - priv: \"0\"\n test: \"csr_mstatus\"\n - priv: \"0\"\n test: \"modesw\"\n - priv: \"0\"\n test: \"insns\"\n - priv: \"0\"\n test: \"perf_counters\"\n # end tests which require user mode\n env:\n GHA_EXTERNAL_DISK: additional-tools\n GHA_SA: gh-sa-veer-uploader\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Run tests\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_dcls_regression\n DCLS_ENABLE: \"1\"\n TEST: ${{ matrix.test }}\n BUS: ${{ matrix.bus }}\n PRIV: ${{ matrix.priv }}\n" }, { "path": ".github/workflows/test-regression-exceptions.yml", "content": "name: Regression exceptions tests\n\non:\n workflow_call:\n\ndefaults:\n run:\n shell: bash\n\njobs:\n regression-tests:\n name: Regression exceptions tests\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n strategy:\n matrix:\n bus: [\"axi\"]\n test: [\"machine_external_ints\", \"dbus_store_error\", \"lsu_trigger_hit\", \"machine_external_vec_ints\", \"dside_pic_access_error\",\n \"iside_fetch_precise_bus_error\", \"dside_access_region_prediction_error\", \"cmark\", \"iside_core_local_unmapped_address_error\",\n \"dside_access_across_region_boundary\", \"nmi_pin_assertion\", \"dside_size_misaligned_access_to_non_idempotent_address\",\n \"dside_core_local_access_unmapped_address_error\", \"dbus_nonblocking_load_error\", \"internal_timer_ints\", \"ebreak_ecall\", \"illegal_instruction\",\n \"clk_override\", \"core_pause\"]\n coverage: [\"all\"]\n cache_waypack: [\"0\", \"1\"]\n priv: [\"0\"]\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n CCACHE_DIR: \"/opt/regression/.cache/\"\n\n steps:\n - name: Install utils\n run: |\n echo \"deb http://archive.ubuntu.com/ubuntu/ noble main universe\" | sudo tee -a /etc/apt/sources.list > /dev/null\n echo \"debconf debconf/frontend select Noninteractive\" | sudo debconf-set-selections\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n git python3 python3-pip build-essential ninja-build ccache \\\n gcc-riscv64-unknown-elf\n pip3 install meson --break-system-packages\n\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install coverage dependencies\n run: |\n python3 -m venv .venv\n source .venv/bin/activate\n pip install -r .github/scripts/requirements-coverage.txt\n echo \"PATH=$PATH\" >> $GITHUB_ENV\n\n - name: Setup environment\n run: |\n echo \"/opt/verilator/bin\" >> $GITHUB_PATH\n RV_ROOT=`pwd`\n echo \"RV_ROOT=$RV_ROOT\" >> $GITHUB_ENV\n PYTHONUNBUFFERED=1\n echo \"PYTHONUNBUFFERED=$PYTHONUNBUFFERED\" >> $GITHUB_ENV\n TEST_PATH=$RV_ROOT/test_results\n echo \"TEST_PATH=$TEST_PATH\" >> $GITHUB_ENV\n echo \"FULL_NAME=${{ matrix.bus }}-exceptions-${{ matrix.test }}-waypack${{ matrix.cache_waypack }}\" >> $GITHUB_ENV\n\n - name: Run tests\n run: |\n export PATH=/opt/verilator/bin:$PATH\n export RV_ROOT=`pwd`\n .github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.bus }} ${{ matrix.test}} ${{ matrix.coverage }} ${{ matrix.priv }} ${{ matrix.cache_waypack }}\n\n - name: Prepare coverage data\n run: |\n source .venv/bin/activate\n mkdir -p results\n .github/scripts/convert_dat.sh ${TEST_PATH}/coverage.dat \\\n results/coverage_${FULL_NAME}\n\n - name: Pack artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: regression_tests_coverage_data-${{ env.FULL_NAME }}_${{ matrix.coverage }}\n path: results/*.info\n\n custom-regression-exceptions-tests:\n name: Custom regression exceptions tests\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: centos:8\n env:\n GHA_EXTERNAL_DISK: additional-tools\n GHA_SA: gh-sa-veer-uploader\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Run tests\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_custom_regression_exceptions_tests\n" }, { "path": ".github/workflows/test-renode.yml", "content": "name: Renode tests\n\non:\n workflow_call:\n\njobs:\n tests:\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n strategy:\n fail-fast: false\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n steps:\n - name: Clone repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install dependencies\n run: |\n echo \"deb http://archive.ubuntu.com/ubuntu/ noble main universe\" | sudo tee -a /etc/apt/sources.list > /dev/null\n echo \"debconf debconf/frontend select Noninteractive\" | sudo debconf-set-selections\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n git python3 python3-dev python3-pip build-essential ninja-build ccache \\\n gcc-riscv64-unknown-elf\n pip3 install meson --break-system-packages\n\n - name: Build tests\n run: |\n export RV_ROOT=`pwd`\n cd ./tools/renode\n ./build-all-tests.sh\n\n - name: Run tests\n run: |\n cd ./tools/renode\n pip3 install -r /opt/renode/tests/requirements.txt --break-system-packages\n /opt/renode/renode-test veer.robot\n\n - name: Upload artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: renode_results\n path: |\n tools/renode/log.html\n tools/renode/report.html\n tools/renode/robot_output.xml\n" }, { "path": ".github/workflows/test-riscof.yml", "content": "name: RISCOF tests\n\non:\n workflow_call:\n\ndefaults:\n run:\n shell: bash\n\njobs:\n\n tests:\n name: Run RISCOF tests\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n strategy:\n fail-fast: false\n matrix:\n coverage: [\"all\"]\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n CCACHE_DIR: \"/opt/riscof/.cache/\"\n\n steps:\n - name: Install utils\n run: |\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n git ccache python3-minimal python3-pip device-tree-compiler \\\n build-essential ninja-build\n\n # ghcr.io/antmicro/cores-veer-el2:20250411084921 is ubuntu-22.04.5 which has a riscv toolchain\n # without the support for the Zicsr extension\n - name: Install cross-compiler\n run: |\n echo \"deb http://archive.ubuntu.com/ubuntu/ noble main universe\" | sudo tee -a /etc/apt/sources.list > /dev/null\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n gcc-riscv64-unknown-elf\n riscv64-unknown-elf-gcc --version\n\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install coverage dependencies\n run: |\n python3 -m venv .venv\n source .venv/bin/activate\n pip install -r .github/scripts/requirements-coverage.txt\n echo \"PATH=$PATH\" >> $GITHUB_ENV\n\n - name: Install RISCOF\n run: |\n pip3 install git+https://github.com/riscv/riscof@a25e315\n\n - name: Clone tests\n run: |\n mkdir -p riscof\n pushd riscof\n riscof --verbose info arch-test --clone\n popd\n\n - name: Skip tests\n run: |\n pushd riscof/riscv-arch-test/riscv-test-suite\n # This test accesses memory at address 0x0.\n # These accesses fail on Spike because it has a debug module in range [0x0; 0x1000).\n # VeeR doesn't have such restrictions, so they don't fail, which results in a test failure.\n rm -f rv32i_m/pmp/src/pmpm_cfg_A_tor_zero.S\n rm -f rv32i_m/pmp/src/pmpzca_misaligned_na4.S\n popd\n\n - name: Configure RISCOF\n run: |\n pushd riscof\n # Copy RISCOF configuration\n cp ../tools/riscof/config.ini ./\n cp -r ../tools/riscof/spike ./\n cp -r ../tools/riscof/veer ./\n # Build the test list\n riscof testlist --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env\n popd\n\n - name: Build VeeR model\n run: |\n export PATH=/opt/verilator/bin:$PATH\n export RV_ROOT=`pwd`\n pushd riscof\n VEER_OPTS=\"-set=user_mode=1 -set=smepmp=1\"\n make -f $RV_ROOT/tools/Makefile verilator-build CONF_PARAMS=\"-set build_axi4 $VEER_OPTS\" COVERAGE=${{ matrix.coverage }}\n popd\n\n - name: Run tests, collect coverage\n run: |\n export PATH=/opt/verilator/bin:/opt/spike/bin:$PATH\n pushd riscof\n riscof run --no-browser --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env\n mkdir -p coverage\n verilator_coverage -write ./coverage/coverage.dat `find ./riscof_work/ -type f -name \"coverage.dat\"`\n popd\n\n - name: Prepare coverage data\n run: |\n export PATH=/opt/verilator/bin:$PATH\n .github/scripts/convert_dat.sh riscof/coverage/coverage.dat \\\n riscof/coverage/coverage_riscof-m\n\n - name: Prepare report\n run: |\n PYTEST_STYLE_SRC_DIR=$(pwd)/.github/scripts/pytest/\n PYTEST_CSS=${PYTEST_STYLE_SRC_DIR}/css/styles.css\n pushd riscof/riscof_work\n bash ${PYTEST_STYLE_SRC_DIR}/style_pytest_report.sh ${PYTEST_STYLE_SRC_DIR} . report.html\n echo \"/* Custom CSS */\" >>style.css\n cat ${PYTEST_CSS} >>style.css\n popd\n\n - name: Pack artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: riscof_coverage_data_m_${{ matrix.coverage }}\n path: riscof/coverage/*.info\n\n - name: Pack artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: riscof-report_m_${{ matrix.coverage }}\n path: |\n riscof/riscof_work/report.html\n riscof/riscof_work/style.css\n riscof/riscof_work/assets\n riscof/riscof_work/script\n riscof/riscof_work/rv*\n !riscof/riscof_work/**/coverage.dat\n\n - name: Check failure\n run: |\n if res=$(grep -no riscof/riscof_work/report.html -e \"&2\n echo \"Check the report in artifacts for details.\" >&2\n exit 1\n fi\n" }, { "path": ".github/workflows/test-riscv-dv.yml", "content": "name: RISCV-DV tests\n\non:\n workflow_call:\n\ndefaults:\n run:\n shell: bash\n\nenv:\n ITERATIONS: 3\n SEED: 999\n\njobs:\n generate-config:\n name: Generate configs\n runs-on: ubuntu-24.04\n outputs:\n test-types: ${{ steps.test-types.outputs.tests }}\n test-include-generate: ${{ steps.test-types.outputs.include-generate }}\n test-include-run: ${{ steps.test-types.outputs.include-run }}\n test-include-run-custom: ${{ steps.test-types.outputs.include-run-custom }}\n # The same exclude can be used in both `run-tests` and `run-custom-tests` jobs cause they\n # exclude all matrix entries with matching keys regardless of other keys so it doesn't matter\n # that matrix in `run-tests` has twice the entries from `run-tests-custom` due to `coverage`.\n test-exclude-run: ${{ steps.test-types.outputs.exclude-run }}\n hash: ${{ steps.hash.outputs.files-hash }}\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n - id: test-types\n run: |\n python3 -m pip install pyyaml\n echo \"tests=$(python3 .github/scripts/riscv_dv_parse_testlist.py tools/riscv-dv/testlist.yaml)\" | tee -a $GITHUB_OUTPUT\n echo \"include-generate=$(python3 .github/scripts/riscv_dv_matrix_include.py generate)\" | tee -a $GITHUB_OUTPUT\n echo \"include-run=$(python3 .github/scripts/riscv_dv_matrix_include.py run-tests)\" | tee -a $GITHUB_OUTPUT\n echo \"include-run-custom=$(python3 .github/scripts/riscv_dv_matrix_include.py run-custom-tests)\" | tee -a $GITHUB_OUTPUT\n echo \"exclude-run=[ \\\n {'iss': 'renode', 'test': 'riscv_bitmanip_full_test_veer'}, \\\n {'iss': 'renode', 'test': 'riscv_bitmanip_balanced_test_veer'}, \\\n {'iss': 'renode', 'test': 'riscv_illegal_instr_test'}, \\\n {'iss': 'renode', 'test': 'riscv_hint_instr_test'}, \\\n {'iss': 'renode', 'test': 'riscv_ebreak_test', 'priv': 'mu'}, \\\n {'iss': 'renode', 'test': 'riscv_ebreak_debug_mode_test', 'priv': 'mu'} \\\n ]\" | tee -a $GITHUB_OUTPUT\n - id: hash\n run: |\n echo \"files-hash=$(.github/scripts/get_code_hash.sh)\" | tee -a $GITHUB_OUTPUT\n\n generate-code:\n name: Generate code for tests\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: centos:8\n needs: generate-config\n strategy:\n fail-fast: false\n matrix:\n test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}\n version: [ uvm ]\n include: ${{ fromJSON(needs.generate-config.outputs.test-include-generate) }}\n env:\n GHA_EXTERNAL_DISK: additional-tools\n CACHE_HASH: ${{ needs.generate-config.outputs.hash }}\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Prepare Environment\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_prepare_env\n\n - name: Generate code\n if: matrix.version == 'uvm'\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_generate_code\n RISCV_DV_TEST: ${{ matrix.test }}\n RISCV_DV_ITER: ${{ env.ITERATIONS }}\n RISCV_DV_SEED: ${{ env.SEED }}\n\n - name: Generate code (pyflow)\n if: matrix.version == 'pyflow'\n run: |\n export RV_ROOT=`realpath .`\n pushd tools/riscv-dv\n make -j`nproc` \\\n RISCV_DV_TEST=${{ matrix.test }} \\\n RISCV_DV_ITER=$ITERATIONS \\\n RISCV_DV_SEED=$SEED \\\n generate\n popd\n\n - name: Pack artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: riscv-dv_generated_code_${{ matrix.test }}_${{ matrix.version }}\n path: tools/riscv-dv/work/**/asm_test/*.S\n\n run-tests:\n name: Run RISC-V DV tests\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n needs: [ generate-config, generate-code ]\n strategy:\n fail-fast: false\n matrix:\n test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}\n iss:\n - spike\n - renode\n coverage: [\"all\"]\n version: [ uvm ]\n priv: [\"m\", \"mu\"]\n include: ${{ fromJSON(needs.generate-config.outputs.test-include-run) }}\n exclude: ${{ fromJSON(needs.generate-config.outputs.test-exclude-run) }}\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n CCACHE_DIR: \"/opt/riscv-dv/.cache/\"\n CACHE_HASH: ${{ needs.generate-config.outputs.hash }}\n\n steps:\n - name: Install utils\n run: |\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n git ccache device-tree-compiler python3-minimal python3-pip \\\n libboost-all-dev\n\n # As of July 9th, 2024 `ubuntu:latest` comes with riscv64-unknown-elf-gcc\n # 10.0.2. We need a newer version for bitmanip extension support.\n - name: Install cross-compiler\n run: |\n echo \"deb http://archive.ubuntu.com/ubuntu/ noble main universe\" | sudo tee -a /etc/apt/sources.list > /dev/null\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n gcc-riscv64-unknown-elf\n riscv64-unknown-elf-gcc --version\n\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install coverage dependencies\n run: |\n python3 -m venv .venv\n source .venv/bin/activate\n pip install -r .github/scripts/requirements-coverage.txt\n echo \"PATH=$PATH\" >> $GITHUB_ENV\n\n - name: Install Python deps\n run: |\n pip install -r third_party/riscv-dv/requirements.txt\n\n - name: Download Code Artifact\n uses: actions/download-artifact@v4\n with:\n name: riscv-dv_generated_code_${{ matrix.test }}_${{ matrix.version }}\n path: tools/riscv-dv/work/\n\n - name: Run test\n run: |\n ls tools/riscv-dv/work\n export FULL_NAME=riscv_dv-${{ matrix.test }}-${{ matrix.priv }}-${{ matrix.iss }}-${{ matrix.version }}\n export PATH=/opt/verilator/bin:$PATH\n export RV_ROOT=`realpath .`\n export RISCV_GCC=riscv64-unknown-elf-gcc\n export RISCV_OBJCOPY=riscv64-unknown-elf-objcopy\n export RISCV_NM=riscv64-unknown-elf-nm\n export SPIKE_PATH=/opt/spike/bin\n export RENODE_PATH=/opt/renode/renode\n\n echo \"FULL_NAME=${FULL_NAME}\" >> $GITHUB_ENV\n echo \"RV_ROOT=${RV_ROOT}\" >> ${GITHUB_ENV}\n echo \"PATH=${PATH}\" >> ${GITHUB_ENV}\n\n ${RISCV_GCC} --version\n\n pushd tools/riscv-dv\n make -j`nproc` \\\n RISCV_DV_TEST=${{ matrix.test }} \\\n RISCV_DV_ISS=${{ matrix.iss }} \\\n RISCV_DV_ITER=$ITERATIONS \\\n RISCV_DV_SEED=$SEED \\\n COVERAGE=${{ matrix.coverage }} \\\n RISCV_DV_PRIV=${{ matrix.priv }} \\\n run\n popd\n\n - name: Prepare coverage data\n run: |\n mkdir -p results\n\n for ((i=0; i> $GITHUB_ENV\n\n # To avoid compiling code and running ISS on CentOS, let's just get\n # compiled code and ISS logs from the artifacts of Verilator tests.\n - name: Download Code and ISS logs\n uses: actions/download-artifact@v4\n with:\n name: artifacts-${{ env.FULL_NAME }}-all\n path: verilator-artifacts\n\n - name: Move Code and ISS logs to workdir\n run: |\n SRC_DIR=verilator-artifacts/test_${{ matrix.test }}\n TEST_DIR=tools/riscv-dv/work/test_${{ matrix.test }}\n\n mkdir -p $TEST_DIR/asm_test\n cp $SRC_DIR/asm_test/*.hex $TEST_DIR/asm_test/\n cp -r $SRC_DIR/${{ matrix.iss }}_sim $TEST_DIR/\n rm -rf verilator-artifacts\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Prepare Environment\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_prepare_env\n\n - name: Perform custom tests\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_custom_riscv_dv\n RISCV_DV_ITER: ${{ env.ITERATIONS }}\n RISCV_DV_TEST: ${{ matrix.test }}\n RISCV_DV_PRIV: ${{ matrix.priv }}\n RISCV_DV_ISS: ${{ matrix.iss }}\n VERSION: ${{ matrix.version }}\n" }, { "path": ".github/workflows/test-uarch.yml", "content": "name: VeeR-EL2 Microarchitectural tests\n\non:\n workflow_call:\n\ndefaults:\n run:\n shell: bash\n\njobs:\n lint:\n name: Lint microarchitectural tests\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n steps:\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Setup environment\n run: |\n RV_ROOT=`pwd`\n echo \"RV_ROOT=$RV_ROOT\" >> $GITHUB_ENV\n PYTHONUNBUFFERED=1\n echo \"PYTHONUNBUFFERED=$PYTHONUNBUFFERED\" >> $GITHUB_ENV\n\n TEST_PATH=$RV_ROOT/verification/block\n echo \"TEST_PATH=$TEST_PATH\" >> $GITHUB_ENV\n\n python3 -m venv .venv\n source .venv/bin/activate\n python3 -m pip install nox\n - name: Lint\n run: |\n source .venv/bin/activate\n pushd ${TEST_PATH}\n nox -s test_lint\n popd\n tests:\n name: Microarchitectural tests\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n strategy:\n matrix:\n include:\n - test: \"block/pic\"\n artifact: \"block_pic\"\n - test: \"block/pic_gw\"\n artifact: \"block_pic_gw\"\n - test: \"block/dma\"\n artifact: \"block_dma\"\n - test: \"block/ifu_compress\"\n artifact: \"block_ifu_compress\"\n - test: \"block/ifu_mem_ctl\"\n artifact: \"block_ifu_mem_ctl\"\n - test: \"block/dec_tl\"\n artifact: \"block_dec_tl\"\n - test: \"block/dec_ib\"\n artifact: \"block_dec_ib\"\n - test: \"block/exu_alu\"\n artifact: \"block_exu_alu\"\n - test: \"block/exu_mul\"\n artifact: \"block_exu_mul\"\n - test: \"block/exu_div\"\n artifact: \"block_exu_div\"\n - test: \"block/iccm\"\n artifact: \"block_iccm\"\n - test: \"block/dccm\"\n artifact: \"block_dccm\"\n - test: \"block/lib_axi4_to_ahb\"\n artifact: \"block_lib_axi4_to_ahb\"\n - test: \"block/lib_ahb_to_axi4\"\n artifact: \"block_lib_ahb_to_axi4\"\n - test: \"block/pmp\"\n artifact: \"block_pmp\"\n - test: \"block/pmp_random\"\n artifact: \"block_pmp_random\"\n - test: \"block/dec_pmp_ctl\"\n artifact: \"block_dec_pmp_ctl\"\n - test: \"block/dmi\"\n artifact: \"block_dmi\"\n - test: \"block/lsu_tl\"\n artifact: \"block_lsu_tl\"\n - test: \"block/dec_tlu_ctl\"\n artifact: \"block_dec_tlu_ctl\"\n - test: \"block/dec\"\n artifact: \"block_dec\"\n - test: \"block/dcls\"\n artifact: \"block_dcls\"\n env:\n CCACHE_DIR: \"/opt/verification/.cache/\"\n DEBIAN_FRONTEND: \"noninteractive\"\n steps:\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install prerequisites\n run: |\n echo \"deb http://archive.ubuntu.com/ubuntu/ noble main universe\" | sudo tee -a /etc/apt/sources.list > /dev/null\n echo \"debconf debconf/frontend select Noninteractive\" | sudo debconf-set-selections\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n autoconf automake autotools-dev \\\n bc bison build-essential \\\n ccache curl \\\n flex \\\n gawk gcc-riscv64-unknown-elf git gperf \\\n help2man \\\n libexpat-dev libfl-dev libfl2 libgmp-dev \\\n libmpc-dev libmpfr-dev libpython3-all-dev libtool \\\n ninja-build \\\n patchutils python3 python3-dev python3-pip \\\n texinfo \\\n zip zlib1g zlib1g-dev \\\n libbit-vector-perl\n\n - name: Install coverage dependencies\n run: |\n python3 -m venv .venv\n source .venv/bin/activate\n pip install -r .github/scripts/requirements-coverage.txt\n python3 -m pip install meson nox\n\n - name: Setup environment\n run: |\n echo \"/opt/verilator/bin\" >> $GITHUB_PATH\n RV_ROOT=`pwd`\n echo \"RV_ROOT=$RV_ROOT\" >> $GITHUB_ENV\n PYTHONUNBUFFERED=1\n echo \"PYTHONUNBUFFERED=$PYTHONUNBUFFERED\" >> $GITHUB_ENV\n\n TEST_TYPE=`echo ${{ matrix.test }} | cut -d'/' -f1`\n TEST_NAME=`echo ${{ matrix.test }} | cut -d'/' -f2`\n TEST_PATH=$RV_ROOT/verification/${TEST_TYPE}\n\n echo \"TEST_TYPE=$TEST_TYPE\" >> $GITHUB_ENV\n echo \"TEST_NAME=$TEST_NAME\" >> $GITHUB_ENV\n echo \"TEST_PATH=$TEST_PATH\" >> $GITHUB_ENV\n\n # Fix random generator seed\n echo \"RANDOM_SEED=1377424946\" >> $GITHUB_ENV\n\n - name: Run ${{ matrix.test }}\n run: |\n source .venv/bin/activate\n pushd ${TEST_PATH}\n nox -s ${TEST_NAME}_verify\n popd\n zip verification/${{ matrix.test }}/dump.vcd.zip verification/${{ matrix.test }}/dump.vcd\n\n - name: Prepare coverage data\n run: |\n shopt -s extglob\n export PATH=/opt/verilator/bin:$PATH\n source .venv/bin/activate\n\n mkdir -p results\n for FILE in ${TEST_PATH}/${TEST_NAME}/*.dat; do\n .github/scripts/convert_dat.sh \"${FILE}\" \"results/$(basename \"${FILE%_@(all|branch|toggle).dat}\")\"\n done\n\n # Prefix coverage results\n pushd results\n for OLD_NAME in *.info; do\n # e.g. coverage_uarch-dma-ecc_line.info instead of coverage_test_ecc_line.info\n NEW_NAME=${OLD_NAME/coverage_/coverage_uarch-${TEST_NAME}-}\n NEW_NAME=${NEW_NAME/test_/}\n echo \"renaming '${OLD_NAME}' to '${NEW_NAME}'\"\n mv ${OLD_NAME} ${NEW_NAME}\n done\n popd\n\n - name: Upload coverage data artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: uarch_tests_coverage_data-${{ matrix.artifact }}\n path: ./results/*.info\n\n - name: Upload test logs\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: uarch_tests_logs-${{ matrix.artifact }}\n path: |\n verification/${{ matrix.test }}/*.log\n verification/${{ matrix.test }}/*.vcd.zip\n\n custom_tests:\n name: Run custom Microarchitectural tests\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: centos:8\n strategy:\n matrix:\n test:\n - \"block/pic\"\n - \"block/pic_gw\"\n - \"block/dma\"\n - \"block/ifu_compress\"\n - \"block/ifu_mem_ctl\"\n - \"block/dec_tl\"\n - \"block/dec_ib\"\n - \"block/exu_alu\"\n - \"block/exu_mul\"\n - \"block/exu_div\"\n - \"block/iccm\"\n - \"block/dccm\"\n - \"block/lib_axi4_to_ahb\"\n - \"block/lib_ahb_to_axi4\"\n - \"block/pmp\"\n - \"block/pmp_random\"\n - \"block/dec_pmp_ctl\"\n - \"block/dmi\"\n - \"block/lsu_tl\"\n - \"block/dec_tlu_ctl\"\n - \"block/dec\"\n env:\n GHA_EXTERNAL_DISK: additional-tools\n GHA_SA: gh-sa-veer-uploader\n TEST: ${{ matrix.test }}\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Perform custom tests\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_custom_uarch\n TEST: ${{ matrix.test }}\n\n" }, { "path": ".github/workflows/test-uvm.yml", "content": "name: VeeR-EL2 verification\n\non:\n workflow_call:\n\njobs:\n tests:\n name: UVM tests\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n env:\n CCACHE_DIR: \"/opt/uvm/.cache/\"\n DEBIAN_FRONTEND: \"noninteractive\"\n steps:\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install prerequisities\n run: |\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n git build-essential ccache\n\n - name: Setup environment\n run: |\n echo \"/opt/verilator/bin\" >> $GITHUB_PATH\n RV_ROOT=`pwd`\n echo \"RV_ROOT=$RV_ROOT\" >> $GITHUB_ENV\n PYTHONUNBUFFERED=1\n echo \"PYTHONUNBUFFERED=$PYTHONUNBUFFERED\" >> $GITHUB_ENV\n\n - name: Build UVM testbench\n run: |\n make -C testbench/uvm/mem build -j$(nproc)\n\n - name: Run UVM testbench\n run: |\n make -C testbench/uvm/mem simulate | tee test.out\n\n - name: Upload test output\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: uvm_test_output\n path: test.out\n" }, { "path": ".github/workflows/test-verification.yml", "content": "name: VeeR-EL2 verification\n\non:\n workflow_call:\n\ndefaults:\n run:\n shell: bash\n\njobs:\n tests:\n name: Verification tests\n runs-on: ubuntu-24.04\n container: ghcr.io/antmicro/cores-veer-el2:20250411084921\n strategy:\n matrix:\n bus: [\"ahb\", \"axi\"]\n test: [\"test_pyuvm\"]\n coverage: [\"all\"]\n env:\n DEBIAN_FRONTEND: \"noninteractive\"\n CCACHE_DIR: \"/opt/regression/.cache/\"\n FULL_NAME: \"${{ matrix.bus }}-verification-${{ matrix.test }}\"\n steps:\n - name: Setup repository\n uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Install prerequisities\n run: |\n echo \"deb http://archive.ubuntu.com/ubuntu/ noble main universe\" | sudo tee -a /etc/apt/sources.list > /dev/null\n echo \"debconf debconf/frontend select Noninteractive\" | sudo debconf-set-selections\n sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \\\n autoconf automake autotools-dev \\\n bc bison build-essential \\\n ccache curl \\\n flex \\\n gawk gcc-riscv64-unknown-elf git gperf \\\n help2man \\\n libexpat-dev libfl-dev libfl2 libgmp-dev \\\n libmpc-dev libmpfr-dev libpython3-all-dev libtool \\\n ninja-build \\\n patchutils python3 python3-dev python3-pip \\\n texinfo \\\n zlib1g zlib1g-dev \\\n libbit-vector-perl\n \n - name: Install coverage dependencies\n run: |\n python3 -m venv .venv\n source .venv/bin/activate\n pip install -r .github/scripts/requirements-coverage.txt\n\n - name: Setup environment\n run: |\n echo \"/opt/verilator/bin\" >> $GITHUB_PATH\n RV_ROOT=`pwd`\n echo \"RV_ROOT=$RV_ROOT\" >> $GITHUB_ENV\n PYTHONUNBUFFERED=1\n echo \"PYTHONUNBUFFERED=$PYTHONUNBUFFERED\" >> $GITHUB_ENV\n TEST_PATH=$RV_ROOT/verification/top/${{ matrix.test }}\n echo \"TEST_PATH=$TEST_PATH\" >> $GITHUB_ENV\n echo \"HTML_FILE=${FULL_NAME}_${{ matrix.coverage }}.html\" >> $GITHUB_ENV\n\n\n - name: Run ${{ matrix.test }}\n run: |\n source .venv/bin/activate\n pip3 install meson\n pip3 install -r $RV_ROOT/verification/top/requirements.txt\n PYTEST_STYLE_SRC_DIR=$RV_ROOT/.github/scripts/pytest/\n PYTEST_CSS=${PYTEST_STYLE_SRC_DIR}/css/styles.css\n if [ ${{ matrix.bus }} = axi ]; then\n CONF_PARAMS='-set build_axi4'\n else\n CONF_PARAMS='-set build_ahb_lite'\n fi\n pushd ${TEST_PATH}\n python3 -m pytest ${{ matrix.test }}.py -sv --coverage=${{ matrix.coverage }} --html=$HTML_FILE --md=$GITHUB_STEP_SUMMARY --css=$PYTEST_CSS --conf_params=\"$CONF_PARAMS\"\n bash ${PYTEST_STYLE_SRC_DIR}/style_pytest_report.sh ${PYTEST_STYLE_SRC_DIR} ${TEST_PATH} ${HTML_FILE}\n popd\n\n - name: Prepare pytest-html data\n run: |\n source .venv/bin/activate\n pushd $RV_ROOT\n WEBPAGE_DIR=webpage_${FULL_NAME}_${{ matrix.coverage }}\n mkdir -p $WEBPAGE_DIR\n mv ${TEST_PATH}/$HTML_FILE $WEBPAGE_DIR\n mv ${TEST_PATH}/assets $WEBPAGE_DIR\n JS_SCRIPT_DIR=$RV_ROOT/.github/scripts/pytest/script\n mv $JS_SCRIPT_DIR $WEBPAGE_DIR\n popd\n\n - name: Prepare coverage data\n run: |\n source .venv/bin/activate\n export PATH=/opt/verilator/bin:$PATH\n mkdir -p results\n .github/scripts/convert_dat.sh ${TEST_PATH}/coverage.dat \\\n results/coverage_${FULL_NAME/test_/}\n\n - name: Upload pytest-html artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: verification_dashboard_${{ env.FULL_NAME }}_${{ matrix.coverage }}\n path: webpage_*\n\n - name: Upload coverage artifacts\n if: always()\n uses: actions/upload-artifact@v4\n with:\n name: verification_tests_coverage_data_${{ env.FULL_NAME }}_${{ matrix.coverage }}\n path: results/*.info\n\n custom-verification-tests:\n name: Custom verification tests\n runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]\n container: centos:8\n strategy:\n matrix:\n bus: [\"axi\", \"ahb\"]\n test: [\"test_pyuvm\"]\n env:\n GHA_EXTERNAL_DISK: additional-tools\n GHA_SA: gh-sa-veer-uploader\n steps:\n - uses: actions/checkout@v4\n with:\n submodules: recursive\n\n - name: Set secrets version\n run: echo \"SECRETS_VERSION=`cat .github/scripts/secrets_version`\" >> $GITHUB_ENV\n\n - name: Run tests\n run: _secret_combined_${{ env.SECRETS_VERSION }}\n env:\n SECRET_NAME: _secret_custom_verification_tests\n TEST: ${{ matrix.test }}\n BUS: ${{ matrix.bus }}\n" }, { "path": ".github/workflows/verible-format.yml", "content": "name: Verible formatter\n\non:\n pull_request_target:\n\njobs:\n format-review:\n runs-on: ubuntu-24.04\n permissions:\n checks: write\n contents: read\n pull-requests: write\n steps:\n - uses: actions/checkout@v4\n with:\n ref: ${{ github.event.pull_request.head.sha }}\n - uses: antmicro/verible-formatter-action@update-upload-action\n with:\n github_token: ${{ secrets.GITHUB_TOKEN }}\n reviewdog_reporter: 'local'\n fail_on_formatting_suggestions: ${{ github.event_name != 'pull_request_target' }}\n" }, { "path": ".github/workflows/verible-lint.yml", "content": "name: Verible linter\n\non:\n pull_request_target:\n\njobs:\n lint-review:\n runs-on: ubuntu-24.04\n permissions:\n checks: write\n contents: read\n pull-requests: write\n steps:\n - uses: actions/checkout@v4\n with:\n ref: ${{ github.event.pull_request.head.sha }}\n - uses: chipsalliance/verible-linter-action@main\n with:\n github_token: ${{ secrets.GITHUB_TOKEN }}\n reviewdog_reporter: 'local'\n extra_args: '--waiver_files=./violations.waiver'\n paths: |\n ./design\n\n" }, { "path": ".gitignore", "content": "configs/snapshots\nwork\nobj_dir\n*.vcd\n*.csv\n*.log\n*.exe\n*.swp\n*.sym\nverilator-build\nprogram.hex\nsnapshots\n__pycache__\nsim_build\nsim-build*\nvenv\nresults.xml\nverification/sim\nverilator-cocotb-build\n*.dat\n*.xml\n*.json\ntools/renode/renode_run\ntools/renode/build\ntools/renode/*.elf\ntools/renode/.venv\ndocs/build\n" }, { "path": ".gitmodules", "content": "[submodule \"third-party/picolibc\"]\n\tpath = third_party/picolibc\n\turl = https://github.com/picolibc/picolibc\n[submodule \"third_party/riscv-dv\"]\n\tpath = third_party/riscv-dv\n\turl = https://github.com/chipsalliance/riscv-dv\n[submodule \"third_party/cocotb\"]\n\tpath = third_party/cocotb\n\turl = https://github.com/cocotb/cocotb\n" }, { "path": "LICENSE", "content": "Apache License\nVersion 2.0, January 2004\nhttp://www.apache.org/licenses/\n\nTERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION\n\n1. Definitions.\n\n\"License\" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document.\n\n\"Licensor\" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License.\n\n\"Legal Entity\" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. 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You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License.\n\n8. Limitation of Liability.\n\nIn no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages.\n\n9. Accepting Warranty or Additional Liability.\n\nWhile redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.\n" }, { "path": "MAINTAINERS.md", "content": "# Maintainers\n\n* [Maciej Kurc](https://github.com/mkurc-ant)\n* [Tomasz Michalak](https://github.com/tmichalak)\n* [Karol Gugala](https://github.com/kgugala)\n" }, { "path": "README.md", "content": "\n \n \n\n \n \n\n \n \n\n\n# VeeR EL2 RISC-V Core\n\nThis repository contains the VeeR EL2 RISC-V Core design RTL.\n\n## License\n\nBy contributing to this project, you agree that your contribution is governed by [Apache-2.0](LICENSE). \nFiles under the [tools](tools/) directory may be available under a different license. Please review individual files for details.\n\n## Directory Structure\n\n ├── configs # Configurations Dir\n │   └── snapshots # Where generated configuration files are created\n ├── design # Design root dir\n │   ├── dbg # Debugger\n │   ├── dec # Decode, Registers and Exceptions\n │   ├── dmi # DMI block\n │   ├── exu # EXU (ALU/MUL/DIV)\n │   ├── ifu # Fetch & Branch Prediction\n │   ├── include \n │   ├── lib\n │   └── lsu # Load/Store\n ├── docs\n ├── tools # Scripts/Makefiles\n └── testbench # (Very) simple testbench\n    ├── asm # Example assembly files\n    ├── hex # Canned demo hex files\n    └── tests # Example tests\n \n## Dependencies\n\n- Verilator **(4.106 or later)** must be installed on the system if running with Verilator\n- If adding/removing instructions, [`espresso`](https://github.com/chipsalliance/espresso/tree/master) must be installed (used by `tools/coredecode`). Remember to checkout on `3.x` branch.\n- RISCV tool chain (based on gcc version 8.3 or higher) must be installed so that it can be used to prepare RISCV binaries to run.\n- [**Verible**](https://github.com/chipsalliance/verible) is used for SystemVerilog linting and formatting.\n- **Python 3.10+** is required for verification, documentation, and linting.\n\n### Python Environment Setup\n\nIt is recommended to use a virtual environment (venv) or Conda to manage Python dependencies.\n\n#### Using `venv`\n```bash\n# Create a virtual environment\npython3 -m venv .venv\n\n# Activate it\nsource .venv/bin/activate\n\n# Install all project dependencies\npip install -r requirements.txt\n```\n\n#### Using `Conda`\n```bash\n# Create a conda environment\nconda create -n veer-el2 python=3.12\n\n# Activate it\nconda activate veer-el2\n\n# Install dependencies\npip install -r requirements.txt\n```\n\n## Quickstart guide\n\n1. Clone the repository, clone submodules with `git submodule update --init --recursive`\n1. Setup `RV_ROOT` to point to the path in your local filesystem\n1. Determine your configuration (optional)\n1. Run `make` with `tools/Makefile`\n\n## Release Notes for this version\n\nPlease see [release notes](release-notes.md) for changes and bug fixes in this version of VeeR.\n\n### Configurations\n\nVeeR can be configured by running the `$RV_ROOT/configs/veer.config` script:\n\n`% $RV_ROOT/configs/veer.config -h` for detailed help options\n\nFor example to build with a DCCM of size 64 Kb: \n\n`% $RV_ROOT/configs/veer.config -dccm_size=64` \n\nThis will update the **default** snapshot in `./snapshots/default/` with parameters for a 64K DCCM. \n\nAdd `-snapshot=dccm64`, for example, if you wish to name your build snapshot `dccm64` and refer to it during the build. \n\nThere are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via \nthe `-target=name` option to `veer.config`. **Note:** that the `typical_pd` target is what we base our published PPA numbers. It does not include an ICCM.\n\n**Building an FPGA speed optimized model:**\nUse ``-fpga_optimize=1`` option to ``veer.config`` to build a model that removes clock gating logic from flop model so that the FPGA builds can run at higher speeds. **This is now the default option for targets other than ``typical_pd``.**\n\n**Building a Power optimized model (ASIC flows):**\nUse ``-fpga_optimize=0`` option to ``veer.config`` to build a model that **enables** clock gating logic into the flop model so that the ASIC flows get a better power footprint. **This is now the default option for target``typical_pd``.**\n\nThis script derives the following consistent set of include files:\n\n ./snapshots/default\n ├── common_defines.vh # `defines for testbench or design\n ├── defines.h # #defines for C/assembly headers\n ├── el2_param.vh # Design parameters\n ├── el2_pdef.vh # Parameter structure\n ├── pd_defines.vh # `defines for physical design\n ├── perl_configs.pl # Perl %configs hash for scripting\n ├── pic_map_auto.h # PIC memory map based on configure size\n └── whisper.json # JSON file for veer-iss\n └── link.ld # default linker control file\n\n### Building a model\n\nWhile in a work directory:\n\n1. Set the `RV_ROOT` environment variable to the root of the VeeR directory structure.\n\n Example for bash shell: `export RV_ROOT=/path/to/veer` \n Example for csh or its derivatives: `setenv RV_ROOT /path/to/veer`\n \n1. Create your specific configuration\n\n *(Skip if default is sufficient)* \n *(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)* \n\n For example if `mybuild` is the name for the snapshot:\n\n `$RV_ROOT/configs/veer.config [configuration options..] -snapshot=mybuild` \n \n Snapshots are placed in the `./snapshots` directory\n\n1. Run a simple Hello World program (Verilator)\n\n ```shell\n make -f $RV_ROOT/tools/Makefile\n ```\n\nThis command will build a Verilator model of VeeR EL2 with the AXI bus, and\nexecute a short sequence of instructions that writes out \"HELLO WORLD\"\nto the bus.\n\nThe simulation produces output on the screen like:\n\n```\nVerilatorTB: Start of sim\n\n-------------------------\nHello World from VeeR EL2\n-------------------------\nTEST_PASSED\n\nFinished : minstret = 437, mcycle = 922\nSee \"exec.log\" for execution trace with register updates..\n\n```\nThe simulation generates the following files:\n\n* `console.log` contains what the cpu writes to the console address of 0xd0580000. \n* `exec.log` shows instruction trace with GPR updates. \n* `trace_port.csv` contains a log of the trace port. \n\nWhen `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by gtkwave or similar waveform viewers.\n \nYou can re-execute the simulation using:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile verilator\n```\n\nThe simulation run/build command has following generic form:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile [] [debug=1] [snapshot=mybuild] [target=] [TEST=] [TEST_DIR=]\n```\n\nwhere:\n\n``` \n - can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa\n 'riviera'- Aldec Riviera-PRO. if not provided, 'make' cleans work directory, builds verilator executable and runs a test.\ndebug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option.\nassert=1 - enables assertions in simulation runs (with simulators other than Verilator)\n - predefined CPU configurations 'default' ( by default), 'default_ahb', 'typical_pd', 'high_perf' \nTEST - allows to run a C (.c) or assembly (.s) test, hello_world is run by default \nTEST_DIR - alternative to test source directory testbench/asm or testbench/tests\n - run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument \n for runs on custom configurations.\nCONF_PARAMS - allows to provide -set options to veer.conf script to alter predefined EL2 targets parameters\n```\n\nExample:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile verilator TEST=cmark\n```\n\nwill build and simulate the `testbench/asm/cmark.c` program with Verilator.\n\nIf you want to compile a test only, you can run:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile program.hex TEST= [TEST_DIR=/path/to/dir]\n```\n\nThe Makefile uses the `snapshot//link.ld` file, generated by the `veer.conf` script by default to build the test executable.\nUser can provide test specific linker file in form `.ld` to build the test executable,\nin the same directory with the test source.\n\nUser also can create a test-specific Makefile in `.makefile`, containing building instructions\nhow to create the `program.hex` file used by simulation. The private Makefile should be in the same directory\nas the test source. See examples in the `testbench/asm` directory.\n\nAnother way to alter test building process is to use `.mki` file in test source directory. It may help to select multiple sources\nto compile and/or alter compilation swiches. See examples in the `testbench/tests/` directory\n \n*(the `program.hex` file is loaded to instruction and LSU bus memory slaves and optionally to DCCM/ICCM at the beginning of simulation)*.\n\nUser can build the `program.hex` file by any other means and then run simulation with the following command:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile \n```\n\nNote: You may need to delete the `program.hex` file from the work directory, when running a new test.\n\nThe `$RV_ROOT/testbench/asm` directory contains the following tests ready to simulate:\n\n```\nhello_world - default test program to run, prints Hello World message to screen and console.log\nhello_world_dccm - the same as above, but takes the string from preloaded DCCM.\nhello_world_iccm - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes\n it from there. Runs on EL2 with AXI4 buses only. \ncmark - coremark benchmark running with code and data in external memories\ncmark_dccm - the same as above, running data and stack from DCCM (faster)\ncmark_iccm - the same as above with preloaded code to ICCM (slower, optimized for size to fit into default ICCM). \n\ndhry - Run dhrystone. (Scale by 1757 to get DMIPS/MHZ)\n```\n\nThe `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISC-V SW tools are not installed.\n\n**Note**: The testbench has a simple synthesizable bridge that allows you to load the ICCM via load/store instructions. This is only supported for AXI4 builds.\n" }, { "path": "cm.cfg", "content": "+tree tb_top.rvtop_wrapper.rvtop\n\n////////////////////////////////// MAIN CORE //////////////////////////////////\n///////////////////////////////////////////////////////////////////////////////\n\n//////////////////////////////// rvrangecheck /////////////////////////////////\n// 'start_addr' and 'region' are tied to module parameters\n-node tb_top.rvtop_wrapper.rvtop.veer*rangecheck.start_addr\n-node tb_top.rvtop_wrapper.rvtop.veer*rangecheck.region\n\n////////////////////////////// el2_veer_wrapper ///////////////////////////////\n-node tb_top.rvtop_wrapper.rvtop.unused_dmi_hard_reset\n-node tb_top.rvtop_wrapper.rvtop.trace_rv_i_address_ip[0]\n\n/////////////////////////////////// el2_veer //////////////////////////////////\n-node tb_top.rvtop_wrapper.rvtop.veer.trace_rv_i_address_ip[0]\n-node tb_top.rvtop_wrapper.rvtop.veer.trace_rv_trace_pkt.trace_rv_i_address_ip[0]\n-node tb_top.rvtop_wrapper.rvtop.veer.*hprot[3:1] // Tied to 3'001\n\n/////////////////////////////////// el2_dbg ///////////////////////////////////\n// Tied to '0\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.abstractcs_reg[31:13]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.abstractcs_reg[11]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.abstractcs_reg[7:4]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmcontrol_reg[29]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmcontrol_reg[27:2]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[31:20]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[15:14]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[6:4]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.haltsum0_reg[31:1]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[31:30]\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[28:23]\n\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[7] // Tied to '1\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[3:0] // Tied to 4'h2\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.abstractcs_reg[3:0] // Tied to 4'h2\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[29] // Tied to '1\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[11:5] // Tied to 7'h20\n-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[4:0] // Tied to 5'b01111\n\n/////////////////////////////////// el2_exu ///////////////////////////////////\n-node tb_top.rvtop_wrapper.rvtop.veer.exu.i_mul.crc32_poly_rev // Tied to 32'hEDB88320\n-node tb_top.rvtop_wrapper.rvtop.veer.exu.i_mul.crc32c_poly_rev // Tied to 32'h82F63B78\n\n////////////////////////////////// rvjtag_tap /////////////////////////////////\n-node tb_top.rvtop_wrapper.rvtop.dmi_wrapper.i_jtag_tap.abits // Tied to AWID[5:0]\n\n///////////////////////////////// dec_tlu_ctl /////////////////////////////////\n// Tied to '0\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr[14]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr[9]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr[5:4]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr_ns[14]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr_ns[9]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr_ns[5:4]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.ifu_mscause[2]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mcgc[6]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mcgc_int[6]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mcgc_ns[6]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mcountinhibit[1]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mepc_rf[0]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[31]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[27:12]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[10:8]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[6:4]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[2:0]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mip_rf[27:12]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mip_rf[10:8]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mip_rf[6:4]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mip_rf[2:0]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[31:17]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[15:12]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[10:8]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[6:4]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[2:0]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[26]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[18:13]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[10:8]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[5:3]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtvec_rf[1]\n\n/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////\n// Tied to '0\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.*pmpcfg_ff.din[6:5]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.*pmpcfg_ff.dout[6:5]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.*csr_wdata[6:5]\n\n// Aggregation of four 'el2_pmp_cfg_pkt_t' entries\n// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[30:29]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[22:21]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[14:13]\n-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[6:5]\n\n//////////////////////////// el2_ifu_compress_ctl /////////////////////////////\n// Tied to '0\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[31]\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[29:21]\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[19:15]\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[11:7]\n\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[1:0] // Tied to 2'b11\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l1[1:0] // Tied to o[1:0] (2'b11)\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l2[1:0] // Tied to l1[1:0] (2'b11)\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l3[1:0] // Tied to l2[1:0] (2'b11)\n\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l1[31] // Tied to o[31] ('0)\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l1[29:25] // Tied to o[29:25] ('0)\n\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.rdpd[4:3] // Tied to 2'01\n-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.rs2pd[4:3] // Tied to 2'01\n\n////////////////////////////////// LOCKSTEP ///////////////////////////////////\n///////////////////////////////////////////////////////////////////////////////\n\n//////////////////////////////// rvrangecheck /////////////////////////////////\n// 'start_addr' and 'region' are tied to module parameters\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core*rangecheck.start_addr\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core*rangecheck.region\n\n////////////////////////////// el2_veer_lockstep //////////////////////////////\n-node tb_top.rvtop_wrapper.rvtop.lockstep.trace_rv_i_address_ip[0]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.*trace_rv_i_address_ip[0]\n\n/////////////////////////////////// el2_veer //////////////////////////////////\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.trace_rv_i_address_ip[0]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.trace_rv_trace_pkt.trace_rv_i_address_ip[0]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.*hprot[3:1] // Tied to 3'001\n\n/////////////////////////////////// el2_dbg ///////////////////////////////////\n// Tied to '0\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[31:13]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[11]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[7:4]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmcontrol_reg[29]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmcontrol_reg[27:2]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[31:20]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[15:14]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[6:4]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.haltsum0_reg[31:1]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[31:30]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[28:23]\n\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[7] // Tied to '1\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[3:0] // Tied to 4'h2\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[3:0] // Tied to 4'h2\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[29] // Tied to '1\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[11:5] // Tied to 7'h20\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[4:0] // Tied to 5'b01111\n\n/////////////////////////////////// el2_exu ///////////////////////////////////\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.exu.i_mul.crc32_poly_rev // Tied to 32'hEDB88320\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.exu.i_mul.crc32c_poly_rev // Tied to 32'h82F63B78\n\n///////////////////////////////// dec_tlu_ctl /////////////////////////////////\n// Tied to '0\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr[14]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr[9]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr[5:4]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr_ns[14]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr_ns[9]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr_ns[5:4]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.ifu_mscause[2]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcgc[6]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcgc_int[6]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcgc_ns[6]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcountinhibit[1]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mepc_rf[0]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[31]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[27:12]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[10:8]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[6:4]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[2:0]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[27:12]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[10:8]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[6:4]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[2:0]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[31:17]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[15:12]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[10:8]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[6:4]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[2:0]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[26]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[18:13]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[10:8]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[5:3]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtvec_rf[1]\n\n/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////\n// Tied to '0\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.*pmpcfg_ff.din[6:5]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.*pmpcfg_ff.dout[6:5]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.*csr_wdata[6:5]\n\n// Aggregation of four 'el2_pmp_cfg_pkt_t' entries\n// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[30:29]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[22:21]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[14:13]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[6:5]\n\n//////////////////////////// el2_ifu_compress_ctl /////////////////////////////\n// Tied to '0\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[31]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[29:21]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[19:15]\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[11:7]\n\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[1:0] // Tied to 2'b11\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l1[1:0] // Tied to o[1:0] (2'b11)\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l2[1:0] // Tied to l1[1:0] (2'b11)\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l3[1:0] // Tied to l2[1:0] (2'b11)\n\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l1[31] // Tied to o[31] ('0)\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l1[29:25] // Tied to o[29:25] ('0)\n\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.rdpd[4:3] // Tied to 2'01\n-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.rs2pd[4:3] // Tied to 2'01\n" }, { "path": "configs/README.md", "content": "# VeeR EL2 RISC-V Core\n\n## Configuration\n\n### Contents\nName | Description\n---------------------- | ------------------------------\nVeeR.config | Configuration script for VeeR-EL2\nveer_config_gen.py | Python wrapper to run veer.config, used by VeeRVolf\n\n\nThis script will generate a consistent set of `defines/#defines/parameters` needed for the design and testbench.\nA perl hash (*perl_configs.pl*) and a JSON format for VeeR-iss are also generated.\nThis set of include files :\n\n ./snapshots/\n ├── common_defines.vh # `defines for testbench\n ├── defines.h # #defines for C/assembly headers\n ├── el2_param.vh # Actual Design parameters\n ├── el2_pdef.vh # Parameter structure definition\n ├── pd_defines.vh # `defines for physical design\n ├── perl_configs.pl # Perl %configs hash for scripting\n ├── pic_map_auto.h # PIC memory map based on configure size\n ├── whisper.json # JSON file for veer-iss\n └── link.ld # Default linker file for tests\n\n\n\nWhile the defines may be modified by hand, it is recommended that this script be used to generate a consistent set.\n\n### Targets\nThere are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to veer.config.\n\nTarget | Description\n---------------------- | ------------------------------\ndefault | Default configuration. AXI4 bus interface\ndefault_ahb | Default configuration, AHB-Lite bus interface\ntypical_pd | No ICCM, AXI4 bus interface\nhigh_perf | Large BTB/BHT, AXI4 interface\n\n\n`veer.config` may be edited to add additional target configurations, or new configurations may be created via the command line `-set` or `-unset` options.\n\n**Run `$RV_ROOT/configs/veer.config -h` for options and settable parameters.**\n" }, { "path": "configs/veer.config", "content": "#! /usr/bin/env perl\n\nuse strict; # Do not turn this off or else\nuse Data::Dumper;\nuse Getopt::Long;\nuse Bit::Vector;\nuse lib \"$ENV{RV_ROOT}/tools\";\nuse JSON;\n\nmy ($self) = $0 =~ m/.*\\/(\\w+)/o;\nmy @argv_orig = @ARGV;\n\n\n# Master configuration file\n#\n# Configuration is perl hash\n# Output are define files for various flows\n# Verilog (`defines common to RTL/TB)\n# Software (#defines)\n# Whisper (JSON/#defines)\n#\n# Default values and valid ranges should be specified\n# Can be overridden via the cmd line (-set=name=value-string)\n#\n# Format of the hash is\n# name => VALUE | LIST | HASH\n#\n# Special name \"inside\" followed by list .. values must be one of provided list\n# Special name \"derive\" followed by equation to derive\n#\n\n# Dump verilog/assembly macros in upper case\nmy $defines_case = \"U\";\n\n# Include these macros in verilog (pattern matched)\nmy @verilog_vars = qw (xlen config_key reset_vec tec_rv_icg numiregs nmi_vec target protection.* testbench.* dccm.* retstack core.* iccm.* btb.* bht.* icache.* pic.* regwidth memmap bus.* tech_specific_.* user_.*);\n\n# Include these macros in assembly (pattern matched)\nmy @asm_vars = qw (xlen reset_vec nmi_vec target dccm.* iccm.* pic.* memmap testbench.* protection.* core.*);\nmy @asm_overridable = qw (reset_vec nmi_vec serialio external_data) ;\n\n# Include these macros in PD (pattern matched)\nmy @pd_vars = qw (physical retstack target btb.* bht.* dccm.* iccm.* icache.* pic.* bus.* reset_vec nmi_vec build_ahb_lite datawidth );\n\n# Dump non-derived/settable vars/values for these vars in stdout :\nmy @dvars = qw(retstack btb bht core dccm iccm icache pic protection memmap bus);\n\n# Prefix all macros with\nmy $prefix = \"RV_\";\n# No prefix if keyword has\nmy $no_prefix = 'RV|TOP|tec_rv_icg|regwidth|clock_period|^datawidth|verilator|SDVT_AHB|tech_specific_.*|user_ec_rv_icg';\n\nmy $vlog_use__wh = 1;\n\nmy %regions_used = ();\n\n# Cmd Line options#{{{\nour %sets;\nour %unsets;\nmy $help;\nmy @sets = ();\nmy @unsets = ();\n\n#Configurations may be changed via the -set option\n#\n# -set=name=value : Change the default config parameter value (lowercase)\\n\";\n# -unset=name : Remove the default config parameter (lowercase)\\n\";\n# : Do not prepend RV_ prefex to -set/-unset variables\\n\";\n# : multiple -set/-unset options accepted\\n\\n\";\n#\n\nmy $helpusage = \"\n\nMain configuration database for VeeR\n\nThis script documents, and generates the {`#} define/include files for verilog/assembly/backend flows\n\nIt is run by vsim (with defaults) every time the file changes, or when -config_set=VAR=value options are passed to vsim\n\nThis script can be run stand-alone by processes not running vsim\n\nUser options:\n\n -target = {default, default_ahb, high_perf, typical_pd}\n use default settings for one of the targets\n\n -set=var=value\n set arbitrary variable(parameter) to a value\n -unset=var\n unset any definitions for var\n -snapshot=name\n name the configuration (only if no -target specified)\n\nParameters that can be set by the end user:\n\n -set=user_mode = {0,1}\n enable, disable user mode support in the core\n -set=ret_stack_size = {2, 3, 4, ... 8}\n size of return stack\n -set=btb_enable = {0,1}\n BTB enabled\n -set=btb_fullya = {0,1}\n BTB Fully set-associative\n -set=btb_size = { 8, 16, 32, 64, 128, 256, 512 }\n size of branch target buffer\n -set=bht_size = {32, 64, 128, 256, 512, 1024, 2048}\n size of branch history buffer\n -set=div_bit = {1,2,3,4}\n number of bits to process each cycle\n -set=div_new = {0,1}\n new div algorithm\n -set=dccm_enable = {0,1}\n DCCM enabled\n -set=dccm_num_banks = {2, 4}\n DCCM number of banks\n -set=dccm_region = { 0x0, 0x1, ... 0xf }\n number of 256Mb memory region containig DCCM\n -set=dccm_offset = hexadecimal\n offset (in bytes) of DCCM witin dccm_region\n dccm address will be: 256M * dccm_region + dccm_offset\\\", and that must be aligned\n to the dccm size or the next larger power of 2 if size is not a power of 2\n -set=dccm_size = { 4, 8, 16, 32, 48, 64, 128, 256, 512 } kB\n size of DCCM\n -set=dma_buf_depth = {2,4,5}\n DMA buffer depth\n -set=fast_interrupt_redirect = {0, 1}\n Fast interrupt redirect mechanism\n -set=iccm_enable = { 0, 1 }\n whether or not ICCM is enabled\n -set=icache_enable = { 0, 1 }\n whether or not icache is enabled\n -set=icache_waypack = { 0, 1 }\n whether or not icache packing is enabled\n -set=icache_ecc = { 0, 1 }\n whether or not icache has ecc - EXPENSIVE 30% sram growth\n default: icache_ecc==0 (parity)\n -set=icache_size = { 8, 16, 32, 64, 128, 256 } kB\n size of icache\n -set=icache_2banks = {0,1}\n Enable 2 banks for icache\n -set=icache_num_ways { 2,4}\n Number of ways in icache\n -set=icache_bypass_enable = {0,1}\n Enable Icache data bypass buffer\n -set=icache_num_bypass = {1..8}\n Number of entries in bypass buffer\n -set=icache_num_tag_bypass = {1..8}\n Number of entries in bypass buffer\n -set=icache_tag_bypass_enable = {0,1}\n Enable icache tag bypass buffer\n -set=iccm_region = { 0x0, 0x1, ... 0xf }\n number of 256Mb memory region containing ICCM\n -set=iccm_offset = hexadecimal\n offcet (in bytes) of ICCM within iccm_region\n iccm address will be: \\\"256M * iccm_region + iccm_offset\\\", and that must be aligned\n to the iccm size or the next larger power of 2 if size is not a power of 2\n -set=iccm_size = { 4 , 8 , 16 , 32, 64, 128, 256, 512 } kB\n size of ICCM\n -set=iccm_num_banks = {2,4,8,16}\n Number of ICCM banks\n -set=iccm_ecc_width\n Width of ICCM ECC [bits]\n -set=lsu_stbuf_depth = {2,4,8 }\n LSU stbuf depth\n -set=lsu_num_nbload = {2,4,8 }\n LSU number of outstanding Non Blocking loads\n -set=load_to_use_plus1 = {0 1}\n Load to use latency (fast or +1cycle)\n -set=pic_2cycle = { 0, 1 }\n whether or not 2-cycle PIC is enabled (2 cycle pic may result\n in an overall smaller cycle time)\n -set=pic_region = { 0x0, 0x1, ... 0xf }\n number of 256Mb memory region containing PIC memory-mapped registers\n -set=pic_offset = hexadecial\n offset (in bytes) of PIC within pic_region\n pic address will be: \\\"256M * pic_region + pic_offset\\\", and that must be aligned\n to the pic size or the next larger power of 2 if size is not a power of 2\n -set=pic_size = { 32, 64, 128, 256 } kB\n size of PIC\n -set=pic_total_int = { 1, 2, 3, ..., 255 }\n number of interrupt sources in PIC\n -set=dma_buf_depth = {2,4,5}\n DMA buffer depth\n -set=timer_legal_en = {0,1}\n Internal timers legal/enabled\n -set=bitmanip_zba = {0,1}\n Bit manipulation extension ZBa enabled/legal\n -set=bitmanip_zbb = {0,1}\n Bit manipulation extension ZBb enabled/legal\n -set=bitmanip_zbc = {0,1}\n Bit manipulation extension ZBc enabled/legal\n -set=bitmanip_zbe = {0,1}\n Bit manipulation extension ZBe enabled/legal\n -set=bitmanip_zbf = {0,1}\n Bit manipulation extension ZBf enabled/legal\n -set=bitmanip_zbp = {0,1}\n Bit manipulation extension ZBp enabled/legal\n -set=bitmanip_zbr = {0,1}\n Bit manipulation extension ZBr enabled/legal\n -set=bitmanip_zbs = {0,1}\n Bit manipulation extension ZBs enabled/legal\n -fpga_optimize = { 0, 1 }\n if 1, minimize clock-gating to facilitate FPGA builds\n -text_in_iccm = {0, 1}\n Don't add ICCM preload code in generated link.ld\n -set=pmp_entries = {0, 16, 64 }\n number of PMP entries\n -set=smepmp = {0, 1}\n Enable Smepmp PMP extension\n -set=lockstep_enable = {0, 1}\n Enable Dual Core Lockstep (DCLS) in the core\n -set=lockstep_regfile_enable = {0, 1}\n Enable observing register file in the DCLS\n -set=lockstep_delay = {2, 3, 4}\n Set delay value for the Dual Core Lockstep\n\n\nAdditionally the following may be set for bus masters and slaves using the -set=var=value option:\n\n {inst|data}_access_enable[0-7] : default 0\n {inst|data}_access_addr[0-7] : default 0x00000000\n {inst|data}_access_mask[0-7] : default 0xffffffff\n\";\n\nmy $user_mode;\n\nmy $ret_stack_size;\nmy $btb_size;\nmy $bht_size;\nmy $btb_fullya;\nmy $btb_toffset_size;\nmy $dccm_region;\nmy $dccm_offset;\nmy $dccm_size;\nmy $iccm_enable;\nmy $icache_enable;\nmy $icache_waypack;\nmy $icache_num_ways;\nmy $icache_banks_way;\nmy $icache_ln_sz;\nmy $icache_bank_width;\nmy $icache_ecc;\nmy $iccm_region;\nmy $iccm_offset;\nmy $iccm_size;\nmy $icache_size;\nmy $pic_2cycle;\nmy $pic_region;\nmy $pic_offset;\nmy $pic_size;\nmy $pic_total_int;\n\nmy $top_align_iccm = 0;\n\nmy $target = \"default\";\nmy $snapshot ;\nmy $build_path ;\nmy $verbose;\nmy $load_to_use_plus1;\nmy $btb_enable;\nmy $dccm_enable;\nmy $icache_2banks;\nmy $lsu_stbuf_depth;\nmy $dma_buf_depth;\nmy $lsu_num_nbload;\nmy $dccm_num_banks;\nmy $iccm_num_banks;\nmy $iccm_ecc_width;\nmy $verilator;\nmy $icache_bypass_enable=1;\nmy $icache_num_bypass=2;\nmy $icache_num_bypass_width;\nmy $icache_tag_bypass_enable=1;\nmy $icache_tag_num_bypass=2;\nmy $icache_tag_num_bypass_width;\n\nmy $fast_interrupt_redirect = 1; # ON by default\nmy $lsu_num_nbload=4;\nmy $ahb = 0;\nmy $axi = 1;\nmy $openocd_test = 0;\nmy $text_in_iccm = 0;\n\nmy $lsu2dma = 0;\n\nmy $pmp_entries=16;\nmy $smepmp=0;\nmy $lockstep_enable=0;\nmy $lockstep_regfile_enable=0;\nmy $lockstep_delay=3;\n\n$user_mode=0;\n$ret_stack_size=8;\n$btb_enable=1;\n$btb_fullya=0;\n$btb_toffset_size=12;\n$btb_size=512;\n$bht_size=512;\n$dccm_enable=1;\n$dccm_region=\"0xf\";\n$dccm_offset=\"0x40000\"; #1*256*1024\n$dccm_size=64;\n$dccm_num_banks=4;\n$iccm_enable=1;\n$iccm_region=\"0xe\";\n$top_align_iccm = 1;\n$iccm_offset=\"0xe000000\"; #0x380*256*1024\n$iccm_size=64;\n$iccm_num_banks=4;\n$iccm_ecc_width=7;\n$icache_enable=1;\n$icache_waypack=1;\n$icache_num_ways=2;\n$icache_banks_way=2;\n$icache_2banks=1;\n$icache_bank_width=8;\n$icache_ln_sz=64;\n$icache_ecc=1;\n$icache_size=16;\n$pic_2cycle=0;\n$pic_region=\"0xf\";\n$pic_offset=\"0xc0000\"; # 3*256*1024\n$pic_size=32;\n$pic_total_int=31;\n$load_to_use_plus1=0;\n$lsu_stbuf_depth=4;\n$dma_buf_depth=5;\n\nmy $div_bit=4; # number of bits to process each cycle for div\nmy $div_new=1; # old or new div algorithm\n\nmy $fpga_optimize = 1;\n\n# Default bitmanip options\nmy $bitmanip_zba = 1;\nmy $bitmanip_zbb = 1;\nmy $bitmanip_zbc = 1;\nmy $bitmanip_zbe = 0;\nmy $bitmanip_zbf = 0;\nmy $bitmanip_zbp = 0;\nmy $bitmanip_zbr = 0;\nmy $bitmanip_zbs = 1;\n\nGetOptions(\n \"help\" => \\$help,\n \"target=s\" => \\$target,\n \"snapshot=s\" => \\$snapshot,\n \"verbose\" => \\$verbose,\n \"load_to_use_plus1\" => \\$load_to_use_plus1,\n \"ret_stack_size=s\" => \\$ret_stack_size,\n \"btb_fullya\" => \\$btb_fullya,\n \"btb_enable=s\" => \\$btb_enable,\n \"btb_size=s\" => \\$btb_size,\n \"bht_size=s\" => \\$bht_size,\n \"dccm_enable=s\" => \\$dccm_enable,\n \"dccm_region=s\" => \\$dccm_region,\n \"dccm_offset=s\" => \\$dccm_offset,\n \"dccm_size=s\" => \\$dccm_size,\n \"dma_buf_depth\" => \\$dma_buf_depth,\n \"iccm_enable=s\" => \\$iccm_enable,\n \"icache_enable=s\" => \\$icache_enable,\n \"icache_waypack=s\" => \\$icache_waypack,\n \"icache_num_ways=s\" => \\$icache_num_ways,\n \"icache_ln_sz=s\" => \\$icache_ln_sz,\n \"icache_ecc=s\" => \\$icache_ecc,\n \"icache_2banks=s\" => \\$icache_2banks,\n \"iccm_region=s\" => \\$iccm_region,\n \"iccm_offset=s\" => \\$iccm_offset,\n \"iccm_size=s\" => \\$iccm_size,\n \"lsu_stbuf_depth\" => \\$lsu_stbuf_depth,\n \"lsu_num_nbload\" => \\$lsu_num_nbload,\n \"pic_2cycle=s\" => \\$pic_2cycle,\n \"pic_region=s\" => \\$pic_region,\n \"pic_offset=s\" => \\$pic_offset,\n \"pic_size=s\" => \\$pic_size,\n \"pic_total_int=s\" => \\$pic_total_int,\n \"icache_size=s\" => \\$icache_size,\n \"set=s@\" => \\@sets,\n \"unset=s@\" => \\@unsets,\n \"fpga_optimize=s\" => \\$fpga_optimize,\n \"text_in_iccm=s\" => \\$text_in_iccm,\n) || die(\"$helpusage\");\n\nif ($help) {\n print \"$helpusage\\n\";\n exit;\n}\n\nif (!defined $snapshot ) {\n $snapshot = $target;\n}\n\nif (!defined $ENV{BUILD_PATH}) {\n $build_path = \"$ENV{PWD}/snapshots/$snapshot\" ;\n} else {\n $build_path = $ENV{BUILD_PATH};\n}\n\nif (! -d \"$build_path\") {\n system (\"mkdir -p $build_path\");\n}\n\n# Parameter file\nmy $tdfile = \"$build_path/el2_pdef.vh\";\nmy $paramfile = \"$build_path/el2_param.vh\";\n\n# Verilog defines file path\nmy $vlogfile = \"$build_path/common_defines.vh\";\n\n# Assembly defines file path\nmy $asmfile = \"$build_path/defines.h\";\n\n# PD defines file path\nmy $pdfile = \"$build_path/pd_defines.vh\";\n\n# Whisper config file path\nmy $whisperfile = \"$build_path/whisper.json\";\n#\n# Default linker file\nmy $linkerfile = \"$build_path/link.ld\";\n\n\n# Perl defines file path\nmy $perlfile = \"$build_path/perl_configs.pl\";\n\nmy $opensource=0;\n\n\n\n# IDEA: is ghr at 5b the right size for el2 core\n\nif ($target eq \"default\") { }\nelsif ($target eq \"lsu2dma_axi\") {\n $lsu2dma = 1;\n $iccm_enable = 1;\n}\nelsif ($target eq \"typical_pd\") {\n print \"$self: Using target \\\"typical_pd\\\"\\n\";\n $fpga_optimize = 0;\n $ret_stack_size=2;\n $btb_size=32;\n $bht_size=128;\n $dccm_size=16;\n $dccm_num_banks=2;\n $iccm_enable=0;\n}\nelsif ($target eq \"high_perf\") {\n print \"$self: Using target \\\"high_perf\\\"\\n\";\n $btb_size=512;\n $bht_size=2048;\n}\nelsif ($target eq \"default_ahb\") {\n print \"$self: Using target \\\"default_ahb\\\"\\n\";\n $axi = 0;\n $ahb = 1;\n}\nelse {\n die \"$self: ERROR! Unsupported target \\\"$target\\\". Supported are 'default', 'default_ahb', 'typical_pd', 'high_perf', 'lsu2dma_axi\\n\" ;\n}\n\n\n\n# Configure triggers\nour @triggers = (#{{{\n {\n \"reset\" => [\"0x23e00000\", \"0x00000000\", \"0x00000000\"],\n \"mask\" => [\"0x081818c7\", \"0xffffffff\", \"0x00000000\"],\n \"poke_mask\" => [\"0x081818c7\", \"0xffffffff\", \"0x00000000\"]\n },\n {\n \"reset\" => [\"0x23e00000\", \"0x00000000\", \"0x00000000\"],\n \"mask\" => [\"0x081810c7\", \"0xffffffff\", \"0x00000000\"],\n \"poke_mask\" => [\"0x081810c7\", \"0xffffffff\", \"0x00000000\"]\n },\n {\n \"reset\" => [\"0x23e00000\", \"0x00000000\", \"0x00000000\"],\n \"mask\" => [\"0x081818c7\", \"0xffffffff\", \"0x00000000\"],\n \"poke_mask\" => [\"0x081818c7\", \"0xffffffff\", \"0x00000000\"]\n },\n {\n \"reset\" => [\"0x23e00000\", \"0x00000000\", \"0x00000000\"],\n \"mask\" => [\"0x081810c7\", \"0xffffffff\", \"0x00000000\"],\n \"poke_mask\" => [\"0x081810c7\", \"0xffffffff\", \"0x00000000\"]\n },\n );#}}}\n\n\n# Configure CSRs\nour %csr = (#{{{\n \"mstatus\" => {\n \"reset\" => \"0x1800\", # MPP bits hard wired to binrary 11.\n \"mask\" => \"0x88\", # Only mpie(7) & mie(3) bits writeable\n \"exists\" => \"true\",\n },\n \"mie\" => {\n \"reset\" => \"0x0\",\n # Only external, timer, local, and software writeable\n \"mask\" => \"0x70000888\",\n \"exists\" => \"true\",\n },\n \"mip\" => {\n \"reset\" => \"0x0\",\n # None of the bits are writeable using CSR instructions\n \"mask\" => \"0x0\",\n # Bits corresponding to error overflow, external, timer and stoftware\n # interrupts are modifiable\n \"poke_mask\" => \"0x70000888\",\n \"exists\" => \"true\",\n },\n \"mcountinhibit\" => {\n \"commnet\" => \"Performance counter inhibit. One bit per counter.\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x7d\",\n \"poke_mask\" => \"0x7d\",\n \"exists\" => \"true\",\n },\n \"mcounteren\" => {\n \"exists\" => \"false\",\n },\n \"mvendorid\" => {\n \"reset\" => \"0x45\",\n \"mask\" => \"0x0\",\n \"exists\" => \"true\",\n },\n \"marchid\" => {\n \"reset\" => \"0x00000010\",\n \"mask\" => \"0x0\",\n \"exists\" => \"true\",\n },\n \"mimpid\" => {\n \"reset\" => \"0x4\",\n \"mask\" => \"0x0\",\n \"exists\" => \"true\",\n },\n \"misa\" => {\n \"reset\" => \"0x40001104\",\n \"mask\" => \"0x0\",\n \"exists\" => \"true\",\n },\n \"tselect\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0x3\", # Four triggers\n \"exists\" => \"true\",\n },\n \"mhartid\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0\",\n \"poke_mask\" => \"0xfffffff0\",\n \"exists\" => \"true\",\n },\n \"dcsr\" => {\n \"reset\" => \"0x40000003\",\n \"mask\" => \"0x00008c04\",\n \"poke_mask\" => \"0x00008dcc\", # cause field modifiable, nmip modifiable\n \"exists\" => \"true\",\n \"debug\" => \"true\",\n },\n \"cycle\" => {\n \"exists\" => \"false\",\n },\n \"time\" => {\n \"exists\" => \"false\",\n },\n \"instret\" => {\n \"exists\" => \"false\",\n },\n \"mhpmcounter3\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmcounter4\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmcounter5\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmcounter6\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmcounter3h\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmcounter4h\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmcounter5h\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmcounter6h\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmevent3\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmevent4\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmevent5\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mhpmevent6\" => {\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n# Remaining CSRs are non-standard. These are specific to VeeR\n \"dicawics\" => {\n \"number\" => \"0x7c8\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0130fffc\",\n \"exists\" => \"true\",\n },\n \"dicad0\" => {\n \"number\" => \"0x7c9\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"dicad1\" => {\n \"number\" => \"0x7ca\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x3\",\n \"exists\" => \"true\",\n },\n \"dicago\" => {\n \"number\" => \"0x7cb\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0\",\n \"exists\" => \"true\",\n },\n \"mitcnt0\" => {\n \"number\" => \"0x7d2\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mitbnd0\" => {\n \"number\" => \"0x7d3\",\n \"reset\" => \"0xffffffff\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mitctl0\" => {\n \"number\" => \"0x7d4\",\n \"reset\" => \"0x1\",\n \"mask\" => \"0x00000007\",\n \"exists\" => \"true\",\n },\n \"mitcnt1\" => {\n \"number\" => \"0x7d5\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mitbnd1\" => {\n \"number\" => \"0x7d6\",\n \"reset\" => \"0xffffffff\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mitctl1\" => {\n \"number\" => \"0x7d7\",\n \"reset\" => \"0x1\",\n \"mask\" => \"0x0000000f\",\n \"exists\" => \"true\",\n },\n \"mcpc\" => {\n \"comment\" => \"Core pause\",\n \"number\" => \"0x7c2\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0\",\n \"exists\" => \"true\",\n },\n \"mpmc\" => {\n \"number\" => \"0x7c6\",\n \"reset\" => \"0x2\",\n \"mask\" => \"0x2\",\n \"exists\" => \"true\",\n },\n \"micect\" => {\n \"number\" => \"0x7f0\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"miccmect\" => {\n \"number\" => \"0x7f1\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mdccmect\" => {\n \"number\" => \"0x7f2\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n },\n \"mcgc\" => {\n \"number\" => \"0x7f8\",\n \"reset\" => \"0x200\",\n \"mask\" => \"0x000003ff\",\n \"poke_mask\" => \"0x000003ff\",\n \"exists\" => \"true\",\n },\n \"mfdc\" => {\n \"number\" => \"0x7f9\",\n \"reset\" => \"0x00070000\",\n \"mask\" => \"0x00071fff\",\n \"exists\" => \"true\",\n },\n \"mrac\" => {\n \"comment\" => \"Memory region io and cache control.\",\n \"number\" => \"0x7c0\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n \"shared\" => \"true\",\n },\n \"dmst\" => {\n \"comment\" => \"Memory synch trigger: Flush caches in debug mode.\",\n \"number\" => \"0x7c4\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0\",\n \"exists\" => \"true\",\n \"debug\" => \"true\",\n },\n \"dicawics\" => {\n \"comment\" => \"Cache diagnostics.\",\n \"number\" => \"0x7c8\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0130fffc\",\n \"exists\" => \"true\",\n \"debug\" => \"true\",\n },\n \"dicad0\" => {\n \"comment\" => \"Cache diagnostics.\",\n \"number\" => \"0x7c9\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xffffffff\",\n \"exists\" => \"true\",\n \"debug\" => \"true\",\n },\n \"dicad1\" => {\n \"comment\" => \"Cache diagnostics.\",\n \"number\" => \"0x7ca\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x3\",\n \"exists\" => \"true\",\n \"debug\" => \"true\",\n },\n \"dicago\" => {\n \"comment\" => \"Cache diagnostics.\",\n \"number\" => \"0x7cb\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0\",\n \"exists\" => \"true\",\n \"debug\" => \"true\",\n },\n \"meipt\" => {\n \"comment\" => \"External interrupt priority threshold.\",\n \"number\" => \"0xbc9\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xf\",\n \"exists\" => \"true\",\n },\n \"meicpct\" => {\n \"comment\" => \"External claim id/priority capture.\",\n \"number\" => \"0xbca\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0\",\n \"exists\" => \"true\",\n },\n \"meicidpl\" => {\n \"comment\" => \"External interrupt claim id priority level.\",\n \"number\" => \"0xbcb\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xf\",\n \"exists\" => \"true\",\n },\n \"meicurpl\" => {\n \"comment\" => \"External interrupt current priority level.\",\n \"number\" => \"0xbcc\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0xf\",\n \"exists\" => \"true\",\n },\n \"mfdht\" => {\n \"comment\" => \"Force Debug Halt Threshold\",\n \"number\" => \"0x7ce\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0000003f\",\n \"exists\" => \"true\",\n \"shared\" => \"true\",\n },\n \"mfdhs\" => {\n \"comment\" => \"Force Debug Halt Status\",\n \"number\" => \"0x7cf\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x00000003\",\n \"exists\" => \"true\",\n },\n \"mscause\" => {\n \"number\" => \"0x7ff\",\n \"reset\" => \"0x0\",\n \"mask\" => \"0x0000000f\",\n \"exists\" => \"true\",\n },\n\n);#}}}\n\n\n# These are the peformance counters events implemented for el2s. An\n# event number from outside this list will be replaced by zero if\n# written to an MHPMEVENT CSR.\nmy @perf_events = (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,\n 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30,\n 31, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,\n 45, 46, 47, 48, 49, 50, 54, 55, 56,\n 512, 513, 514, 515, 516);\n\n# FIXME: PMP CSR handling\n\n#foreach my $i (0 .. 3) {\n# $csr{\"pmpcfg$i\"} = { \"exists\" => \"false\" };\n#}\n\n#foreach my $i (0 .. 15) {\n# $csr{\"pmpaddr$i\"} = { \"exists\" => \"false\" };\n#}\n\n# }}}\n# Main config hash, with default values\n#\n# Hash can be hierarchical with arbitrary levels\n# Hexadecimal values are prefixed with 0x\n#\n# For verilog, if bit width is expected, add to %width hash below\n#\n# NOTE: params/keys marked 'derived' are not settable via cmd line, unless they ALSO have the 'overridable' tag\n#\nour %config = (#{{{\n \"harts\" => \"1\",\n \"xlen\" => \"32\", # Testbench, Do Not Override\n \"numiregs\" => \"32\", # Testbench, Do Not Override\n \"regwidth\" => \"32\", # Testbench, Do Not Override\n \"reset_vec\" => \"0x80000000\", # Testbench, Overridable\n \"nmi_vec\" => \"0x11110000\", # Testbench, Overridable\n \"physical\" => \"1\",\n \"num_mmode_perf_regs\" => \"4\", # Whisper only\n \"max_mmode_perf_event\" => \"516\", # Whisper only: performance counters event ids will be clamped to this\n \"target\" => $target, # Flow Infrastructure\n \"config_key\" => \"derived\",\n \"tec_rv_icg\" => \"clockhdr\",\n\n \"retstack\" => {\n \"ret_stack_size\" => \"$ret_stack_size\", # Design Parm, Overridable\n },\n\n \"btb\" => {\n \"btb_enable\" => \"$btb_enable\", # Design Parm, Overridable\n \"btb_fullya\" => \"$btb_fullya\", # Design Parm, Overridable\n \"btb_toffset_size\" => \"$btb_toffset_size\", # Constant\n \"btb_size\" => \"$btb_size\", # Design Parm, Overridable\n \"btb_index1_hi\" => \"derived\",\n \"btb_index1_lo\" => \"2\", # Constant, Do Not Override\n \"btb_index2_hi\" => \"derived\",\n \"btb_index2_lo\" => \"derived\",\n \"btb_index3_hi\" => \"derived\",\n \"btb_index3_lo\" => \"derived\",\n \"btb_addr_hi\" => \"derived\",\n \"btb_array_depth\" => \"derived\",\n \"btb_addr_lo\" => \"2\", # Constant, Do Not Override\n \"btb_btag_size\" => \"derived\",\n \"btb_btag_fold\" => \"derived\",\n \"btb_fold2_index_hash\" => \"derived\",\n },\n \"bht\" => {\n \"bht_size\" => \"$bht_size\", # Design Parm, Overridable\n \"bht_addr_hi\" => \"derived\",\n \"bht_addr_lo\" => \"2\", # Constant, Do Not Override\n \"bht_array_depth\" => \"derived\",\n \"bht_ghr_size\" => \"derived\",\n \"bht_ghr_range\" => \"derived\",\n \"bht_hash_string\" => \"derived\",\n \"bht_ghr_hash_1\" => \"derived\",\n },\n\n \"core\" => {\n \"user_mode\" => \"$user_mode\",\n \"div_bit\" => \"$div_bit\", # Design Parm, Overridable\n \"div_new\" => \"$div_new\", # Design Parm, Overridable\n \"lsu_stbuf_depth\" => \"$lsu_stbuf_depth\", # Design Parm, Overridable\n \"dma_buf_depth\" => \"$dma_buf_depth\", # Design Parm, Overridable\n \"lsu_num_nbload\" => \"$lsu_num_nbload\", # Design Parm, Overridable\n \"opensource\" => \"$opensource\", # Flow Infrastructure\n \"verilator\" => \"$verilator\", # Flow Infrastructure\n \"load_to_use_plus1\" => \"$load_to_use_plus1\", # Design Parm, Overridable\n \"iccm_icache\" => 'derived', # Used by design\n \"iccm_only\" => 'derived', # Used by design\n \"icache_only\" => 'derived', # Used by design\n \"no_iccm_no_icache\" => 'derived', # Used by design\n \"timer_legal_en\" => '1', # Design Parm, Overridable\n \"bitmanip_zba\" => $bitmanip_zba, # Design Parm, Overridable\n \"bitmanip_zbb\" => $bitmanip_zbb, # Design Parm, Overridable\n \"bitmanip_zbc\" => $bitmanip_zbc, # Design Parm, Overridable\n \"bitmanip_zbe\" => $bitmanip_zbe, # Design Parm, Overridable\n \"bitmanip_zbf\" => $bitmanip_zbf, # Design Parm, Overridable\n \"bitmanip_zbp\" => $bitmanip_zbp, # Design Parm, Overridable\n \"bitmanip_zbr\" => $bitmanip_zbr, # Design Parm, Overridable\n \"bitmanip_zbs\" => $bitmanip_zbs, # Design Parm, Overridable\n \"fast_interrupt_redirect\" => \"$fast_interrupt_redirect\", # Design Parm, Overridable\n \"lsu2dma\" => $lsu2dma, # used by design/TB for LSU to DMA bridge\n \"fpga_optimize\" => $fpga_optimize # Design Parm, Overridable\n },\n\n \"dccm\" => {\n \"dccm_enable\" => \"$dccm_enable\", # Design Parm, Overridable\n \"dccm_region\" => \"$dccm_region\", # Design Parm, Overridable\n \"dccm_offset\" => \"$dccm_offset\", # Design Parm, Overridable\n \"dccm_size\" => \"$dccm_size\", # Design Parm, Overridable\n \"dccm_num_banks\" => \"$dccm_num_banks\", # Design Parm, Overridable\n \"dccm_sadr\" => 'derived',\n \"dccm_eadr\" => 'derived',\n \"dccm_bits\" => 'derived',\n \"dccm_bank_bits\" => 'derived',\n \"dccm_data_width\" => 'derived',\n \"dccm_fdata_width\" => 'derived',\n \"dccm_byte_width\" => 'derived',\n \"dccm_width_bits\" => 'derived',\n \"dccm_index_bits\" => 'derived',\n \"dccm_ecc_width\" => 'derived',\n \"lsu_sb_bits\" => 'derived',\n \"dccm_data_cell\" => 'derived',\n \"dccm_rows\" => 'derived',\n \"dccm_reserved\" => 'derived', # Testbench use only : reserve dccm space for SW/stack - no random r/w\n },\n\n\n \"iccm\" => {\n \"iccm_enable\" => \"$iccm_enable\", # Design Parm, Overridable\n \"iccm_region\" => \"$iccm_region\", # Design Parm, Overridable\n \"iccm_offset\" => \"$iccm_offset\", # Design Parm, Overridable\n \"iccm_size\" => \"$iccm_size\", # Design Parm, Overridable\n \"iccm_num_banks\" => \"$iccm_num_banks\", # Design Parm, Overridable\n \"iccm_bank_bits\" => 'derived',\n \"iccm_index_bits\" => 'derived',\n \"iccm_rows\" => 'derived',\n \"iccm_data_cell\" => 'derived',\n \"iccm_sadr\" => 'derived',\n \"iccm_eadr\" => 'derived',\n \"iccm_reserved\" => 'derived', # Testbench use only : reserve iccm space for SW/handlers - no random r/w\n \"iccm_bank_hi\" => 'derived',\n \"iccm_ecc_width\" => \"$iccm_ecc_width\",\n \"iccm_bank_index_lo\" => 'derived',\n },\n \"icache\" => {\n \"icache_enable\" => \"$icache_enable\", # Design Parm, Overridable\n \"icache_waypack\" => \"$icache_waypack\", # Design Parm, Overridable\n \"icache_num_ways\" => \"$icache_num_ways\", # Design Parm, Overridable\n \"icache_banks_way\" => \"2\", # Design Parm, Constant\n \"icache_bank_width\" => \"8\", # Design Parm, Constant\n \"icache_ln_sz\" => \"$icache_ln_sz\", # Design Parm, Overridable\n \"icache_size\" => \"$icache_size\", # Design Parm, Overridable\n \"icache_bypass_enable\" => \"$icache_bypass_enable\", # Design Parm, Overridable\n \"icache_num_bypass\" => \"$icache_num_bypass\", # Design Parm, Overridable\n \"icache_num_bypass_width\" => 'derived',\n \"icache_tag_bypass_enable\" => \"$icache_tag_bypass_enable\", # Design Parm, Overridable\n \"icache_tag_num_bypass\" => \"$icache_tag_num_bypass\", # Design Parm, Overridable\n \"icache_tag_num_bypass_width\" => 'derived',\n \"icache_bank_hi\" => 'derived',\n \"icache_bank_lo\" => 'derived',\n \"icache_data_cell\" => 'derived',\n \"icache_tag_cell\" => 'derived',\n \"icache_tag_depth\" => 'derived',\n \"icache_data_depth\" => 'derived',\n \"icache_num_lines\" => 'derived',\n \"icache_num_lines_bank\" => 'derived',\n \"icache_num_lines_way\" => 'derived',\n \"icache_data_depth\" => 'derived',\n \"icache_tag_lo\" => 'derived',\n \"icache_index_hi\" => 'derived',\n \"icache_data_index_lo\" => 'derived',\n \"icache_data_width\" => 'derived',\n \"icache_fdata_width\" => 'derived',\n \"icache_tag_index_lo\" => 'derived',\n \"icache_ecc\" => \"$icache_ecc\", # Design Parm, Overridable\n \"icache_2banks\" => \"$icache_2banks\", # Design Parm, Overridable\n \"icache_bank_bits\" => \"derived\",\n \"icache_status_bits\" => \"derived\",\n \"icache_num_beats\" => \"derived\",\n \"icache_beat_bits\" => \"derived\",\n \"icache_scnd_last\" => \"derived\",\n \"icache_beat_addr_hi\" => \"derived\",\n },\n \"pic\" => {\n \"pic_2cycle\" => \"$pic_2cycle\", # Design Parm, Overridable\n \"pic_region\" => \"$pic_region\", # Design Parm, Overridable\n \"pic_offset\" => \"$pic_offset\", # Design Parm, Overridable\n \"pic_size\" => \"$pic_size\", # Design Parm, Overridable\n \"pic_base_addr\" => 'derived',\n \"pic_total_int_plus1\" => 'derived', # pic_total_int + 1\n \"pic_total_int\" => \"$pic_total_int\", # Design Parm, Overridable\n \"pic_int_words\" => 'derived', # number of 32 bit words for packed registers (Xmax)\n \"pic_bits\" => 'derived', # of bits needs to address the PICM\n \"pic_meipl_offset\" => '0x0000', # Testbench only: Offset of meipl relative to pic_base_addr\n \"pic_meip_offset\" => '0x1000', # Testbench only: Offset of meip relative to pic_base_addr\n \"pic_meie_offset\" => '0x2000', # Testbench only: Offset of meie relative to pic_base_addr\n \"pic_mpiccfg_offset\" => '0x3000', # Testbench only: Offset of mpiccfg relative to pic_base_addr\n \"pic_meipt_offset\" => '0x3004', # Testbench only: Offset of meipt relative to pic_base_addr -- deprecated\n \"pic_meigwctrl_offset\" => '0x4000', # Testbench only: gateway control regs relative to pic_base_addr\n \"pic_meigwclr_offset\" => '0x5000', # Testbench only: gateway clear regs relative to pic_base_addr\n\n \"pic_meipl_mask\" => '0xf', # Whisper only\n \"pic_meip_mask\" => '0x0',\n \"pic_meie_mask\" => '0x1',\n \"pic_mpiccfg_mask\" => '0x1',\n \"pic_meipt_mask\" => '0x0',\n \"pic_meigwctrl_mask\" => '0x3',\n \"pic_meigwclr_mask\" => '0x0',\n\n \"pic_meipl_count\" => 'derived',\n \"pic_meip_count\" => 'derived',\n \"pic_meie_count\" => 'derived',\n \"pic_mpiccfg_count\" => 1,\n \"pic_meipt_count\" => 'derived',\n \"pic_meigwctrl_count\" => 'derived',\n \"pic_meigwclr_count\" => 'derived',\n },\n \"testbench\" => { # Testbench only\n \"TOP\" => \"tb_top\",\n \"RV_TOP\" => \"`TOP.rvtop_wrapper.rvtop\",\n \"CPU_TOP\" => \"`RV_TOP.veer\",\n \"clock_period\" => \"100\",\n \"build_ahb_lite\" => \"$ahb\",\n \"build_axi4\" => \"$axi\",\n \"build_axi_native\" => \"1\",\n \"openocd_test\" => \"$openocd_test\",\n \"ext_datawidth\" => \"64\",\n \"ext_addrwidth\" => \"32\",\n \"sterr_rollback\" => \"0\",\n \"lderr_rollback\" => \"1\",\n \"SDVT_AHB\" => \"$ahb\",\n },\n \"protection\" => { # Design parms, Overridable - static MPU\n \"pmp_entries\" => \"$pmp_entries\",\n \"smepmp\" => \"$smepmp\",\n \"lockstep_enable\" => \"$lockstep_enable\",\n \"lockstep_regfile_enable\" => \"$lockstep_regfile_enable\",\n \"lockstep_delay\" => \"$lockstep_delay\",\n \"inst_access_enable0\" => \"0x0\",\n \"inst_access_addr0\" => \"0x00000000\",\n \"inst_access_mask0\" => \"0xffffffff\",\n \"inst_access_enable1\" => \"0x0\",\n \"inst_access_addr1\" => \"0x00000000\",\n \"inst_access_mask1\" => \"0xffffffff\",\n \"inst_access_enable2\" => \"0x0\",\n \"inst_access_addr2\" => \"0x00000000\",\n \"inst_access_mask2\" => \"0xffffffff\",\n \"inst_access_enable3\" => \"0x0\",\n \"inst_access_addr3\" => \"0x00000000\",\n \"inst_access_mask3\" => \"0xffffffff\",\n \"inst_access_enable4\" => \"0x0\",\n \"inst_access_addr4\" => \"0x00000000\",\n \"inst_access_mask4\" => \"0xffffffff\",\n \"inst_access_enable5\" => \"0x0\",\n \"inst_access_addr5\" => \"0x00000000\",\n \"inst_access_mask5\" => \"0xffffffff\",\n \"inst_access_enable6\" => \"0x0\",\n \"inst_access_addr6\" => \"0x00000000\",\n \"inst_access_mask6\" => \"0xffffffff\",\n \"inst_access_enable7\" => \"0x0\",\n \"inst_access_addr7\" => \"0x00000000\",\n \"inst_access_mask7\" => \"0xffffffff\",\n \"data_access_enable0\" => \"0x0\",\n \"data_access_addr0\" => \"0x00000000\",\n \"data_access_mask0\" => \"0xffffffff\",\n \"data_access_enable1\" => \"0x0\",\n \"data_access_addr1\" => \"0x00000000\",\n \"data_access_mask1\" => \"0xffffffff\",\n \"data_access_enable2\" => \"0x0\",\n \"data_access_addr2\" => \"0x00000000\",\n \"data_access_mask2\" => \"0xffffffff\",\n \"data_access_enable3\" => \"0x0\",\n \"data_access_addr3\" => \"0x00000000\",\n \"data_access_mask3\" => \"0xffffffff\",\n \"data_access_enable4\" => \"0x0\",\n \"data_access_addr4\" => \"0x00000000\",\n \"data_access_mask4\" => \"0xffffffff\",\n \"data_access_enable5\" => \"0x0\",\n \"data_access_addr5\" => \"0x00000000\",\n \"data_access_mask5\" => \"0xffffffff\",\n \"data_access_enable6\" => \"0x0\",\n \"data_access_addr6\" => \"0x00000000\",\n \"data_access_mask6\" => \"0xffffffff\",\n \"data_access_enable7\" => \"0x0\",\n \"data_access_addr7\" => \"0x00000000\",\n \"data_access_mask7\" => \"0xffffffff\",\n },\n \"memmap\" => { # Testbench only\n \"serialio\" => 'derived, overridable', # Testbench only\n \"external_data\" => 'derived, overridable', # Testbench only\n \"debug_sb_mem\" => 'derived, overridable', # Testbench only\n \"external_data_1\" => 'derived, overridable', # Testbench only\n \"external_mem_hole\" => 'default disabled', # Testbench only\n# \"consoleio\" => 'derived', # Part of serial io.\n },\n \"bus\" => {\n \"lsu_bus_tag\" => 'derived',\n \"lsu_bus_id\" => '1',\n \"lsu_bus_prty\" => '2',\n \"dma_bus_tag\" => '1',\n \"dma_bus_id\" => '1',\n \"dma_bus_prty\" => '2',\n \"sb_bus_tag\" => '1',\n \"sb_bus_id\" => '1',\n \"sb_bus_prty\" => '2',\n \"ifu_bus_tag\" => 'derived',\n \"ifu_bus_id\" => '1',\n \"ifu_bus_prty\" => '2',\n \"bus_prty_default\" => '3',\n },\n \"triggers\" => \\@triggers, # Whisper only\n \"csr\" => \\%csr, # Whisper only\n \"perf_events\" => \\@perf_events, # Whisper only\n \"even_odd_trigger_chains\" => \"true\", # Whisper only\n\n \"tech_specific_ec_rv_icg\" => '0',\n\n \"user_ec_rv_icg\" => 'user_clock_gate',\n);\n\n\n# These parms are used in the Verilog and will be part of global parm structure\n# need to have this be width in binary\n# for now autosize to the data\nour %verilog_parms = (\n \"user_mode\" => '1',\n\n \"lsu2dma\" => '1',\n \"timer_legal_en\" => '1',\n \"bitmanip_zbb\" => '1',\n \"bitmanip_zbs\" => '1',\n \"bitmanip_zba\" => '1',\n \"bitmanip_zbc\" => '1',\n \"bitmanip_zbe\" => '1',\n \"bitmanip_zbf\" => '1',\n \"bitmanip_zbp\" => '1',\n \"bitmanip_zbr\" => '1',\n \"fast_interrupt_redirect\" => '1',\n\n \"pmp_entries\" => '7',\n \"smepmp\" => '1',\n \"lockstep_enable\" => '1',\n \"lockstep_regfile_enable\" => '1',\n \"lockstep_delay\" => '3',\n \"inst_access_enable0\" => '1',\n \"inst_access_addr0\" => '32',\n \"inst_access_mask0\" => '32',\n \"inst_access_enable1\" => '1',\n \"inst_access_addr1\" => '32',\n \"inst_access_mask1\" => '32',\n \"inst_access_enable2\" => '1',\n \"inst_access_addr2\" => '32',\n \"inst_access_mask2\" => '32',\n \"inst_access_enable3\" => '1',\n \"inst_access_addr3\" => '32',\n \"inst_access_mask3\" => '32',\n \"inst_access_enable4\" => '1',\n \"inst_access_addr4\" => '32',\n \"inst_access_mask4\" => '32',\n \"inst_access_enable5\" => '1',\n \"inst_access_addr5\" => '32',\n \"inst_access_mask5\" => '32',\n \"inst_access_enable6\" => '1',\n \"inst_access_addr6\" => '32',\n \"inst_access_mask6\" => '32',\n \"inst_access_enable7\" => '1',\n \"inst_access_addr7\" => '32',\n \"inst_access_mask7\" => '32',\n \"data_access_enable0\" => '1',\n \"data_access_addr0\" => '32',\n \"data_access_mask0\" => '32',\n \"data_access_enable1\" => '1',\n \"data_access_addr1\" => '32',\n \"data_access_mask1\" => '32',\n \"data_access_enable2\" => '1',\n \"data_access_addr2\" => '32',\n \"data_access_mask2\" => '32',\n \"data_access_enable3\" => '1',\n \"data_access_addr3\" => '32',\n \"data_access_mask3\" => '32',\n \"data_access_enable4\" => '1',\n \"data_access_addr4\" => '32',\n \"data_access_mask4\" => '32',\n \"data_access_enable5\" => '1',\n \"data_access_addr5\" => '32',\n \"data_access_mask5\" => '32',\n \"data_access_enable6\" => '1',\n \"data_access_addr6\" => '32',\n \"data_access_mask6\" => '32',\n \"data_access_enable7\" => '1',\n \"data_access_addr7\" => '32',\n \"data_access_mask7\" => '32',\n \"iccm_bits\" => '5',\n \"iccm_bank_hi\" => '5',\n \"iccm_bank_index_lo\" => '5',\n \"icache_bank_bits\" => '3',\n \"icache_status_bits\" => '3',\n \"icache_num_beats\" => '4',\n \"icache_beat_bits\" => '4',\n \"icache_scnd_last\" => '4',\n \"icache_beat_addr_hi\" => '4',\n \"icache_bypass_enable\" => '1',\n \"icache_num_bypass\" => '4',\n \"icache_num_bypass_width\" => '4',\n \"icache_tag_bypass_enable\" => '1',\n \"icache_tag_num_bypass\" => '4',\n \"icache_tag_num_bypass_width\" => '4',\n \"iccm_icache\" => '1',\n \"iccm_only\" => '1',\n \"icache_only\" => '1',\n \"no_iccm_no_icache\" => '1',\n \"build_axi4\" => '1',\n \"build_ahb_lite\" => '1',\n \"build_axi_native\" => '1',\n \"lsu_num_nbload_width\" => '3',\n \"lsu_num_nbload\" => '5',\n \"ret_stack_size\" => '4',\n \"btb_fullya\" => '1',\n \"btb_toffset_size\" => '5',\n \"btb_enable\" => '1',\n \"btb_size\" => '10',\n \"btb_index1_hi\" => '5',\n \"btb_index1_lo\" => '5',\n \"btb_index2_hi\" => '5',\n \"btb_index2_lo\" => '5',\n \"btb_index3_hi\" => '5',\n \"btb_index3_lo\" => '5',\n \"btb_addr_hi\" => '5',\n \"btb_array_depth\" => '9',\n \"btb_addr_lo\" => '2',\n \"btb_btag_size\" => '5',\n \"btb_btag_fold\" => '1',\n \"btb_fold2_index_hash\" => '1',\n \"bht_size\" => '12',\n \"bht_addr_hi\" => '4',\n \"bht_addr_lo\" => '2',\n \"bht_array_depth\" => '11',\n \"bht_ghr_size\" => '4',\n \"bht_ghr_hash_1\" => '1',\n \"div_bit\" => '3',\n \"div_new\" => '1',\n \"lsu_stbuf_depth\" => '4',\n \"dma_buf_depth\" => '3',\n \"load_to_use_plus1\" => '1',\n \"dccm_enable\" => '1',\n \"dccm_region\" => '4',\n \"dccm_size\" => '10',\n \"dccm_num_banks\" => '5',\n \"dccm_sadr\" => '32',\n \"dccm_bits\" => '5',\n \"dccm_bank_bits\" => '3',\n \"dccm_data_width\" => '6',\n \"dccm_fdata_width\" => '6',\n \"dccm_byte_width\" => '3',\n \"dccm_width_bits\" => '2',\n \"dccm_index_bits\" => '4',\n \"dccm_ecc_width\" => '3',\n \"lsu_sb_bits\" => '5',\n \"iccm_enable\" => '1',\n \"iccm_region\" => '4',\n \"iccm_size\" => '10',\n \"iccm_num_banks\" => '5',\n \"iccm_bank_bits\" => '3',\n \"iccm_index_bits\" => '4',\n \"iccm_sadr\" => '32',\n \"iccm_ecc_width\" => '3',\n \"icache_enable\" => '1',\n \"icache_waypack\" => '1',\n \"icache_num_ways\" => '3',\n \"icache_banks_way\" => '3',\n \"icache_bank_width\" => '4',\n \"icache_ln_sz\" => '7',\n \"icache_size\" => '9',\n \"icache_bank_hi\" => '3',\n \"icache_bank_lo\" => '2',\n \"icache_tag_depth\" => '13',\n \"icache_data_depth\" => '14',\n \"icache_tag_lo\" => '5',\n \"icache_index_hi\" => '5',\n \"icache_data_index_lo\" => '3',\n \"icache_data_width\" => '7',\n \"icache_fdata_width\" => '7',\n \"icache_tag_index_lo\" => '3',\n \"icache_ecc\" => '1',\n \"icache_2banks\" => '1',\n \"pic_2cycle\" => '1',\n \"pic_region\" => '4',\n \"pic_size\" => '9',\n \"pic_base_addr\" => '32',\n \"pic_total_int_plus1\" => '9',\n \"pic_total_int\" => '8',\n \"pic_int_words\" => '4',\n \"pic_bits\" => '5',\n \"lsu_bus_tag\" => '4',\n \"lsu_bus_id\" => '1',\n \"lsu_bus_prty\" => '2',\n \"dma_bus_tag\" => '4',\n \"dma_bus_id\" => '5',\n \"dma_bus_prty\" => '2',\n \"sb_bus_tag\" => '4',\n \"sb_bus_id\" => '1',\n \"sb_bus_prty\" => '2',\n \"ifu_bus_tag\" => '4',\n \"ifu_bus_id\" => '1',\n \"ifu_bus_prty\" => '2',\n \"bus_prty_default\" => '2',\n);\n\n# to make sure parameter math works properly add 4 to each key of %verilog_parms - was an issue in btb calculations\nmy $key;\nforeach $key (sort keys %verilog_parms) {\n if ( $key ne \"user_mode\" && $key ne \"smepmp\" ) {\n $verilog_parms{$key} += 4;\n }\n}\n\n\n# need to figure out what to do here\n# for now none of these can be parameters\n\n\n# move deletes lower\n\n# Perform any overrides first before derived values\n#\nmap_set_unset();\n\ngen_define(\"\",\"\", \\%config,\"\",[]);\n\n# perform final checks\nmy $c;\n$c=$config{retstack}{ret_stack_size}; if (!($c >=2 && $c <=8)) { die(\"$helpusage\\n\\nFAIL: ret_stack_size == $c; ILLEGAL !!!\\n\\n\"); }\n$c=$config{btb}{btb_size}; if (!($c==8||$c==16||$c==32||$c==64||$c==128||$c==256||$c==512)) { die(\"$helpusage\\n\\nFAIL: btb_size == $c; ILLEGAL !!!\\n\\n\"); }\n$c=$config{btb}{btb_size}; if (($c==64||$c==128||$c==256||$c==512) && $config{btb}{btb_fullya}) { die(\"$helpusage\\n\\nFAIL: btb_size == $c; btb_fullya=1 ILLEGAL !!!\\n\\n\"); }\n$c=$config{iccm}{iccm_region}; if (!($c>=0 && $c<16)) { die(\"$helpusage\\n\\nFAIL: iccm_region == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{iccm}{iccm_offset}; if (!($c>=0 && $c<256*1024*1024 && ($c&0xfff)==0)) { die(\"$helpusage\\n\\nFAIL: iccm_offset == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{iccm}{iccm_size}; if (!($c==2||$c==4||$c==8||$c==16||$c==32||$c==64||$c==128||$c==256||$c==512)) { die(\"$helpusage\\n\\nFAIL: iccm_size == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{iccm}{iccm_num_banks}; if (!($c==2 || $c==4 || ($c==8 && $config{iccm}{iccm_size} != 2) || ($c==16 && $config{iccm}{iccm_size} > 4))) { die(\"$helpusage\\n\\nFAIL: iccm_num_banks == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{iccm}{iccm_enable}; if (!($c==0 || $c==1)) { die(\"$helpusage\\n\\nFAIL: iccm_enable == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{dccm}{dccm_region}; if (!($c>=0 && $c<16)) { die(\"$helpusage\\n\\nFAIL: dccm_region == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{dccm}{dccm_num_banks}; if (!(($c==2 && $config{dccm}{dccm_size} != 48) || $c==4 || ($c==8 && $config{dccm}{dccm_size} != 48) || ($c==16 && $config{dccm}{dccm_size} != 4 && $config{dccm}{dccm_size} != 48)))\n { die(\"$helpusage\\n\\nFAIL: dccm_num_banks == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{dccm}{dccm_offset}; if (!($c>=0 && $c<256*1024*1024 && ($c&0xfff)==0)) { die(\"$helpusage\\n\\nFAIL: dccm_offset == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{dccm}{dccm_size}; if (!($c==4||$c==8||$c==16||$c==32||$c==48||$c==64||$c==128||$c==256||$c==512)) { die(\"$helpusage\\n\\nFAIL: dccm_size == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{pic}{pic_2cycle}; if (!($c==0 || $c==1)) { die(\"$helpusage\\n\\nFAIL: pic_2cycle == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{pic}{pic_region}; if (!($c>=0 && $c<16)) { die(\"$helpusage\\n\\nFAIL: pic_region == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{pic}{pic_offset}; if (!($c>=0 && $c<256*1024*1024 && ($c&0xfff)==0)) { die(\"$helpusage\\n\\nFAIL: pic_offset == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{pic}{pic_size}; if (!($c==32 || $c==64 || $c==128 || $c==256)) { die(\"$helpusage\\n\\nFAIL: pic_size == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{pic}{pic_total_int}; if ( $c<1 || $c>255) { die(\"$helpusage\\n\\nFAIL: pic_total_int == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{icache}{icache_num_bypass}; if ($c<1 || $c>8) { die(\"$helpusage\\n\\nFAIL: icache_num_bypass == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{icache}{icache_bypass_enable}; if (!($c==0 || $c==1)) { die(\"$helpusage\\n\\nFAIL: icache_bypass_enable == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{icache}{icache_tag_num_bypass}; if ($c<1 || $c>8) { die(\"$helpusage\\n\\nFAIL: icache_tag_num_bypass == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{icache}{icache_tag_bypass_enable}; if (!($c==0 || $c==1)) { die(\"$helpusage\\n\\nFAIL: icache_tag_bypass_enable == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{icache}{icache_enable}; if (!($c==0 || $c==1)) { die(\"$helpusage\\n\\nFAIL: icache_enable == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{icache}{icache_waypack}; if (!($c==0 || $c==1)) { die(\"$helpusage\\n\\nFAIL: icache_waypack == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{icache}{icache_num_ways}; if (!($c==2 || $c==4)) { die(\"$helpusage\\n\\nFAIL: icache_num_ways == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{icache}{icache_ln_sz}; if (!($c==32 || $c==64)) { die(\"$helpusage\\n\\nFAIL: icache_ln_sz == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{icache}{icache_size}; if (!($c==8 || $c==16 || $c==32 || $c==64 || $c==128 || $c==256)) { die(\"$helpusage\\n\\nFAIL: icache_size == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{core}{div_bit}; if (!($c==1 || $c==2 || $c==3 || $c==4 )) { die(\"$helpusage\\n\\nFAIL: div_bit == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{core}{div_new}; if (!($c==0 || $c==1)) { die(\"$helpusage\\n\\nFAIL: div_new == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{core}{lsu_stbuf_depth}; if (!($c==2 || $c==4 || $c==8)) { die(\"$helpusage\\n\\nFAIL: lsu_stbuf_depth == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{core}{dma_buf_depth}; if (!($c==2 || $c==4 || $c==5)) { die(\"$helpusage\\n\\nFAIL: dma_buf_depth == $c ILLEGAL !!!\\n\\n\"); }\n$c=$config{core}{lsu_num_nbload}; if (!($c==2 || $c==4 || $c==8)) { die(\"$helpusage\\n\\nFAIL: lsu_num_nbload == $c ILLEGAL !!!\\n\\n\"); }\n\n\n# force div_bit to be 1 for old div algorithm\nif ($config{core}{div_new}==0 && $config{core}{div_bit}!=1) {\n die(\"$helpusage\\n\\nFAIL: div_new=0 requires div_bit=1 ILLEGAL !!!\\n\\n\");\n}\n\n$c=$config{protection}{pmp_entries}; if (!($c==64 || $c==16 || $c==0)) { die(\"$helpusage\\n\\nFAIL: pmp_entries must be either 0, 16 or 64 !!!\\n\\n\"); }\n$c=$config{protection}{lockstep_delay}; if ($config{protection}{lockstep_enable} && ($c<2 || $c>4)) { die(\"$helpusage\\n\\nFAIL: lockstep_delay must fit in range <2, 4> !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_addr0}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr0 lower 6b must be 0s $c !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_addr1}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr1 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_addr2}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr2 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_addr3}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr3 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_addr4}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr4 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_addr5}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr5 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_addr6}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr6 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_addr7}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr7 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_mask0}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: inst_access_mask0 invalid !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_mask1}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: inst_access_mask1 invalid !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_mask2}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: inst_access_mask2 invalid !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_mask3}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: inst_access_mask3 invalid !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_mask4}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: inst_access_mask4 invalid !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_mask5}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: inst_access_mask5 invalid !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_mask6}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: inst_access_mask6 invalid !!!\\n\\n\"); }\n$c=$config{protection}{inst_access_mask7}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: inst_access_mask7 invalid !!!\\n\\n\"); }\n$c=$config{protection}{data_access_addr0}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: data_access_addr0 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{data_access_addr1}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: data_access_addr1 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{data_access_addr2}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: data_access_addr2 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{data_access_addr3}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: data_access_addr3 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{data_access_addr4}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: data_access_addr4 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{data_access_addr5}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: data_access_addr5 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{data_access_addr6}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: data_access_addr6 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{data_access_addr7}; if ((hex($c)&0x3f) != 0) { die(\"$helpusage\\n\\nFAIL: data_access_addr7 lower 6b must be 0s !!!\\n\\n\"); }\n$c=$config{protection}{data_access_mask0}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: data_access_mask0 invalid !!!\\n\\n\"); }\n$c=$config{protection}{data_access_mask1}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: data_access_mask1 invalid !!!\\n\\n\"); }\n$c=$config{protection}{data_access_mask2}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: data_access_mask2 invalid !!!\\n\\n\"); }\n$c=$config{protection}{data_access_mask3}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: data_access_mask3 invalid !!!\\n\\n\"); }\n$c=$config{protection}{data_access_mask4}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: data_access_mask4 invalid !!!\\n\\n\"); }\n$c=$config{protection}{data_access_mask5}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: data_access_mask5 invalid !!!\\n\\n\"); }\n$c=$config{protection}{data_access_mask6}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: data_access_mask6 invalid !!!\\n\\n\"); }\n$c=$config{protection}{data_access_mask7}; if ((hex($c)&0x3f) != 63 || invalid_mask($c)) { die(\"$helpusage\\n\\nFAIL: data_access_mask7 invalid !!!\\n\\n\"); }\n\nif ((hex($config{protection}{inst_access_addr0}) & hex($config{protection}{inst_access_mask0}))!=0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr0 and inst_access_mask0 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{inst_access_addr1}) & hex($config{protection}{inst_access_mask1}))!=0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr1 and inst_access_mask1 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{inst_access_addr2}) & hex($config{protection}{inst_access_mask2}))!=0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr2 and inst_access_mask2 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{inst_access_addr3}) & hex($config{protection}{inst_access_mask3}))!=0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr3 and inst_access_mask3 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{inst_access_addr4}) & hex($config{protection}{inst_access_mask4}))!=0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr4 and inst_access_mask4 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{inst_access_addr5}) & hex($config{protection}{inst_access_mask5}))!=0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr5 and inst_access_mask5 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{inst_access_addr6}) & hex($config{protection}{inst_access_mask6}))!=0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr6 and inst_access_mask6 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{inst_access_addr7}) & hex($config{protection}{inst_access_mask7}))!=0) { die(\"$helpusage\\n\\nFAIL: inst_access_addr7 and inst_access_mask7 must be orthogonal!!!\\n\\n\"); }\n\nif ((hex($config{protection}{data_access_addr0}) & hex($config{protection}{data_access_mask0}))!=0) { die(\"$helpusage\\n\\nFAIL: data_access_addr0 and data_access_mask0 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{data_access_addr1}) & hex($config{protection}{data_access_mask1}))!=0) { die(\"$helpusage\\n\\nFAIL: data_access_addr1 and data_access_mask1 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{data_access_addr2}) & hex($config{protection}{data_access_mask2}))!=0) { die(\"$helpusage\\n\\nFAIL: data_access_addr2 and data_access_mask2 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{data_access_addr3}) & hex($config{protection}{data_access_mask3}))!=0) { die(\"$helpusage\\n\\nFAIL: data_access_addr3 and data_access_mask3 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{data_access_addr4}) & hex($config{protection}{data_access_mask4}))!=0) { die(\"$helpusage\\n\\nFAIL: data_access_addr4 and data_access_mask4 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{data_access_addr5}) & hex($config{protection}{data_access_mask5}))!=0) { die(\"$helpusage\\n\\nFAIL: data_access_addr5 and data_access_mask5 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{data_access_addr6}) & hex($config{protection}{data_access_mask6}))!=0) { die(\"$helpusage\\n\\nFAIL: data_access_addr6 and data_access_mask6 must be orthogonal!!!\\n\\n\"); }\nif ((hex($config{protection}{data_access_addr7}) & hex($config{protection}{data_access_mask7}))!=0) { die(\"$helpusage\\n\\nFAIL: data_access_addr7 and data_access_mask7 must be orthogonal!!!\\n\\n\"); }\n\n\n# Fill in derived configuration entries.\n\nif (($config{icache}{icache_enable}==0 || grep(/icache_enable/, @unsets)) && $config{iccm}{iccm_enable}==0) {\n $config{core}{no_iccm_no_icache}=1;\n}\nelsif (($config{icache}{icache_enable}==0 || grep(/icache_enable/, @unsets)) && $config{iccm}{iccm_enable}==1) {\n $config{core}{iccm_only}=1;\n}\nelsif ($config{icache}{icache_enable}==1 && $config{iccm}{iccm_enable}==0) {\n $config{core}{icache_only}=1;\n}\nelsif ($config{icache}{icache_enable}==1 && $config{iccm}{iccm_enable}==1) {\n $config{core}{iccm_icache}=1;\n}\n\nif (!$config{dccm}{dccm_enable}) {\n $config{core}{fast_interrupt_redirect} = 0;\n print \"$self: Disabling fast_interrupt_redirect because DCCM not enabled\\n\";\n}\n\n\n\n$config{btb}{btb_btag_fold} = 0;\n$config{btb}{btb_fold2_index_hash} = 0;\n$config{btb}{btb_btag_size} = 31;\n\nif($config{btb}{btb_size}==512){\n $config{btb}{btb_index1_hi} = 9;\n $config{btb}{btb_index2_hi} = 17;\n $config{btb}{btb_index3_hi} = 25;\n $config{btb}{btb_array_depth}= 256;\n $config{btb}{btb_btag_size} = 5;\n} elsif($config{btb}{btb_size}==256){\n $config{btb}{btb_index1_hi} = 8;\n $config{btb}{btb_index2_hi} = 15;\n $config{btb}{btb_index3_hi} = 22;\n $config{btb}{btb_array_depth}= 128;\n $config{btb}{btb_btag_size} = 6;\n} elsif($config{btb}{btb_size}==128){\n $config{btb}{btb_index1_hi} = 7;\n $config{btb}{btb_index2_hi} = 13;\n $config{btb}{btb_index3_hi} = 19;\n $config{btb}{btb_array_depth}= 64;\n $config{btb}{btb_btag_size} = 7;\n} elsif($config{btb}{btb_size}==64){\n $config{btb}{btb_index1_hi} = 6;\n $config{btb}{btb_index2_hi} = 11;\n $config{btb}{btb_index3_hi} = 16;\n $config{btb}{btb_array_depth}= 32;\n $config{btb}{btb_btag_size} = 8;\n} elsif($config{btb}{btb_size}==32){\n $config{btb}{btb_index1_hi} = 5;\n $config{btb}{btb_index2_hi} = 9;\n $config{btb}{btb_index3_hi} = 13;\n $config{btb}{btb_array_depth}= 16;\n $config{btb}{btb_btag_size} = 9 unless $config{btb}{btb_fullya};\n $config{btb}{btb_btag_fold} = 1;\n} elsif($config{btb}{btb_size}<32){\n #verif issues require these even though they are not needed\n $config{btb}{btb_index1_hi} = 5;\n $config{btb}{btb_index2_hi} = 8;\n $config{btb}{btb_index3_hi} = 11;\n $config{btb}{btb_fullya} = 1;\n}\n\n$config{btb}{btb_index2_lo} = $config{btb}{btb_index1_hi}+1;\n$config{btb}{btb_index3_lo} = $config{btb}{btb_index2_hi}+1;\n$config{btb}{btb_addr_hi} = $config{btb}{btb_index1_hi};\n\nif($config{bht}{bht_size}==2048){\n $config{bht}{bht_ghr_size}= 10;\n $config{bht}{bht_ghr_range}= \"9:0\";\n $config{bht}{bht_array_depth}= 1024;\n $config{bht}{bht_addr_hi}= 11;\n} elsif($config{bht}{bht_size}==1024){\n $config{bht}{bht_ghr_size}= 9;\n $config{bht}{bht_ghr_range}= \"8:0\";\n $config{bht}{bht_array_depth}= 512;\n $config{bht}{bht_addr_hi}= 10;\n} elsif($config{bht}{bht_size}==512){\n $config{bht}{bht_ghr_size}= 8;\n $config{bht}{bht_ghr_range}= \"7:0\";\n $config{bht}{bht_array_depth}= 256;\n $config{bht}{bht_addr_hi}= 9;\n} elsif($config{bht}{bht_size}==256){\n $config{bht}{bht_ghr_size}= 7;\n $config{bht}{bht_ghr_range}= \"6:0\";\n $config{bht}{bht_addr_hi} = 8;\n $config{bht}{bht_array_depth}= 128;\n} elsif($config{bht}{bht_size}==128){\n $config{bht}{bht_ghr_size}= 6;\n $config{bht}{bht_ghr_range}= \"5:0\";\n $config{bht}{bht_addr_hi} = 7;\n $config{bht}{bht_array_depth}= 64;\n} elsif($config{bht}{bht_size}==64){\n $config{bht}{bht_ghr_size}= 5;\n $config{bht}{bht_ghr_range}= \"4:0\";\n $config{bht}{bht_addr_hi} = 6;\n $config{bht}{bht_array_depth}= 32;\n} elsif($config{bht}{bht_size}==32){\n $config{bht}{bht_ghr_size}= 4;\n $config{bht}{bht_ghr_range}= \"3:0\";\n $config{bht}{bht_addr_hi} = 5;\n $config{bht}{bht_array_depth}= 16;\n}\n$config{bht}{bht_ghr_hash_1} = ($config{bht}{bht_ghr_size} > ($config{btb}{btb_index1_hi}-1));\n\n$config{bht}{bht_hash_string} = &ghrhash($config{btb}{btb_index1_hi}, $config{bht}{bht_ghr_size});\n\n\n\n\n# PIC derived\n$config{pic}{pic_base_addr} = (hex($config{pic}{pic_region})<<28) +\n (hex($config{pic}{pic_offset}));\n$config{pic}{pic_base_addr} = sprintf(\"0x%x\", $config{pic}{pic_base_addr});\n\n$config{pic}{pic_int_words} = int($config{pic}{pic_total_int}/32 +0.9);\n$config{pic}{pic_bits} = 10 + log2($config{pic}{pic_size});\n\n$config{pic}{pic_total_int_plus1} = $config{pic}{pic_total_int} + 1;\n$config{pic}{pic_meipl_count} = $config{pic}{pic_total_int};\n$config{pic}{pic_meip_count} = $config{pic}{pic_int_words};\n$config{pic}{pic_meie_count} = $config{pic}{pic_total_int};\n$config{pic}{pic_meipt_count} = $config{pic}{pic_total_int};\n$config{pic}{pic_meigwctrl_count} = $config{pic}{pic_total_int};\n$config{pic}{pic_meigwclr_count} = $config{pic}{pic_total_int};\n\n$config{icache}{icache_num_bypass_width} = int(log2($config{icache}{icache_num_bypass})) + 1;\n$config{icache}{icache_tag_num_bypass_width} = int(log2($config{icache}{icache_tag_num_bypass})) + 1;\n\n$config{core}{lsu_num_nbload_width} = log2($config{core}{lsu_num_nbload});\n\n$config{bus}{lsu_bus_tag} = log2($config{core}{lsu_num_nbload}) + 1;\n\n$config{bus}{ifu_bus_tag} = log2($config{icache}{icache_ln_sz}/8);\n\n$config{dccm}{dccm_sadr} = (hex($config{dccm}{dccm_region})<<28) +\n (hex($config{dccm}{dccm_offset}));\n$config{dccm}{dccm_sadr} = sprintf(\"0x%x\", $config{dccm}{dccm_sadr});\n\n$config{dccm}{dccm_eadr} = (hex($config{dccm}{dccm_region})<<28) +\n (hex($config{dccm}{dccm_offset})) + size($config{dccm}{dccm_size})-1;\n$config{dccm}{dccm_eadr} = sprintf(\"0x%x\", $config{dccm}{dccm_eadr});\n\n$config{dccm}{dccm_reserved} = sprintf(\"0x%x\", ($config{dccm}{dccm_size}>=16)? 5120 : ($config{dccm}{dccm_size}*1024)/4);\n\n$config{dccm}{dccm_bits} = ($config{dccm}{dccm_size}==48 ) ? 16 : 10 + log2($config{dccm}{dccm_size});\n\n$config{dccm}{dccm_bank_bits} = log2($config{dccm}{dccm_num_banks});\n$config{dccm}{dccm_data_width} = 32;\n$config{dccm}{dccm_fdata_width} = $config{dccm}{dccm_data_width} + log2($config{dccm}{dccm_data_width}) + 2;\n$config{dccm}{dccm_byte_width} = $config{dccm}{dccm_data_width}/8;\n\n$config{dccm}{dccm_width_bits} = log2($config{dccm}{dccm_byte_width});\n$config{dccm}{dccm_index_bits} = $config{dccm}{dccm_bits} - $config{dccm}{dccm_bank_bits} - $config{dccm}{dccm_width_bits};\n\n$config{dccm}{dccm_ecc_width} = log2($config{dccm}{dccm_data_width}) + 2;\n$config{dccm}{lsu_sb_bits} = $config{dccm}{dccm_bits};\n$config{dccm}{dccm_rows} = ($config{dccm}{dccm_size}==48 ) ? (2**($config{dccm}{dccm_index_bits}-1) + 2**$config{dccm}{dccm_index_bits})/2 : 2**$config{dccm}{dccm_index_bits};\n$config{dccm}{dccm_data_cell} = \"ram_$config{dccm}{dccm_rows}x39\";\n\n\n$config{icache}{icache_num_lines} = $config{icache}{icache_size}*1024/$config{icache}{icache_ln_sz};\n$config{icache}{icache_num_lines_way} = $config{icache}{icache_num_lines}/$config{icache}{icache_num_ways};\n$config{icache}{icache_num_lines_bank} = $config{icache}{icache_num_lines}/($config{icache}{icache_num_ways} * $config{icache}{icache_banks_way});\n$config{icache}{icache_data_depth} = $config{icache}{icache_num_lines_bank} * $config{icache}{icache_ln_sz} /$config{icache}{icache_bank_width};\n$config{icache}{icache_data_index_lo} = log2($config{icache}{icache_bank_width}) + log2($config{icache}{icache_banks_way});\n$config{icache}{icache_index_hi} = $config{icache}{icache_data_index_lo} + log2($config{icache}{icache_data_depth}) -1;\n$config{icache}{icache_bank_hi} = $config{icache}{icache_data_index_lo} - 1;\n$config{icache}{icache_bank_lo} = log2($config{icache}{icache_bank_width});\n$config{icache}{icache_tag_index_lo} = log2($config{icache}{icache_ln_sz});\n$config{icache}{icache_tag_lo} = log2($config{icache}{icache_num_lines_way}) + $config{icache}{icache_tag_index_lo};\n$config{icache}{icache_tag_depth} = $config{icache}{icache_num_lines}/$config{icache}{icache_num_ways};\n$config{icache}{icache_data_width} = 8*$config{icache}{icache_bank_width};\n\n$config{icache}{icache_bank_bits} = 1+$config{icache}{icache_bank_hi}-$config{icache}{icache_bank_lo};\n$config{icache}{icache_status_bits} = $config{icache}{icache_num_ways}-1;\n$config{icache}{icache_num_beats} = ($config{icache}{icache_ln_sz}==64) ? 8 : 4;\n$config{icache}{icache_beat_bits} = ($config{icache}{icache_ln_sz}==64) ? 3 : 2;\n$config{icache}{icache_scnd_last} = ($config{icache}{icache_ln_sz}==64) ? 6 : 2;\n$config{icache}{icache_beat_addr_hi} = ($config{icache}{icache_ln_sz}==64) ? 5 : 4;\n\n\nif (($config{icache}{icache_ecc})) {\n$config{icache}{icache_fdata_width} = $config{icache}{icache_data_width} + 7;\n$config{icache}{icache_data_cell} = \"ram_$config{icache}{icache_data_depth}x$config{icache}{icache_fdata_width}\";\n$config{icache}{icache_tag_cell} = ($config{icache}{icache_tag_depth} == 32) ? \"ram_$config{icache}{icache_tag_depth}x26\" : \"ram_$config{icache}{icache_tag_depth}x25\";\n\n}\nelse {\n$config{icache}{icache_fdata_width} = $config{icache}{icache_data_width} + 4;\n$config{icache}{icache_data_cell} = \"ram_$config{icache}{icache_data_depth}x$config{icache}{icache_fdata_width}\";\n$config{icache}{icache_tag_cell} = \"ram_$config{icache}{icache_tag_depth}x21\";\n}\n$config{pic}{pic_total_int_plus1} = $config{pic}{pic_total_int} + 1;\n# Defines with explicit values in the macro name\n$config{dccm}{\"dccm_num_banks_$config{dccm}{dccm_num_banks}\"} = \"\";\n$config{dccm}{\"dccm_size_$config{dccm}{dccm_size}\"} = \"\";\n\n# If ICCM offset not explicitly provided, align to TOP of the region\nif ($top_align_iccm && ($config{iccm}{iccm_offset} eq $iccm_offset) && ($config{iccm}{iccm_size} < 32)) {\n $config{iccm}{iccm_region} = \"0xa\";\n print \"$self: Setting default iccm region to region $config{iccm}{iccm_region}\\n\";\n $config{iccm}{iccm_offset} = sprintf(\"0x%08x\",256*1024*1024-size($config{iccm}{iccm_size}));\n print \"$self: Aligning default iccm offset to top of region @ $config{iccm}{iccm_offset}\\n\";\n}\n$config{iccm}{iccm_sadr} = (hex($config{iccm}{iccm_region})<<28) +\n (hex($config{iccm}{iccm_offset}));\n$config{iccm}{iccm_sadr} = sprintf(\"0x%08x\", $config{iccm}{iccm_sadr});\n\n$config{iccm}{iccm_eadr} = (hex($config{iccm}{iccm_region})<<28) +\n (hex($config{iccm}{iccm_offset})) + size($config{iccm}{iccm_size})-1;\n$config{iccm}{iccm_eadr} = sprintf(\"0x%08x\", $config{iccm}{iccm_eadr});\n\n$config{iccm}{iccm_reserved} = sprintf(\"0x%x\", ($config{iccm}{iccm_size}>30)? 4096 : ($config{iccm}{iccm_size}*1024)/4);\n\n$config{iccm}{iccm_bits} = 10 + log2($config{iccm}{iccm_size});\n$config{iccm}{iccm_bank_bits} = log2($config{iccm}{iccm_num_banks}); //-1;\n$config{iccm}{iccm_index_bits} = $config{iccm}{iccm_bits} - $config{iccm}{iccm_bank_bits} - 2; # always 4 bytes\n$config{iccm}{iccm_rows} = 2**$config{iccm}{iccm_index_bits};\n$config{iccm}{iccm_data_cell} = \"ram_$config{iccm}{iccm_rows}x39\";\n\n$config{iccm}{iccm_bank_hi} = 2+$config{iccm}{iccm_bank_bits}-1;\n$config{iccm}{iccm_bank_index_lo} = 1+$config{iccm}{iccm_bank_hi};\n\n# Defines with explicit values in the macro name\n$config{iccm}{\"iccm_num_banks_$config{iccm}{iccm_num_banks}\"} = \"\";\n$config{iccm}{\"iccm_size_$config{iccm}{iccm_size}\"} = \"\";\n\n# Track used regions\n\n$regions_used{hex($config{iccm}{iccm_region})} = 1;\n$regions_used{hex($config{dccm}{dccm_region})} = 1;\n$regions_used{hex($config{pic}{pic_region})} = 1;\n$regions_used{hex($config{reset_vec})>>28} = 1;\n\n# Find an unused region for serial IO\nfor (my $rgn = 15;$rgn >= 0; $rgn--) {\n if (($rgn != hex($config{iccm}{iccm_region})) &&\n ($rgn != hex($config{dccm}{dccm_region})) &&\n ($rgn != (hex($config{pic}{pic_region})))) {\n $config{memmap}{serialio} = ($rgn << 28) + (22<<18);\n $regions_used{$rgn} = 1;\n last;\n }\n}\n\n$config{memmap}{serialio} = sprintf(\"0x%08x\", $config{memmap}{serialio});\n\n# Find an unused region for external data\nfor (my $rgn = 15;$rgn >= 0; $rgn--) {\n if (($rgn != hex($config{iccm}{iccm_region})) &&\n ($rgn != hex($config{dccm}{dccm_region})) &&\n ($rgn != (hex($config{memmap}{serialio})>>28)) &&\n ($rgn != (hex($config{pic}{pic_region})))) {\n $config{memmap}{external_data} = ($rgn << 28) + (22<<18);\n $regions_used{$rgn} = 1;\n last;\n }\n}\n$config{memmap}{external_data} = sprintf(\"0x%08x\", $config{memmap}{external_data});\n#\n\n# Unused region for second data\nfor (my $rgn = 15;$rgn >= 0; $rgn--) {\n if (($rgn != hex($config{iccm}{iccm_region})) &&\n ($rgn != hex($config{dccm}{dccm_region})) &&\n ($rgn != (hex($config{memmap}{serialio})>>28)) &&\n ($rgn != (hex($config{memmap}{external_data})>>28)) &&\n ($rgn != (hex($config{pic}{pic_region})))) {\n $config{memmap}{external_data_1} = ($rgn << 28);\n $regions_used{$rgn} = 1;\n last;\n }\n}\n$config{memmap}{external_data_1} = sprintf(\"0x%08x\", $config{memmap}{external_data_1});\n\n\n#$config{memmap}{consoleio} = hex($config{memmap}{serialio}) + 0x100;\n#$config{memmap}{consoleio} = sprintf(\"0x%x\", $config{memmap}{consoleio});\n\n# Find an unused region for debug_sb_memory data\nfor (my $rgn = 15;$rgn >= 0; $rgn--) {\n if (($rgn != hex($config{iccm}{iccm_region})) &&\n ($rgn != hex($config{dccm}{dccm_region})) &&\n ($rgn != (hex($config{memmap}{serialio})>>28)) &&\n ($rgn != (hex($config{memmap}{external_data})>>28)) &&\n ($rgn != (hex($config{memmap}{external_data_1})>>28)) &&\n ($rgn != (hex($config{pic}{pic_region})))) {\n $config{memmap}{debug_sb_mem} = ($rgn << 28) + (22<<18);\n $regions_used{$rgn} = 1;\n last;\n }\n}\n$config{memmap}{debug_sb_mem} = sprintf(\"0x%08x\", $config{memmap}{debug_sb_mem});\n\n\n# Create the memory map hole for random testing\n# Only do this if masks are not enabled already\nif (hex($config{protection}{data_access_enable0}) > 0 ||\n hex($config{protection}{data_access_enable1}) > 0 ||\n hex($config{protection}{data_access_enable2}) > 0 ||\n hex($config{protection}{data_access_enable3}) > 0 ||\n hex($config{protection}{data_access_enable4}) > 0 ||\n hex($config{protection}{data_access_enable5}) > 0 ||\n hex($config{protection}{data_access_enable6}) > 0 ||\n hex($config{protection}{data_access_enable7}) > 0 ||\n hex($config{protection}{inst_access_enable0}) > 0 ||\n hex($config{protection}{inst_access_enable1}) > 0 ||\n hex($config{protection}{inst_access_enable2}) > 0 ||\n hex($config{protection}{inst_access_enable3}) > 0 ||\n hex($config{protection}{inst_access_enable4}) > 0 ||\n hex($config{protection}{inst_access_enable5}) > 0 ||\n hex($config{protection}{inst_access_enable6}) > 0 ||\n hex($config{protection}{inst_access_enable7}) > 0 ||\n $config{memmap}{external_mem_hole} eq \"default disabled\"){\n delete($config{memmap}{external_mem_hole}) ;\n} else {\n # Unused region to create a memory map hole, if not already specified\n if ($config{memmap}{external_mem_hole} eq 'derived, overridable') {\n for (my $rgn = 15;$rgn >= 0; $rgn--) {\n if (!defined($regions_used{$rgn})) {\n $config{memmap}{external_mem_hole} = ($rgn << 28);\n $regions_used{$rgn} = 1;\n last;\n }\n }\n } else {\n my $rgn = hex($config{memmap}{external_mem_hole})>>28;\n $config{memmap}{external_mem_hole} = ($rgn << 28);\n $regions_used{$rgn} =1;\n }\n my $hreg = $config{memmap}{external_mem_hole}>>28;\n $config{protection}{data_access_addr0} = sprintf(\"0x%x\", (($hreg^8)&8)<<28);\n $config{protection}{data_access_mask0} = \"0x7fffffff\";\n $config{protection}{data_access_addr1} = sprintf(\"0x%x\", ($hreg&8) << 28 |(($hreg^4)&4)<<28);\n $config{protection}{data_access_mask1} = \"0x3fffffff\";\n $config{protection}{data_access_addr2} = sprintf(\"0x%x\", ($hreg&12) <<28 | (($hreg^2)&2) <<28);\n $config{protection}{data_access_mask2} = \"0x1fffffff\";\n $config{protection}{data_access_addr3} = sprintf(\"0x%x\", ($hreg&14) << 28 |(($hreg^1)&1)<<28);\n $config{protection}{data_access_mask3} = \"0x0fffffff\";\n $config{protection}{data_access_enable0} = \"1\";\n $config{protection}{data_access_enable1} = \"1\";\n $config{protection}{data_access_enable2} = \"1\";\n $config{protection}{data_access_enable3} = \"1\";\n $config{protection}{inst_access_addr0} = sprintf(\"0x%x\", (($hreg^8)&8)<<28);\n $config{protection}{inst_access_mask0} = \"0x7fffffff\";\n $config{protection}{inst_access_addr1} = sprintf(\"0x%x\", ($hreg&8) << 28 |(($hreg^4)&4)<<28);\n $config{protection}{inst_access_mask1} = \"0x3fffffff\";\n $config{protection}{inst_access_addr2} = sprintf(\"0x%x\", ($hreg&12) <<28 | (($hreg^2)&2) <<28);\n $config{protection}{inst_access_mask2} = \"0x1fffffff\";\n $config{protection}{inst_access_addr3} = sprintf(\"0x%x\", ($hreg&14) << 28 |(($hreg^1)&1)<<28);\n $config{protection}{inst_access_mask3} = \"0x0fffffff\";\n $config{protection}{inst_access_enable0} = \"1\";\n $config{protection}{inst_access_enable1} = \"1\";\n $config{protection}{inst_access_enable2} = \"1\";\n $config{protection}{inst_access_enable3} = \"1\";\n\n $config{memmap}{external_mem_hole} = sprintf(\"0x%08x\", $config{memmap}{external_mem_hole});\n}\n\n#Define 5 unused regions for used in TG\n\nmy $unrg = 0;\nforeach my $unr (reverse(0 .. 15)) {\n if (!defined($regions_used{$unr})) {\n $config{memmap}{\"unused_region$unrg\"} = sprintf(\"0x%08x\",($unr << 28));\n $regions_used{$unr} = 1;\n $unrg++;\n }\n}\n\nif ($target eq \"baseline\") {\n $config{reset_vec} = $config{iccm}{iccm_sadr};\n $config{testbench}{magellan} = 1;\n print \"$self: Setting reset_vec = ICCM start address for Baseline\\n\";\n}\n\n\n# Output bit-width specifiers for these variables\nour %widths = (\n \"dccm_region\" => \"4\",\n \"dccm_offset\" => \"28\",\n \"dccm_sadr\" => \"32\",\n \"dccm_eadr\" => \"32\",\n \"pic_region\" => \"4\",\n \"pic_offset\" => \"10\",\n \"pic_base_addr\" => \"32\",\n \"iccm_region\" => \"4\",\n \"iccm_offset\" => \"10\",\n \"iccm_sadr\" => \"32\",\n \"iccm_eadr\" => \"32\",\n \"bus_prty_default\" => \"2\",\n \"inst_access_enable0\" => \"1\",\n \"inst_access_enable1\" => \"1\",\n \"inst_access_enable2\" => \"1\",\n \"inst_access_enable3\" => \"1\",\n \"inst_access_enable4\" => \"1\",\n \"inst_access_enable5\" => \"1\",\n \"inst_access_enable6\" => \"1\",\n \"inst_access_enable7\" => \"1\",\n \"data_access_enable0\" => \"1\",\n \"data_access_enable1\" => \"1\",\n \"data_access_enable2\" => \"1\",\n \"data_access_enable3\" => \"1\",\n \"data_access_enable4\" => \"1\",\n \"data_access_enable5\" => \"1\",\n \"data_access_enable6\" => \"1\",\n \"data_access_enable7\" => \"1\",\n);\n#}}}\n\nmy $d=$config{protection}{lockstep_enable}; if ($d==0 || !grep(/lockstep_enable=1/, @sets)) { delete $config{\"protection\"}{\"lockstep_enable\"}; }\n$c=$config{protection}{lockstep_delay}; if ($d==0 || ($c==0 && !grep(/lockstep_delay=/, @sets))) { delete $config{\"protection\"}{\"lockstep_delay\"}; }\n$c=$config{protection}{lockstep_regfile_enable}; if ($d==0 || ($c==0 || !grep(/lockstep_regfile_enable=/, @sets))) { delete $config{\"protection\"}{\"lockstep_regfile_enable\"}; }\n\nprint \"\\nVeeR configuration for target=$target\\n\\n\";\ndump_define(\"\",\"\", \\%config,[]);\n\n\n#print Dumper(\\%config);\n#print Dumper(\\%width);\n\n#print Dumper(\\%sets);\n#print Dumper(\\%unsets);\n\n# Sanity checks\n\n# Do not allow Smepmp to be enabled when user mode is disabled\n# TODO: Allowing this combination would require adding additional CSR decoder\n# variants.\nif(( $config{core}{user_mode} eq 0 ) && ( $config{protection}{smepmp} eq 1 )) {\n die \"$self: ERROR! Currently Smepmp feature cannot be enabled when user mode support is disabled\\n\";\n}\n\ncheck_addr_align(\"dccm\", hex($config{dccm}{dccm_sadr}), $config{dccm}{dccm_size}*1024);\ncheck_addr_align(\"iccm\", hex($config{iccm}{iccm_sadr}), $config{iccm}{iccm_size}*1024);\ncheck_addr_align(\"pic\", hex($config{pic}{pic_base_addr}), $config{pic}{pic_size}*1024);\n\n# Prevent overlap of internal memories\nif ((hex($config{pic}{pic_region}) == hex($config{iccm}{iccm_region})) && (hex($config{pic}{pic_offset}) == hex($config{iccm}{iccm_offset}))) {\n die \"$self: ERROR! PIC and ICCM blocks collide (region $config{iccm}{iccm_region}, offset $config{pic}{pic_offset})!\\n\";\n}\nif ((hex($config{pic}{pic_region}) == hex($config{dccm}{dccm_region})) && (hex($config{pic}{pic_offset}) == hex($config{dccm}{dccm_offset}))) {\n die \"$self: ERROR! PIC and DCCM blocks collide (region $config{dccm}{dccm_region}, offset $config{pic}{pic_offset})!\\n\";\n}\nif ((hex($config{iccm}{iccm_region}) == hex($config{dccm}{dccm_region})) && (hex($config{iccm}{iccm_offset}) == hex($config{dccm}{dccm_offset}))) {\n die \"$self: ERROR! ICCM and DCCM blocks collide (region $config{iccm}{iccm_region}, offset $config{dccm}{dccm_offset})!\\n\";\n}\n\n#printf( \"axi4 %s\\n\",$config{\"testbench\"}{\"build_axi4\"});\n#printf( \"ahb_lite %s\\n\",$config{\"testbench\"}{\"build_ahb_lite\"});\n#printf( \"axi_native %s\\n\",$config{\"testbench\"}{\"build_axi_native\"});\n\nif( $target eq \"el2_formal_axi\" ) {\n $config{testbench}{build_axi_native} = 1;\n $config{testbench}{build_axi4} = 1;\n print( \"\\$config{testbench}{build_axi_native} = $config{testbench}{build_axi_native} \\n\" );\n print( \"\\$config{testbench}{build_axi4 } = $config{testbench}{build_axi4 } \\n\" );\n}\n\n\nif (($config{testbench}{build_ahb_lite} == 1)) {\n delete $config{testbench}{build_axi4};\n $config{testbench}{build_axi_native}=1;\n $verilog_parms{build_axi4} = 0;\n}\nelsif (($config{testbench}{build_axi4} == 1)) {\n $config{testbench}{build_axi_native}=1;\n delete $config{testbench}{build_ahb_lite};\n $verilog_parms{build_ahb_lite} = 0;\n}\nelsif (($config{testbench}{build_axi_native} == 1)) {\n die(\"illegal to set build_axi_native w/out build_axi4\");\n}\n\n#printf( \"axi4 %s\\n\",$config{\"testbench\"}{\"build_axi4\"});\n#printf( \"ahb_lite %s\\n\",$config{\"testbench\"}{\"build_ahb_lite\"});\n#printf( \"axi_native %s\\n\",$config{\"testbench\"}{\"build_axi_native\"});\n\n\n# Over-ride MFDC reset value for AXI.\n# Disable Bus barrier and 64b for AXI\nif (defined($config{\"testbench\"}{\"build_axi_native\"}) && ($config{\"testbench\"}{\"build_axi_native\"} ne \"0\")) {\n if (! (defined($config{testbench}{build_ahb_lite}) && $config{testbench}{build_ahb_lite} ne \"0\")) {\n $config{csr}{mfdc}{reset} = \"0x00070040\" if exists $config{csr}{mfdc};\n }\n\n}\n\n\n\n# parm processing before any values are deleted from the hash\n\ndelete $config{core}{fpga_optimize} if ($config{core}{fpga_optimize} == 0);\n\ndelete $config{testbench}{openocd_test} if ($config{testbench}{openocd_test} == 0);\n\n# Remove TECH_SPECIFIC_* defines if they are set to 0\nforeach my $key (sort keys(%config)) {\n if (grep(/tech_specific_/, $key)) {\n if ($config{$key} == 0) {\n delete $config{$key};\n }\n }\n}\n\nprint \"$self: Writing $tdfile\\n\";\nprint \"$self: Writing $paramfile\\n\";\nopen (FILE1, \">$tdfile\") || die \"Cannot open $tdfile for writing $!\\n\";\nopen (FILE2, \">$paramfile\") || die \"Cannot open $paramfile for writing $!\\n\";\nprint_header(\"//\");\ngen_define(\"\",\"`\", \\%config, \\%verilog_parms, \\@verilog_vars);\ndump_parms(\\%verilog_parms);\nclose FILE1;\nclose FILE2;\n\n$config{config_key}=\"32'hdeadbeef\";\n\n# end parms\n\n# deletes\nif (($load_to_use_plus1==0) && !grep(/load_to_use_plus1/, @sets)) { delete $config{\"core\"}{\"load_to_use_plus1\"}; }\nif (($iccm_enable==0) && !grep(/iccm_enable/, @sets)) { delete $config{\"iccm\"}{\"iccm_enable\"}; }\n\n\n# new code to handle the -set=parm=0 value correctly for common_defines.vh\n$c=$config{core}{user_mode}; if ($c==0 && !grep(/user_mode=1/, @sets)) { delete $config{\"core\"}{\"user_mode\"}; }\n$c=$config{core}{load_to_use_plus1}; if ($c==0 && !grep(/load_to_use_plus1=1/, @sets)) { delete $config{\"core\"}{\"load_to_use_plus1\"}; }\n$c=$config{core}{opensource}; if ($c==0 && !grep(/opensource=1/, @sets)) { delete $config{\"core\"}{\"opensource\"}; }\n$c=$config{core}{verilator}; if ($c==0 && !grep(/verilator=1/, @sets)) { delete $config{\"core\"}{\"verilator\"}; }\n$c=$config{core}{div_new}; if ($c==0 && !grep(/div_new=1/, @sets)) { delete $config{\"core\"}{\"div_new\"}; }\n# not needed\n#$c=$config{core}{div_bit}; if ($c==0 && !grep(/div_bit=1/, @sets)) { delete $config{\"core\"}{\"div_bit\"}; }\n$c=$config{iccm}{iccm_enable}; if ($c==0 && !grep(/iccm_enable=1/, @sets)) { delete $config{\"iccm\"}{\"iccm_enable\"}; }\n$c=$config{btb}{btb_enable}; if ($c==0 && !grep(/btb_enable=1/, @sets)) { delete $config{\"btb\"}{\"btb_enable\"}; }\n$c=$config{dccm}{dccm_enable}; if ($c==0 && !grep(/dccm_enable=1/, @sets)) { delete $config{\"dccm\"}{\"dccm_enable\"}; }\n$c=$config{icache}{icache_waypack}; if ($c==0 && !grep(/icache_waypack=1/, @sets)) { delete $config{\"icache\"}{\"icache_waypack\"}; }\n$c=$config{icache}{icache_enable}; if ($c==0 && !grep(/icache_enable=1/, @sets)) { delete $config{\"icache\"}{\"icache_enable\"}; }\n\n$c=$config{icache}{icache_2banks}; if ($c==0 && !grep(/icache_2banks=1/, @sets)) { delete $config{\"icache\"}{\"icache_2banks\"}; }\n$c=$config{pic}{pic_2cycle}; if ($c==0 && !grep(/pic_2cycle=1/, @sets)) { delete $config{\"pic\"}{\"pic_2cycle\"}; }\n\n$c=$config{btb}{btb_fullya}; if ($c==0 && !grep(/btb_fullya=1/, @sets)) { delete $config{\"btb\"}{\"btb_fullya\"}; }\n$c=$config{protection}{smepmp}; if ($c==0 && !grep(/smepmp=1/, @sets)) { delete $config{\"protection\"}{\"smepmp\"}; }\n\n\n\nif ($target eq \"default\") {\n}\nelsif (($config{\"testbench\"}{\"build_axi4\"} == 1)) {\n delete $config{\"testbench\"}{\"build_ahb_lite\"};\n delete $config{\"testbench\"}{\"build_axi_native_ahb\"};\n}\nelsif (($config{\"testbench\"}{\"build_ahb_lite\"} == 1)) {\n delete $config{\"testbench\"}{\"build_axi4\"};\n delete $config{\"testbench\"}{\"build_axi_native\"};\n delete $config{\"testbench\"}{\"build_axi_native_ahb\"};\n}\nelsif (($config{\"testbench\"}{\"build_axi_native_ahb\"} == 1)) {\n delete $config{\"testbench\"}{\"build_axi4\"};\n delete $config{\"testbench\"}{\"build_axi_native_ahb\"};\n}\nelsif (($config{\"testbench\"}{\"build_axi_native\"} == 1)) {\n die(\"illegal to set build_axi_native w/out build_axi4\");\n}\nelse {\n delete $config{\"testbench\"}{\"build_ahb_lite\"};\n delete $config{\"testbench\"}{\"build_axi4\"};\n delete $config{\"testbench\"}{\"build_axi_native\"};\n delete $config{\"testbench\"}{\"build_axi_native_ahb\"};\n}\n\n\n\n\n\n\n##################### Add dumper routines here ##########################\n\n\n#\n# Dump Verilog $RV_ROOT/configs/common_defines.vh\nprint \"$self: Writing $vlogfile\\n\";\nopen (FILE, \">$vlogfile\") || die \"Cannot open $vlogfile for writing $!\\n\";\nprint_header(\"//\");\nbegin_include_guard(\\*FILE, \"`\", \"COMMON_DEFINES\");\nprint FILE \"`define RV_ROOT \\\"\".$ENV{RV_ROOT}.\"\\\"\\n\";\ngen_define(\"\",\"`\", \\%config, \"\", \\@verilog_vars);\nend_include_guard(\\*FILE, \"`\", \"COMMON_DEFINES\");\nclose FILE;\n\nprint \"$self: Writing $asmfile\\n\";\nopen (FILE, \">$asmfile\") || die \"Cannot open $asmfile for writing $!\\n\";\n# Dump ASM/C $RV_ROOT/diags/env/defines.h\nprint_header(\"//\");\nbegin_include_guard(\\*FILE, \"#\", \"DEFINES\");\ngen_define(\"\",\"#\", \\%config, \"\", \\@asm_vars, \\@asm_overridable);\nend_include_guard(\\*FILE, \"#\", \"DEFINES\");\nclose FILE;\n\n# add `define PHYSICAL 1\n# remove `undef RV_ICCM_ENABLE\n\nmy $pddata='\n`include \"common_defines.vh\"\n`undef TEC_RV_ICG\n`define RV_PHYSICAL 1\n';\n\n\nprint \"$self: Writing $pdfile\\n\";\nopen (FILE, \">$pdfile\") || die \"Cannot open $pdfile for writing $!\\n\";\n# Dump PD $RV_ROOT/$RV_ROOT/configs/pd_defines.vh\nprint_header(\"//\");\nprintf (FILE \"$pddata\");\nclose FILE;\n\nprint \"$self: Writing $whisperfile\\n\";\ndump_whisper_config(\\%config, $whisperfile);\n\n\n# PIC address map based on config\n`$ENV{RV_ROOT}/tools/picmap -t $config{pic}{pic_total_int} > $build_path/pic_map_auto.h`;\n\n# Perl vars for use by scripts\nprint \"$self: Writing $perlfile\\n\";\nopen (FILE, \">$perlfile\") || die \"Cannot open $perlfile for writing $!\\n\";\nprint_header(\"# \");\nprint FILE \"# To use this in a perf script, use 'require \\$RV_ROOT/configs/config.pl'\\n\";\nprint FILE \"# Reference the hash via \\$config{name}..\\n\\n\\n\";\nprint FILE Data::Dumper->Dump([\\%config], [ qw(*config) ]);\nprint FILE \"1;\\n\";\nclose FILE;\n\n\n# Default linker script\ngen_default_linker_script();\n\n# Done ##################################################################\n#\nexit(0);\n\n# ###################### Helper subroutines ##########################{{{\n# Convert size in kilobytes to real value\n\nsub size {#{{{\n my $ksize = shift;\n my $size = sprintf(\"%d\",$ksize*1024);\n return $size;\n}#}}}\n\n# Print the defines with prefix\nsub print_define {#{{{\n my ($sym, $key,$value, $override) = @_;\n my $lprefix = $prefix if ($key !~ /$no_prefix/);\n if ($sym eq \"`\") {\n if (defined($widths{$key})) {\n $value =~ s/^(0x)*/$widths{$key}'h/;\n } else {\n $value =~ s/^0x/'h/;\n }\n }\n if ($defines_case eq \"U\") {\n print FILE \"${sym}ifndef \\U$lprefix$key\\E\\n\" if ($override);\n print FILE \"${sym}define \\U$lprefix$key\\E $value\\n\";\n print FILE \"${sym}endif\\n\" if ($override);\n } else {\n print FILE \"${sym}ifndef $lprefix$key\\n\" if ($override);\n print FILE \"${sym}define $lprefix$key $value\\n\";\n print FILE \"${sym}endif\\n\" if ($override);\n }\n}#}}}\n\n# print header\nsub print_header {#{{{\n my $cs = shift;\n print FILE \"$cs NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE\\n\";\n print FILE \"$cs This is an automatically generated file by $ENV{USER} on \",`date`;\n print FILE \"$cs\\n$cs cmd: $self @argv_orig \\n\";\n print FILE \"$cs\\n\";\n}#}}}\n\n# Begins include guard\nsub begin_include_guard {\n my ($fh, $sym, $name) = @_;\n print $fh \"${sym}ifndef $prefix$name\\n\";\n print $fh \"${sym}define $prefix$name\\n\\n\";\n}\n\n# Ends include guard\nsub end_include_guard {\n my ($fh, $sym, $name) = @_;\n print $fh \"\\n${sym}endif // $prefix$name\\n\";\n}\n\n# evaluate derivations\nsub derive {#{{{\n my $eqn = shift;\n return sprintf(\"0x%x\", eval($eqn));\n}#}}}\n\n# traverse the database and extract the key/value pair\nsub gen_define {#{{{\n my $matched = shift;\n my $prefix = shift;\n my $hash = @_[0];\n my $parms = @_[1];\n my @printvars = @{@_[2]};\n my @overridable = @{@_[3]} if defined @_[3];\n my $re = join(\"|\",@printvars);\n $re = qr/($re)/;\n #print Dumper($hash);\n foreach my $key (sort keys %$hash) {\n next if $key eq \"csr\";\n #print \"looking at $key:$matched ($re)\\n\";\n if (defined($unsets{$key})) {\n print \"$self:unsetting $key\\n\";\n delete($config{$key});\n if ($parms and defined($parms->{$key})) {\n $parms->{$key} = 0;\n }\n next\n }\n if (defined($sets{$key}) && $sets{$key} ne $$hash{$key}) {\n if (($$hash{$key} =~ /derived/i) && ($$hash{$key} !~ /overridable/i)) {\n die (\"$self: ERROR! $key is a derived and non-overridable parameter!\\n\");\n } else {\n print \"$self: Overriding $key value $$hash{$key} with $sets{$key}\\n\";\n $$hash{$key} = $sets{$key};\n }\n }\n my $value = $$hash{$key};\n if (ref($value) eq \"HASH\") {\n if ($key =~ /$re/) {\n $matched = 1;\n }\n gen_define($matched,$prefix, $value, $parms, \\@printvars, \\@overridable);\n $matched = 0;\n } elsif (ref($value) eq \"ARRAY\") {\n # print \"$key : @{$value}\\n\";\n $matched = 0;\n } else {\n if ($matched eq \"1\" || $key =~ /$re/) {\n if($value =~ /derive\\(.*\\)/o) {\n $value = eval($value);\n }\n my $override = grep(/^$key$/, @overridable);\n print_define($prefix, $key, $value, $override) if ($value !~ /derived/);\n #printf(\"$key = $value\\n\");\n if ($parms and defined($parms->{$key})) {\n $value=decimal($value);\n #printf(\"verilog parm $key = $value %s\\n\",$parms->{$key});\n $value=d2b($key,$value,$parms->{$key});\n #printf(\"verilog parm $key = $value\\n\");\n $parms->{$key}=$value;\n }\n }\n }\n }\n}#}}}\n\nsub dump_define {#{{{\n my $matched = shift;\n my $prefix = shift;\n my $hash = @_[0];\n my @printvars = @{@_[1]};\n my @overridable = @{@_[2]} if defined @_[2];\n my $re = join(\"|\",@printvars);\n $re = qr/($re)/;\n #print Dumper($hash);\n foreach my $key (sort keys %$hash) {\n next if $key eq \"csr\";\n next unless $matched || grep(/^$key$/,@dvars);\n #print \"looking at $key:$matched ($re)\\n\";\n if (defined($unsets{$key})) {\n print \"$self:unsetting $key\\n\";\n delete($config{$key});\n next\n }\n if (defined($sets{$key}) && $sets{$key} ne $$hash{$key}) {\n if (($$hash{$key} =~ /derived/i) && ($$hash{$key} !~ /overridable/i)) {\n die (\"$self: ERROR! $key is a derived and non-overridable parameter!\\n\");\n } else {\n print \"$self: Overriding $key value $$hash{$key} with $sets{$key}\\n\";\n $$hash{$key} = $sets{$key};\n }\n }\n my $value = $$hash{$key};\n if (ref($value) eq \"HASH\") {\n if ($key =~ /$re/) {\n $matched = 1;\n }\n dump_define($matched,$prefix, $value, \\@printvars, \\@overridable);\n $matched = 0;\n } elsif (ref($value) eq \"ARRAY\") {\n # print \"$key : @{$value}\\n\";\n $matched = 0;\n } else {\n if ($matched eq \"1\" || $key =~ /$re/) {\n if($value =~ /derive\\(.*\\)/o) {\n $value = eval($value);\n }\n printf (\"veer: %-30s = $value\\n\",$key) if ($value !~ /derived/);\n }\n }\n }\n}#}}}\n\n# Perform cmd line set/unset ############################################{{{\nsub map_set_unset {\n if (scalar(@sets)) {\n print \"$self: Set(s) requested : @sets\\n\";\n foreach (@sets) {\n my ($key,$value) = m/(\\w+)=*(\\w+)*/o;\n $value = 1 if (!defined($value));\n $sets{$key} = $value;\n }\n }\n if (scalar(@unsets)) {\n print \"$self: Unset(s) requested : @unsets\\n\";\n foreach (@unsets) {\n $unsets{$_} = 1;\n }\n }\n} #}}}\n#}}}\n\n\n# If arg looks like a hexadecimal string, then convert it to decimal.#{{{\n# Otherwise, return arg.\nsub decimal {\n my ($x) = @_;\n return hex($x) if $x =~ /^0x/o;\n return $x;\n}#}}}\n\n\n# Collect memory protection specs (array of address pairs) in the given\n# resutls array. Tag is either \"data\" or \"inst\".\nsub collect_mem_protection {#{{{\n my ($tag, $config, $results) = @_;\n return unless exists $config{protection};\n\n my $prot = $config{protection};\n\n my $enable_tag = $tag . \"_access_enable\";\n my $addr_tag = $tag . \"_access_addr\";\n my $mask_tag = $tag . \"_access_mask\";\n\n foreach my $key (sort keys %{$prot}) {\n next unless $key =~ /^$enable_tag(\\d+)$/;\n my $ix = $1;\n\n my $enable = $prot->{$key};\n if ($enable !~ /[01]$/) {\n warn(\"Invalid value for protection entry $key: $enable\\n\");\n next;\n }\n\n next unless ($enable eq \"1\" or $enable eq \"1'b1\");\n\n if (! exists $prot->{\"$addr_tag$ix\"}) {\n warn(\"Missing $addr_tag$ix\\n\");\n next;\n }\n\n if (! exists $prot->{\"$mask_tag$ix\"}) {\n warn(\"Missing $mask_tag$ix\\n\");\n next;\n }\n\n my $addr = $prot->{\"$addr_tag$ix\"};\n my $mask = $prot->{\"$mask_tag$ix\"};\n\n if ($addr !~ /^0x[0-9a-fA-F]+$/) {\n warn(\"Invalid $addr_tag$ix: $addr\\n\");\n next;\n }\n\n if ($mask !~ /^0x[0-9a-fA-F]+$/) {\n warn(\"Invalid $mask_tag$ix: $mask\\n\");\n next;\n }\n\n if ((hex($addr) & hex($mask)) != 0) {\n warn(\"Protection mask bits overlap address bits in $tag mask $mask and addr $addr\\n\");\n }\n\n if ($mask !~ /^0x0*[137]?f*$/) {\n warn(\"Protection $tag mask ($mask) must have all its one bits to the right of its zero bits\\n\");\n next;\n }\n\n my $start = hex($addr) & ~hex($mask) & 0xffffffff;\n my $end = (hex($addr) | hex($mask)) & 0xffffffff;\n\n $start = sprintf(\"0x%08x\", $start);\n $end = sprintf(\"0x%08x\", $end);\n\n push(@{$results}, [ $start, $end ]);\n }\n}#}}}\n\n\n# Collect the memory mapped registers associated with the pic (platform\n# interrup controller) to include in the whisper.json file.\nsub collect_mem_mapped_regs {#{{{\n my ($pic, $results) = @_;\n my $default_mask = 0;\n $results->{default_mask} = $default_mask;\n my $addr = hex($pic->{pic_region})*256*1024*1024 + hex($pic->{pic_offset});\n $results->{address} = sprintf(\"0x%x\", $addr);\n $results->{size} = sprintf(\"0x%x\", $pic->{pic_size}*1024);\n\n my @names = qw ( mpiccfg meipl meip meie meigwctrl meigwclr meidels );\n $results->{registers} = {};\n foreach my $name (@names) {\n my $tag = \"pic_${name}_offset\";\n next unless exists $pic->{$tag};\n my %item;\n my $offset = hex($pic->{$tag});\n $offset += 4 if ($name ne 'mpiccfg' and $name ne 'meip');\n $item{address} = sprintf(\"0x%x\", $addr + $offset);\n $item{mask} = $pic->{\"pic_${name}_mask\"};\n $item{count} = $pic->{\"pic_${name}_count\"};\n $results->{registers}{$name} = \\%item;\n }\n}#}}}\n\n\nsub dump_whisper_config{#{{{\n my ($config, $path) = @_;\n\n open(my $fh, \">\", \"$path\") or die (\"Failed to open $path for writing: $!\\n\");\n\n # Put the configuration parameters relevant to whisper into a hash\n # in preparation for a JSON dump.\n my %jh; # Json hash\n\n # Collect top-level integer entries.\n foreach my $tag (qw( harts xlen )) {\n $jh{$tag} = $config{$tag} + 0 if exists $config{$tag};\n }\n\n # Collect top-level string/hex entries.\n foreach my $tag (qw ( reset_vec nmi_vec num_mmode_perf_regs max_mmode_perf_event\n even_odd_trigger_chains)) {\n $jh{$tag} = $config{$tag} if exists $config{$tag};\n }\n\n # Collect memory map configs.\n my (@inst_mem_prot, @data_mem_prot);\n collect_mem_protection(\"inst\", $config, \\@inst_mem_prot);\n collect_mem_protection(\"data\", $config, \\@data_mem_prot);\n $jh{memmap}{inst} = [@inst_mem_prot] if @inst_mem_prot;\n $jh{memmap}{data} = [@data_mem_prot] if @data_mem_prot;\n $config{memmap}{consoleio} = $config{memmap}{serialio} if exists $config{memmap}{serialio};\n foreach my $tag (qw ( size page_size serialio consoleio)) {\n $jh{memmap}{$tag} = $config{memmap}{$tag} if exists $config{memmap}{$tag};\n }\n\n # Collect load/store-error rollback parameter.\n if (exists $config{testbench} and exists $config{testbench}{sterr_rollback}) {\n $jh{store_error_rollback} = $config{testbench}{sterr_rollback};\n }\n if (exists $config{testbench} and exists $config{testbench}{lderr_rollback}) {\n $jh{load_error_rollback} = $config{testbench}{lderr_rollback};\n }\n\n # Collect dccm configs\n if (exists $config{dccm} and $config{dccm}{dccm_enable}) {\n $jh{dccm}{region} = $config{dccm}{dccm_region};\n $jh{dccm}{size} = 1024*decimal($config{dccm}{dccm_size}); # From 1k to bytes\n $jh{dccm}{offset} = $config{dccm}{dccm_offset};\n\n $jh{dccm}{size} = sprintf(\"0x%x\", $jh{dccm}{size});\n }\n\n # Collect icccm configs.\n if (exists $config{iccm} and $config{iccm}{iccm_enable}) {\n $jh{iccm}{region} = $config{iccm}{iccm_region};\n $jh{iccm}{size} = 1024*decimal($config{iccm}{iccm_size}); # From 1k to bytes\n $jh{iccm}{offset} = $config{iccm}{iccm_offset};\n\n $jh{iccm}{size} = sprintf(\"0x%x\", $jh{iccm}{size});\n }\n\n # Collect CSRs\n $jh{csr} = $config{csr} if exists $config{csr};\n\n # Collect CSRs not included in verilog.\n my @removed_csrs;\n if (! $config{core}{timer_legal_en}) {\n push(@removed_csrs, $_) for qw (mitcnt0 mitbnd0 mitctl0\n mitcnt1 mitbnd1 mitctl1);\n }\n\n # Collect fast interrupt enable.\n if (exists $config{core}{fast_interrupt_redirect}) {\n $jh{fast_interrupt_redirect} = $config{core}{fast_interrupt_redirect};\n # meicpct CSR is not built if fast interrupt.\n push(@removed_csrs, 'meicpct') if $jh{fast_interrupt_redirect};\n }\n\n # Remove CSRs not configured into verilog.\n delete $jh{csr}{$_} foreach @removed_csrs;\n\n # Collect zb extension configs\n $jh{enable_zbb} = $config{core}{bitmanip_zbb};\n $jh{enable_zbs} = $config{core}{bitmanip_zbs};\n $jh{enable_zba} = $config{core}{bitmanip_zba};\n $jh{enable_zbc} = $config{core}{bitmanip_zbc};\n $jh{enable_zbe} = $config{core}{bitmanip_zbe};\n $jh{enable_zbf} = $config{core}{bitmanip_zbf};\n $jh{enable_zbp} = $config{core}{bitmanip_zbp};\n $jh{enable_zbr} = $config{core}{bitmanip_zbr};\n\n # Collect pic configs.\n if (exists $config{pic}) {\n my %mem_mapped;\n collect_mem_mapped_regs($config{pic}, \\%mem_mapped);\n $jh{'memory_mapped_registers'} = \\%mem_mapped;\n }\n\n # Collect performance events. Uncomment when RTL ready.\n if (exists $config{perf_events}) {\n $jh{mmode_perf_events} = $config{perf_events};\n }\n\n # Make atomic instructions illegal outside of DCCM.\n $jh{amo_illegal_outside_dccm} = \"true\";\n\n # Make ld/st instructions trigger misaligned exceptions if base\n # address (value in rs1) and effective address refer to regions of\n # different types.\n $jh{effective_address_compatible_with_base} = \"true\";\n\n # Collect triggers.\n $jh{triggers} = $config{triggers} if exists $config{triggers};\n\n # Dump JSON config file.\n my $json = JSON->new->allow_nonref;\n my $text = $json->pretty->encode(\\%jh);\n print($fh $text);\n\n close $fh;\n}#}}}\n\n\n# Checker for iccm/dccm/pic sub-region address alignment. Address must be a multiple\n# of size or next higher power of 2 if size is not a power of 2.\nsub check_addr_align {#{{{\n my ($section, $addr, $size) = @_;\n\n die(\"Invalid $section size: $size\\n\") if $size <= 0;\n\n my $log_size = log2($size);\n my $p2 = 1 << $log_size;\n $size = 2*$p2 if $size != $p2;\n\n if (($addr % $size) != 0) {\n printf(\"Address of $section area(0x%x) is not a multiple of its size (0x%x)\\n\",\n $addr, $size);\n exit(1);\n }\n}#}}}\n\nsub log2 {#{{{\n my ($n) = @_;\n return log($n)/log(2);\n}#}}}\n\nsub b2d {#{{{\n my ($v) = @_;\n\n $v = oct(\"0b\" . $v);\n\n return($v);\n}#}}}\n\nsub d2b {#{{{\n my ($key,$v,$LEN) = @_;\n\n my $repeat;\n\n $v = sprintf \"%b\",$v;\n if (length($v)<$LEN) {\n $repeat=$LEN-length($v);\n $v=\"0\"x$repeat.$v;\n }\n elsif (length($v)>$LEN) {\n die(\"d2b: parm $key value $v > len $LEN\");\n }\n\n return($v);\n}#}}}\n\n\nsub invalid_mask {#{{{\n my ($m) = @_;\n\n if ($m =~ /^0x(0)*([137]?f+)$/) { return(0); }\n\n return(1);\n}#}}}\n\n\nsub b2h {#{{{\n my ($bin) = @_;\n\n # Make input bit string a multiple of 4\n $bin = substr(\"0000\",length($bin)%4) . $bin if length($bin)%4;\n\n my ($hex, $nybble) = (\"\");\n while (length($bin)) {\n ($nybble,$bin) = (substr($bin,0,4), substr($bin,4));\n $nybble = eval \"0b$nybble\";\n $hex .= substr(\"0123456789ABCDEF\", $nybble, 1);\n }\n return $hex;\n}#}}}\n\n# BHT index is a hash of the GHR and PC_HASH\nsub ghrhash{#{{{\n my($btb_index_hi,$ghr_size) = @_;\n\n $btb_size = $btb_index_hi - 1;\n\n my $ghr_hi = $ghr_size - 1;\n my $ghr_lo = $btb_size;\n\n my $ghr_start = \"{\";\n if($ghr_size > $btb_size){\n return \"{ghr[$ghr_hi:$ghr_lo], hashin[$btb_index_hi:2]^ghr[$ghr_lo-1:0]} // cf1\";\n }\n else {\n return \"{hashin[$ghr_size+1:2]^ghr[$ghr_size-1:0]}// cf2\";\n }\n}#}}}\n\nsub dump_parms {#{{{\n my ($hash) = @_;\n\n my ($bvalue, $blen, $upper);\n printf(FILE1 \"typedef struct packed {\\n\");\n foreach my $key (sort keys %$hash) {\n $bvalue=$hash->{$key};\n $blen=length($bvalue);\n $upper=$key;\n $upper=~ tr/a-z/A-Z/;\n if ($blen==1) {\n printf(FILE1 \"\\tlogic %-10s $upper;\\n\");\n }\n else {\n printf(FILE1 \"\\tlogic %-10s $upper;\\n\",sprintf(\"[%d:0]\",$blen-1));\n }\n }\n printf(FILE1 \"} el2_param_t;\\n\\n\");\n\n my $bcat=\"\";\n my $parmcnt=0;\n foreach my $key (sort keys %$hash) {\n #printf(\"// $key = %s\\n\",$verilog_parms{$key});\n $bcat.=$hash->{$key};\n $parmcnt++;\n }\n\n my $bvalue=\"\";\n my $pcnt=0;\n my $delim=\",\";\n my $msb;\n printf(FILE2 \"// parameter el2_param_t pt = '{\\n\");\n foreach my $key (sort keys %$hash) {\n $upper=$key;\n $upper=~ tr/a-z/A-Z/;\n $pcnt++;\n if ($pcnt==$parmcnt) { undef $delim; }\n if ($hash->{$key} eq \"0\") { $hash->{$key}=\"0000\"; }\n if (length($hash->{$key}) != 1) {\n $msb=substr($hash->{$key},0,4); # require upper 4b to be 0\n if ($msb ne \"0000\") { die(\"parameter $upper upper 4b must be 0\"); }\n }\n printf(FILE2 \"// \\t%-22s : %d\\'h%-10s $delim\\n\",$upper,length($hash->{$key}),b2h($hash->{$key}));\n }\n printf(FILE2 \"// }\\n\");\n\n printf(FILE2 \"parameter el2_param_t pt = %d'h%s\\n\",length($bcat),b2h($bcat));\n\n}#}}}\n\nsub gen_default_linker_script {#{{{\n\n open (FILE, \">$linkerfile\") || die \"Cannot open $linkerfile for writing $!\\n\";\n print \"$self: Writing $linkerfile\\n\";\n print FILE \"/*\\n\";\n print_header();\n\n my $io = \"0xd0580000\";\n $io = $config{memmap}{serialio} if exists $config{memmap}{serialio};\n\n my $iccm = \"\"; my $iccm_ctl = \"\";\n if (exists $config{iccm} and $config{iccm}{iccm_enable} and $text_in_iccm) {\n my $sa = $config{iccm}{iccm_sadr}; my $ea = $config{iccm}{iccm_eadr};\n $iccm = \" . = $sa ;\";\n $iccm_ctl = \" . = 0xfffffff0; .iccm.ctl . : { LONG($sa); LONG($ea) }\" ;\n }\n\n my $sa = $config{memmap}{external_data}; my $dccm_ctl = \"\";\n if (exists $config{dccm} and $config{dccm}{dccm_enable}) {\n $sa = $config{dccm}{dccm_sadr};\n $dccm_ctl = \" . = 0xfffffff8; .data.ctl : { LONG($sa); LONG(STACK) }\" ;\n }\n my $data_loc = \" . = $sa ;\";\n\n print FILE \"*/\\n\";\n print FILE <<\"EOF\";\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS\n{\n . = $config{reset_vec};\n .text.init . : { *(.text.init) }\n $iccm\n .text . : { *(.text) }\n _end = .;\n . = $io;\n .data.io . : { *(.data.io) }\n $data_loc\n .data : ALIGN(0x800) { *(.*data) *(.rodata*)}\n .bss : {BSS_START = .; *(.*bss)}\n BSS_END = .;\n STACK = ALIGN(16) + 0x1000;\n $iccm_ctl\n $dccm_ctl\n}\n\nEOF\n close FILE;\n} #}}}\n\n\n" }, { "path": "configs/veer_config_gen.py", "content": "#!/usr/bin/env python3\nfrom fusesoc.capi2.generator import Generator\nimport os\nimport subprocess\nimport sys\n\nclass VeerConfigGenerator(Generator):\n def run(self):\n script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))\n files = [\n {\"common_defines.vh\" : {\n \"copyto\" : \"config/common_defines.vh\",\n \"file_type\" : \"systemVerilogSource\"}},\n {\"el2_pdef.vh\" : {\n \"copyto\" : \"config/el2_pdef.vh\",\n \"file_type\" : \"systemVerilogSource\"}},\n {\"el2_param.vh\" : {\n \"is_include_file\" : True,\n \"file_type\" : \"systemVerilogSource\"}},\n {\"pic_map_auto.h\" : {\n \"is_include_file\" : True,\n \"file_type\" : \"systemVerilogSource\"}}]\n\n env = os.environ.copy()\n env['RV_ROOT'] = script_root\n env['BUILD_PATH'] = os.getcwd()\n args = ['configs/veer.config'] + self.config.get('args', [])\n\n rc = subprocess.call(args, cwd=script_root, env=env, stdout=subprocess.DEVNULL)\n if rc:\n exit(1)\n filenames = []\n for f in files:\n for k in f:\n filenames.append(k)\n\n self.add_files(files)\n\ng = VeerConfigGenerator()\ng.run()\ng.write()\n" }, { "path": "design/dbg/el2_dbg.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n// $Id$\n//\n// Function: Top level VeeR core file to control the debug mode\n// Comments: Responsible to put the rest of the core in quiesce mode,\n// Send the commands/address. sends WrData and Recieve read Data.\n// And then Resume the core to do the normal mode\n// Author :\n//********************************************************************************\nmodule el2_dbg\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n // outputs to the core for command and data interface\n output logic [31:0] dbg_cmd_addr,\n output logic [31:0] dbg_cmd_wrdata,\n output logic dbg_cmd_valid,\n output logic dbg_cmd_write, // 1: write command, 0: read_command\n output logic [1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory\n output logic [1:0] dbg_cmd_size, // size of the abstract mem access debug command\n output logic dbg_core_rst_l, // core reset from dm\n\n // inputs back from the core/dec\n input logic [31:0] core_dbg_rddata,\n input logic core_dbg_cmd_done, // This will be treated like a valid signal\n input logic core_dbg_cmd_fail, // Exception during command run\n\n // Signals to dma to get a bubble\n output logic dbg_dma_bubble, // Debug needs a bubble to send a valid\n input logic dma_dbg_ready, // DMA is ready to accept debug request\n\n // interface with the rest of the core to halt/resume handshaking\n output logic dbg_halt_req, // This is a pulse\n output logic dbg_resume_req, // Debug sends a resume requests. Pulse\n input logic dec_tlu_debug_mode, // Core is in debug mode\n input logic dec_tlu_dbg_halted, // The core has finished the queiscing sequence. Core is halted now\n input logic dec_tlu_mpc_halted_only, // Only halted due to MPC\n input logic dec_tlu_resume_ack, // core sends back an ack for the resume (pulse)\n\n // inputs from the JTAG\n input logic dmi_reg_en, // read or write\n input logic [6:0] dmi_reg_addr, // address of DM register\n input logic dmi_reg_wr_en, // write instruction\n input logic [31:0] dmi_reg_wdata, // write data\n\n // output\n output logic [31:0] dmi_reg_rdata, // read data\n\n // AXI Write Channels\n output logic sb_axi_awvalid,\n input logic sb_axi_awready,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,\n /*pragma coverage on*/\n output logic [31:0] sb_axi_awaddr,\n output logic [3:0] sb_axi_awregion,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [7:0] sb_axi_awlen,\n /*pragma coverage on*/\n output logic [2:0] sb_axi_awsize,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [1:0] sb_axi_awburst,\n output logic sb_axi_awlock,\n output logic [3:0] sb_axi_awcache,\n output logic [2:0] sb_axi_awprot,\n output logic [3:0] sb_axi_awqos,\n /*pragma coverage on*/\n\n output logic sb_axi_wvalid,\n input logic sb_axi_wready,\n output logic [63:0] sb_axi_wdata,\n output logic [7:0] sb_axi_wstrb,\n output logic sb_axi_wlast,\n\n input logic sb_axi_bvalid,\n output logic sb_axi_bready,\n input logic [1:0] sb_axi_bresp,\n\n // AXI Read Channels\n output logic sb_axi_arvalid,\n input logic sb_axi_arready,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,\n /*pragma coverage on*/\n output logic [31:0] sb_axi_araddr,\n output logic [3:0] sb_axi_arregion,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [7:0] sb_axi_arlen,\n /*pragma coverage on*/\n output logic [2:0] sb_axi_arsize,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [1:0] sb_axi_arburst,\n output logic sb_axi_arlock,\n output logic [3:0] sb_axi_arcache,\n output logic [2:0] sb_axi_arprot,\n output logic [3:0] sb_axi_arqos,\n /*pragma coverage on*/\n\n input logic sb_axi_rvalid,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic sb_axi_rready,\n /*pragma coverage on*/\n input logic [63:0] sb_axi_rdata,\n input logic [1:0] sb_axi_rresp,\n\n input logic dbg_bus_clk_en,\n\n // general inputs\n input logic clk,\n input logic free_clk,\n input logic rst_l, // This includes both top rst and debug rst\n input logic dbg_rst_l,\n input logic clk_override,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n);\n\n\n typedef enum logic [3:0] {IDLE=4'h0, HALTING=4'h1, HALTED=4'h2, CORE_CMD_START=4'h3, CORE_CMD_WAIT=4'h4, SB_CMD_START=4'h5, SB_CMD_SEND=4'h6, SB_CMD_RESP=4'h7, CMD_DONE=4'h8, RESUMING=4'h9} state_t;\n typedef enum logic [3:0] {SBIDLE=4'h0, WAIT_RD=4'h1, WAIT_WR=4'h2, CMD_RD=4'h3, CMD_WR=4'h4, CMD_WR_ADDR=4'h5, CMD_WR_DATA=4'h6, RSP_RD=4'h7, RSP_WR=4'h8, DONE=4'h9} sb_state_t;\n\n state_t dbg_state;\n state_t dbg_nxtstate;\n logic dbg_state_en;\n // these are the registers that the debug module implements\n logic [31:0] dmstatus_reg; // [26:24]-dmerr, [17:16]-resume ack, [9:8]-halted, [3:0]-version\n logic [31:0] dmcontrol_reg; // dmcontrol register has only 6 bits implemented. 31: haltreq, 30: resumereq, 29: haltreset, 28: ackhavereset, 1: ndmreset, 0: dmactive.\n logic [31:0] command_reg;\n logic [31:0] abstractcs_reg; // bits implemted are [12] - busy and [10:8]= command error\n logic [31:0] haltsum0_reg;\n logic [31:0] data0_reg;\n logic [31:0] data1_reg;\n\n // data 0\n logic [31:0] data0_din;\n logic data0_reg_wren, data0_reg_wren0, data0_reg_wren1, data0_reg_wren2;\n // data 1\n logic [31:0] data1_din;\n logic data1_reg_wren, data1_reg_wren0, data1_reg_wren1;\n // abstractcs\n logic abstractcs_busy_wren;\n logic abstractcs_busy_din;\n logic [2:0] abstractcs_error_din;\n logic abstractcs_error_sel0, abstractcs_error_sel1, abstractcs_error_sel2, abstractcs_error_sel3, abstractcs_error_sel4, abstractcs_error_sel5, abstractcs_error_sel6;\n logic dbg_sb_bus_error;\n // abstractauto\n logic abstractauto_reg_wren;\n logic [1:0] abstractauto_reg;\n\n // dmstatus\n logic dmstatus_resumeack_wren;\n logic dmstatus_resumeack_din;\n logic dmstatus_haveresetn_wren;\n logic dmstatus_resumeack;\n logic dmstatus_unavail;\n logic dmstatus_running;\n logic dmstatus_halted;\n logic dmstatus_havereset, dmstatus_haveresetn;\n\n // dmcontrol\n logic resumereq;\n logic dmcontrol_wren, dmcontrol_wren_Q;\n // command\n logic execute_command_ns, execute_command;\n logic command_wren, command_regno_wren;\n logic command_transfer_din;\n logic command_postexec_din;\n logic [31:0] command_din;\n logic [3:0] dbg_cmd_addr_incr;\n logic [31:0] dbg_cmd_curr_addr;\n logic [31:0] dbg_cmd_next_addr;\n\n // needed to send the read data back for dmi reads\n logic [31:0] dmi_reg_rdata_din;\n\n sb_state_t sb_state;\n sb_state_t sb_nxtstate;\n logic sb_state_en;\n\n //System bus section\n logic sbcs_wren;\n logic sbcs_sbbusy_wren;\n logic sbcs_sbbusy_din;\n logic sbcs_sbbusyerror_wren;\n logic sbcs_sbbusyerror_din;\n\n logic sbcs_sberror_wren;\n logic [2:0] sbcs_sberror_din;\n logic sbcs_unaligned;\n logic sbcs_illegal_size;\n logic [19:15] sbcs_reg_int;\n\n // data\n logic sbdata0_reg_wren0;\n logic sbdata0_reg_wren1;\n logic sbdata0_reg_wren;\n logic [31:0] sbdata0_din;\n\n logic sbdata1_reg_wren0;\n logic sbdata1_reg_wren1;\n logic sbdata1_reg_wren;\n logic [31:0] sbdata1_din;\n\n logic sbaddress0_reg_wren0;\n logic sbaddress0_reg_wren1;\n logic sbaddress0_reg_wren;\n logic [31:0] sbaddress0_reg_din;\n logic [3:0] sbaddress0_incr;\n logic sbreadonaddr_access;\n logic sbreadondata_access;\n logic sbdata0wr_access;\n\n logic sb_abmem_cmd_done_in, sb_abmem_data_done_in;\n logic sb_abmem_cmd_done_en, sb_abmem_data_done_en;\n logic sb_abmem_cmd_done, sb_abmem_data_done;\n logic [31:0] abmem_addr;\n logic abmem_addr_in_dccm_region, abmem_addr_in_iccm_region, abmem_addr_in_pic_region;\n logic abmem_addr_core_local;\n logic abmem_addr_external;\n\n logic sb_cmd_pending, sb_abmem_cmd_pending;\n logic sb_abmem_cmd_write;\n logic [2:0] sb_abmem_cmd_size;\n logic [31:0] sb_abmem_cmd_addr;\n logic [31:0] sb_abmem_cmd_wdata;\n\n logic [2:0] sb_cmd_size;\n logic [31:0] sb_cmd_addr;\n logic [63:0] sb_cmd_wdata;\n\n logic sb_bus_cmd_read, sb_bus_cmd_write_addr, sb_bus_cmd_write_data;\n logic sb_bus_rsp_read, sb_bus_rsp_write;\n logic sb_bus_rsp_error;\n logic [63:0] sb_bus_rdata;\n\n //registers\n logic [31:0] sbcs_reg;\n logic [31:0] sbaddress0_reg;\n logic [31:0] sbdata0_reg;\n logic [31:0] sbdata1_reg;\n\n logic sb_abmem_cmd_arvalid, sb_abmem_cmd_awvalid, sb_abmem_cmd_wvalid;\n logic sb_abmem_read_pend;\n logic sb_cmd_awvalid, sb_cmd_wvalid, sb_cmd_arvalid;\n logic sb_read_pend;\n logic [31:0] sb_axi_addr;\n logic [63:0] sb_axi_wrdata;\n logic [2:0] sb_axi_size;\n\n logic dbg_dm_rst_l;\n logic rst_l_sync;\n\n //clken\n logic dbg_free_clken;\n logic dbg_free_clk;\n\n logic sb_free_clken;\n logic sb_free_clk;\n\n // clocking\n // used for the abstract commands.\n assign dbg_free_clken = dmi_reg_en | execute_command | (dbg_state != IDLE) | dbg_state_en | dec_tlu_dbg_halted | dec_tlu_mpc_halted_only | dec_tlu_debug_mode | dbg_halt_req | clk_override;\n\n // used for the system bus\n assign sb_free_clken = dmi_reg_en | execute_command | sb_state_en | (sb_state != SBIDLE) | clk_override;\n\n rvoclkhdr dbg_free_cgc (.en(dbg_free_clken), .l1clk(dbg_free_clk), .*);\n rvoclkhdr sb_free_cgc (.en(sb_free_clken), .l1clk(sb_free_clk), .*);\n\n // end clocking section\n\n // Reset logic\n assign dbg_dm_rst_l = dbg_rst_l & (dmcontrol_reg[0] | scan_mode);\n assign dbg_core_rst_l = ~dmcontrol_reg[1] | scan_mode;\n\n // synchronize the rst\n rvsyncss #(1) rstl_syncff (.din(rst_l), .dout(rst_l_sync), .clk(free_clk), .rst_l(dbg_rst_l));\n\n // system bus register\n // sbcs[31:29], sbcs - [22]:sbbusyerror, [21]: sbbusy, [20]:sbreadonaddr, [19:17]:sbaccess, [16]:sbautoincrement, [15]:sbreadondata, [14:12]:sberror, sbsize=32, 128=0, 64/32/16/8 are legal\n assign sbcs_reg[31:29] = 3'b1;\n assign sbcs_reg[28:23] = '0;\n assign sbcs_reg[19:15] = {sbcs_reg_int[19], ~sbcs_reg_int[18], sbcs_reg_int[17:15]};\n assign sbcs_reg[11:5] = 7'h20;\n assign sbcs_reg[4:0] = 5'b01111;\n assign sbcs_wren = (dmi_reg_addr == 7'h38) & dmi_reg_en & dmi_reg_wr_en & (sb_state == SBIDLE);\n assign sbcs_sbbusyerror_wren = (sbcs_wren & dmi_reg_wdata[22]) |\n (sbcs_reg[21] & dmi_reg_en & ((dmi_reg_wr_en & (dmi_reg_addr == 7'h39)) | (dmi_reg_addr == 7'h3c) | (dmi_reg_addr == 7'h3d)));\n assign sbcs_sbbusyerror_din = ~(sbcs_wren & dmi_reg_wdata[22]); // Clear when writing one\n\n rvdffs #(1) sbcs_sbbusyerror_reg (.din(sbcs_sbbusyerror_din), .dout(sbcs_reg[22]), .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));\n rvdffs #(1) sbcs_sbbusy_reg (.din(sbcs_sbbusy_din), .dout(sbcs_reg[21]), .en(sbcs_sbbusy_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));\n rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]), .dout(sbcs_reg[20]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));\n rvdffs #(5) sbcs_misc_reg (.din({dmi_reg_wdata[19],~dmi_reg_wdata[18],dmi_reg_wdata[17:15]}),\n .dout(sbcs_reg_int[19:15]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));\n rvdffs #(3) sbcs_error_reg (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));\n\n assign sbcs_unaligned = ((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) |\n ((sbcs_reg[19:17] == 3'b010) & (|sbaddress0_reg[1:0])) |\n ((sbcs_reg[19:17] == 3'b011) & (|sbaddress0_reg[2:0]));\n\n assign sbcs_illegal_size = sbcs_reg[19]; // Anything bigger than 64 bits is illegal\n\n assign sbaddress0_incr[3:0] = ({4{(sbcs_reg[19:17] == 3'h0)}} & 4'b0001) |\n ({4{(sbcs_reg[19:17] == 3'h1)}} & 4'b0010) |\n ({4{(sbcs_reg[19:17] == 3'h2)}} & 4'b0100) |\n ({4{(sbcs_reg[19:17] == 3'h3)}} & 4'b1000);\n\n // sbdata\n assign sbdata0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3c); // write data only when single read is 0\n assign sbdata0_reg_wren1 = (sb_state == RSP_RD) & sb_state_en & ~sbcs_sberror_wren;\n assign sbdata0_reg_wren = sbdata0_reg_wren0 | sbdata0_reg_wren1;\n\n assign sbdata1_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3d); // write data only when single read is 0;\n assign sbdata1_reg_wren1 = (sb_state == RSP_RD) & sb_state_en & ~sbcs_sberror_wren;\n assign sbdata1_reg_wren = sbdata1_reg_wren0 | sbdata1_reg_wren1;\n\n assign sbdata0_din[31:0] = ({32{sbdata0_reg_wren0}} & dmi_reg_wdata[31:0]) |\n ({32{sbdata0_reg_wren1}} & sb_bus_rdata[31:0]);\n assign sbdata1_din[31:0] = ({32{sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) |\n ({32{sbdata1_reg_wren1}} & sb_bus_rdata[63:32]);\n\n rvdffe #(32) dbg_sbdata0_reg (.*, .din(sbdata0_din[31:0]), .dout(sbdata0_reg[31:0]), .en(sbdata0_reg_wren), .rst_l(dbg_dm_rst_l));\n rvdffe #(32) dbg_sbdata1_reg (.*, .din(sbdata1_din[31:0]), .dout(sbdata1_reg[31:0]), .en(sbdata1_reg_wren), .rst_l(dbg_dm_rst_l));\n\n // sbaddress\n assign sbaddress0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39);\n assign sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1;\n assign sbaddress0_reg_din[31:0]= ({32{sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) |\n ({32{sbaddress0_reg_wren1}} & (32'(sbaddress0_reg[31:0] + {28'b0,sbaddress0_incr[3:0]})));\n rvdffe #(32) dbg_sbaddress0_reg (.*, .din(sbaddress0_reg_din[31:0]), .dout(sbaddress0_reg[31:0]), .en(sbaddress0_reg_wren), .rst_l(dbg_dm_rst_l));\n\n assign sbreadonaddr_access = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39) & sbcs_reg[20]; // if readonaddr is set the next command will start upon writing of addr0\n assign sbreadondata_access = dmi_reg_en & ~dmi_reg_wr_en & (dmi_reg_addr == 7'h3c) & sbcs_reg[15]; // if readondata is set the next command will start upon reading of data0\n assign sbdata0wr_access = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3c); // write to sbdata0 will start write command to system bus\n\n // memory mapped registers\n // dmcontrol register has only 5 bits implemented. 31: haltreq, 30: resumereq, 28: ackhavereset, 1: ndmreset, 0: dmactive.\n // rest all the bits are zeroed out\n // dmactive flop is reset based on core rst_l, all other flops use dm_rst_l\n assign dmcontrol_wren = (dmi_reg_addr == 7'h10) & dmi_reg_en & dmi_reg_wr_en;\n assign dmcontrol_reg[29] = '0;\n assign dmcontrol_reg[27:2] = '0;\n assign resumereq = dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q;\n rvdffs #(4) dmcontrolff (.din({dmi_reg_wdata[31:30],dmi_reg_wdata[28],dmi_reg_wdata[1]}), .dout({dmcontrol_reg[31:30], dmcontrol_reg[28], dmcontrol_reg[1]}), .en(dmcontrol_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));\n rvdffs #(1) dmcontrol_dmactive_ff (.din(dmi_reg_wdata[0]), .dout(dmcontrol_reg[0]), .en(dmcontrol_wren), .rst_l(dbg_rst_l), .clk(dbg_free_clk));\n rvdff #(1) dmcontrol_wrenff(.din(dmcontrol_wren), .dout(dmcontrol_wren_Q), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));\n\n // dmstatus register bits that are implemented\n // [19:18]-havereset,[17:16]-resume ack, [9:8]-halted, [3:0]-version\n // rest all the bits are zeroed out\n //assign dmstatus_wren = (dmi_reg_addr[31:0] == 32'h11) & dmi_reg_en;\n assign dmstatus_reg[31:20] = '0;\n assign dmstatus_reg[19:18] = {2{dmstatus_havereset}};\n assign dmstatus_reg[15:14] = '0;\n assign dmstatus_reg[7] = '1;\n assign dmstatus_reg[6:4] = '0;\n assign dmstatus_reg[17:16] = {2{dmstatus_resumeack}};\n assign dmstatus_reg[13:12] = {2{dmstatus_unavail}};\n assign dmstatus_reg[11:10] = {2{dmstatus_running}};\n assign dmstatus_reg[9:8] = {2{dmstatus_halted}};\n assign dmstatus_reg[3:0] = 4'h2;\n\n assign dmstatus_resumeack_wren = ((dbg_state == RESUMING) & dec_tlu_resume_ack) | (dmstatus_resumeack & resumereq & dmstatus_halted);\n assign dmstatus_resumeack_din = (dbg_state == RESUMING) & dec_tlu_resume_ack;\n\n assign dmstatus_haveresetn_wren = (dmi_reg_addr == 7'h10) & dmi_reg_wdata[28] & dmi_reg_en & dmi_reg_wr_en & dmcontrol_reg[0]; // clear the havereset\n assign dmstatus_havereset = ~dmstatus_haveresetn;\n\n assign dmstatus_unavail = dmcontrol_reg[1] | ~rst_l_sync;\n assign dmstatus_running = ~(dmstatus_unavail | dmstatus_halted);\n\n rvdffs #(1) dmstatus_resumeack_reg (.din(dmstatus_resumeack_din), .dout(dmstatus_resumeack), .en(dmstatus_resumeack_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));\n rvdff #(1) dmstatus_halted_reg (.din(dec_tlu_dbg_halted & ~dec_tlu_mpc_halted_only), .dout(dmstatus_halted), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));\n rvdffs #(1) dmstatus_haveresetn_reg (.din(1'b1), .dout(dmstatus_haveresetn), .en(dmstatus_haveresetn_wren), .rst_l(rst_l), .clk(dbg_free_clk));\n\n // haltsum0 register\n assign haltsum0_reg[31:1] = '0;\n assign haltsum0_reg[0] = dmstatus_halted;\n\n // abstractcs register\n // bits implemted are [12] - busy and [10:8]= command error\n assign abstractcs_reg[31:13] = '0;\n assign abstractcs_reg[11] = '0;\n assign abstractcs_reg[7:4] = '0;\n assign abstractcs_reg[3:0] = 4'h2; // One data register\n\n assign abstractcs_error_sel0 = abstractcs_reg[12] & ~(|abstractcs_reg[10:8]) & dmi_reg_en & ((dmi_reg_wr_en & ((dmi_reg_addr == 7'h16) | (dmi_reg_addr == 7'h17)) | (dmi_reg_addr == 7'h18)) |\n (dmi_reg_addr == 7'h4) | (dmi_reg_addr == 7'h5));\n assign abstractcs_error_sel1 = execute_command & ~(|abstractcs_reg[10:8]) &\n ((~((command_reg[31:24] == 8'b0) | (command_reg[31:24] == 8'h2))) | // Illegal command\n (((command_reg[22:20] == 3'b011) | (command_reg[22])) & (command_reg[31:24] == 8'h2)) | // Illegal abstract memory size (can't be DW or higher)\n ((command_reg[22:20] != 3'b010) & ((command_reg[31:24] == 8'h0) & command_reg[17])) | // Illegal abstract reg size\n ((command_reg[31:24] == 8'h0) & command_reg[18])); //postexec for abstract register access\n assign abstractcs_error_sel2 = ((core_dbg_cmd_done & core_dbg_cmd_fail) | // exception from core\n (execute_command & (command_reg[31:24] == 8'h0) & // unimplemented regs\n (((command_reg[15:12] == 4'h1) & (command_reg[11:5] != 0)) | (command_reg[15:13] != 0)))) & ~(|abstractcs_reg[10:8]);\n assign abstractcs_error_sel3 = execute_command & (dbg_state != HALTED) & ~(|abstractcs_reg[10:8]);\n assign abstractcs_error_sel4 = dbg_sb_bus_error & dbg_bus_clk_en & ~(|abstractcs_reg[10:8]);// sb bus error for abstract memory command\n assign abstractcs_error_sel5 = execute_command & (command_reg[31:24] == 8'h2) & ~(|abstractcs_reg[10:8]) &\n (((command_reg[22:20] == 3'b001) & data1_reg[0]) | ((command_reg[22:20] == 3'b010) & (|data1_reg[1:0]))); //Unaligned address for abstract memory\n assign abstractcs_error_sel6 = (dmi_reg_addr == 7'h16) & dmi_reg_en & dmi_reg_wr_en;\n\n assign abstractcs_error_din[2:0] = abstractcs_error_sel0 ? 3'b001 : // writing command or abstractcs while a command was executing. Or accessing data0\n abstractcs_error_sel1 ? 3'b010 : // writing a illegal command type to cmd field of command\n abstractcs_error_sel2 ? 3'b011 : // exception while running command\n abstractcs_error_sel3 ? 3'b100 : // writing a comnand when not in the halted state\n abstractcs_error_sel4 ? 3'b101 : // Bus error\n abstractcs_error_sel5 ? 3'b111 : // unaligned or illegal size abstract memory command\n abstractcs_error_sel6 ? (~dmi_reg_wdata[10:8] & abstractcs_reg[10:8]) : //W1C\n abstractcs_reg[10:8]; //hold\n\n rvdffs #(1) dmabstractcs_busy_reg (.din(abstractcs_busy_din), .dout(abstractcs_reg[12]), .en(abstractcs_busy_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));\n rvdff #(3) dmabstractcs_error_reg (.din(abstractcs_error_din[2:0]), .dout(abstractcs_reg[10:8]), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));\n\n // abstract auto reg\n assign abstractauto_reg_wren = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h18) & ~abstractcs_reg[12];\n rvdffs #(2) dbg_abstractauto_reg (.*, .din(dmi_reg_wdata[1:0]), .dout(abstractauto_reg[1:0]), .en(abstractauto_reg_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));\n\n // command register - implemented all the bits in this register\n // command[16] = 1: write, 0: read\n assign execute_command_ns = command_wren |\n (dmi_reg_en & ~abstractcs_reg[12] & (((dmi_reg_addr == 7'h4) & abstractauto_reg[0]) | ((dmi_reg_addr == 7'h5) & abstractauto_reg[1])));\n assign command_wren = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en;\n assign command_regno_wren = command_wren | ((command_reg[31:24] == 8'h0) & command_reg[19] & (dbg_state == CMD_DONE) & ~(|abstractcs_reg[10:8])); // aarpostincrement\n assign command_postexec_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[18];\n assign command_transfer_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[17];\n assign command_din[31:16] = {dmi_reg_wdata[31:24],1'b0,dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din, dmi_reg_wdata[16]};\n assign command_din[15:0] = command_wren ? dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0];\n rvdff #(1) execute_commandff (.*, .din(execute_command_ns), .dout(execute_command), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l));\n rvdffe #(16) dmcommand_reg (.*, .din(command_din[31:16]), .dout(command_reg[31:16]), .en(command_wren), .rst_l(dbg_dm_rst_l));\n rvdffe #(16) dmcommand_regno_reg (.*, .din(command_din[15:0]), .dout(command_reg[15:0]), .en(command_regno_wren), .rst_l(dbg_dm_rst_l));\n\n // data0 reg\n assign data0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h4) & (dbg_state == HALTED) & ~abstractcs_reg[12]);\n assign data0_reg_wren1 = core_dbg_cmd_done & (dbg_state == CORE_CMD_WAIT) & ~command_reg[16];\n assign data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 | data0_reg_wren2;\n\n assign data0_din[31:0] = ({32{data0_reg_wren0}} & dmi_reg_wdata[31:0]) |\n ({32{data0_reg_wren1}} & core_dbg_rddata[31:0]) |\n ({32{data0_reg_wren2}} & sb_bus_rdata[31:0]);\n\n rvdffe #(32) dbg_data0_reg (.*, .din(data0_din[31:0]), .dout(data0_reg[31:0]), .en(data0_reg_wren), .rst_l(dbg_dm_rst_l));\n\n // data 1\n assign data1_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h5) & (dbg_state == HALTED) & ~abstractcs_reg[12]);\n assign data1_reg_wren1 = (dbg_state == CMD_DONE) & (command_reg[31:24] == 8'h2) & command_reg[19] & ~(|abstractcs_reg[10:8]); // aampostincrement\n assign data1_reg_wren = data1_reg_wren0 | data1_reg_wren1;\n\n assign data1_din[31:0] = ({32{data1_reg_wren0}} & dmi_reg_wdata[31:0]) |\n ({32{data1_reg_wren1}} & dbg_cmd_next_addr[31:0]);\n\n rvdffe #(32) dbg_data1_reg (.*, .din(data1_din[31:0]), .dout(data1_reg[31:0]), .en(data1_reg_wren), .rst_l(dbg_dm_rst_l));\n\n rvdffs #(1) sb_abmem_cmd_doneff (.din(sb_abmem_cmd_done_in), .dout(sb_abmem_cmd_done), .en(sb_abmem_cmd_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*);\n rvdffs #(1) sb_abmem_data_doneff (.din(sb_abmem_data_done_in), .dout(sb_abmem_data_done), .en(sb_abmem_data_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*);\n\n // FSM to control the debug mode entry, command send/recieve, and Resume flow.\n always_comb begin\n dbg_nxtstate = IDLE;\n dbg_state_en = 1'b0;\n abstractcs_busy_wren = 1'b0;\n abstractcs_busy_din = 1'b0;\n dbg_halt_req = dmcontrol_wren_Q & dmcontrol_reg[31]; // single pulse output to the core. Need to drive every time this register is written since core might be halted due to MPC\n dbg_resume_req = 1'b0; // single pulse output to the core\n dbg_sb_bus_error = 1'b0;\n data0_reg_wren2 = 1'b0;\n sb_abmem_cmd_done_in = 1'b0;\n sb_abmem_data_done_in = 1'b0;\n sb_abmem_cmd_done_en = 1'b0;\n sb_abmem_data_done_en = 1'b0;\n\n case (dbg_state)\n IDLE: begin\n dbg_nxtstate = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING; // initiate the halt command to the core\n dbg_state_en = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only; // when the jtag writes the halt bit in the DM register, OR when the status indicates H\n dbg_halt_req = dmcontrol_reg[31]; // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes\n end\n HALTING : begin\n dbg_nxtstate = HALTED; // Goto HALTED once the core sends an ACK\n dbg_state_en = dmstatus_reg[9] | dec_tlu_mpc_halted_only; // core indicates halted\n end\n HALTED: begin\n // wait for halted to go away before send to resume. Else start of new command\n dbg_nxtstate = dmstatus_reg[9] ? (resumereq ? RESUMING : (((command_reg[31:24] == 8'h2) & abmem_addr_external) ? SB_CMD_START : CORE_CMD_START)) :\n (dmcontrol_reg[31] ? HALTING : IDLE); // This is MPC halted case\n dbg_state_en = (dmstatus_reg[9] & resumereq) | execute_command | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only);\n abstractcs_busy_wren = dbg_state_en & ((dbg_nxtstate == CORE_CMD_START) | (dbg_nxtstate == SB_CMD_START)); // write busy when a new command was written by jtag\n abstractcs_busy_din = 1'b1;\n dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming\n end\n CORE_CMD_START: begin\n // Don't execute the command if cmderror or transfer=0 for abstract register access\n dbg_nxtstate = ((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) ? CMD_DONE : CORE_CMD_WAIT; // new command sent to the core\n dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]);\n end\n CORE_CMD_WAIT: begin\n dbg_nxtstate = CMD_DONE;\n dbg_state_en = core_dbg_cmd_done; // go to done state for one cycle after completing current command\n end\n SB_CMD_START: begin\n dbg_nxtstate = (|abstractcs_reg[10:8]) ? CMD_DONE : SB_CMD_SEND;\n dbg_state_en = (dbg_bus_clk_en & ~sb_cmd_pending) | (|abstractcs_reg[10:8]);\n end\n SB_CMD_SEND: begin\n sb_abmem_cmd_done_in = 1'b1;\n sb_abmem_data_done_in= 1'b1;\n sb_abmem_cmd_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_addr) & dbg_bus_clk_en;\n sb_abmem_data_done_en= (sb_bus_cmd_read | sb_bus_cmd_write_data) & dbg_bus_clk_en;\n dbg_nxtstate = SB_CMD_RESP;\n dbg_state_en = (sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en) & dbg_bus_clk_en;\n end\n SB_CMD_RESP: begin\n dbg_nxtstate = CMD_DONE;\n dbg_state_en = (sb_bus_rsp_read | sb_bus_rsp_write) & dbg_bus_clk_en;\n dbg_sb_bus_error = (sb_bus_rsp_read | sb_bus_rsp_write) & sb_bus_rsp_error & dbg_bus_clk_en;\n data0_reg_wren2 = dbg_state_en & ~sb_abmem_cmd_write & ~dbg_sb_bus_error;\n end\n CMD_DONE: begin\n dbg_nxtstate = HALTED;\n dbg_state_en = 1'b1;\n abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 )\n abstractcs_busy_din = 1'b0;\n sb_abmem_cmd_done_in = 1'b0;\n sb_abmem_data_done_in= 1'b0;\n sb_abmem_cmd_done_en = 1'b1;\n sb_abmem_data_done_en= 1'b1;\n end\n RESUMING : begin\n dbg_nxtstate = IDLE;\n dbg_state_en = dmstatus_reg[17]; // resume ack has been updated in the dmstatus register\n end\n /* All legal values are handled above. Exclude the default part from coverage. */\n /*pragma coverage off*/\n default : begin\n dbg_nxtstate = IDLE;\n dbg_state_en = 1'b0;\n abstractcs_busy_wren = 1'b0;\n abstractcs_busy_din = 1'b0;\n dbg_halt_req = 1'b0; // single pulse output to the core\n dbg_resume_req = 1'b0; // single pulse output to the core\n dbg_sb_bus_error = 1'b0;\n data0_reg_wren2 = 1'b0;\n sb_abmem_cmd_done_in = 1'b0;\n sb_abmem_data_done_in = 1'b0;\n sb_abmem_cmd_done_en = 1'b0;\n sb_abmem_data_done_en = 1'b0;\n end\n /*pragma coverage on*/\n endcase\n end // always_comb begin\n\n assign dmi_reg_rdata_din[31:0] = ({32{dmi_reg_addr == 7'h4}} & data0_reg[31:0]) |\n ({32{dmi_reg_addr == 7'h5}} & data1_reg[31:0]) |\n ({32{dmi_reg_addr == 7'h10}} & {2'b0,dmcontrol_reg[29],1'b0,dmcontrol_reg[27:0]}) | // Read0 to Write only bits\n ({32{dmi_reg_addr == 7'h11}} & dmstatus_reg[31:0]) |\n ({32{dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0]) |\n ({32{dmi_reg_addr == 7'h17}} & command_reg[31:0]) |\n ({32{dmi_reg_addr == 7'h18}} & {30'h0,abstractauto_reg[1:0]}) |\n ({32{dmi_reg_addr == 7'h40}} & haltsum0_reg[31:0]) |\n ({32{dmi_reg_addr == 7'h38}} & sbcs_reg[31:0]) |\n ({32{dmi_reg_addr == 7'h39}} & sbaddress0_reg[31:0]) |\n ({32{dmi_reg_addr == 7'h3c}} & sbdata0_reg[31:0]) |\n ({32{dmi_reg_addr == 7'h3d}} & sbdata1_reg[31:0]);\n\n\n rvdffs #($bits(state_t)) dbg_state_reg (.din(dbg_nxtstate), .dout({dbg_state}), .en(dbg_state_en), .rst_l(dbg_dm_rst_l & rst_l), .clk(dbg_free_clk));\n rvdffe #(32) dmi_rddata_reg (.din(dmi_reg_rdata_din[31:0]), .dout(dmi_reg_rdata[31:0]), .en(dmi_reg_en), .rst_l(dbg_dm_rst_l), .clk(clk), .*);\n\n assign abmem_addr[31:0] = data1_reg[31:0];\n assign abmem_addr_core_local = (abmem_addr_in_dccm_region | abmem_addr_in_iccm_region | abmem_addr_in_pic_region);\n assign abmem_addr_external = ~abmem_addr_core_local;\n\n assign abmem_addr_in_dccm_region = (abmem_addr[31:28] == pt.DCCM_REGION) & pt.DCCM_ENABLE;\n assign abmem_addr_in_iccm_region = (abmem_addr[31:28] == pt.ICCM_REGION) & pt.ICCM_ENABLE;\n assign abmem_addr_in_pic_region = (abmem_addr[31:28] == pt.PIC_REGION);\n\n // interface for the core\n assign dbg_cmd_addr[31:0] = (command_reg[31:24] == 8'h2) ? data1_reg[31:0] : {20'b0, command_reg[11:0]};\n assign dbg_cmd_wrdata[31:0] = data0_reg[31:0];\n assign dbg_cmd_valid = (dbg_state == CORE_CMD_START) & ~((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]) | ((command_reg[31:24] == 8'h2) & abmem_addr_external)) & dma_dbg_ready;\n assign dbg_cmd_write = command_reg[16];\n assign dbg_cmd_type[1:0] = (command_reg[31:24] == 8'h2) ? 2'b10 : {1'b0, (command_reg[15:12] == 4'b0)};\n assign dbg_cmd_size[1:0] = command_reg[21:20];\n\n assign dbg_cmd_addr_incr[3:0] = (command_reg[31:24] == 8'h2) ? (4'h1 << sb_abmem_cmd_size[1:0]) : 4'h1;\n assign dbg_cmd_curr_addr[31:0] = (command_reg[31:24] == 8'h2) ? data1_reg[31:0] : {16'b0, command_reg[15:0]};\n assign dbg_cmd_next_addr[31:0] = dbg_cmd_curr_addr[31:0] + {28'h0,dbg_cmd_addr_incr[3:0]};\n\n // Ask DMA to stop taking bus trxns since debug request is done\n assign dbg_dma_bubble = ((dbg_state == CORE_CMD_START) & ~(|abstractcs_reg[10:8])) | (dbg_state == CORE_CMD_WAIT);\n\n assign sb_cmd_pending = (sb_state == CMD_RD) | (sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR) | (sb_state == CMD_WR_DATA) | (sb_state == RSP_RD) | (sb_state == RSP_WR);\n assign sb_abmem_cmd_pending = (dbg_state == SB_CMD_START) | (dbg_state == SB_CMD_SEND) | (dbg_state== SB_CMD_RESP);\n\n\n // system bus FSM\n always_comb begin\n sb_nxtstate = SBIDLE;\n sb_state_en = 1'b0;\n sbcs_sbbusy_wren = 1'b0;\n sbcs_sbbusy_din = 1'b0;\n sbcs_sberror_wren = 1'b0;\n sbcs_sberror_din[2:0] = 3'b0;\n sbaddress0_reg_wren1 = 1'b0;\n case (sb_state)\n SBIDLE: begin\n sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD;\n sb_state_en = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];\n sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command\n sbcs_sbbusy_din = 1'b1;\n sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits\n sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];\n end\n WAIT_RD: begin\n sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;\n sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size;\n sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;\n sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;\n end\n WAIT_WR: begin\n sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_WR;\n sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size;\n sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;\n sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;\n end\n CMD_RD : begin\n sb_nxtstate = RSP_RD;\n sb_state_en = sb_bus_cmd_read & dbg_bus_clk_en;\n end\n CMD_WR : begin\n sb_nxtstate = (sb_bus_cmd_write_addr & sb_bus_cmd_write_data) ? RSP_WR : (sb_bus_cmd_write_data ? CMD_WR_ADDR : CMD_WR_DATA);\n sb_state_en = (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & dbg_bus_clk_en;\n end\n CMD_WR_ADDR : begin\n sb_nxtstate = RSP_WR;\n sb_state_en = sb_bus_cmd_write_addr & dbg_bus_clk_en;\n end\n CMD_WR_DATA : begin\n sb_nxtstate = RSP_WR;\n sb_state_en = sb_bus_cmd_write_data & dbg_bus_clk_en;\n end\n RSP_RD: begin\n sb_nxtstate = DONE;\n sb_state_en = sb_bus_rsp_read & dbg_bus_clk_en;\n sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error;\n sbcs_sberror_din[2:0] = 3'b010;\n end\n RSP_WR: begin\n sb_nxtstate = DONE;\n sb_state_en = sb_bus_rsp_write & dbg_bus_clk_en;\n sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error;\n sbcs_sberror_din[2:0] = 3'b010;\n end\n DONE: begin\n sb_nxtstate = SBIDLE;\n sb_state_en = 1'b1;\n sbcs_sbbusy_wren = 1'b1; // reset the single read\n sbcs_sbbusy_din = 1'b0;\n sbaddress0_reg_wren1 = sbcs_reg[16] & (sbcs_reg[14:12] == 3'b0); // auto increment was set and no error. Update to new address after completing the current command\n end\n /* All legal values are handled above. Exclude the default part from coverage. */\n /*pragma coverage off*/\n default : begin\n sb_nxtstate = SBIDLE;\n sb_state_en = 1'b0;\n sbcs_sbbusy_wren = 1'b0;\n sbcs_sbbusy_din = 1'b0;\n sbcs_sberror_wren = 1'b0;\n sbcs_sberror_din[2:0] = 3'b0;\n sbaddress0_reg_wren1 = 1'b0;\n end\n /*pragma coverage on*/\n endcase\n end // always_comb begin\n\n rvdffs #($bits(sb_state_t)) sb_state_reg (.din(sb_nxtstate), .dout({sb_state}), .en(sb_state_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));\n\n assign sb_abmem_cmd_write = command_reg[16];\n assign sb_abmem_cmd_size[2:0] = {1'b0, command_reg[21:20]};\n assign sb_abmem_cmd_addr[31:0] = abmem_addr[31:0];\n assign sb_abmem_cmd_wdata[31:0] = data0_reg[31:0];\n\n assign sb_cmd_size[2:0] = sbcs_reg[19:17];\n assign sb_cmd_wdata[63:0] = {sbdata1_reg[31:0], sbdata0_reg[31:0]};\n assign sb_cmd_addr[31:0] = sbaddress0_reg[31:0];\n\n assign sb_abmem_cmd_awvalid = (dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write & ~sb_abmem_cmd_done;\n assign sb_abmem_cmd_wvalid = (dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write & ~sb_abmem_data_done;\n assign sb_abmem_cmd_arvalid = (dbg_state == SB_CMD_SEND) & ~sb_abmem_cmd_write & ~sb_abmem_cmd_done & ~sb_abmem_data_done;\n assign sb_abmem_read_pend = (dbg_state == SB_CMD_RESP) & ~sb_abmem_cmd_write;\n\n assign sb_cmd_awvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR));\n assign sb_cmd_wvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_DATA));\n assign sb_cmd_arvalid = (sb_state == CMD_RD);\n assign sb_read_pend = (sb_state == RSP_RD);\n\n assign sb_axi_size[2:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend) ? sb_abmem_cmd_size[2:0] : sb_cmd_size[2:0];\n assign sb_axi_addr[31:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend) ? sb_abmem_cmd_addr[31:0] : sb_cmd_addr[31:0];\n assign sb_axi_wrdata[63:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid) ? {2{sb_abmem_cmd_wdata[31:0]}} : sb_cmd_wdata[63:0];\n\n // Generic bus response signals\n assign sb_bus_cmd_read = sb_axi_arvalid & sb_axi_arready;\n assign sb_bus_cmd_write_addr = sb_axi_awvalid & sb_axi_awready;\n assign sb_bus_cmd_write_data = sb_axi_wvalid & sb_axi_wready;\n\n assign sb_bus_rsp_read = sb_axi_rvalid & sb_axi_rready;\n assign sb_bus_rsp_write = sb_axi_bvalid & sb_axi_bready;\n assign sb_bus_rsp_error = (sb_bus_rsp_read & (|(sb_axi_rresp[1:0]))) | (sb_bus_rsp_write & (|(sb_axi_bresp[1:0])));\n\n // AXI Request signals\n assign sb_axi_awvalid = sb_abmem_cmd_awvalid | sb_cmd_awvalid;\n assign sb_axi_awaddr[31:0] = sb_axi_addr[31:0];\n assign sb_axi_awid[pt.SB_BUS_TAG-1:0] = '0;\n assign sb_axi_awsize[2:0] = sb_axi_size[2:0];\n assign sb_axi_awprot[2:0] = 3'b001;\n assign sb_axi_awcache[3:0] = 4'b1111;\n assign sb_axi_awregion[3:0] = sb_axi_addr[31:28];\n assign sb_axi_awlen[7:0] = '0;\n assign sb_axi_awburst[1:0] = 2'b01;\n assign sb_axi_awqos[3:0] = '0;\n assign sb_axi_awlock = '0;\n\n assign sb_axi_wvalid = sb_abmem_cmd_wvalid | sb_cmd_wvalid;\n assign sb_axi_wdata[63:0] = ({64{(sb_axi_size[2:0] == 3'h0)}} & {8{sb_axi_wrdata[7:0]}}) |\n ({64{(sb_axi_size[2:0] == 3'h1)}} & {4{sb_axi_wrdata[15:0]}}) |\n ({64{(sb_axi_size[2:0] == 3'h2)}} & {2{sb_axi_wrdata[31:0]}}) |\n ({64{(sb_axi_size[2:0] == 3'h3)}} & {sb_axi_wrdata[63:0]});\n assign sb_axi_wstrb[7:0] = ({8{(sb_axi_size[2:0] == 3'h0)}} & (8'h1 << sb_axi_addr[2:0])) |\n ({8{(sb_axi_size[2:0] == 3'h1)}} & (8'h3 << {sb_axi_addr[2:1],1'b0})) |\n ({8{(sb_axi_size[2:0] == 3'h2)}} & (8'hf << {sb_axi_addr[2],2'b0})) |\n ({8{(sb_axi_size[2:0] == 3'h3)}} & 8'hff);\n assign sb_axi_wlast = '1;\n\n assign sb_axi_arvalid = sb_abmem_cmd_arvalid | sb_cmd_arvalid;\n assign sb_axi_araddr[31:0] = sb_axi_addr[31:0];\n assign sb_axi_arid[pt.SB_BUS_TAG-1:0] = '0;\n assign sb_axi_arsize[2:0] = sb_axi_size[2:0];\n assign sb_axi_arprot[2:0] = 3'b001;\n assign sb_axi_arcache[3:0] = 4'b0;\n assign sb_axi_arregion[3:0] = sb_axi_addr[31:28];\n assign sb_axi_arlen[7:0] = '0;\n assign sb_axi_arburst[1:0] = 2'b01;\n assign sb_axi_arqos[3:0] = '0;\n assign sb_axi_arlock = '0;\n\n // AXI Response signals\n assign sb_axi_bready = 1'b1;\n\n assign sb_axi_rready = 1'b1;\n assign sb_bus_rdata[63:0] = ({64{sb_axi_size == 3'h0}} & ((sb_axi_rdata[63:0] >> 8*sb_axi_addr[2:0]) & 64'hff)) |\n ({64{sb_axi_size == 3'h1}} & ((sb_axi_rdata[63:0] >> 16*sb_axi_addr[2:1]) & 64'hffff)) |\n ({64{sb_axi_size == 3'h2}} & ((sb_axi_rdata[63:0] >> 32*sb_axi_addr[2]) & 64'hffff_ffff)) |\n ({64{sb_axi_size == 3'h3}} & sb_axi_rdata[63:0]);\n\n`ifdef RV_ASSERT_ON\n// assertion.\n// when the resume_ack is asserted then the dec_tlu_dbg_halted should be 0\n dm_check_resume_and_halted: assert property (@(posedge clk) disable iff(~rst_l) (~dec_tlu_resume_ack | ~dec_tlu_dbg_halted));\n\n assert_b2b_haltreq: assert property (@(posedge clk) disable iff (~(rst_l)) (##1 dbg_halt_req |=> ~dbg_halt_req)); // One cycle delay to fix weird issue around reset\n assert_halt_resume_onehot: assert #0 ($onehot0({dbg_halt_req, dbg_resume_req}));\n`endif\nendmodule\n" }, { "path": "design/dec/cdecode", "content": "\n.definition\n\n\n\n# invalid rs2=0\nc.add0 = [1001.....1....10]\nc.add1 = [1001......1...10]\nc.add2 = [1001.......1..10]\nc.add3 = [1001........1.10]\nc.add4 = [1001.........110]\n\n# invalid rs2=0\nc.mv0 = [1000.....1....10]\nc.mv1 = [1000......1...10]\nc.mv2 = [1000.......1..10]\nc.mv3 = [1000........1.10]\nc.mv4 = [1000.........110]\n\n\n# invalid if rs1=0\nc.jalr0 = [10011....0000010]\nc.jalr1 = [1001.1...0000010]\nc.jalr2 = [1001..1..0000010]\nc.jalr3 = [1001...1.0000010]\nc.jalr4 = [1001....10000010]\n\nc.addi = [000...........01]\n\n# invalid imm=0\nc.addi16sp0 = [011100010.....01]\nc.addi16sp1 = [011.000101....01]\nc.addi16sp2 = [011.00010.1...01]\nc.addi16sp3 = [011.00010..1..01]\nc.addi16sp4 = [011.00010...1.01]\nc.addi16sp5 = [011.00010....101]\n\n# invalid uimm=0\nc.addi4spn0 = [0001..........00]\nc.addi4spn1 = [000.1.........00]\nc.addi4spn2 = [000..1........00]\nc.addi4spn3 = [000...1.......00]\nc.addi4spn4 = [000....1......00]\nc.addi4spn5 = [000.....1.....00]\nc.addi4spn6 = [000......1....00]\nc.addi4spn7 = [000.......1...00]\n\n\nc.and = [100011...11...01]\nc.andi = [100.10........01]\nc.beqz = [110...........01]\nc.bnez = [111...........01]\nc.ebreak = [1001000000000010]\nc.j = [101...........01]\nc.jal = [001...........01]\n\n\nc.jr0 = [10001....0000010]\nc.jr1 = [1000.1...0000010]\nc.jr2 = [1000..1..0000010]\nc.jr3 = [1000...1.0000010]\nc.jr4 = [1000....10000010]\n\nc.li = [010...........01]\n\n# invalid rd=x2 or imm=0\nc.lui0 = [01111.........01]\nc.lui1 = [0111.1........01]\nc.lui2 = [0111..1.......01]\nc.lui3 = [0111...0......01]\nc.lui4 = [0111....1.....01]\nc.lui5 = [011.1....1....01]\nc.lui6 = [011..1...1....01]\nc.lui7 = [011...1..1....01]\nc.lui8 = [011....0.1....01]\nc.lui9 = [011.....11....01]\nc.lui10= [011.1.....1...01]\nc.lui11= [011..1....1...01]\nc.lui12 = [011...1...1...01]\nc.lui13 = [011....0..1...01]\nc.lui14 = [011.....1.1...01]\nc.lui15 = [011.1......1..01]\nc.lui16 = [011..1.....1..01]\nc.lui17 = [011...1....1..01]\nc.lui18 = [011....0...1..01]\nc.lui19 = [011.....1..1..01]\nc.lui20 = [011.1.......1.01]\nc.lui21 = [011..1......1.01]\nc.lui22 = [011...1.....1.01]\nc.lui23 = [011....0....1.01]\nc.lui24 = [011.....1...1.01]\nc.lui25 = [011.1........101]\nc.lui26 = [011..1.......101]\nc.lui27 = [011...1......101]\nc.lui28 = [011....0.....101]\nc.lui29 = [011.....1....101]\n\n\nc.lw = [010...........00]\n\n\n# invalid if rd=x0\nc.lwsp0 = [010.....1.....10]\nc.lwsp1 = [010....1......10]\nc.lwsp2 = [010...1.......10]\nc.lwsp3 = [010..1........10]\nc.lwsp4 = [010.1.........10]\n\nc.or = [100011...10...01]\n\n# bit 5 of the shift must be 0 to be legal\nc.slli = [0000..........10]\n\nc.srai = [100001........01]\n\nc.srli = [100000........01]\n\nc.sub = [100011...00...01]\nc.sw = [110...........00]\nc.swsp = [110...........10]\nc.xor = [100011...01...01]\n\n\n.input\nrv32c = {\n i[15]\n i[14]\n i[13]\n i[12]\n i[11]\n i[10]\n i[9]\n i[8]\n i[7]\n i[6]\n i[5]\n i[4]\n i[3]\n i[2]\n i[1]\n i[0]\n}\n\n.output\nrv32c = {\n rdrd\n rdrs1\n rs2rs2\n rdprd\n rdprs1\n rs2prs2\n rs2prd\n uimm9_2\n ulwimm6_2\n ulwspimm7_2\n rdeq2\n rdeq1\n rs1eq2\n sbroffset8_1\n simm9_4\n simm5_0\n sjaloffset11_1\n sluimm17_12\n uimm5_0\n uswimm6_2\n uswspimm7_2\n o[31]\n o[30]\n o[29]\n o[28]\n o[27]\n o[26]\n o[25]\n o[24]\n o[23]\n o[22]\n o[21]\n o[20]\n o[19]\n o[18]\n o[17]\n o[16]\n o[15]\n o[14]\n o[13]\n o[12]\n o[11]\n o[10]\n o[9]\n o[8]\n o[7]\n o[6]\n o[5]\n o[4]\n o[3]\n o[2]\n o[1]\n o[0]\n }\n\n# assign rs2d[4:0] = i[6:2];\n#\n# assign rdd[4:0] = i[11:7];\n#\n# assign rdpd[4:0] = {2'b01, i[9:7]};\n#\n# assign rs2pd[4:0] = {2'b01, i[4:2]};\n\n.decode\n\n\n\n\nrv32c[c.add{0-4}] = { rdrd rdrs1 rs2rs2 o[5] o[4] o[1] o[0] }\n\nrv32c[c.mv{0-4}] = { rdrd rs2rs2 o[5] o[4] o[1] o[0] }\n\nrv32c[c.addi] = { rdrd rdrs1 simm5_0 o[4] o[1] o[0] }\n\nrv32c[c.addi16sp{0-5}] = { rdeq2 rs1eq2 simm9_4 o[4] o[1] o[0] }\nrv32c[c.addi4spn{0-7}] = { rs2prd rs1eq2 uimm9_2 o[4] o[1] o[0] }\n\n\nrv32c[c.and] = { rdprd rdprs1 rs2prs2 o[14] o[13] o[12] o[5] o[4] o[1] o[0] }\nrv32c[c.andi] = { rdprd rdprs1 simm5_0 o[14] o[13] o[12] o[4] o[1] o[0] }\nrv32c[c.beqz] = { rdprs1 sbroffset8_1 o[6] o[5] o[1] o[0] }\nrv32c[c.bnez] = { rdprs1 sbroffset8_1 o[12] o[6] o[5] o[1] o[0] }\n\n\nrv32c[c.ebreak] = { o[20] o[6] o[5] o[4] o[1] o[0] }\n\nrv32c[c.j] = { sjaloffset11_1 o[6] o[5] o[3] o[2] o[1] o[0] }\nrv32c[c.jal] = { sjaloffset11_1 rdeq1 o[6] o[5] o[3] o[2] o[1] o[0] }\n\n\nrv32c[c.jalr{0-4}] = { rdeq1 rdrs1 o[6] o[5] o[2] o[1] o[0] }\nrv32c[c.jr{0-4}] = { rdrs1 o[6] o[5] o[2] o[1] o[0] }\nrv32c[c.li] = { rdrd simm5_0 o[4] o[1] o[0] }\n\nrv32c[c.lui{0-29}] = { rdrd sluimm17_12 o[5] o[4] o[2] o[1] o[0] }\nrv32c[c.lw] = { rs2prd rdprs1 ulwimm6_2 o[13] o[1] o[0] }\nrv32c[c.lwsp{0-4}] = { rdrd rs1eq2 ulwspimm7_2 o[13] o[1] o[0] }\n\n\nrv32c[c.or] = { rdprd rdprs1 rs2prs2 o[14] o[13] o[5] o[4] o[1] o[0] }\n\nrv32c[c.slli] = { rdrd rdrs1 uimm5_0 o[12] o[4] o[1] o[0] }\nrv32c[c.srai] = { rdprd rdprs1 uimm5_0 o[30] o[14] o[12] o[4] o[1] o[0] }\nrv32c[c.srli] = { rdprd rdprs1 uimm5_0 o[14] o[12] o[4] o[1] o[0] }\n\n\nrv32c[c.sub] = { rdprd rdprs1 rs2prs2 o[30] o[5] o[4] o[1] o[0] }\nrv32c[c.sw] = { rdprs1 rs2prs2 uswimm6_2 o[13] o[5] o[1] o[0] }\nrv32c[c.swsp] = { rs2rs2 rs1eq2 uswspimm7_2 o[13] o[5] o[1] o[0] }\nrv32c[c.xor] = { rdprd rdprs1 rs2prs2 o[14] o[5] o[4] o[1] o[0] }\n\n\n\n.end" }, { "path": "design/dec/csrdecode_m", "content": ".definition\n\ncsr_misa = [001100000001]\ncsr_mvendorid = [111100010001]\ncsr_marchid = [111100010010]\ncsr_mimpid = [111100010011]\ncsr_mhartid = [111100010100]\ncsr_mstatus = [001100000000]\ncsr_mtvec = [001100000101]\ncsr_mip = [001101000100]\ncsr_mie = [001100000100]\ncsr_mcyclel = [101100000000]\ncsr_mcycleh = [101110000000]\ncsr_minstretl = [101100000010]\ncsr_minstreth = [101110000010]\ncsr_mscratch = [001101000000]\ncsr_mepc = [001101000001]\ncsr_mcause = [001101000010]\ncsr_mscause = [011111111111]\ncsr_mtval = [001101000011]\ncsr_mrac = [011111000000]\ncsr_dmst = [011111000100]\ncsr_mdeau = [101111000000]\ncsr_mdseac = [111111000000]\ncsr_meivt = [101111001000]\ncsr_meihap = [111111001000]\ncsr_meipt = [101111001001]\ncsr_meicpct = [101111001010]\ncsr_meicurpl = [101111001100]\ncsr_meicidpl = [101111001011]\ncsr_dcsr = [011110110000]\ncsr_dpc = [011110110001]\ncsr_dicawics = [011111001000]\ncsr_dicad0h = [011111001100]\ncsr_dicad0 = [011111001001]\ncsr_dicad1 = [011111001010]\ncsr_dicago = [011111001011]\ncsr_mtsel = [011110100000]\ncsr_mtdata1 = [011110100001]\ncsr_mtdata2 = [011110100010]\ncsr_mhpmc3 = [101100000011]\ncsr_mhpmc4 = [101100000100]\ncsr_mhpmc5 = [101100000101]\ncsr_mhpmc6 = [101100000110]\ncsr_mhpmc3h = [101110000011]\ncsr_mhpmc4h = [101110000100]\ncsr_mhpmc5h = [101110000101]\ncsr_mhpmc6h = [101110000110]\ncsr_mhpme3 = [001100100011]\ncsr_mhpme4 = [001100100100]\ncsr_mhpme5 = [001100100101]\ncsr_mhpme6 = [001100100110]\ncsr_micect = [011111110000]\ncsr_miccmect = [011111110001]\ncsr_mdccmect = [011111110010]\ncsr_mpmc = [011111000110]\ncsr_mcgc = [011111111000]\ncsr_mcpc = [011111000010]\ncsr_mfdc = [011111111001]\ncsr_mitctl0 = [011111010100]\ncsr_mitctl1 = [011111010111]\ncsr_mitb0 = [011111010011]\ncsr_mitb1 = [011111010110]\ncsr_mitcnt0 = [011111010010]\ncsr_mitcnt1 = [011111010101]\ncsr_perfva = [101100000111]\ncsr_perfvb = [101100001...]\ncsr_perfvc = [10110001....]\ncsr_perfvd = [101110000111]\ncsr_perfve = [101110001...]\ncsr_perfvf = [10111001....]\ncsr_perfvg = [001100100111]\ncsr_perfvh = [001100101...]\ncsr_perfvi = [00110011....]\ncsr_mcountinhibit = [001100100000]\ncsr_mfdht = [011111001110]\ncsr_mfdhs = [011111001111]\ncsr_pmpcfg = [00111010....]\ncsr_pmpaddr0 = [00111011....]\ncsr_pmpaddr16 = [00111100....]\ncsr_pmpaddr32 = [00111101....]\ncsr_pmpaddr48 = [00111110....]\n\n.input\n\ncsr = {\n dec_csr_rdaddr_d[11]\n dec_csr_rdaddr_d[10]\n dec_csr_rdaddr_d[9]\n dec_csr_rdaddr_d[8]\n dec_csr_rdaddr_d[7]\n dec_csr_rdaddr_d[6]\n dec_csr_rdaddr_d[5]\n dec_csr_rdaddr_d[4]\n dec_csr_rdaddr_d[3]\n dec_csr_rdaddr_d[2]\n dec_csr_rdaddr_d[1]\n dec_csr_rdaddr_d[0]\n}\n\n.output\n\ncsr = {\n csr_misa\n csr_mvendorid\n csr_marchid\n csr_mimpid\n csr_mhartid\n csr_mstatus\n csr_mtvec\n csr_mip\n csr_mie\n csr_mcyclel\n csr_mcycleh\n csr_minstretl\n csr_minstreth\n csr_mscratch\n csr_mepc\n csr_mcause\n csr_mscause\n csr_mtval\n csr_mrac\n csr_dmst\n csr_mdseac\n csr_meihap\n csr_meivt\n csr_meipt\n csr_meicurpl\n csr_meicidpl\n csr_dcsr\n csr_mcgc\n csr_mfdc\n csr_dpc\n csr_mtsel\n csr_mtdata1\n csr_mtdata2\n csr_mhpmc3\n csr_mhpmc4\n csr_mhpmc5\n csr_mhpmc6\n csr_mhpmc3h\n csr_mhpmc4h\n csr_mhpmc5h\n csr_mhpmc6h\n csr_mhpme3\n csr_mhpme4\n csr_mhpme5\n csr_mhpme6\n csr_mcountinhibit\n csr_mitctl0\n csr_mitctl1\n csr_mitb0\n csr_mitb1\n csr_mitcnt0\n csr_mitcnt1\ncsr_perfva\ncsr_perfvb\ncsr_perfvc\ncsr_perfvd\ncsr_perfve\ncsr_perfvf\ncsr_perfvg\ncsr_perfvh\ncsr_perfvi\n csr_mpmc\n csr_mcpc\n csr_meicpct\n csr_mdeau\n csr_micect\n csr_miccmect\n csr_mdccmect\ncsr_mfdht\ncsr_mfdhs\ncsr_dicawics\ncsr_dicad0h\ncsr_dicad0\ncsr_dicad1\ncsr_dicago\n csr_pmpcfg\n csr_pmpaddr0\n csr_pmpaddr16\n csr_pmpaddr32\n csr_pmpaddr48\n valid_only\n presync\n postsync\n}\n\n.decode\n\ncsr[ csr_misa ] = { csr_misa }\ncsr[ csr_mvendorid ] = { csr_mvendorid }\ncsr[ csr_marchid ] = { csr_marchid }\ncsr[ csr_mimpid ] = { csr_mimpid }\ncsr[ csr_mhartid ] = { csr_mhartid }\ncsr[ csr_mstatus ] = { csr_mstatus postsync }\ncsr[ csr_mtvec ] = { csr_mtvec postsync}\ncsr[ csr_mip ] = { csr_mip }\ncsr[ csr_mie ] = { csr_mie }\ncsr[ csr_mcyclel ] = { csr_mcyclel }\ncsr[ csr_mcycleh ] = { csr_mcycleh }\ncsr[ csr_minstretl ] = { csr_minstretl presync }\ncsr[ csr_minstreth ] = { csr_minstreth presync }\ncsr[ csr_mscratch ] = { csr_mscratch }\ncsr[ csr_mepc ] = { csr_mepc postsync}\ncsr[ csr_mcause ] = { csr_mcause }\ncsr[ csr_mscause ] = { csr_mscause }\ncsr[ csr_mtval ] = { csr_mtval }\ncsr[ csr_mrac ] = { csr_mrac postsync }\ncsr[ csr_dmst ] = { csr_dmst postsync}\ncsr[ csr_mdseac ] = { csr_mdseac }\ncsr[ csr_meipt ] = { csr_meipt }\ncsr[ csr_meihap ] = { csr_meihap }\ncsr[ csr_meivt ] = { csr_meivt }\ncsr[ csr_meicurpl ] = { csr_meicurpl }\ncsr[ csr_mdeau ] = { csr_mdeau }\ncsr[ csr_meicpct ] = { csr_meicpct }\ncsr[ csr_mpmc ] = { csr_mpmc }\ncsr[ csr_mcpc ] = { csr_mcpc presync postsync }\ncsr[ csr_meicidpl ] = { csr_meicidpl }\ncsr[ csr_mcgc ] = { csr_mcgc }\ncsr[ csr_mcountinhibit] = { csr_mcountinhibit presync postsync }\ncsr[ csr_mfdc ] = { csr_mfdc presync postsync }\ncsr[ csr_dcsr ] = { csr_dcsr }\ncsr[ csr_dpc ] = { csr_dpc }\ncsr[ csr_mtsel ] = { csr_mtsel }\ncsr[ csr_mtdata1 ] = { csr_mtdata1 presync postsync }\ncsr[ csr_mtdata2 ] = { csr_mtdata2 postsync }\ncsr[ csr_mhpmc3 ] = { csr_mhpmc3 presync }\ncsr[ csr_mhpmc4 ] = { csr_mhpmc4 presync }\ncsr[ csr_mhpmc5 ] = { csr_mhpmc5 presync }\ncsr[ csr_mhpmc6 ] = { csr_mhpmc6 presync }\ncsr[ csr_mhpmc3h ] = { csr_mhpmc3h presync }\ncsr[ csr_mhpmc4h ] = { csr_mhpmc4h presync }\ncsr[ csr_mhpmc5h ] = { csr_mhpmc5h presync }\ncsr[ csr_mhpmc6h ] = { csr_mhpmc6h presync }\ncsr[ csr_mhpme3 ] = { csr_mhpme3 }\ncsr[ csr_mhpme4 ] = { csr_mhpme4 }\ncsr[ csr_mhpme5 ] = { csr_mhpme5 }\ncsr[ csr_mhpme6 ] = { csr_mhpme6 }\ncsr[ csr_micect ] = { csr_micect }\ncsr[ csr_miccmect ] = { csr_miccmect }\ncsr[ csr_mdccmect ] = { csr_mdccmect }\ncsr[ csr_dicawics ] = { csr_dicawics }\ncsr[ csr_dicad0h ] = { csr_dicad0h }\ncsr[ csr_dicad0 ] = { csr_dicad0 }\ncsr[ csr_dicad1 ] = { csr_dicad1 }\ncsr[ csr_dicago ] = { csr_dicago }\ncsr[ csr_mitctl0 ] = { csr_mitctl0 }\ncsr[ csr_mitctl1 ] = { csr_mitctl1 }\ncsr[ csr_mitb0 ] = { csr_mitb0 }\ncsr[ csr_mitb1 ] = { csr_mitb1 }\ncsr[ csr_mitcnt0 ] = { csr_mitcnt0 }\ncsr[ csr_mitcnt1 ] = { csr_mitcnt1 }\ncsr[ csr_mfdht ] = { csr_mfdht }\ncsr[ csr_mfdhs ] = { csr_mfdhs }\ncsr[ csr_mcountinhibit] = { csr_mcountinhibit presync postsync }\n\ncsr[ csr_perfva ] = { valid_only }\ncsr[ csr_perfvb ] = { valid_only }\ncsr[ csr_perfvc ] = { valid_only }\ncsr[ csr_perfvd ] = { valid_only }\ncsr[ csr_perfve ] = { valid_only }\ncsr[ csr_perfvf ] = { valid_only }\ncsr[ csr_perfvg ] = { valid_only }\ncsr[ csr_perfvh ] = { valid_only }\ncsr[ csr_perfvi ] = { valid_only }\n\ncsr[ csr_pmpcfg ] = { csr_pmpcfg }\ncsr[ csr_pmpaddr0 ] = { csr_pmpaddr0 }\ncsr[ csr_pmpaddr16 ] = { csr_pmpaddr16 }\ncsr[ csr_pmpaddr32 ] = { csr_pmpaddr32 }\ncsr[ csr_pmpaddr48 ] = { csr_pmpaddr48 }\n\n.end\n" }, { "path": "design/dec/csrdecode_mu", "content": ".definition\n\ncsr_misa = [001100000001]\ncsr_mvendorid = [111100010001]\ncsr_marchid = [111100010010]\ncsr_mimpid = [111100010011]\ncsr_mhartid = [111100010100]\ncsr_mstatus = [001100000000]\ncsr_mtvec = [001100000101]\ncsr_mip = [001101000100]\ncsr_mie = [001100000100]\ncsr_mcyclel = [101100000000]\ncsr_mcycleh = [101110000000]\ncsr_minstretl = [101100000010]\ncsr_minstreth = [101110000010]\ncsr_mscratch = [001101000000]\ncsr_mepc = [001101000001]\ncsr_mcause = [001101000010]\ncsr_mscause = [011111111111]\ncsr_mtval = [001101000011]\ncsr_mrac = [011111000000]\ncsr_dmst = [011111000100]\ncsr_mdeau = [101111000000]\ncsr_mdseac = [111111000000]\ncsr_meivt = [101111001000]\ncsr_meihap = [111111001000]\ncsr_meipt = [101111001001]\ncsr_meicpct = [101111001010]\ncsr_meicurpl = [101111001100]\ncsr_meicidpl = [101111001011]\ncsr_dcsr = [011110110000]\ncsr_dpc = [011110110001]\ncsr_dicawics = [011111001000]\ncsr_dicad0h = [011111001100]\ncsr_dicad0 = [011111001001]\ncsr_dicad1 = [011111001010]\ncsr_dicago = [011111001011]\ncsr_mtsel = [011110100000]\ncsr_mtdata1 = [011110100001]\ncsr_mtdata2 = [011110100010]\ncsr_mhpmc3 = [101100000011]\ncsr_mhpmc4 = [101100000100]\ncsr_mhpmc5 = [101100000101]\ncsr_mhpmc6 = [101100000110]\ncsr_mhpmc3h = [101110000011]\ncsr_mhpmc4h = [101110000100]\ncsr_mhpmc5h = [101110000101]\ncsr_mhpmc6h = [101110000110]\ncsr_mhpme3 = [001100100011]\ncsr_mhpme4 = [001100100100]\ncsr_mhpme5 = [001100100101]\ncsr_mhpme6 = [001100100110]\ncsr_micect = [011111110000]\ncsr_miccmect = [011111110001]\ncsr_mdccmect = [011111110010]\ncsr_mpmc = [011111000110]\ncsr_mcgc = [011111111000]\ncsr_mcpc = [011111000010]\ncsr_mfdc = [011111111001]\ncsr_mitctl0 = [011111010100]\ncsr_mitctl1 = [011111010111]\ncsr_mitb0 = [011111010011]\ncsr_mitb1 = [011111010110]\ncsr_mitcnt0 = [011111010010]\ncsr_mitcnt1 = [011111010101]\ncsr_perfva = [101100000111]\ncsr_perfvb = [101100001...]\ncsr_perfvc = [10110001....]\ncsr_perfvd = [101110000111]\ncsr_perfve = [101110001...]\ncsr_perfvf = [10111001....]\ncsr_perfvg = [001100100111]\ncsr_perfvh = [001100101...]\ncsr_perfvi = [00110011....]\ncsr_mcounteren = [001100000110]\ncsr_mcountinhibit = [001100100000]\ncsr_mfdht = [011111001110]\ncsr_mfdhs = [011111001111]\ncsr_menvcfg = [001100001010]\ncsr_menvcfgh = [001100011010]\ncsr_pmpcfg = [00111010....]\ncsr_pmpaddr0 = [00111011....]\ncsr_pmpaddr16 = [00111100....]\ncsr_pmpaddr32 = [00111101....]\ncsr_pmpaddr48 = [00111110....]\ncsr_cyclel = [110000000000]\ncsr_cycleh = [110010000000]\ncsr_instretl = [110000000010]\ncsr_instreth = [110010000010]\ncsr_hpmc3 = [110000000011]\ncsr_hpmc4 = [110000000100]\ncsr_hpmc5 = [110000000101]\ncsr_hpmc6 = [110000000110]\ncsr_hpmc3h = [110010000011]\ncsr_hpmc4h = [110010000100]\ncsr_hpmc5h = [110010000101]\ncsr_hpmc6h = [110010000110]\ncsr_mseccfgl = [011101000111]\ncsr_mseccfgh = [011101010111]\n\n.input\n\ncsr = {\n dec_csr_rdaddr_d[11]\n dec_csr_rdaddr_d[10]\n dec_csr_rdaddr_d[9]\n dec_csr_rdaddr_d[8]\n dec_csr_rdaddr_d[7]\n dec_csr_rdaddr_d[6]\n dec_csr_rdaddr_d[5]\n dec_csr_rdaddr_d[4]\n dec_csr_rdaddr_d[3]\n dec_csr_rdaddr_d[2]\n dec_csr_rdaddr_d[1]\n dec_csr_rdaddr_d[0]\n}\n\n.output\n\ncsr = {\n csr_misa\n csr_mvendorid\n csr_marchid\n csr_mimpid\n csr_mhartid\n csr_mstatus\n csr_mtvec\n csr_mip\n csr_mie\n csr_mcyclel\n csr_mcycleh\n csr_minstretl\n csr_minstreth\n csr_mscratch\n csr_mepc\n csr_mcause\n csr_mscause\n csr_mtval\n csr_mrac\n csr_dmst\n csr_mdseac\n csr_meihap\n csr_meivt\n csr_meipt\n csr_meicurpl\n csr_meicidpl\n csr_dcsr\n csr_mcgc\n csr_mfdc\n csr_dpc\n csr_mtsel\n csr_mtdata1\n csr_mtdata2\n csr_mhpmc3\n csr_mhpmc4\n csr_mhpmc5\n csr_mhpmc6\n csr_mhpmc3h\n csr_mhpmc4h\n csr_mhpmc5h\n csr_mhpmc6h\n csr_mhpme3\n csr_mhpme4\n csr_mhpme5\n csr_mhpme6\n csr_mcounteren\n csr_mcountinhibit\n csr_mitctl0\n csr_mitctl1\n csr_mitb0\n csr_mitb1\n csr_mitcnt0\n csr_mitcnt1\ncsr_perfva\ncsr_perfvb\ncsr_perfvc\ncsr_perfvd\ncsr_perfve\ncsr_perfvf\ncsr_perfvg\ncsr_perfvh\ncsr_perfvi\n csr_mpmc\n csr_mcpc\n csr_meicpct\n csr_mdeau\n csr_micect\n csr_miccmect\n csr_mdccmect\ncsr_mfdht\ncsr_mfdhs\ncsr_dicawics\ncsr_dicad0h\ncsr_dicad0\ncsr_dicad1\ncsr_dicago\n csr_menvcfg \n csr_menvcfgh\n csr_pmpcfg\n csr_pmpaddr0\n csr_pmpaddr16\n csr_pmpaddr32\n csr_pmpaddr48\n csr_cyclel\n csr_cycleh\n csr_instretl\n csr_instreth\n csr_hpmc3\n csr_hpmc4\n csr_hpmc5\n csr_hpmc6\n csr_hpmc3h\n csr_hpmc4h\n csr_hpmc5h\n csr_hpmc6h\n csr_mseccfgl\n csr_mseccfgh\n valid_only\n presync\n postsync\n}\n\n.decode\n\ncsr[ csr_misa ] = { csr_misa }\ncsr[ csr_mvendorid ] = { csr_mvendorid }\ncsr[ csr_marchid ] = { csr_marchid }\ncsr[ csr_mimpid ] = { csr_mimpid }\ncsr[ csr_mhartid ] = { csr_mhartid }\ncsr[ csr_mstatus ] = { csr_mstatus postsync }\ncsr[ csr_mtvec ] = { csr_mtvec postsync}\ncsr[ csr_mip ] = { csr_mip }\ncsr[ csr_mie ] = { csr_mie }\ncsr[ csr_mcyclel ] = { csr_mcyclel }\ncsr[ csr_mcycleh ] = { csr_mcycleh }\ncsr[ csr_minstretl ] = { csr_minstretl presync }\ncsr[ csr_minstreth ] = { csr_minstreth presync }\ncsr[ csr_mscratch ] = { csr_mscratch }\ncsr[ csr_mepc ] = { csr_mepc postsync}\ncsr[ csr_mcause ] = { csr_mcause }\ncsr[ csr_mscause ] = { csr_mscause }\ncsr[ csr_mtval ] = { csr_mtval }\ncsr[ csr_mrac ] = { csr_mrac postsync }\ncsr[ csr_dmst ] = { csr_dmst postsync}\ncsr[ csr_mdseac ] = { csr_mdseac }\ncsr[ csr_meipt ] = { csr_meipt }\ncsr[ csr_meihap ] = { csr_meihap }\ncsr[ csr_meivt ] = { csr_meivt }\ncsr[ csr_meicurpl ] = { csr_meicurpl }\ncsr[ csr_mdeau ] = { csr_mdeau }\ncsr[ csr_meicpct ] = { csr_meicpct }\ncsr[ csr_mpmc ] = { csr_mpmc }\ncsr[ csr_mcpc ] = { csr_mcpc presync postsync }\ncsr[ csr_meicidpl ] = { csr_meicidpl }\ncsr[ csr_mcgc ] = { csr_mcgc }\ncsr[ csr_mcountinhibit] = { csr_mcountinhibit presync postsync }\ncsr[ csr_mfdc ] = { csr_mfdc presync postsync }\ncsr[ csr_dcsr ] = { csr_dcsr }\ncsr[ csr_dpc ] = { csr_dpc }\ncsr[ csr_mtsel ] = { csr_mtsel }\ncsr[ csr_mtdata1 ] = { csr_mtdata1 presync postsync }\ncsr[ csr_mtdata2 ] = { csr_mtdata2 postsync }\ncsr[ csr_mhpmc3 ] = { csr_mhpmc3 presync }\ncsr[ csr_mhpmc4 ] = { csr_mhpmc4 presync }\ncsr[ csr_mhpmc5 ] = { csr_mhpmc5 presync }\ncsr[ csr_mhpmc6 ] = { csr_mhpmc6 presync }\ncsr[ csr_mhpmc3h ] = { csr_mhpmc3h presync }\ncsr[ csr_mhpmc4h ] = { csr_mhpmc4h presync }\ncsr[ csr_mhpmc5h ] = { csr_mhpmc5h presync }\ncsr[ csr_mhpmc6h ] = { csr_mhpmc6h presync }\ncsr[ csr_mhpme3 ] = { csr_mhpme3 }\ncsr[ csr_mhpme4 ] = { csr_mhpme4 }\ncsr[ csr_mhpme5 ] = { csr_mhpme5 }\ncsr[ csr_mhpme6 ] = { csr_mhpme6 }\ncsr[ csr_micect ] = { csr_micect }\ncsr[ csr_miccmect ] = { csr_miccmect }\ncsr[ csr_mdccmect ] = { csr_mdccmect }\ncsr[ csr_dicawics ] = { csr_dicawics }\ncsr[ csr_dicad0h ] = { csr_dicad0h }\ncsr[ csr_dicad0 ] = { csr_dicad0 }\ncsr[ csr_dicad1 ] = { csr_dicad1 }\ncsr[ csr_dicago ] = { csr_dicago }\ncsr[ csr_mitctl0 ] = { csr_mitctl0 }\ncsr[ csr_mitctl1 ] = { csr_mitctl1 }\ncsr[ csr_mitb0 ] = { csr_mitb0 }\ncsr[ csr_mitb1 ] = { csr_mitb1 }\ncsr[ csr_mitcnt0 ] = { csr_mitcnt0 }\ncsr[ csr_mitcnt1 ] = { csr_mitcnt1 }\ncsr[ csr_mfdht ] = { csr_mfdht }\ncsr[ csr_mfdhs ] = { csr_mfdhs }\ncsr[ csr_menvcfg ] = { csr_menvcfg }\ncsr[ csr_menvcfgh ] = { csr_menvcfgh }\ncsr[ csr_mcounteren ] = { csr_mcounteren }\ncsr[ csr_mcountinhibit] = { csr_mcountinhibit presync postsync }\n\ncsr[ csr_perfva ] = { valid_only }\ncsr[ csr_perfvb ] = { valid_only }\ncsr[ csr_perfvc ] = { valid_only }\ncsr[ csr_perfvd ] = { valid_only }\ncsr[ csr_perfve ] = { valid_only }\ncsr[ csr_perfvf ] = { valid_only }\ncsr[ csr_perfvg ] = { valid_only }\ncsr[ csr_perfvh ] = { valid_only }\ncsr[ csr_perfvi ] = { valid_only }\n\ncsr[ csr_pmpcfg ] = { csr_pmpcfg }\ncsr[ csr_pmpaddr0 ] = { csr_pmpaddr0 }\ncsr[ csr_pmpaddr16 ] = { csr_pmpaddr16 }\ncsr[ csr_pmpaddr32 ] = { csr_pmpaddr32 }\ncsr[ csr_pmpaddr48 ] = { csr_pmpaddr48 }\n\ncsr[ csr_cyclel ] = { csr_cyclel }\ncsr[ csr_cycleh ] = { csr_cycleh }\ncsr[ csr_instretl ] = { csr_instretl presync }\ncsr[ csr_instreth ] = { csr_instreth presync }\ncsr[ csr_hpmc3 ] = { csr_hpmc3 presync }\ncsr[ csr_hpmc4 ] = { csr_hpmc4 presync }\ncsr[ csr_hpmc5 ] = { csr_hpmc5 presync }\ncsr[ csr_hpmc6 ] = { csr_hpmc6 presync }\ncsr[ csr_hpmc3h ] = { csr_hpmc3h presync }\ncsr[ csr_hpmc4h ] = { csr_hpmc4h presync }\ncsr[ csr_hpmc5h ] = { csr_hpmc5h presync }\ncsr[ csr_hpmc6h ] = { csr_hpmc6h presync }\n\ncsr[ csr_mseccfgl ] = { csr_mseccfgl }\ncsr[ csr_mseccfgh ] = { csr_mseccfgh }\n\n.end\n" }, { "path": "design/dec/decode", "content": "\n.definition\n\nclz = [011000000000.....001.....0010011]\nctz = [011000000001.....001.....0010011]\ncpop = [011000000010.....001.....0010011]\nsext_b = [011000000100.....001.....0010011]\nsext_h = [011000000101.....001.....0010011]\n\nmin = [0000101..........100.....0110011]\nmax = [0000101..........110.....0110011]\nminu = [0000101..........101.....0110011]\nmaxu = [0000101..........111.....0110011]\n\nandn = [0100000..........111.....0110011]\norn = [0100000..........110.....0110011]\nxnor = [0100000..........100.....0110011]\n\n#pack = [0000100..........100.....0110011]\nzext_h = [000010000000.....100.....0110011]\npack1 = [000010000001.....100.....0110011]\npack2 = [000010000010.....100.....0110011]\npack3 = [000010000011.....100.....0110011]\npack4 = [000010000100.....100.....0110011]\npack5 = [000010000101.....100.....0110011]\npack6 = [000010000110.....100.....0110011]\npack7 = [000010000111.....100.....0110011]\npack8 = [000010001000.....100.....0110011]\npack9 = [000010001001.....100.....0110011]\npack10 = [000010001010.....100.....0110011]\npack11 = [000010001011.....100.....0110011]\npack12 = [000010001100.....100.....0110011]\npack13 = [000010001101.....100.....0110011]\npack14 = [000010001110.....100.....0110011]\npack15 = [000010001111.....100.....0110011]\npack16 = [000010010000.....100.....0110011]\npack17 = [000010010001.....100.....0110011]\npack18 = [000010010010.....100.....0110011]\npack19 = [000010010011.....100.....0110011]\npack20 = [000010010100.....100.....0110011]\npack21 = [000010010101.....100.....0110011]\npack22 = [000010010110.....100.....0110011]\npack23 = [000010010111.....100.....0110011]\npack24 = [000010011000.....100.....0110011]\npack25 = [000010011001.....100.....0110011]\npack26 = [000010011010.....100.....0110011]\npack27 = [000010011011.....100.....0110011]\npack28 = [000010011100.....100.....0110011]\npack29 = [000010011101.....100.....0110011]\npack30 = [000010011110.....100.....0110011]\npack31 = [000010011111.....100.....0110011]\n\npacku = [0100100..........100.....0110011]\npackh = [0000100..........111.....0110011]\nrol = [0110000..........001.....0110011]\nror = [0110000..........101.....0110011]\nrori = [0110000..........101.....0010011]\n\nsh1add = [0010000..........010.....0110011]\nsh2add = [0010000..........100.....0110011]\nsh3add = [0010000..........110.....0110011]\n\nbset = [0010100..........001.....0110011]\nbclr = [0100100..........001.....0110011]\nbinv = [0110100..........001.....0110011]\nbext = [0100100..........101.....0110011]\n\nbseti = [0010100..........001.....0010011]\nbclri = [0100100..........001.....0010011]\nbinvi = [0110100..........001.....0010011]\nbexti = [0100100..........101.....0010011]\n\ngrev = [0110100..........101.....0110011]\n#grevi = [01101............101.....0010011]\ngrevi0 = [011010000000.....101.....0010011]\ngrevi1 = [011010000001.....101.....0010011]\ngrevi2 = [011010000010.....101.....0010011]\ngrevi3 = [011010000011.....101.....0010011]\ngrevi4 = [011010000100.....101.....0010011]\ngrevi5 = [011010000101.....101.....0010011]\ngrevi6 = [011010000110.....101.....0010011]\ngrevi7 = [011010000111.....101.....0010011]\ngrevi8 = [011010001000.....101.....0010011]\ngrevi9 = [011010001001.....101.....0010011]\ngrevi10 = [011010001010.....101.....0010011]\ngrevi11 = [011010001011.....101.....0010011]\ngrevi12 = [011010001100.....101.....0010011]\ngrevi13 = [011010001101.....101.....0010011]\ngrevi14 = [011010001110.....101.....0010011]\ngrevi15 = [011010001111.....101.....0010011]\ngrevi16 = [011010010000.....101.....0010011]\ngrevi17 = [011010010001.....101.....0010011]\ngrevi18 = [011010010010.....101.....0010011]\ngrevi19 = [011010010011.....101.....0010011]\ngrevi20 = [011010010100.....101.....0010011]\ngrevi21 = [011010010101.....101.....0010011]\ngrevi22 = [011010010110.....101.....0010011]\ngrevi23 = [011010010111.....101.....0010011]\n#grevi24 = [011010011000.....101.....0010011] # REV8\nrev8 = [011010011000.....101.....0010011]\ngrevi25 = [011010011001.....101.....0010011]\ngrevi26 = [011010011010.....101.....0010011]\ngrevi27 = [011010011011.....101.....0010011]\ngrevi28 = [011010011100.....101.....0010011]\ngrevi29 = [011010011101.....101.....0010011]\ngrevi30 = [011010011110.....101.....0010011]\ngrevi31 = [011010011111.....101.....0010011]\n\ngorc = [0010100..........101.....0110011]\n#gorci = [00101............101.....0010011]\ngorci0 = [001010000000.....101.....0010011]\ngorci1 = [001010000001.....101.....0010011]\ngorci2 = [001010000010.....101.....0010011]\ngorci3 = [001010000011.....101.....0010011]\ngorci4 = [001010000100.....101.....0010011]\ngorci5 = [001010000101.....101.....0010011]\ngorci6 = [001010000110.....101.....0010011]\n#gorci7 = [001010000111.....101.....0010011] # ORC_B\norc_b = [001010000111.....101.....0010011]\ngorci8 = [001010001000.....101.....0010011]\ngorci9 = [001010001001.....101.....0010011]\ngorci10 = [001010001010.....101.....0010011]\ngorci11 = [001010001011.....101.....0010011]\ngorci12 = [001010001100.....101.....0010011]\ngorci13 = [001010001101.....101.....0010011]\ngorci14 = [001010001110.....101.....0010011]\ngorci15 = [001010001111.....101.....0010011]\ngorci16 = [001010010000.....101.....0010011]\ngorci17 = [001010010001.....101.....0010011]\ngorci18 = [001010010010.....101.....0010011]\ngorci19 = [001010010011.....101.....0010011]\ngorci20 = [001010010100.....101.....0010011]\ngorci21 = [001010010101.....101.....0010011]\ngorci22 = [001010010110.....101.....0010011]\ngorci23 = [001010010111.....101.....0010011]\ngorci24 = [001010011000.....101.....0010011]\ngorci25 = [001010011001.....101.....0010011]\ngorci26 = [001010011010.....101.....0010011]\ngorci27 = [001010011011.....101.....0010011]\ngorci28 = [001010011100.....101.....0010011]\ngorci29 = [001010011101.....101.....0010011]\ngorci30 = [001010011110.....101.....0010011]\ngorci31 = [001010011111.....101.....0010011]\n\n\nshfl = [0000100..........001.....0110011]\nshfli = [00001000.........001.....0010011]\n\nunshfl = [0000100..........101.....0110011]\nunshfli = [00001000.........101.....0010011]\n\nbdecompress = [0100100..........110.....0110011]\nbcompress = [0000100..........110.....0110011]\n\nclmul = [0000101..........001.....0110011]\nclmulr = [0000101..........010.....0110011]\nclmulh = [0000101..........011.....0110011]\n\ncrc32_b = [011000010000.....001.....0010011]\ncrc32_h = [011000010001.....001.....0010011]\ncrc32_w = [011000010010.....001.....0010011]\ncrc32c_b = [011000011000.....001.....0010011]\ncrc32c_h = [011000011001.....001.....0010011]\ncrc32c_w = [011000011010.....001.....0010011]\n\nbfp = [0100100..........111.....0110011]\n\nxperm_n = [0010100..........010.....0110011]\nxperm_b = [0010100..........100.....0110011]\nxperm_h = [0010100..........110.....0110011]\n\n\n\n\n\n\nadd = [0000000..........000.....0110011]\naddi = [.................000.....0010011]\n\nsub = [0100000..........000.....0110011]\n\nand = [0000000..........111.....0110011]\nandi = [.................111.....0010011]\n\nor = [0000000..........110.....0110011]\nori = [.................110.....0010011]\n\nxor = [0000000..........100.....0110011]\nxori = [.................100.....0010011]\n\nsll = [0000000..........001.....0110011]\nslli = [0000000..........001.....0010011]\n\nsra = [0100000..........101.....0110011]\nsrai = [0100000..........101.....0010011]\n\nsrl = [0000000..........101.....0110011]\nsrli = [0000000..........101.....0010011]\n\nlui = [.........................0110111]\nauipc = [.........................0010111]\n\nslt = [0000000..........010.....0110011]\nsltu = [0000000..........011.....0110011]\nslti = [.................010.....0010011]\nsltiu = [.................011.....0010011]\n\nbeq = [.................000.....1100011]\nbne = [.................001.....1100011]\nbge = [.................101.....1100011]\nblt = [.................100.....1100011]\nbgeu = [.................111.....1100011]\nbltu = [.................110.....1100011]\n\njal = [.........................1101111]\njalr = [.................000.....1100111]\n\nlb = [.................000.....0000011]\nlh = [.................001.....0000011]\nlw = [.................010.....0000011]\n\nsb = [.................000.....0100011]\nsh = [.................001.....0100011]\nsw = [.................010.....0100011]\n\nlbu = [.................100.....0000011]\nlhu = [.................101.....0000011]\n\nfence = [.000.............000.....0001111]\nfence.i = [.................001.....0001111]\n\nebreak = [00000000000100000000000001110011]\necall = [00000000000000000000000001110011]\n\nmret = [00110000001000000000000001110011]\n\nwfi = [00010000010100000000000001110011]\n\ncsrrc_ro = [............00000011.....1110011]\ncsrrc_rw0 = [............1....011.....1110011]\ncsrrc_rw1 = [.............1...011.....1110011]\ncsrrc_rw2 = [..............1..011.....1110011]\ncsrrc_rw3 = [...............1.011.....1110011]\ncsrrc_rw4 = [................1011.....1110011]\n\ncsrrci_ro = [............00000111.....1110011]\ncsrrci_rw0 = [............1....111.....1110011]\ncsrrci_rw1 = [.............1...111.....1110011]\ncsrrci_rw2 = [..............1..111.....1110011]\ncsrrci_rw3 = [...............1.111.....1110011]\ncsrrci_rw4 = [................1111.....1110011]\n\ncsrrs_ro = [............00000010.....1110011]\ncsrrs_rw0 = [............1....010.....1110011]\ncsrrs_rw1 = [.............1...010.....1110011]\ncsrrs_rw2 = [..............1..010.....1110011]\ncsrrs_rw3 = [...............1.010.....1110011]\ncsrrs_rw4 = [................1010.....1110011]\n\ncsrrsi_ro = [............00000110.....1110011]\ncsrrsi_rw0 = [............1....110.....1110011]\ncsrrsi_rw1 = [.............1...110.....1110011]\ncsrrsi_rw2 = [..............1..110.....1110011]\ncsrrsi_rw3 = [...............1.110.....1110011]\ncsrrsi_rw4 = [................1110.....1110011]\n\n\ncsrw = [.................001000001110011]\ncsrrw0 = [.................001....11110011]\ncsrrw1 = [.................001...1.1110011]\ncsrrw2 = [.................001..1..1110011]\ncsrrw3 = [.................001.1...1110011]\ncsrrw4 = [.................0011....1110011]\n\ncsrwi = [.................101000001110011]\ncsrrwi0 = [.................101....11110011]\ncsrrwi1 = [.................101...1.1110011]\ncsrrwi2 = [.................101..1..1110011]\ncsrrwi3 = [.................101.1...1110011]\ncsrrwi4 = [.................1011....1110011]\n\nmul = [0000001..........000.....0110011]\nmulh = [0000001..........001.....0110011]\nmulhsu = [0000001..........010.....0110011]\nmulhu = [0000001..........011.....0110011]\n\ndiv = [0000001..........100.....0110011]\ndivu = [0000001..........101.....0110011]\nrem = [0000001..........110.....0110011]\nremu = [0000001..........111.....0110011]\n\n\n.input\n\nrv32i = {\n i[31]\n i[30]\n i[29]\n i[28]\n i[27]\n i[26]\n i[25]\n i[24]\n i[23]\n i[22]\n i[21]\n i[20]\n i[19]\n i[18]\n i[17]\n i[16]\n i[15]\n i[14]\n i[13]\n i[12]\n i[11]\n i[10]\n i[9]\n i[8]\n i[7]\n i[6]\n i[5]\n i[4]\n i[3]\n i[2]\n i[1]\n i[0]\n}\n\n\n.output\n\nrv32i = {\n alu\n rs1\n rs2\n imm12\n rd\n shimm5\n imm20\n pc\n load\n store\n lsu\n add\n sub\n land\n lor\n lxor\n sll\n sra\n srl\n slt\n unsign\n condbr\n beq\n bne\n bge\n blt\n jal\n by\n half\n word\n csr_read\n csr_clr\n csr_set\n csr_write\n csr_imm\n presync\n postsync\n ebreak\n ecall\n mret\n mul\n rs1_sign\n rs2_sign\n low\n div\n rem\n fence\n fence_i\n clz\n ctz\n cpop\n sext_b\n sext_h\n min\n max\n pack\n packu\n packh\n rol\n ror\n zbb\n bset\n bclr\n binv\n bext\n zbs\n bcompress\n bdecompress\n zbe\n clmul\n clmulh\n clmulr\n zbc\n grev\n gorc\n shfl\n unshfl\n xperm_n\n xperm_b\n xperm_h\n zbp\n crc32_b\n crc32_h\n crc32_w\n crc32c_b\n crc32c_h\n crc32c_w\n zbr\n bfp\n zbf\n sh1add\n sh2add\n sh3add\n zba\n pm_alu\n}\n\n.decode\n\nrv32i[clz] = { alu zbb rs1 rd clz }\nrv32i[ctz] = { alu zbb rs1 rd ctz }\nrv32i[cpop] = { alu zbb rs1 rd cpop }\nrv32i[sext_b] = { alu zbb rs1 rd sext_b}\nrv32i[sext_h] = { alu zbb rs1 rd sext_h}\nrv32i[min] = { alu zbb rs1 rs2 rd sub min }\nrv32i[max] = { alu zbb rs1 rs2 rd sub max }\nrv32i[minu] = { alu zbb rs1 rs2 rd unsign sub min }\nrv32i[maxu] = { alu zbb rs1 rs2 rd unsign sub max }\nrv32i[andn] = { alu zbb zbp rs1 rs2 rd land }\nrv32i[orn] = { alu zbb zbp rs1 rs2 rd lor }\nrv32i[xnor] = { alu zbb zbp rs1 rs2 rd lxor }\nrv32i[packu] = { alu zbp rs1 rs2 rd packu }\nrv32i[packh] = { alu zbp rs1 rs2 rd packh zbe zbf}\nrv32i[rol] = { alu zbb zbp rs1 rs2 rd rol }\nrv32i[ror] = { alu zbb zbp rs1 rs2 rd ror }\nrv32i[rori] = { alu zbb zbp rs1 rd shimm5 ror }\nrv32i[bset] = { alu zbs rs1 rs2 rd bset }\nrv32i[bclr] = { alu zbs rs1 rs2 rd bclr }\nrv32i[binv] = { alu zbs rs1 rs2 rd binv }\nrv32i[bext] = { alu zbs rs1 rs2 rd bext }\nrv32i[bseti] = { alu zbs rs1 rd shimm5 bset }\nrv32i[bclri] = { alu zbs rs1 rd shimm5 bclr }\nrv32i[binvi] = { alu zbs rs1 rd shimm5 binv }\nrv32i[bexti] = { alu zbs rs1 rd shimm5 bext }\nrv32i[sh1add] = { alu zba rs1 rs2 rd sh1add}\nrv32i[sh2add] = { alu zba rs1 rs2 rd sh2add}\nrv32i[sh3add] = { alu zba rs1 rs2 rd sh3add}\n\n#v32i[pack] = { alu zbp rs1 rs2 rd pack zbe zbf}\nrv32i[zext_h] = { alu zbb zbp rs1 rs2 rd pack zbe zbf} # pack with rs2=x0\nrv32i[pack{1-31}]= { alu zbp rs1 rs2 rd pack zbe zbf}\n\nrv32i[mul] = { mul rs1 rs2 rd low }\nrv32i[mulh] = { mul rs1 rs2 rd rs1_sign rs2_sign }\nrv32i[mulhu] = { mul rs1 rs2 rd }\nrv32i[mulhsu] = { mul rs1 rs2 rd rs1_sign }\nrv32i[bcompress] = { mul zbe rs1 rs2 rd bcompress }\nrv32i[bdecompress] = { mul zbe rs1 rs2 rd bdecompress }\nrv32i[clmul] = { mul zbc rs1 rs2 rd clmul }\nrv32i[clmulh] = { mul zbc rs1 rs2 rd clmulh}\nrv32i[clmulr] = { mul zbc rs1 rs2 rd clmulr}\n\nrv32i[crc32_b] = { mul zbr rs1 rd crc32_b}\nrv32i[crc32_h] = { mul zbr rs1 rd crc32_h}\nrv32i[crc32_w] = { mul zbr rs1 rd crc32_w}\nrv32i[crc32c_b] = { mul zbr rs1 rd crc32c_b}\nrv32i[crc32c_h] = { mul zbr rs1 rd crc32c_h}\nrv32i[crc32c_w] = { mul zbr rs1 rd crc32c_w}\n\nrv32i[bfp] = { mul zbf rs1 rs2 rd bfp }\n\nrv32i[grev] = { mul zbp rs1 rs2 rd grev }\n\nrv32i[grevi{0-23}] = { mul zbp rs1 rd shimm5 grev }\nrv32i[grevi{25-31}] = { mul zbp rs1 rd shimm5 grev }\n\nrv32i[rev8] = { alu zbb zbp rs1 rd shimm5 grev } # grevi24\n\nrv32i[gorc] = { mul zbp rs1 rs2 rd gorc }\n\nrv32i[gorci{0-6}] = { mul zbp rs1 rd shimm5 gorc }\nrv32i[gorci{8-31}] = { mul zbp rs1 rd shimm5 gorc }\n\nrv32i[orc_b] = { alu zbb zbp rs1 rd shimm5 gorc } # gorci7\n\n\nrv32i[shfl] = { mul zbp rs1 rs2 rd shfl }\nrv32i[shfli] = { mul zbp rs1 rd shimm5 shfl }\n\nrv32i[unshfl] = { mul zbp rs1 rs2 rd unshfl}\nrv32i[unshfli] = { mul zbp rs1 rd shimm5 unshfl}\n\nrv32i[xperm_n] = { mul zbp rs1 rs2 rd xperm_n}\nrv32i[xperm_b] = { mul zbp rs1 rs2 rd xperm_b}\nrv32i[xperm_h] = { mul zbp rs1 rs2 rd xperm_h}\n\n\n\nrv32i[div] = { div rs1 rs2 rd }\nrv32i[divu] = { div rs1 rs2 rd unsign }\nrv32i[rem] = { div rs1 rs2 rd rem}\nrv32i[remu] = { div rs1 rs2 rd unsign rem}\n\nrv32i[add] = { alu rs1 rs2 rd add pm_alu }\nrv32i[addi] = { alu rs1 imm12 rd add pm_alu }\n\nrv32i[sub] = { alu rs1 rs2 rd sub pm_alu }\n\nrv32i[and] = { alu rs1 rs2 rd land pm_alu }\nrv32i[andi] = { alu rs1 imm12 rd land pm_alu }\n\nrv32i[or] = { alu rs1 rs2 rd lor pm_alu }\nrv32i[ori] = { alu rs1 imm12 rd lor pm_alu }\n\nrv32i[xor] = { alu rs1 rs2 rd lxor pm_alu }\nrv32i[xori] = { alu rs1 imm12 rd lxor pm_alu }\n\nrv32i[sll] = { alu rs1 rs2 rd sll pm_alu }\nrv32i[slli] = { alu rs1 shimm5 rd sll pm_alu }\n\nrv32i[sra] = { alu rs1 rs2 rd sra pm_alu }\nrv32i[srai] = { alu rs1 shimm5 rd sra pm_alu }\n\nrv32i[srl] = { alu rs1 rs2 rd srl pm_alu }\nrv32i[srli] = { alu rs1 shimm5 rd srl pm_alu }\n\nrv32i[lui] = { alu imm20 rd lor pm_alu }\nrv32i[auipc] = { alu imm20 pc rd add pm_alu }\n\n\nrv32i[slt] = { alu rs1 rs2 rd sub slt pm_alu }\nrv32i[sltu] = { alu rs1 rs2 rd sub slt unsign pm_alu }\nrv32i[slti] = { alu rs1 imm12 rd sub slt pm_alu }\nrv32i[sltiu] = { alu rs1 imm12 rd sub slt unsign pm_alu }\n\nrv32i[beq] = { alu rs1 rs2 sub condbr beq }\nrv32i[bne] = { alu rs1 rs2 sub condbr bne }\nrv32i[bge] = { alu rs1 rs2 sub condbr bge }\nrv32i[blt] = { alu rs1 rs2 sub condbr blt }\nrv32i[bgeu] = { alu rs1 rs2 sub condbr bge unsign }\nrv32i[bltu] = { alu rs1 rs2 sub condbr blt unsign }\n\nrv32i[jal] = { alu imm20 rd pc jal }\nrv32i[jalr] = { alu rs1 rd imm12 jal }\n\n\n\nrv32i[lb] = { lsu load rs1 rd by }\nrv32i[lh] = { lsu load rs1 rd half }\nrv32i[lw] = { lsu load rs1 rd word }\nrv32i[lbu] = { lsu load rs1 rd by unsign }\nrv32i[lhu] = { lsu load rs1 rd half unsign }\n\nrv32i[sb] = { lsu store rs1 rs2 by }\nrv32i[sh] = { lsu store rs1 rs2 half }\nrv32i[sw] = { lsu store rs1 rs2 word }\n\n\nrv32i[fence] = { alu lor fence presync}\n\n# fence.i has fence effect in addtion to flush I$ and redirect\nrv32i[fence.i] = { alu lor fence fence_i presync postsync}\n\n# nops for now\n\nrv32i[ebreak] = { alu rs1 imm12 rd lor ebreak postsync}\nrv32i[ecall] = { alu rs1 imm12 rd lor ecall postsync}\nrv32i[mret] = { alu rs1 imm12 rd lor mret postsync}\n\nrv32i[wfi] = { alu rs1 imm12 rd lor pm_alu }\n\n# csr means read\n\n# csr_read - put csr on rs2 and rs1 0's\nrv32i[csrrc_ro] = { alu rd csr_read }\n\n# put csr on rs2 and make rs1 0's into alu. Save rs1 for csr_clr later\nrv32i[csrrc_rw{0-4}] = { alu rd csr_read rs1 csr_clr presync postsync }\n\nrv32i[csrrci_ro] = { alu rd csr_read }\n\nrv32i[csrrci_rw{0-4}] = { alu rd csr_read rs1 csr_clr csr_imm presync postsync }\n\nrv32i[csrrs_ro] = { alu rd csr_read }\n\nrv32i[csrrs_rw{0-4}] = { alu rd csr_read rs1 csr_set presync postsync }\n\nrv32i[csrrsi_ro] = { alu rd csr_read }\n\nrv32i[csrrsi_rw{0-4}] = { alu rd csr_read rs1 csr_set csr_imm presync postsync }\n\nrv32i[csrrw{0-4}] = { alu rd csr_read rs1 csr_write presync postsync }\n\n\nrv32i[csrrwi{0-4}] = { alu rd csr_read rs1 csr_write csr_imm presync postsync }\n\n# optimize csr write only - pipelined\nrv32i[csrw] = { alu rd rs1 csr_write }\n\nrv32i[csrwi] = { alu rd csr_write csr_imm }\n\n\n.end\n\n" }, { "path": "design/dec/el2_dec.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n// dec: decode unit - decode, bypassing, ARF, interrupts\n//\n//********************************************************************************\n// $Id$\n//\n//\n// Function: Decode\n// Comments: Decode, dependency scoreboard, ARF\n//\n//\n// A -> D -> EX1 ... WB\n//\n//********************************************************************************\n\nmodule el2_dec\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic free_clk, // Clock always. Through two clock headers. For flops without second clock header built in.\n input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.\n\n input logic lsu_fastint_stall_any, // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle\n\n output logic dec_extint_stall, // Stall on external interrupt\n\n output logic dec_i0_decode_d, // Valid instruction at D-stage and not blocked\n output logic dec_pause_state_cg, // to top for active state clock gating\n\n output logic dec_tlu_core_empty,\n\n input logic rst_l, // reset, active low\n // rst_vec is supposed to be connected to a constant in the top level\n /*pragma coverage off*/\n input logic [31:1] rst_vec, // reset vector, from core pins\n /*pragma coverage on*/\n\n input logic nmi_int, // NMI pin\n // nmi_vec is supposed to be connected to a constant in the top level\n /*pragma coverage off*/\n input logic [31:1] nmi_vec, // NMI vector, from pins\n /*pragma coverage on*/\n\n input logic i_cpu_halt_req, // Asynchronous Halt request to CPU\n input logic i_cpu_run_req, // Asynchronous Restart request to CPU\n\n output logic o_cpu_halt_status, // Halt status of core (pmu/fw)\n output logic o_cpu_halt_ack, // Halt request ack\n output logic o_cpu_run_ack, // Run request ack\n output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request\n\n /*pragma coverage off*/\n input logic [31:4] core_id, // CORE ID\n /*pragma coverage on*/\n\n // external MPC halt/run interface\n input logic mpc_debug_halt_req, // Async halt request\n input logic mpc_debug_run_req, // Async run request\n input logic mpc_reset_run_req, // Run/halt after reset\n output logic mpc_debug_halt_ack, // Halt ack\n output logic mpc_debug_run_ack, // Run ack\n output logic debug_brkpt_status, // debug breakpoint\n\n input logic exu_pmu_i0_br_misp, // slot 0 branch misp\n input logic exu_pmu_i0_br_ataken, // slot 0 branch actual taken\n input logic exu_pmu_i0_pc4, // slot 0 4 byte branch\n\n\n input logic lsu_nonblock_load_valid_m, // valid nonblock load at m\n input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag\n input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r\n input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag\n input logic lsu_nonblock_load_data_valid, // valid nonblock load data back\n input logic lsu_nonblock_load_data_error, // nonblock load bus error\n input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag\n input logic [31:0] lsu_nonblock_load_data, // nonblock load data\n\n input logic lsu_pmu_bus_trxn, // D side bus transaction\n input logic lsu_pmu_bus_misaligned, // D side bus misaligned\n input logic lsu_pmu_bus_error, // D side bus error\n input logic lsu_pmu_bus_busy, // D side bus busy\n input logic lsu_pmu_misaligned_m, // D side load or store misaligned\n input logic lsu_pmu_load_external_m, // D side bus load\n input logic lsu_pmu_store_external_m, // D side bus store\n input logic dma_pmu_dccm_read, // DMA DCCM read\n input logic dma_pmu_dccm_write, // DMA DCCM write\n input logic dma_pmu_any_read, // DMA read\n input logic dma_pmu_any_write, // DMA write\n\n input logic [31:1] lsu_fir_addr, // Fast int address\n input logic [ 1:0] lsu_fir_error, // Fast int lookup error\n\n input logic ifu_pmu_instr_aligned, // aligned instructions\n input logic ifu_pmu_fetch_stall, // fetch unit stalled\n input logic ifu_pmu_ic_miss, // icache miss\n input logic ifu_pmu_ic_hit, // icache hit\n input logic ifu_pmu_bus_error, // Instruction side bus error\n input logic ifu_pmu_bus_busy, // Instruction side bus busy\n input logic ifu_pmu_bus_trxn, // Instruction side bus transaction\n\n input logic ifu_ic_error_start, // IC single bit error\n input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error\n\n input logic [ 3:0] lsu_trigger_match_m,\n input logic dbg_cmd_valid, // debugger abstract command valid\n input logic dbg_cmd_write, // command is a write\n input logic [ 1:0] dbg_cmd_type, // command type\n input logic [31:0] dbg_cmd_addr, // command address\n input logic [ 1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i\n\n\n input logic ifu_i0_icaf, // icache access fault\n input logic [1:0] ifu_i0_icaf_type, // icache access fault type\n\n input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst\n input logic ifu_i0_dbecc, // icache/iccm double-bit error\n\n input logic lsu_idle_any, // lsu idle for halting\n\n input el2_br_pkt_t i0_brp, // branch packet\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index\n input logic [ pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR\n input logic [ pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag\n input logic [ $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index\n\n input el2_lsu_error_pkt_t lsu_error_pkt_r, // LSU exception/error packet\n input logic lsu_single_ecc_error_incr, // LSU inc SB error counter\n\n input logic lsu_imprecise_error_load_any, // LSU imprecise load bus error\n input logic lsu_imprecise_error_store_any, // LSU imprecise store bus error\n input logic [31:0] lsu_imprecise_error_addr_any, // LSU imprecise bus error address\n\n input logic [31:0] exu_div_result, // final div result\n input logic exu_div_wren, // Divide write enable to GPR\n\n input logic [31:0] exu_csr_rs1_x, // rs1 for csr instruction\n\n input logic [31:0] lsu_result_m, // load result\n input logic [31:0] lsu_result_corr_r, // load result - corrected load data\n\n input logic lsu_load_stall_any, // This is for blocking loads\n input logic lsu_store_stall_any, // This is for blocking stores\n input logic dma_dccm_stall_any, // stall any load/store at decode, pmu event\n input logic dma_iccm_stall_any, // iccm stalled, pmu event\n\n input logic iccm_dma_sb_error, // ICCM DMA single bit error\n\n input logic exu_flush_final, // slot0 flush\n\n input logic [31:1] exu_npc_r, // next PC\n\n input logic [31:0] exu_i0_result_x, // alu result x\n\n\n input logic ifu_i0_valid, // fetch valids to instruction buffer\n input logic [31:0] ifu_i0_instr, // fetch inst's to instruction buffer\n input logic [31:1] ifu_i0_pc, // pc's for instruction buffer\n input logic ifu_i0_pc4, // indication of 4B or 2B for corresponding inst\n input logic [31:1] exu_i0_pc_x, // pc's for e1 from the alu's\n\n input logic mexintpend, // External interrupt pending\n input logic timer_int, // Timer interrupt pending (from pin)\n input logic soft_int, // Software interrupt pending (from pin)\n\n input logic [7:0] pic_claimid, // PIC claimid\n input logic [3:0] pic_pl, // PIC priv level\n input logic mhwakeup, // High priority wakeup\n\n output logic [3:0] dec_tlu_meicurpl, // to PIC, Current priv level\n output logic [3:0] dec_tlu_meipt, // to PIC\n\n input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data\n input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid\n output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics\n\n\n // Debug start\n input logic dbg_halt_req, // DM requests a halt\n input logic dbg_resume_req, // DM requests a resume\n input logic ifu_miss_state_idle, // I-side miss buffer empty\n\n output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command\n output logic dec_tlu_debug_mode, // Core is in debug mode\n output logic dec_tlu_resume_ack, // Resume acknowledge\n output logic dec_tlu_flush_noredir_r, // Tell fetch to idle on this flush\n output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC\n output logic dec_tlu_flush_leak_one_r, // single step\n output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc\n output logic [31:2] dec_tlu_meihap, // Fast ext int base\n\n output logic dec_debug_wdata_rs1_d, // insert debug write data into rs1 at decode\n\n output logic [31:0] dec_dbg_rddata, // debug command read data\n\n output logic dec_dbg_cmd_done, // abstract command is done\n output logic dec_dbg_cmd_fail, // abstract command failed (illegal reg address)\n\n output el2_trigger_pkt_t [3:0] trigger_pkt_any, // info needed by debug trigger blocks\n\n output logic dec_tlu_force_halt, // halt has been forced\n // Debug end\n // branch info from pipe0 for errors or counter updates\n input logic [1:0] exu_i0_br_hist_r, // history\n input logic exu_i0_br_error_r, // error\n input logic exu_i0_br_start_error_r, // start error\n input logic exu_i0_br_valid_r, // valid\n input logic exu_i0_br_mp_r, // mispredict\n input logic exu_i0_br_middle_r, // middle of bank\n\n // branch info from pipe1 for errors or counter updates\n\n input logic exu_i0_br_way_r, // way hit or repl\n\n output logic dec_i0_rs1_en_d, // Qualify GPR RS1 data\n output logic dec_i0_rs2_en_d, // Qualify GPR RS2 data\n output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data\n output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data\n\n output logic [31:0] dec_i0_immed_d, // immediate data\n output logic [12:1] dec_i0_br_immed_d, // br immediate data\n\n output el2_alu_pkt_t i0_ap, // alu packet\n\n output logic dec_i0_alu_decode_d, // schedule on D-stage alu\n output logic dec_i0_branch_d, // Branch in D-stage\n\n output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's\n\n output logic [31:1] dec_i0_pc_d, // pc's at decode\n output logic [ 3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable\n output logic [ 3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable\n\n output logic [31:0] dec_i0_result_r, // Result R-stage\n\n output el2_lsu_pkt_t lsu_p, // lsu packet\n output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands\n output el2_mul_pkt_t mul_p, // mul packet\n output el2_div_pkt_t div_p, // div packet\n output logic dec_div_cancel, // cancel divide operation\n\n output logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses\n\n output logic dec_csr_ren_d, // CSR read enable\n output logic [31:0] dec_csr_rddata_d, // CSR read data\n\n output logic dec_tlu_flush_lower_r, // tlu flush due to late mp, exception, rfpc, or int\n output logic dec_tlu_flush_lower_wb,\n output logic [31:1] dec_tlu_flush_path_r, // tlu flush target\n output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state\n output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache\n\n output logic [31:1] pred_correct_npc_x, // npc if prediction is correct at e2 stage\n\n output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot 0 branch predictor update packet\n\n output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc\n output logic dec_tlu_perfcnt1, // toggles when slot0 perf counter 1 has an event inc\n output logic dec_tlu_perfcnt2, // toggles when slot0 perf counter 2 has an event inc\n output logic dec_tlu_perfcnt3, // toggles when slot0 perf counter 3 has an event inc\n\n output el2_predict_pkt_t dec_i0_predict_p_d, // prediction packet to alus\n output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index\n output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag\n\n output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index\n\n output logic dec_lsu_valid_raw_d,\n\n output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control\n\n output logic [1:0] dec_data_en, // clock-gate control logic\n output logic [1:0] dec_ctl_en,\n\n input logic [15:0] ifu_i0_cinst, // 16b compressed instruction\n\n output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet\n\n // PMP signals\n output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],\n output logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],\n\n`ifdef RV_USER_MODE\n\n // Privilege mode\n output logic priv_mode,\n output logic priv_mode_eff,\n output logic priv_mode_ns,\n\n // mseccfg CSR content for PMP\n output el2_mseccfg_pkt_t mseccfg,\n\n`endif\n\n // feature disable from mfdc\n output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding\n output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address\n output logic dec_tlu_core_ecc_disable, // disable core ECC\n output logic dec_tlu_bpred_disable, // disable branch prediction\n output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing\n output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16]\n\n // clock gating overrides from mcgc\n output logic dec_tlu_misc_clk_override, // override misc clock domain gating\n output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating\n output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating\n output logic dec_tlu_bus_clk_override, // override bus clock domain gating\n output logic dec_tlu_pic_clk_override, // override PIC clock domain gating\n output logic dec_tlu_picio_clk_override, // override PICIO clock domain gating\n output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating\n output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n el2_regfile_if.veer_rf_src regfile,\n`endif\n\n output logic dec_tlu_i0_commit_cmt, // committed i0 instruction\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // Flop scan mode control\n /*pragma coverage on*/\n\n);\n\n\n logic dec_tlu_dec_clk_override; // to and from dec blocks\n logic clk_override;\n\n logic dec_ib0_valid_d;\n\n logic dec_pmu_instr_decoded;\n logic dec_pmu_decode_stall;\n logic dec_pmu_presync_stall;\n logic dec_pmu_postsync_stall;\n\n logic dec_tlu_wr_pause_r; // CSR write to pause reg is at R.\n\n logic [4:0] dec_i0_rs1_d;\n logic [4:0] dec_i0_rs2_d;\n\n logic [31:0] dec_i0_instr_d;\n\n logic dec_tlu_trace_disable;\n logic dec_tlu_pipelining_disable;\n\n\n logic [4:0] dec_i0_waddr_r;\n logic dec_i0_wen_r;\n logic [31:0] dec_i0_wdata_r;\n logic dec_csr_wen_r; // csr write enable at wb\n logic [11:0] dec_csr_rdaddr_r; // read address for csrs\n logic [11:0] dec_csr_wraddr_r; // write address for csryes\n logic [31:0] dec_csr_wrdata_r; // csr write data at wb\n\n logic [11:0] dec_csr_rdaddr_d; // read address for csr\n logic dec_csr_legal_d; // csr indicates legal operation\n\n logic dec_csr_wen_unq_d; // valid csr with write - for csr legal\n logic dec_csr_any_unq_d; // valid csr - for csr legal\n logic dec_csr_stall_int_ff; // csr is mie/mstatus\n\n el2_trap_pkt_t dec_tlu_packet_r;\n\n logic dec_i0_pc4_d;\n logic dec_tlu_presync_d;\n logic dec_tlu_postsync_d;\n logic dec_tlu_debug_stall;\n\n logic [31:0] dec_illegal_inst;\n\n logic dec_i0_icaf_d;\n\n logic dec_i0_dbecc_d;\n logic dec_i0_icaf_second_d;\n logic [3:0] dec_i0_trigger_match_d;\n logic dec_debug_fence_d;\n logic dec_nonblock_load_wen;\n logic [4:0] dec_nonblock_load_waddr;\n logic dec_tlu_flush_pause_r;\n el2_br_pkt_t dec_i0_brp;\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;\n logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;\n logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag;\n logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index; // Fully associt btb index\n\n logic [31:1] dec_tlu_i0_pc_r;\n logic dec_tlu_i0_kill_writeb_wb;\n logic dec_tlu_i0_valid_r;\n\n logic dec_pause_state;\n\n logic [1:0] dec_i0_icaf_type_d; // i0 instruction access fault type\n\n logic dec_tlu_flush_extint; // Fast ext int started\n\n logic [31:0] dec_i0_inst_wb;\n logic [31:1] dec_i0_pc_wb;\n logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;\n logic [ 4:0] dec_tlu_exc_cause_wb1;\n logic [31:0] dec_tlu_mtval_wb1;\n logic dec_tlu_i0_exc_valid_wb1;\n\n logic [ 4:0] div_waddr_wb;\n logic dec_div_active;\n\n logic dec_debug_valid_d;\n\n assign clk_override = dec_tlu_dec_clk_override;\n\n\n assign dec_dbg_rddata[31:0] = dec_i0_wdata_r[31:0];\n\n\n el2_dec_ib_ctl #(.pt(pt)) instbuff (.*);\n\n\n el2_dec_decode_ctl #(.pt(pt)) decode (.*);\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n el2_regfile_if regfile_if ();\n assign regfile.gpr.ra = regfile_if.gpr.ra;\n assign regfile.gpr.sp = regfile_if.gpr.sp;\n assign regfile.gpr.fp = regfile_if.gpr.fp;\n assign regfile.gpr.a0 = regfile_if.gpr.a0;\n assign regfile.gpr.a1 = regfile_if.gpr.a1;\n assign regfile.gpr.a2 = regfile_if.gpr.a2;\n assign regfile.gpr.a3 = regfile_if.gpr.a3;\n assign regfile.gpr.a4 = regfile_if.gpr.a4;\n assign regfile.gpr.a5 = regfile_if.gpr.a5;\n assign regfile.gpr.a6 = regfile_if.gpr.a6;\n assign regfile.gpr.a7 = regfile_if.gpr.a7;\n\n assign regfile.tlu.pc = regfile_if.tlu.pc;\n assign regfile.tlu.npc = regfile_if.tlu.npc;\n assign regfile.tlu.mstatus = regfile_if.tlu.mstatus;\n assign regfile.tlu.mie = regfile_if.tlu.mie;\n assign regfile.tlu.mtvec = regfile_if.tlu.mtvec;\n assign regfile.tlu.mscratch = regfile_if.tlu.mscratch;\n assign regfile.tlu.mepc = regfile_if.tlu.mepc;\n assign regfile.tlu.mcause = regfile_if.tlu.mcause;\n assign regfile.tlu.mtval = regfile_if.tlu.mtval;\n assign regfile.tlu.mip = regfile_if.tlu.mip;\n assign regfile.tlu.mcyclel = regfile_if.tlu.mcyclel;\n assign regfile.tlu.mcycleh = regfile_if.tlu.mcycleh;\n assign regfile.tlu.minstretl = regfile_if.tlu.minstretl;\n assign regfile.tlu.minstreth = regfile_if.tlu.minstreth;\n assign regfile.tlu.mrac = regfile_if.tlu.mrac;\n`endif\n\n el2_dec_tlu_ctl #(.pt(pt)\n ) tlu (\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .regfile(regfile_if.veer_tlu_rf),\n`endif\n .*);\n\n\n el2_dec_gpr_ctl #(\n .pt(pt)\n ) arf (\n .*,\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .regfile(regfile_if.veer_gpr_rf),\n`endif\n // inputs\n .raddr0(dec_i0_rs1_d[4:0]),\n .raddr1(dec_i0_rs2_d[4:0]),\n\n .wen0(dec_i0_wen_r),\n .waddr0(dec_i0_waddr_r[4:0]),\n .wd0(dec_i0_wdata_r[31:0]),\n .wen1(dec_nonblock_load_wen),\n .waddr1(dec_nonblock_load_waddr[4:0]),\n .wd1(lsu_nonblock_load_data[31:0]),\n .wen2(exu_div_wren),\n .waddr2(div_waddr_wb),\n .wd2(exu_div_result[31:0]),\n\n // outputs\n .rd0(gpr_i0_rs1_d[31:0]),\n .rd1(gpr_i0_rs2_d[31:0])\n );\n\n\n // Trigger\n\n el2_dec_trigger #(.pt(pt)) dec_trigger (.*);\n\n\n\n\n // trace\n assign trace_rv_trace_pkt.trace_rv_i_insn_ip = dec_i0_inst_wb[31:0];\n assign trace_rv_trace_pkt.trace_rv_i_address_ip = {dec_i0_pc_wb[31:1], 1'b0};\n\n assign trace_rv_trace_pkt.trace_rv_i_valid_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1;\n assign trace_rv_trace_pkt.trace_rv_i_exception_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_exc_valid_wb1;\n assign trace_rv_trace_pkt.trace_rv_i_ecause_ip = dec_tlu_exc_cause_wb1[4:0]; // replicate across ports\n assign trace_rv_trace_pkt.trace_rv_i_interrupt_ip = dec_tlu_int_valid_wb1;\n assign trace_rv_trace_pkt.trace_rv_i_tval_ip = dec_tlu_mtval_wb1[31:0]; // replicate across ports\n\n\n\n // end trace\n\n\nendmodule // el2_dec\n\n" }, { "path": "design/dec/el2_dec_decode_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n\nmodule el2_dec_decode_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic dec_tlu_trace_disable,\n input logic dec_debug_valid_d,\n\n input logic dec_tlu_flush_extint, // Flush external interrupt\n\n input logic dec_tlu_force_halt, // invalidate nonblock load cam on a force halt event\n\n output logic dec_extint_stall, // Stall from external interrupt\n\n input logic [15:0] ifu_i0_cinst, // 16b compressed instruction\n output logic [31:0] dec_i0_inst_wb, // 32b instruction at wb+1 for trace encoder\n output logic [31:1] dec_i0_pc_wb, // 31b pc at wb+1 for trace encoder\n\n\n input logic lsu_nonblock_load_valid_m, // valid nonblock load at m\n input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag\n input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r\n input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag\n input logic lsu_nonblock_load_data_valid, // valid nonblock load data back\n input logic lsu_nonblock_load_data_error, // nonblock load bus error\n input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag\n\n\n input logic [3:0] dec_i0_trigger_match_d, // i0 decode trigger matches\n\n input logic dec_tlu_wr_pause_r, // pause instruction at r\n input logic dec_tlu_pipelining_disable, // pipeline disable - presync, i0 decode only\n\n input logic [3:0] lsu_trigger_match_m, // lsu trigger matches\n\n input logic lsu_pmu_misaligned_m, // perf mon: load/store misalign\n input logic dec_tlu_debug_stall, // debug stall decode\n input logic dec_tlu_flush_leak_one_r, // leak1 instruction\n\n input logic dec_debug_fence_d, // debug fence instruction\n\n input logic [1:0] dbg_cmd_wrdata, // disambiguate fence, fence_i\n\n input logic dec_i0_icaf_d, // icache access fault\n input logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst\n input logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type\n\n input logic dec_i0_dbecc_d, // icache/iccm double-bit error\n\n input el2_br_pkt_t dec_i0_brp, // branch packet\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index\n input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR\n input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag\n input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index\n\n input logic lsu_idle_any, // lsu idle: if fence instr & ~lsu_idle then stall decode\n\n input logic lsu_load_stall_any, // stall any load at decode\n input logic lsu_store_stall_any, // stall any store at decode\n input logic dma_dccm_stall_any, // stall any load/store at decode\n\n input logic exu_div_wren, // nonblocking divide write enable to GPR.\n\n input logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state\n input logic dec_tlu_flush_lower_wb, // trap lower flush\n input logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state\n input logic dec_tlu_flush_lower_r, // trap lower flush\n input logic dec_tlu_flush_pause_r, // don't clear pause state on initial lower flush\n input logic dec_tlu_presync_d, // CSR read needs to be presync'd\n input logic dec_tlu_postsync_d, // CSR ops that need to be postsync'd\n\n input logic dec_i0_pc4_d, // inst is 4B inst else 2B\n\n input logic [31:0] dec_csr_rddata_d, // csr read data at wb\n input logic dec_csr_legal_d, // csr indicates legal operation\n\n input logic [31:0] exu_csr_rs1_x, // rs1 for csr instr\n\n input logic [31:0] lsu_result_m, // load result\n input logic [31:0] lsu_result_corr_r, // load result - corrected data for writing gpr's, not for bypassing\n\n input logic exu_flush_final, // lower flush or i0 flush at X or D\n\n input logic [31:1] exu_i0_pc_x, // pcs at e1\n\n input logic [31:0] dec_i0_instr_d, // inst at decode\n\n input logic dec_ib0_valid_d, // inst valid at decode\n\n input logic [31:0] exu_i0_result_x, // from primary alu's\n\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.\n\n input logic clk_override, // Override non-functional clock gating\n input logic rst_l, // Flop reset\n\n\n\n output logic dec_i0_rs1_en_d, // rs1 enable at decode\n output logic dec_i0_rs2_en_d, // rs2 enable at decode\n\n output logic [4:0] dec_i0_rs1_d, // rs1 logical source\n output logic [4:0] dec_i0_rs2_d, // rs2 logical source\n\n output logic [31:0] dec_i0_immed_d, // 32b immediate data decode\n\n\n output logic [12:1] dec_i0_br_immed_d, // 12b branch immediate\n\n output el2_alu_pkt_t i0_ap, // alu packets\n\n output logic dec_i0_decode_d, // i0 decode\n\n output logic dec_i0_alu_decode_d, // decode to D-stage alu\n output logic dec_i0_branch_d, // Branch in D-stage\n\n output logic [4:0] dec_i0_waddr_r, // i0 logical source to write to gpr's\n output logic dec_i0_wen_r, // i0 write enable\n output logic [31:0] dec_i0_wdata_r, // i0 write data\n\n output logic dec_i0_select_pc_d, // i0 select pc for rs1 - branches\n\n output logic [3:0] dec_i0_rs1_bypass_en_d, // i0 rs1 bypass enable\n output logic [3:0] dec_i0_rs2_bypass_en_d, // i0 rs2 bypass enable\n output logic [31:0] dec_i0_result_r, // Result R-stage\n\n output el2_lsu_pkt_t lsu_p, // load/store packet\n output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands\n\n output el2_mul_pkt_t mul_p, // multiply packet\n\n output el2_div_pkt_t div_p, // divide packet\n output logic [4:0] div_waddr_wb, // DIV write address to GPR\n output logic dec_div_cancel, // cancel the divide operation\n\n output logic dec_lsu_valid_raw_d,\n output logic [11:0] dec_lsu_offset_d,\n\n output logic dec_csr_ren_d, // valid csr decode\n output logic dec_csr_wen_unq_d, // valid csr with write - for csr legal\n output logic dec_csr_any_unq_d, // valid csr - for csr legal\n output logic [11:0] dec_csr_rdaddr_d, // read address for csr\n output logic dec_csr_wen_r, // csr write enable at r\n output logic [11:0] dec_csr_rdaddr_r, // read address for csr\n output logic [11:0] dec_csr_wraddr_r, // write address for csr\n output logic [31:0] dec_csr_wrdata_r, // csr write data at r\n output logic dec_csr_stall_int_ff, // csr is mie/mstatus\n\n output dec_tlu_i0_valid_r, // i0 valid inst at c\n\n output el2_trap_pkt_t dec_tlu_packet_r, // trap packet\n\n output logic [31:1] dec_tlu_i0_pc_r, // i0 trap pc\n\n output logic [31:0] dec_illegal_inst, // illegal inst\n output logic [31:1] pred_correct_npc_x, // npc e2 if the prediction is correct\n\n output el2_predict_pkt_t dec_i0_predict_p_d, // i0 predict packet decode\n output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index\n output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag\n\n output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index\n\n output logic [1:0] dec_data_en, // clock-gating logic\n output logic [1:0] dec_ctl_en,\n\n output logic dec_pmu_instr_decoded, // number of instructions decode this cycle encoded\n output logic dec_pmu_decode_stall, // decode is stalled\n output logic dec_pmu_presync_stall, // decode has presync stall\n output logic dec_pmu_postsync_stall, // decode has postsync stall\n\n output logic dec_nonblock_load_wen, // write enable for nonblock load\n output logic [4:0] dec_nonblock_load_waddr, // logical write addr for nonblock load\n output logic dec_pause_state, // core in pause state\n output logic dec_pause_state_cg, // pause state for clock-gating\n\n output logic dec_div_active, // non-block divide is active\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n );\n\n\n\n\n el2_dec_pkt_t i0_dp_raw, i0_dp;\n\n logic [31:0] i0;\n logic i0_valid_d;\n\n logic [31:0] i0_result_r;\n\n logic [2:0] i0_rs1bypass, i0_rs2bypass;\n\n logic i0_jalimm20;\n logic i0_uiimm20;\n\n logic lsu_decode_d;\n logic [31:0] i0_immed_d;\n logic i0_presync;\n logic i0_postsync;\n\n logic postsync_stall;\n logic ps_stall;\n\n logic prior_inflight, prior_inflight_wb;\n\n logic csr_clr_d, csr_set_d, csr_write_d;\n\n logic csr_clr_x,csr_set_x,csr_write_x,csr_imm_x;\n logic [31:0] csr_mask_x;\n logic [31:0] write_csr_data_x;\n logic [31:0] write_csr_data_in;\n logic [31:0] write_csr_data;\n logic csr_data_wen;\n\n logic [4:0] csrimm_x;\n\n logic [31:0] csr_rddata_x;\n\n logic mul_decode_d;\n logic div_decode_d;\n logic div_e1_to_r;\n logic div_flush;\n logic div_active_in;\n logic div_active;\n logic i0_nonblock_div_stall;\n logic i0_div_prior_div_stall;\n logic nonblock_div_cancel;\n\n logic i0_legal;\n logic shift_illegal;\n logic illegal_inst_en;\n logic illegal_lockout_in, illegal_lockout;\n logic i0_legal_decode_d;\n logic i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;\n\n logic [12:1] last_br_immed_d;\n logic i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;\n logic i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;\n\n logic i0_div_decode_d;\n logic i0_load_block_d;\n logic [1:0] i0_rs1_depth_d, i0_rs2_depth_d;\n\n logic i0_load_stall_d;\n logic i0_store_stall_d;\n\n logic i0_predict_nt, i0_predict_t;\n\n logic i0_notbr_error, i0_br_toffset_error;\n logic i0_ret_error;\n logic i0_br_error;\n logic i0_br_error_all;\n logic [11:0] i0_br_offset;\n\n logic [20:1] i0_pcall_imm; // predicted jal's\n logic i0_pcall_12b_offset;\n logic i0_pcall_raw;\n logic i0_pcall_case;\n logic i0_pcall;\n\n logic i0_pja_raw;\n logic i0_pja_case;\n logic i0_pja;\n\n logic i0_pret_case;\n logic i0_pret_raw, i0_pret;\n\n logic i0_jal; // jal's that are not predicted\n\n\n logic i0_predict_br;\n\n logic store_data_bypass_d, store_data_bypass_m;\n\n el2_class_pkt_t i0_rs1_class_d, i0_rs2_class_d;\n\n el2_class_pkt_t i0_d_c, i0_x_c, i0_r_c;\n\n\n logic i0_ap_pc2, i0_ap_pc4;\n\n logic i0_rd_en_d;\n\n logic load_ldst_bypass_d;\n\n logic leak1_i0_stall_in, leak1_i0_stall;\n logic leak1_i1_stall_in, leak1_i1_stall;\n logic leak1_mode;\n\n logic i0_csr_write_only_d;\n\n logic prior_inflight_x, prior_inflight_eff;\n logic any_csr_d;\n\n logic prior_csr_write;\n\n logic [3:0] i0_pipe_en;\n logic i0_r_ctl_en, i0_x_ctl_en, i0_wb_ctl_en;\n logic i0_x_data_en, i0_r_data_en, i0_wb_data_en;\n\n logic debug_fence_i;\n logic debug_fence;\n\n logic i0_csr_write;\n logic presync_stall;\n\n logic i0_instr_error;\n logic i0_icaf_d;\n\n logic clear_pause;\n logic pause_state_in, pause_state;\n logic pause_stall;\n\n logic i0_brp_valid;\n logic nonblock_load_cancel;\n logic lsu_idle;\n logic lsu_pmu_misaligned_r;\n logic csr_ren_qual_d;\n logic csr_read_x;\n logic i0_block_d;\n logic i0_block_raw_d; // This is use to create the raw valid\n logic ps_stall_in;\n logic [31:0] i0_result_x;\n\n el2_dest_pkt_t d_d, x_d, r_d, wbd;\n el2_dest_pkt_t x_d_in, r_d_in;\n\n el2_trap_pkt_t d_t, x_t, x_t_in, r_t_in, r_t;\n\n logic [3:0] lsu_trigger_match_r;\n\n logic [31:1] dec_i0_pc_r;\n\n logic csr_read, csr_write;\n logic i0_br_unpred;\n\n logic nonblock_load_valid_m_delay;\n logic i0_wen_r;\n\n logic tlu_wr_pause_r1;\n logic tlu_wr_pause_r2;\n\n logic flush_final_r;\n\n logic bitmanip_zbb_legal;\n logic bitmanip_zbs_legal;\n logic bitmanip_zbe_legal;\n logic bitmanip_zbc_legal;\n logic bitmanip_zbp_legal;\n logic bitmanip_zbr_legal;\n logic bitmanip_zbf_legal;\n logic bitmanip_zba_legal;\n logic bitmanip_zbb_zbp_legal;\n logic bitmanip_zbp_zbe_zbf_legal;\n logic bitmanip_zbb_zbp_zbe_zbf_legal;\n logic bitmanip_legal;\n\n\n localparam NBLOAD_SIZE = pt.LSU_NUM_NBLOAD;\n localparam NBLOAD_SIZE_MSB = int'(pt.LSU_NUM_NBLOAD)-1;\n localparam NBLOAD_TAG_MSB = pt.LSU_NUM_NBLOAD_WIDTH-1;\n\n\n logic cam_write, cam_inv_reset, cam_data_reset;\n logic [NBLOAD_TAG_MSB:0] cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;\n logic [NBLOAD_SIZE_MSB:0] cam_wen;\n\n logic [NBLOAD_TAG_MSB:0] load_data_tag;\n logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;\n\n el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;\n el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;\n el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;\n\n logic [4:0] nonblock_load_rd;\n logic i0_nonblock_load_stall;\n logic i0_nonblock_boundary_stall;\n\n logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;\n\n logic i0_load_kill_wen_r;\n\n logic found;\n\n logic [NBLOAD_SIZE_MSB:0] cam_inv_reset_val, cam_data_reset_val;\n\n logic debug_fence_raw;\n\n logic [31:0] i0_result_r_raw;\n logic [31:0] i0_result_corr_r;\n\n logic [12:1] last_br_immed_x;\n\n logic [31:0] i0_inst_d;\n logic [31:0] i0_inst_x;\n logic [31:0] i0_inst_r;\n logic [31:0] i0_inst_wb_in;\n logic [31:0] i0_inst_wb;\n\n logic [31:1] i0_pc_wb;\n\n logic i0_wb_en;\n\n logic trace_enable;\n\n logic debug_valid_x;\n\n el2_inst_pkt_t i0_itype;\n el2_reg_pkt_t i0r;\n\n\n rvdffie #(8) misc1ff (.*,\n .clk(free_l2clk),\n .din( {leak1_i1_stall_in,leak1_i0_stall_in,dec_tlu_flush_extint,pause_state_in ,dec_tlu_wr_pause_r, tlu_wr_pause_r1,illegal_lockout_in,ps_stall_in}),\n .dout({leak1_i1_stall, leak1_i0_stall, dec_extint_stall, pause_state, tlu_wr_pause_r1,tlu_wr_pause_r2,illegal_lockout, ps_stall })\n );\n\n rvdffie #(8) misc2ff (.*,\n .clk(free_l2clk),\n .din( {lsu_trigger_match_m[3:0],lsu_pmu_misaligned_m,div_active_in,exu_flush_final, dec_debug_valid_d}),\n .dout({lsu_trigger_match_r[3:0],lsu_pmu_misaligned_r,div_active, flush_final_r, debug_valid_x})\n );\n\nif(pt.BTB_ENABLE==1) begin\n// branch prediction\n\n\n // in leak1_mode, ignore any predictions for i0, treat branch as if we haven't seen it before\n // in leak1 mode, also ignore branch errors for i0\n assign i0_brp_valid = dec_i0_brp.valid & ~leak1_mode & ~i0_icaf_d;\n\n assign dec_i0_predict_p_d.misp = '0;\n assign dec_i0_predict_p_d.ataken = '0;\n assign dec_i0_predict_p_d.boffset = '0;\n\n assign dec_i0_predict_p_d.pcall = i0_pcall; // don't mark as pcall if branch error\n assign dec_i0_predict_p_d.pja = i0_pja;\n assign dec_i0_predict_p_d.pret = i0_pret;\n assign dec_i0_predict_p_d.prett[31:1] = dec_i0_brp.prett[31:1];\n assign dec_i0_predict_p_d.pc4 = dec_i0_pc4_d;\n assign dec_i0_predict_p_d.hist[1:0] = dec_i0_brp.hist[1:0];\n assign dec_i0_predict_p_d.valid = i0_brp_valid & i0_legal_decode_d;\n assign i0_notbr_error = i0_brp_valid & ~(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw);\n\n // no toffset error for a pret\n assign i0_br_toffset_error = i0_brp_valid & dec_i0_brp.hist[1] & (dec_i0_brp.toffset[11:0] != i0_br_offset[11:0]) & ~i0_pret_raw;\n assign i0_ret_error = i0_brp_valid & (dec_i0_brp.ret ^ i0_pret_raw);\n assign i0_br_error = dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error;\n assign dec_i0_predict_p_d.br_error = i0_br_error & i0_legal_decode_d & ~leak1_mode;\n assign dec_i0_predict_p_d.br_start_error = dec_i0_brp.br_start_error & i0_legal_decode_d & ~leak1_mode;\n assign i0_predict_index_d[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = dec_i0_bp_index;\n\n assign i0_predict_btag_d[pt.BTB_BTAG_SIZE-1:0] = dec_i0_bp_btag[pt.BTB_BTAG_SIZE-1:0];\n assign i0_br_error_all = (i0_br_error | dec_i0_brp.br_start_error) & ~leak1_mode;\n assign dec_i0_predict_p_d.toffset[11:0] = i0_br_offset[11:0];\n assign i0_predict_fghr_d[pt.BHT_GHR_SIZE-1:0] = dec_i0_bp_fghr[pt.BHT_GHR_SIZE-1:0];\n assign dec_i0_predict_p_d.way = dec_i0_brp.way;\n\n\n if(pt.BTB_FULLYA) begin : genblock\n logic btb_error_found, btb_error_found_f;\n logic [$clog2(pt.BTB_SIZE)-1:0] fa_error_index_ns;\n\n assign btb_error_found = (i0_br_error_all | btb_error_found_f) & ~dec_tlu_flush_lower_r;\n assign fa_error_index_ns = (i0_br_error_all & ~btb_error_found_f) ? dec_i0_bp_fa_index : dec_fa_error_index;\n\n rvdff #($clog2(pt.BTB_SIZE)+1) btberrorfa_f (.*, .clk(active_clk),\n .din({btb_error_found, fa_error_index_ns}),\n .dout({btb_error_found_f, dec_fa_error_index}));\n\n\n end\n else\n assign dec_fa_error_index = 'b0;\n\n\n // end\nend // if (pt.BTB_ENABLE==1)\nelse begin\n\n always_comb begin\n dec_i0_predict_p_d = '0;\n dec_i0_predict_p_d.pcall = i0_pcall; // don't mark as pcall if branch error\n dec_i0_predict_p_d.pja = i0_pja;\n dec_i0_predict_p_d.pret = i0_pret;\n dec_i0_predict_p_d.pc4 = dec_i0_pc4_d;\n end\n\n assign i0_br_error_all = '0;\n assign i0_predict_index_d = '0;\n assign i0_predict_btag_d = '0;\n assign i0_predict_fghr_d = '0;\n assign i0_brp_valid = '0;\nend // else: !if(pt.BTB_ENABLE==1)\n\n // on br error turn anything into a nop\n // on i0 instruction fetch access fault turn anything into a nop\n // nop => alu rs1 imm12 rd lor\n\n assign i0_icaf_d = dec_i0_icaf_d | dec_i0_dbecc_d;\n\n assign i0_instr_error = i0_icaf_d;\n\n always_comb begin\n i0_dp = i0_dp_raw;\n if (i0_br_error_all | i0_instr_error) begin\n i0_dp = '0;\n i0_dp.alu = 1'b1;\n i0_dp.rs1 = 1'b1;\n i0_dp.rs2 = 1'b1;\n i0_dp.lor = 1'b1;\n i0_dp.legal = 1'b1;\n i0_dp.postsync = 1'b1;\n end\n end\n\n assign i0[31:0] = dec_i0_instr_d[31:0];\n\n assign dec_i0_select_pc_d = i0_dp.pc;\n\n // branches that can be predicted\n\n assign i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;\n\n assign i0_predict_nt = ~(dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br;\n assign i0_predict_t = (dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br;\n\n assign i0_ap.add = i0_dp.add;\n assign i0_ap.sub = i0_dp.sub;\n assign i0_ap.land = i0_dp.land;\n assign i0_ap.lor = i0_dp.lor;\n assign i0_ap.lxor = i0_dp.lxor;\n assign i0_ap.sll = i0_dp.sll;\n assign i0_ap.srl = i0_dp.srl;\n assign i0_ap.sra = i0_dp.sra;\n assign i0_ap.slt = i0_dp.slt;\n assign i0_ap.unsign = i0_dp.unsign;\n assign i0_ap.beq = i0_dp.beq;\n assign i0_ap.bne = i0_dp.bne;\n assign i0_ap.blt = i0_dp.blt;\n assign i0_ap.bge = i0_dp.bge;\n\n assign i0_ap.clz = i0_dp.clz;\n assign i0_ap.ctz = i0_dp.ctz;\n assign i0_ap.cpop = i0_dp.cpop;\n assign i0_ap.sext_b = i0_dp.sext_b;\n assign i0_ap.sext_h = i0_dp.sext_h;\n assign i0_ap.sh1add = i0_dp.sh1add;\n assign i0_ap.sh2add = i0_dp.sh2add;\n assign i0_ap.sh3add = i0_dp.sh3add;\n assign i0_ap.zba = i0_dp.zba;\n assign i0_ap.min = i0_dp.min;\n assign i0_ap.max = i0_dp.max;\n assign i0_ap.pack = i0_dp.pack;\n assign i0_ap.packu = i0_dp.packu;\n assign i0_ap.packh = i0_dp.packh;\n assign i0_ap.rol = i0_dp.rol;\n assign i0_ap.ror = i0_dp.ror;\n assign i0_ap.grev = i0_dp.grev;\n assign i0_ap.gorc = i0_dp.gorc;\n assign i0_ap.zbb = i0_dp.zbb;\n assign i0_ap.bset = i0_dp.bset;\n assign i0_ap.bclr = i0_dp.bclr;\n assign i0_ap.binv = i0_dp.binv;\n assign i0_ap.bext = i0_dp.bext;\n\n assign i0_ap.csr_write = i0_csr_write_only_d;\n assign i0_ap.csr_imm = i0_dp.csr_imm;\n assign i0_ap.jal = i0_jal;\n\n assign i0_ap_pc2 = ~dec_i0_pc4_d;\n assign i0_ap_pc4 = dec_i0_pc4_d;\n\n assign i0_ap.predict_nt = i0_predict_nt;\n assign i0_ap.predict_t = i0_predict_t;\n\n\n// non block load cam logic\n\n always_comb begin\n found = 0;\n for (int i=0; i coredecode.e\n// 2) espresso -Dso -oeqntott < coredecode.e | addassign -pre out. > equations\n// 3) copy-paste assignments from the file \"equations\" and replace ones below.\n//\n// To generate instruction legality check equation do:\n// 1) coredecode -in decode -legal > legal.e\n// 2) espresso -Dso -oeqntott < legal.e | addassign -pre out. > legal\n// 3) copy-paste assignment from the file \"legal\" and replace the one below.\n\nmodule el2_dec_dec_ctl\n import el2_pkg::*;\n(\n input logic [31:0] inst,\n output el2_dec_pkt_t out\n);\n\n logic [31:0] i;\n\n assign i[31:0] = inst[31:0];\n\n assign out.alu = (i[30]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[5]&i[4]) | (i[30]\n &!i[27]&!i[24]&i[4]) | (!i[30]&!i[25]&i[13]&i[12]) | (!i[29]&!i[27]\n &!i[5]&i[4]) | (i[27]&i[25]&i[14]&i[4]) | (!i[29]&!i[25]&!i[13]&!i[12]\n &i[4]) | (i[29]&i[27]&!i[14]&i[12]&i[4]) | (!i[27]&i[14]&!i[5]&i[4]) | (\n i[30]&!i[29]&!i[13]&i[4]) | (!i[27]&!i[25]&i[5]&i[4]) | (i[13]&!i[5]\n &i[4]) | (i[6]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&!i[5]\n &i[4]) | (i[2]) | (!i[12]&!i[5]&i[4]);\n\n assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | (\n !i[13]&i[9]&!i[2]) | (i[18]&i[13]&!i[2]) | (!i[13]&i[8]&!i[2]) | (\n i[17]&i[13]&!i[2]) | (!i[13]&i[7]&!i[2]) | (i[16]&i[13]&!i[2]) | (\n i[15]&i[13]&!i[2]) | (!i[4]&!i[2]) | (!i[14]&!i[13]&i[6]&!i[3]) | (\n !i[6]&!i[2]);\n\n assign out.rs2 = (i[5] & !i[4] & !i[2]) | (!i[6] & i[5] & !i[2]);\n\n assign out.imm12 = (!i[4]&!i[3]&i[2]) | (i[13]&!i[5]&i[4]&!i[2]) | (!i[13]&!i[12]\n &i[6]&i[4]) | (!i[12]&!i[5]&i[4]&!i[2]);\n\n assign out.rd = (!i[5] & !i[2]) | (i[5] & i[2]) | (i[4]);\n\n assign out.shimm5 = (!i[29]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[13]&i[12]\n &!i[5]&i[4]&!i[2]) | (i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);\n\n assign out.imm20 = (i[5] & i[3]) | (i[4] & i[2]);\n\n assign out.pc = (!i[5] & !i[3] & i[2]) | (i[5] & i[3]);\n\n assign out.load = (!i[5] & !i[4] & !i[2]);\n\n assign out.store = (!i[6] & i[5] & !i[4]);\n\n assign out.lsu = (!i[6] & !i[4] & !i[2]);\n\n assign out.add = (!i[14]&!i[13]&!i[12]&!i[5]&i[4]) | (!i[5]&!i[3]&i[2]) | (!i[30]\n &!i[25]&!i[14]&!i[13]&!i[12]&!i[6]&i[4]&!i[2]);\n\n assign out.sub = (i[30]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[29]&!i[25]&!i[14]\n &i[13]&!i[6]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]) | (\n !i[14]&i[13]&!i[5]&i[4]&!i[2]) | (i[6]&!i[4]&!i[2]);\n\n assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12]\n &!i[5]&!i[2]);\n\n assign out.lor = (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | (!i[6]&i[3]) | (\n i[5]&i[4]&i[2]) | (!i[13]&!i[12]&i[6]&i[4]) | (i[14]&i[13]&!i[12]\n &!i[5]&!i[2]);\n\n assign out.lxor = (!i[29]&!i[27]&!i[25]&i[14]&!i[13]&!i[12]&i[4]&!i[2]) | (i[14]\n &!i[13]&!i[12]&!i[5]&i[4]&!i[2]);\n\n assign out.sll = (!i[29] & !i[27] & !i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.sra = (i[30] & !i[29] & !i[27] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.srl = (!i[30] & !i[27] & !i[25] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.slt = (!i[29]&!i[25]&!i[14]&i[13]&!i[6]&i[4]&!i[2]) | (!i[14]&i[13]&!i[5]\n &i[4]&!i[2]);\n\n assign out.unsign = (!i[14]&i[13]&i[12]&!i[5]&!i[2]) | (i[13]&i[6]&!i[4]&!i[2]) | (\n i[14]&!i[5]&!i[4]) | (!i[25]&!i[14]&i[13]&i[12]&!i[6]&!i[2]) | (\n i[25]&i[14]&i[12]&!i[6]&i[5]&!i[2]);\n\n assign out.condbr = (i[6] & !i[4] & !i[2]);\n\n assign out.beq = (!i[14] & !i[12] & i[6] & !i[4] & !i[2]);\n\n assign out.bne = (!i[14] & i[12] & i[6] & !i[4] & !i[2]);\n\n assign out.bge = (i[14] & i[12] & i[5] & !i[4] & !i[2]);\n\n assign out.blt = (i[14] & !i[12] & i[5] & !i[4] & !i[2]);\n\n assign out.jal = (i[6] & i[2]);\n\n assign out.by = (!i[13] & !i[12] & !i[6] & !i[4] & !i[2]);\n\n assign out.half = (i[12] & !i[6] & !i[4] & !i[2]);\n\n assign out.word = (i[13] & !i[6] & !i[4]);\n\n assign out.csr_read = (i[13]&i[6]&i[4]) | (i[7]&i[6]&i[4]) | (i[8]&i[6]&i[4]) | (\n i[9]&i[6]&i[4]) | (i[10]&i[6]&i[4]) | (i[11]&i[6]&i[4]);\n\n assign out.csr_clr = (i[15]&i[13]&i[12]&i[6]&i[4]) | (i[16]&i[13]&i[12]&i[6]&i[4]) | (\n i[17]&i[13]&i[12]&i[6]&i[4]) | (i[18]&i[13]&i[12]&i[6]&i[4]) | (\n i[19]&i[13]&i[12]&i[6]&i[4]);\n\n assign out.csr_set = (i[15]&!i[12]&i[6]&i[4]) | (i[16]&!i[12]&i[6]&i[4]) | (i[17]\n &!i[12]&i[6]&i[4]) | (i[18]&!i[12]&i[6]&i[4]) | (i[19]&!i[12]&i[6]\n &i[4]);\n\n assign out.csr_write = (!i[13] & i[12] & i[6] & i[4]);\n\n assign out.csr_imm = (i[14]&!i[13]&i[6]&i[4]) | (i[15]&i[14]&i[6]&i[4]) | (i[16]\n &i[14]&i[6]&i[4]) | (i[17]&i[14]&i[6]&i[4]) | (i[18]&i[14]&i[6]&i[4]) | (\n i[19]&i[14]&i[6]&i[4]);\n\n assign out.presync = (!i[5]&i[3]) | (!i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | (\n !i[13]&i[9]&i[6]&i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11]\n &i[6]&i[4]) | (i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | (\n i[17]&i[13]&i[6]&i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6]\n &i[4]);\n\n assign out.postsync = (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | (i[12]&!i[5]&i[3]) | (\n !i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | (!i[13]&i[9]&i[6]\n &i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11]&i[6]&i[4]) | (\n i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | (i[17]&i[13]&i[6]\n &i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6]&i[4]);\n\n assign out.ebreak = (!i[22] & i[20] & !i[13] & !i[12] & i[6] & i[4]);\n\n assign out.ecall = (!i[21] & !i[20] & !i[13] & !i[12] & i[6] & i[4]);\n\n assign out.mret = (i[29] & !i[13] & !i[12] & i[6] & i[4]);\n\n assign out.mul = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]\n &i[27]&i[13]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[23]&!i[20]\n &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[21]&i[20]\n &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&i[24]&i[21]\n &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[24]&!i[22]\n &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&i[29]&i[23]&i[14]\n &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]&i[29]&i[27]&i[22]&i[14]\n &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[25]&i[13]&!i[12]&!i[6]\n &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6]\n &i[4]&!i[2]) | (i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]\n &i[14]&!i[6]&i[5]&!i[2]);\n\n assign out.rs1_sign = (!i[27]&i[25]&!i[14]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (\n !i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);\n\n assign out.rs2_sign = (!i[27] & i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.low = (i[25] & !i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);\n\n assign out.div = (!i[27] & i[25] & i[14] & !i[6] & i[5] & !i[2]);\n\n assign out.rem = (!i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]);\n\n assign out.fence = (!i[5] & i[3]);\n\n assign out.fence_i = (i[12] & !i[5] & i[3]);\n\n assign out.clz = (i[29]&!i[27]&!i[24]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]\n &i[4]&!i[2]);\n\n assign out.ctz = (i[29]&!i[27]&!i[24]&!i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]\n &!i[2]);\n\n assign out.cpop = (i[29]&!i[27]&!i[24]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);\n\n assign out.sext_b = (i[29]&!i[27]&i[22]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);\n\n assign out.sext_h = (i[29]&!i[27]&i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);\n\n assign out.min = (i[27] & i[25] & i[14] & !i[13] & !i[6] & i[5] & !i[2]);\n\n assign out.max = (i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]);\n\n assign out.pack = (!i[30] & !i[29] & i[27] & !i[25] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);\n\n assign out.packu = (i[30] & i[27] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);\n\n assign out.packh = (!i[30] & i[27] & !i[25] & i[13] & i[12] & !i[6] & i[5] & !i[2]);\n\n assign out.rol = (i[29] & !i[27] & !i[14] & i[12] & !i[6] & i[5] & i[4] & !i[2]);\n\n assign out.ror = (i[29] & !i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.zbb = (!i[30]&!i[29]&i[27]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[13]\n &!i[12]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&!i[24]&!i[13]&i[12]&!i[5]\n &i[4]&!i[2]) | (i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (\n i[30]&!i[27]&i[14]&!i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]\n &!i[6]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (\n !i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&i[14]&!i[13]&i[12]&!i[5]\n &i[4]&!i[2]) | (i[30]&i[29]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]\n &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);\n\n assign out.bset = (!i[30] & i[29] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.bclr = (i[30] & !i[29] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.binv = (i[30] & i[29] & i[27] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.bext = (i[30] & !i[29] & i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.zbs = (i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]) | (i[30]&!i[29]\n &i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);\n\n assign out.bcompress = (!i[30]&!i[29]&i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]);\n\n assign out.bdecompress = (i[30] & i[27] & i[13] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);\n\n assign out.zbe = (i[30]&i[27]&i[14]&i[13]&!i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&i[27]\n &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]\n &!i[12]&!i[6]&i[5]&i[4]&!i[2]);\n\n assign out.clmul = (i[27] & i[25] & !i[14] & !i[13] & !i[6] & i[5] & i[4] & !i[2]);\n\n assign out.clmulh = (i[27] & !i[14] & i[13] & i[12] & !i[6] & i[5] & !i[2]);\n\n assign out.clmulr = (i[27] & i[25] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);\n\n assign out.zbc = (i[27] & i[25] & !i[14] & !i[6] & i[5] & i[4] & !i[2]);\n\n assign out.grev = (i[30] & i[29] & i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.gorc = (!i[30] & i[29] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);\n\n assign out.shfl = (!i[30]&!i[29]&i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);\n\n assign out.unshfl = (!i[30]&!i[29]&i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);\n\n assign out.xperm_n = (i[29] & i[27] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);\n\n assign out.xperm_b = (i[29] & i[27] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);\n\n assign out.xperm_h = (i[29] & i[27] & i[14] & i[13] & !i[6] & i[5] & !i[2]);\n\n assign out.zbp = (i[30]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[30]&i[27]\n &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]&!i[6]\n &i[5]&i[4]&!i[2]) | (i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (\n i[30]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[12]&!i[6]\n &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6]\n &i[4]&!i[2]) | (i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);\n\n assign out.crc32_b = (i[29]&!i[27]&i[24]&!i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]\n &!i[5]&i[4]&!i[2]);\n\n assign out.crc32_h = (i[29]&!i[27]&i[24]&!i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]\n &!i[2]);\n\n assign out.crc32_w = (i[29]&!i[27]&i[24]&!i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]\n &!i[2]);\n\n assign out.crc32c_b = (i[29]&!i[27]&i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]\n &i[4]&!i[2]);\n\n assign out.crc32c_h = (i[29]&!i[27]&i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);\n\n assign out.crc32c_w = (i[29]&!i[27]&i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);\n\n assign out.zbr = (i[29] & !i[27] & i[24] & !i[14] & !i[13] & i[12] & !i[5] & i[4] & !i[2]);\n\n assign out.bfp = (i[30] & i[27] & i[13] & i[12] & !i[6] & i[5] & !i[2]);\n\n assign out.zbf = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (\n i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]);\n\n assign out.sh1add = (i[29] & !i[27] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);\n\n assign out.sh2add = (i[29] & !i[27] & i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);\n\n assign out.sh3add = (i[29] & !i[27] & i[14] & i[13] & !i[6] & i[5] & !i[2]);\n\n assign out.zba = (i[29] & !i[27] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);\n\n assign out.pm_alu = (i[28]&i[20]&!i[13]&!i[12]&i[4]) | (!i[30]&!i[29]&!i[27]&!i[25]\n &!i[6]&i[4]) | (!i[29]&!i[27]&!i[25]&!i[13]&i[12]&!i[6]&i[4]) | (\n !i[29]&!i[27]&!i[25]&!i[14]&!i[6]&i[4]) | (i[13]&!i[5]&i[4]) | (i[4]\n &i[2]) | (!i[12]&!i[5]&i[4]);\n\n\n assign out.legal = (!i[31]&!i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]\n &!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]\n &!i[10]&!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (\n !i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&i[22]\n &!i[21]&i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]\n &!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]\n &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]\n &!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]&!i[9]&!i[8]\n &!i[7]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]\n &!i[26]&!i[25]&i[24]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (\n !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&i[24]&!i[22]&!i[21]&!i[6]\n &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]&!i[26]\n &!i[25]&!i[23]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (\n !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[24]&!i[23]&!i[21]&!i[6]\n &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26]\n &i[25]&i[13]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[28]&i[27]&!i[26]\n &!i[25]&!i[24]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]\n &i[29]&!i[28]&!i[26]&!i[25]&i[13]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (\n !i[31]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[13]&!i[12]&!i[6]&i[4]\n &!i[3]&i[1]&i[0]) | (!i[31]&i[30]&!i[28]&!i[26]&!i[25]&i[14]&!i[6]\n &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26]\n &!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]\n &!i[28]&!i[27]&!i[26]&!i[25]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]\n &i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]\n &i[1]&i[0]) | (!i[31]&i[30]&!i[28]&i[27]&!i[26]&!i[25]&!i[13]&i[12]\n &!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&!i[26]&!i[25]\n &i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[27]\n &!i[26]&!i[25]&!i[13]&i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]\n &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | (\n !i[31]&!i[30]&!i[29]&!i[28]&!i[26]&i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]\n &i[0]) | (!i[14]&!i[13]&!i[12]&i[6]&i[5]&!i[4]&!i[3]&i[1]&i[0]) | (\n i[14]&i[6]&i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&!i[13]&i[5]\n &!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[12]&!i[6]&!i[5]&i[4]&!i[3]&i[1]\n &i[0]) | (!i[13]&i[12]&i[6]&i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[13]&i[6]\n &i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&!i[29]&!i[28]&!i[14]\n &!i[13]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]\n &!i[26]&!i[25]&i[14]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[14]\n &!i[13]&i[12]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (i[6]&i[5]\n &!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[14]&!i[12]&!i[6]&!i[4]&!i[3]&!i[2]\n &i[1]&i[0]) | (!i[13]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (\n i[13]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[6]&i[4]&!i[3]&i[2]&i[1]\n &i[0]);\n\nendmodule // el2_dec_dec_ctl\n" }, { "path": "design/dec/el2_dec_gpr_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\nmodule el2_dec_gpr_ctl\nimport el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n ) (\n input logic [4:0] raddr0, // logical read addresses\n input logic [4:0] raddr1,\n\n input logic wen0, // write enable\n input logic [4:0] waddr0, // write address\n input logic [31:0] wd0, // write data\n\n input logic wen1, // write enable\n input logic [4:0] waddr1, // write address\n input logic [31:0] wd1, // write data\n\n input logic wen2, // write enable\n input logic [4:0] waddr2, // write address\n input logic [31:0] wd2, // write data\n\n input logic clk,\n input logic rst_l,\n\n output logic [31:0] rd0, // read data\n output logic [31:0] rd1,\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n el2_regfile_if.veer_gpr_rf regfile,\n`endif\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n);\n\n logic [31:1] [31:0] gpr_out; // 31 x 32 bit GPRs\n logic [31:1] [31:0] gpr_in;\n logic [31:1] w0v,w1v,w2v;\n logic [31:1] gpr_wr_en;\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n assign regfile.gpr.ra = gpr_out[1][31:0]; // x1\n assign regfile.gpr.sp = gpr_out[2][31:0]; // x2\n assign regfile.gpr.fp = gpr_out[8][31:0]; // x8\n assign regfile.gpr.a0 = gpr_out[10][31:0]; // x10\n assign regfile.gpr.a1 = gpr_out[11][31:0]; // x11\n assign regfile.gpr.a2 = gpr_out[12][31:0]; // x12\n assign regfile.gpr.a3 = gpr_out[13][31:0]; // x13\n assign regfile.gpr.a4 = gpr_out[14][31:0]; // x14\n assign regfile.gpr.a5 = gpr_out[15][31:0]; // x15\n assign regfile.gpr.a6 = gpr_out[16][31:0]; // x16\n assign regfile.gpr.a7 = gpr_out[17][31:0]; // x17\n`endif\n\n // GPR Write Enables\n assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);\n for ( genvar j=1; j<32; j++ ) begin : gpr\n rvdffe #(32) gprff (.*, .en(gpr_wr_en[j]), .din(gpr_in[j][31:0]), .dout(gpr_out[j][31:0]));\n end : gpr\n\n // the read out\n always_comb begin\n rd0[31:0] = 32'b0;\n rd1[31:0] = 32'b0;\n w0v[31:1] = 31'b0;\n w1v[31:1] = 31'b0;\n w2v[31:1] = 31'b0;\n gpr_in[31:1] = '0;\n\n // GPR Read logic\n for (int j=1; j<32; j++ ) begin\n rd0[31:0] |= ({32{(raddr0[4:0]== 5'(j))}} & gpr_out[j][31:0]);\n rd1[31:0] |= ({32{(raddr1[4:0]== 5'(j))}} & gpr_out[j][31:0]);\n end\n\n // GPR Write logic\n for (int j=1; j<32; j++ ) begin\n w0v[j] = wen0 & (waddr0[4:0]== 5'(j) );\n w1v[j] = wen1 & (waddr1[4:0]== 5'(j) );\n w2v[j] = wen2 & (waddr2[4:0]== 5'(j) );\n gpr_in[j] = ({32{w0v[j]}} & wd0[31:0]) |\n ({32{w1v[j]}} & wd1[31:0]) |\n ({32{w2v[j]}} & wd2[31:0]);\n end\n end // always_comb begin\n\n`ifdef RV_ASSERT_ON\n\n logic write_collision_unused;\n assign write_collision_unused = ( (w0v[31:1] == w1v[31:1]) & wen0 & wen1 ) |\n ( (w0v[31:1] == w2v[31:1]) & wen0 & wen2 ) |\n ( (w1v[31:1] == w2v[31:1]) & wen1 & wen2 );\n\n\n // asserting that no 2 ports will write to the same gpr simultaneously\n assert_multiple_wen_to_same_gpr: assert #0 (~( write_collision_unused ) );\n\n`endif\n\nendmodule\n" }, { "path": "design/dec/el2_dec_ib_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\nmodule el2_dec_ib_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic dbg_cmd_valid, // valid dbg cmd\n\n input logic dbg_cmd_write, // dbg cmd is write\n input logic [1:0] dbg_cmd_type, // dbg type\n input logic [31:0] dbg_cmd_addr, // expand to 31:0\n\n input el2_br_pkt_t i0_brp, // i0 branch packet from aligner\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index\n input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR\n input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag\n input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index\n\n input logic ifu_i0_pc4, // i0 is 4B inst else 2B\n input logic ifu_i0_valid, // i0 valid from ifu\n input logic ifu_i0_icaf, // i0 instruction access fault\n input logic [1:0] ifu_i0_icaf_type, // i0 instruction access fault type\n\n input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst\n input logic ifu_i0_dbecc, // i0 double-bit error\n input logic [31:0] ifu_i0_instr, // i0 instruction from the aligner\n input logic [31:1] ifu_i0_pc, // i0 pc from the aligner\n\n\n output logic dec_ib0_valid_d, // ib0 valid\n output logic dec_debug_valid_d, // Debug read or write at D-stage\n\n\n output logic [31:0] dec_i0_instr_d, // i0 inst at decode\n\n output logic [31:1] dec_i0_pc_d, // i0 pc at decode\n\n output logic dec_i0_pc4_d, // i0 is 4B inst else 2B\n\n output el2_br_pkt_t dec_i0_brp, // i0 branch packet at decode\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index\n output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR\n output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag\n output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index\n\n output logic dec_i0_icaf_d, // i0 instruction access fault at decode\n output logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst\n output logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type\n output logic dec_i0_dbecc_d, // i0 double-bit error at decode\n output logic dec_debug_wdata_rs1_d, // put debug write data onto rs1 source: machine is halted\n\n output logic dec_debug_fence_d // debug fence inst\n\n );\n\n\n logic debug_valid;\n logic [4:0] dreg;\n logic [11:0] dcsr;\n logic [31:0] ib0, ib0_debug_in;\n\n logic debug_read;\n logic debug_write;\n logic debug_read_gpr;\n logic debug_write_gpr;\n logic debug_read_csr;\n logic debug_write_csr;\n\n logic [34:0] ifu_i0_pcdata, pc0;\n\n assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf,\n ifu_i0_pc[31:1], ifu_i0_pc4 };\n\n assign pc0[34:0] = ifu_i0_pcdata[34:0];\n\n assign dec_i0_icaf_second_d = pc0[34]; // icaf's can only decode as i0\n\n assign dec_i0_dbecc_d = pc0[33];\n\n assign dec_i0_icaf_d = pc0[32];\n assign dec_i0_pc_d[31:1] = pc0[31:1];\n assign dec_i0_pc4_d = pc0[0];\n\n assign dec_i0_icaf_type_d[1:0] = ifu_i0_icaf_type[1:0];\n\n// GPR accesses\n\n// put reg to read on rs1\n// read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011}\n\n// put write date on rs1\n// write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011}\n\n\n// CSR accesses\n// csr is of form rd, csr, rs1\n\n// read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011}\n\n// put write data on rs1\n// write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011}\n\n// abstract memory command not done here\n assign debug_valid = dbg_cmd_valid & (dbg_cmd_type[1:0] != 2'h2);\n\n\n assign debug_read = debug_valid & ~dbg_cmd_write;\n assign debug_write = debug_valid & dbg_cmd_write;\n\n assign debug_read_gpr = debug_read & (dbg_cmd_type[1:0]==2'h0);\n assign debug_write_gpr = debug_write & (dbg_cmd_type[1:0]==2'h0);\n assign debug_read_csr = debug_read & (dbg_cmd_type[1:0]==2'h1);\n assign debug_write_csr = debug_write & (dbg_cmd_type[1:0]==2'h1);\n\n assign dreg[4:0] = dbg_cmd_addr[4:0];\n assign dcsr[11:0] = dbg_cmd_addr[11:0];\n\n\n assign ib0_debug_in[31:0] = ({32{debug_read_gpr}} & {12'b000000000000,dreg[4:0],15'b110000000110011}) |\n ({32{debug_write_gpr}} & {20'b00000000000000000110,dreg[4:0],7'b0110011}) |\n ({32{debug_read_csr}} & {dcsr[11:0],20'b00000010000001110011}) |\n ({32{debug_write_csr}} & {dcsr[11:0],20'b00000001000001110011});\n\n\n\n // machine is in halted state, pipe empty, write will always happen next cycle\n\n assign dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr;\n\n\n // special fence csr for use only in debug mode\n\n assign dec_debug_fence_d = debug_write_csr & (dcsr[11:0] == 12'h7c4);\n\n assign ib0[31:0] = (debug_valid) ? ib0_debug_in[31:0] : ifu_i0_instr[31:0];\n\n assign dec_ib0_valid_d = ifu_i0_valid | debug_valid;\n\n assign dec_debug_valid_d = debug_valid;\n\n assign dec_i0_instr_d[31:0] = ib0[31:0];\n\n assign dec_i0_brp = i0_brp;\n assign dec_i0_bp_index = ifu_i0_bp_index;\n assign dec_i0_bp_fghr = ifu_i0_bp_fghr;\n assign dec_i0_bp_btag = ifu_i0_bp_btag;\n assign dec_i0_bp_fa_index = ifu_i0_fa_index;\n\nendmodule\n" }, { "path": "design/dec/el2_dec_pmp_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2023 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n\n//********************************************************************************\n// el2_dec_pmp_ctl.sv\n//\n//\n// Function: Physical Memory Protection CSRs\n// Comments:\n//\n//********************************************************************************\n\nmodule el2_dec_pmp_ctl\n import el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic clk,\n input logic free_l2clk,\n input logic csr_wr_clk,\n input logic rst_l,\n input logic dec_csr_wen_r_mod, // csr write enable at wb\n input logic [11:0] dec_csr_wraddr_r, // write address for csr\n input logic [31:0] dec_csr_wrdata_r, // csr write data at wb\n input logic [11:0] dec_csr_rdaddr_d, // read address for csr\n\n input logic csr_pmpcfg,\n input logic csr_pmpaddr0,\n input logic csr_pmpaddr16,\n input logic csr_pmpaddr32,\n input logic csr_pmpaddr48,\n\n input logic dec_pause_state, // Paused\n input logic dec_tlu_pmu_fw_halted, // pmu/fw halted\n input logic internal_dbg_halt_timers, // debug halted\n\n`ifdef RV_SMEPMP\n input el2_mseccfg_pkt_t mseccfg,\n`endif\n\n output logic [31:0] dec_pmp_rddata_d, // pmp CSR read data\n output logic dec_pmp_read_d, // pmp CSR address match\n\n output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],\n output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES],\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n );\n\n logic wr_pmpcfg_r;\n logic [3:0] wr_pmpcfg_group;\n\n logic wr_pmpaddr0_sel;\n logic wr_pmpaddr16_sel;\n logic wr_pmpaddr32_sel;\n logic wr_pmpaddr48_sel;\n logic wr_pmpaddr_r;\n logic [1:0] wr_pmpaddr_quarter;\n logic [5:0] wr_pmpaddr_address;\n\n logic [3:0] pmp_quarter_rdaddr;\n logic [31:0] pmp_pmpcfg_rddata;\n\n // ----------------------------------------------------------------------\n\n logic [pt.PMP_ENTRIES-1:0] entry_lock_eff; // Effective entry lock\n for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_pmpcfg_lock\n`ifdef RV_SMEPMP\n // Smepmp allow modifying locked entries when mseccfg.RLB is set\n assign entry_lock_eff[r] = pmp_pmpcfg[r].lock & ~mseccfg.RLB;\n`else\n assign entry_lock_eff[r] = pmp_pmpcfg[r].lock;\n`endif\n end\n\n // ----------------------------------------------------------------------\n // PMPCFGx (RW)\n // [31:24] : PMP entry (x*4 + 3) configuration\n // [23:16] : PMP entry (x*4 + 2) configuration\n // [15:8] : PMP entry (x*4 + 1) configuration\n // [7:0] : PMP entry (x*4 + 0) configuration\n\n localparam PMPCFG = 12'h3a0;\n localparam PMP_ENTRIES_WIDTH = $clog2(pt.PMP_ENTRIES);\n\n assign wr_pmpcfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:4] == PMPCFG[11:4]);\n assign wr_pmpcfg_group = dec_csr_wraddr_r[3:0]; // selects group of 4 pmpcfg entries (group 1 -> entries 4-7; up to 16 groups)\n\n for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpcfg_ff\n logic [7:0] raw_wdata;\n logic [7:0] csr_wdata;\n\n // PMPCFG fields are WARL. Mask out bits 6:5 during write.\n // When Smepmp is disabled R=0 and W=1 combination is illegal mask out W\n // when R is cleared.\n assign raw_wdata = dec_csr_wrdata_r[(entry_idx[1:0]*8)+7:(entry_idx[1:0]*8)+0];\n`ifdef RV_SMEPMP\n assign csr_wdata = raw_wdata & 8'b10011111;\n`else\n assign csr_wdata = raw_wdata[0] ? (raw_wdata & 8'b10011111) : (raw_wdata & 8'b10011101);\n`endif\n\n rvdffe #(8) pmpcfg_ff (.*, .clk(free_l2clk),\n .en(wr_pmpcfg_r & (wr_pmpcfg_group == entry_idx[5:2]) & (~entry_lock_eff[entry_idx])),\n .din(csr_wdata),\n .dout(pmp_pmpcfg[entry_idx]));\n end\n\n // ----------------------------------------------------------------------\n // PMPADDRx (RW)\n // [31:0] : PMP entry (x) address selector (word addressing)\n //\n // NOTE: VeeR-EL2 uses 32-bit physical addressing, register bits 31:30 mapping\n // to bits 33:32 of the physical address are always set to 0. (WARL)\n\n localparam PMPADDR0 = 12'h3b0;\n localparam PMPADDR16 = 12'h3c0;\n localparam PMPADDR32 = 12'h3d0;\n localparam PMPADDR48 = 12'h3e0;\n\n assign wr_pmpaddr0_sel = dec_csr_wraddr_r[11:4] == PMPADDR0[11:4];\n assign wr_pmpaddr16_sel = dec_csr_wraddr_r[11:4] == PMPADDR16[11:4];\n assign wr_pmpaddr32_sel = dec_csr_wraddr_r[11:4] == PMPADDR32[11:4];\n assign wr_pmpaddr48_sel = dec_csr_wraddr_r[11:4] == PMPADDR48[11:4];\n assign wr_pmpaddr_r = dec_csr_wen_r_mod & (wr_pmpaddr0_sel | wr_pmpaddr16_sel | wr_pmpaddr32_sel | wr_pmpaddr48_sel);\n\n assign wr_pmpaddr_quarter[0] = wr_pmpaddr16_sel | wr_pmpaddr48_sel;\n assign wr_pmpaddr_quarter[1] = wr_pmpaddr32_sel | wr_pmpaddr48_sel;\n assign wr_pmpaddr_address = {wr_pmpaddr_quarter, dec_csr_wraddr_r[3:0]}; // entry address\n\n for (genvar entry_idx = 0; entry_idx < pt.PMP_ENTRIES; entry_idx++) begin : gen_pmpaddr_ff\n logic pmpaddr_lock;\n logic pmpaddr_lock_next;\n if (entry_idx+1 < pt.PMP_ENTRIES)\n assign pmpaddr_lock_next = entry_lock_eff[entry_idx+1] & pmp_pmpcfg[entry_idx+1].mode == TOR;\n else\n assign pmpaddr_lock_next = 1'b0;\n assign pmpaddr_lock = entry_lock_eff[entry_idx] | pmpaddr_lock_next;\n assign pmp_pmpaddr[entry_idx][31:30] = 2'b00;\n rvdffe #(30) pmpaddr_ff (.*, .clk(free_l2clk),\n .en(wr_pmpaddr_r & (wr_pmpaddr_address == entry_idx)\n & (~pmpaddr_lock)),\n .din(dec_csr_wrdata_r[29:0]),\n .dout(pmp_pmpaddr[entry_idx][29:0]));\n end\n\n // CSR read mux\n logic [5:0] pmp_pmpcfg_rdata_selector [4];\n logic [5:0] dec_pmp_rdata_selector [4];\n\n assign pmp_quarter_rdaddr = dec_csr_rdaddr_d[3:0];\n\n for (genvar i = 0; i < 4; i++) begin: gen_csr_selector\n assign pmp_pmpcfg_rdata_selector[i] = {pmp_quarter_rdaddr, 2'(i)};\n assign dec_pmp_rdata_selector[i] = {2'(i), pmp_quarter_rdaddr};\n end\n\n assign pmp_pmpcfg_rddata = { pmp_pmpcfg[pmp_pmpcfg_rdata_selector[3][PMP_ENTRIES_WIDTH-1:0]],\n pmp_pmpcfg[pmp_pmpcfg_rdata_selector[2][PMP_ENTRIES_WIDTH-1:0]],\n pmp_pmpcfg[pmp_pmpcfg_rdata_selector[1][PMP_ENTRIES_WIDTH-1:0]],\n pmp_pmpcfg[pmp_pmpcfg_rdata_selector[0][PMP_ENTRIES_WIDTH-1:0]]\n };\n assign dec_pmp_read_d = csr_pmpcfg | csr_pmpaddr0 | csr_pmpaddr16 | csr_pmpaddr32 | csr_pmpaddr48;\n assign dec_pmp_rddata_d[31:0] = ( ({32{csr_pmpcfg}} & pmp_pmpcfg_rddata) |\n ({32{csr_pmpaddr0}} & pmp_pmpaddr[dec_pmp_rdata_selector[0][PMP_ENTRIES_WIDTH-1:0]]) |\n ({32{csr_pmpaddr16}} & pmp_pmpaddr[dec_pmp_rdata_selector[1][PMP_ENTRIES_WIDTH-1:0]]) |\n ({32{csr_pmpaddr32}} & pmp_pmpaddr[dec_pmp_rdata_selector[2][PMP_ENTRIES_WIDTH-1:0]]) |\n ({32{csr_pmpaddr48}} & pmp_pmpaddr[dec_pmp_rdata_selector[3][PMP_ENTRIES_WIDTH-1:0]])\n );\n\nendmodule // dec_pmp_ctl\n" }, { "path": "design/dec/el2_dec_tlu_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or it's affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n\n//********************************************************************************\n// el2_dec_tlu_ctl.sv\n//\n//\n// Function: CSRs, Commit/WB, flushing, exceptions, interrupts\n// Comments:\n//\n//********************************************************************************\n\nmodule el2_dec_tlu_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic clk,\n input logic free_clk,\n input logic free_l2clk,\n input logic rst_l,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n\n //rst_vec is supposed to be connected to constant in the top level\n /*pragma coverage off*/\n input logic [31:1] rst_vec, // reset vector, from core pins\n /*pragma coverage on*/\n input logic nmi_int, // nmi pin\n //nmi_vec is supposed to be connected to constant in the top level\n /*pragma coverage off*/\n input logic [31:1] nmi_vec, // nmi vector\n /*pragma coverage on*/\n input logic i_cpu_halt_req, // Asynchronous Halt request to CPU\n input logic i_cpu_run_req, // Asynchronous Restart request to CPU\n\n input logic lsu_fastint_stall_any, // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle\n\n\n // perf counter inputs\n input logic ifu_pmu_instr_aligned, // aligned instructions\n input logic ifu_pmu_fetch_stall, // fetch unit stalled\n input logic ifu_pmu_ic_miss, // icache miss\n input logic ifu_pmu_ic_hit, // icache hit\n input logic ifu_pmu_bus_error, // Instruction side bus error\n input logic ifu_pmu_bus_busy, // Instruction side bus busy\n input logic ifu_pmu_bus_trxn, // Instruction side bus transaction\n input logic dec_pmu_instr_decoded, // decoded instructions\n input logic dec_pmu_decode_stall, // decode stall\n input logic dec_pmu_presync_stall, // decode stall due to presync'd inst\n input logic dec_pmu_postsync_stall,// decode stall due to postsync'd inst\n input logic lsu_store_stall_any, // SB or WB is full, stall decode\n input logic dma_dccm_stall_any, // DMA stall of lsu\n input logic dma_iccm_stall_any, // DMA stall of ifu\n input logic exu_pmu_i0_br_misp, // pipe 0 branch misp\n input logic exu_pmu_i0_br_ataken, // pipe 0 branch actual taken\n input logic exu_pmu_i0_pc4, // pipe 0 4 byte branch\n input logic lsu_pmu_bus_trxn, // D side bus transaction\n input logic lsu_pmu_bus_misaligned, // D side bus misaligned\n input logic lsu_pmu_bus_error, // D side bus error\n input logic lsu_pmu_bus_busy, // D side bus busy\n input logic lsu_pmu_load_external_m, // D side bus load\n input logic lsu_pmu_store_external_m, // D side bus store\n input logic dma_pmu_dccm_read, // DMA DCCM read\n input logic dma_pmu_dccm_write, // DMA DCCM write\n input logic dma_pmu_any_read, // DMA read\n input logic dma_pmu_any_write, // DMA write\n\n input logic [31:1] lsu_fir_addr, // Fast int address\n input logic [1:0] lsu_fir_error, // Fast int lookup error\n\n input logic iccm_dma_sb_error, // I side dma single bit error\n\n input el2_lsu_error_pkt_t lsu_error_pkt_r, // lsu precise exception/error packet\n input logic lsu_single_ecc_error_incr, // LSU inc SB error counter\n\n input logic dec_pause_state, // Pause counter not zero\n input logic lsu_imprecise_error_store_any, // store bus error\n input logic lsu_imprecise_error_load_any, // store bus error\n input logic [31:0] lsu_imprecise_error_addr_any, // store bus error address\n\n input logic dec_csr_wen_unq_d, // valid csr with write - for csr legal\n input logic dec_csr_any_unq_d, // valid csr - for csr legal\n input logic [11:0] dec_csr_rdaddr_d, // read address for csr\n\n input logic dec_csr_wen_r, // csr write enable at wb\n input logic [11:0] dec_csr_rdaddr_r, // read address for csr\n input logic [11:0] dec_csr_wraddr_r, // write address for csr\n input logic [31:0] dec_csr_wrdata_r, // csr write data at wb\n\n input logic dec_csr_stall_int_ff, // csr is mie/mstatus\n\n input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid\n\n input logic [31:1] exu_npc_r, // for NPC tracking\n\n input logic [31:1] dec_tlu_i0_pc_r, // for PC/NPC tracking\n\n input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode\n\n input logic [31:0] dec_illegal_inst, // For mtval\n input logic dec_i0_decode_d, // decode valid, used for clean icache diagnostics\n\n // branch info from pipe0 for errors or counter updates\n input logic [1:0] exu_i0_br_hist_r, // history\n input logic exu_i0_br_error_r, // error\n input logic exu_i0_br_start_error_r, // start error\n input logic exu_i0_br_valid_r, // valid\n input logic exu_i0_br_mp_r, // mispredict\n input logic exu_i0_br_middle_r, // middle of bank\n\n // branch info from pipe1 for errors or counter updates\n\n input logic exu_i0_br_way_r, // way hit or repl\n\n output logic dec_tlu_core_empty, // core is empty\n // Debug start\n output logic dec_dbg_cmd_done, // abstract command done\n output logic dec_dbg_cmd_fail, // abstract command failed\n output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command\n output logic dec_tlu_debug_mode, // Core is in debug mode\n output logic dec_tlu_resume_ack, // Resume acknowledge\n output logic dec_tlu_debug_stall, // stall decode while waiting on core to empty\n\n output logic dec_tlu_flush_noredir_r , // Tell fetch to idle on this flush\n output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC\n output logic dec_tlu_flush_leak_one_r, // single step\n output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc. This is the D stage of the error\n\n output logic dec_tlu_flush_extint, // fast ext int started\n output logic [31:2] dec_tlu_meihap, // meihap for fast int\n\n input logic dbg_halt_req, // DM requests a halt\n input logic dbg_resume_req, // DM requests a resume\n input logic ifu_miss_state_idle, // I-side miss buffer empty\n input logic lsu_idle_any, // lsu is idle\n input logic dec_div_active, // oop div is active\n output el2_trigger_pkt_t [3:0] trigger_pkt_any, // trigger info for trigger blocks\n\n input logic ifu_ic_error_start, // IC single bit error\n input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error\n\n\n input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data\n input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid\n output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics\n // Debug end\n\n input logic [7:0] pic_claimid, // pic claimid for csr\n input logic [3:0] pic_pl, // pic priv level for csr\n input logic mhwakeup, // high priority external int, wakeup if halted\n\n input logic mexintpend, // external interrupt pending\n input logic timer_int, // timer interrupt pending\n input logic soft_int, // software interrupt pending\n\n output logic o_cpu_halt_status, // PMU interface, halted\n output logic o_cpu_halt_ack, // halt req ack\n output logic o_cpu_run_ack, // run req ack\n output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request\n\n /*pragma coverage off*/\n input logic [31:4] core_id, // Core ID\n /*pragma coverage on*/\n\n // external MPC halt/run interface\n input logic mpc_debug_halt_req, // Async halt request\n input logic mpc_debug_run_req, // Async run request\n input logic mpc_reset_run_req, // Run/halt after reset\n output logic mpc_debug_halt_ack, // Halt ack\n output logic mpc_debug_run_ack, // Run ack\n output logic debug_brkpt_status, // debug breakpoint\n\n output logic [3:0] dec_tlu_meicurpl, // to PIC\n output logic [3:0] dec_tlu_meipt, // to PIC\n\n\n output logic [31:0] dec_csr_rddata_d, // csr read data at wb\n output logic dec_csr_legal_d, // csr indicates legal operation\n\n output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp\n\n output logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state\n output logic dec_tlu_flush_lower_wb, // commit has a flush (exception, int, mispredict at e4)\n output logic dec_tlu_i0_commit_cmt, // committed an instruction\n\n output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state\n output logic dec_tlu_flush_lower_r, // commit has a flush (exception, int)\n output logic [31:1] dec_tlu_flush_path_r, // flush pc\n output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache\n output logic dec_tlu_wr_pause_r, // CSR write to pause reg is at R.\n output logic dec_tlu_flush_pause_r, // Flush is due to pause\n\n output logic dec_tlu_presync_d, // CSR read needs to be presync'd\n output logic dec_tlu_postsync_d, // CSR needs to be presync'd\n\n\n output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control\n\n output logic dec_tlu_force_halt, // halt has been forced\n\n output logic dec_tlu_perfcnt0, // toggles when pipe0 perf counter 0 has an event inc\n output logic dec_tlu_perfcnt1, // toggles when pipe0 perf counter 1 has an event inc\n output logic dec_tlu_perfcnt2, // toggles when pipe0 perf counter 2 has an event inc\n output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc\n\n output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid\n output logic dec_tlu_i0_valid_wb1, // pipe 0 valid\n output logic dec_tlu_int_valid_wb1, // pipe 2 int valid\n output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause\n output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value\n\n // feature disable from mfdc\n output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding\n output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address\n output logic dec_tlu_core_ecc_disable, // disable core ECC\n output logic dec_tlu_bpred_disable, // disable branch prediction\n output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing\n output logic dec_tlu_pipelining_disable, // disable pipelining\n output logic dec_tlu_trace_disable, // disable trace\n output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16]\n\n // clock gating overrides from mcgc\n output logic dec_tlu_misc_clk_override, // override misc clock domain gating\n output logic dec_tlu_dec_clk_override, // override decode clock domain gating\n output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating\n output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating\n output logic dec_tlu_bus_clk_override, // override bus clock domain gating\n output logic dec_tlu_pic_clk_override, // override PIC clock domain gating\n output logic dec_tlu_picio_clk_override,// override PICIO clock domain gating\n output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating\n output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n el2_regfile_if.veer_tlu_rf regfile,\n`endif\n\n`ifdef RV_USER_MODE\n\n // Privilege mode\n // 0 - machine, 1 - user\n output logic priv_mode,\n output logic priv_mode_eff,\n output logic priv_mode_ns,\n\n // mseccfg CSR content for PMP\n output logic [2:0] mseccfg,\n\n`endif\n\n // pmp\n output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],\n output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES]\n );\n\n logic clk_override, e4e5_int_clk, nmi_fir_type, nmi_lsu_load_type, nmi_lsu_store_type, nmi_int_detected_f, nmi_lsu_load_type_f,\n nmi_lsu_store_type_f, allow_dbg_halt_csr_write, dbg_cmd_done_ns, i_cpu_run_req_d1_raw, debug_mode_status, lsu_single_ecc_error_r_d1,\n sel_npc_r, sel_npc_resume, ce_int,\n nmi_in_debug_mode, dpc_capture_npc, dpc_capture_pc, tdata_load, tdata_opcode, tdata_action, perfcnt_halted, tdata_chain,\n tdata_kill_write;\n\n\n logic reset_delayed, reset_detect, reset_detected;\n logic wr_mstatus_r, wr_mtvec_r, wr_mcyclel_r, wr_mcycleh_r,\n wr_minstretl_r, wr_minstreth_r, wr_mscratch_r, wr_mepc_r, wr_mcause_r, wr_mscause_r, wr_mtval_r,\n wr_mrac_r, wr_meihap_r, wr_meicurpl_r, wr_meipt_r, wr_dcsr_r,\n wr_dpc_r, wr_meicidpl_r, wr_meivt_r, wr_meicpct_r, wr_micect_r, wr_miccmect_r, wr_mfdht_r, wr_mfdhs_r,\n wr_mdccmect_r,wr_mhpme3_r, wr_mhpme4_r, wr_mhpme5_r, wr_mhpme6_r;\n logic wr_mpmc_r;\n logic [1:1] mpmc_b_ns, mpmc, mpmc_b;\n logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted;\n logic wr_mcountinhibit_r;\n`ifdef RV_USER_MODE\n logic wr_mcounteren_r;\n logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY\n logic wr_mseccfg_r;\n logic [2:0] mseccfg_ns;\n`endif\n logic [6:0] mcountinhibit;\n logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;\n logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out;\n logic [9:0] mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3;\n logic [9:0] tdata_wrdata_r;\n logic [1:0] mtsel_ns, mtsel;\n logic tlu_i0_kill_writeb_r;\n`ifdef RV_USER_MODE\n logic [3:0] mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE\n`else\n logic [1:0] mstatus_ns, mstatus;\n`endif\n logic [1:0] mfdhs_ns, mfdhs;\n logic [31:0] force_halt_ctr, force_halt_ctr_f;\n logic force_halt;\n logic [5:0] mfdht, mfdht_ns;\n logic mstatus_mie_ns;\n logic [30:0] mtvec_ns, mtvec;\n logic [15:2] dcsr_ns, dcsr;\n logic [5:0] mip_ns, mip;\n logic [5:0] mie_ns, mie;\n logic [31:0] mcyclel_ns, mcyclel;\n logic [31:0] mcycleh_ns, mcycleh;\n logic [31:0] minstretl_ns, minstretl;\n logic [31:0] minstreth_ns, minstreth;\n logic [31:0] micect_ns, micect, miccmect_ns, miccmect, mdccmect_ns, mdccmect;\n logic [26:0] micect_inc, miccmect_inc, mdccmect_inc;\n logic [31:0] mscratch;\n logic [31:0] mhpmc3, mhpmc3_ns, mhpmc4, mhpmc4_ns, mhpmc5, mhpmc5_ns, mhpmc6, mhpmc6_ns;\n logic [31:0] mhpmc3h, mhpmc3h_ns, mhpmc4h, mhpmc4h_ns, mhpmc5h, mhpmc5h_ns, mhpmc6h, mhpmc6h_ns;\n logic [9:0] mhpme3, mhpme4, mhpme5, mhpme6;\n logic [31:0] mrac;\n logic [9:2] meihap;\n logic [31:10] meivt;\n logic [3:0] meicurpl_ns, meicurpl;\n logic [3:0] meicidpl_ns, meicidpl;\n logic [3:0] meipt_ns, meipt;\n logic [31:0] mdseac;\n logic mdseac_locked_ns, mdseac_locked_f, mdseac_en, nmi_lsu_detected;\n logic [31:1] mepc_ns, mepc;\n logic [31:1] dpc_ns, dpc;\n logic [31:0] mcause_ns, mcause;\n logic [3:0] mscause_ns, mscause, mscause_type;\n logic [31:0] mtval_ns, mtval;\n logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb;\n logic tlu_flush_lower_r, tlu_flush_lower_r_d1;\n logic [31:1] tlu_flush_path_r, tlu_flush_path_r_d1;\n logic i0_valid_wb;\n logic tlu_i0_commit_cmt;\n logic [31:1] vectored_path, interrupt_path;\n logic [16:0] dicawics_ns, dicawics;\n logic wr_dicawics_r, wr_dicad0_r, wr_dicad1_r, wr_dicad0h_r;\n logic [31:0] dicad0_ns, dicad0, dicad0h_ns, dicad0h;\n\n logic [6:0] dicad1_ns, dicad1_raw;\n logic [31:0] dicad1;\n logic ebreak_r, ebreak_to_debug_mode_r, ecall_r, illegal_r, mret_r, inst_acc_r, fence_i_r,\n ic_perr_r, iccm_sbecc_r, ebreak_to_debug_mode_r_d1, kill_ebreak_count_r, inst_acc_second_r;\n logic ce_int_ready, ext_int_ready, timer_int_ready, soft_int_ready, int_timer0_int_ready, int_timer1_int_ready, mhwakeup_ready,\n take_ext_int, take_ce_int, take_timer_int, take_soft_int, take_int_timer0_int, take_int_timer1_int, take_nmi, take_nmi_r_d1, int_timer0_int_possible, int_timer1_int_possible;\n logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;\n logic synchronous_flush_r;\n logic [4:0] exc_cause_r, exc_cause_wb;\n logic mcyclel_cout, mcyclel_cout_f, mcyclela_cout;\n logic [31:0] mcyclel_inc;\n logic [31:0] mcycleh_inc;\n\n logic minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;\n\n logic [31:0] minstretl_inc, minstretl_read;\n logic [31:0] minstreth_inc, minstreth_read;\n logic [31:1] pc_r, pc_r_d1, npc_r, npc_r_d1;\n logic valid_csr;\n logic rfpc_i0_r;\n logic lsu_i0_rfnpc_r;\n logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;\n logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,\n lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;\n logic i0_trigger_eval_r;\n\n logic request_debug_mode_r, request_debug_mode_r_d1, request_debug_mode_done, request_debug_mode_done_f;\n logic take_halt, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset,\n dbg_tlu_halted, core_empty, lsu_idle_any_f, ifu_miss_state_idle_f, resume_ack_ns,\n debug_halt_req_f, debug_resume_req_f_raw, debug_resume_req_f, enter_debug_halt_req, dcsr_single_step_done, dcsr_single_step_done_f,\n debug_halt_req_d1, debug_halt_req_ns, dcsr_single_step_running, dcsr_single_step_running_f, internal_dbg_halt_timers;\n\n logic [3:0] i0_trigger_r, trigger_action, trigger_enabled,\n i0_trigger_chain_masked_r;\n logic i0_trigger_hit_r, i0_trigger_hit_raw_r, i0_trigger_action_r,\n trigger_hit_r_d1,\n mepc_trigger_hit_sel_pc_r;\n logic [3:0] update_hit_bit_r, i0_iside_trigger_has_pri_r,i0trigger_qual_r, i0_lsu_trigger_has_pri_r;\n logic cpu_halt_status, cpu_halt_ack, cpu_run_ack, ext_halt_pulse, i_cpu_halt_req_d1, i_cpu_run_req_d1;\n\n logic inst_acc_r_raw, trigger_hit_dmode_r, trigger_hit_dmode_r_d1;\n logic [9:0] mcgc, mcgc_ns, mcgc_int;\n logic [18:0] mfdc;\n logic i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, pmu_fw_halt_req_ns, pmu_fw_halt_req_f, int_timer_stalled,\n fw_halt_req, enter_pmu_fw_halt_req, pmu_fw_tlu_halted, pmu_fw_tlu_halted_f, internal_pmu_fw_halt_mode,\n internal_pmu_fw_halt_mode_f, int_timer0_int_hold, int_timer1_int_hold, int_timer0_int_hold_f, int_timer1_int_hold_f;\n logic nmi_int_delayed, nmi_int_detected;\n logic [3:0] trigger_execute, trigger_data, trigger_store;\n logic dec_tlu_pmu_fw_halted;\n\n logic mpc_run_state_ns, debug_brkpt_status_ns, mpc_debug_halt_ack_ns, mpc_debug_run_ack_ns, dbg_halt_state_ns, dbg_run_state_ns,\n dbg_halt_state_f, mpc_debug_halt_req_sync_f, mpc_debug_run_req_sync_f, mpc_halt_state_f, mpc_halt_state_ns, mpc_run_state_f, debug_brkpt_status_f,\n mpc_debug_halt_ack_f, mpc_debug_run_ack_f, dbg_run_state_f, mpc_debug_halt_req_sync_pulse,\n mpc_debug_run_req_sync_pulse, debug_brkpt_valid, debug_halt_req, debug_resume_req, dec_tlu_mpc_halted_only_ns;\n logic take_ext_int_start, ext_int_freeze, take_ext_int_start_d1, take_ext_int_start_d2,\n take_ext_int_start_d3, ext_int_freeze_d1, ignore_ext_int_due_to_lsu_stall;\n logic mcause_sel_nmi_store, mcause_sel_nmi_load, mcause_sel_nmi_ext, fast_int_meicpct;\n logic [1:0] mcause_fir_error_type;\n logic dbg_halt_req_held_ns, dbg_halt_req_held, dbg_halt_req_final;\n logic iccm_repair_state_ns, iccm_repair_state_d1, iccm_repair_state_rfnpc;\n\n\n // internal timer, isolated for size reasons\n logic [31:0] dec_timer_rddata_d;\n logic dec_timer_read_d, dec_timer_t0_pulse, dec_timer_t1_pulse;\n\n // PMP unit, isolated for size reasons\n logic [31:0] dec_pmp_rddata_d;\n logic dec_pmp_read_d;\n\n logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;\n logic csr_wr_clk;\n logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;\n logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;\n logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;\n logic lsu_single_ecc_error_r;\n logic [31:0] lsu_error_pkt_addr_r;\n logic mcyclel_cout_in;\n logic i0_valid_no_ebreak_ecall_r;\n logic minstret_enable_f;\n logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;\n logic pc0_valid_r;\n logic [15:0] mfdc_int, mfdc_ns;\n logic [31:0] mrac_in;\n logic [31:27] csr_sat;\n logic [8:6] dcsr_cause;\n logic enter_debug_halt_req_le, dcsr_cause_upgradeable;\n logic icache_rd_valid, icache_wr_valid, icache_rd_valid_f, icache_wr_valid_f;\n logic [3:0] mhpmc_inc_r, mhpmc_inc_r_d1;\n\n logic [3:0][9:0] mhpme_vec;\n logic mhpmc3_wr_en0, mhpmc3_wr_en1, mhpmc3_wr_en;\n logic mhpmc4_wr_en0, mhpmc4_wr_en1, mhpmc4_wr_en;\n logic mhpmc5_wr_en0, mhpmc5_wr_en1, mhpmc5_wr_en;\n logic mhpmc6_wr_en0, mhpmc6_wr_en1, mhpmc6_wr_en;\n logic mhpmc3h_wr_en0, mhpmc3h_wr_en;\n logic mhpmc4h_wr_en0, mhpmc4h_wr_en;\n logic mhpmc5h_wr_en0, mhpmc5h_wr_en;\n logic mhpmc6h_wr_en0, mhpmc6h_wr_en;\n logic [63:0] mhpmc3_incr, mhpmc4_incr, mhpmc5_incr, mhpmc6_incr;\n logic perfcnt_halted_d1, zero_event_r;\n logic [3:0] perfcnt_during_sleep;\n logic [9:0] event_r;\n\n el2_inst_pkt_t pmu_i0_itype_qual;\n\n logic dec_csr_wen_r_mod;\n\n logic flush_clkvalid;\n logic sel_fir_addr;\n logic wr_mie_r;\n logic mtval_capture_pc_r;\n logic mtval_capture_pc_plus2_r;\n logic mtval_capture_inst_r;\n logic mtval_capture_lsu_r;\n logic mtval_clear_r;\n logic wr_mcgc_r;\n logic wr_mfdc_r;\n logic wr_mdeau_r;\n logic trigger_hit_for_dscr_cause_r_d1;\n logic conditionally_illegal;\n\n logic [3:0] ifu_mscause ;\n logic ifu_ic_error_start_f, ifu_iccm_rd_ecc_single_err_f;\n\n // CSR address decoder\n\n// files \"csrdecode_m\" (machine mode only) and \"csrdecode_mu\" (machine mode plus\n// user mode) are human readable that have all of the CSR decodes defined and\n// are part of the git repo. Modify these files as needed.\n\n// to generate all the equations below from \"csrdecode\" except legal equation:\n\n// 1) coredecode -in csrdecode > corecsrdecode.e\n\n// 2) espresso -Dso -oeqntott < corecsrdecode.e | addassign > csrequations\n\n// to generate the legal CSR equation below:\n\n// 1) coredecode -in csrdecode -legal > csrlegal.e\n\n// 2) espresso -Dso -oeqntott < csrlegal.e | addassign > csrlegal_equation\n\n// coredecode -in csrdecode > corecsrdecode.e; espresso -Dso -oeqntott < corecsrdecode.e | addassign > csrequations; coredecode -in csrdecode -legal > csrlegal.e; espresso -Dso -oeqntott csrlegal.e | addassign > csrlegal_equation\n\n`ifdef RV_USER_MODE\n\n `include \"el2_dec_csr_equ_mu.svh\"\n\n logic csr_acc_r; // CSR access error\n logic csr_wr_usr_r; // Write to an unprivileged/user-level CSR\n logic csr_rd_usr_r; // REad from an unprivileged/user-level CSR\n\n`else\n\n `include \"el2_dec_csr_equ_m.svh\"\n\n`endif\n\n el2_dec_timer_ctl #(.pt(pt)) int_timers(.*);\n // end of internal timers\n\n el2_dec_pmp_ctl #(.pt(pt)) pmp(.*);\n // end of pmp\n\n assign clk_override = dec_tlu_dec_clk_override;\n\n // Async inputs to the core have to be sync'd to the core clock.\n rvsyncss #(7) syncro_ff(.*,\n .clk(free_clk),\n .din ({nmi_int, timer_int, soft_int, i_cpu_halt_req, i_cpu_run_req, mpc_debug_halt_req, mpc_debug_run_req}),\n .dout({nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync_raw, mpc_debug_run_req_sync}));\n\n // for CSRs that have inpipe writes only\n\n rvoclkhdr csrwr_r_cgc ( .en(dec_csr_wen_r_mod | clk_override), .l1clk(csr_wr_clk), .* );\n\n assign e4_valid = dec_tlu_i0_valid_r;\n assign e4e5_valid = e4_valid | e5_valid;\n assign flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 |\n reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | iccm_sbecc_r |\n clk_override;\n rvoclkhdr e4e5_cgc ( .en(e4e5_valid | clk_override), .l1clk(e4e5_clk), .* );\n rvoclkhdr e4e5_int_cgc ( .en(e4e5_valid | flush_clkvalid), .l1clk(e4e5_int_clk), .* );\n\n rvdffie #(11) freeff (.*, .clk(free_l2clk),\n .din ({ifu_ic_error_start, ifu_iccm_rd_ecc_single_err, iccm_repair_state_ns, e4_valid, internal_dbg_halt_mode,\n lsu_pmu_load_external_m, lsu_pmu_store_external_m, tlu_flush_lower_r, tlu_i0_kill_writeb_r,\n internal_dbg_halt_mode_f, force_halt}),\n .dout({ifu_ic_error_start_f, ifu_iccm_rd_ecc_single_err_f, iccm_repair_state_d1, e5_valid, internal_dbg_halt_mode_f,\n lsu_pmu_load_external_r, lsu_pmu_store_external_r, tlu_flush_lower_r_d1, dec_tlu_i0_kill_writeb_wb,\n internal_dbg_halt_mode_f2, dec_tlu_force_halt}));\n\n assign dec_tlu_i0_kill_writeb_r = tlu_i0_kill_writeb_r;\n\n assign nmi_int_detected = (nmi_int_sync & ~nmi_int_delayed) | nmi_lsu_detected | (nmi_int_detected_f & ~take_nmi_r_d1) | nmi_fir_type;\n // if the first nmi is a lsu type, note it. If there's already an nmi pending, ignore. Simultaneous with FIR, drop.\n assign nmi_lsu_load_type = (nmi_lsu_detected & lsu_imprecise_error_load_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) |\n (nmi_lsu_load_type_f & ~take_nmi_r_d1);\n assign nmi_lsu_store_type = (nmi_lsu_detected & lsu_imprecise_error_store_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) |\n (nmi_lsu_store_type_f & ~take_nmi_r_d1);\n\n assign nmi_fir_type = ~nmi_int_detected_f & take_ext_int_start_d3 & |lsu_fir_error[1:0];\n\n // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared\n assign nmi_lsu_detected = ~mdseac_locked_f & (lsu_imprecise_error_load_any | lsu_imprecise_error_store_any) & ~nmi_fir_type;\n\n\nlocalparam MSTATUS_MIE = 0;\nlocalparam int MSTATUS_MPIE = 1;\n`ifdef RV_USER_MODE\nlocalparam MSTATUS_MPP = 2;\nlocalparam MSTATUS_MPRV = 3;\n`endif\n\nlocalparam MIP_MCEIP = 5;\nlocalparam MIP_MITIP0 = 4;\nlocalparam MIP_MITIP1 = 3;\nlocalparam MIP_MEIP = 2;\nlocalparam MIP_MTIP = 1;\nlocalparam MIP_MSIP = 0;\n\nlocalparam MIE_MCEIE = 5;\nlocalparam MIE_MITIE0 = 4;\nlocalparam MIE_MITIE1 = 3;\nlocalparam MIE_MEIE = 2;\nlocalparam MIE_MTIE = 1;\nlocalparam MIE_MSIE = 0;\n\nlocalparam DCSR_EBREAKM = 15;\nlocalparam DCSR_STEPIE = 11;\nlocalparam DCSR_STOPC = 10;\nlocalparam DCSR_STEP = 2;\n\n`ifdef RV_USER_MODE\nlocalparam MCOUNTEREN_CY = 0;\nlocalparam MCOUNTEREN_IR = 1;\nlocalparam MCOUNTEREN_HPM3 = 2;\nlocalparam MCOUNTEREN_HPM4 = 3;\nlocalparam MCOUNTEREN_HPM5 = 4;\nlocalparam MCOUNTEREN_HPM6 = 5;\n\nlocalparam MSECCFG_RLB = 2;\nlocalparam MSECCFG_MMWP = 1;\nlocalparam MSECCFG_MML = 0;\n`endif\n\n // ----------------------------------------------------------------------\n // MISA (RO)\n // [31:30] XLEN - implementation width, 2'b01 - 32 bits\n // [20] U - user mode support (if enabled in config)\n // [12] M - integer mul/div\n // [8] I - RV32I\n // [2] C - Compressed extension\n localparam MISA = 12'h301;\n\n // MVENDORID, MARCHID, MIMPID, MHARTID\n localparam MVENDORID = 12'hf11;\n localparam MARCHID = 12'hf12;\n localparam MIMPID = 12'hf13;\n localparam MHARTID = 12'hf14;\n\n\n // ----------------------------------------------------------------------\n // MSTATUS (RW)\n // [17] MPRV : Modify PRiVilege (if enabled in config)\n // [12:11] MPP : Prior priv level, either 2'b11 (machine) or 2'b00 (user)\n // [7] MPIE : Int enable previous [1]\n // [3] MIE : Int enable [0]\n localparam MSTATUS = 12'h300;\n\n // ----------------------------------------------------------------------\n // MTVEC (RW)\n // [31:2] BASE : Trap vector base address\n // [1] - Reserved, not implemented, reads zero\n // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE)\n localparam MTVEC = 12'h305;\n\n // ----------------------------------------------------------------------\n // MIP (RW)\n //\n // [30] MCEIP : (RO) M-Mode Correctable Error interrupt pending\n // [29] MITIP0 : (RO) M-Mode Internal Timer0 interrupt pending\n // [28] MITIP1 : (RO) M-Mode Internal Timer1 interrupt pending\n // [11] MEIP : (RO) M-Mode external interrupt pending\n // [7] MTIP : (RO) M-Mode timer interrupt pending\n // [3] MSIP : (RO) M-Mode software interrupt pending\n localparam MIP = 12'h344;\n\n // ----------------------------------------------------------------------\n // MIE (RW)\n // [30] MCEIE : (RO) M-Mode Correctable Error interrupt enable\n // [29] MITIE0 : (RO) M-Mode Internal Timer0 interrupt enable\n // [28] MITIE1 : (RO) M-Mode Internal Timer1 interrupt enable\n // [11] MEIE : (RW) M-Mode external interrupt enable\n // [7] MTIE : (RW) M-Mode timer interrupt enable\n // [3] MSIE : (RW) M-Mode software interrupt enable\n localparam MIE = 12'h304;\n\n // ----------------------------------------------------------------------\n // MCYCLEL (RW)\n // [31:0] : Lower Cycle count\n\n localparam MCYCLEL = 12'hb00;\n localparam logic [11:0] CYCLEL = 12'hc00;\n\n // ----------------------------------------------------------------------\n // MCYCLEH (RW)\n // [63:32] : Higher Cycle count\n // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored.\n\n localparam MCYCLEH = 12'hb80;\n localparam logic [11:0] CYCLEH = 12'hc80;\n\n // ----------------------------------------------------------------------\n // MINSTRETL (RW)\n // [31:0] : Lower Instruction retired count\n // From the spec \"Some CSRs, such as the instructions retired counter, instret, may be modified as side effects\n // of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the\n // value prior to the execution of the instruction. If a CSR access instruction writes a CSR, the\n // update occurs after the execution of the instruction. In particular, a value written to instret by\n // one instruction will be the value read by the following instruction (i.e., the increment of instret\n // caused by the first instruction retiring happens before the write of the new value).\"\n localparam MINSTRETL = 12'hb02;\n localparam logic [11:0] INSTRETL = 12'hc02;\n\n // ----------------------------------------------------------------------\n // MINSTRETH (RW)\n // [63:32] : Higher Instret count\n // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored.\n\n localparam MINSTRETH = 12'hb82;\n localparam logic [11:0] INSTRETH = 12'hc82;\n\n // ----------------------------------------------------------------------\n // MSCRATCH (RW)\n // [31:0] : Scratch register\n localparam MSCRATCH = 12'h340;\n\n // ----------------------------------------------------------------------\n // MEPC (RW)\n // [31:1] : Exception PC\n localparam MEPC = 12'h341;\n\n // ----------------------------------------------------------------------\n // MCAUSE (RW)\n // [31:0] : Exception Cause\n localparam MCAUSE = 12'h342;\n\n // ----------------------------------------------------------------------\n // MSCAUSE (RW)\n // [2:0] : Secondary exception Cause\n localparam MSCAUSE = 12'h7ff;\n\n // ----------------------------------------------------------------------\n // MTVAL (RW)\n // [31:0] : Exception address if relevant\n localparam MTVAL = 12'h343;\n\n // ----------------------------------------------------------------------\n // MCGC (RW) Clock gating control\n // [31:10]: Reserved, reads 0x0\n // [9] : picio_clk_override\n // [7] : dec_clk_override\n // [6] : Unused\n // [5] : ifu_clk_override\n // [4] : lsu_clk_override\n // [3] : bus_clk_override\n // [2] : pic_clk_override\n // [1] : dccm_clk_override\n // [0] : icm_clk_override\n //\n localparam MCGC = 12'h7f8;\n\n // ----------------------------------------------------------------------\n // MFDC (RW) Feature Disable Control\n // [31:19] : Reserved, reads 0x0\n // [18:16] : DMA QoS Prty\n // [15:13] : Reserved, reads 0x0\n // [12] : Disable trace\n // [11] : Disable external load forwarding\n // [10] : Disable dual issue\n // [9] : Disable pic multiple ints\n // [8] : Disable core ecc\n // [7] : Disable secondary alu?s\n // [6] : Unused, 0x0\n // [5] : Disable non-blocking loads/divides\n // [4] : Disable fast divide\n // [3] : Disable branch prediction and return stack\n // [2] : Disable write buffer coalescing\n // [1] : Disable load misses that bypass the write buffer\n // [0] : Disable pipelining - Enable single instruction execution\n //\n localparam MFDC = 12'h7f9;\n\n // ----------------------------------------------------------------------\n // MRAC (RW)\n // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs\n localparam MRAC = 12'h7c0;\n\n // ----------------------------------------------------------------------\n // MDEAU (WAR0)\n // [31:0] : Dbus Error Address Unlock register\n //\n localparam MDEAU = 12'hbc0;\n\n // ----------------------------------------------------------------------\n // MDSEAC (R)\n // [31:0] : Dbus Store Error Address Capture register\n //\n localparam MDSEAC = 12'hfc0;\n\n // ----------------------------------------------------------------------\n // MPMC (R0W1)\n // [0] : FW halt\n // [1] : Set MSTATUS[MIE] on halt\n localparam MPMC = 12'h7c6;\n\n // ----------------------------------------------------------------------\n // MICECT (I-Cache error counter/threshold)\n // [31:27] : Icache parity error threshold\n // [26:0] : Icache parity error count\n localparam MICECT = 12'h7f0;\n\n // ----------------------------------------------------------------------\n // MICCMECT (ICCM error counter/threshold)\n // [31:27] : ICCM parity error threshold\n // [26:0] : ICCM parity error count\n localparam MICCMECT = 12'h7f1;\n\n // ----------------------------------------------------------------------\n // MDCCMECT (DCCM error counter/threshold)\n // [31:27] : DCCM parity error threshold\n // [26:0] : DCCM parity error count\n localparam MDCCMECT = 12'h7f2;\n\n // ----------------------------------------------------------------------\n // MFDHT (Force Debug Halt Threshold)\n // [5:1] : Halt timeout threshold (power of 2)\n // [0] : Halt timeout enabled\n localparam MFDHT = 12'h7ce;\n\n // ----------------------------------------------------------------------\n // MFDHS(RW)\n // [1] : LSU operation pending when debug halt threshold reached\n // [0] : IFU operation pending when debug halt threshold reached\n localparam MFDHS = 12'h7cf;\n\n // ----------------------------------------------------------------------\n // MEIVT (External Interrupt Vector Table (R/W))\n // [31:10]: Base address (R/W)\n // [9:0] : Reserved, reads 0x0\n localparam MEIVT = 12'hbc8;\n\n // ----------------------------------------------------------------------\n // MEICURPL (R/W)\n // [31:4] : Reserved (read 0x0)\n // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W)\n localparam MEICURPL = 12'hbcc;\n\n // ----------------------------------------------------------------------\n // MEICIDPL (R/W)\n // [31:4] : Reserved (read 0x0)\n // [3:0] : External Interrupt Claim ID's Priority Level Register\n localparam MEICIDPL = 12'hbcb;\n\n // ----------------------------------------------------------------------\n // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL\n // [31:1] : Reserved (read 0x0)\n // [0] : Capture (W1, Read 0)\n localparam MEICPCT = 12'hbca;\n\n // ----------------------------------------------------------------------\n // MEIPT (External Interrupt Priority Threshold)\n // [31:4] : Reserved (read 0x0)\n // [3:0] : PRITHRESH\n localparam MEIPT = 12'hbc9;\n\n // ----------------------------------------------------------------------\n // DCSR (R/W) (Only accessible in debug mode)\n // [31:28] : xdebugver (hard coded to 0x4) RO\n // [27:16] : 0x0, reserved\n // [15] : ebreakm\n // [14] : 0x0, reserved\n // [13] : ebreaks (0x0 for this core)\n // [12] : ebreaku (0x0 for this core)\n // [11] : stepie\n // [10] : stopcount\n // [9] : 0x0 //stoptime\n // [8:6] : cause (RO)\n // [5:4] : 0x0, reserved\n // [3] : nmip\n // [2] : step\n // [1:0] : prv (0x3 for this core)\n //\n localparam DCSR = 12'h7b0;\n\n // ----------------------------------------------------------------------\n // DPC (R/W) (Only accessible in debug mode)\n // [31:0] : Debug PC\n localparam DPC = 12'h7b1;\n\n // ----------------------------------------------------------------------\n // DICAWICS (R/W) (Only accessible in debug mode)\n // [31:25] : Reserved\n // [24] : Array select, 0 is data, 1 is tag\n // [23:22] : Reserved\n // [21:20] : Way select\n // [19:17] : Reserved\n // [16:3] : Index\n // [2:0] : Reserved\n localparam DICAWICS = 12'h7c8;\n\n // ----------------------------------------------------------------------\n // DICAD0 (R/W) (Only accessible in debug mode)\n //\n // If dicawics[array] is 0\n // [31:0] : inst data\n //\n // If dicawics[array] is 1\n // [31:16] : Tag\n // [15:7] : Reserved\n // [6:4] : LRU\n // [3:1] : Reserved\n // [0] : Valid\n localparam DICAD0 = 12'h7c9;\n\n // ----------------------------------------------------------------------\n // DICAD0H (R/W) (Only accessible in debug mode)\n //\n // If dicawics[array] is 0\n // [63:32] : inst data\n //\n localparam DICAD0H = 12'h7cc;\n\n // ----------------------------------------------------------------------\n // DICAGO (R/W) (Only accessible in debug mode)\n // [0] : Go\n localparam DICAGO = 12'h7cb;\n\n // ----------------------------------------------------------------------\n // MHPMC3H(RW), MHPMC3(RW)\n // [63:32][31:0] : Hardware Performance Monitor Counter 3\n localparam MHPMC3 = 12'hB03;\n localparam MHPMC3H = 12'hB83;\n`ifdef RV_USER_MODE\n localparam HPMC3 = 12'hC03;\n localparam HPMC3H = 12'hC83;\n`endif\n\n // ----------------------------------------------------------------------\n // MHPMC4H(RW), MHPMC4(RW)\n // [63:32][31:0] : Hardware Performance Monitor Counter 4\n localparam MHPMC4 = 12'hB04;\n localparam MHPMC4H = 12'hB84;\n`ifdef RV_USER_MODE\n localparam HPMC4 = 12'hC04;\n localparam HPMC4H = 12'hC84;\n`endif\n\n // ----------------------------------------------------------------------\n // MHPMC5H(RW), MHPMC5(RW)\n // [63:32][31:0] : Hardware Performance Monitor Counter 5\n localparam MHPMC5 = 12'hB05;\n localparam MHPMC5H = 12'hB85;\n`ifdef RV_USER_MODE\n localparam HPMC5 = 12'hC05;\n localparam HPMC5H = 12'hC85;\n`endif\n\n // ----------------------------------------------------------------------\n // MHPMC6H(RW), MHPMC6(RW)\n // [63:32][31:0] : Hardware Performance Monitor Counter 6\n localparam MHPMC6 = 12'hB06;\n localparam MHPMC6H = 12'hB86;\n`ifdef RV_USER_MODE\n localparam HPMC6 = 12'hC06;\n localparam HPMC6H = 12'hC86;\n`endif\n\n // ----------------------------------------------------------------------\n // MHPME3(RW)\n // [9:0] : Hardware Performance Monitor Event 3\n localparam MHPME3 = 12'h323;\n\n // ----------------------------------------------------------------------\n // MHPME4(RW)\n // [9:0] : Hardware Performance Monitor Event 4\n localparam MHPME4 = 12'h324;\n\n // ----------------------------------------------------------------------\n // MHPME5(RW)\n // [9:0] : Hardware Performance Monitor Event 5\n localparam MHPME5 = 12'h325;\n\n // ----------------------------------------------------------------------\n // MHPME6(RW)\n // [9:0] : Hardware Performance Monitor Event 6\n localparam MHPME6 = 12'h326;\n\n // MCOUNTINHIBIT(RW)\n // [31:7] : Reserved, read 0x0\n // [6] : HPM6 disable\n // [5] : HPM5 disable\n // [4] : HPM4 disable\n // [3] : HPM3 disable\n // [2] : MINSTRET disable\n // [1] : reserved, read 0x0\n // [0] : MCYCLE disable\n\n localparam MCOUNTINHIBIT = 12'h320;\n\n // ----------------------------------------------------------------------\n // MTSEL (R/W)\n // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count\n localparam MTSEL = 12'h7a0;\n\n // ----------------------------------------------------------------------\n // MTDATA1 (R/W)\n // [31:0] : Trigger Data 1\n localparam MTDATA1 = 12'h7a1;\n\n // ----------------------------------------------------------------------\n // MTDATA2 (R/W)\n // [31:0] : Trigger Data 2\n localparam MTDATA2 = 12'h7a2;\n\n assign reset_delayed = reset_detect ^ reset_detected;\n\n // ----------------------------------------------------------------------\n // MPC halt\n // - can interact with debugger halt and v-v\n\n // fast ints in progress have priority\n assign mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1;\n\n rvdffie #(16) mpvhalt_ff (.*, .clk(free_l2clk),\n .din({1'b1, reset_detect,\n nmi_int_sync, nmi_int_detected, nmi_lsu_load_type, nmi_lsu_store_type,\n mpc_debug_halt_req_sync, mpc_debug_run_req_sync,\n mpc_halt_state_ns, mpc_run_state_ns, debug_brkpt_status_ns,\n mpc_debug_halt_ack_ns, mpc_debug_run_ack_ns,\n dbg_halt_state_ns, dbg_run_state_ns,\n dec_tlu_mpc_halted_only_ns}),\n .dout({reset_detect, reset_detected,\n nmi_int_delayed, nmi_int_detected_f, nmi_lsu_load_type_f, nmi_lsu_store_type_f,\n mpc_debug_halt_req_sync_f, mpc_debug_run_req_sync_f,\n mpc_halt_state_f, mpc_run_state_f, debug_brkpt_status_f,\n mpc_debug_halt_ack_f, mpc_debug_run_ack_f,\n dbg_halt_state_f, dbg_run_state_f,\n dec_tlu_mpc_halted_only}));\n\n // turn level sensitive requests into pulses\n assign mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & ~mpc_debug_halt_req_sync_f;\n assign mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & ~mpc_debug_run_req_sync_f;\n\n // states\n assign mpc_halt_state_ns = (mpc_halt_state_f | mpc_debug_halt_req_sync_pulse | (reset_delayed & ~mpc_reset_run_req)) & ~mpc_debug_run_req_sync;\n assign mpc_run_state_ns = (mpc_run_state_f | (mpc_debug_run_req_sync_pulse & ~mpc_debug_run_ack_f)) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f);\n\n // note, MPC halt can allow the jtag debugger to just start sending commands. When that happens, set the interal debugger halt state to prevent\n // MPC run from starting the core.\n assign dbg_halt_state_ns = (dbg_halt_state_f | (dbg_halt_req_final | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1)) & ~dbg_resume_req;\n assign dbg_run_state_ns = (dbg_run_state_f | dbg_resume_req) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f);\n\n // tell dbg we are only MPC halted\n assign dec_tlu_mpc_halted_only_ns = ~dbg_halt_state_f & mpc_halt_state_f;\n\n // this asserts from detection of bkpt until after we leave debug mode\n assign debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1;\n assign debug_brkpt_status_ns = (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f);\n\n // acks back to interface\n assign mpc_debug_halt_ack_ns = (mpc_halt_state_f & internal_dbg_halt_mode_f & mpc_debug_halt_req_sync & core_empty) | (mpc_debug_halt_ack_f & mpc_debug_halt_req_sync);\n assign mpc_debug_run_ack_ns = (mpc_debug_run_req_sync & ~internal_dbg_halt_mode & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync) ;\n\n // Pins\n assign mpc_debug_halt_ack = mpc_debug_halt_ack_f;\n assign mpc_debug_run_ack = mpc_debug_run_ack_f;\n assign debug_brkpt_status = debug_brkpt_status_f;\n\n // DBG halt req is a pulse, fast ext int in progress has priority\n assign dbg_halt_req_held_ns = (dbg_halt_req | dbg_halt_req_held) & ext_int_freeze_d1;\n assign dbg_halt_req_final = (dbg_halt_req | dbg_halt_req_held) & ~ext_int_freeze_d1;\n\n // combine MPC and DBG halt requests\n assign debug_halt_req = (dbg_halt_req_final | mpc_debug_halt_req_sync | (reset_delayed & ~mpc_reset_run_req)) & ~internal_dbg_halt_mode_f & ~ext_int_freeze_d1;\n\n assign debug_resume_req = ~debug_resume_req_f & // squash back to back resumes\n ((mpc_run_state_ns & ~dbg_halt_state_ns) | // MPC run req\n (dbg_run_state_ns & ~mpc_halt_state_ns)); // dbg request is a pulse\n\n\n // HALT\n // dbg/pmu/fw requests halt, service as soon as lsu is not blocking interrupts\n assign take_halt = (debug_halt_req_f | pmu_fw_halt_req_f) & ~synchronous_flush_r & ~mret_r & ~halt_taken_f & ~dec_tlu_flush_noredir_r_d1 & ~take_reset;\n\n // hold after we take a halt, so we don't keep taking halts\n assign halt_taken = (dec_tlu_flush_noredir_r_d1 & ~dec_tlu_flush_pause_r_d1 & ~take_ext_int_start_d1) | (halt_taken_f & ~dbg_tlu_halted_f & ~pmu_fw_tlu_halted_f & ~interrupt_valid_r_d1);\n\n // After doing halt flush (RFNPC) wait until core is idle before asserting a particular halt mode\n // It takes a cycle for mb_empty to assert after a fetch, take_halt covers that cycle\n assign core_empty = force_halt |\n (lsu_idle_any & lsu_idle_any_f & ifu_miss_state_idle & ifu_miss_state_idle_f & ~debug_halt_req & ~debug_halt_req_d1 & ~dec_div_active);\n\n assign dec_tlu_core_empty = core_empty;\n\n//--------------------------------------------------------------------------------\n// Debug start\n//\n\n assign enter_debug_halt_req = (~internal_dbg_halt_mode_f & debug_halt_req) | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1;\n\n // dbg halt state active from request until non-step resume\n assign internal_dbg_halt_mode = debug_halt_req_ns | (internal_dbg_halt_mode_f & ~(debug_resume_req_f & ~dcsr[DCSR_STEP]));\n // dbg halt can access csrs as long as we are not stepping\n assign allow_dbg_halt_csr_write = internal_dbg_halt_mode_f & ~dcsr_single_step_running_f;\n\n\n // hold debug_halt_req_ns high until we enter debug halt\n assign debug_halt_req_ns = enter_debug_halt_req | (debug_halt_req_f & ~dbg_tlu_halted);\n\n assign dbg_tlu_halted = (debug_halt_req_f & core_empty & halt_taken) | (dbg_tlu_halted_f & ~debug_resume_req_f);\n\n assign resume_ack_ns = (debug_resume_req_f & dbg_tlu_halted_f & dbg_run_state_ns);\n\n assign dcsr_single_step_done = dec_tlu_i0_valid_r & ~dec_tlu_dbg_halted & dcsr[DCSR_STEP] & ~rfpc_i0_r;\n\n assign dcsr_single_step_running = (debug_resume_req_f & dcsr[DCSR_STEP]) | (dcsr_single_step_running_f & ~dcsr_single_step_done_f);\n\n assign dbg_cmd_done_ns = dec_tlu_i0_valid_r & dec_tlu_dbg_halted;\n\n // used to hold off commits after an in-pipe debug mode request (triggers, DCSR)\n assign request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~dec_tlu_flush_lower_wb);\n\n assign request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f;\n\n rvdffie #(18) halt_ff (.*, .clk(free_l2clk),\n .din({dec_tlu_flush_noredir_r, halt_taken, lsu_idle_any, ifu_miss_state_idle, dbg_tlu_halted,\n resume_ack_ns, debug_halt_req_ns, debug_resume_req, trigger_hit_dmode_r,\n dcsr_single_step_done, debug_halt_req, dec_tlu_wr_pause_r, dec_pause_state,\n request_debug_mode_r, request_debug_mode_done, dcsr_single_step_running, dec_tlu_flush_pause_r,\n dbg_halt_req_held_ns}),\n .dout({dec_tlu_flush_noredir_r_d1, halt_taken_f, lsu_idle_any_f, ifu_miss_state_idle_f, dbg_tlu_halted_f,\n dec_tlu_resume_ack , debug_halt_req_f, debug_resume_req_f_raw, trigger_hit_dmode_r_d1,\n dcsr_single_step_done_f, debug_halt_req_d1, dec_tlu_wr_pause_r_d1, dec_pause_state_f,\n request_debug_mode_r_d1, request_debug_mode_done_f, dcsr_single_step_running_f, dec_tlu_flush_pause_r_d1,\n dbg_halt_req_held}));\n\n // MPC run collides with DBG halt, fix it here\n assign debug_resume_req_f = debug_resume_req_f_raw & ~dbg_halt_req;\n\n assign dec_tlu_debug_stall = debug_halt_req_f;\n assign dec_tlu_dbg_halted = dbg_tlu_halted_f;\n assign dec_tlu_debug_mode = internal_dbg_halt_mode_f;\n assign dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f;\n\n // kill fetch redirection on flush if going to halt, or if there's a fence during db-halt\n assign dec_tlu_flush_noredir_r = take_halt | (fence_i_r & internal_dbg_halt_mode) | dec_tlu_flush_pause_r | (i0_trigger_hit_r & trigger_hit_dmode_r) | take_ext_int_start;\n\n assign dec_tlu_flush_extint = take_ext_int_start;\n\n // 1 cycle after writing the PAUSE counter, flush with noredir to idle F1-D.\n assign dec_tlu_flush_pause_r = dec_tlu_wr_pause_r_d1 & ~interrupt_valid_r & ~take_ext_int_start;\n\n // detect end of pause counter and rfpc\n assign pause_expired_r = ~dec_pause_state & dec_pause_state_f & ~(ext_int_ready | ce_int_ready | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | nmi_int_detected | ext_int_freeze_d1) & ~interrupt_valid_r_d1 & ~debug_halt_req_f & ~pmu_fw_halt_req_f & ~halt_taken_f;\n\n assign dec_tlu_flush_leak_one_r = dec_tlu_flush_lower_r & dcsr[DCSR_STEP] & (dec_tlu_resume_ack | dcsr_single_step_running) & ~dec_tlu_flush_noredir_r;\n assign dec_tlu_flush_err_r = dec_tlu_flush_lower_r & (ic_perr_r | iccm_sbecc_r);\n\n // If DM attempts to access an illegal CSR, send cmd_fail back\n assign dec_dbg_cmd_done = dbg_cmd_done_ns;\n assign dec_dbg_cmd_fail = illegal_r & dec_dbg_cmd_done;\n\n\n //--------------------------------------------------------------------------------\n //--------------------------------------------------------------------------------\n // Triggers\n //\nlocalparam MTDATA1_DMODE = 9;\nlocalparam MTDATA1_SEL = 7;\nlocalparam MTDATA1_ACTION = 6;\nlocalparam MTDATA1_CHAIN = 5;\nlocalparam MTDATA1_MATCH = 4;\nlocalparam MTDATA1_M_ENABLED = 3;\nlocalparam MTDATA1_EXE = 2;\nlocalparam MTDATA1_ST = 1;\nlocalparam MTDATA1_LD = 0;\n\n // Prioritize trigger hits with other exceptions.\n //\n // Trigger should have highest priority except:\n // - trigger is an execute-data and there is an inst_access exception (lsu triggers won't fire, inst. is nop'd by decode)\n // - trigger is a store-data and there is a lsu_acc_exc or lsu_ma_exc.\n assign trigger_execute[3:0] = {mtdata1_t3[MTDATA1_EXE], mtdata1_t2[MTDATA1_EXE], mtdata1_t1[MTDATA1_EXE], mtdata1_t0[MTDATA1_EXE]};\n assign trigger_data[3:0] = {mtdata1_t3[MTDATA1_SEL], mtdata1_t2[MTDATA1_SEL], mtdata1_t1[MTDATA1_SEL], mtdata1_t0[MTDATA1_SEL]};\n assign trigger_store[3:0] = {mtdata1_t3[MTDATA1_ST], mtdata1_t2[MTDATA1_ST], mtdata1_t1[MTDATA1_ST], mtdata1_t0[MTDATA1_ST]};\n\n // MSTATUS[MIE] needs to be on to take triggers unless the action is trigger to debug mode.\n assign trigger_enabled[3:0] = {(mtdata1_t3[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t3[MTDATA1_M_ENABLED],\n (mtdata1_t2[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t2[MTDATA1_M_ENABLED],\n (mtdata1_t1[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t1[MTDATA1_M_ENABLED],\n (mtdata1_t0[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t0[MTDATA1_M_ENABLED]};\n\n // iside exceptions are always in i0\n assign i0_iside_trigger_has_pri_r[3:0] = ~( (trigger_execute[3:0] & trigger_data[3:0] & {4{inst_acc_r_raw}}) | // exe-data with inst_acc\n ({4{exu_i0_br_error_r | exu_i0_br_start_error_r}})); // branch error in i0\n\n // lsu excs have to line up with their respective triggers since the lsu op can be i0\n assign i0_lsu_trigger_has_pri_r[3:0] = ~(trigger_store[3:0] & trigger_data[3:0] & {4{lsu_i0_exc_r_raw}});\n\n // trigger hits have to be eval'd to cancel side effect lsu ops even though the pipe is already frozen\n assign i0_trigger_eval_r = dec_tlu_i0_valid_r;\n\n assign i0trigger_qual_r[3:0] = {4{i0_trigger_eval_r}} & dec_tlu_packet_r.i0trigger[3:0] & i0_iside_trigger_has_pri_r[3:0] & i0_lsu_trigger_has_pri_r[3:0] & trigger_enabled[3:0];\n\n // Qual trigger hits\n assign i0_trigger_r[3:0] = ~{4{dec_tlu_flush_lower_wb | dec_tlu_dbg_halted}} & i0trigger_qual_r[3:0];\n\n // chaining can mask raw trigger info\n assign i0_trigger_chain_masked_r[3:0] = {i0_trigger_r[3] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[2]),\n i0_trigger_r[2] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[3]),\n i0_trigger_r[1] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[0]),\n i0_trigger_r[0] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[1])};\n\n // This is the highest priority by this point.\n assign i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r[3:0];\n\n assign i0_trigger_hit_r = i0_trigger_hit_raw_r;\n\n // Actions include breakpoint, or dmode. Dmode is only possible if the DMODE bit is set.\n // Otherwise, take a breakpoint.\n assign trigger_action[3:0] = {mtdata1_t3[MTDATA1_ACTION] & mtdata1_t3[MTDATA1_DMODE],\n mtdata1_t2[MTDATA1_ACTION] & mtdata1_t2[MTDATA1_DMODE] & ~mtdata1_t2[MTDATA1_CHAIN],\n mtdata1_t1[MTDATA1_ACTION] & mtdata1_t1[MTDATA1_DMODE],\n mtdata1_t0[MTDATA1_ACTION] & mtdata1_t0[MTDATA1_DMODE] & ~mtdata1_t0[MTDATA1_CHAIN]};\n\n // this is needed to set the HIT bit in the triggers\n assign update_hit_bit_r[3:0] = ({4{|i0_trigger_r[3:0] & ~rfpc_i0_r}} & {i0_trigger_chain_masked_r[3], i0_trigger_r[2], i0_trigger_chain_masked_r[1], i0_trigger_r[0]});\n\n // action, 1 means dmode. Simultaneous triggers with at least 1 set for dmode force entire action to dmode.\n assign i0_trigger_action_r = |(i0_trigger_chain_masked_r[3:0] & trigger_action[3:0]);\n\n assign trigger_hit_dmode_r = (i0_trigger_hit_r & i0_trigger_action_r);\n\n assign mepc_trigger_hit_sel_pc_r = i0_trigger_hit_r & ~trigger_hit_dmode_r;\n\n\n//\n// Debug end\n//--------------------------------------------------------------------------------\n\n //----------------------------------------------------------------------\n //\n // Commit\n //\n //----------------------------------------------------------------------\n\n\n\n //--------------------------------------------------------------------------------\n // External halt (not debug halt)\n // - Fully interlocked handshake\n // i_cpu_halt_req ____|--------------|_______________\n // core_empty ---------------|___________\n // o_cpu_halt_ack _________________|----|__________\n // o_cpu_halt_status _______________|---------------------|_________\n // i_cpu_run_req ______|----------|____\n // o_cpu_run_ack ____________|------|________\n //\n\n\n // debug mode has priority, ignore PMU/FW halt/run while in debug mode\n assign i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~dec_tlu_debug_mode & ~ext_int_freeze_d1;\n assign i_cpu_run_req_sync_qual = i_cpu_run_req_sync & ~dec_tlu_debug_mode & pmu_fw_tlu_halted_f & ~ext_int_freeze_d1;\n\n rvdffie #(10) exthaltff (.*, .clk(free_l2clk), .din({i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, cpu_halt_status,\n cpu_halt_ack, cpu_run_ack, internal_pmu_fw_halt_mode,\n pmu_fw_halt_req_ns, pmu_fw_tlu_halted,\n int_timer0_int_hold, int_timer1_int_hold}),\n .dout({i_cpu_halt_req_d1, i_cpu_run_req_d1_raw, o_cpu_halt_status,\n o_cpu_halt_ack, o_cpu_run_ack, internal_pmu_fw_halt_mode_f,\n pmu_fw_halt_req_f, pmu_fw_tlu_halted_f,\n int_timer0_int_hold_f, int_timer1_int_hold_f}));\n\n // only happens if we aren't in dgb_halt\n assign ext_halt_pulse = i_cpu_halt_req_sync_qual & ~i_cpu_halt_req_d1;\n\n assign enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req;\n\n assign pmu_fw_halt_req_ns = (enter_pmu_fw_halt_req | (pmu_fw_halt_req_f & ~pmu_fw_tlu_halted)) & ~debug_halt_req_f;\n\n assign internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | (internal_pmu_fw_halt_mode_f & ~i_cpu_run_req_d1 & ~debug_halt_req_f);\n\n // debug halt has priority\n assign pmu_fw_tlu_halted = ((pmu_fw_halt_req_f & core_empty & halt_taken & ~enter_debug_halt_req) | (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1)) & ~debug_halt_req_f;\n\n assign cpu_halt_ack = (i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f) | (o_cpu_halt_ack & i_cpu_halt_req_sync);\n assign cpu_halt_status = (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1) | (o_cpu_halt_status & ~i_cpu_run_req_d1 & ~internal_dbg_halt_mode_f);\n assign cpu_run_ack = (~pmu_fw_tlu_halted_f & i_cpu_run_req_sync) | (o_cpu_halt_status & i_cpu_run_req_d1_raw) | (o_cpu_run_ack & i_cpu_run_req_sync);\n assign debug_mode_status = internal_dbg_halt_mode_f;\n assign o_debug_mode_status = debug_mode_status;\n\n`ifdef RV_ASSERT_ON\n assert_commit_while_halted: assert #0 (~(tlu_i0_commit_cmt & o_cpu_halt_status)) else $display(\"ERROR: Commiting while cpu_halt_status asserted!\");\n assert_flush_while_fastint: assert #0 (~((take_ext_int_start_d1 | take_ext_int_start_d2) & dec_tlu_flush_lower_r)) else $display(\"ERROR: TLU Flushing inside fast interrupt procedure!\");\n`endif\n\n // high priority interrupts can wakeup from external halt, so can unmasked timer interrupts\n assign i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (mhwakeup & mhwakeup_ready)) & o_cpu_halt_status & ~i_cpu_halt_req_d1);\n\n //--------------------------------------------------------------------------------\n //--------------------------------------------------------------------------------\n\n assign lsu_single_ecc_error_r = lsu_single_ecc_error_incr;\n\n assign lsu_error_pkt_addr_r[31:0] = lsu_error_pkt_r.addr[31:0];\n\n\n assign lsu_exc_valid_r_raw = lsu_error_pkt_r.exc_valid & ~dec_tlu_flush_lower_wb;\n\n assign lsu_i0_exc_r_raw = lsu_error_pkt_r.exc_valid;\n\n assign lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r;\n\n assign lsu_exc_valid_r = lsu_i0_exc_r;\n\n assign lsu_exc_ma_r = lsu_i0_exc_r & ~lsu_error_pkt_r.exc_type;\n assign lsu_exc_acc_r = lsu_i0_exc_r & lsu_error_pkt_r.exc_type;\n assign lsu_exc_st_r = lsu_i0_exc_r & lsu_error_pkt_r.inst_type;\n\n // Single bit ECC errors on loads are RFNPC corrected, with the corrected data written to the GPR.\n // LSU turns the load into a store and patches the data in the DCCM\n assign lsu_i0_rfnpc_r = dec_tlu_i0_valid_r & ~i0_trigger_hit_r &\n (~lsu_error_pkt_r.inst_type & lsu_error_pkt_r.single_ecc_error);\n\n // Final commit valids\n`ifdef RV_USER_MODE\n assign tlu_i0_commit_cmt = dec_tlu_i0_valid_r &\n ~rfpc_i0_r &\n ~lsu_i0_exc_r &\n ~inst_acc_r &\n ~dec_tlu_dbg_halted &\n ~request_debug_mode_r_d1 &\n ~i0_trigger_hit_r &\n ~csr_acc_r;\n`else\n assign tlu_i0_commit_cmt = dec_tlu_i0_valid_r &\n ~rfpc_i0_r &\n ~lsu_i0_exc_r &\n ~inst_acc_r &\n ~dec_tlu_dbg_halted &\n ~request_debug_mode_r_d1 &\n ~i0_trigger_hit_r;\n`endif\n\n // unified place to manage the killing of arch state writebacks\n`ifdef RV_USER_MODE\n assign tlu_i0_kill_writeb_r = rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & dec_tlu_dbg_halted) | i0_trigger_hit_r | csr_acc_r;\n`else\n assign tlu_i0_kill_writeb_r = rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & dec_tlu_dbg_halted) | i0_trigger_hit_r;\n`endif\n assign dec_tlu_i0_commit_cmt = tlu_i0_commit_cmt;\n\n\n // refetch PC, microarch flush\n // ic errors only in pipe0\n assign rfpc_i0_r = ((dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (exu_i0_br_error_r | exu_i0_br_start_error_r)) | // inst commit with rfpc\n ((ic_perr_r | iccm_sbecc_r) & ~ext_int_freeze_d1)) & // ic/iccm without inst commit\n ~i0_trigger_hit_r & // unless there's a trigger. Err signal to ic/iccm will assert anyway to clear the error.\n ~lsu_i0_rfnpc_r;\n\n // From the indication of a iccm single bit error until the first commit or flush, maintain a repair state. In the repair state, rfnpc i0 commits.\n assign iccm_repair_state_ns = iccm_sbecc_r | (iccm_repair_state_d1 & ~dec_tlu_flush_lower_r);\n\n\n localparam MCPC = 12'h7c2;\n\n // this is a flush of last resort, meaning only assert it if there is no other flush happening.\n assign iccm_repair_state_rfnpc = tlu_i0_commit_cmt & iccm_repair_state_d1 &\n ~(ebreak_r | ecall_r | mret_r | take_reset | illegal_r | (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC)));\n\nif(pt.BTB_ENABLE==1) begin\n // go ahead and repair the branch error on other flushes, doesn't have to be the rfpc flush\n assign dec_tlu_br0_error_r = exu_i0_br_error_r & dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1;\n assign dec_tlu_br0_start_error_r = exu_i0_br_start_error_r & dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1;\n assign dec_tlu_br0_v_r = exu_i0_br_valid_r & dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~exu_i0_br_mp_r | ~exu_pmu_i0_br_ataken);\n\n\n assign dec_tlu_br0_r_pkt.hist[1:0] = exu_i0_br_hist_r[1:0];\n assign dec_tlu_br0_r_pkt.br_error = dec_tlu_br0_error_r;\n assign dec_tlu_br0_r_pkt.br_start_error = dec_tlu_br0_start_error_r;\n assign dec_tlu_br0_r_pkt.valid = dec_tlu_br0_v_r;\n assign dec_tlu_br0_r_pkt.way = exu_i0_br_way_r;\n assign dec_tlu_br0_r_pkt.middle = exu_i0_br_middle_r;\nend // if (pt.BTB_ENABLE==1)\nelse begin\n assign dec_tlu_br0_error_r = '0;\n assign dec_tlu_br0_start_error_r = '0;\n assign dec_tlu_br0_v_r = '0;\n assign dec_tlu_br0_r_pkt = '0;\nend // else: !if(pt.BTB_ENABLE==1)\n\n\n // only expect these in pipe 0\n assign ebreak_r = (dec_tlu_packet_r.pmu_i0_itype == EBREAK) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr[DCSR_EBREAKM] & ~rfpc_i0_r;\n assign ecall_r = (dec_tlu_packet_r.pmu_i0_itype == ECALL) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;\n`ifdef RV_USER_MODE\n assign illegal_r = (((dec_tlu_packet_r.pmu_i0_itype == MRET) & priv_mode) | ~dec_tlu_packet_r.legal) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;\n assign mret_r = ( (dec_tlu_packet_r.pmu_i0_itype == MRET) & ~priv_mode ) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;\n`else\n assign illegal_r = ~dec_tlu_packet_r.legal & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;\n assign mret_r = (dec_tlu_packet_r.pmu_i0_itype == MRET) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;\n`endif\n // fence_i includes debug only fence_i's\n assign fence_i_r = (dec_tlu_packet_r.fence_i & dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & ~rfpc_i0_r;\n assign ic_perr_r = ifu_ic_error_start_f & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f;\n assign iccm_sbecc_r = ifu_iccm_rd_ecc_single_err_f & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f;\n assign inst_acc_r_raw = dec_tlu_packet_r.icaf & dec_tlu_i0_valid_r;\n assign inst_acc_r = inst_acc_r_raw & ~rfpc_i0_r & ~i0_trigger_hit_r;\n assign inst_acc_second_r = dec_tlu_packet_r.icaf_second;\n\n assign ebreak_to_debug_mode_r = (dec_tlu_packet_r.pmu_i0_itype == EBREAK) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & dcsr[DCSR_EBREAKM] & ~rfpc_i0_r;\n\n rvdff #(1) exctype_wb_ff (.*, .clk(e4e5_clk),\n .din (ebreak_to_debug_mode_r ),\n .dout(ebreak_to_debug_mode_r_d1));\n\n assign dec_tlu_fence_i_r = fence_i_r;\n\n`ifdef RV_USER_MODE\n\n // CSR access\n // Address bits 9:8 == 2'b00 indicate unprivileged / user-level CSR\n assign csr_wr_usr_r = ~|dec_csr_wraddr_r[9:8];\n assign csr_rd_usr_r = ~|dec_csr_rdaddr_r[9:8];\n\n // CSR access error\n // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR\n logic csr_wr_acc_r;\n logic csr_rd_acc_r;\n\n assign csr_wr_acc_r = csr_wr_usr_r & (\n ((dec_csr_wraddr_r[11:0] == CYCLEL) & mcounteren[MCOUNTEREN_CY]) |\n ((dec_csr_wraddr_r[11:0] == CYCLEH) & mcounteren[MCOUNTEREN_CY]) |\n ((dec_csr_wraddr_r[11:0] == INSTRETL) & mcounteren[MCOUNTEREN_IR]) |\n ((dec_csr_wraddr_r[11:0] == INSTRETH) & mcounteren[MCOUNTEREN_IR]) |\n ((dec_csr_wraddr_r[11:0] == HPMC3) & mcounteren[MCOUNTEREN_HPM3]) |\n ((dec_csr_wraddr_r[11:0] == HPMC3H) & mcounteren[MCOUNTEREN_HPM3]) |\n ((dec_csr_wraddr_r[11:0] == HPMC4) & mcounteren[MCOUNTEREN_HPM4]) |\n ((dec_csr_wraddr_r[11:0] == HPMC4H) & mcounteren[MCOUNTEREN_HPM4]) |\n ((dec_csr_wraddr_r[11:0] == HPMC5) & mcounteren[MCOUNTEREN_HPM5]) |\n ((dec_csr_wraddr_r[11:0] == HPMC5H) & mcounteren[MCOUNTEREN_HPM5]) |\n ((dec_csr_wraddr_r[11:0] == HPMC6) & mcounteren[MCOUNTEREN_HPM6]) |\n ((dec_csr_wraddr_r[11:0] == HPMC6H) & mcounteren[MCOUNTEREN_HPM6]));\n\n assign csr_rd_acc_r = csr_rd_usr_r & (\n ((dec_csr_rdaddr_r[11:0] == CYCLEL) & mcounteren[MCOUNTEREN_CY]) |\n ((dec_csr_rdaddr_r[11:0] == CYCLEH) & mcounteren[MCOUNTEREN_CY]) |\n ((dec_csr_rdaddr_r[11:0] == INSTRETL) & mcounteren[MCOUNTEREN_IR]) |\n ((dec_csr_rdaddr_r[11:0] == INSTRETH) & mcounteren[MCOUNTEREN_IR]) |\n ((dec_csr_rdaddr_r[11:0] == HPMC3) & mcounteren[MCOUNTEREN_HPM3]) |\n ((dec_csr_rdaddr_r[11:0] == HPMC3H) & mcounteren[MCOUNTEREN_HPM3]) |\n ((dec_csr_rdaddr_r[11:0] == HPMC4) & mcounteren[MCOUNTEREN_HPM4]) |\n ((dec_csr_rdaddr_r[11:0] == HPMC4H) & mcounteren[MCOUNTEREN_HPM4]) |\n ((dec_csr_rdaddr_r[11:0] == HPMC5) & mcounteren[MCOUNTEREN_HPM5]) |\n ((dec_csr_rdaddr_r[11:0] == HPMC5H) & mcounteren[MCOUNTEREN_HPM5]) |\n ((dec_csr_rdaddr_r[11:0] == HPMC6) & mcounteren[MCOUNTEREN_HPM6]) |\n ((dec_csr_rdaddr_r[11:0] == HPMC6H) & mcounteren[MCOUNTEREN_HPM6]));\n\n assign csr_acc_r = priv_mode & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r & (\n (dec_tlu_packet_r.pmu_i0_itype == CSRREAD) & ~csr_rd_acc_r |\n (dec_tlu_packet_r.pmu_i0_itype == CSRWRITE) & ~csr_wr_acc_r |\n (dec_tlu_packet_r.pmu_i0_itype == CSRRW) & ~csr_rd_acc_r & ~csr_wr_acc_r);\n\n`endif\n\n //\n // Exceptions\n //\n // - MEPC <- PC\n // - PC <- MTVEC, assert flush_lower\n // - MCAUSE <- cause\n // - MSCAUSE <- secondary cause\n // - MTVAL <-\n // - MPIE <- MIE\n // - MIE <- 0\n //\n`ifdef RV_USER_MODE\n assign i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r | csr_acc_r) & ~rfpc_i0_r & ~dec_tlu_dbg_halted;\n`else\n assign i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r) & ~rfpc_i0_r & ~dec_tlu_dbg_halted;\n`endif\n\n // Cause:\n //\n // 0x2 : illegal\n // 0x3 : breakpoint\n // 0x8 : Environment call U-mode (if U-mode is enabled)\n // 0xb : Environment call M-mode\n\n\n assign exc_cause_r[4:0] = ( ({5{take_ext_int}} & 5'h0b) |\n ({5{take_timer_int}} & 5'h07) |\n ({5{take_soft_int}} & 5'h03) |\n ({5{take_int_timer0_int}} & 5'h1d) |\n ({5{take_int_timer1_int}} & 5'h1c) |\n ({5{take_ce_int}} & 5'h1e) |\n`ifdef RV_USER_MODE\n ({5{illegal_r| csr_acc_r}} & 5'h02) |\n ({5{ecall_r & priv_mode}} & 5'h08) |\n ({5{ecall_r & ~priv_mode}} & 5'h0b) |\n`else\n ({5{illegal_r}} & 5'h02) |\n ({5{ecall_r}} & 5'h0b) |\n`endif\n ({5{inst_acc_r}} & 5'h01) |\n ({5{ebreak_r | i0_trigger_hit_r}} & 5'h03) |\n ({5{lsu_exc_ma_r & ~lsu_exc_st_r}} & 5'h04) |\n ({5{lsu_exc_acc_r & ~lsu_exc_st_r}} & 5'h05) |\n ({5{lsu_exc_ma_r & lsu_exc_st_r}} & 5'h06) |\n ({5{lsu_exc_acc_r & lsu_exc_st_r}} & 5'h07)\n ) & ~{5{take_nmi}};\n\n //\n // Interrupts\n //\n // exceptions that are committed have already happened and will cause an int at E4 to wait a cycle\n // or more if MSTATUS[MIE] is cleared.\n //\n // -in priority order, highest to lowest\n // -single cycle window where a csr write to MIE/MSTATUS is at E4 when the other conditions for externals are met.\n // Hold off externals for a cycle to make sure we are consistent with what was just written\n assign mhwakeup_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MEIP] & mie_ns[MIE_MEIE];\n assign ext_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MEIP] & mie_ns[MIE_MEIE] & ~ignore_ext_int_due_to_lsu_stall;\n assign ce_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MCEIP] & mie_ns[MIE_MCEIE];\n assign soft_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MSIP] & mie_ns[MIE_MSIE];\n assign timer_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MTIP] & mie_ns[MIE_MTIE];\n\n // MIP for internal timers pulses for 1 clock, resets the timer counter. Mip won't hold past the various stall conditions.\n assign int_timer0_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE0];\n assign int_timer0_int_ready = mip[MIP_MITIP0] & int_timer0_int_possible;\n assign int_timer1_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE1];\n assign int_timer1_int_ready = mip[MIP_MITIP1] & int_timer1_int_possible;\n\n // Internal timers pulse and reset. If core is PMU/FW halted, the pulse will cause an exit from halt, but won't stick around\n // Make it sticky, also for 1 cycle stall conditions.\n assign int_timer_stalled = dec_csr_stall_int_ff | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r;\n\n assign int_timer0_int_hold = (int_timer0_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer0_int_possible & int_timer0_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f);\n assign int_timer1_int_hold = (int_timer1_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer1_int_possible & int_timer1_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f);\n\n\n assign internal_dbg_halt_timers = internal_dbg_halt_mode_f & ~dcsr_single_step_running;\n\n\n assign block_interrupts = ( (internal_dbg_halt_mode & (~dcsr_single_step_running | dec_tlu_i0_valid_r)) | // No ints in db-halt unless we are single stepping\n internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 |// No ints in PMU/FW halt. First we exit halt\n take_nmi | // NMI is top priority\n ebreak_to_debug_mode_r | // Heading to debug mode, hold off ints\n synchronous_flush_r | // exception flush this cycle\n exc_or_int_valid_r_d1 | // ext/int past cycle (need time for MIE to update)\n mret_r | // mret in progress, for cases were ISR enables ints before mret\n ext_int_freeze_d1 // Fast interrupt in progress (optional)\n );\n\n\nif (pt.FAST_INTERRUPT_REDIRECT) begin\n\n\n assign take_ext_int_start = ext_int_ready & ~block_interrupts;\n\n assign ext_int_freeze = take_ext_int_start | take_ext_int_start_d1 | take_ext_int_start_d2 | take_ext_int_start_d3;\n assign take_ext_int = take_ext_int_start_d3 & ~|lsu_fir_error[1:0];\n assign fast_int_meicpct = csr_meicpct & dec_csr_any_unq_d; // MEICPCT becomes illegal if fast ints are enabled\n\n assign ignore_ext_int_due_to_lsu_stall = lsu_fastint_stall_any;\nend\nelse begin\n assign take_ext_int_start = 1'b0;\n assign ext_int_freeze = 1'b0;\n assign ext_int_freeze_d1 = 1'b0;\n assign take_ext_int_start_d1 = 1'b0;\n assign take_ext_int_start_d2 = 1'b0;\n assign take_ext_int_start_d3 = 1'b0;\n assign fast_int_meicpct = 1'b0;\n assign ignore_ext_int_due_to_lsu_stall = 1'b0;\n\n assign take_ext_int = ext_int_ready & ~block_interrupts;\nend\n\n assign take_ce_int = ce_int_ready & ~ext_int_ready & ~block_interrupts;\n assign take_soft_int = soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts;\n assign take_timer_int = timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts;\n assign take_int_timer0_int = (int_timer0_int_ready | int_timer0_int_hold_f) & int_timer0_int_possible & ~dec_csr_stall_int_ff &\n ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts;\n assign take_int_timer1_int = (int_timer1_int_ready | int_timer1_int_hold_f) & int_timer1_int_possible & ~dec_csr_stall_int_ff &\n ~(int_timer0_int_ready | int_timer0_int_hold_f) & ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts;\n\n assign take_reset = reset_delayed & mpc_reset_run_req;\n assign take_nmi = nmi_int_detected & ~internal_pmu_fw_halt_mode & (~internal_dbg_halt_mode | (dcsr_single_step_running_f & dcsr[DCSR_STEPIE] & ~dec_tlu_i0_valid_r & ~dcsr_single_step_done_f)) &\n ~synchronous_flush_r & ~mret_r & ~take_reset & ~ebreak_to_debug_mode_r & (~ext_int_freeze_d1 | (take_ext_int_start_d3 & |lsu_fir_error[1:0]));\n\n assign interrupt_valid_r = take_ext_int | take_timer_int | take_soft_int | take_nmi | take_ce_int | take_int_timer0_int | take_int_timer1_int;\n\n\n // Compute interrupt path:\n // If vectored async is set in mtvec, flush path for interrupts is MTVEC + (4 * CAUSE);\n assign vectored_path[31:1] = {mtvec[30:1], 1'b0} + {25'b0, exc_cause_r[4:0], 1'b0};\n assign interrupt_path[31:1] = take_nmi ? nmi_vec[31:1] : ((mtvec[0] == 1'b1) ? vectored_path[31:1] : {mtvec[30:1], 1'b0});\n\n assign sel_npc_r = lsu_i0_rfnpc_r | fence_i_r | iccm_repair_state_rfnpc | (i_cpu_run_req_d1 & ~interrupt_valid_r) | (rfpc_i0_r & ~dec_tlu_i0_valid_r);\n assign sel_npc_resume = (i_cpu_run_req_d1 & pmu_fw_tlu_halted_f) | pause_expired_r;\n\n assign sel_fir_addr = take_ext_int_start_d3 & ~|lsu_fir_error[1:0];\n\n assign synchronous_flush_r = i0_exception_valid_r | // exception\n rfpc_i0_r | // rfpc\n lsu_exc_valid_r | // lsu exception in either pipe 0 or pipe 1\n fence_i_r | // fence, a rfnpc\n lsu_i0_rfnpc_r | // lsu dccm sb ecc\n iccm_repair_state_rfnpc | // Iccm sb ecc\n debug_resume_req_f | // resume from debug halt, fetch the dpc\n sel_npc_resume | // resume from pmu/fw halt, or from pause and fetch the NPC\n dec_tlu_wr_pause_r_d1 | // flush at start of pause\n i0_trigger_hit_r; // trigger hit, ebreak or goto debug mode\n\n assign tlu_flush_lower_r = interrupt_valid_r | mret_r | synchronous_flush_r | take_halt | take_reset | take_ext_int_start;\n\n assign tlu_flush_path_r[31:1] = take_reset ? rst_vec[31:1] :\n\n ( ({31{sel_fir_addr}} & lsu_fir_addr[31:1]) |\n ({31{~take_nmi & sel_npc_r}} & npc_r[31:1]) |\n ({31{~take_nmi & rfpc_i0_r & dec_tlu_i0_valid_r & ~sel_npc_r}} & dec_tlu_i0_pc_r[31:1]) |\n ({31{interrupt_valid_r & ~sel_fir_addr}} & interrupt_path[31:1]) |\n ({31{(i0_exception_valid_r | lsu_exc_valid_r |\n (i0_trigger_hit_r & ~trigger_hit_dmode_r)) & ~interrupt_valid_r & ~sel_fir_addr}} & {mtvec[30:1],1'b0}) |\n ({31{~take_nmi & mret_r}} & mepc[31:1]) |\n ({31{~take_nmi & debug_resume_req_f}} & dpc[31:1]) |\n ({31{~take_nmi & sel_npc_resume}} & npc_r_d1[31:1]) );\n\n rvdffpcie #(31) flush_lower_ff (.*, .en(tlu_flush_lower_r),\n .din({tlu_flush_path_r[31:1]}),\n .dout({tlu_flush_path_r_d1[31:1]}));\n\n assign dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1;\n assign dec_tlu_flush_lower_r = tlu_flush_lower_r;\n assign dec_tlu_flush_path_r[31:1] = tlu_flush_path_r[31:1];\n\n\n // this is used to capture mepc, etc.\n assign exc_or_int_valid_r = lsu_exc_valid_r | i0_exception_valid_r | interrupt_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r);\n\n\n rvdffie #(12) excinfo_wb_ff (.*,\n .din({interrupt_valid_r, i0_exception_valid_r, exc_or_int_valid_r,\n exc_cause_r[4:0], tlu_i0_commit_cmt & ~illegal_r, i0_trigger_hit_r,\n take_nmi, pause_expired_r }),\n .dout({interrupt_valid_r_d1, i0_exception_valid_r_d1, exc_or_int_valid_r_d1,\n exc_cause_wb[4:0], i0_valid_wb, trigger_hit_r_d1,\n take_nmi_r_d1, pause_expired_wb}));\n`ifdef RV_USER_MODE\n\n //\n // Privilege mode\n //\n assign priv_mode_ns = (mret_r & mstatus[MSTATUS_MPP]) |\n (exc_or_int_valid_r & 1'b0 ) |\n ((~mret_r & ~exc_or_int_valid_r) & priv_mode);\n\n rvdff #(1) priv_ff (\n .clk (free_l2clk),\n .rst_l (rst_l),\n .din (priv_mode_ns),\n .dout (priv_mode)\n );\n\n`endif\n\n //----------------------------------------------------------------------\n //\n // CSRs\n //\n //----------------------------------------------------------------------\n\n // ----------------------------------------------------------------------\n // MSTATUS (RW)\n // [17] MPRV : Modify PRiVilege (if enabled in config)\n // [12:11] MPP : Prior priv level, either 2'b11 (machine) or 2'b00 (user)\n // [7] MPIE : Int enable previous [1]\n // [3] MIE : Int enable [0]\n\n\n //When executing a MRET instruction, supposing MPP holds the value 3, MIE\n //is set to MPIE; the privilege mode is changed to 3; MPIE is set to 1; and MPP is set to 3\n`ifdef RV_USER_MODE\n assign dec_csr_wen_r_mod = dec_csr_wen_r & ~i0_trigger_hit_r & ~rfpc_i0_r & ~csr_acc_r;\n`else\n assign dec_csr_wen_r_mod = dec_csr_wen_r & ~i0_trigger_hit_r & ~rfpc_i0_r;\n`endif\n\n assign wr_mstatus_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSTATUS);\n\n // set this even if we don't go to fwhalt due to debug halt. We committed the inst, so ...\n assign set_mie_pmu_fw_halt = ~mpmc_b_ns[1] & fw_halt_req;\n\n`ifdef RV_USER_MODE\n // mstatus[2] / mstatus_ns[2] actually stores inverse of the MPP field !\n assign mstatus_ns[3:0] = ( ({4{~wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MPRV], priv_mode, mstatus[MSTATUS_MIE], 1'b0}) |\n ({4{ wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MPRV], priv_mode, dec_csr_wrdata_r[3], 1'b0}) |\n ({4{mret_r & ~exc_or_int_valid_r}} & {mstatus[MSTATUS_MPRV] & ~mstatus[MSTATUS_MPP], 1'b1, 1'b1, mstatus[MSTATUS_MPIE]}) |\n ({4{set_mie_pmu_fw_halt}} & {mstatus[3:2], mstatus[MSTATUS_MPIE], 1'b1}) |\n ({4{wr_mstatus_r & ~exc_or_int_valid_r}} & {dec_csr_wrdata_r[17], ~dec_csr_wrdata_r[12], dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]}) |\n ({4{~wr_mstatus_r & ~exc_or_int_valid_r & ~mret_r & ~set_mie_pmu_fw_halt}} & mstatus[3:0]) );\n\n // gate MIE if we are single stepping and DCSR[STEPIE] is off\n // in user mode machine interrupts are always enabled as per RISC-V privilege spec (chapter 3.1.6.1).\n assign mstatus_mie_ns = (priv_mode | mstatus[MSTATUS_MIE]) & (~dcsr_single_step_running_f | dcsr[DCSR_STEPIE]);\n\n // set effective privilege mode according to MPRV and MPP\n assign priv_mode_eff = ( mstatus[MSTATUS_MPRV] & mstatus[MSTATUS_MPP]) | // MPRV=1, use MPP\n (~mstatus[MSTATUS_MPRV] & priv_mode); // MPRV=0, use current operating mode\n\n`else\n\n assign mstatus_ns[1:0] = ( ({2{~wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MIE], 1'b0}) |\n ({2{ wr_mstatus_r & exc_or_int_valid_r}} & {dec_csr_wrdata_r[3], 1'b0}) |\n ({2{mret_r & ~exc_or_int_valid_r}} & {1'b1, mstatus[MSTATUS_MPIE]}) |\n ({2{set_mie_pmu_fw_halt}} & {mstatus[MSTATUS_MPIE], 1'b1}) |\n ({2{wr_mstatus_r & ~exc_or_int_valid_r}} & {dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]}) |\n ({2{~wr_mstatus_r & ~exc_or_int_valid_r & ~mret_r & ~set_mie_pmu_fw_halt}} & mstatus[1:0]) );\n\n assign mstatus_mie_ns = mstatus[MSTATUS_MIE] & (~dcsr_single_step_running_f | dcsr[DCSR_STEPIE]);\n\n`endif\n\n // ----------------------------------------------------------------------\n // MTVEC (RW)\n // [31:2] BASE : Trap vector base address\n // [1] - Reserved, not implemented, reads zero\n // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE)\n\n assign wr_mtvec_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVEC);\n assign mtvec_ns[30:0] = {dec_csr_wrdata_r[31:2], dec_csr_wrdata_r[0]} ;\n rvdffe #(31) mtvec_ff (.*, .en(wr_mtvec_r), .din(mtvec_ns[30:0]), .dout(mtvec[30:0]));\n\n // ----------------------------------------------------------------------\n // MIP (RW)\n //\n // [30] MCEIP : (RO) M-Mode Correctable Error interrupt pending\n // [29] MITIP0 : (RO) M-Mode Internal Timer0 interrupt pending\n // [28] MITIP1 : (RO) M-Mode Internal Timer1 interrupt pending\n // [11] MEIP : (RO) M-Mode external interrupt pending\n // [7] MTIP : (RO) M-Mode timer interrupt pending\n // [3] MSIP : (RO) M-Mode software interrupt pending\n\n assign ce_int = (mdccme_ce_req | miccme_ce_req | mice_ce_req);\n\n assign mip_ns[5:0] = {ce_int, dec_timer_t0_pulse, dec_timer_t1_pulse, mexintpend, timer_int_sync, soft_int_sync};\n\n // ----------------------------------------------------------------------\n // MIE (RW)\n // [30] MCEIE : (RO) M-Mode Correctable Error interrupt enable\n // [29] MITIE0 : (RO) M-Mode Internal Timer0 interrupt enable\n // [28] MITIE1 : (RO) M-Mode Internal Timer1 interrupt enable\n // [11] MEIE : (RW) M-Mode external interrupt enable\n // [7] MTIE : (RW) M-Mode timer interrupt enable\n // [3] MSIE : (RW) M-Mode software interrupt enable\n\n assign wr_mie_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MIE);\n assign mie_ns[5:0] = wr_mie_r ? {dec_csr_wrdata_r[30:28], dec_csr_wrdata_r[11], dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]} : mie[5:0];\n rvdff #(6) mie_ff (.*, .clk(csr_wr_clk), .din(mie_ns[5:0]), .dout(mie[5:0]));\n\n\n // ----------------------------------------------------------------------\n // MCYCLEL (RW)\n // [31:0] : Lower Cycle count\n\n assign kill_ebreak_count_r = ebreak_to_debug_mode_r & dcsr[DCSR_STOPC];\n\n assign wr_mcyclel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEL);\n\n assign mcyclel_cout_in = ~(kill_ebreak_count_r | (dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted | mcountinhibit[0]);\n\n // split for power\n assign {mcyclela_cout, mcyclel_inc[7:0]} = mcyclel[7:0] + {7'b0, 1'b1};\n assign {mcyclel_cout, mcyclel_inc[31:8]} = mcyclel[31:8] + {23'b0, mcyclela_cout};\n\n assign mcyclel_ns[31:0] = wr_mcyclel_r ? dec_csr_wrdata_r[31:0] : mcyclel_inc[31:0];\n\n rvdffe #(24) mcyclel_bff (.*, .clk(free_l2clk), .en(wr_mcyclel_r | (mcyclela_cout & mcyclel_cout_in)), .din(mcyclel_ns[31:8]), .dout(mcyclel[31:8]));\n rvdffe #(8) mcyclel_aff (.*, .clk(free_l2clk), .en(wr_mcyclel_r | mcyclel_cout_in), .din(mcyclel_ns[7:0]), .dout(mcyclel[7:0]));\n\n // ----------------------------------------------------------------------\n // MCYCLEH (RW)\n // [63:32] : Higher Cycle count\n // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored.\n\n assign wr_mcycleh_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEH);\n\n assign mcycleh_inc[31:0] = mcycleh[31:0] + {31'b0, mcyclel_cout_f};\n assign mcycleh_ns[31:0] = wr_mcycleh_r ? dec_csr_wrdata_r[31:0] : mcycleh_inc[31:0];\n\n rvdffe #(32) mcycleh_ff (.*, .clk(free_l2clk), .en(wr_mcycleh_r | mcyclel_cout_f), .din(mcycleh_ns[31:0]), .dout(mcycleh[31:0]));\n\n // ----------------------------------------------------------------------\n // MINSTRETL (RW)\n // [31:0] : Lower Instruction retired count\n // From the spec \"Some CSRs, such as the instructions retired counter, instret, may be modified as side effects\n // of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the\n // value prior to the execution of the instruction. If a CSR access instruction writes a CSR, the\n // update occurs after the execution of the instruction. In particular, a value written to instret by\n // one instruction will be the value read by the following instruction (i.e., the increment of instret\n // caused by the first instruction retiring happens before the write of the new value).\"\n\n assign i0_valid_no_ebreak_ecall_r = dec_tlu_i0_valid_r & ~(ebreak_r | ecall_r | ebreak_to_debug_mode_r | illegal_r | mcountinhibit[2]);\n\n assign wr_minstretl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETL);\n\n assign {minstretl_couta, minstretl_inc[7:0]} = minstretl[7:0] + {7'b0,1'b1};\n assign {minstretl_cout, minstretl_inc[31:8]} = minstretl[31:8] + {23'b0, minstretl_couta};\n\n assign minstret_enable = (i0_valid_no_ebreak_ecall_r & tlu_i0_commit_cmt) | wr_minstretl_r;\n\n assign minstretl_cout_ns = minstretl_cout & ~wr_minstreth_r & i0_valid_no_ebreak_ecall_r & ~dec_tlu_dbg_halted;\n\n assign minstretl_ns[31:0] = wr_minstretl_r ? dec_csr_wrdata_r[31:0] : minstretl_inc[31:0];\n rvdffe #(24) minstretl_bff (.*, .en(wr_minstretl_r | (minstretl_couta & minstret_enable)),\n .din(minstretl_ns[31:8]), .dout(minstretl[31:8]));\n rvdffe #(8) minstretl_aff (.*, .en(minstret_enable),\n .din(minstretl_ns[7:0]), .dout(minstretl[7:0]));\n\n\n assign minstretl_read[31:0] = minstretl[31:0];\n // ----------------------------------------------------------------------\n // MINSTRETH (RW)\n // [63:32] : Higher Instret count\n // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored.\n\n assign wr_minstreth_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETH);\n\n assign minstreth_inc[31:0] = minstreth[31:0] + {31'b0, minstretl_cout_f};\n assign minstreth_ns[31:0] = wr_minstreth_r ? dec_csr_wrdata_r[31:0] : minstreth_inc[31:0];\n rvdffe #(32) minstreth_ff (.*, .en((minstret_enable_f & minstretl_cout_f) | wr_minstreth_r), .din(minstreth_ns[31:0]), .dout(minstreth[31:0]));\n\n assign minstreth_read[31:0] = minstreth_inc[31:0];\n\n // ----------------------------------------------------------------------\n // MSCRATCH (RW)\n // [31:0] : Scratch register\n assign wr_mscratch_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCRATCH);\n\n rvdffe #(32) mscratch_ff (.*, .en(wr_mscratch_r), .din(dec_csr_wrdata_r[31:0]), .dout(mscratch[31:0]));\n\n // ----------------------------------------------------------------------\n // MEPC (RW)\n // [31:1] : Exception PC\n\n // NPC\n\n assign sel_exu_npc_r = ~dec_tlu_dbg_halted & ~tlu_flush_lower_r_d1 & dec_tlu_i0_valid_r;\n assign sel_flush_npc_r = ~dec_tlu_dbg_halted & tlu_flush_lower_r_d1 & ~dec_tlu_flush_noredir_r_d1;\n assign sel_hold_npc_r = ~sel_exu_npc_r & ~sel_flush_npc_r;\n\n assign npc_r[31:1] = ( ({31{sel_exu_npc_r}} & exu_npc_r[31:1]) |\n ({31{~mpc_reset_run_req & reset_delayed}} & rst_vec[31:1]) | // init to reset vector for mpc halt on reset case\n ({31{(sel_flush_npc_r)}} & tlu_flush_path_r_d1[31:1]) |\n ({31{(sel_hold_npc_r)}} & npc_r_d1[31:1]) );\n\n rvdffpcie #(31) npwbc_ff (.*, .en(sel_exu_npc_r | sel_flush_npc_r | reset_delayed), .din(npc_r[31:1]), .dout(npc_r_d1[31:1]));\n\n // PC has to be captured for exceptions and interrupts. For MRET, we could execute it and then take an\n // interrupt before the next instruction.\n assign pc0_valid_r = ~dec_tlu_dbg_halted & dec_tlu_i0_valid_r;\n\n assign pc_r[31:1] = ( ({31{ pc0_valid_r}} & dec_tlu_i0_pc_r[31:1]) |\n ({31{~pc0_valid_r}} & pc_r_d1[31:1]));\n\n rvdffpcie #(31) pwbc_ff (.*, .en(pc0_valid_r), .din(pc_r[31:1]), .dout(pc_r_d1[31:1]));\n\n assign wr_mepc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEPC);\n\n assign mepc_ns[31:1] = ( ({31{i0_exception_valid_r | lsu_exc_valid_r | mepc_trigger_hit_sel_pc_r}} & pc_r[31:1]) |\n ({31{interrupt_valid_r}} & npc_r[31:1]) |\n ({31{wr_mepc_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:1]) |\n ({31{~wr_mepc_r & ~exc_or_int_valid_r}} & mepc[31:1]) );\n\n\n rvdffe #(31) mepc_ff (.*, .en(i0_exception_valid_r | lsu_exc_valid_r | mepc_trigger_hit_sel_pc_r | interrupt_valid_r | wr_mepc_r), .din(mepc_ns[31:1]), .dout(mepc[31:1]));\n\n // ----------------------------------------------------------------------\n // MCAUSE (RW)\n // [31:0] : Exception Cause\n\n assign wr_mcause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCAUSE);\n assign mcause_sel_nmi_store = exc_or_int_valid_r & take_nmi & nmi_lsu_store_type;\n assign mcause_sel_nmi_load = exc_or_int_valid_r & take_nmi & nmi_lsu_load_type;\n assign mcause_sel_nmi_ext = exc_or_int_valid_r & take_nmi & take_ext_int_start_d3 & |lsu_fir_error[1:0] & ~nmi_int_detected_f;\n // FIR value decoder\n // 0 –no error\n // 1 –uncorrectable ecc => f000_1000\n // 2 –dccm region access error => f000_1001\n // 3 –non dccm region access error => f000_1002\n assign mcause_fir_error_type[1:0] = {&lsu_fir_error[1:0], lsu_fir_error[1] & ~lsu_fir_error[0]};\n\n assign mcause_ns[31:0] = ( ({32{mcause_sel_nmi_store}} & {32'hf000_0000}) |\n ({32{mcause_sel_nmi_load}} & {32'hf000_0001}) |\n ({32{mcause_sel_nmi_ext}} & {28'hf000_100, 2'b0, mcause_fir_error_type[1:0]}) |\n ({32{exc_or_int_valid_r & ~take_nmi}} & {interrupt_valid_r, 26'b0, exc_cause_r[4:0]}) |\n ({32{wr_mcause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:0]) |\n ({32{~wr_mcause_r & ~exc_or_int_valid_r}} & mcause[31:0]) );\n\n rvdffe #(32) mcause_ff (.*, .en(exc_or_int_valid_r | wr_mcause_r), .din(mcause_ns[31:0]), .dout(mcause[31:0]));\n // ----------------------------------------------------------------------\n // MSCAUSE (RW)\n // [2:0] : Secondary exception Cause\n assign wr_mscause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCAUSE);\n\n assign ifu_mscause[3:0] = (dec_tlu_packet_r.icaf_type[1:0] == 2'b00) ? 4'b1001 :\n {2'b00 , dec_tlu_packet_r.icaf_type[1:0]} ;\n\n assign mscause_type[3:0] = ( ({4{lsu_i0_exc_r}} & lsu_error_pkt_r.mscause[3:0]) |\n ({4{i0_trigger_hit_r}} & 4'b0001) |\n ({4{ebreak_r}} & 4'b0010) |\n ({4{inst_acc_r}} & ifu_mscause[3:0])\n );\n\n assign mscause_ns[3:0] = ( ({4{exc_or_int_valid_r}} & mscause_type[3:0]) |\n ({4{ wr_mscause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[3:0]) |\n ({4{~wr_mscause_r & ~exc_or_int_valid_r}} & mscause[3:0])\n );\n\n rvdff #(4) mscause_ff (.*, .clk(e4e5_int_clk), .din(mscause_ns[3:0]), .dout(mscause[3:0]));\n // ----------------------------------------------------------------------\n // MTVAL (RW)\n // [31:0] : Exception address if relevant\n\n assign wr_mtval_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVAL);\n assign mtval_capture_pc_r = exc_or_int_valid_r & (ebreak_r | (inst_acc_r & ~inst_acc_second_r) | mepc_trigger_hit_sel_pc_r) & ~take_nmi;\n assign mtval_capture_pc_plus2_r = exc_or_int_valid_r & (inst_acc_r & inst_acc_second_r) & ~take_nmi;\n assign mtval_capture_inst_r = exc_or_int_valid_r & illegal_r & ~take_nmi;\n assign mtval_capture_lsu_r = exc_or_int_valid_r & lsu_exc_valid_r & ~take_nmi;\n assign mtval_clear_r = exc_or_int_valid_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_capture_lsu_r & ~mepc_trigger_hit_sel_pc_r;\n\n\n assign mtval_ns[31:0] = (({32{mtval_capture_pc_r}} & {pc_r[31:1], 1'b0}) |\n ({32{mtval_capture_pc_plus2_r}} & {pc_r[31:1] + 31'b1, 1'b0}) |\n ({32{mtval_capture_inst_r}} & dec_illegal_inst[31:0]) |\n ({32{mtval_capture_lsu_r}} & lsu_error_pkt_addr_r[31:0]) |\n ({32{wr_mtval_r & ~interrupt_valid_r}} & dec_csr_wrdata_r[31:0]) |\n ({32{~take_nmi & ~wr_mtval_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_clear_r & ~mtval_capture_lsu_r}} & mtval[31:0]) );\n\n\n rvdffe #(32) mtval_ff (.*, .en(tlu_flush_lower_r | wr_mtval_r), .din(mtval_ns[31:0]), .dout(mtval[31:0]));\n\n // ----------------------------------------------------------------------\n // MSECCFG\n // [31:3] : Reserved, read 0x0\n // [2] : RLB\n // [1] : MMWP\n // [0] : MML\n\n`ifdef RV_USER_MODE\n\n localparam MSECCFG = 12'h747;\n localparam MSECCFGH = 12'h757;\n\n // Detect if any PMP region is locked regardless of being enabled. This is\n // necessary for mseccfg.RLB bit write behavior\n logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;\n for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions\n assign pmp_region_locked[r] = pmp_pmpcfg[r].lock;\n end\n\n logic pmp_any_region_locked;\n assign pmp_any_region_locked = |pmp_region_locked;\n\n // mseccfg\n assign wr_mseccfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSECCFG);\n rvdffs #(3) mseccfg_ff (.*, .clk(csr_wr_clk), .en(wr_mseccfg_r), .din(mseccfg_ns), .dout(mseccfg));\n\n assign mseccfg_ns = {\n pmp_any_region_locked ?\n (dec_csr_wrdata_r[MSECCFG_RLB] & mseccfg[MSECCFG_RLB]) : // When any PMP region is locked this bit can only be cleared\n dec_csr_wrdata_r[MSECCFG_RLB], // Otherwise regularly writeable\n dec_csr_wrdata_r[MSECCFG_MMWP] | mseccfg[MSECCFG_MMWP], // Sticky bit, can only be set but not cleared\n dec_csr_wrdata_r[MSECCFG_MML ] | mseccfg[MSECCFG_MML ] // Sticky bit, can only be set but never cleared\n };\n\n`endif\n\n // ----------------------------------------------------------------------\n // MCGC (RW) Clock gating control\n // [31:10]: Reserved, reads 0x0\n // [9] : picio_clk_override\n // [7] : dec_clk_override\n // [6] : Unused\n // [5] : ifu_clk_override\n // [4] : lsu_clk_override\n // [3] : bus_clk_override\n // [2] : pic_clk_override\n // [1] : dccm_clk_override\n // [0] : icm_clk_override\n //\n assign wr_mcgc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCGC);\n\n assign mcgc_ns[9:0] = wr_mcgc_r ? {~dec_csr_wrdata_r[9], dec_csr_wrdata_r[8:0]} : mcgc_int[9:0];\n rvdffe #(10) mcgc_ff (.*, .en(wr_mcgc_r), .din(mcgc_ns[9:0]), .dout(mcgc_int[9:0]));\n\n assign mcgc[9:0] = {~mcgc_int[9], mcgc_int[8:0]};\n\n assign dec_tlu_picio_clk_override= mcgc[9];\n assign dec_tlu_misc_clk_override = mcgc[8];\n assign dec_tlu_dec_clk_override = mcgc[7];\n //sign dec_tlu_exu_clk_override = mcgc[6];\n assign dec_tlu_ifu_clk_override = mcgc[5];\n assign dec_tlu_lsu_clk_override = mcgc[4];\n assign dec_tlu_bus_clk_override = mcgc[3];\n assign dec_tlu_pic_clk_override = mcgc[2];\n assign dec_tlu_dccm_clk_override = mcgc[1];\n assign dec_tlu_icm_clk_override = mcgc[0];\n\n // ----------------------------------------------------------------------\n // MFDC (RW) Feature Disable Control\n // [31:19] : Reserved, reads 0x0\n // [18:16] : DMA QoS Prty\n // [15:13] : Reserved, reads 0x0\n // [12] : Disable trace\n // [11] : Disable external load forwarding\n // [10] : Disable dual issue\n // [9] : Disable pic multiple ints\n // [8] : Disable core ecc\n // [7] : Disable secondary alu?s\n // [6] : Unused, 0x0\n // [5] : Disable non-blocking loads/divides\n // [4] : Disable fast divide\n // [3] : Disable branch prediction and return stack\n // [2] : Disable write buffer coalescing\n // [1] : Disable load misses that bypass the write buffer\n // [0] : Disable pipelining - Enable single instruction execution\n //\n\n assign wr_mfdc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDC);\n\n rvdffe #(16) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[15:0]}), .dout(mfdc_int[15:0]));\n\n // flip poweron value of bit 6 for AXI build\n if(pt.BUILD_AXI4==1) begin : axi4\n // flip poweron valid of bit 12\n assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16], dec_csr_wrdata_r[12], dec_csr_wrdata_r[11:7], ~dec_csr_wrdata_r[6], dec_csr_wrdata_r[5:0]};\n assign mfdc[18:0] = {~mfdc_int[15:13], 3'b0, mfdc_int[12], mfdc_int[11:7], ~mfdc_int[6], mfdc_int[5:0]};\n end\n else begin\n // flip poweron valid of bit 12\n assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16],dec_csr_wrdata_r[12:0]};\n assign mfdc[18:0] = {~mfdc_int[15:13], 3'b0, mfdc_int[12:0]};\n end\n\n\n assign dec_tlu_dma_qos_prty[2:0] = mfdc[18:16];\n assign dec_tlu_trace_disable = mfdc[12];\n assign dec_tlu_external_ldfwd_disable = mfdc[11];\n assign dec_tlu_core_ecc_disable = mfdc[8];\n assign dec_tlu_sideeffect_posted_disable = mfdc[6];\n assign dec_tlu_bpred_disable = mfdc[3];\n assign dec_tlu_wb_coalescing_disable = mfdc[2];\n assign dec_tlu_pipelining_disable = mfdc[0];\n\n // ----------------------------------------------------------------------\n // MCPC (RW) Pause counter\n // [31:0] : Reads 0x0, decs in the wb register in decode_ctl\n\n assign dec_tlu_wr_pause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC) & ~interrupt_valid_r & ~take_ext_int_start;\n\n // ----------------------------------------------------------------------\n // MRAC (RW)\n // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs\n\n assign wr_mrac_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MRAC);\n\n // prevent pairs of 0x11, side_effect and cacheable\n assign mrac_in[31:0] = {dec_csr_wrdata_r[31], dec_csr_wrdata_r[30] & ~dec_csr_wrdata_r[31],\n dec_csr_wrdata_r[29], dec_csr_wrdata_r[28] & ~dec_csr_wrdata_r[29],\n dec_csr_wrdata_r[27], dec_csr_wrdata_r[26] & ~dec_csr_wrdata_r[27],\n dec_csr_wrdata_r[25], dec_csr_wrdata_r[24] & ~dec_csr_wrdata_r[25],\n dec_csr_wrdata_r[23], dec_csr_wrdata_r[22] & ~dec_csr_wrdata_r[23],\n dec_csr_wrdata_r[21], dec_csr_wrdata_r[20] & ~dec_csr_wrdata_r[21],\n dec_csr_wrdata_r[19], dec_csr_wrdata_r[18] & ~dec_csr_wrdata_r[19],\n dec_csr_wrdata_r[17], dec_csr_wrdata_r[16] & ~dec_csr_wrdata_r[17],\n dec_csr_wrdata_r[15], dec_csr_wrdata_r[14] & ~dec_csr_wrdata_r[15],\n dec_csr_wrdata_r[13], dec_csr_wrdata_r[12] & ~dec_csr_wrdata_r[13],\n dec_csr_wrdata_r[11], dec_csr_wrdata_r[10] & ~dec_csr_wrdata_r[11],\n dec_csr_wrdata_r[9], dec_csr_wrdata_r[8] & ~dec_csr_wrdata_r[9],\n dec_csr_wrdata_r[7], dec_csr_wrdata_r[6] & ~dec_csr_wrdata_r[7],\n dec_csr_wrdata_r[5], dec_csr_wrdata_r[4] & ~dec_csr_wrdata_r[5],\n dec_csr_wrdata_r[3], dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[3],\n dec_csr_wrdata_r[1], dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[1]};\n\n rvdffe #(32) mrac_ff (.*, .en(wr_mrac_r), .din(mrac_in[31:0]), .dout(mrac[31:0]));\n\n // drive to LSU/IFU\n assign dec_tlu_mrac_ff[31:0] = mrac[31:0];\n\n // ----------------------------------------------------------------------\n // MDEAU (WAR0)\n // [31:0] : Dbus Error Address Unlock register\n //\n\n assign wr_mdeau_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDEAU);\n\n\n // ----------------------------------------------------------------------\n // MDSEAC (R)\n // [31:0] : Dbus Store Error Address Capture register\n //\n\n // only capture error bus if the MDSEAC reg is not locked\n assign mdseac_locked_ns = mdseac_en | (mdseac_locked_f & ~wr_mdeau_r);\n\n assign mdseac_en = (lsu_imprecise_error_store_any | lsu_imprecise_error_load_any) & ~nmi_int_detected_f & ~mdseac_locked_f;\n\n rvdffe #(32) mdseac_ff (.*, .en(mdseac_en), .din(lsu_imprecise_error_addr_any[31:0]), .dout(mdseac[31:0]));\n\n // ----------------------------------------------------------------------\n // MPMC (R0W1)\n // [0] : FW halt\n // [1] : Set MSTATUS[MIE] on halt\n\n assign wr_mpmc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MPMC);\n\n // allow the cycle of the dbg halt flush that contains the wr_mpmc_r to\n // set the mstatus bit potentially, use delayed version of internal dbg halt.\n assign fw_halt_req = wr_mpmc_r & dec_csr_wrdata_r[0] & ~internal_dbg_halt_mode_f2 & ~ext_int_freeze_d1;\n\n assign fw_halted_ns = (fw_halt_req | fw_halted) & ~set_mie_pmu_fw_halt;\n assign mpmc_b_ns[1] = wr_mpmc_r ? ~dec_csr_wrdata_r[1] : ~mpmc[1];\n rvdff #(1) mpmc_ff (.*, .clk(csr_wr_clk), .din(mpmc_b_ns[1]), .dout(mpmc_b[1]));\n assign mpmc[1] = ~mpmc_b[1];\n\n // ----------------------------------------------------------------------\n // MICECT (I-Cache error counter/threshold)\n // [31:27] : Icache parity error threshold\n // [26:0] : Icache parity error count\n\n assign csr_sat[31:27] = (dec_csr_wrdata_r[31:27] > 5'd26) ? 5'd26 : dec_csr_wrdata_r[31:27];\n\n assign wr_micect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICECT);\n assign micect_inc[26:0] = micect[26:0] + {26'b0, ic_perr_r};\n assign micect_ns = wr_micect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {micect[31:27], micect_inc[26:0]};\n\n rvdffe #(32) micect_ff (.*, .en(wr_micect_r | ic_perr_r), .din(micect_ns[31:0]), .dout(micect[31:0]));\n\n assign mice_ce_req = |({32'hffffffff << micect[31:27]} & {5'b0, micect[26:0]});\n\n // ----------------------------------------------------------------------\n // MICCMECT (ICCM error counter/threshold)\n // [31:27] : ICCM parity error threshold\n // [26:0] : ICCM parity error count\n\n assign wr_miccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICCMECT);\n assign miccmect_inc[26:0] = miccmect[26:0] + {26'b0, iccm_sbecc_r | iccm_dma_sb_error};\n assign miccmect_ns = wr_miccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {miccmect[31:27], miccmect_inc[26:0]};\n\n rvdffe #(32) miccmect_ff (.*, .clk(free_l2clk), .en(wr_miccmect_r | iccm_sbecc_r | iccm_dma_sb_error), .din(miccmect_ns[31:0]), .dout(miccmect[31:0]));\n\n assign miccme_ce_req = |({32'hffffffff << miccmect[31:27]} & {5'b0, miccmect[26:0]});\n\n // ----------------------------------------------------------------------\n // MDCCMECT (DCCM error counter/threshold)\n // [31:27] : DCCM parity error threshold\n // [26:0] : DCCM parity error count\n\n assign wr_mdccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDCCMECT);\n assign mdccmect_inc[26:0] = mdccmect[26:0] + {26'b0, lsu_single_ecc_error_r_d1};\n assign mdccmect_ns = wr_mdccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {mdccmect[31:27], mdccmect_inc[26:0]};\n\n rvdffe #(32) mdccmect_ff (.*, .clk(free_l2clk), .en(wr_mdccmect_r | lsu_single_ecc_error_r_d1), .din(mdccmect_ns[31:0]), .dout(mdccmect[31:0]));\n\n assign mdccme_ce_req = |({32'hffffffff << mdccmect[31:27]} & {5'b0, mdccmect[26:0]});\n\n\n // ----------------------------------------------------------------------\n // MFDHT (Force Debug Halt Threshold)\n // [5:1] : Halt timeout threshold (power of 2)\n // [0] : Halt timeout enabled\n\n assign wr_mfdht_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHT);\n\n assign mfdht_ns[5:0] = wr_mfdht_r ? dec_csr_wrdata_r[5:0] : mfdht[5:0];\n\n rvdffs #(6) mfdht_ff (.*, .clk(csr_wr_clk), .en(wr_mfdht_r), .din(mfdht_ns[5:0]), .dout(mfdht[5:0]));\n\n // ----------------------------------------------------------------------\n // MFDHS(RW)\n // [1] : LSU operation pending when debug halt threshold reached\n // [0] : IFU operation pending when debug halt threshold reached\n\n assign wr_mfdhs_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHS);\n\n assign mfdhs_ns[1:0] = wr_mfdhs_r ? dec_csr_wrdata_r[1:0] : ((dbg_tlu_halted & ~dbg_tlu_halted_f) ? {~lsu_idle_any_f, ~ifu_miss_state_idle_f} : mfdhs[1:0]);\n\n rvdffs #(2) mfdhs_ff (.*, .clk(free_clk), .en(wr_mfdhs_r | dbg_tlu_halted), .din(mfdhs_ns[1:0]), .dout(mfdhs[1:0]));\n\n assign force_halt_ctr[31:0] = debug_halt_req_f ? (force_halt_ctr_f[31:0] + 32'b1) : (dbg_tlu_halted_f ? 32'b0 : force_halt_ctr_f[31:0]);\n\n rvdffe #(32) forcehaltctr_ff (.*, .en(mfdht[0]), .din(force_halt_ctr[31:0]), .dout(force_halt_ctr_f[31:0]));\n\n assign force_halt = mfdht[0] & |(force_halt_ctr_f[31:0] & (32'hffffffff << mfdht[5:1]));\n\n\n // ----------------------------------------------------------------------\n // MEIVT (External Interrupt Vector Table (R/W))\n // [31:10]: Base address (R/W)\n // [9:0] : Reserved, reads 0x0\n assign wr_meivt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIVT);\n\n rvdffe #(22) meivt_ff (.*, .en(wr_meivt_r), .din(dec_csr_wrdata_r[31:10]), .dout(meivt[31:10]));\n\n\n // ----------------------------------------------------------------------\n // MEIHAP (External Interrupt Handler Access Pointer (R))\n // [31:10]: Base address (R/W)\n // [9:2] : ClaimID (R)\n // [1:0] : Reserved, 0x0\n\n assign wr_meihap_r = wr_meicpct_r;\n\n rvdffe #(8) meihap_ff (.*, .en(wr_meihap_r), .din(pic_claimid[7:0]), .dout(meihap[9:2]));\n\n assign dec_tlu_meihap[31:2] = {meivt[31:10], meihap[9:2]};\n\n // ----------------------------------------------------------------------\n // MEICURPL (R/W)\n // [31:4] : Reserved (read 0x0)\n // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W)\n assign wr_meicurpl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICURPL);\n assign meicurpl_ns[3:0] = wr_meicurpl_r ? dec_csr_wrdata_r[3:0] : meicurpl[3:0];\n\n rvdff #(4) meicurpl_ff (.*, .clk(csr_wr_clk), .din(meicurpl_ns[3:0]), .dout(meicurpl[3:0]));\n\n // PIC needs this reg\n assign dec_tlu_meicurpl[3:0] = meicurpl[3:0];\n\n\n // ----------------------------------------------------------------------\n // MEICIDPL (R/W)\n // [31:4] : Reserved (read 0x0)\n // [3:0] : External Interrupt Claim ID's Priority Level Register\n\n assign wr_meicidpl_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICIDPL)) | take_ext_int_start;\n\n assign meicidpl_ns[3:0] = wr_meicpct_r ? pic_pl[3:0] : (wr_meicidpl_r ? dec_csr_wrdata_r[3:0] : meicidpl[3:0]);\n\n\n // ----------------------------------------------------------------------\n // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL\n // [31:1] : Reserved (read 0x0)\n // [0] : Capture (W1, Read 0)\n assign wr_meicpct_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICPCT)) | take_ext_int_start;\n\n // ----------------------------------------------------------------------\n // MEIPT (External Interrupt Priority Threshold)\n // [31:4] : Reserved (read 0x0)\n // [3:0] : PRITHRESH\n\n assign wr_meipt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIPT);\n assign meipt_ns[3:0] = wr_meipt_r ? dec_csr_wrdata_r[3:0] : meipt[3:0];\n\n rvdff #(4) meipt_ff (.*, .clk(csr_wr_clk), .din(meipt_ns[3:0]), .dout(meipt[3:0]));\n\n // to PIC\n assign dec_tlu_meipt[3:0] = meipt[3:0];\n // ----------------------------------------------------------------------\n // DCSR (R/W) (Only accessible in debug mode)\n // [31:28] : xdebugver (hard coded to 0x4) RO\n // [27:16] : 0x0, reserved\n // [15] : ebreakm\n // [14] : 0x0, reserved\n // [13] : ebreaks (0x0 for this core)\n // [12] : ebreaku (0x0 for this core)\n // [11] : stepie\n // [10] : stopcount\n // [9] : 0x0 //stoptime\n // [8:6] : cause (RO)\n // [5:4] : 0x0, reserved\n // [3] : nmip\n // [2] : step\n // [1:0] : prv (0x3 for this core)\n //\n\n // RV has clarified that 'priority 4' in the spec means top priority.\n // 4. single step. 3. Debugger request. 2. Ebreak. 1. Trigger.\n\n // RV debug spec indicates a cause priority change for trigger hits during single step.\n assign trigger_hit_for_dscr_cause_r_d1 = trigger_hit_dmode_r_d1 | (trigger_hit_r_d1 & dcsr_single_step_done_f);\n\n assign dcsr_cause[8:6] = ( ({3{dcsr_single_step_done_f & ~ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1 & ~debug_halt_req}} & 3'b100) |\n ({3{debug_halt_req & ~ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b011) |\n ({3{ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b001) |\n ({3{trigger_hit_for_dscr_cause_r_d1}} & 3'b010));\n\n assign wr_dcsr_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DCSR);\n\n\n\n // Multiple halt enter requests can happen before we are halted.\n // We have to continue to upgrade based on dcsr_cause priority but we can't downgrade.\n assign dcsr_cause_upgradeable = internal_dbg_halt_mode_f & (dcsr[8:6] == 3'b011);\n assign enter_debug_halt_req_le = enter_debug_halt_req & (~dbg_tlu_halted | dcsr_cause_upgradeable);\n\n assign nmi_in_debug_mode = nmi_int_detected_f & internal_dbg_halt_mode_f;\n assign dcsr_ns[15:2] = enter_debug_halt_req_le ? {dcsr[15:9], dcsr_cause[8:6], dcsr[5:2]} :\n (wr_dcsr_r ? {dec_csr_wrdata_r[15], 3'b0, dec_csr_wrdata_r[11:10], 1'b0, dcsr[8:6], 2'b00, nmi_in_debug_mode | dcsr[3], dec_csr_wrdata_r[2]} :\n {dcsr[15:4], nmi_in_debug_mode, dcsr[2]});\n\n rvdffe #(14) dcsr_ff (.*, .clk(free_l2clk), .en(enter_debug_halt_req_le | wr_dcsr_r | internal_dbg_halt_mode | take_nmi), .din(dcsr_ns[15:2]), .dout(dcsr[15:2]));\n\n // ----------------------------------------------------------------------\n // DPC (R/W) (Only accessible in debug mode)\n // [31:0] : Debug PC\n\n assign wr_dpc_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DPC);\n assign dpc_capture_npc = dbg_tlu_halted & ~dbg_tlu_halted_f & ~request_debug_mode_done;\n assign dpc_capture_pc = request_debug_mode_r;\n\n assign dpc_ns[31:1] = ( ({31{~dpc_capture_pc & ~dpc_capture_npc & wr_dpc_r}} & dec_csr_wrdata_r[31:1]) |\n ({31{dpc_capture_pc}} & pc_r[31:1]) |\n ({31{~dpc_capture_pc & dpc_capture_npc}} & npc_r[31:1]) );\n\n rvdffe #(31) dpc_ff (.*, .en(wr_dpc_r | dpc_capture_pc | dpc_capture_npc), .din(dpc_ns[31:1]), .dout(dpc[31:1]));\n\n // ----------------------------------------------------------------------\n // DICAWICS (R/W) (Only accessible in debug mode)\n // [31:25] : Reserved\n // [24] : Array select, 0 is data, 1 is tag\n // [23:22] : Reserved\n // [21:20] : Way select\n // [19:17] : Reserved\n // [16:3] : Index\n // [2:0] : Reserved\n\n assign dicawics_ns[16:0] = {dec_csr_wrdata_r[24], dec_csr_wrdata_r[21:20], dec_csr_wrdata_r[16:3]};\n assign wr_dicawics_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAWICS);\n\n rvdffe #(17) dicawics_ff (.*, .en(wr_dicawics_r), .din(dicawics_ns[16:0]), .dout(dicawics[16:0]));\n\n // ----------------------------------------------------------------------\n // DICAD0 (R/W) (Only accessible in debug mode)\n //\n // If dicawics[array] is 0\n // [31:0] : inst data\n //\n // If dicawics[array] is 1\n // [31:16] : Tag\n // [15:7] : Reserved\n // [6:4] : LRU\n // [3:1] : Reserved\n // [0] : Valid\n\n assign dicad0_ns[31:0] = wr_dicad0_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[31:0];\n\n assign wr_dicad0_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD0);\n\n rvdffe #(32) dicad0_ff (.*, .en(wr_dicad0_r | ifu_ic_debug_rd_data_valid), .din(dicad0_ns[31:0]), .dout(dicad0[31:0]));\n\n // ----------------------------------------------------------------------\n // DICAD0H (R/W) (Only accessible in debug mode)\n //\n // If dicawics[array] is 0\n // [63:32] : inst data\n //\n\n assign dicad0h_ns[31:0] = wr_dicad0h_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[63:32];\n\n assign wr_dicad0h_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD0H);\n\n rvdffe #(32) dicad0h_ff (.*, .en(wr_dicad0h_r | ifu_ic_debug_rd_data_valid), .din(dicad0h_ns[31:0]), .dout(dicad0h[31:0]));\n\n\nif (pt.ICACHE_ECC == 1) begin : genblock1\n // ----------------------------------------------------------------------\n // DICAD1 (R/W) (Only accessible in debug mode)\n // [6:0] : ECC\n localparam DICAD1 = 12'h7ca;\n\n assign dicad1_ns[6:0] = wr_dicad1_r ? dec_csr_wrdata_r[6:0] : ifu_ic_debug_rd_data[70:64];\n\n assign wr_dicad1_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD1);\n\n rvdffe #(.WIDTH(7), .OVERRIDE(1)) dicad1_ff (.*, .en(wr_dicad1_r | ifu_ic_debug_rd_data_valid), .din(dicad1_ns[6:0]), .dout(dicad1_raw[6:0]));\n\n assign dicad1[31:0] = {25'b0, dicad1_raw[6:0]};\n\nend\nelse begin : genblock1\n // ----------------------------------------------------------------------\n // DICAD1 (R/W) (Only accessible in debug mode)\n // [3:0] : Parity\n localparam DICAD1 = 12'h7ca;\n\n assign dicad1_ns[3:0] = wr_dicad1_r ? dec_csr_wrdata_r[3:0] : ifu_ic_debug_rd_data[67:64];\n\n assign wr_dicad1_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD1);\n\n rvdffs #(4) dicad1_ff (.*, .clk(free_clk), .en(wr_dicad1_r | ifu_ic_debug_rd_data_valid), .din(dicad1_ns[3:0]), .dout(dicad1_raw[3:0]));\n\n assign dicad1[31:0] = {28'b0, dicad1_raw[3:0]};\nend\n // ----------------------------------------------------------------------\n // DICAGO (R/W) (Only accessible in debug mode)\n // [0] : Go\n\nif (pt.ICACHE_ECC == 1)\n assign dec_tlu_ic_diag_pkt.icache_wrdata[70:0] = { dicad1[6:0], dicad0h[31:0], dicad0[31:0]};\nelse\n assign dec_tlu_ic_diag_pkt.icache_wrdata[70:0] = {3'b0, dicad1[3:0], dicad0h[31:0], dicad0[31:0]};\n\n\n assign dec_tlu_ic_diag_pkt.icache_dicawics[16:0] = dicawics[16:0];\n\n assign icache_rd_valid = allow_dbg_halt_csr_write & dec_csr_any_unq_d & dec_i0_decode_d & ~dec_csr_wen_unq_d & (dec_csr_rdaddr_d[11:0] == DICAGO);\n assign icache_wr_valid = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAGO);\n\n\n assign dec_tlu_ic_diag_pkt.icache_rd_valid = icache_rd_valid_f;\n assign dec_tlu_ic_diag_pkt.icache_wr_valid = icache_wr_valid_f;\n\n // ----------------------------------------------------------------------\n // MTSEL (R/W)\n // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count\n\n assign wr_mtsel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTSEL);\n assign mtsel_ns[1:0] = wr_mtsel_r ? {dec_csr_wrdata_r[1:0]} : mtsel[1:0];\n\n rvdff #(2) mtsel_ff (.*, .clk(csr_wr_clk), .din(mtsel_ns[1:0]), .dout(mtsel[1:0]));\n\n // ----------------------------------------------------------------------\n // MTDATA1 (R/W)\n // [31:0] : Trigger Data 1\n\n // for triggers 0, 1, 2 and 3 aka Match Control\n // [31:28] : type, hard coded to 0x2\n // [27] : dmode\n // [26:21] : hard coded to 0x1f\n // [20] : hit\n // [19] : select (0 - address, 1 - data)\n // [18] : timing, always 'before', reads 0x0\n // [17:12] : action, bits [17:13] not implemented and reads 0x0\n // [11] : chain\n // [10:7] : match, bits [10:8] not implemented and reads 0x0\n // [6] : M\n // [5:3] : not implemented, reads 0x0\n // [2] : execute\n // [1] : store\n // [0] : load\n //\n // decoder ring\n // [27] : => 9\n // [20] : => 8\n // [19] : => 7\n // [12] : => 6\n // [11] : => 5\n // [7] : => 4\n // [6] : => 3\n // [2] : => 2\n // [1] : => 1\n // [0] : => 0\n\n\n // don't allow setting load-data.\n assign tdata_load = dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[19];\n // don't allow setting execute-data.\n assign tdata_opcode = dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[19];\n // don't allow clearing DMODE and action=1\n assign tdata_action = (dec_csr_wrdata_r[27] & dbg_tlu_halted_f) & dec_csr_wrdata_r[12];\n\n // Chain bit has conditions: WARL for triggers without chains. Force to zero if dmode is 0 but next trigger dmode is 1.\n assign tdata_chain = mtsel[0] ? 1'b0 : // triggers 1 and 3 chain bit is always zero\n mtsel[1] ? dec_csr_wrdata_r[11] & ~(mtdata1_t3[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27]) : // trigger 2\n dec_csr_wrdata_r[11] & ~(mtdata1_t1[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27]); // trigger 0\n\n // Kill mtdata1 write if dmode=1 but prior trigger has dmode=0/chain=1. Only applies to T1 and T3\n assign tdata_kill_write = mtsel[1] ? dec_csr_wrdata_r[27] & (~mtdata1_t2[MTDATA1_DMODE] & mtdata1_t2[MTDATA1_CHAIN]) : // trigger 3\n dec_csr_wrdata_r[27] & (~mtdata1_t0[MTDATA1_DMODE] & mtdata1_t0[MTDATA1_CHAIN]) ; // trigger 1\n\n\n assign tdata_wrdata_r[9:0] = {dec_csr_wrdata_r[27] & dbg_tlu_halted_f,\n dec_csr_wrdata_r[20:19],\n tdata_action,\n tdata_chain,\n dec_csr_wrdata_r[7:6],\n tdata_opcode,\n dec_csr_wrdata_r[1],\n tdata_load};\n\n // If the DMODE bit is set, tdata1 can only be updated in debug_mode\n assign wr_mtdata1_t0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b0) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f);\n assign mtdata1_t0_ns[9:0] = wr_mtdata1_t0_r ? tdata_wrdata_r[9:0] :\n {mtdata1_t0[9], update_hit_bit_r[0] | mtdata1_t0[8], mtdata1_t0[7:0]};\n\n assign wr_mtdata1_t1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b01) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f) & ~tdata_kill_write;\n assign mtdata1_t1_ns[9:0] = wr_mtdata1_t1_r ? tdata_wrdata_r[9:0] :\n {mtdata1_t1[9], update_hit_bit_r[1] | mtdata1_t1[8], mtdata1_t1[7:0]};\n\n assign wr_mtdata1_t2_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b10) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f);\n assign mtdata1_t2_ns[9:0] = wr_mtdata1_t2_r ? tdata_wrdata_r[9:0] :\n {mtdata1_t2[9], update_hit_bit_r[2] | mtdata1_t2[8], mtdata1_t2[7:0]};\n\n assign wr_mtdata1_t3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b11) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f) & ~tdata_kill_write;\n assign mtdata1_t3_ns[9:0] = wr_mtdata1_t3_r ? tdata_wrdata_r[9:0] :\n {mtdata1_t3[9], update_hit_bit_r[3] | mtdata1_t3[8], mtdata1_t3[7:0]};\n\n\n rvdffe #(10) mtdata1_t0_ff (.*, .en(trigger_enabled[0] | wr_mtdata1_t0_r), .din(mtdata1_t0_ns[9:0]), .dout(mtdata1_t0[9:0]));\n rvdffe #(10) mtdata1_t1_ff (.*, .en(trigger_enabled[1] | wr_mtdata1_t1_r), .din(mtdata1_t1_ns[9:0]), .dout(mtdata1_t1[9:0]));\n rvdffe #(10) mtdata1_t2_ff (.*, .en(trigger_enabled[2] | wr_mtdata1_t2_r), .din(mtdata1_t2_ns[9:0]), .dout(mtdata1_t2[9:0]));\n rvdffe #(10) mtdata1_t3_ff (.*, .en(trigger_enabled[3] | wr_mtdata1_t3_r), .din(mtdata1_t3_ns[9:0]), .dout(mtdata1_t3[9:0]));\n\n assign mtdata1_tsel_out[31:0] = ( ({32{(mtsel[1:0] == 2'b00)}} & {4'h2, mtdata1_t0[9], 6'b011111, mtdata1_t0[8:7], 6'b0, mtdata1_t0[6:5], 3'b0, mtdata1_t0[4:3], 3'b0, mtdata1_t0[2:0]}) |\n ({32{(mtsel[1:0] == 2'b01)}} & {4'h2, mtdata1_t1[9], 6'b011111, mtdata1_t1[8:7], 6'b0, mtdata1_t1[6:5], 3'b0, mtdata1_t1[4:3], 3'b0, mtdata1_t1[2:0]}) |\n ({32{(mtsel[1:0] == 2'b10)}} & {4'h2, mtdata1_t2[9], 6'b011111, mtdata1_t2[8:7], 6'b0, mtdata1_t2[6:5], 3'b0, mtdata1_t2[4:3], 3'b0, mtdata1_t2[2:0]}) |\n ({32{(mtsel[1:0] == 2'b11)}} & {4'h2, mtdata1_t3[9], 6'b011111, mtdata1_t3[8:7], 6'b0, mtdata1_t3[6:5], 3'b0, mtdata1_t3[4:3], 3'b0, mtdata1_t3[2:0]}));\n\n assign trigger_pkt_any[0].select = mtdata1_t0[MTDATA1_SEL];\n assign trigger_pkt_any[0].match = mtdata1_t0[MTDATA1_MATCH];\n assign trigger_pkt_any[0].store = mtdata1_t0[MTDATA1_ST];\n assign trigger_pkt_any[0].load = mtdata1_t0[MTDATA1_LD];\n assign trigger_pkt_any[0].execute = mtdata1_t0[MTDATA1_EXE];\n assign trigger_pkt_any[0].m = mtdata1_t0[MTDATA1_M_ENABLED];\n\n assign trigger_pkt_any[1].select = mtdata1_t1[MTDATA1_SEL];\n assign trigger_pkt_any[1].match = mtdata1_t1[MTDATA1_MATCH];\n assign trigger_pkt_any[1].store = mtdata1_t1[MTDATA1_ST];\n assign trigger_pkt_any[1].load = mtdata1_t1[MTDATA1_LD];\n assign trigger_pkt_any[1].execute = mtdata1_t1[MTDATA1_EXE];\n assign trigger_pkt_any[1].m = mtdata1_t1[MTDATA1_M_ENABLED];\n\n assign trigger_pkt_any[2].select = mtdata1_t2[MTDATA1_SEL];\n assign trigger_pkt_any[2].match = mtdata1_t2[MTDATA1_MATCH];\n assign trigger_pkt_any[2].store = mtdata1_t2[MTDATA1_ST];\n assign trigger_pkt_any[2].load = mtdata1_t2[MTDATA1_LD];\n assign trigger_pkt_any[2].execute = mtdata1_t2[MTDATA1_EXE];\n assign trigger_pkt_any[2].m = mtdata1_t2[MTDATA1_M_ENABLED];\n\n assign trigger_pkt_any[3].select = mtdata1_t3[MTDATA1_SEL];\n assign trigger_pkt_any[3].match = mtdata1_t3[MTDATA1_MATCH];\n assign trigger_pkt_any[3].store = mtdata1_t3[MTDATA1_ST];\n assign trigger_pkt_any[3].load = mtdata1_t3[MTDATA1_LD];\n assign trigger_pkt_any[3].execute = mtdata1_t3[MTDATA1_EXE];\n assign trigger_pkt_any[3].m = mtdata1_t3[MTDATA1_M_ENABLED];\n\n\n\n\n\n // ----------------------------------------------------------------------\n // MTDATA2 (R/W)\n // [31:0] : Trigger Data 2\n\n // If the DMODE bit is set, tdata2 can only be updated in debug_mode\n assign wr_mtdata2_t0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b0) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f);\n assign wr_mtdata2_t1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b01) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f);\n assign wr_mtdata2_t2_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b10) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f);\n assign wr_mtdata2_t3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b11) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f);\n\n rvdffe #(32) mtdata2_t0_ff (.*, .en(wr_mtdata2_t0_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t0[31:0]));\n rvdffe #(32) mtdata2_t1_ff (.*, .en(wr_mtdata2_t1_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t1[31:0]));\n rvdffe #(32) mtdata2_t2_ff (.*, .en(wr_mtdata2_t2_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t2[31:0]));\n rvdffe #(32) mtdata2_t3_ff (.*, .en(wr_mtdata2_t3_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t3[31:0]));\n\n assign mtdata2_tsel_out[31:0] = ( ({32{(mtsel[1:0] == 2'b00)}} & mtdata2_t0[31:0]) |\n ({32{(mtsel[1:0] == 2'b01)}} & mtdata2_t1[31:0]) |\n ({32{(mtsel[1:0] == 2'b10)}} & mtdata2_t2[31:0]) |\n ({32{(mtsel[1:0] == 2'b11)}} & mtdata2_t3[31:0]));\n\n assign trigger_pkt_any[0].tdata2[31:0] = mtdata2_t0[31:0];\n assign trigger_pkt_any[1].tdata2[31:0] = mtdata2_t1[31:0];\n assign trigger_pkt_any[2].tdata2[31:0] = mtdata2_t2[31:0];\n assign trigger_pkt_any[3].tdata2[31:0] = mtdata2_t3[31:0];\n\n\n //----------------------------------------------------------------------\n // Performance Monitor Counters section starts\n //----------------------------------------------------------------------\n localparam MHPME_NOEVENT = 10'd0;\n localparam MHPME_CLK_ACTIVE = 10'd1; // OOP - out of pipe\n localparam MHPME_ICACHE_HIT = 10'd2; // OOP\n localparam MHPME_ICACHE_MISS = 10'd3; // OOP\n localparam MHPME_INST_COMMIT = 10'd4;\n localparam MHPME_INST_COMMIT_16B = 10'd5;\n localparam MHPME_INST_COMMIT_32B = 10'd6;\n localparam MHPME_INST_ALIGNED = 10'd7; // OOP\n localparam MHPME_INST_DECODED = 10'd8; // OOP\n localparam MHPME_INST_MUL = 10'd9;\n localparam MHPME_INST_DIV = 10'd10;\n localparam MHPME_INST_LOAD = 10'd11;\n localparam MHPME_INST_STORE = 10'd12;\n localparam MHPME_INST_MALOAD = 10'd13;\n localparam MHPME_INST_MASTORE = 10'd14;\n localparam MHPME_INST_ALU = 10'd15;\n localparam MHPME_INST_CSRREAD = 10'd16;\n localparam MHPME_INST_CSRRW = 10'd17;\n localparam MHPME_INST_CSRWRITE = 10'd18;\n localparam MHPME_INST_EBREAK = 10'd19;\n localparam MHPME_INST_ECALL = 10'd20;\n localparam MHPME_INST_FENCE = 10'd21;\n localparam MHPME_INST_FENCEI = 10'd22;\n localparam MHPME_INST_MRET = 10'd23;\n localparam MHPME_INST_BRANCH = 10'd24;\n localparam MHPME_BRANCH_MP = 10'd25;\n localparam MHPME_BRANCH_TAKEN = 10'd26;\n localparam MHPME_BRANCH_NOTP = 10'd27;\n localparam MHPME_FETCH_STALL = 10'd28; // OOP\n localparam MHPME_DECODE_STALL = 10'd30; // OOP\n localparam MHPME_POSTSYNC_STALL = 10'd31; // OOP\n localparam MHPME_PRESYNC_STALL = 10'd32; // OOP\n localparam MHPME_LSU_SB_WB_STALL = 10'd34; // OOP\n localparam MHPME_DMA_DCCM_STALL = 10'd35; // OOP\n localparam MHPME_DMA_ICCM_STALL = 10'd36; // OOP\n localparam MHPME_EXC_TAKEN = 10'd37;\n localparam MHPME_TIMER_INT_TAKEN = 10'd38;\n localparam MHPME_EXT_INT_TAKEN = 10'd39;\n localparam MHPME_FLUSH_LOWER = 10'd40;\n localparam MHPME_BR_ERROR = 10'd41;\n localparam MHPME_IBUS_TRANS = 10'd42; // OOP\n localparam MHPME_DBUS_TRANS = 10'd43; // OOP\n localparam MHPME_DBUS_MA_TRANS = 10'd44; // OOP\n localparam MHPME_IBUS_ERROR = 10'd45; // OOP\n localparam MHPME_DBUS_ERROR = 10'd46; // OOP\n localparam MHPME_IBUS_STALL = 10'd47; // OOP\n localparam MHPME_DBUS_STALL = 10'd48; // OOP\n localparam MHPME_INT_DISABLED = 10'd49; // OOP\n localparam MHPME_INT_STALLED = 10'd50; // OOP\n localparam MHPME_INST_BITMANIP = 10'd54;\n localparam MHPME_DBUS_LOAD = 10'd55;\n localparam MHPME_DBUS_STORE = 10'd56;\n // Counts even during sleep state\n localparam MHPME_SLEEP_CYC = 10'd512; // OOP\n localparam MHPME_DMA_READ_ALL = 10'd513; // OOP\n localparam MHPME_DMA_WRITE_ALL = 10'd514; // OOP\n localparam MHPME_DMA_READ_DCCM = 10'd515; // OOP\n localparam MHPME_DMA_WRITE_DCCM = 10'd516; // OOP\n\n // Pack the event selects into a vector for genvar\n assign mhpme_vec[0][9:0] = mhpme3[9:0];\n assign mhpme_vec[1][9:0] = mhpme4[9:0];\n assign mhpme_vec[2][9:0] = mhpme5[9:0];\n assign mhpme_vec[3][9:0] = mhpme6[9:0];\n\n // only consider committed itypes\n //logic [3:0] pmu_i0_itype_qual;\n assign pmu_i0_itype_qual[3:0] = dec_tlu_packet_r.pmu_i0_itype[3:0] & {4{tlu_i0_commit_cmt}};\n\n // Generate the muxed incs for all counters based on event type\n for (genvar i=0 ; i < 4; i++) begin\n assign mhpmc_inc_r[i] = {{~mcountinhibit[i+3]}} &\n (\n ({1{(mhpme_vec[i][9:0] == MHPME_CLK_ACTIVE )}} & 1'b1) |\n ({1{(mhpme_vec[i][9:0] == MHPME_ICACHE_HIT )}} & {ifu_pmu_ic_hit}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_ICACHE_MISS )}} & {ifu_pmu_ic_miss}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT )}} & {tlu_i0_commit_cmt & ~illegal_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT_16B )}} & {tlu_i0_commit_cmt & ~exu_pmu_i0_pc4 & ~illegal_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT_32B )}} & {tlu_i0_commit_cmt & exu_pmu_i0_pc4 & ~illegal_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_ALIGNED )}} & ifu_pmu_instr_aligned) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_DECODED )}} & dec_pmu_instr_decoded) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_MUL )}} & {(pmu_i0_itype_qual == MUL)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_DIV )}} & {dec_tlu_packet_r.pmu_divide & tlu_i0_commit_cmt & ~illegal_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_LOAD )}} & {(pmu_i0_itype_qual == LOAD)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_STORE )}} & {(pmu_i0_itype_qual == STORE)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_MALOAD )}} & {(pmu_i0_itype_qual == LOAD)} &\n {1{dec_tlu_packet_r.pmu_lsu_misaligned}}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_MASTORE )}} & {(pmu_i0_itype_qual == STORE)} &\n {1{dec_tlu_packet_r.pmu_lsu_misaligned}}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_ALU )}} & {(pmu_i0_itype_qual == ALU)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_CSRREAD )}} & {(pmu_i0_itype_qual == CSRREAD)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_CSRWRITE )}} & {(pmu_i0_itype_qual == CSRWRITE)})|\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_CSRRW )}} & {(pmu_i0_itype_qual == CSRRW)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_EBREAK )}} & {(pmu_i0_itype_qual == EBREAK)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_ECALL )}} & {(pmu_i0_itype_qual == ECALL)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_FENCE )}} & {(pmu_i0_itype_qual == FENCE)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_FENCEI )}} & {(pmu_i0_itype_qual == FENCEI)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_MRET )}} & {(pmu_i0_itype_qual == MRET)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_BRANCH )}} & {\n ((pmu_i0_itype_qual == CONDBR) | (pmu_i0_itype_qual == JAL))}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_BRANCH_MP )}} & {exu_pmu_i0_br_misp & tlu_i0_commit_cmt & ~illegal_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_BRANCH_TAKEN )}} & {exu_pmu_i0_br_ataken & tlu_i0_commit_cmt & ~illegal_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_BRANCH_NOTP )}} & {dec_tlu_packet_r.pmu_i0_br_unpred & tlu_i0_commit_cmt & ~illegal_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_FETCH_STALL )}} & { ifu_pmu_fetch_stall}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DECODE_STALL )}} & { dec_pmu_decode_stall}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_POSTSYNC_STALL )}} & {dec_pmu_postsync_stall}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_PRESYNC_STALL )}} & {dec_pmu_presync_stall}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_LSU_SB_WB_STALL )}} & { lsu_store_stall_any}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DMA_DCCM_STALL )}} & { dma_dccm_stall_any}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DMA_ICCM_STALL )}} & { dma_iccm_stall_any}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_EXC_TAKEN )}} & { (i0_exception_valid_r | i0_trigger_hit_r | lsu_exc_valid_r)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_TIMER_INT_TAKEN )}} & { take_timer_int | take_int_timer0_int | take_int_timer1_int}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_EXT_INT_TAKEN )}} & { take_ext_int}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_FLUSH_LOWER )}} & { tlu_flush_lower_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_BR_ERROR )}} & {(dec_tlu_br0_error_r | dec_tlu_br0_start_error_r) & rfpc_i0_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_IBUS_TRANS )}} & {ifu_pmu_bus_trxn}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_TRANS )}} & {lsu_pmu_bus_trxn}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_MA_TRANS )}} & {lsu_pmu_bus_misaligned}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_IBUS_ERROR )}} & {ifu_pmu_bus_error}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_ERROR )}} & {lsu_pmu_bus_error}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_IBUS_STALL )}} & {ifu_pmu_bus_busy}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_STALL )}} & {lsu_pmu_bus_busy}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INT_DISABLED )}} & {~mstatus[MSTATUS_MIE]}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INT_STALLED )}} & {~mstatus[MSTATUS_MIE] & |(mip[5:0] & mie[5:0])}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_INST_BITMANIP )}} & {(pmu_i0_itype_qual == BITMANIPU)}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_LOAD )}} & {tlu_i0_commit_cmt & lsu_pmu_load_external_r & ~illegal_r}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_STORE )}} & {tlu_i0_commit_cmt & lsu_pmu_store_external_r & ~illegal_r}) |\n // These count even during sleep\n ({1{(mhpme_vec[i][9:0] == MHPME_SLEEP_CYC )}} & {dec_tlu_pmu_fw_halted}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DMA_READ_ALL )}} & {dma_pmu_any_read}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DMA_WRITE_ALL )}} & {dma_pmu_any_write}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DMA_READ_DCCM )}} & {dma_pmu_dccm_read}) |\n ({1{(mhpme_vec[i][9:0] == MHPME_DMA_WRITE_DCCM )}} & {dma_pmu_dccm_write})\n );\n end\n\n\n if(pt.FAST_INTERRUPT_REDIRECT) begin : genblock2\n\n`ifdef RV_USER_MODE\n rvdffie #(33) mstatus_ff (.*, .clk(free_l2clk),\n .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,\n take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze,\n mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in,\n minstret_enable, minstretl_cout_ns, fw_halted_ns,\n meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted,\n mstatus_ns[3:0]}),\n .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1,\n take_ext_int_start_d1, take_ext_int_start_d2, take_ext_int_start_d3, ext_int_freeze_d1,\n mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f,\n fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f,\n mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,\n mstatus[3:0]}));\n`else\n rvdffie #(31) mstatus_ff (.*, .clk(free_l2clk),\n .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,\n take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze,\n mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in,\n minstret_enable, minstretl_cout_ns, fw_halted_ns,\n meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted,\n mstatus_ns[1:0]}),\n .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1,\n take_ext_int_start_d1, take_ext_int_start_d2, take_ext_int_start_d3, ext_int_freeze_d1,\n mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f,\n fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f,\n mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,\n mstatus[1:0]}));\n\n`endif\n\n end\n else begin : genblock2\n`ifdef RV_USER_MODE\n rvdffie #(29) mstatus_ff (.*, .clk(free_l2clk),\n .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,\n mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in,\n minstret_enable, minstretl_cout_ns, fw_halted_ns,\n meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted,\n mstatus_ns[3:0]}),\n .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1,\n mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f,\n fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f,\n mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,\n mstatus[3:0]}));\n`else\n rvdffie #(27) mstatus_ff (.*, .clk(free_l2clk),\n .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,\n mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in,\n minstret_enable, minstretl_cout_ns, fw_halted_ns,\n meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted,\n mstatus_ns[1:0]}),\n .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1,\n mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f,\n fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f,\n mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,\n mstatus[1:0]}));\n`endif\n end\n\n assign perfcnt_halted = ((dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted);\n assign perfcnt_during_sleep[3:0] = {4{~(dec_tlu_dbg_halted & dcsr[DCSR_STOPC])}} & {mhpme_vec[3][9],mhpme_vec[2][9],mhpme_vec[1][9],mhpme_vec[0][9]};\n\n assign dec_tlu_perfcnt0 = mhpmc_inc_r_d1[0] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[0]);\n assign dec_tlu_perfcnt1 = mhpmc_inc_r_d1[1] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[1]);\n assign dec_tlu_perfcnt2 = mhpmc_inc_r_d1[2] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[2]);\n assign dec_tlu_perfcnt3 = mhpmc_inc_r_d1[3] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[3]);\n\n // ----------------------------------------------------------------------\n // MHPMC3H(RW), MHPMC3(RW)\n // [63:32][31:0] : Hardware Performance Monitor Counter 3\n\n assign mhpmc3_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3);\n assign mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[0]) & (|(mhpmc_inc_r[0]));\n assign mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1;\n assign mhpmc3_incr[63:0] = {mhpmc3h[31:0],mhpmc3[31:0]} + {63'b0, 1'b1};\n assign mhpmc3_ns[31:0] = mhpmc3_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[31:0];\n rvdffe #(32) mhpmc3_ff (.*, .clk(free_l2clk), .en(mhpmc3_wr_en), .din(mhpmc3_ns[31:0]), .dout(mhpmc3[31:0]));\n\n assign mhpmc3h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3H);\n assign mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1;\n assign mhpmc3h_ns[31:0] = mhpmc3h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[63:32];\n rvdffe #(32) mhpmc3h_ff (.*, .clk(free_l2clk), .en(mhpmc3h_wr_en), .din(mhpmc3h_ns[31:0]), .dout(mhpmc3h[31:0]));\n\n // ----------------------------------------------------------------------\n // MHPMC4H(RW), MHPMC4(RW)\n // [63:32][31:0] : Hardware Performance Monitor Counter 4\n\n assign mhpmc4_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4);\n assign mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[1]) & (|(mhpmc_inc_r[1]));\n assign mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1;\n assign mhpmc4_incr[63:0] = {mhpmc4h[31:0],mhpmc4[31:0]} + {63'b0,1'b1};\n assign mhpmc4_ns[31:0] = mhpmc4_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[31:0];\n rvdffe #(32) mhpmc4_ff (.*, .clk(free_l2clk), .en(mhpmc4_wr_en), .din(mhpmc4_ns[31:0]), .dout(mhpmc4[31:0]));\n\n assign mhpmc4h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4H);\n assign mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1;\n assign mhpmc4h_ns[31:0] = mhpmc4h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[63:32];\n rvdffe #(32) mhpmc4h_ff (.*, .clk(free_l2clk), .en(mhpmc4h_wr_en), .din(mhpmc4h_ns[31:0]), .dout(mhpmc4h[31:0]));\n\n // ----------------------------------------------------------------------\n // MHPMC5H(RW), MHPMC5(RW)\n // [63:32][31:0] : Hardware Performance Monitor Counter 5\n\n assign mhpmc5_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5);\n assign mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[2]) & (|(mhpmc_inc_r[2]));\n assign mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1;\n assign mhpmc5_incr[63:0] = {mhpmc5h[31:0],mhpmc5[31:0]} + {63'b0,1'b1};\n assign mhpmc5_ns[31:0] = mhpmc5_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[31:0];\n rvdffe #(32) mhpmc5_ff (.*, .clk(free_l2clk), .en(mhpmc5_wr_en), .din(mhpmc5_ns[31:0]), .dout(mhpmc5[31:0]));\n\n assign mhpmc5h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5H);\n assign mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1;\n assign mhpmc5h_ns[31:0] = mhpmc5h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[63:32];\n rvdffe #(32) mhpmc5h_ff (.*, .clk(free_l2clk), .en(mhpmc5h_wr_en), .din(mhpmc5h_ns[31:0]), .dout(mhpmc5h[31:0]));\n\n // ----------------------------------------------------------------------\n // MHPMC6H(RW), MHPMC6(RW)\n // [63:32][31:0] : Hardware Performance Monitor Counter 6\n\n assign mhpmc6_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6);\n assign mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[3]) & (|(mhpmc_inc_r[3]));\n assign mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1;\n assign mhpmc6_incr[63:0] = {mhpmc6h[31:0],mhpmc6[31:0]} + {63'b0,1'b1};\n assign mhpmc6_ns[31:0] = mhpmc6_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[31:0];\n rvdffe #(32) mhpmc6_ff (.*, .clk(free_l2clk), .en(mhpmc6_wr_en), .din(mhpmc6_ns[31:0]), .dout(mhpmc6[31:0]));\n\n assign mhpmc6h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6H);\n assign mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1;\n assign mhpmc6h_ns[31:0] = mhpmc6h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[63:32];\n rvdffe #(32) mhpmc6h_ff (.*, .clk(free_l2clk), .en(mhpmc6h_wr_en), .din(mhpmc6h_ns[31:0]), .dout(mhpmc6h[31:0]));\n\n // ----------------------------------------------------------------------\n // MHPME3(RW)\n // [9:0] : Hardware Performance Monitor Event 3\n\n // we only have events 0-56 with holes, 512-516, HPME* are WARL so zero otherwise.\n assign zero_event_r = ( (dec_csr_wrdata_r[9:0] > 10'd516) |\n (|dec_csr_wrdata_r[31:10]) |\n ((dec_csr_wrdata_r[9:0] < 10'd512) & (dec_csr_wrdata_r[9:0] > 10'd56)) |\n ((dec_csr_wrdata_r[9:0] < 10'd54) & (dec_csr_wrdata_r[9:0] > 10'd50)) |\n (dec_csr_wrdata_r[9:0] == 10'd29) |\n (dec_csr_wrdata_r[9:0] == 10'd33)\n );\n\n assign event_r[9:0] = zero_event_r ? '0 : dec_csr_wrdata_r[9:0];\n\n assign wr_mhpme3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME3);\n rvdffe #(10) mhpme3_ff (.*, .en(wr_mhpme3_r), .din(event_r[9:0]), .dout(mhpme3[9:0]));\n // ----------------------------------------------------------------------\n // MHPME4(RW)\n // [9:0] : Hardware Performance Monitor Event 4\n\n assign wr_mhpme4_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME4);\n rvdffe #(10) mhpme4_ff (.*, .en(wr_mhpme4_r), .din(event_r[9:0]), .dout(mhpme4[9:0]));\n // ----------------------------------------------------------------------\n // MHPME5(RW)\n // [9:0] : Hardware Performance Monitor Event 5\n\n assign wr_mhpme5_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME5);\n rvdffe #(10) mhpme5_ff (.*, .en(wr_mhpme5_r), .din(event_r[9:0]), .dout(mhpme5[9:0]));\n // ----------------------------------------------------------------------\n // MHPME6(RW)\n // [9:0] : Hardware Performance Monitor Event 6\n\n assign wr_mhpme6_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME6);\n rvdffe #(10) mhpme6_ff (.*, .en(wr_mhpme6_r), .din(event_r[9:0]), .dout(mhpme6[9:0]));\n\n //----------------------------------------------------------------------\n // Performance Monitor Counters section ends\n //----------------------------------------------------------------------\n // ----------------------------------------------------------------------\n\n // ----------------------------------------------------------------------\n // MCOUNTEREN\n // [31:3] : Reserved, read 0x0\n // [2] : INSTRET user-mode access disable\n // [1] : reserved, read 0x0\n // [0] : CYCLE user-mode access disable\n\n`ifdef RV_USER_MODE\n\n localparam MCOUNTEREN = 12'h306;\n\n assign wr_mcounteren_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCOUNTEREN);\n rvdffs #(6) mcounteren_ff (.*, .clk(csr_wr_clk), .en(wr_mcounteren_r), .din({dec_csr_wrdata_r[6:2], dec_csr_wrdata_r[0]}), .dout(mcounteren));\n\n`endif\n\n // MCOUNTINHIBIT(RW)\n // [31:7] : Reserved, read 0x0\n // [6] : HPM6 disable\n // [5] : HPM5 disable\n // [4] : HPM4 disable\n // [3] : HPM3 disable\n // [2] : MINSTRET disable\n // [1] : reserved, read 0x0\n // [0] : MCYCLE disable\n\n assign wr_mcountinhibit_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCOUNTINHIBIT);\n rvdffs #(6) mcountinhibit_ff (.*, .clk(csr_wr_clk), .en(wr_mcountinhibit_r), .din({dec_csr_wrdata_r[6:2], dec_csr_wrdata_r[0]}), .dout({mcountinhibit[6:2], mcountinhibit[0]}));\n assign mcountinhibit[1] = 1'b0;\n\n //--------------------------------------------------------------------------------\n // trace\n //--------------------------------------------------------------------------------\n logic [4:0] dec_tlu_exc_cause_wb1_raw, dec_tlu_exc_cause_wb2;\n logic dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2;\n\n assign {dec_tlu_i0_valid_wb1,\n dec_tlu_i0_exc_valid_wb1,\n dec_tlu_exc_cause_wb1_raw[4:0],\n dec_tlu_int_valid_wb1_raw} = {8{~dec_tlu_trace_disable}} & {i0_valid_wb,\n i0_exception_valid_r_d1 | lsu_i0_exc_r_d1 | (trigger_hit_r_d1 & ~trigger_hit_dmode_r_d1),\n exc_cause_wb[4:0],\n interrupt_valid_r_d1};\n\n\n\n // skid buffer for ints, reduces trace port count by 1\n rvdffie #(.WIDTH(6), .OVERRIDE(1)) traceskidff (.*, .clk(clk),\n .din ({dec_tlu_exc_cause_wb1_raw[4:0],\n dec_tlu_int_valid_wb1_raw}),\n .dout({dec_tlu_exc_cause_wb2[4:0],\n dec_tlu_int_valid_wb2}));\n //skid for ints\n assign dec_tlu_exc_cause_wb1[4:0] = dec_tlu_int_valid_wb2 ? dec_tlu_exc_cause_wb2[4:0] : dec_tlu_exc_cause_wb1_raw[4:0];\n assign dec_tlu_int_valid_wb1 = dec_tlu_int_valid_wb2;\n\n assign dec_tlu_mtval_wb1 = mtval[31:0];\n\n // end trace\n //--------------------------------------------------------------------------------\n\n\n // ----------------------------------------------------------------------\n // CSR read mux\n // ----------------------------------------------------------------------\n\nassign dec_tlu_presync_d = presync & dec_csr_any_unq_d & ~dec_csr_wen_unq_d;\nassign dec_tlu_postsync_d = postsync & dec_csr_any_unq_d;\n\n // allow individual configuration of these features\nassign conditionally_illegal = ((csr_mitcnt0 | csr_mitcnt1 | csr_mitb0 | csr_mitb1 | csr_mitctl0 | csr_mitctl1) & ~|pt.TIMER_LEGAL_EN);\n\nassign valid_csr = ( legal & (~(csr_dcsr | csr_dpc | csr_dmst | csr_dicawics | csr_dicad0 | csr_dicad0h | csr_dicad1 | csr_dicago) | dbg_tlu_halted_f)\n & ~fast_int_meicpct & ~conditionally_illegal);\n\nassign dec_csr_legal_d = ( dec_csr_any_unq_d &\n valid_csr & // of a valid CSR\n ~(dec_csr_wen_unq_d & (csr_mvendorid | csr_marchid | csr_mimpid | csr_mhartid | csr_mdseac | csr_meihap)) // that's not a write to a RO CSR\n );\n // CSR read mux\nlogic [31:0] mstatus_rf, mie_rf, mtvec_rf, mscratch_rf, mepc_rf, mcause_rf, mtval_rf, mip_rf, mcyclel_rf, mcycleh_rf, minstretl_rf, minstreth_rf, mrac_rf;\n`ifdef RV_USER_MODE\nassign mstatus_rf = {14'b0, mstatus[MSTATUS_MPRV], 4'b0, ~mstatus[MSTATUS_MPP], ~mstatus[MSTATUS_MPP], 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0};\n`else\nassign mstatus_rf = {19'b0, 2'b11, 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0};\n`endif\nassign mie_rf = {1'b0, mie[5:3], 16'b0, mie[2], 3'b0, mie[1], 3'b0, mie[0], 3'b0};\nassign mtvec_rf = {mtvec[30:1], 1'b0, mtvec[0]};\nassign mscratch_rf = mscratch[31:0];\nassign mepc_rf = {mepc[31:1], 1'b0};\nassign mcause_rf = mcause[31:0];\nassign mtval_rf = mtval[31:0];\nassign mip_rf = {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0};\nassign mcyclel_rf = mcyclel[31:0];\nassign mcycleh_rf = mcycleh_inc[31:0];\nassign minstretl_rf = minstretl_read[31:0];\nassign minstreth_rf = minstreth_read[31:0];\nassign mrac_rf = mrac[31:0];\n\nassign dec_csr_rddata_d[31:0] = (\n`ifdef RV_USER_MODE\n ({32{csr_misa}} & 32'h40101104) |\n`else\n ({32{csr_misa}} & 32'h40001104) |\n`endif\n ({32{csr_mvendorid}} & 32'h00000045) |\n ({32{csr_marchid}} & 32'h00000010) |\n ({32{csr_mimpid}} & 32'h4) |\n ({32{csr_mhartid}} & {core_id[31:4], 4'b0}) |\n ({32{csr_mstatus}} & mstatus_rf[31:0]) |\n ({32{csr_mtvec}} & mtvec_rf) |\n ({32{csr_mip}} & mip_rf) |\n ({32{csr_mie}} & mie_rf) |\n ({32{csr_mcyclel}} & mcyclel_rf) |\n ({32{csr_mcycleh}} & mcycleh_rf) |\n ({32{csr_minstretl}} & minstretl_rf) |\n ({32{csr_minstreth}} & minstreth_rf) |\n ({32{csr_mscratch}} & mscratch_rf) |\n ({32{csr_mepc}} & mepc_rf) |\n ({32{csr_mcause}} & mcause_rf) |\n ({32{csr_mscause}} & {28'b0, mscause[3:0]}) |\n ({32{csr_mtval}} & mtval_rf) |\n ({32{csr_mrac}} & mrac_rf) |\n ({32{csr_mdseac}} & mdseac[31:0]) |\n ({32{csr_meivt}} & {meivt[31:10], 10'b0}) |\n ({32{csr_meihap}} & {meivt[31:10], meihap[9:2], 2'b0}) |\n ({32{csr_meicurpl}} & {28'b0, meicurpl[3:0]}) |\n ({32{csr_meicidpl}} & {28'b0, meicidpl[3:0]}) |\n ({32{csr_meipt}} & {28'b0, meipt[3:0]}) |\n ({32{csr_mcgc}} & {22'b0, mcgc[9:0]}) |\n ({32{csr_mfdc}} & {13'b0, mfdc[18:0]}) |\n ({32{csr_dcsr}} & {16'h4000, dcsr[15:2], 2'b11}) |\n ({32{csr_dpc}} & {dpc[31:1], 1'b0}) |\n ({32{csr_dicad0}} & dicad0[31:0]) |\n ({32{csr_dicad0h}} & dicad0h[31:0]) |\n ({32{csr_dicad1}} & dicad1[31:0]) |\n ({32{csr_dicawics}} & {7'b0, dicawics[16], 2'b0, dicawics[15:14], 3'b0, dicawics[13:0], 3'b0}) |\n ({32{csr_mtsel}} & {30'b0, mtsel[1:0]}) |\n ({32{csr_mtdata1}} & {mtdata1_tsel_out[31:0]}) |\n ({32{csr_mtdata2}} & {mtdata2_tsel_out[31:0]}) |\n ({32{csr_micect}} & {micect[31:0]}) |\n ({32{csr_miccmect}} & {miccmect[31:0]}) |\n ({32{csr_mdccmect}} & {mdccmect[31:0]}) |\n ({32{csr_mhpmc3}} & mhpmc3[31:0]) |\n ({32{csr_mhpmc4}} & mhpmc4[31:0]) |\n ({32{csr_mhpmc5}} & mhpmc5[31:0]) |\n ({32{csr_mhpmc6}} & mhpmc6[31:0]) |\n ({32{csr_mhpmc3h}} & mhpmc3h[31:0]) |\n ({32{csr_mhpmc4h}} & mhpmc4h[31:0]) |\n ({32{csr_mhpmc5h}} & mhpmc5h[31:0]) |\n ({32{csr_mhpmc6h}} & mhpmc6h[31:0]) |\n ({32{csr_mfdht}} & {26'b0, mfdht[5:0]}) |\n ({32{csr_mfdhs}} & {30'b0, mfdhs[1:0]}) |\n ({32{csr_mhpme3}} & {22'b0,mhpme3[9:0]}) |\n ({32{csr_mhpme4}} & {22'b0,mhpme4[9:0]}) |\n ({32{csr_mhpme5}} & {22'b0,mhpme5[9:0]}) |\n ({32{csr_mhpme6}} & {22'b0,mhpme6[9:0]}) |\n`ifdef RV_USER_MODE\n ({32{csr_menvcfg}} & 32'd0) |\n ({32{csr_menvcfgh}} & 32'd0) |\n ({32{csr_mcounteren}} & {25'b0, mcounteren[5:1], 1'b0, mcounteren[0]}) |\n ({32{csr_cyclel}} & mcyclel[31:0]) |\n ({32{csr_cycleh}} & mcycleh_inc[31:0]) |\n ({32{csr_instretl}} & minstretl_read[31:0]) |\n ({32{csr_instreth}} & minstreth_read[31:0]) |\n ({32{csr_hpmc3}} & mhpmc3[31:0]) |\n ({32{csr_hpmc4}} & mhpmc4[31:0]) |\n ({32{csr_hpmc5}} & mhpmc5[31:0]) |\n ({32{csr_hpmc6}} & mhpmc6[31:0]) |\n ({32{csr_hpmc3h}} & mhpmc3h[31:0]) |\n ({32{csr_hpmc4h}} & mhpmc4h[31:0]) |\n ({32{csr_hpmc5h}} & mhpmc5h[31:0]) |\n ({32{csr_hpmc6h}} & mhpmc6h[31:0]) |\n ({32{csr_mseccfgl}} & {29'd0, mseccfg}) |\n ({32{csr_mseccfgh}} & 32'd0) | // All bits are WPRI\n`endif\n ({32{csr_mcountinhibit}} & {25'b0, mcountinhibit[6:0]}) |\n ({32{csr_mpmc}} & {30'b0, mpmc[1], 1'b0}) |\n ({32{dec_timer_read_d}} & dec_timer_rddata_d[31:0]) |\n ({32{dec_pmp_read_d}} & dec_pmp_rddata_d[31:0])\n );\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n // Expose the register file\n assign regfile.tlu.pc = pc_r;\n assign regfile.tlu.npc = npc_r;\n assign regfile.tlu.mstatus = mstatus_rf;\n assign regfile.tlu.mie = mie_rf;\n assign regfile.tlu.mtvec = mtvec_rf;\n assign regfile.tlu.mscratch = mscratch_rf;\n assign regfile.tlu.mepc = mepc_rf;\n assign regfile.tlu.mcause = mcause_rf;\n assign regfile.tlu.mtval = mtval_rf;\n assign regfile.tlu.mip = mip_rf;\n assign regfile.tlu.mcyclel = mcyclel_rf;\n assign regfile.tlu.mcycleh = mcycleh_rf;\n assign regfile.tlu.minstretl = minstretl_rf;\n assign regfile.tlu.minstreth = minstreth_rf;\n assign regfile.tlu.mrac = mrac_rf;\n`endif\n\nendmodule // el2_dec_tlu_ctl\n\nmodule el2_dec_timer_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic clk,\n input logic free_l2clk,\n input logic csr_wr_clk,\n input logic rst_l,\n input logic dec_csr_wen_r_mod, // csr write enable at wb\n input logic [11:0] dec_csr_wraddr_r, // write address for csr\n input logic [31:0] dec_csr_wrdata_r, // csr write data at wb\n\n input logic csr_mitctl0,\n input logic csr_mitctl1,\n input logic csr_mitb0,\n input logic csr_mitb1,\n input logic csr_mitcnt0,\n input logic csr_mitcnt1,\n\n\n input logic dec_pause_state, // Paused\n input logic dec_tlu_pmu_fw_halted, // pmu/fw halted\n input logic internal_dbg_halt_timers, // debug halted\n\n output logic [31:0] dec_timer_rddata_d, // timer CSR read data\n output logic dec_timer_read_d, // timer CSR address match\n output logic dec_timer_t0_pulse, // timer0 int\n output logic dec_timer_t1_pulse, // timer1 int\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n );\n localparam MITCTL_ENABLE = 0;\n localparam MITCTL_ENABLE_HALTED = 1;\n localparam MITCTL_ENABLE_PAUSED = 2;\n\n logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;\n logic [2:0] mitctl0_ns, mitctl0;\n logic [3:0] mitctl1_ns, mitctl1;\n logic wr_mitcnt0_r, wr_mitcnt1_r, wr_mitb0_r, wr_mitb1_r, wr_mitctl0_r, wr_mitctl1_r;\n logic mitcnt0_inc_ok, mitcnt1_inc_ok;\n logic mitcnt0_inc_cout, mitcnt1_inc_cout;\n logic mit0_match_ns;\n logic mit1_match_ns;\n logic mitctl0_0_b_ns;\n logic mitctl0_0_b;\n logic mitctl1_0_b_ns;\n logic mitctl1_0_b;\n\n assign mit0_match_ns = (mitcnt0[31:0] >= mitb0[31:0]);\n assign mit1_match_ns = (mitcnt1[31:0] >= mitb1[31:0]);\n\n assign dec_timer_t0_pulse = mit0_match_ns;\n assign dec_timer_t1_pulse = mit1_match_ns;\n // ----------------------------------------------------------------------\n // MITCNT0 (RW)\n // [31:0] : Internal Timer Counter 0\n\n localparam MITCNT0 = 12'h7d2;\n\n assign wr_mitcnt0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT0);\n\n assign mitcnt0_inc_ok = mitctl0[MITCTL_ENABLE] & (~dec_pause_state | mitctl0[MITCTL_ENABLE_PAUSED]) & (~dec_tlu_pmu_fw_halted | mitctl0[MITCTL_ENABLE_HALTED]) & ~internal_dbg_halt_timers;\n\n assign {mitcnt0_inc_cout, mitcnt0_inc[7:0]} = mitcnt0[7:0] + {7'b0, 1'b1};\n assign mitcnt0_inc[31:8] = mitcnt0[31:8] + {23'b0, mitcnt0_inc_cout};\n\n assign mitcnt0_ns[31:0] = wr_mitcnt0_r ? dec_csr_wrdata_r[31:0] : mit0_match_ns ? 'b0 : mitcnt0_inc[31:0];\n\n rvdffe #(24) mitcnt0_ffb (.*, .clk(free_l2clk), .en(wr_mitcnt0_r | (mitcnt0_inc_ok & mitcnt0_inc_cout) | mit0_match_ns), .din(mitcnt0_ns[31:8]), .dout(mitcnt0[31:8]));\n rvdffe #(8) mitcnt0_ffa (.*, .clk(free_l2clk), .en(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns), .din(mitcnt0_ns[7:0]), .dout(mitcnt0[7:0]));\n\n // ----------------------------------------------------------------------\n // MITCNT1 (RW)\n // [31:0] : Internal Timer Counter 0\n\n localparam MITCNT1 = 12'h7d5;\n\n assign wr_mitcnt1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT1);\n\n assign mitcnt1_inc_ok = mitctl1[MITCTL_ENABLE] &\n (~dec_pause_state | mitctl1[MITCTL_ENABLE_PAUSED]) &\n (~dec_tlu_pmu_fw_halted | mitctl1[MITCTL_ENABLE_HALTED]) &\n ~internal_dbg_halt_timers &\n (~mitctl1[3] | mit0_match_ns);\n\n // only inc MITCNT1 if not cascaded with 0, or if 0 overflows\n assign {mitcnt1_inc_cout, mitcnt1_inc[7:0]} = mitcnt1[7:0] + {7'b0, 1'b1};\n assign mitcnt1_inc[31:8] = mitcnt1[31:8] + {23'b0, mitcnt1_inc_cout};\n\n assign mitcnt1_ns[31:0] = wr_mitcnt1_r ? dec_csr_wrdata_r[31:0] : mit1_match_ns ? 'b0 : mitcnt1_inc[31:0];\n\n rvdffe #(24) mitcnt1_ffb (.*, .clk(free_l2clk), .en(wr_mitcnt1_r | (mitcnt1_inc_ok & mitcnt1_inc_cout) | mit1_match_ns), .din(mitcnt1_ns[31:8]), .dout(mitcnt1[31:8]));\n rvdffe #(8) mitcnt1_ffa (.*, .clk(free_l2clk), .en(wr_mitcnt1_r | mitcnt1_inc_ok | mit1_match_ns), .din(mitcnt1_ns[7:0]), .dout(mitcnt1[7:0]));\n\n\n // ----------------------------------------------------------------------\n // MITB0 (RW)\n // [31:0] : Internal Timer Bound 0\n\n localparam MITB0 = 12'h7d3;\n\n assign wr_mitb0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB0);\n\n rvdffe #(32) mitb0_ff (.*, .en(wr_mitb0_r), .din(~dec_csr_wrdata_r[31:0]), .dout(mitb0_b[31:0]));\n assign mitb0[31:0] = ~mitb0_b[31:0];\n\n // ----------------------------------------------------------------------\n // MITB1 (RW)\n // [31:0] : Internal Timer Bound 1\n\n localparam MITB1 = 12'h7d6;\n\n assign wr_mitb1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB1);\n\n rvdffe #(32) mitb1_ff (.*, .en(wr_mitb1_r), .din(~dec_csr_wrdata_r[31:0]), .dout(mitb1_b[31:0]));\n assign mitb1[31:0] = ~mitb1_b[31:0];\n\n // ----------------------------------------------------------------------\n // MITCTL0 (RW) Internal Timer Ctl 0\n // [31:3] : Reserved, reads 0x0\n // [2] : Enable while PAUSEd\n // [1] : Enable while HALTed\n // [0] : Enable (resets to 0x1)\n\n localparam MITCTL0 = 12'h7d4;\n\n assign wr_mitctl0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL0);\n assign mitctl0_ns[2:0] = wr_mitctl0_r ? {dec_csr_wrdata_r[2:0]} : {mitctl0[2:0]};\n\n assign mitctl0_0_b_ns = ~mitctl0_ns[0];\n rvdffs #(3) mitctl0_ff (.*, .clk(csr_wr_clk), .en(wr_mitctl0_r), .din({mitctl0_ns[2:1], mitctl0_0_b_ns}), .dout({mitctl0[2:1], mitctl0_0_b}));\n assign mitctl0[0] = ~mitctl0_0_b;\n\n // ----------------------------------------------------------------------\n // MITCTL1 (RW) Internal Timer Ctl 1\n // [31:4] : Reserved, reads 0x0\n // [3] : Cascade\n // [2] : Enable while PAUSEd\n // [1] : Enable while HALTed\n // [0] : Enable (resets to 0x1)\n\n localparam MITCTL1 = 12'h7d7;\n\n assign wr_mitctl1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL1);\n assign mitctl1_ns[3:0] = wr_mitctl1_r ? {dec_csr_wrdata_r[3:0]} : {mitctl1[3:0]};\n\n assign mitctl1_0_b_ns = ~mitctl1_ns[0];\n rvdffs #(4) mitctl1_ff (.*, .clk(csr_wr_clk), .en(wr_mitctl1_r), .din({mitctl1_ns[3:1], mitctl1_0_b_ns}), .dout({mitctl1[3:1], mitctl1_0_b}));\n assign mitctl1[0] = ~mitctl1_0_b;\n assign dec_timer_read_d = csr_mitcnt1 | csr_mitcnt0 | csr_mitb1 | csr_mitb0 | csr_mitctl0 | csr_mitctl1;\n assign dec_timer_rddata_d[31:0] = ( ({32{csr_mitcnt0}} & mitcnt0[31:0]) |\n ({32{csr_mitcnt1}} & mitcnt1[31:0]) |\n ({32{csr_mitb0}} & mitb0[31:0]) |\n ({32{csr_mitb1}} & mitb1[31:0]) |\n ({32{csr_mitctl0}} & {29'b0, mitctl0[2:0]}) |\n ({32{csr_mitctl1}} & {28'b0, mitctl1[3:0]})\n );\n\n\nendmodule // dec_timer_ctl\n" }, { "path": "design/dec/el2_dec_trigger.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n//\n// Owner:\n// Function: DEC Trigger Logic\n// Comments:\n//\n//********************************************************************************\nmodule el2_dec_trigger\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n\n input el2_trigger_pkt_t [3:0] trigger_pkt_any, // Packet from tlu. 'select':0-pc,1-Opcode 'Execute' needs to be set for dec triggers to fire. 'match'-1 do mask, 0: full match\n input logic [31:1] dec_i0_pc_d, // i0 pc\n\n output logic [3:0] dec_i0_trigger_match_d // Trigger match\n);\n\n logic [3:0][31:0] dec_i0_match_data;\n logic [3:0] dec_i0_trigger_data_match;\n\n for (genvar i=0; i<4; i++) begin : genblock\n assign dec_i0_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select & trigger_pkt_any[i].execute}} & {dec_i0_pc_d[31:1], trigger_pkt_any[i].tdata2[0]}); // select=0; do a PC match\n\n rvmaskandmatch trigger_i0_match (.mask(trigger_pkt_any[i].tdata2[31:0]), .data(dec_i0_match_data[i][31:0]), .masken(trigger_pkt_any[i].match), .match(dec_i0_trigger_data_match[i]));\n\n assign dec_i0_trigger_match_d[i] = trigger_pkt_any[i].execute & trigger_pkt_any[i].m & dec_i0_trigger_data_match[i];\n end\n\nendmodule // el2_dec_trigger\n\n" }, { "path": "design/dmi/dmi_jtag_to_core_sync.v", "content": "// SPDX-License-Identifier: Apache-2.0\r\n// Copyright 2018 Western Digital Corporation or it's affiliates.\r\n// \r\n// Licensed under the Apache License, Version 2.0 (the \"License\");\r\n// you may not use this file except in compliance with the License.\r\n// You may obtain a copy of the License at\r\n// \r\n// http://www.apache.org/licenses/LICENSE-2.0\r\n// \r\n// Unless required by applicable law or agreed to in writing, software\r\n// distributed under the License is distributed on an \"AS IS\" BASIS,\r\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n// See the License for the specific language governing permissions and\r\n// limitations under the License.\r\n//------------------------------------------------------------------------------------\r\n//\r\n// Copyright Western Digital, 2019\r\n// Owner : Alex Grobman\r\n// Description: \r\n// This module Synchronizes the signals between JTAG (TCK) and\r\n// processor (Core_clk)\r\n//\r\n//-------------------------------------------------------------------------------------\r\n\r\nmodule dmi_jtag_to_core_sync (\r\n// JTAG signals\r\ninput rd_en, // 1 bit Read Enable from JTAG\r\ninput wr_en, // 1 bit Write enable from JTAG\r\n\r\n// Processor Signals\r\ninput rst_n, // Core reset\r\ninput clk, // Core clock\r\n\r\noutput reg_en, // 1 bit Write interface bit to Processor\r\noutput reg_wr_en // 1 bit Write enable to Processor\r\n);\r\n \r\nwire c_rd_en;\r\nwire c_wr_en;\r\nreg [2:0] rden, wren;\r\n \r\n\r\n// Outputs\r\nassign reg_en = c_wr_en | c_rd_en;\r\nassign reg_wr_en = c_wr_en;\r\n\r\n\r\n// synchronizers \r\nalways @ ( posedge clk or negedge rst_n) begin\r\n if(!rst_n) begin\r\n rden <= '0;\r\n wren <= '0;\r\n end\r\n else begin\r\n rden <= {rden[1:0], rd_en};\r\n wren <= {wren[1:0], wr_en};\r\n end\r\nend\r\n\r\nassign c_rd_en = rden[1] & ~rden[2];\r\nassign c_wr_en = wren[1] & ~wren[2];\r\n \r\n\r\nendmodule\r\n" }, { "path": "design/dmi/dmi_mux.v", "content": "// DMI core aperture ranges from 0x00 to 0x4F. Addresses starting from 0x50\n// and above are considered uncore.\n\nmodule dmi_mux (\n\n // Core access enable\n input wire core_enable,\n // Uncore access enable\n input wire uncore_enable,\n\n // DMI upstream\n input wire dmi_en,\n input wire dmi_wr_en,\n input wire [ 6:0] dmi_addr,\n input wire [31:0] dmi_wdata,\n output wire [31:0] dmi_rdata,\n\n // DMI downstream for core\n output wire dmi_core_en,\n output wire dmi_core_wr_en,\n output wire [ 6:0] dmi_core_addr,\n output wire [31:0] dmi_core_wdata,\n input wire [31:0] dmi_core_rdata,\n\n // DMI downstream for uncore\n output wire dmi_uncore_en,\n output wire dmi_uncore_wr_en,\n output wire [ 6:0] dmi_uncore_addr,\n output wire [31:0] dmi_uncore_wdata,\n input wire [31:0] dmi_uncore_rdata\n);\n logic is_uncore_aperture;\n\n // Uncore address decoder\n assign is_uncore_aperture = (dmi_addr[6] & (dmi_addr[5] | dmi_addr[4]));\n\n // Core signals\n assign dmi_core_en = dmi_en & ~is_uncore_aperture & core_enable;\n assign dmi_core_wr_en = dmi_wr_en & ~is_uncore_aperture & core_enable;\n assign dmi_core_addr = dmi_addr;\n assign dmi_core_wdata = dmi_wdata;\n\n // Uncore signals\n assign dmi_uncore_en = dmi_en & is_uncore_aperture & uncore_enable;\n assign dmi_uncore_wr_en = dmi_wr_en & is_uncore_aperture & uncore_enable;\n assign dmi_uncore_addr = dmi_addr;\n assign dmi_uncore_wdata = dmi_wdata;\n\n // Read mux\n assign dmi_rdata = is_uncore_aperture ? dmi_uncore_rdata : dmi_core_rdata;\n\nendmodule\n" }, { "path": "design/dmi/dmi_wrapper.v", "content": "// SPDX-License-Identifier: Apache-2.0\r\n// Copyright 2018 Western Digital Corporation or it's affiliates.\r\n// \r\n// Licensed under the Apache License, Version 2.0 (the \"License\");\r\n// you may not use this file except in compliance with the License.\r\n// You may obtain a copy of the License at\r\n// \r\n// http://www.apache.org/licenses/LICENSE-2.0\r\n// \r\n// Unless required by applicable law or agreed to in writing, software\r\n// distributed under the License is distributed on an \"AS IS\" BASIS,\r\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n// See the License for the specific language governing permissions and\r\n// limitations under the License.\r\n//------------------------------------------------------------------------------------\r\n//\r\n// Copyright Western Digital, 2018\r\n// Owner : Anusha Narayanamoorthy\r\n// Description: \r\n// Wrapper module for JTAG_TAP and DMI synchronizer\r\n//\r\n//-------------------------------------------------------------------------------------\r\n\r\nmodule dmi_wrapper(\r\n\r\n // JTAG signals\r\n input trst_n, // JTAG reset\r\n input tck, // JTAG clock\r\n input tms, // Test mode select \r\n input tdi, // Test Data Input\r\n output tdo, // Test Data Output \r\n output tdoEnable, // Test Data Output enable \r\n\r\n // Processor Signals\r\n input core_rst_n, // Core reset \r\n input core_clk, // Core clock \r\n //jtag_id is supposed to be connected to a constant in the top level\r\n /* pragma coverage off*/\r\n input [31:1] jtag_id, // JTAG ID\r\n /* pragma coverage on*/\r\n input [31:0] rd_data, // 32 bit Read data from Processor \r\n output [31:0] reg_wr_data, // 32 bit Write data to Processor \r\n output [6:0] reg_wr_addr, // 7 bit reg address to Processor \r\n output reg_en, // 1 bit Read enable to Processor \r\n output reg_wr_en, // 1 bit Write enable to Processor \r\n output dmi_hard_reset \r\n);\r\n\r\n\r\n \r\n\r\n\r\n //Wire Declaration\r\n wire rd_en;\r\n wire wr_en;\r\n wire dmireset;\r\n\r\n \r\n //jtag_tap instantiation\r\n rvjtag_tap i_jtag_tap(\r\n .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset\r\n .tck(tck), // dedicated JTAG TCK pad signal\r\n .tms(tms), // dedicated JTAG TMS pad signal\r\n .tdi(tdi), // dedicated JTAG TDI pad signal\r\n .tdo(tdo), // dedicated JTAG TDO pad signal\r\n .tdoEnable(tdoEnable), // enable for TDO pad\r\n .wr_data(reg_wr_data), // 32 bit Write data\r\n .wr_addr(reg_wr_addr), // 7 bit Write address\r\n .rd_en(rd_en), // 1 bit read enable\r\n .wr_en(wr_en), // 1 bit Write enable\r\n .rd_data(rd_data), // 32 bit Read data\r\n .rd_status(2'b0),\r\n .idle(3'h0), // no need to wait to sample data\r\n .dmi_stat(2'b0), // no need to wait or error possible\r\n .version(4'h1), // debug spec 0.13 compliant\r\n .jtag_id(jtag_id),\r\n .dmi_hard_reset(dmi_hard_reset),\r\n .dmi_reset(dmireset)\r\n);\r\n\r\n\r\n // dmi_jtag_to_core_sync instantiation\r\n dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(\r\n .wr_en(wr_en), // 1 bit Write enable\r\n .rd_en(rd_en), // 1 bit Read enable\r\n\r\n .rst_n(core_rst_n),\r\n .clk(core_clk),\r\n .reg_en(reg_en), // 1 bit Write interface bit\r\n .reg_wr_en(reg_wr_en) // 1 bit Write enable\r\n );\r\n\r\nendmodule\r\n" }, { "path": "design/dmi/rvjtag_tap.v", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or it's affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License\n\nmodule rvjtag_tap #(\nparameter AWIDTH = 7\n)\n(\ninput trst,\ninput tck,\ninput tms,\ninput tdi,\noutput reg tdo,\noutput tdoEnable,\n\noutput [31:0] wr_data,\noutput [AWIDTH-1:0] wr_addr,\noutput wr_en,\noutput rd_en,\n\ninput [31:0] rd_data,\n/*pragma coverage off*/\ninput [1:0] rd_status,\n/*pragma coverage on*/\n\noutput reg dmi_reset,\noutput reg dmi_hard_reset,\n\n/*pragma coverage off*/\ninput [2:0] idle,\ninput [1:0] dmi_stat,\n/*pragma coverage on*/\n/*\n-- revisionCode : 4'h0;\n-- manufacturersIdCode : 11'h45;\n-- deviceIdCode : 16'h0001;\n-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB]\n*/\n/*pragma coverage off*/\ninput [31:1] jtag_id,\ninput [3:0] version\n/*pragma coverage on*/\n);\n\nlocalparam USER_DR_LENGTH = AWIDTH + 34;\n\n\nreg [USER_DR_LENGTH-1:0] sr, nsr, dr;\n\n///////////////////////////////////////////////////////\n// Tap controller\n///////////////////////////////////////////////////////\nlogic[3:0] state, nstate;\nlogic [4:0] ir;\nwire jtag_reset;\nwire shift_dr;\nwire pause_dr;\nwire update_dr;\nwire capture_dr;\nwire shift_ir;\nwire pause_ir ;\nwire update_ir ;\nwire capture_ir;\nwire[1:0] dr_en;\nwire devid_sel;\nwire [5:0] abits;\n\nassign abits = AWIDTH[5:0];\n\n\nlocalparam TEST_LOGIC_RESET_STATE = 0;\nlocalparam RUN_TEST_IDLE_STATE = 1;\nlocalparam SELECT_DR_SCAN_STATE = 2;\nlocalparam CAPTURE_DR_STATE = 3;\nlocalparam SHIFT_DR_STATE = 4;\nlocalparam EXIT1_DR_STATE = 5;\nlocalparam PAUSE_DR_STATE = 6;\nlocalparam EXIT2_DR_STATE = 7;\nlocalparam UPDATE_DR_STATE = 8;\nlocalparam SELECT_IR_SCAN_STATE = 9;\nlocalparam CAPTURE_IR_STATE = 10;\nlocalparam SHIFT_IR_STATE = 11;\nlocalparam EXIT1_IR_STATE = 12;\nlocalparam PAUSE_IR_STATE = 13;\nlocalparam EXIT2_IR_STATE = 14;\nlocalparam UPDATE_IR_STATE = 15;\n\nalways_comb begin\n nstate = state;\n case(state)\n TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE;\n RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;\n SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE;\n CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;\n SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;\n EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE;\n PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE;\n EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE;\n UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;\n SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE;\n CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;\n SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;\n EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE;\n PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE;\n EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE;\n UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;\n default: nstate = TEST_LOGIC_RESET_STATE;\n endcase\nend\n\nalways @ (posedge tck or negedge trst) begin\n if(!trst) state <= TEST_LOGIC_RESET_STATE;\n else state <= nstate;\nend\n\nassign jtag_reset = state == TEST_LOGIC_RESET_STATE;\nassign shift_dr = state == SHIFT_DR_STATE;\nassign pause_dr = state == PAUSE_DR_STATE;\nassign update_dr = state == UPDATE_DR_STATE;\nassign capture_dr = state == CAPTURE_DR_STATE;\nassign shift_ir = state == SHIFT_IR_STATE;\nassign pause_ir = state == PAUSE_IR_STATE;\nassign update_ir = state == UPDATE_IR_STATE;\nassign capture_ir = state == CAPTURE_IR_STATE;\n\nassign tdoEnable = shift_dr | shift_ir;\n\n///////////////////////////////////////////////////////\n// IR register\n///////////////////////////////////////////////////////\n\nalways @ (negedge tck or negedge trst) begin\n if (!trst) ir <= 5'b1;\n else begin\n if (jtag_reset) ir <= 5'b1;\n else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];\n end\nend\n\n\nassign devid_sel = ir == 5'b00001;\nassign dr_en[0] = ir == 5'b10000;\nassign dr_en[1] = ir == 5'b10001;\n\n///////////////////////////////////////////////////////\n// Shift register\n///////////////////////////////////////////////////////\nalways @ (posedge tck or negedge trst) begin\n if(!trst)begin\n sr <= '0;\n end\n else begin\n sr <= nsr;\n end\nend\n\n// SR next value\nalways_comb begin\n nsr = sr;\n case(1)\n shift_dr: begin\n case(1)\n dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]};\n\n dr_en[0],\n devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};\n default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass\n endcase\n end\n capture_dr: begin\n nsr[0] = 1'b0;\n case(1)\n dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};\n dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};\n devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};\n endcase\n end\n shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};\n capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};\n endcase\nend\n\n// TDO retiming\nalways @ (negedge tck ) tdo <= sr[0];\n\n// DMI CS register\nalways @ (posedge tck or negedge trst) begin\n if(!trst) begin\n dmi_hard_reset <= 1'b0;\n dmi_reset <= 1'b0;\n end\n else if (update_dr & dr_en[0]) begin\n dmi_hard_reset <= sr[17];\n dmi_reset <= sr[16];\n end\n else begin\n dmi_hard_reset <= 1'b0;\n dmi_reset <= 1'b0;\n end\nend\n\n// DR register\nalways @ (posedge tck or negedge trst) begin\n if(!trst)\n dr <= '0;\n else begin\n if (update_dr & dr_en[1])\n dr <= sr;\n else\n dr <= {dr[USER_DR_LENGTH-1:2],2'b0};\n end\nend\n\nassign {wr_addr, wr_data, wr_en, rd_en} = dr;\n\n\n\n\nendmodule\n" }, { "path": "design/el2_dma_ctrl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n// Function: Top level VeeR core file\n// Comments:\n//\n//********************************************************************************\n\nmodule el2_dma_ctrl \nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input logic clk,\n input logic free_clk,\n input logic rst_l,\n input logic dma_bus_clk_en, // slave bus clock enable\n input logic clk_override,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n\n // Debug signals\n input logic [31:0] dbg_cmd_addr,\n input logic [31:0] dbg_cmd_wrdata,\n input logic dbg_cmd_valid,\n input logic dbg_cmd_write, // 1: write command, 0: read_command\n input logic [1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory\n input logic [1:0] dbg_cmd_size, // size of the abstract mem access debug command\n\n input logic dbg_dma_bubble, // Debug needs a bubble to send a valid\n output logic dma_dbg_ready, // DMA is ready to accept debug request\n\n output logic dma_dbg_cmd_done,\n output logic dma_dbg_cmd_fail,\n output logic [31:0] dma_dbg_rddata,\n\n // Core side signals\n output logic dma_dccm_req, // DMA dccm request (only one of dccm/iccm will be set)\n output logic dma_iccm_req, // DMA iccm request\n output logic [2:0] dma_mem_tag, // DMA Buffer entry number\n output logic [31:0] dma_mem_addr, // DMA request address\n output logic [2:0] dma_mem_sz, // DMA request size\n output logic dma_mem_write, // DMA write to dccm/iccm\n output logic [63:0] dma_mem_wdata, // DMA write data\n\n input logic dccm_dma_rvalid, // dccm data valid for DMA read\n input logic dccm_dma_ecc_error, // ECC error on DMA read\n input logic [2:0] dccm_dma_rtag, // Tag of the DMA req\n input logic [63:0] dccm_dma_rdata, // dccm data for DMA read\n input logic iccm_dma_rvalid, // iccm data valid for DMA read\n input logic iccm_dma_ecc_error, // ECC error on DMA read\n input logic [2:0] iccm_dma_rtag, // Tag of the DMA req\n input logic [63:0] iccm_dma_rdata, // iccm data for DMA read\n\n output logic dma_active, // DMA is busy\n output logic dma_dccm_stall_any, // stall dccm pipe (bubble) so that DMA can proceed\n output logic dma_iccm_stall_any, // stall iccm pipe (bubble) so that DMA can proceed\n input logic dccm_ready, // dccm ready to accept DMA request\n input logic iccm_ready, // iccm ready to accept DMA request\n input logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:15]\n\n // PMU signals\n output logic dma_pmu_dccm_read,\n output logic dma_pmu_dccm_write,\n output logic dma_pmu_any_read,\n output logic dma_pmu_any_write,\n\n // AXI Write Channels\n input logic dma_axi_awvalid,\n output logic dma_axi_awready,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,\n input logic [31:0] dma_axi_awaddr,\n input logic [2:0] dma_axi_awsize,\n\n\n input logic dma_axi_wvalid,\n output logic dma_axi_wready,\n input logic [63:0] dma_axi_wdata,\n input logic [7:0] dma_axi_wstrb,\n\n output logic dma_axi_bvalid,\n input logic dma_axi_bready,\n output logic [1:0] dma_axi_bresp,\n output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,\n\n // AXI Read Channels\n input logic dma_axi_arvalid,\n output logic dma_axi_arready,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,\n input logic [31:0] dma_axi_araddr,\n input logic [2:0] dma_axi_arsize,\n\n output logic dma_axi_rvalid,\n input logic dma_axi_rready,\n output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,\n output logic [63:0] dma_axi_rdata,\n output logic [1:0] dma_axi_rresp,\n output logic dma_axi_rlast\n);\n\n\n localparam DEPTH = pt.DMA_BUF_DEPTH;\n localparam DEPTH_PTR = $clog2(DEPTH);\n localparam NACK_COUNT = 7;\n\n logic [DEPTH-1:0] fifo_valid;\n logic [DEPTH-1:0][1:0] fifo_error;\n logic [DEPTH-1:0] fifo_error_bus;\n logic [DEPTH-1:0] fifo_rpend;\n logic [DEPTH-1:0] fifo_done; // DMA trxn is done in core\n logic [DEPTH-1:0] fifo_done_bus; // DMA trxn is done in core but synced to bus clock\n logic [DEPTH-1:0][31:0] fifo_addr;\n logic [DEPTH-1:0][2:0] fifo_sz;\n logic [DEPTH-1:0][7:0] fifo_byteen;\n logic [DEPTH-1:0] fifo_write;\n logic [DEPTH-1:0] fifo_posted_write;\n logic [DEPTH-1:0] fifo_dbg;\n logic [DEPTH-1:0][63:0] fifo_data;\n logic [DEPTH-1:0][pt.DMA_BUS_TAG-1:0] fifo_tag;\n logic [DEPTH-1:0][pt.DMA_BUS_ID-1:0] fifo_mid;\n logic [DEPTH-1:0][pt.DMA_BUS_PRTY-1:0] fifo_prty;\n\n logic [DEPTH-1:0] fifo_cmd_en;\n logic [DEPTH-1:0] fifo_data_en;\n logic [DEPTH-1:0] fifo_pend_en;\n logic [DEPTH-1:0] fifo_done_en;\n logic [DEPTH-1:0] fifo_done_bus_en;\n logic [DEPTH-1:0] fifo_error_en;\n logic [DEPTH-1:0] fifo_error_bus_en;\n logic [DEPTH-1:0] fifo_reset;\n logic [DEPTH-1:0][1:0] fifo_error_in;\n logic [DEPTH-1:0][63:0] fifo_data_in;\n\n logic fifo_write_in;\n logic fifo_posted_write_in;\n logic fifo_dbg_in;\n logic [31:0] fifo_addr_in;\n logic [2:0] fifo_sz_in;\n logic [7:0] fifo_byteen_in;\n\n logic [DEPTH_PTR-1:0] RspPtr, NxtRspPtr;\n logic [DEPTH_PTR-1:0] WrPtr, NxtWrPtr;\n logic [DEPTH_PTR-1:0] RdPtr, NxtRdPtr;\n logic WrPtrEn, RdPtrEn, RspPtrEn;\n\n logic [1:0] dma_dbg_sz;\n logic [1:0] dma_dbg_addr;\n logic [31:0] dma_dbg_mem_rddata;\n logic [31:0] dma_dbg_mem_wrdata;\n logic dma_dbg_cmd_error;\n logic dma_dbg_cmd_done_q;\n\n logic fifo_full, fifo_full_spec, fifo_empty;\n logic dma_address_error, dma_alignment_error;\n logic [3:0] num_fifo_vld;\n logic dma_mem_req;\n logic [31:0] dma_mem_addr_int;\n logic [2:0] dma_mem_sz_int;\n logic [7:0] dma_mem_byteen;\n logic dma_mem_addr_in_dccm;\n logic dma_mem_addr_in_iccm;\n logic dma_mem_addr_in_pic;\n logic dma_mem_addr_in_pic_region_nc;\n logic dma_mem_addr_in_dccm_region_nc;\n logic dma_mem_addr_in_iccm_region_nc;\n\n logic [2:0] dma_nack_count, dma_nack_count_d, dma_nack_count_csr;\n\n logic dma_buffer_c1_clken;\n logic dma_free_clken;\n logic dma_buffer_c1_clk;\n logic dma_free_clk;\n logic dma_bus_clk;\n\n logic bus_rsp_valid, bus_rsp_sent;\n logic bus_cmd_valid, bus_cmd_sent;\n logic bus_cmd_write, bus_cmd_posted_write;\n logic [7:0] bus_cmd_byteen;\n logic [2:0] bus_cmd_sz;\n logic [31:0] bus_cmd_addr;\n logic [63:0] bus_cmd_wdata;\n logic [pt.DMA_BUS_TAG-1:0] bus_cmd_tag;\n logic [pt.DMA_BUS_ID-1:0] bus_cmd_mid;\n logic [pt.DMA_BUS_PRTY-1:0] bus_cmd_prty;\n logic bus_posted_write_done;\n\n logic fifo_full_spec_bus;\n logic dbg_dma_bubble_bus;\n logic stall_dma_in;\n logic dma_fifo_ready;\n\n logic wrbuf_en, wrbuf_data_en;\n logic wrbuf_cmd_sent, wrbuf_rst, wrbuf_data_rst;\n logic wrbuf_vld, wrbuf_data_vld;\n logic [pt.DMA_BUS_TAG-1:0] wrbuf_tag;\n logic [2:0] wrbuf_sz;\n logic [31:0] wrbuf_addr;\n logic [63:0] wrbuf_data;\n logic [7:0] wrbuf_byteen;\n\n logic rdbuf_en;\n logic rdbuf_cmd_sent, rdbuf_rst;\n logic rdbuf_vld;\n logic [pt.DMA_BUS_TAG-1:0] rdbuf_tag;\n logic [2:0] rdbuf_sz;\n logic [31:0] rdbuf_addr;\n\n logic axi_mstr_prty_in, axi_mstr_prty_en;\n logic axi_mstr_priority;\n logic axi_mstr_sel;\n\n logic axi_rsp_valid;\n logic axi_rsp_write;\n logic [pt.DMA_BUS_TAG-1:0] axi_rsp_tag;\n logic [1:0] axi_rsp_error;\n logic [63:0] axi_rsp_rdata;\n\n //------------------------LOGIC STARTS HERE---------------------------------\n\n // FIFO inputs\n assign fifo_addr_in[31:0] = dbg_cmd_valid ? dbg_cmd_addr[31:0] : bus_cmd_addr[31:0];\n assign fifo_byteen_in[7:0] = {8{~dbg_cmd_valid}} & bus_cmd_byteen[7:0]; // Byte enable is used only for bus requests\n assign fifo_sz_in[2:0] = dbg_cmd_valid ? {1'b0,dbg_cmd_size[1:0]} : bus_cmd_sz[2:0];\n assign fifo_write_in = dbg_cmd_valid ? dbg_cmd_write : bus_cmd_write;\n assign fifo_posted_write_in = ~dbg_cmd_valid & bus_cmd_posted_write;\n assign fifo_dbg_in = dbg_cmd_valid;\n\n for (genvar i=0 ;i= DEPTH);\n\n assign dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus);\n\n // Error logic\n assign dma_address_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & ~fifo_dbg[RdPtr] & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)); // request not for ICCM or DCCM\n assign dma_alignment_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & ~fifo_dbg[RdPtr] & ~dma_address_error &\n (((dma_mem_sz_int[2:0] == 3'h1) & dma_mem_addr_int[0]) | // HW size but unaligned\n ((dma_mem_sz_int[2:0] == 3'h2) & (|dma_mem_addr_int[1:0])) | // W size but unaligned\n ((dma_mem_sz_int[2:0] == 3'h3) & (|dma_mem_addr_int[2:0])) | // DW size but unaligned\n (dma_mem_addr_in_iccm & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // ICCM access not word size\n (dma_mem_addr_in_dccm & dma_mem_write & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // DCCM write not word size\n (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_addr_int[2:0] == 3'h0) & (dma_mem_byteen[3:0] != 4'hf)) | // Write byte enables not aligned for word store\n (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_addr_int[2:0] == 3'h4) & (dma_mem_byteen[7:4] != 4'hf)) | // Write byte enables not aligned for word store\n (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h3) & ~((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0) | (dma_mem_byteen[7:0] == 8'hff)))); // Write byte enables not aligned for dword store\n\n\n //Dbg outputs\n assign dma_dbg_ready = fifo_empty & dbg_dma_bubble;\n assign dma_dbg_cmd_done = (fifo_valid[RspPtr] & fifo_dbg[RspPtr] & fifo_done[RspPtr]);\n assign dma_dbg_cmd_fail = (|fifo_error[RspPtr] & dma_dbg_cmd_done) ;\n\n assign dma_dbg_sz[1:0] = fifo_sz[RspPtr][1:0];\n assign dma_dbg_addr[1:0] = fifo_addr[RspPtr][1:0];\n assign dma_dbg_mem_rddata[31:0] = fifo_addr[RspPtr][2] ? fifo_data[RspPtr][63:32] : fifo_data[RspPtr][31:0];\n assign dma_dbg_rddata[31:0] = ({32{(dma_dbg_sz[1:0] == 2'h0)}} & ((dma_dbg_mem_rddata[31:0] >> 8*dma_dbg_addr[1:0]) & 32'hff)) |\n ({32{(dma_dbg_sz[1:0] == 2'h1)}} & ((dma_dbg_mem_rddata[31:0] >> 16*dma_dbg_addr[1]) & 32'hffff)) |\n ({32{(dma_dbg_sz[1:0] == 2'h2)}} & dma_dbg_mem_rddata[31:0]);\n\n assign dma_dbg_cmd_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & fifo_dbg[RdPtr] &\n ((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)) | // Address outside of ICCM/DCCM/PIC\n ((dma_mem_addr_in_iccm | dma_mem_addr_in_pic) & (dma_mem_sz_int[1:0] != 2'b10))); // Only word accesses allowed for ICCM/PIC\n\n assign dma_dbg_mem_wrdata[31:0] = ({32{dbg_cmd_size[1:0] == 2'h0}} & {4{dbg_cmd_wrdata[7:0]}}) |\n ({32{dbg_cmd_size[1:0] == 2'h1}} & {2{dbg_cmd_wrdata[15:0]}}) |\n ({32{dbg_cmd_size[1:0] == 2'h2}} & dbg_cmd_wrdata[31:0]);\n\n // Block the decode if fifo full\n assign dma_dccm_stall_any = dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr);\n assign dma_iccm_stall_any = dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);\n\n // Used to indicate ready to debug\n assign fifo_empty = ~((|(fifo_valid[DEPTH-1:0])) | bus_cmd_sent);\n\n // Nack counter, stall the lsu pipe if 7 nacks\n assign dma_nack_count_csr[2:0] = dec_tlu_dma_qos_prty[2:0];\n assign dma_nack_count_d[2:0] = (dma_nack_count[2:0] >= dma_nack_count_csr[2:0]) ? ({3{~(dma_dccm_req | dma_iccm_req)}} & dma_nack_count[2:0]) :\n (dma_mem_req & ~(dma_dccm_req | dma_iccm_req)) ? (dma_nack_count[2:0] + 1'b1) : 3'b0;\n\n rvdffs #(3) nack_count_dff(.din(dma_nack_count_d[2:0]), .dout(dma_nack_count[2:0]), .en(dma_mem_req), .clk(dma_free_clk), .*);\n\n // Core outputs\n assign dma_mem_req = fifo_valid[RdPtr] & ~fifo_rpend[RdPtr] & ~fifo_done[RdPtr] & ~(dma_address_error | dma_alignment_error | dma_dbg_cmd_error);\n assign dma_dccm_req = dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & dccm_ready;\n assign dma_iccm_req = dma_mem_req & dma_mem_addr_in_iccm & iccm_ready;\n assign dma_mem_tag[2:0] = 3'(RdPtr);\n assign dma_mem_addr_int[31:0] = fifo_addr[RdPtr];\n assign dma_mem_sz_int[2:0] = fifo_sz[RdPtr];\n assign dma_mem_addr[31:0] = (dma_mem_write & ~fifo_dbg[RdPtr] & (dma_mem_byteen[7:0] == 8'hf0)) ? {dma_mem_addr_int[31:3],1'b1,dma_mem_addr_int[1:0]} : dma_mem_addr_int[31:0];\n assign dma_mem_sz[2:0] = (dma_mem_write & ~fifo_dbg[RdPtr] & ((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0))) ? 3'h2 : dma_mem_sz_int[2:0];\n assign dma_mem_byteen[7:0] = fifo_byteen[RdPtr];\n assign dma_mem_write = fifo_write[RdPtr];\n assign dma_mem_wdata[63:0] = fifo_data[RdPtr];\n\n // PMU outputs\n assign dma_pmu_dccm_read = dma_dccm_req & ~dma_mem_write;\n assign dma_pmu_dccm_write = dma_dccm_req & dma_mem_write;\n assign dma_pmu_any_read = (dma_dccm_req | dma_iccm_req) & ~dma_mem_write;\n assign dma_pmu_any_write = (dma_dccm_req | dma_iccm_req) & dma_mem_write;\n\n // Address check dccm\n if (pt.DCCM_ENABLE) begin: Gen_dccm_enable\n rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),\n .CCM_SIZE(pt.DCCM_SIZE)) addr_dccm_rangecheck (\n .addr(dma_mem_addr_int[31:0]),\n .in_range(dma_mem_addr_in_dccm),\n .in_region(dma_mem_addr_in_dccm_region_nc)\n );\n end else begin: Gen_dccm_disable\n assign dma_mem_addr_in_dccm = '0;\n assign dma_mem_addr_in_dccm_region_nc = '0;\n end // else: !if(pt.ICCM_ENABLE)\n\n // Address check iccm\n if (pt.ICCM_ENABLE) begin: Gen_iccm_enable\n rvrangecheck #(.CCM_SADR(pt.ICCM_SADR),\n .CCM_SIZE(pt.ICCM_SIZE)) addr_iccm_rangecheck (\n .addr(dma_mem_addr_int[31:0]),\n .in_range(dma_mem_addr_in_iccm),\n .in_region(dma_mem_addr_in_iccm_region_nc)\n );\n end else begin: Gen_iccm_disable\n assign dma_mem_addr_in_iccm = '0;\n assign dma_mem_addr_in_iccm_region_nc = '0;\n end // else: !if(pt.ICCM_ENABLE)\n\n\n // PIC memory address check\n rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),\n .CCM_SIZE(pt.PIC_SIZE)) addr_pic_rangecheck (\n .addr(dma_mem_addr_int[31:0]),\n .in_range(dma_mem_addr_in_pic),\n .in_region(dma_mem_addr_in_pic_region_nc)\n );\n\n // Inputs\n rvdff_fpga #(1) fifo_full_bus_ff (.din(fifo_full_spec), .dout(fifo_full_spec_bus), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(1) dbg_dma_bubble_ff (.din(dbg_dma_bubble), .dout(dbg_dma_bubble_bus), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n rvdff #(1) dma_dbg_cmd_doneff (.din(dma_dbg_cmd_done), .dout(dma_dbg_cmd_done_q), .clk(free_clk), .*);\n\n // Clock Gating logic\n assign dma_buffer_c1_clken = (bus_cmd_valid & dma_bus_clk_en) | dbg_cmd_valid | clk_override;\n assign dma_free_clken = (bus_cmd_valid | bus_rsp_valid | dbg_cmd_valid | dma_dbg_cmd_done | dma_dbg_cmd_done_q | (|fifo_valid[DEPTH-1:0]) | clk_override);\n\n rvoclkhdr dma_buffer_c1cgc ( .en(dma_buffer_c1_clken), .l1clk(dma_buffer_c1_clk), .* );\n rvoclkhdr dma_free_cgc (.en(dma_free_clken), .l1clk(dma_free_clk), .*);\n\n`ifdef RV_FPGA_OPTIMIZE\n assign dma_bus_clk = 1'b0;\n`else\n rvclkhdr dma_bus_cgc (.en(dma_bus_clk_en), .l1clk(dma_bus_clk), .*);\n`endif\n\n // Write channel buffer\n assign wrbuf_en = dma_axi_awvalid & dma_axi_awready;\n assign wrbuf_data_en = dma_axi_wvalid & dma_axi_wready;\n assign wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write;\n assign wrbuf_rst = wrbuf_cmd_sent & ~wrbuf_en;\n assign wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en;\n\n rvdffsc_fpga #(.WIDTH(1)) wrbuf_vldff (.din(1'b1), .dout(wrbuf_vld), .en(wrbuf_en), .clear(wrbuf_rst), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n rvdffsc_fpga #(.WIDTH(1)) wrbuf_data_vldff (.din(1'b1), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clear(wrbuf_data_rst), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(pt.DMA_BUS_TAG)) wrbuf_tagff (.din(dma_axi_awid[pt.DMA_BUS_TAG-1:0]), .dout(wrbuf_tag[pt.DMA_BUS_TAG-1:0]), .en(wrbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(3)) wrbuf_szff (.din(dma_axi_awsize[2:0]), .dout(wrbuf_sz[2:0]), .en(wrbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n rvdffe #(.WIDTH(32)) wrbuf_addrff (.din(dma_axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]), .en(wrbuf_en & dma_bus_clk_en), .*);\n rvdffe #(.WIDTH(64)) wrbuf_dataff (.din(dma_axi_wdata[63:0]), .dout(wrbuf_data[63:0]), .en(wrbuf_data_en & dma_bus_clk_en), .*);\n rvdffs_fpga #(.WIDTH(8)) wrbuf_byteenff (.din(dma_axi_wstrb[7:0]), .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n\n // Read channel buffer\n assign rdbuf_en = dma_axi_arvalid & dma_axi_arready;\n assign rdbuf_cmd_sent = bus_cmd_sent & ~bus_cmd_write;\n assign rdbuf_rst = rdbuf_cmd_sent & ~rdbuf_en;\n\n rvdffsc_fpga #(.WIDTH(1)) rdbuf_vldff (.din(1'b1), .dout(rdbuf_vld), .en(rdbuf_en), .clear(rdbuf_rst), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(pt.DMA_BUS_TAG)) rdbuf_tagff (.din(dma_axi_arid[pt.DMA_BUS_TAG-1:0]), .dout(rdbuf_tag[pt.DMA_BUS_TAG-1:0]), .en(rdbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(3)) rdbuf_szff (.din(dma_axi_arsize[2:0]), .dout(rdbuf_sz[2:0]), .en(rdbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n rvdffe #(.WIDTH(32)) rdbuf_addrff (.din(dma_axi_araddr[31:0]), .dout(rdbuf_addr[31:0]), .en(rdbuf_en & dma_bus_clk_en), .*);\n\n assign dma_axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent);\n assign dma_axi_wready = ~(wrbuf_data_vld & ~wrbuf_cmd_sent);\n assign dma_axi_arready = ~(rdbuf_vld & ~rdbuf_cmd_sent);\n\n //Generate a single request from read/write channel\n assign bus_cmd_valid = (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld;\n assign bus_cmd_sent = bus_cmd_valid & dma_fifo_ready;\n assign bus_cmd_write = axi_mstr_sel;\n assign bus_cmd_posted_write = '0;\n assign bus_cmd_addr[31:0] = axi_mstr_sel ? wrbuf_addr[31:0] : rdbuf_addr[31:0];\n assign bus_cmd_sz[2:0] = axi_mstr_sel ? wrbuf_sz[2:0] : rdbuf_sz[2:0];\n assign bus_cmd_wdata[63:0] = wrbuf_data[63:0];\n assign bus_cmd_byteen[7:0] = wrbuf_byteen[7:0];\n assign bus_cmd_tag[pt.DMA_BUS_TAG-1:0] = axi_mstr_sel ? wrbuf_tag[pt.DMA_BUS_TAG-1:0] : rdbuf_tag[pt.DMA_BUS_TAG-1:0];\n assign bus_cmd_mid[pt.DMA_BUS_ID-1:0] = '0;\n assign bus_cmd_prty[pt.DMA_BUS_PRTY-1:0] = '0;\n\n // Sel=1 -> write has higher priority\n assign axi_mstr_sel = (wrbuf_vld & wrbuf_data_vld & rdbuf_vld) ? axi_mstr_priority : (wrbuf_vld & wrbuf_data_vld);\n assign axi_mstr_prty_in = ~axi_mstr_priority;\n assign axi_mstr_prty_en = bus_cmd_sent;\n rvdffs_fpga #(.WIDTH(1)) mstr_prtyff(.din(axi_mstr_prty_in), .dout(axi_mstr_priority), .en(axi_mstr_prty_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);\n\n assign axi_rsp_valid = fifo_valid[RspPtr] & ~fifo_dbg[RspPtr] & fifo_done_bus[RspPtr];\n assign axi_rsp_rdata[63:0] = fifo_data[RspPtr];\n assign axi_rsp_write = fifo_write[RspPtr];\n assign axi_rsp_error[1:0] = fifo_error[RspPtr][0] ? 2'b10 : (fifo_error[RspPtr][1] ? 2'b11 : 2'b0);\n assign axi_rsp_tag[pt.DMA_BUS_TAG-1:0] = fifo_tag[RspPtr];\n\n // AXI response channel signals\n assign dma_axi_bvalid = axi_rsp_valid & axi_rsp_write;\n assign dma_axi_bresp[1:0] = axi_rsp_error[1:0];\n assign dma_axi_bid[pt.DMA_BUS_TAG-1:0] = axi_rsp_tag[pt.DMA_BUS_TAG-1:0];\n\n assign dma_axi_rvalid = axi_rsp_valid & ~axi_rsp_write;\n assign dma_axi_rresp[1:0] = axi_rsp_error;\n assign dma_axi_rdata[63:0] = axi_rsp_rdata[63:0];\n assign dma_axi_rlast = 1'b1;\n assign dma_axi_rid[pt.DMA_BUS_TAG-1:0] = axi_rsp_tag[pt.DMA_BUS_TAG-1:0];\n\n assign bus_posted_write_done = 1'b0;\n assign bus_rsp_valid = (dma_axi_bvalid | dma_axi_rvalid);\n assign bus_rsp_sent = (dma_axi_bvalid & dma_axi_bready) | (dma_axi_rvalid & dma_axi_rready);\n\n assign dma_active = wrbuf_vld | rdbuf_vld | (|fifo_valid[DEPTH-1:0]);\n\n\n`ifdef RV_ASSERT_ON\n\n for (genvar i=0; i $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_awvalid_stable: assert property (dma_axi_awvalid_stable) else\n $display(\"DMA AXI awvalid changed in middle of bus clock\");\n\n // Assertion to check awid stays stable during entire bus clock\n property dma_axi_awid_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_awvalid & (dma_axi_awid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_awid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_awid_stable: assert property (dma_axi_awid_stable) else\n $display(\"DMA AXI awid changed in middle of bus clock\");\n\n // Assertion to check awaddr stays stable during entire bus clock\n property dma_axi_awaddr_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_awvalid & (dma_axi_awaddr[31:0] != $past(dma_axi_awaddr[31:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_awaddr_stable: assert property (dma_axi_awaddr_stable) else\n $display(\"DMA AXI awaddr changed in middle of bus clock\");\n\n // Assertion to check awsize stays stable during entire bus clock\n property dma_axi_awsize_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_awvalid & (dma_axi_awsize[2:0] != $past(dma_axi_awsize[2:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_awsize_stable: assert property (dma_axi_awsize_stable) else\n $display(\"DMA AXI awsize changed in middle of bus clock\");\n\n // Assertion to check wstrb stays stable during entire bus clock\n property dma_axi_wstrb_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_wvalid & (dma_axi_wstrb[7:0] != $past(dma_axi_wstrb[7:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_wstrb_stable: assert property (dma_axi_wstrb_stable) else\n $display(\"DMA AXI wstrb changed in middle of bus clock\");\n\n // Assertion to check wdata stays stable during entire bus clock\n property dma_axi_wdata_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_wvalid & (dma_axi_wdata[63:0] != $past(dma_axi_wdata[63:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_wdata_stable: assert property (dma_axi_wdata_stable) else\n $display(\"DMA AXI wdata changed in middle of bus clock\");\n\n // Assertion to check awvalid stays stable during entire bus clock\n property dma_axi_arvalid_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_arvalid != $past(dma_axi_arvalid)) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_arvalid_stable: assert property (dma_axi_arvalid_stable) else\n $display(\"DMA AXI awvalid changed in middle of bus clock\");\n\n // Assertion to check awid stays stable during entire bus clock\n property dma_axi_arid_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_arvalid & (dma_axi_arid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_arid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_arid_stable: assert property (dma_axi_arid_stable) else\n $display(\"DMA AXI awid changed in middle of bus clock\");\n\n // Assertion to check awaddr stays stable during entire bus clock\n property dma_axi_araddr_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_arvalid & (dma_axi_araddr[31:0] != $past(dma_axi_araddr[31:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_araddr_stable: assert property (dma_axi_araddr_stable) else\n $display(\"DMA AXI awaddr changed in middle of bus clock\");\n\n // Assertion to check awsize stays stable during entire bus clock\n property dma_axi_arsize_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_awvalid & (dma_axi_arsize[2:0] != $past(dma_axi_arsize[2:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_arsize_stable: assert property (dma_axi_arsize_stable) else\n $display(\"DMA AXI awsize changed in middle of bus clock\");\n\n // Assertion to check bvalid stays stable during entire bus clock\n property dma_axi_bvalid_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_bvalid != $past(dma_axi_bvalid)) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_bvalid_stable: assert property (dma_axi_bvalid_stable) else\n $display(\"DMA AXI bvalid changed in middle of bus clock\");\n\n // Assertion to check bvalid stays stable if bready is low\n property dma_axi_bvalid_stable_till_bready;\n @(posedge clk) disable iff(~rst_l) (~dma_axi_bvalid && $past(dma_axi_bvalid)) |-> $past(dma_axi_bready);\n endproperty\n assert_dma_axi_bvalid_stable_till_bready: assert property (dma_axi_bvalid_stable_till_bready) else\n $display(\"DMA AXI bvalid deasserted without bready\");\n\n // Assertion to check bresp stays stable during entire bus clock\n property dma_axi_bresp_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_bvalid & (dma_axi_bresp[1:0] != $past(dma_axi_bresp[1:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_bresp_stable: assert property (dma_axi_bresp_stable) else\n $display(\"DMA AXI bresp changed in middle of bus clock\");\n\n // Assertion to check bid stays stable during entire bus clock\n property dma_axi_bid_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_bvalid & (dma_axi_bid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_bid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_bid_stable: assert property (dma_axi_bid_stable) else\n $display(\"DMA AXI bid changed in middle of bus clock\");\n\n // Assertion to check rvalid stays stable during entire bus clock\n property dma_axi_rvalid_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_rvalid != $past(dma_axi_rvalid)) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_rvalid_stable: assert property (dma_axi_rvalid_stable) else\n $display(\"DMA AXI bvalid changed in middle of bus clock\");\n\n // Assertion to check rvalid stays stable if bready is low\n property dma_axi_rvalid_stable_till_ready;\n @(posedge clk) disable iff(~rst_l) (~dma_axi_rvalid && $past(dma_axi_rvalid)) |-> $past(dma_axi_rready);\n endproperty\n assert_dma_axi_rvalid_stable_till_ready: assert property (dma_axi_rvalid_stable_till_ready) else\n $display(\"DMA AXI bvalid changed in middle of bus clock\");\n\n // Assertion to check rresp stays stable during entire bus clock\n property dma_axi_rresp_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_rvalid & (dma_axi_rresp[1:0] != $past(dma_axi_rresp[1:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_rresp_stable: assert property (dma_axi_rresp_stable) else\n $display(\"DMA AXI bresp changed in middle of bus clock\");\n\n // Assertion to check rid stays stable during entire bus clock\n property dma_axi_rid_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_rvalid & (dma_axi_rid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_rid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_rid_stable: assert property (dma_axi_rid_stable) else\n $display(\"DMA AXI bid changed in middle of bus clock\");\n\n // Assertion to check rdata stays stable during entire bus clock\n property dma_axi_rdata_stable;\n @(posedge clk) disable iff(~rst_l) (dma_axi_rvalid & (dma_axi_rdata[63:0] != $past(dma_axi_rdata[63:0]))) |-> $past(dma_bus_clk_en);\n endproperty\n assert_dma_axi_rdata_stable: assert property (dma_axi_rdata_stable) else\n $display(\"DMA AXI bid changed in middle of bus clock\");\n\n`endif\n\nendmodule // el2_dma_ctrl\n" }, { "path": "design/el2_mem.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n// Copyright (c) 2023 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n\nmodule el2_mem\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n(\n input logic clk,\n input logic rst_l,\n input logic dccm_clk_override,\n input logic icm_clk_override,\n input logic dec_tlu_core_ecc_disable,\n\n //DCCM ports\n input logic dccm_wren,\n input logic dccm_rden,\n input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,\n input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,\n input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,\n input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,\n\n\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,\n\n //ICCM ports\n input logic [pt.ICCM_BITS-1:1] iccm_rw_addr,\n input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle\n input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle\n input logic iccm_wren,\n input logic iccm_rden,\n input logic [2:0] iccm_wr_size,\n input logic [77:0] iccm_wr_data,\n\n output logic [63:0] iccm_rd_data,\n output logic [77:0] iccm_rd_data_ecc,\n\n // Icache and Itag Ports\n\n input logic [31:1] ic_rw_addr,\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,\n input logic ic_rd_en,\n input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.\n input logic ic_sel_premux_data, // Premux data sel\n\n input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC\n input logic [70:0] ic_debug_wr_data, // Debug wr cache.\n output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.\n input logic ic_debug_rd_en, // Icache debug rd\n input logic ic_debug_wr_en, // Icache debug wr\n input logic ic_debug_tag_array, // Debug tag array\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.\n\n output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n output logic [25:0] ictag_debug_rd_data,// Debug icache tag.\n\n\n output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank\n output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,\n output logic ic_tag_perr, // Icache Tag parity error\n\n el2_mem_if.veer_sram_src mem_export,\n el2_mem_if.veer_icache_src icache_export,\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n\n);\n\n logic active_clk;\n rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );\n\n el2_mem_if mem_export_local ();\n\n assign mem_export_local.clk = clk;\n\n assign mem_export .clk = clk;\n assign mem_export .iccm_clken = mem_export_local.iccm_clken;\n assign mem_export .iccm_wren_bank = mem_export_local.iccm_wren_bank;\n assign mem_export .iccm_addr_bank = mem_export_local.iccm_addr_bank;\n assign mem_export .iccm_bank_wr_data = mem_export_local.iccm_bank_wr_data;\n assign mem_export .iccm_bank_wr_ecc = mem_export_local.iccm_bank_wr_ecc;\n assign mem_export_local.iccm_bank_dout = mem_export. iccm_bank_dout;\n assign mem_export_local.iccm_bank_ecc = mem_export. iccm_bank_ecc;\n\n assign mem_export .dccm_clken = mem_export_local.dccm_clken;\n assign mem_export .dccm_wren_bank = mem_export_local.dccm_wren_bank;\n assign mem_export .dccm_addr_bank = mem_export_local.dccm_addr_bank;\n assign mem_export .dccm_wr_data_bank = mem_export_local.dccm_wr_data_bank;\n assign mem_export .dccm_wr_ecc_bank = mem_export_local.dccm_wr_ecc_bank;\n assign mem_export_local.dccm_bank_dout = mem_export .dccm_bank_dout;\n assign mem_export_local.dccm_bank_ecc = mem_export .dccm_bank_ecc;\n\n // icache data\n assign icache_export .ic_b_sb_wren = mem_export_local.ic_b_sb_wren;\n assign icache_export .ic_b_sb_bit_en_vec = mem_export_local.ic_b_sb_bit_en_vec;\n assign icache_export .ic_sb_wr_data = mem_export_local.ic_sb_wr_data;\n assign icache_export .ic_rw_addr_bank_q = mem_export_local.ic_rw_addr_bank_q;\n assign icache_export .ic_bank_way_clken_final = mem_export_local.ic_bank_way_clken_final;\n assign icache_export .ic_bank_way_clken_final_up = mem_export_local.ic_bank_way_clken_final_up;\n assign mem_export_local.wb_packeddout_pre = icache_export .wb_packeddout_pre;\n assign mem_export_local.wb_dout_pre_up = icache_export .wb_dout_pre_up;\n\n // icache tag\n assign icache_export .ic_tag_clken_final = mem_export_local.ic_tag_clken_final;\n assign icache_export .ic_tag_wren_q = mem_export_local.ic_tag_wren_q;\n assign icache_export .ic_tag_wren_biten_vec = mem_export_local.ic_tag_wren_biten_vec;\n assign icache_export .ic_tag_wr_data = mem_export_local.ic_tag_wr_data;\n assign icache_export .ic_rw_addr_q = mem_export_local.ic_rw_addr_q;\n assign mem_export_local.ic_tag_data_raw_packed_pre = icache_export .ic_tag_data_raw_packed_pre;\n assign mem_export_local.ic_tag_data_raw_pre = icache_export .ic_tag_data_raw_pre;\n\n // DCCM Instantiation\n if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable\n el2_lsu_dccm_mem #(.pt(pt)) dccm (\n .clk_override(dccm_clk_override),\n .dccm_mem_export(mem_export_local.veer_dccm),\n .*\n );\n end else begin: Gen_dccm_disable\n assign dccm_rd_data_lo = '0;\n assign dccm_rd_data_hi = '0;\n end\n\nif ( pt.ICACHE_ENABLE ) begin: icache\n el2_ifu_ic_mem #(.pt(pt)) icm (\n .clk_override(icm_clk_override),\n .icache_export(mem_export_local.veer_icache_src),\n .*\n );\nend\nelse begin\n assign ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] = '0;\n assign ic_tag_perr = '0 ;\n assign ic_rd_data = '0 ;\n assign ictag_debug_rd_data = '0 ;\n assign ic_debug_rd_data = '0 ;\n assign ic_eccerr = '0;\n assign ic_parerr = '0;\nend // else: !if( pt.ICACHE_ENABLE )\n\n\n\nif (pt.ICCM_ENABLE) begin : iccm\n el2_ifu_iccm_mem #(.pt(pt)) iccm (.*,\n .clk_override(icm_clk_override),\n .iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]),\n .iccm_rd_data(iccm_rd_data[63:0]),\n .iccm_mem_export(mem_export_local.veer_iccm)\n );\nend\nelse begin\n assign iccm_rd_data = '0 ;\n assign iccm_rd_data_ecc = '0 ;\nend\n\n\nendmodule\n" }, { "path": "design/el2_pic_ctrl.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n\n//********************************************************************************\n// Function: Programmable Interrupt Controller\n// Comments:\n//********************************************************************************\n\nmodule el2_pic_ctrl \nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n\n input logic clk, // Core clock\n input logic free_clk, // free clock\n input logic rst_l, // Reset for all flops\n input logic clk_override, // Clock over-ride for gating\n input logic io_clk_override, // PIC IO Clock over-ride for gating\n input logic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req, // Interrupt requests\n input logic [31:0] picm_rdaddr, // Address of the register\n input logic [31:0] picm_wraddr, // Address of the register\n input logic [31:0] picm_wr_data, // Data to be written to the register\n input logic picm_wren, // Write enable to the register\n input logic picm_rden, // Read enable for the register\n input logic picm_mken, // Read the Mask for the register\n input logic [3:0] meicurpl, // Current Priority Level\n input logic [3:0] meipt, // Current Priority Threshold\n\n output logic mexintpend, // External Inerrupt request to the core\n output logic [7:0] claimid, // Claim Id of the requested interrupt\n output logic [3:0] pl, // Priority level of the requested interrupt\n output logic [31:0] picm_rd_data, // Read data of the register\n output logic mhwakeup, // Wake-up interrupt request\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // scan mode\n /*pragma coverage on*/\n\n);\n\nlocalparam NUM_LEVELS = $clog2(pt.PIC_TOTAL_INT_PLUS1);\nlocalparam INTPRIORITY_BASE_ADDR = pt.PIC_BASE_ADDR ;\nlocalparam INTPEND_BASE_ADDR = pt.PIC_BASE_ADDR + 32'h00001000 ;\nlocalparam INTENABLE_BASE_ADDR = pt.PIC_BASE_ADDR + 32'h00002000 ;\nlocalparam EXT_INTR_PIC_CONFIG = pt.PIC_BASE_ADDR + 32'h00003000 ;\nlocalparam EXT_INTR_GW_CONFIG = pt.PIC_BASE_ADDR + 32'h00004000 ;\nlocalparam EXT_INTR_GW_CLEAR = pt.PIC_BASE_ADDR + 32'h00005000 ;\n\n\nlocalparam INTPEND_SIZE = (pt.PIC_TOTAL_INT_PLUS1 <= 32) ? 32 :\n (pt.PIC_TOTAL_INT_PLUS1 <= 64) ? 64 :\n (pt.PIC_TOTAL_INT_PLUS1 <= 128) ? 128 :\n (pt.PIC_TOTAL_INT_PLUS1 <= 256) ? 256 :\n (pt.PIC_TOTAL_INT_PLUS1 <= 512) ? 512 : 1024 ;\n\nlocalparam INT_GRPS = INTPEND_SIZE / 32 ;\nlocalparam INTPRIORITY_BITS = 4 ;\nlocalparam ID_BITS = 8 ;\nlocalparam int GW_CONFIG[pt.PIC_TOTAL_INT_PLUS1-1:0] = '{default:0} ;\n\nlocalparam INT_ENABLE_GRPS = (pt.PIC_TOTAL_INT_PLUS1 - 1) / 4 ;\n\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_clk_enable ;\n//logic [INT_ENABLE_GRPS:0] intenable_clk_enable_grp ;\nlogic [INT_ENABLE_GRPS:0] gw_clk ;\n\nlogic addr_intpend_base_match;\n\nlogic raddr_config_pic_match ;\nlogic raddr_intenable_base_match;\nlogic raddr_intpriority_base_match;\nlogic raddr_config_gw_base_match ;\n\nlogic waddr_config_pic_match ;\nlogic waddr_intpriority_base_match;\nlogic waddr_intenable_base_match;\nlogic waddr_config_gw_base_match ;\nlogic addr_clear_gw_base_match ;\n\nlogic mexintpend_in;\nlogic mhwakeup_in ;\nlogic intpend_reg_read ;\n\nlogic [31:0] picm_rd_data_in, intpend_rd_out;\nlogic intenable_rd_out ;\nlogic [INTPRIORITY_BITS-1:0] intpriority_rd_out;\nlogic [1:0] gw_config_rd_out;\n\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] [INTPRIORITY_BITS-1:0] intpriority_reg;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] [INTPRIORITY_BITS-1:0] intpriority_reg_inv;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] intpriority_reg_we;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] intpriority_reg_re;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] [1:0] gw_config_reg;\n\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_reg;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_reg_we;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] intenable_reg_re;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] gw_config_reg_we;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] gw_config_reg_re;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] gw_clear_reg_we;\n\nlogic [INTPEND_SIZE-1:0] intpend_reg_extended;\n\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] [INTPRIORITY_BITS-1:0] intpend_w_prior_en;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] [ID_BITS-1:0] intpend_id;\nlogic [INTPRIORITY_BITS-1:0] maxint;\nlogic [INTPRIORITY_BITS-1:0] selected_int_priority;\nlogic [INT_GRPS-1:0] [31:0] intpend_rd_part_out ;\n\nlogic config_reg;\nlogic intpriord;\nlogic config_reg_we ;\nlogic config_reg_re ;\nlogic config_reg_in ;\nlogic intpriority_reg_read ;\nlogic intenable_reg_read ;\nlogic gw_config_reg_read ;\nlogic picm_wren_ff , picm_rden_ff ;\nlogic [31:0] picm_raddr_ff;\nlogic [31:0] picm_waddr_ff;\nlogic [31:0] picm_wr_data_ff;\nlogic [3:0] mask;\nlogic picm_mken_ff;\nlogic [ID_BITS-1:0] claimid_in ;\nlogic [INTPRIORITY_BITS-1:0] pl_in ;\nlogic [INTPRIORITY_BITS-1:0] pl_in_q ;\n\n//logic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req_sync;\nlogic [pt.PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req_gw;\n logic picm_bypass_ff;\n\n// clkens\n logic pic_raddr_c1_clken;\n logic pic_waddr_c1_clken;\n logic pic_data_c1_clken;\n logic pic_pri_c1_clken;\n logic pic_int_c1_clken;\n logic gw_config_c1_clken;\n\n// clocks\n logic pic_raddr_c1_clk;\n logic pic_data_c1_clk;\n logic pic_pri_c1_clk;\n logic pic_int_c1_clk;\n logic gw_config_c1_clk;\n\n// ---- Clock gating section ------\n// c1 clock enables\n assign pic_raddr_c1_clken = picm_mken | picm_rden | clk_override;\n assign pic_data_c1_clken = picm_wren | clk_override;\n assign pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | clk_override;\n assign pic_int_c1_clken = (waddr_intenable_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff) | clk_override;\n assign gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | clk_override;\n\n // C1 - 1 clock pulse for data\n rvoclkhdr pic_addr_c1_cgc ( .en(pic_raddr_c1_clken), .l1clk(pic_raddr_c1_clk), .* );\n rvoclkhdr pic_data_c1_cgc ( .en(pic_data_c1_clken), .l1clk(pic_data_c1_clk), .* );\n rvoclkhdr pic_pri_c1_cgc ( .en(pic_pri_c1_clken), .l1clk(pic_pri_c1_clk), .* );\n rvoclkhdr pic_int_c1_cgc ( .en(pic_int_c1_clken), .l1clk(pic_int_c1_clk), .* );\n rvoclkhdr gw_config_c1_cgc ( .en(gw_config_c1_clken), .l1clk(gw_config_c1_clk), .* );\n\n// ------ end clock gating section ------------------------\n\nassign raddr_intenable_base_match = (picm_raddr_ff[31:NUM_LEVELS+2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS+2]) ;\nassign raddr_intpriority_base_match = (picm_raddr_ff[31:NUM_LEVELS+2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS+2]) ;\nassign raddr_config_gw_base_match = (picm_raddr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS+2]) ;\nassign raddr_config_pic_match = (picm_raddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0]) ;\n\nassign addr_intpend_base_match = (picm_raddr_ff[31:6] == INTPEND_BASE_ADDR[31:6]) ;\n\nassign waddr_config_pic_match = (picm_waddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0]) ;\nassign addr_clear_gw_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CLEAR[31:NUM_LEVELS+2]) ;\nassign waddr_intpriority_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS+2]) ;\nassign waddr_intenable_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS+2]) ;\nassign waddr_config_gw_base_match = (picm_waddr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS+2]) ;\n\n assign picm_bypass_ff = picm_rden_ff & picm_wren_ff & ( picm_raddr_ff[31:0] == picm_waddr_ff[31:0] ); // pic writes and reads to same address together\n\n\nrvdff #(32) picm_radd_flop (.*, .din (picm_rdaddr), .dout(picm_raddr_ff), .clk(pic_raddr_c1_clk));\nrvdff #(32) picm_wadd_flop (.*, .din (picm_wraddr), .dout(picm_waddr_ff), .clk(pic_data_c1_clk));\nrvdff #(1) picm_wre_flop (.*, .din (picm_wren), .dout(picm_wren_ff), .clk(free_clk));\nrvdff #(1) picm_rde_flop (.*, .din (picm_rden), .dout(picm_rden_ff), .clk(free_clk));\nrvdff #(1) picm_mke_flop (.*, .din (picm_mken), .dout(picm_mken_ff), .clk(free_clk));\nrvdff #(32) picm_dat_flop (.*, .din (picm_wr_data[31:0]), .dout(picm_wr_data_ff[31:0]), .clk(pic_data_c1_clk));\n\n//rvsyncss #(pt.PIC_TOTAL_INT_PLUS1-1) sync_inst\n//(\n// .clk (free_clk),\n// .dout(extintsrc_req_sync[pt.PIC_TOTAL_INT_PLUS1-1:1]),\n// .din (extintsrc_req[pt.PIC_TOTAL_INT_PLUS1-1:1]),\n// .*) ;\n//\n//assign extintsrc_req_sync[0] = extintsrc_req[0];\n/*\ngenvar p ;\nfor (p=0; p<=INT_ENABLE_GRPS ; p++) begin : IO_CLK_GRP\n if (p==INT_ENABLE_GRPS) begin : LAST_GRP\n assign intenable_clk_enable_grp[p] = |intenable_clk_enable[pt.PIC_TOTAL_INT_PLUS1-1 : p*4] | io_clk_override;\n rvoclkhdr intenable_c1_cgc ( .en(intenable_clk_enable_grp[p]), .l1clk(gw_clk[p]), .* );\n end else begin : CLK_GRPS\n assign intenable_clk_enable_grp[p] = |intenable_clk_enable[p*4+3 : p*4] | io_clk_override;\n rvoclkhdr intenable_c1_cgc ( .en(intenable_clk_enable_grp[p]), .l1clk(gw_clk[p]), .* );\n end\nend\n*/\n\n\n\ngenvar i ;\ngenvar p ;\nfor (p=0; p<=INT_ENABLE_GRPS ; p++) begin : IO_CLK_GRP\nwire grp_clk, grp_clken;\n\n assign grp_clken = |intenable_clk_enable[(p==INT_ENABLE_GRPS?pt.PIC_TOTAL_INT_PLUS1-1:p*4+3) : p*4] | io_clk_override;\n\n `ifndef RV_FPGA_OPTIMIZE\n rvclkhdr intenable_c1_cgc( .en(grp_clken), .l1clk(grp_clk), .* );\n `else\n/*pragma coverage off*/\n assign gw_clk[p] = 1'b0 ;\n/*pragma coverage on*/\n `endif\n\n for(genvar i= (p==0 ? 1: 0); i< (p==INT_ENABLE_GRPS ? pt.PIC_TOTAL_INT_PLUS1-p*4 :4); i++) begin : GW\n el2_configurable_gw gw_inst(\n .*,\n .gw_clk(grp_clk),\n .rawclk(clk),\n .clken (grp_clken),\n .extintsrc_req(extintsrc_req[i+p*4]) ,\n .meigwctrl_polarity(gw_config_reg[i+p*4][0]) ,\n .meigwctrl_type(gw_config_reg[i+p*4][1]) ,\n .meigwclr(gw_clear_reg_we[i+p*4]) ,\n .extintsrc_req_config(extintsrc_req_gw[i+p*4])\n );\n end\nend\n\n\n\n\n\n\n\n\nfor (i=0; i 0 ) begin : NON_ZERO_INT\n assign intpriority_reg_we[i] = waddr_intpriority_base_match & (picm_waddr_ff[NUM_LEVELS+1:2] == i) & picm_wren_ff;\n assign intpriority_reg_re[i] = raddr_intpriority_base_match & (picm_raddr_ff[NUM_LEVELS+1:2] == i) & picm_rden_ff;\n\n assign intenable_reg_we[i] = waddr_intenable_base_match & (picm_waddr_ff[NUM_LEVELS+1:2] == i) & picm_wren_ff;\n assign intenable_reg_re[i] = raddr_intenable_base_match & (picm_raddr_ff[NUM_LEVELS+1:2] == i) & picm_rden_ff;\n\n assign gw_config_reg_we[i] = waddr_config_gw_base_match & (picm_waddr_ff[NUM_LEVELS+1:2] == i) & picm_wren_ff;\n assign gw_config_reg_re[i] = raddr_config_gw_base_match & (picm_raddr_ff[NUM_LEVELS+1:2] == i) & picm_rden_ff;\n\n assign gw_clear_reg_we[i] = addr_clear_gw_base_match & (picm_waddr_ff[NUM_LEVELS+1:2] == i) & picm_wren_ff ;\n\n rvdffs #(INTPRIORITY_BITS) intpriority_ff (.*, .en( intpriority_reg_we[i]), .din (picm_wr_data_ff[INTPRIORITY_BITS-1:0]), .dout(intpriority_reg[i]), .clk(pic_pri_c1_clk));\n rvdffs #(1) intenable_ff (.*, .en( intenable_reg_we[i]), .din (picm_wr_data_ff[0]), .dout(intenable_reg[i]), .clk(pic_int_c1_clk));\n rvdffs #(2) gw_config_ff (.*, .en( gw_config_reg_we[i]), .din (picm_wr_data_ff[1:0]), .dout(gw_config_reg[i]), .clk(gw_config_c1_clk));\n\n assign intenable_clk_enable[i] = gw_config_reg[i][1] | intenable_reg_we[i] | intenable_reg[i] | gw_clear_reg_we[i] ;\n\n/*\n rvsyncss_fpga #(1) sync_inst\n (\n .gw_clk (gw_clk[i/4]),\n .rawclk (clk),\n .clken (intenable_clk_enable_grp[i/4]),\n .dout (extintsrc_req_sync[i]),\n .din (extintsrc_req[i]),\n .*) ;\n\n\n\n\n\n el2_configurable_gw config_gw_inst(.*,\n .gw_clk(gw_clk[i/4]),\n .rawclk(clk),\n .clken (intenable_clk_enable_grp[i/4]),\n .extintsrc_req_sync(extintsrc_req_sync[i]) ,\n .meigwctrl_polarity(gw_config_reg[i][0]) ,\n .meigwctrl_type(gw_config_reg[i][1]) ,\n .meigwclr(gw_clear_reg_we[i]) ,\n .extintsrc_req_config(extintsrc_req_gw[i])\n );\n */\n\n end else begin : INT_ZERO\n assign intpriority_reg_we[i] = 1'b0 ;\n assign intpriority_reg_re[i] = 1'b0 ;\n assign intenable_reg_we[i] = 1'b0 ;\n assign intenable_reg_re[i] = 1'b0 ;\n\n assign gw_config_reg_we[i] = 1'b0 ;\n assign gw_config_reg_re[i] = 1'b0 ;\n assign gw_clear_reg_we[i] = 1'b0 ;\n\n assign gw_config_reg[i] = '0 ;\n\n assign intpriority_reg[i] = {INTPRIORITY_BITS{1'b0}} ;\n assign intenable_reg[i] = 1'b0 ;\n assign extintsrc_req_gw[i] = 1'b0 ;\n// assign extintsrc_req_sync[i] = 1'b0 ;\n assign intenable_clk_enable[i] = 1'b0;\n end\n\n\n assign intpriority_reg_inv[i] = intpriord ? ~intpriority_reg[i] : intpriority_reg[i] ;\n\n assign intpend_w_prior_en[i] = {INTPRIORITY_BITS{(extintsrc_req_gw[i] & intenable_reg[i])}} & intpriority_reg_inv[i] ;\n assign intpend_id[i] = i ;\nend\n\n\n assign pl_in[INTPRIORITY_BITS-1:0] = selected_int_priority[INTPRIORITY_BITS-1:0] ;\n\n//if (pt.PIC_2CYCLE == 1) begin : genblock\n//end\n//else begin : genblock\n//end\n\n genvar l, m , j, k;\n\nif (pt.PIC_2CYCLE == 1) begin : genblock\n logic [NUM_LEVELS/2:0] [pt.PIC_TOTAL_INT_PLUS1+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en;\n logic [NUM_LEVELS/2:0] [pt.PIC_TOTAL_INT_PLUS1+2:0] [ID_BITS-1:0] level_intpend_id;\n logic [NUM_LEVELS:NUM_LEVELS/2] [(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] [INTPRIORITY_BITS-1:0] levelx_intpend_w_prior_en;\n logic [NUM_LEVELS:NUM_LEVELS/2] [(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] [ID_BITS-1:0] levelx_intpend_id;\n\n assign level_intpend_w_prior_en[0][pt.PIC_TOTAL_INT_PLUS1+2:0] = {4'b0,4'b0,4'b0,intpend_w_prior_en[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;\n assign level_intpend_id[0][pt.PIC_TOTAL_INT_PLUS1+2:0] = {8'b0,8'b0,8'b0,intpend_id[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;\n\n logic [(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0] [INTPRIORITY_BITS-1:0] l2_intpend_w_prior_en_ff;\n logic [(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0] [ID_BITS-1:0] l2_intpend_id_ff;\n\n assign levelx_intpend_w_prior_en[NUM_LEVELS/2][(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] = {{1*INTPRIORITY_BITS{1'b0}},l2_intpend_w_prior_en_ff[(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0]} ;\n assign levelx_intpend_id[NUM_LEVELS/2][(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2))+1:0] = {{1*ID_BITS{1'b1}},l2_intpend_id_ff[(pt.PIC_TOTAL_INT_PLUS1/2**(NUM_LEVELS/2)):0]} ;\n/// Do the prioritization of the interrupts here ////////////\n for (l=0; l meipt_inv[INTPRIORITY_BITS-1:0]) &\n ( selected_int_priority[INTPRIORITY_BITS-1:0] > meicurpl_inv[INTPRIORITY_BITS-1:0]) );\nrvdff #(1) mexintpend_ff (.*, .clk(free_clk), .din (mexintpend_in), .dout(mexintpend));\n\nassign maxint[INTPRIORITY_BITS-1:0] = intpriord ? 0 : 15 ;\nassign mhwakeup_in = ( pl_in_q[INTPRIORITY_BITS-1:0] == maxint) ;\nrvdff #(1) wake_up_ff (.*, .clk(free_clk), .din (mhwakeup_in), .dout(mhwakeup));\n\n\n\n\n\n//////////////////////////////////////////////////////////////////////////\n// Reads of register.\n// 1- intpending\n//////////////////////////////////////////////////////////////////////////\n\nassign intpend_reg_read = addr_intpend_base_match & picm_rden_ff ;\nassign intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff;\nassign intenable_reg_read = raddr_intenable_base_match & picm_rden_ff;\nassign gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff;\n\nassign intpend_reg_extended[INTPEND_SIZE-1:0] = {{INTPEND_SIZE-pt.PIC_TOTAL_INT_PLUS1{1'b0}},extintsrc_req_gw[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;\n\n for (i=0; i<(INT_GRPS); i++) begin\n assign intpend_rd_part_out[i] = (({32{intpend_reg_read & picm_raddr_ff[5:2] == i}}) & intpend_reg_extended[((32*i)+31):(32*i)]) ;\n end\n\n always_comb begin : INTPEND_RD\n intpend_rd_out = '0 ;\n for (int i=0; i\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\nmodule el2_pmp\n import el2_pkg::*;\n#(\n parameter PMP_CHANNELS = 3,\n // Granularity of NAPOT access,\n // 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.\n parameter PMP_GRANULARITY = 0, // TODO: Move to veer.config\n `include \"el2_param.vh\"\n) (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n /* pragma coverage off */\n input logic scan_mode, // Scan mode\n /* pragma coverage on */\n\n`ifdef RV_SMEPMP\n input el2_mseccfg_pkt_t mseccfg, // mseccfg CSR content, RLB, MMWP and MML bits\n`endif\n\n`ifdef RV_USER_MODE\n input logic priv_mode_ns, // operating privilege mode (next clock cycle)\n input logic priv_mode_eff, // operating effective privilege mode\n`endif\n\n input el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],\n input logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],\n\n input logic [31:0] pmp_chan_addr[PMP_CHANNELS],\n input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS],\n output logic pmp_chan_err [PMP_CHANNELS]\n);\n\n logic [ 33:0] csr_pmp_addr_i [pt.PMP_ENTRIES];\n logic [ 33:0] pmp_req_addr_i [ PMP_CHANNELS];\n\n logic [ 33:0] region_start_addr [pt.PMP_ENTRIES];\n logic [33:PMP_GRANULARITY+2] region_addr_mask [pt.PMP_ENTRIES];\n logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_gt;\n logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_lt;\n logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_eq;\n logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_match_all;\n logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_basic_perm_check;\n logic [ PMP_CHANNELS-1:0][pt.PMP_ENTRIES-1:0] region_perm_check;\n\n`ifdef RV_USER_MODE\n logic any_region_enabled;\n`endif\n\n ///////////////////////\n // Functions for PMP //\n ///////////////////////\n\n // Flow of the PMP checking operation follows as below\n //\n // basic_perm_check ---> perm_check_wrapper ---> orig_perm_check ---/\n // |\n // region_match_all -----------------> access_fault_check <----------\n // |\n // \\--> pmp_chan_err\n\n // A wrapper function in which it is decided which form of permission check function gets called\n function automatic logic perm_check_wrapper(el2_mseccfg_pkt_t csr_pmp_mseccfg,\n el2_pmp_cfg_pkt_t csr_pmp_cfg,\n el2_pmp_type_pkt_t req_type,\n logic priv_mode,\n logic permission_check);\n\n return csr_pmp_mseccfg.MML ? mml_perm_check(csr_pmp_cfg,\n req_type,\n priv_mode,\n permission_check) :\n orig_perm_check(csr_pmp_cfg.lock,\n priv_mode,\n permission_check);\n endfunction\n\n // Compute permissions checks that apply when MSECCFG.MML is set. Added for Smepmp support.\n function automatic logic mml_perm_check(el2_pmp_cfg_pkt_t csr_pmp_cfg,\n el2_pmp_type_pkt_t pmp_req_type,\n logic priv_mode,\n logic permission_check);\n logic result;\n logic unused_cfg = |csr_pmp_cfg.mode;\n\n if (!csr_pmp_cfg.read && csr_pmp_cfg.write) begin\n // Special-case shared regions where R = 0, W = 1\n unique case ({csr_pmp_cfg.lock, csr_pmp_cfg.execute})\n // Read/write in M, read only in U\n 2'b00: result =\n (pmp_req_type == READ) |\n ((pmp_req_type == WRITE) & ~priv_mode);\n // Read/write in M/U\n 2'b01: result =\n (pmp_req_type == READ) |\n (pmp_req_type == WRITE);\n // Execute only on M/U\n 2'b10: result = (pmp_req_type == EXEC);\n // Read/execute in M, execute only on U\n 2'b11: result =\n (pmp_req_type == EXEC) |\n ((pmp_req_type == READ) & ~priv_mode);\n /* pragma coverage off */\n default: ;\n /* pragma coverage on */\n endcase\n end else begin\n if (csr_pmp_cfg.read & csr_pmp_cfg.write & csr_pmp_cfg.execute & csr_pmp_cfg.lock) begin\n // Special-case shared read only region when R = 1, W = 1, X = 1, L = 1\n result = (pmp_req_type == READ);\n end else begin\n // Otherwise use basic permission check. Permission is always denied if in U mode and\n // L is set or if in M mode and L is unset.\n result = permission_check & (priv_mode ? ~csr_pmp_cfg.lock : csr_pmp_cfg.lock);\n end\n end\n return result;\n endfunction\n\n // Compute permissions checks that apply when MSECCFG.MML is unset. This is the original PMP\n // behaviour before Smepmp was added.\n function automatic logic orig_perm_check(logic pmp_cfg_lock,\n logic priv_mode,\n logic permission_check);\n // For M-mode, any region which matches with the L-bit clear, or with sufficient\n // access permissions will be allowed.\n // For other modes, the lock bit doesn't matter\n return priv_mode ? (permission_check) : (~pmp_cfg_lock | permission_check);\n endfunction\n\n // Access fault determination / prioritization\n function automatic logic access_fault_check(el2_mseccfg_pkt_t csr_pmp_mseccfg,\n el2_pmp_type_pkt_t req_type,\n logic [pt.PMP_ENTRIES-1:0] match_all,\n logic any_region_enabled,\n logic priv_mode,\n logic [pt.PMP_ENTRIES-1:0] final_perm_check);\n\n`ifdef RV_USER_MODE\n `ifdef RV_SMEPMP\n // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other\n // modes. Also deny unmatched for M-mode when MSECCFG.MML is set and request type is EXEC.\n logic access_fail = csr_pmp_mseccfg.MMWP | priv_mode |\n (csr_pmp_mseccfg.MML && (req_type == EXEC));\n `else\n // When in user mode and at least one PMP region is enabled deny access by default.\n logic access_fail = any_region_enabled & priv_mode;\n `endif\n`else\n logic access_fail = 1'b0;\n`endif\n\n logic matched = 1'b0;\n\n // PMP entries are statically prioritized, from 0 to N-1\n // The lowest-numbered PMP entry which matches an address determines accessibility\n for (int r = 0; r < pt.PMP_ENTRIES; r++) begin\n if (!matched && match_all[r]) begin\n access_fail = ~final_perm_check[r];\n matched = 1'b1;\n end\n end\n return access_fail;\n endfunction\n\n // ---------------\n // Access checking\n // ---------------\n\n`ifdef RV_USER_MODE\n logic [pt.PMP_ENTRIES-1:0] region_enabled;\n for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_reg_ena\n assign region_enabled[r] = pmp_pmpcfg[r].mode != OFF;\n end\n assign any_region_enabled = |region_enabled;\n`endif\n\n for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_addr_exp\n assign csr_pmp_addr_i[r] = {\n pmp_pmpaddr[r], 2'b00\n }; // addr conv.: word @ 32-bit -> byte @ 34-bit\n // Start address for TOR matching\n if (r == 0) begin : g_entry0\n assign region_start_addr[r] = (pmp_pmpcfg[r].mode == TOR) ? 34'h000000000 : csr_pmp_addr_i[r];\n end else begin : g_oth\n assign region_start_addr[r] = (pmp_pmpcfg[r].mode == TOR) ? csr_pmp_addr_i[r-1] :\n csr_pmp_addr_i[r];\n end\n // Address mask for NA matching\n for (genvar b = PMP_GRANULARITY + 2; b < 34; b++) begin : g_bitmask\n if (b == 2) begin : g_bit0\n // Always mask bit 2 for NAPOT\n assign region_addr_mask[r][b] = (pmp_pmpcfg[r].mode != NAPOT);\n end else begin : g_others\n // We will mask this bit if it is within the programmed granule\n // i.e. addr = yyyy 0111\n // ^\n // | This bit pos is the top of the mask, all lower bits set\n // thus mask = 1111 0000\n if (PMP_GRANULARITY == 0) begin : g_region_addr_mask_zero_granularity\n assign region_addr_mask[r][b] = (pmp_pmpcfg[r].mode != NAPOT) |\n ~&csr_pmp_addr_i[r][b-1:2];\n end else begin : g_region_addr_mask_other_granularity\n assign region_addr_mask[r][b] = (pmp_pmpcfg[r].mode != NAPOT) |\n ~&csr_pmp_addr_i[r][b-1:PMP_GRANULARITY+1];\n end\n end\n end\n end\n\n`ifdef RV_USER_MODE\n logic [PMP_CHANNELS-1:0] pmp_priv_mode_eff;\n for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_priv_mode_eff\n assign pmp_priv_mode_eff[c] = (\n ((pmp_chan_type[c] == EXEC) & priv_mode_ns) |\n ((pmp_chan_type[c] != EXEC) & priv_mode_eff)); // RW affected by mstatus.MPRV\n end\n`endif\n\n for (genvar c = 0; c < PMP_CHANNELS; c++) begin : g_access_check\n assign pmp_req_addr_i[c] = {2'b00, pmp_chan_addr[c]}; // addr. widening: 32-bit -> 34-bit\n for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions\n // Comparators are sized according to granularity\n assign region_match_eq[c][r] = (pmp_req_addr_i[c][33:PMP_GRANULARITY+2] &\n region_addr_mask[r]) ==\n (region_start_addr[r][33:PMP_GRANULARITY+2] &\n region_addr_mask[r]);\n assign region_match_gt[c][r] = pmp_req_addr_i[c][33:PMP_GRANULARITY+2] >\n region_start_addr[r][33:PMP_GRANULARITY+2];\n assign region_match_lt[c][r] = pmp_req_addr_i[c][33:PMP_GRANULARITY+2] <\n csr_pmp_addr_i[r][33:PMP_GRANULARITY+2];\n\n always_comb begin\n region_match_all[c][r] = 1'b0;\n unique case (pmp_pmpcfg[r].mode)\n OFF: region_match_all[c][r] = 1'b0;\n NA4: region_match_all[c][r] = region_match_eq[c][r];\n NAPOT: region_match_all[c][r] = region_match_eq[c][r];\n TOR: begin\n region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &\n region_match_lt[c][r];\n end\n default: region_match_all[c][r] = 1'b0;\n endcase\n end\n\n // Basic permission check compares cfg register only.\n assign region_basic_perm_check[c][r] =\n ((pmp_chan_type[c] == EXEC) & pmp_pmpcfg[r].execute) |\n ((pmp_chan_type[c] == WRITE) & pmp_pmpcfg[r].write) |\n ((pmp_chan_type[c] == READ) & pmp_pmpcfg[r].read);\n\n // Check specific required permissions since the behaviour is different\n // between Smepmp implementation and original PMP.\n assign region_perm_check[c][r] = perm_check_wrapper(\n`ifdef RV_SMEPMP\n mseccfg,\n`else\n 3'b000,\n`endif\n pmp_pmpcfg[r],\n pmp_chan_type[c],\n`ifdef RV_USER_MODE\n pmp_priv_mode_eff[c],\n`else\n 1'b0,\n`endif\n region_basic_perm_check[c][r]\n );\n\n // Address bits below PMP granularity (which starts at 4 byte) are deliberately unused.\n logic unused_sigs;\n assign unused_sigs = ^{region_start_addr[r][PMP_GRANULARITY+2-1:0],\n pmp_req_addr_i[c][PMP_GRANULARITY+2-1:0]};\n end\n\n // Once the permission checks of the regions are done, decide if the access is\n // denied by figuring out the matching region and its permission check.\n assign pmp_chan_err[c] = access_fault_check(\n`ifdef RV_SMEPMP\n mseccfg,\n`else\n 3'b000,\n`endif\n pmp_chan_type[c],\n region_match_all[c],\n`ifdef RV_USER_MODE\n any_region_enabled,\n pmp_priv_mode_eff[c],\n`else\n 1'b0,\n 1'b0,\n`endif\n region_perm_check[c]);\n\n end\n\nendmodule // el2_pmp\n" }, { "path": "design/el2_veer.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n// Function: Top level VeeR core file\n// Comments:\n//\n//********************************************************************************\nmodule el2_veer\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic clk,\n input logic rst_l,\n input logic dbg_rst_l,\n // rst_vec is supposed to be connected to a constant in the top level\n /*pragma coverage off*/\n input logic [31:1] rst_vec,\n /*pragma coverage on*/\n input logic nmi_int,\n // nmi_vec is supposed to be connected to a constant in the top level\n /*pragma coverage off*/\n input logic [31:1] nmi_vec,\n /*pragma coverage on*/\n output logic core_rst_l, // This is \"rst_l | dbg_rst_l\"\n\n output logic active_l2clk,\n output logic free_l2clk,\n\n output logic [31:0] trace_rv_i_insn_ip,\n output logic [31:0] trace_rv_i_address_ip,\n output logic trace_rv_i_valid_ip,\n output logic trace_rv_i_exception_ip,\n output logic [4:0] trace_rv_i_ecause_ip,\n output logic trace_rv_i_interrupt_ip,\n output logic [31:0] trace_rv_i_tval_ip,\n\n\n output logic dccm_clk_override,\n output logic icm_clk_override,\n output logic dec_tlu_core_ecc_disable,\n\n // external halt/run interface\n input logic i_cpu_halt_req, // Asynchronous Halt request to CPU\n input logic i_cpu_run_req, // Asynchronous Restart request to CPU\n output logic o_cpu_halt_ack, // Core Acknowledge to Halt request\n output logic o_cpu_halt_status, // 1'b1 indicates processor is halted\n output logic o_cpu_run_ack, // Core Acknowledge to run request\n output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request\n\n /*pragma coverage off*/\n input logic [31:4] core_id, // CORE ID\n /*pragma coverage on*/\n\n // external MPC halt/run interface\n input logic mpc_debug_halt_req, // Async halt request\n input logic mpc_debug_run_req, // Async run request\n input logic mpc_reset_run_req, // Run/halt after reset\n output logic mpc_debug_halt_ack, // Halt ack\n output logic mpc_debug_run_ack, // Run ack\n output logic debug_brkpt_status, // debug breakpoint\n\n output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc\n output logic dec_tlu_perfcnt1,\n output logic dec_tlu_perfcnt2,\n output logic dec_tlu_perfcnt3,\n\n // DCCM ports\n output logic dccm_wren,\n output logic dccm_rden,\n output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,\n output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,\n output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,\n output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,\n\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,\n\n // ICCM ports\n output logic [pt.ICCM_BITS-1:1] iccm_rw_addr,\n output logic iccm_wren,\n output logic iccm_rden,\n output logic [2:0] iccm_wr_size,\n output logic [77:0] iccm_wr_data,\n output logic iccm_buf_correct_ecc,\n output logic iccm_correction_state,\n\n input logic [63:0] iccm_rd_data,\n input logic [77:0] iccm_rd_data_ecc,\n\n // ICache , ITAG ports\n output logic [31:1] ic_rw_addr,\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,\n output logic ic_rd_en,\n\n output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC\n input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [25:0] ictag_debug_rd_data,// Debug icache tag.\n output logic [70:0] ic_debug_wr_data, // Debug wr cache.\n\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,\n output logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.\n output logic ic_sel_premux_data, // Select premux data\n\n\n output logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.\n output logic ic_debug_rd_en, // Icache debug rd\n output logic ic_debug_wr_en, // Icache debug wr\n output logic ic_debug_tag_array, // Debug tag array\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.\n\n\n\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,\n input logic ic_tag_perr, // Icache Tag parity error\n\n //-------------------------- LSU AXI signals--------------------------\n // AXI Write Channels\n output logic lsu_axi_awvalid,\n input logic lsu_axi_awready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,\n output logic [31:0] lsu_axi_awaddr,\n output logic [3:0] lsu_axi_awregion,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_awlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_awsize,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_awburst,\n output logic lsu_axi_awlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_awcache,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_awprot,\n output logic [3:0] lsu_axi_awqos,\n /*pragma coverage on*/\n\n output logic lsu_axi_wvalid,\n input logic lsu_axi_wready,\n output logic [63:0] lsu_axi_wdata,\n output logic [7:0] lsu_axi_wstrb,\n output logic lsu_axi_wlast,\n\n input logic lsu_axi_bvalid,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic lsu_axi_bready,\n /*pragma coverage on*/\n input logic [1:0] lsu_axi_bresp,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,\n\n // AXI Read Channels\n output logic lsu_axi_arvalid,\n input logic lsu_axi_arready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,\n output logic [31:0] lsu_axi_araddr,\n output logic [3:0] lsu_axi_arregion,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_arlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_arsize,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_arburst,\n output logic lsu_axi_arlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_arcache,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_arprot,\n output logic [3:0] lsu_axi_arqos,\n /*pragma coverage on*/\n\n input logic lsu_axi_rvalid,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic lsu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,\n input logic [63:0] lsu_axi_rdata,\n input logic [1:0] lsu_axi_rresp,\n input logic lsu_axi_rlast,\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv\n IFU does not use AXI write channel */\n /*pragma coverage off*/\n output logic ifu_axi_awvalid,\n input logic ifu_axi_awready,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,\n output logic [31:0] ifu_axi_awaddr,\n output logic [3:0] ifu_axi_awregion,\n output logic [7:0] ifu_axi_awlen,\n output logic [2:0] ifu_axi_awsize,\n output logic [1:0] ifu_axi_awburst,\n output logic ifu_axi_awlock,\n output logic [3:0] ifu_axi_awcache,\n output logic [2:0] ifu_axi_awprot,\n output logic [3:0] ifu_axi_awqos,\n\n output logic ifu_axi_wvalid,\n input logic ifu_axi_wready,\n output logic [63:0] ifu_axi_wdata,\n output logic [7:0] ifu_axi_wstrb,\n output logic ifu_axi_wlast,\n\n input logic ifu_axi_bvalid,\n output logic ifu_axi_bready,\n input logic [1:0] ifu_axi_bresp,\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,\n /*pragma coverage on*/\n\n // AXI Read Channels\n output logic ifu_axi_arvalid,\n input logic ifu_axi_arready,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,\n output logic [31:0] ifu_axi_araddr,\n output logic [3:0] ifu_axi_arregion,\n /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */\n /*pragma coverage off*/\n output logic [7:0] ifu_axi_arlen,\n output logic [2:0] ifu_axi_arsize,\n output logic [1:0] ifu_axi_arburst,\n output logic ifu_axi_arlock,\n output logic [3:0] ifu_axi_arcache,\n output logic [2:0] ifu_axi_arprot,\n output logic [3:0] ifu_axi_arqos,\n /*pragma coverage on*/\n\n input logic ifu_axi_rvalid,\n /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */\n /*pragma coverage off*/\n output logic ifu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,\n input logic [63:0] ifu_axi_rdata,\n input logic [1:0] ifu_axi_rresp,\n input logic ifu_axi_rlast,\n\n //-------------------------- SB AXI signals--------------------------\n // AXI Write Channels\n output logic sb_axi_awvalid,\n input logic sb_axi_awready,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,\n /*pragma coverage on*/\n output logic [31:0] sb_axi_awaddr,\n output logic [3:0] sb_axi_awregion,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [7:0] sb_axi_awlen,\n /*pragma coverage on*/\n output logic [2:0] sb_axi_awsize,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [1:0] sb_axi_awburst,\n output logic sb_axi_awlock,\n output logic [3:0] sb_axi_awcache,\n output logic [2:0] sb_axi_awprot,\n output logic [3:0] sb_axi_awqos,\n /*pragma coverage on*/\n\n output logic sb_axi_wvalid,\n input logic sb_axi_wready,\n output logic [63:0] sb_axi_wdata,\n output logic [7:0] sb_axi_wstrb,\n output logic sb_axi_wlast,\n\n input logic sb_axi_bvalid,\n output logic sb_axi_bready,\n input logic [1:0] sb_axi_bresp,\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,\n\n // AXI Read Channels\n output logic sb_axi_arvalid,\n input logic sb_axi_arready,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,\n /*pragma coverage on*/\n output logic [31:0] sb_axi_araddr,\n output logic [3:0] sb_axi_arregion,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [7:0] sb_axi_arlen,\n /*pragma coverage on*/\n output logic [2:0] sb_axi_arsize,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [1:0] sb_axi_arburst,\n output logic sb_axi_arlock,\n output logic [3:0] sb_axi_arcache,\n output logic [2:0] sb_axi_arprot,\n output logic [3:0] sb_axi_arqos,\n /*pragma coverage on*/\n\n input logic sb_axi_rvalid,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic sb_axi_rready,\n /*pragma coverage on*/\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,\n input logic [63:0] sb_axi_rdata,\n input logic [1:0] sb_axi_rresp,\n input logic sb_axi_rlast,\n\n //-------------------------- DMA AXI signals--------------------------\n // AXI Write Channels\n input logic dma_axi_awvalid,\n output logic dma_axi_awready,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,\n input logic [31:0] dma_axi_awaddr,\n input logic [2:0] dma_axi_awsize,\n input logic [2:0] dma_axi_awprot,\n input logic [7:0] dma_axi_awlen,\n input logic [1:0] dma_axi_awburst,\n\n\n input logic dma_axi_wvalid,\n output logic dma_axi_wready,\n input logic [63:0] dma_axi_wdata,\n input logic [7:0] dma_axi_wstrb,\n input logic dma_axi_wlast,\n\n output logic dma_axi_bvalid,\n input logic dma_axi_bready,\n output logic [1:0] dma_axi_bresp,\n output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,\n\n // AXI Read Channels\n input logic dma_axi_arvalid,\n output logic dma_axi_arready,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,\n input logic [31:0] dma_axi_araddr,\n input logic [2:0] dma_axi_arsize,\n input logic [2:0] dma_axi_arprot,\n input logic [7:0] dma_axi_arlen,\n input logic [1:0] dma_axi_arburst,\n\n output logic dma_axi_rvalid,\n input logic dma_axi_rready,\n output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,\n output logic [63:0] dma_axi_rdata,\n output logic [1:0] dma_axi_rresp,\n output logic dma_axi_rlast,\n\n\n //// AHB LITE BUS\n output logic [31:0] haddr,\n /* exclude signals that are tied to constant value in axi4_to_ahb.sv */\n /*pragma coverage off*/\n output logic [2:0] hburst,\n output logic hmastlock,\n /*pragma coverage on*/\n output logic [3:0] hprot,\n output logic [2:0] hsize,\n output logic [1:0] htrans,\n output logic hwrite,\n\n input logic [63:0] hrdata,\n input logic hready,\n input logic hresp,\n\n // LSU AHB Master\n output logic [31:0] lsu_haddr,\n /* exclude signals that are tied to constant value in axi4_to_ahb.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_hburst,\n output logic lsu_hmastlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_hprot,\n output logic [2:0] lsu_hsize,\n output logic [1:0] lsu_htrans,\n output logic lsu_hwrite,\n output logic [63:0] lsu_hwdata,\n\n input logic [63:0] lsu_hrdata,\n input logic lsu_hready,\n input logic lsu_hresp,\n\n //System Bus Debug Master\n output logic [31:0] sb_haddr,\n /* exclude signals that are tied to constant value in axi4_to_ahb.sv */\n /*pragma coverage off*/\n output logic [2:0] sb_hburst,\n output logic sb_hmastlock,\n /*pragma coverage on*/\n output logic [3:0] sb_hprot,\n output logic [2:0] sb_hsize,\n output logic [1:0] sb_htrans,\n output logic sb_hwrite,\n output logic [63:0] sb_hwdata,\n\n input logic [63:0] sb_hrdata,\n input logic sb_hready,\n input logic sb_hresp,\n\n // DMA Slave\n input logic dma_hsel,\n input logic [31:0] dma_haddr,\n input logic [2:0] dma_hburst,\n input logic dma_hmastlock,\n input logic [3:0] dma_hprot,\n input logic [2:0] dma_hsize,\n input logic [1:0] dma_htrans,\n input logic dma_hwrite,\n input logic [63:0] dma_hwdata,\n input logic dma_hreadyin,\n\n output logic [63:0] dma_hrdata,\n output logic dma_hreadyout,\n output logic dma_hresp,\n\n input logic lsu_bus_clk_en,\n input logic ifu_bus_clk_en,\n input logic dbg_bus_clk_en,\n input logic dma_bus_clk_en,\n\n input logic dmi_reg_en, // read or write\n input logic [6:0] dmi_reg_addr, // address of DM register\n input logic dmi_reg_wr_en, // write instruction\n input logic [31:0] dmi_reg_wdata, // write data\n output logic [31:0] dmi_reg_rdata,\n\n // ICCM/DCCM ECC status\n output logic iccm_ecc_single_error,\n output logic iccm_ecc_double_error,\n output logic dccm_ecc_single_error,\n output logic dccm_ecc_double_error,\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n // Register file\n el2_regfile_if.veer_rf_src regfile,\n`endif\n\n input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,\n input logic timer_int,\n input logic soft_int,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n);\n\n\n\n\n logic [63:0] hwdata_nc;\n //----------------------------------------------------------------------\n //\n //----------------------------------------------------------------------\n\n logic ifu_pmu_instr_aligned;\n logic ifu_ic_error_start;\n logic ifu_iccm_dma_rd_ecc_single_err;\n logic ifu_iccm_rd_ecc_single_err;\n logic ifu_iccm_rd_ecc_double_err;\n logic lsu_dccm_rd_ecc_single_err;\n logic lsu_dccm_rd_ecc_double_err;\n\n logic lsu_axi_awready_ahb;\n logic lsu_axi_wready_ahb;\n logic lsu_axi_bvalid_ahb;\n logic lsu_axi_bready_ahb;\n logic [1:0] lsu_axi_bresp_ahb;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_ahb;\n logic lsu_axi_arready_ahb;\n logic lsu_axi_rvalid_ahb;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_ahb;\n logic [63:0] lsu_axi_rdata_ahb;\n logic [1:0] lsu_axi_rresp_ahb;\n logic lsu_axi_rlast_ahb;\n\n logic lsu_axi_awready_int;\n logic lsu_axi_wready_int;\n logic lsu_axi_bvalid_int;\n logic [1:0] lsu_axi_bresp_int;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_int;\n logic lsu_axi_arready_int;\n logic lsu_axi_rvalid_int;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_int;\n logic [63:0] lsu_axi_rdata_int;\n logic [1:0] lsu_axi_rresp_int;\n logic lsu_axi_rlast_int;\n\n logic ifu_axi_awready_ahb;\n logic ifu_axi_wready_ahb;\n logic ifu_axi_bvalid_ahb;\n logic ifu_axi_bready_ahb;\n logic [1:0] ifu_axi_bresp_ahb;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_ahb;\n logic ifu_axi_arready_ahb;\n logic ifu_axi_rvalid_ahb;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_ahb;\n logic [63:0] ifu_axi_rdata_ahb;\n logic [1:0] ifu_axi_rresp_ahb;\n logic ifu_axi_rlast_ahb;\n\n logic ifu_axi_awready_int;\n logic ifu_axi_wready_int;\n logic ifu_axi_bvalid_int;\n logic [1:0] ifu_axi_bresp_int;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_int;\n logic ifu_axi_arready_int;\n logic ifu_axi_rvalid_int;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_int;\n logic [63:0] ifu_axi_rdata_int;\n logic [1:0] ifu_axi_rresp_int;\n logic ifu_axi_rlast_int;\n\n logic sb_axi_awready_ahb;\n logic sb_axi_wready_ahb;\n logic sb_axi_bvalid_ahb;\n logic sb_axi_bready_ahb;\n logic [1:0] sb_axi_bresp_ahb;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_bid_ahb;\n logic sb_axi_arready_ahb;\n logic sb_axi_rvalid_ahb;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_rid_ahb;\n logic [63:0] sb_axi_rdata_ahb;\n logic [1:0] sb_axi_rresp_ahb;\n logic sb_axi_rlast_ahb;\n\n logic sb_axi_awready_int;\n logic sb_axi_wready_int;\n logic sb_axi_bvalid_int;\n logic [1:0] sb_axi_bresp_int;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_bid_int;\n logic sb_axi_arready_int;\n logic sb_axi_rvalid_int;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_rid_int;\n logic [63:0] sb_axi_rdata_int;\n logic [1:0] sb_axi_rresp_int;\n logic sb_axi_rlast_int;\n\n logic dma_axi_awvalid_ahb;\n /* exclude signals that are tied to constant value in ahb_to_axi4.sv */\n /*pragma coverage off*/\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_ahb;\n /*pragma coverage on*/\n logic [31:0] dma_axi_awaddr_ahb;\n logic [2:0] dma_axi_awsize_ahb;\n /* exclude signals that are tied to constant value in ahb_to_axi4.sv */\n /*pragma coverage off*/\n logic [2:0] dma_axi_awprot_ahb;\n logic [7:0] dma_axi_awlen_ahb;\n logic [1:0] dma_axi_awburst_ahb;\n /*pragma coverage on*/\n logic dma_axi_wvalid_ahb;\n logic [63:0] dma_axi_wdata_ahb;\n logic [7:0] dma_axi_wstrb_ahb;\n /* exclude signals that are tied to constant value in ahb_to_axi4.sv */\n /*pragma coverage off*/\n logic dma_axi_wlast_ahb;\n logic dma_axi_bready_ahb;\n /*pragma coverage on*/\n logic dma_axi_arvalid_ahb;\n /* exclude signals that are tied to constant value in ahb_to_axi4.sv */\n /*pragma coverage off*/\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_ahb;\n /*pragma coverage on*/\n logic [31:0] dma_axi_araddr_ahb;\n logic [2:0] dma_axi_arsize_ahb;\n /* exclude signals that are tied to constant value in ahb_to_axi4.sv */\n /*pragma coverage off*/\n logic [2:0] dma_axi_arprot_ahb;\n logic [7:0] dma_axi_arlen_ahb;\n logic [1:0] dma_axi_arburst_ahb;\n logic dma_axi_rready_ahb;\n /*pragma coverage on*/\n\n logic dma_axi_awvalid_int;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_int;\n logic [31:0] dma_axi_awaddr_int;\n logic [2:0] dma_axi_awsize_int;\n logic [2:0] dma_axi_awprot_int;\n logic [7:0] dma_axi_awlen_int;\n logic [1:0] dma_axi_awburst_int;\n logic dma_axi_wvalid_int;\n logic [63:0] dma_axi_wdata_int;\n logic [7:0] dma_axi_wstrb_int;\n logic dma_axi_wlast_int;\n logic dma_axi_bready_int;\n logic dma_axi_arvalid_int;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_int;\n logic [31:0] dma_axi_araddr_int;\n logic [2:0] dma_axi_arsize_int;\n logic [2:0] dma_axi_arprot_int;\n logic [7:0] dma_axi_arlen_int;\n logic [1:0] dma_axi_arburst_int;\n logic dma_axi_rready_int;\n\n\n// Icache debug\n logic [70:0] ifu_ic_debug_rd_data; // diagnostic icache read data\n logic ifu_ic_debug_rd_data_valid; // diagnostic icache read data valid\n el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics\n\n\n logic dec_i0_rs1_en_d;\n logic dec_i0_rs2_en_d;\n logic [31:0] gpr_i0_rs1_d;\n logic [31:0] gpr_i0_rs2_d;\n\n logic [31:0] dec_i0_result_r;\n logic [31:0] exu_i0_result_x;\n logic [31:1] exu_i0_pc_x;\n logic [31:1] exu_npc_r;\n\n el2_alu_pkt_t i0_ap;\n\n // Trigger signals\n el2_trigger_pkt_t [3:0] trigger_pkt_any;\n logic [3:0] lsu_trigger_match_m;\n\n\n logic [31:0] dec_i0_immed_d;\n logic [12:1] dec_i0_br_immed_d;\n logic dec_i0_select_pc_d;\n\n logic [31:1] dec_i0_pc_d;\n logic [3:0] dec_i0_rs1_bypass_en_d;\n logic [3:0] dec_i0_rs2_bypass_en_d;\n\n logic dec_i0_alu_decode_d;\n logic dec_i0_branch_d;\n\n logic ifu_miss_state_idle;\n logic dec_tlu_flush_noredir_r;\n logic dec_tlu_flush_leak_one_r;\n logic dec_tlu_flush_err_r;\n logic ifu_i0_valid;\n logic [31:0] ifu_i0_instr;\n logic [31:1] ifu_i0_pc;\n\n logic exu_flush_final;\n\n logic [31:1] exu_flush_path_final;\n\n logic [31:0] exu_lsu_rs1_d;\n logic [31:0] exu_lsu_rs2_d;\n\n\n el2_lsu_pkt_t lsu_p;\n logic dec_qual_lsu_d;\n\n logic dec_lsu_valid_raw_d;\n logic [11:0] dec_lsu_offset_d;\n\n logic [31:0] lsu_result_m;\n logic [31:0] lsu_result_corr_r; // This is the ECC corrected data going to RF\n logic lsu_single_ecc_error_incr; // Increment the ecc counter\n el2_lsu_error_pkt_t lsu_error_pkt_r;\n logic lsu_imprecise_error_load_any;\n logic lsu_imprecise_error_store_any;\n logic [31:0] lsu_imprecise_error_addr_any;\n logic lsu_load_stall_any; // This is for blocking loads\n logic lsu_store_stall_any; // This is for blocking stores\n logic lsu_idle_any; // doesn't include DMA\n logic lsu_active; // lsu is active. used for clock\n\n\n logic [31:1] lsu_fir_addr; // fast interrupt address\n logic [1:0] lsu_fir_error; // Error during fast interrupt lookup\n\n // Non-blocking loads\n logic lsu_nonblock_load_valid_m;\n logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m;\n logic lsu_nonblock_load_inv_r;\n logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r;\n logic lsu_nonblock_load_data_valid;\n logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag;\n logic [31:0] lsu_nonblock_load_data;\n\n logic dec_csr_ren_d;\n logic [31:0] dec_csr_rddata_d;\n\n logic [31:0] exu_csr_rs1_x;\n\n logic dec_tlu_i0_commit_cmt;\n logic dec_tlu_flush_lower_r;\n logic dec_tlu_flush_lower_wb;\n logic dec_tlu_i0_kill_writeb_r; // I0 is flushed, don't writeback any results to arch state\n logic dec_tlu_fence_i_r; // flush is a fence_i rfnpc, flush icache\n\n logic [31:1] dec_tlu_flush_path_r;\n logic [31:0] dec_tlu_mrac_ff; // CSR for memory region control\n\n logic ifu_i0_pc4;\n\n el2_mul_pkt_t mul_p;\n\n el2_div_pkt_t div_p;\n logic dec_div_cancel;\n\n logic [31:0] exu_div_result;\n logic exu_div_wren;\n\n logic dec_i0_decode_d;\n\n\n logic [31:1] pred_correct_npc_x;\n\n el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;\n\n el2_predict_pkt_t exu_mp_pkt;\n logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr;\n logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr;\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;\n logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag;\n\n logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r;\n logic [1:0] exu_i0_br_hist_r;\n logic exu_i0_br_error_r;\n logic exu_i0_br_start_error_r;\n logic exu_i0_br_valid_r;\n logic exu_i0_br_mp_r;\n logic exu_i0_br_middle_r;\n\n logic exu_i0_br_way_r;\n\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;\n\n logic dma_dccm_req;\n logic dma_iccm_req;\n logic [2:0] dma_mem_tag;\n logic [31:0] dma_mem_addr;\n logic [2:0] dma_mem_sz;\n logic dma_mem_write;\n logic [63:0] dma_mem_wdata;\n\n logic dccm_dma_rvalid;\n logic dccm_dma_ecc_error;\n logic [2:0] dccm_dma_rtag;\n logic [63:0] dccm_dma_rdata;\n logic iccm_dma_rvalid;\n logic iccm_dma_ecc_error;\n logic [2:0] iccm_dma_rtag;\n logic [63:0] iccm_dma_rdata;\n\n logic dma_dccm_stall_any; // Stall the ld/st in decode if asserted\n logic dma_iccm_stall_any; // Stall the fetch\n logic dccm_ready;\n logic iccm_ready;\n\n logic dma_pmu_dccm_read;\n logic dma_pmu_dccm_write;\n logic dma_pmu_any_read;\n logic dma_pmu_any_write;\n\n logic ifu_i0_icaf;\n logic [1:0] ifu_i0_icaf_type;\n\n\n logic ifu_i0_icaf_second;\n logic ifu_i0_dbecc;\n logic iccm_dma_sb_error;\n\n el2_br_pkt_t i0_brp;\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;\n logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;\n logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;\n\n logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;\n logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index\n\n\n el2_predict_pkt_t dec_i0_predict_p_d;\n\n logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d; // DEC predict fghr\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d; // DEC predict index\n logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d; // DEC predict branch tag\n\n // PIC ports\n logic picm_wren;\n logic picm_rden;\n logic picm_mken;\n logic [31:0] picm_rdaddr;\n logic [31:0] picm_wraddr;\n logic [31:0] picm_wr_data;\n logic [31:0] picm_rd_data;\n\n // feature disable from mfdc\n logic dec_tlu_external_ldfwd_disable; // disable external load forwarding\n logic dec_tlu_bpred_disable;\n logic dec_tlu_wb_coalescing_disable;\n logic dec_tlu_sideeffect_posted_disable;\n logic [2:0] dec_tlu_dma_qos_prty; // DMA QoS priority coming from MFDC [18:16]\n\n // clock gating overrides from mcgc\n logic dec_tlu_misc_clk_override;\n logic dec_tlu_ifu_clk_override;\n logic dec_tlu_lsu_clk_override;\n logic dec_tlu_bus_clk_override;\n logic dec_tlu_pic_clk_override;\n logic dec_tlu_dccm_clk_override;\n logic dec_tlu_icm_clk_override;\n\n logic dec_tlu_picio_clk_override;\n\n assign dccm_clk_override = dec_tlu_dccm_clk_override; // dccm memory\n assign icm_clk_override = dec_tlu_icm_clk_override; // icache/iccm memory\n\n // PMP Signals\n el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES];\n logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES];\n logic [31:0] pmp_chan_addr [3];\n el2_pmp_type_pkt_t pmp_chan_type [3];\n logic pmp_chan_err [3];\n\n logic [31:1] ifu_pmp_addr;\n logic ifu_pmp_error;\n logic [31:0] lsu_pmp_addr_start;\n logic lsu_pmp_error_start;\n logic [31:0] lsu_pmp_addr_end;\n logic lsu_pmp_error_end;\n logic lsu_pmp_we;\n logic lsu_pmp_re;\n\n // -----------------------DEBUG START -------------------------------\n\n logic [31:0] dbg_cmd_addr; // the address of the debug command to used by the core\n logic [31:0] dbg_cmd_wrdata; // If the debug command is a write command, this has the data to be written to the CSR/GPR\n logic dbg_cmd_valid; // commad is being driven by the dbg module. One pulse. Only dirven when core_halted has been seen\n logic dbg_cmd_write; // 1: write command; 0: read_command\n logic [1:0] dbg_cmd_type; // 0:gpr 1:csr 2: memory\n logic [1:0] dbg_cmd_size; // size of the abstract mem access debug command\n logic dbg_halt_req; // Sticky signal indicating that the debug module wants to start the entering of debug mode ( start the halting sequence )\n logic dbg_resume_req; // Sticky signal indicating that the debug module wants to resume from debug mode\n logic dbg_core_rst_l; // Core reset from DM\n\n logic core_dbg_cmd_done; // Final muxed cmd done to debug\n logic core_dbg_cmd_fail; // Final muxed cmd done to debug\n logic [31:0] core_dbg_rddata; // Final muxed cmd done to debug\n\n logic dma_dbg_cmd_done; // Abstarct memory command sent to dma is done\n logic dma_dbg_cmd_fail; // Abstarct memory command sent to dma failed\n logic [31:0] dma_dbg_rddata; // Read data for abstract memory access\n\n logic dbg_dma_bubble; // Debug needs a bubble to send a valid\n logic dma_dbg_ready; // DMA is ready to accept debug request\n\n logic [31:0] dec_dbg_rddata; // The core drives this data ( intercepts the pipe and sends it here )\n logic dec_dbg_cmd_done; // This will be treated like a valid signal\n logic dec_dbg_cmd_fail; // Abstract command failed\n logic dec_tlu_mpc_halted_only; // Only halted due to MPC\n logic dec_tlu_dbg_halted; // The core has finished the queiscing sequence. Sticks this signal high\n logic dec_tlu_resume_ack;\n logic dec_tlu_debug_mode; // Core is in debug mode\n logic dec_debug_wdata_rs1_d;\n logic dec_tlu_force_halt; // halt has been forced\n\n logic [1:0] dec_data_en;\n logic [1:0] dec_ctl_en;\n\n // PMU Signals\n logic exu_pmu_i0_br_misp;\n logic exu_pmu_i0_br_ataken;\n logic exu_pmu_i0_pc4;\n\n logic lsu_pmu_load_external_m;\n logic lsu_pmu_store_external_m;\n logic lsu_pmu_misaligned_m;\n logic lsu_pmu_bus_trxn;\n logic lsu_pmu_bus_misaligned;\n logic lsu_pmu_bus_error;\n logic lsu_pmu_bus_busy;\n\n logic ifu_pmu_fetch_stall;\n logic ifu_pmu_ic_miss;\n logic ifu_pmu_ic_hit;\n logic ifu_pmu_bus_error;\n logic ifu_pmu_bus_busy;\n logic ifu_pmu_bus_trxn;\n\n logic active_state;\n logic free_clk;\n logic active_clk;\n logic dec_pause_state_cg;\n\n logic lsu_nonblock_load_data_error;\n\n logic [15:0] ifu_i0_cinst;\n\n// fast interrupt\n logic [31:2] dec_tlu_meihap;\n logic dec_extint_stall;\n\n el2_trace_pkt_t trace_rv_trace_pkt;\n\n\n logic lsu_fastint_stall_any;\n\n logic [7:0] pic_claimid;\n logic [3:0] pic_pl, dec_tlu_meicurpl, dec_tlu_meipt;\n logic mexintpend;\n logic mhwakeup;\n\n logic dma_active;\n\n\n logic pause_state;\n logic halt_state;\n\n logic dec_tlu_core_empty;\n\n assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;\n\n assign halt_state = o_cpu_halt_status & ~(dma_active | lsu_active);\n\n\n assign active_state = (~(halt_state | pause_state) | dec_tlu_flush_lower_r | dec_tlu_flush_lower_wb) | dec_tlu_misc_clk_override;\n\n rvoclkhdr free_cg2 ( .clk(clk), .en(1'b1), .l1clk(free_l2clk), .* );\n rvoclkhdr active_cg2 ( .clk(clk), .en(active_state), .l1clk(active_l2clk), .* );\n\n// all other clock headers are 1st level\n rvoclkhdr free_cg1 ( .clk(free_l2clk), .en(1'b1), .l1clk(free_clk), .* );\n rvoclkhdr active_cg1 ( .clk(active_l2clk), .en(1'b1), .l1clk(active_clk), .* );\n\n\n assign core_dbg_cmd_done = dma_dbg_cmd_done | dec_dbg_cmd_done;\n assign core_dbg_cmd_fail = dma_dbg_cmd_fail | dec_dbg_cmd_fail;\n assign core_dbg_rddata[31:0] = dma_dbg_cmd_done ? dma_dbg_rddata[31:0] : dec_dbg_rddata[31:0];\n\n el2_dbg #(.pt(pt)) dbg (\n .rst_l(core_rst_l),\n .clk(free_l2clk),\n .clk_override(dec_tlu_misc_clk_override),\n\n // AXI signals\n .sb_axi_awready(sb_axi_awready_int),\n .sb_axi_wready(sb_axi_wready_int),\n .sb_axi_bvalid(sb_axi_bvalid_int),\n .sb_axi_bresp(sb_axi_bresp_int[1:0]),\n\n .sb_axi_arready(sb_axi_arready_int),\n .sb_axi_rvalid(sb_axi_rvalid_int),\n .sb_axi_rdata(sb_axi_rdata_int[63:0]),\n .sb_axi_rresp(sb_axi_rresp_int[1:0]),\n .*\n );\n\n`ifdef RV_ASSERT_ON\n assert_fetch_indbghalt: assert #0 (~(ifu.ifc_fetch_req_f & dec.tlu.dbg_tlu_halted_f & ~dec.tlu.dcsr_single_step_running)) else $display(\"ERROR: Fetching in dBG halt!\");\n`endif\n\n // ----------------- DEBUG END -----------------------------\n\n assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);\n\n`ifdef RV_USER_MODE\n\n // Operating privilege mode, 0 - machine, 1 - user\n logic priv_mode;\n // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)\n logic priv_mode_eff;\n // Next privilege mode\n logic priv_mode_ns;\n\n el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP\n\n`endif\n\n // fetch\n el2_ifu #(.pt(pt)) ifu (\n .clk(active_l2clk),\n .rst_l(core_rst_l),\n .dec_tlu_flush_err_wb (dec_tlu_flush_err_r ),\n .dec_tlu_flush_noredir_wb (dec_tlu_flush_noredir_r ),\n .dec_tlu_fence_i_wb (dec_tlu_fence_i_r ),\n .dec_tlu_flush_leak_one_wb (dec_tlu_flush_leak_one_r ),\n .dec_tlu_flush_lower_wb (dec_tlu_flush_lower_r ),\n\n // AXI signals\n .ifu_axi_arready(ifu_axi_arready_int),\n .ifu_axi_rvalid(ifu_axi_rvalid_int),\n .ifu_axi_rid(ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0]),\n .ifu_axi_rdata(ifu_axi_rdata_int[63:0]),\n .ifu_axi_rresp(ifu_axi_rresp_int[1:0]),\n\n .*\n );\n\n\n assign iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || ifu_iccm_dma_rd_ecc_single_err;\n assign iccm_ecc_double_error = ifu_iccm_rd_ecc_double_err;\n\n el2_dec #(.pt(pt)) dec (\n .clk(active_l2clk),\n .dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),\n .rst_l(core_rst_l),\n .*\n );\n\n el2_exu #(.pt(pt)) exu (\n .clk(active_l2clk),\n .rst_l(core_rst_l),\n .*\n );\n\n el2_lsu #(.pt(pt)) lsu (\n .clk(active_l2clk),\n .rst_l(core_rst_l),\n .clk_override(dec_tlu_lsu_clk_override),\n .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r),\n\n // AXI signals\n .lsu_axi_awready(lsu_axi_awready_int),\n .lsu_axi_wready(lsu_axi_wready_int),\n .lsu_axi_bvalid(lsu_axi_bvalid_int),\n .lsu_axi_bid(lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0]),\n .lsu_axi_bresp(lsu_axi_bresp_int[1:0]),\n\n .lsu_axi_arready(lsu_axi_arready_int),\n .lsu_axi_rvalid(lsu_axi_rvalid_int),\n .lsu_axi_rid(lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0]),\n .lsu_axi_rdata(lsu_axi_rdata_int[63:0]),\n .lsu_axi_rresp(lsu_axi_rresp_int[1:0]),\n .lsu_axi_rlast(lsu_axi_rlast_int),\n\n .*\n\n );\n\n assign dccm_ecc_single_error = lsu_dccm_rd_ecc_single_err;\n assign dccm_ecc_double_error = lsu_dccm_rd_ecc_double_err;\n\n el2_pic_ctrl #(.pt(pt)) pic_ctrl_inst (\n .clk(free_l2clk),\n .clk_override(dec_tlu_pic_clk_override),\n .io_clk_override(dec_tlu_picio_clk_override),\n .picm_mken (picm_mken),\n .extintsrc_req({extintsrc_req[pt.PIC_TOTAL_INT:1],1'b0}),\n .pl(pic_pl[3:0]),\n .claimid(pic_claimid[7:0]),\n .meicurpl(dec_tlu_meicurpl[3:0]),\n .meipt(dec_tlu_meipt[3:0]),\n .rst_l(core_rst_l),\n .*);\n\n el2_dma_ctrl #(.pt(pt)) dma_ctrl (\n .clk(free_l2clk),\n .rst_l(core_rst_l),\n .clk_override(dec_tlu_misc_clk_override),\n\n // AXI signals\n .dma_axi_awvalid(dma_axi_awvalid_int),\n .dma_axi_awid(dma_axi_awid_int[pt.DMA_BUS_TAG-1:0]),\n .dma_axi_awaddr(dma_axi_awaddr_int[31:0]),\n .dma_axi_awsize(dma_axi_awsize_int[2:0]),\n .dma_axi_wvalid(dma_axi_wvalid_int),\n .dma_axi_wdata(dma_axi_wdata_int[63:0]),\n .dma_axi_wstrb(dma_axi_wstrb_int[7:0]),\n .dma_axi_bready(dma_axi_bready_int),\n\n .dma_axi_arvalid(dma_axi_arvalid_int),\n .dma_axi_arid(dma_axi_arid_int[pt.DMA_BUS_TAG-1:0]),\n .dma_axi_araddr(dma_axi_araddr_int[31:0]),\n .dma_axi_arsize(dma_axi_arsize_int[2:0]),\n .dma_axi_rready(dma_axi_rready_int),\n\n .*\n );\n\n assign pmp_chan_addr[0] = {ifu_pmp_addr, 1'b0};\n assign pmp_chan_type[0] = EXEC;\n assign ifu_pmp_error = pmp_chan_err[0];\n assign pmp_chan_addr[1] = lsu_pmp_addr_start;\n assign pmp_chan_type[1] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);\n assign lsu_pmp_error_start = pmp_chan_err[1];\n assign pmp_chan_addr[2] = lsu_pmp_addr_end;\n assign pmp_chan_type[2] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);\n assign lsu_pmp_error_end = pmp_chan_err[2];\n\n el2_pmp #(\n .PMP_CHANNELS(3),\n .pt(pt)\n ) pmp (\n .clk (active_l2clk),\n .rst_l(core_rst_l),\n .*\n );\n\n if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB\n\n // AXI4 -> AHB Gasket for LSU\n axi4_to_ahb #(.pt(pt),\n .TAG(pt.LSU_BUS_TAG)) lsu_axi4_to_ahb (\n\n .clk(free_l2clk),\n .free_clk(free_clk),\n .rst_l(core_rst_l),\n .clk_override(dec_tlu_bus_clk_override),\n .bus_clk_en(lsu_bus_clk_en),\n .dec_tlu_force_halt(dec_tlu_force_halt),\n\n // AXI Write Channels\n .axi_awvalid(lsu_axi_awvalid),\n .axi_awready(lsu_axi_awready_ahb),\n .axi_awid(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]),\n .axi_awaddr(lsu_axi_awaddr[31:0]),\n .axi_awsize(lsu_axi_awsize[2:0]),\n .axi_awprot(lsu_axi_awprot[2:0]),\n\n .axi_wvalid(lsu_axi_wvalid),\n .axi_wready(lsu_axi_wready_ahb),\n .axi_wdata(lsu_axi_wdata[63:0]),\n .axi_wstrb(lsu_axi_wstrb[7:0]),\n .axi_wlast(lsu_axi_wlast),\n\n .axi_bvalid(lsu_axi_bvalid_ahb),\n .axi_bready(lsu_axi_bready),\n .axi_bresp(lsu_axi_bresp_ahb[1:0]),\n .axi_bid(lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0]),\n\n // AXI Read Channels\n .axi_arvalid(lsu_axi_arvalid),\n .axi_arready(lsu_axi_arready_ahb),\n .axi_arid(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]),\n .axi_araddr(lsu_axi_araddr[31:0]),\n .axi_arsize(lsu_axi_arsize[2:0]),\n .axi_arprot(lsu_axi_arprot[2:0]),\n\n .axi_rvalid(lsu_axi_rvalid_ahb),\n .axi_rready(lsu_axi_rready),\n .axi_rid(lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0]),\n .axi_rdata(lsu_axi_rdata_ahb[63:0]),\n .axi_rresp(lsu_axi_rresp_ahb[1:0]),\n .axi_rlast(lsu_axi_rlast_ahb),\n\n // AHB-LITE signals\n .ahb_haddr(lsu_haddr[31:0]),\n .ahb_hburst(lsu_hburst),\n .ahb_hmastlock(lsu_hmastlock),\n .ahb_hprot(lsu_hprot[3:0]),\n .ahb_hsize(lsu_hsize[2:0]),\n .ahb_htrans(lsu_htrans[1:0]),\n .ahb_hwrite(lsu_hwrite),\n .ahb_hwdata(lsu_hwdata[63:0]),\n\n .ahb_hrdata(lsu_hrdata[63:0]),\n .ahb_hready(lsu_hready),\n .ahb_hresp(lsu_hresp),\n\n .*\n );\n\n axi4_to_ahb #(.pt(pt),\n .TAG(pt.IFU_BUS_TAG)) ifu_axi4_to_ahb (\n .clk(free_l2clk),\n .free_clk(free_clk),\n .rst_l(core_rst_l),\n .clk_override(dec_tlu_bus_clk_override),\n .bus_clk_en(ifu_bus_clk_en),\n .dec_tlu_force_halt(dec_tlu_force_halt),\n\n // AHB-Lite signals\n .ahb_haddr(haddr[31:0]),\n .ahb_hburst(hburst),\n .ahb_hmastlock(hmastlock),\n .ahb_hprot(hprot[3:0]),\n .ahb_hsize(hsize[2:0]),\n .ahb_htrans(htrans[1:0]),\n .ahb_hwrite(hwrite),\n .ahb_hwdata(hwdata_nc[63:0]),\n\n .ahb_hrdata(hrdata[63:0]),\n .ahb_hready(hready),\n .ahb_hresp(hresp),\n\n // AXI Write Channels\n .axi_awvalid(ifu_axi_awvalid),\n .axi_awready(ifu_axi_awready_ahb),\n .axi_awid(ifu_axi_awid[pt.IFU_BUS_TAG-1:0]),\n .axi_awaddr(ifu_axi_awaddr[31:0]),\n .axi_awsize(ifu_axi_awsize[2:0]),\n .axi_awprot(ifu_axi_awprot[2:0]),\n\n .axi_wvalid(ifu_axi_wvalid),\n .axi_wready(ifu_axi_wready_ahb),\n .axi_wdata(ifu_axi_wdata[63:0]),\n .axi_wstrb(ifu_axi_wstrb[7:0]),\n .axi_wlast(ifu_axi_wlast),\n\n .axi_bvalid(ifu_axi_bvalid_ahb),\n .axi_bready(1'b1),\n .axi_bresp(ifu_axi_bresp_ahb[1:0]),\n .axi_bid(ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0]),\n\n // AXI Read Channels\n .axi_arvalid(ifu_axi_arvalid),\n .axi_arready(ifu_axi_arready_ahb),\n .axi_arid(ifu_axi_arid[pt.IFU_BUS_TAG-1:0]),\n .axi_araddr(ifu_axi_araddr[31:0]),\n .axi_arsize(ifu_axi_arsize[2:0]),\n .axi_arprot(ifu_axi_arprot[2:0]),\n\n .axi_rvalid(ifu_axi_rvalid_ahb),\n .axi_rready(ifu_axi_rready),\n .axi_rid(ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0]),\n .axi_rdata(ifu_axi_rdata_ahb[63:0]),\n .axi_rresp(ifu_axi_rresp_ahb[1:0]),\n .axi_rlast(ifu_axi_rlast_ahb),\n .*\n );\n\n // AXI4 -> AHB Gasket for System Bus\n axi4_to_ahb #(.pt(pt),\n .TAG(pt.SB_BUS_TAG)) sb_axi4_to_ahb (\n .clk(free_l2clk),\n .free_clk(free_clk),\n .rst_l(dbg_rst_l),\n .clk_override(dec_tlu_bus_clk_override),\n .bus_clk_en(dbg_bus_clk_en),\n .dec_tlu_force_halt(1'b0),\n\n // AXI Write Channels\n .axi_awvalid(sb_axi_awvalid),\n .axi_awready(sb_axi_awready_ahb),\n .axi_awid(sb_axi_awid[pt.SB_BUS_TAG-1:0]),\n .axi_awaddr(sb_axi_awaddr[31:0]),\n .axi_awsize(sb_axi_awsize[2:0]),\n .axi_awprot(sb_axi_awprot[2:0]),\n\n .axi_wvalid(sb_axi_wvalid),\n .axi_wready(sb_axi_wready_ahb),\n .axi_wdata(sb_axi_wdata[63:0]),\n .axi_wstrb(sb_axi_wstrb[7:0]),\n .axi_wlast(sb_axi_wlast),\n\n .axi_bvalid(sb_axi_bvalid_ahb),\n .axi_bready(sb_axi_bready),\n .axi_bresp(sb_axi_bresp_ahb[1:0]),\n .axi_bid(sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0]),\n\n // AXI Read Channels\n .axi_arvalid(sb_axi_arvalid),\n .axi_arready(sb_axi_arready_ahb),\n .axi_arid(sb_axi_arid[pt.SB_BUS_TAG-1:0]),\n .axi_araddr(sb_axi_araddr[31:0]),\n .axi_arsize(sb_axi_arsize[2:0]),\n .axi_arprot(sb_axi_arprot[2:0]),\n\n .axi_rvalid(sb_axi_rvalid_ahb),\n .axi_rready(sb_axi_rready),\n .axi_rid(sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0]),\n .axi_rdata(sb_axi_rdata_ahb[63:0]),\n .axi_rresp(sb_axi_rresp_ahb[1:0]),\n .axi_rlast(sb_axi_rlast_ahb),\n // AHB-LITE signals\n .ahb_haddr(sb_haddr[31:0]),\n .ahb_hburst(sb_hburst),\n .ahb_hmastlock(sb_hmastlock),\n .ahb_hprot(sb_hprot[3:0]),\n .ahb_hsize(sb_hsize[2:0]),\n .ahb_htrans(sb_htrans[1:0]),\n .ahb_hwrite(sb_hwrite),\n .ahb_hwdata(sb_hwdata[63:0]),\n\n .ahb_hrdata(sb_hrdata[63:0]),\n .ahb_hready(sb_hready),\n .ahb_hresp(sb_hresp),\n\n .*\n );\n\n //AHB -> AXI4 Gasket for DMA\n ahb_to_axi4 #(.pt(pt),\n .TAG(pt.DMA_BUS_TAG)) dma_ahb_to_axi4 (\n .clk(free_l2clk),\n .rst_l(core_rst_l),\n .clk_override(dec_tlu_bus_clk_override),\n .bus_clk_en(dma_bus_clk_en),\n\n // AXI Write Channels\n .axi_awvalid(dma_axi_awvalid_ahb),\n .axi_awready(dma_axi_awready),\n .axi_awid(dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0]),\n .axi_awaddr(dma_axi_awaddr_ahb[31:0]),\n .axi_awsize(dma_axi_awsize_ahb[2:0]),\n .axi_awprot(dma_axi_awprot_ahb[2:0]),\n .axi_awlen(dma_axi_awlen_ahb[7:0]),\n .axi_awburst(dma_axi_awburst_ahb[1:0]),\n\n .axi_wvalid(dma_axi_wvalid_ahb),\n .axi_wready(dma_axi_wready),\n .axi_wdata(dma_axi_wdata_ahb[63:0]),\n .axi_wstrb(dma_axi_wstrb_ahb[7:0]),\n .axi_wlast(dma_axi_wlast_ahb),\n\n .axi_bvalid(dma_axi_bvalid),\n .axi_bready(dma_axi_bready_ahb),\n .axi_bresp(dma_axi_bresp[1:0]),\n .axi_bid(dma_axi_bid[pt.DMA_BUS_TAG-1:0]),\n\n // AXI Read Channels\n .axi_arvalid(dma_axi_arvalid_ahb),\n .axi_arready(dma_axi_arready),\n .axi_arid(dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0]),\n .axi_araddr(dma_axi_araddr_ahb[31:0]),\n .axi_arsize(dma_axi_arsize_ahb[2:0]),\n .axi_arprot(dma_axi_arprot_ahb[2:0]),\n .axi_arlen(dma_axi_arlen_ahb[7:0]),\n .axi_arburst(dma_axi_arburst_ahb[1:0]),\n\n .axi_rvalid(dma_axi_rvalid),\n .axi_rready(dma_axi_rready_ahb),\n .axi_rid(dma_axi_rid[pt.DMA_BUS_TAG-1:0]),\n .axi_rdata(dma_axi_rdata[63:0]),\n .axi_rresp(dma_axi_rresp[1:0]),\n\n // AHB signals\n .ahb_haddr(dma_haddr[31:0]),\n .ahb_hburst(dma_hburst),\n .ahb_hmastlock(dma_hmastlock),\n .ahb_hprot(dma_hprot[3:0]),\n .ahb_hsize(dma_hsize[2:0]),\n .ahb_htrans(dma_htrans[1:0]),\n .ahb_hwrite(dma_hwrite),\n .ahb_hwdata(dma_hwdata[63:0]),\n\n .ahb_hrdata(dma_hrdata[63:0]),\n .ahb_hreadyout(dma_hreadyout),\n .ahb_hresp(dma_hresp),\n .ahb_hreadyin(dma_hreadyin),\n .ahb_hsel(dma_hsel),\n .*\n );\n\n end\n\n // Drive the final AXI inputs\n assign lsu_axi_awready_int = pt.BUILD_AHB_LITE ? lsu_axi_awready_ahb : lsu_axi_awready;\n assign lsu_axi_wready_int = pt.BUILD_AHB_LITE ? lsu_axi_wready_ahb : lsu_axi_wready;\n assign lsu_axi_bvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_bvalid_ahb : lsu_axi_bvalid;\n assign lsu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bresp_ahb[1:0] : lsu_axi_bresp[1:0];\n assign lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_bid[pt.LSU_BUS_TAG-1:0];\n assign lsu_axi_arready_int = pt.BUILD_AHB_LITE ? lsu_axi_arready_ahb : lsu_axi_arready;\n assign lsu_axi_rvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_rvalid_ahb : lsu_axi_rvalid;\n assign lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_rid[pt.LSU_BUS_TAG-1:0];\n assign lsu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? lsu_axi_rdata_ahb[63:0] : lsu_axi_rdata[63:0];\n assign lsu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rresp_ahb[1:0] : lsu_axi_rresp[1:0];\n assign lsu_axi_rlast_int = pt.BUILD_AHB_LITE ? lsu_axi_rlast_ahb : lsu_axi_rlast;\n\n assign ifu_axi_awready_int = pt.BUILD_AHB_LITE ? ifu_axi_awready_ahb : ifu_axi_awready;\n assign ifu_axi_wready_int = pt.BUILD_AHB_LITE ? ifu_axi_wready_ahb : ifu_axi_wready;\n assign ifu_axi_bvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_bvalid_ahb : ifu_axi_bvalid;\n assign ifu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bresp_ahb[1:0] : ifu_axi_bresp[1:0];\n assign ifu_axi_bid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_bid[pt.IFU_BUS_TAG-1:0];\n assign ifu_axi_arready_int = pt.BUILD_AHB_LITE ? ifu_axi_arready_ahb : ifu_axi_arready;\n assign ifu_axi_rvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_rvalid_ahb : ifu_axi_rvalid;\n assign ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_rid[pt.IFU_BUS_TAG-1:0];\n assign ifu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? ifu_axi_rdata_ahb[63:0] : ifu_axi_rdata[63:0];\n assign ifu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rresp_ahb[1:0] : ifu_axi_rresp[1:0];\n assign ifu_axi_rlast_int = pt.BUILD_AHB_LITE ? ifu_axi_rlast_ahb : ifu_axi_rlast;\n\n assign sb_axi_awready_int = pt.BUILD_AHB_LITE ? sb_axi_awready_ahb : sb_axi_awready;\n assign sb_axi_wready_int = pt.BUILD_AHB_LITE ? sb_axi_wready_ahb : sb_axi_wready;\n assign sb_axi_bvalid_int = pt.BUILD_AHB_LITE ? sb_axi_bvalid_ahb : sb_axi_bvalid;\n assign sb_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_bresp_ahb[1:0] : sb_axi_bresp[1:0];\n assign sb_axi_bid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_bid[pt.SB_BUS_TAG-1:0];\n assign sb_axi_arready_int = pt.BUILD_AHB_LITE ? sb_axi_arready_ahb : sb_axi_arready;\n assign sb_axi_rvalid_int = pt.BUILD_AHB_LITE ? sb_axi_rvalid_ahb : sb_axi_rvalid;\n assign sb_axi_rid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_rid[pt.SB_BUS_TAG-1:0];\n assign sb_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? sb_axi_rdata_ahb[63:0] : sb_axi_rdata[63:0];\n assign sb_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_rresp_ahb[1:0] : sb_axi_rresp[1:0];\n assign sb_axi_rlast_int = pt.BUILD_AHB_LITE ? sb_axi_rlast_ahb : sb_axi_rlast;\n\n assign dma_axi_awvalid_int = pt.BUILD_AHB_LITE ? dma_axi_awvalid_ahb : dma_axi_awvalid;\n assign dma_axi_awid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_awid[pt.DMA_BUS_TAG-1:0];\n assign dma_axi_awaddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_awaddr_ahb[31:0] : dma_axi_awaddr[31:0];\n assign dma_axi_awsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awsize_ahb[2:0] : dma_axi_awsize[2:0];\n assign dma_axi_awprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awprot_ahb[2:0] : dma_axi_awprot[2:0];\n assign dma_axi_awlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_awlen_ahb[7:0] : dma_axi_awlen[7:0];\n assign dma_axi_awburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_awburst_ahb[1:0] : dma_axi_awburst[1:0];\n assign dma_axi_wvalid_int = pt.BUILD_AHB_LITE ? dma_axi_wvalid_ahb : dma_axi_wvalid;\n assign dma_axi_wdata_int[63:0] = pt.BUILD_AHB_LITE ? dma_axi_wdata_ahb[63:0] : dma_axi_wdata;\n assign dma_axi_wstrb_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_wstrb_ahb[7:0] : dma_axi_wstrb[7:0];\n assign dma_axi_wlast_int = pt.BUILD_AHB_LITE ? dma_axi_wlast_ahb : dma_axi_wlast;\n assign dma_axi_bready_int = pt.BUILD_AHB_LITE ? dma_axi_bready_ahb : dma_axi_bready;\n assign dma_axi_arvalid_int = pt.BUILD_AHB_LITE ? dma_axi_arvalid_ahb : dma_axi_arvalid;\n assign dma_axi_arid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_arid[pt.DMA_BUS_TAG-1:0];\n assign dma_axi_araddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_araddr_ahb[31:0] : dma_axi_araddr[31:0];\n assign dma_axi_arsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arsize_ahb[2:0] : dma_axi_arsize[2:0];\n assign dma_axi_arprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arprot_ahb[2:0] : dma_axi_arprot[2:0];\n assign dma_axi_arlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_arlen_ahb[7:0] : dma_axi_arlen[7:0];\n assign dma_axi_arburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_arburst_ahb[1:0] : dma_axi_arburst[1:0];\n assign dma_axi_rready_int = pt.BUILD_AHB_LITE ? dma_axi_rready_ahb : dma_axi_rready;\n\n\nif (pt.BUILD_AHB_LITE == 1) begin\n`ifdef RV_ASSERT_ON\n property ahb_trxn_aligned;\n @(posedge clk) disable iff(~rst_l) (lsu_htrans[1:0] != 2'b0) |-> ((lsu_hsize[2:0] == 3'h0) |\n ((lsu_hsize[2:0] == 3'h1) & (lsu_haddr[0] == 1'b0)) |\n ((lsu_hsize[2:0] == 3'h2) & (lsu_haddr[1:0] == 2'b0)) |\n ((lsu_hsize[2:0] == 3'h3) & (lsu_haddr[2:0] == 3'b0)));\n endproperty\n assert_ahb_trxn_aligned: assert property (ahb_trxn_aligned) else\n $display(\"Assertion ahb_trxn_aligned failed: lsu_htrans=2'h%h, lsu_hsize=3'h%h, lsu_haddr=32'h%h\",lsu_htrans[1:0], lsu_hsize[2:0], lsu_haddr[31:0]);\n\n property dma_trxn_aligned;\n @(posedge clk) disable iff(~rst_l) (dma_htrans[1:0] != 2'b0) |-> ((dma_hsize[2:0] == 3'h0) |\n ((dma_hsize[2:0] == 3'h1) & (dma_haddr[0] == 1'b0)) |\n ((dma_hsize[2:0] == 3'h2) & (dma_haddr[1:0] == 2'b0)) |\n ((dma_hsize[2:0] == 3'h3) & (dma_haddr[2:0] == 3'b0)));\n endproperty\n\n\n`endif\n end // if (pt.BUILD_AHB_LITE == 1)\n\n\n // unpack packet\n // also need retires_p==3\n\n assign trace_rv_i_insn_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_insn_ip[31:0];\n\n assign trace_rv_i_address_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_address_ip[31:0];\n\n assign trace_rv_i_valid_ip = trace_rv_trace_pkt.trace_rv_i_valid_ip;\n\n assign trace_rv_i_exception_ip = trace_rv_trace_pkt.trace_rv_i_exception_ip;\n\n assign trace_rv_i_ecause_ip[4:0] = trace_rv_trace_pkt.trace_rv_i_ecause_ip[4:0];\n\n assign trace_rv_i_interrupt_ip = trace_rv_trace_pkt.trace_rv_i_interrupt_ip;\n\n assign trace_rv_i_tval_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_tval_ip[31:0];\n\n\n\nendmodule // el2_veer\n\n" }, { "path": "design/el2_veer_lockstep.sv", "content": "// Copyright 2024 Antmicro \n//\n// SPDX-License-Identifier: Apache-2.0\n\nmodule el2_veer_lockstep\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n el2_regfile_if.veer_rf_sink main_core_regfile,\n`endif\n\n input logic clk,\n input logic rst_l,\n input logic dbg_rst_l,\n input logic [31:1] rst_vec,\n input logic nmi_int,\n input logic [31:1] nmi_vec,\n input logic core_rst_l, // This is \"rst_l | dbg_rst_l\"\n\n input logic active_l2clk,\n input logic free_l2clk,\n\n input logic [31:0] trace_rv_i_insn_ip,\n input logic [31:0] trace_rv_i_address_ip,\n input logic trace_rv_i_valid_ip,\n input logic trace_rv_i_exception_ip,\n input logic [4:0] trace_rv_i_ecause_ip,\n input logic trace_rv_i_interrupt_ip,\n input logic [31:0] trace_rv_i_tval_ip,\n\n\n input logic dccm_clk_override,\n input logic icm_clk_override,\n input logic dec_tlu_core_ecc_disable,\n\n // external halt/run interface\n input logic i_cpu_halt_req, // Asynchronous Halt request to CPU\n input logic i_cpu_run_req, // Asynchronous Restart request to CPU\n input logic o_cpu_halt_ack, // Core Acknowledge to Halt request\n input logic o_cpu_halt_status, // 1'b1 indicates processor is halted\n input logic o_cpu_run_ack, // Core Acknowledge to run request\n input logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request\n\n input logic [31:4] core_id, // CORE ID\n\n // external MPC halt/run interface\n input logic mpc_debug_halt_req, // Async halt request\n input logic mpc_debug_run_req, // Async run request\n input logic mpc_reset_run_req, // Run/halt after reset\n input logic mpc_debug_halt_ack, // Halt ack\n input logic mpc_debug_run_ack, // Run ack\n input logic debug_brkpt_status, // debug breakpoint\n\n input logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc\n input logic dec_tlu_perfcnt1,\n input logic dec_tlu_perfcnt2,\n input logic dec_tlu_perfcnt3,\n\n // DCCM ports\n input logic dccm_wren,\n input logic dccm_rden,\n input logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_lo,\n input logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_hi,\n input logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_lo,\n input logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_hi,\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,\n\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,\n\n // ICCM ports\n input logic [pt.ICCM_BITS-1:1] iccm_rw_addr,\n input logic iccm_wren,\n input logic iccm_rden,\n input logic [ 2:0] iccm_wr_size,\n input logic [ 77:0] iccm_wr_data,\n input logic iccm_buf_correct_ecc,\n input logic iccm_correction_state,\n\n input logic [63:0] iccm_rd_data,\n input logic [77:0] iccm_rd_data_ecc,\n\n // ICache , ITAG ports\n input logic [ 31:1] ic_rw_addr,\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,\n input logic ic_rd_en,\n\n input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC\n input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [25:0] ictag_debug_rd_data, // Debug icache tag.\n input logic [70:0] ic_debug_wr_data, // Debug wr cache.\n\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,\n input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.\n input logic ic_sel_premux_data, // Select premux data\n\n\n input logic [ pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.\n input logic ic_debug_rd_en, // Icache debug rd\n input logic ic_debug_wr_en, // Icache debug wr\n input logic ic_debug_tag_array, // Debug tag array\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.\n\n\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,\n input logic ic_tag_perr, // Icache Tag parity error\n\n //-------------------------- LSU AXI signals--------------------------\n // AXI Write Channels\n input logic lsu_axi_awvalid,\n input logic lsu_axi_awready,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,\n input logic [ 31:0] lsu_axi_awaddr,\n input logic [ 3:0] lsu_axi_awregion,\n input logic [ 7:0] lsu_axi_awlen,\n input logic [ 2:0] lsu_axi_awsize,\n input logic [ 1:0] lsu_axi_awburst,\n input logic lsu_axi_awlock,\n input logic [ 3:0] lsu_axi_awcache,\n input logic [ 2:0] lsu_axi_awprot,\n input logic [ 3:0] lsu_axi_awqos,\n\n input logic lsu_axi_wvalid,\n input logic lsu_axi_wready,\n input logic [63:0] lsu_axi_wdata,\n input logic [ 7:0] lsu_axi_wstrb,\n input logic lsu_axi_wlast,\n\n input logic lsu_axi_bvalid,\n input logic lsu_axi_bready,\n input logic [ 1:0] lsu_axi_bresp,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,\n\n // AXI Read Channels\n input logic lsu_axi_arvalid,\n input logic lsu_axi_arready,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,\n input logic [ 31:0] lsu_axi_araddr,\n input logic [ 3:0] lsu_axi_arregion,\n input logic [ 7:0] lsu_axi_arlen,\n input logic [ 2:0] lsu_axi_arsize,\n input logic [ 1:0] lsu_axi_arburst,\n input logic lsu_axi_arlock,\n input logic [ 3:0] lsu_axi_arcache,\n input logic [ 2:0] lsu_axi_arprot,\n input logic [ 3:0] lsu_axi_arqos,\n\n input logic lsu_axi_rvalid,\n input logic lsu_axi_rready,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,\n input logic [ 63:0] lsu_axi_rdata,\n input logic [ 1:0] lsu_axi_rresp,\n input logic lsu_axi_rlast,\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n input logic ifu_axi_awvalid,\n input logic ifu_axi_awready,\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,\n input logic [ 31:0] ifu_axi_awaddr,\n input logic [ 3:0] ifu_axi_awregion,\n input logic [ 7:0] ifu_axi_awlen,\n input logic [ 2:0] ifu_axi_awsize,\n input logic [ 1:0] ifu_axi_awburst,\n input logic ifu_axi_awlock,\n input logic [ 3:0] ifu_axi_awcache,\n input logic [ 2:0] ifu_axi_awprot,\n input logic [ 3:0] ifu_axi_awqos,\n\n input logic ifu_axi_wvalid,\n input logic ifu_axi_wready,\n input logic [63:0] ifu_axi_wdata,\n input logic [ 7:0] ifu_axi_wstrb,\n input logic ifu_axi_wlast,\n\n input logic ifu_axi_bvalid,\n input logic ifu_axi_bready,\n input logic [ 1:0] ifu_axi_bresp,\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,\n\n // AXI Read Channels\n input logic ifu_axi_arvalid,\n input logic ifu_axi_arready,\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,\n input logic [ 31:0] ifu_axi_araddr,\n input logic [ 3:0] ifu_axi_arregion,\n input logic [ 7:0] ifu_axi_arlen,\n input logic [ 2:0] ifu_axi_arsize,\n input logic [ 1:0] ifu_axi_arburst,\n input logic ifu_axi_arlock,\n input logic [ 3:0] ifu_axi_arcache,\n input logic [ 2:0] ifu_axi_arprot,\n input logic [ 3:0] ifu_axi_arqos,\n\n input logic ifu_axi_rvalid,\n input logic ifu_axi_rready,\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,\n input logic [ 63:0] ifu_axi_rdata,\n input logic [ 1:0] ifu_axi_rresp,\n input logic ifu_axi_rlast,\n\n //-------------------------- SB AXI signals--------------------------\n // AXI Write Channels\n input logic sb_axi_awvalid,\n input logic sb_axi_awready,\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,\n input logic [ 31:0] sb_axi_awaddr,\n input logic [ 3:0] sb_axi_awregion,\n input logic [ 7:0] sb_axi_awlen,\n input logic [ 2:0] sb_axi_awsize,\n input logic [ 1:0] sb_axi_awburst,\n input logic sb_axi_awlock,\n input logic [ 3:0] sb_axi_awcache,\n input logic [ 2:0] sb_axi_awprot,\n input logic [ 3:0] sb_axi_awqos,\n\n input logic sb_axi_wvalid,\n input logic sb_axi_wready,\n input logic [63:0] sb_axi_wdata,\n input logic [ 7:0] sb_axi_wstrb,\n input logic sb_axi_wlast,\n\n input logic sb_axi_bvalid,\n input logic sb_axi_bready,\n input logic [ 1:0] sb_axi_bresp,\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,\n\n // AXI Read Channels\n input logic sb_axi_arvalid,\n input logic sb_axi_arready,\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,\n input logic [ 31:0] sb_axi_araddr,\n input logic [ 3:0] sb_axi_arregion,\n input logic [ 7:0] sb_axi_arlen,\n input logic [ 2:0] sb_axi_arsize,\n input logic [ 1:0] sb_axi_arburst,\n input logic sb_axi_arlock,\n input logic [ 3:0] sb_axi_arcache,\n input logic [ 2:0] sb_axi_arprot,\n input logic [ 3:0] sb_axi_arqos,\n\n input logic sb_axi_rvalid,\n input logic sb_axi_rready,\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,\n input logic [ 63:0] sb_axi_rdata,\n input logic [ 1:0] sb_axi_rresp,\n input logic sb_axi_rlast,\n\n //-------------------------- DMA AXI signals--------------------------\n // AXI Write Channels\n input logic dma_axi_awvalid,\n input logic dma_axi_awready,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,\n input logic [ 31:0] dma_axi_awaddr,\n input logic [ 2:0] dma_axi_awsize,\n input logic [ 2:0] dma_axi_awprot,\n input logic [ 7:0] dma_axi_awlen,\n input logic [ 1:0] dma_axi_awburst,\n\n\n input logic dma_axi_wvalid,\n input logic dma_axi_wready,\n input logic [63:0] dma_axi_wdata,\n input logic [ 7:0] dma_axi_wstrb,\n input logic dma_axi_wlast,\n\n input logic dma_axi_bvalid,\n input logic dma_axi_bready,\n input logic [ 1:0] dma_axi_bresp,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,\n\n // AXI Read Channels\n input logic dma_axi_arvalid,\n input logic dma_axi_arready,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,\n input logic [ 31:0] dma_axi_araddr,\n input logic [ 2:0] dma_axi_arsize,\n input logic [ 2:0] dma_axi_arprot,\n input logic [ 7:0] dma_axi_arlen,\n input logic [ 1:0] dma_axi_arburst,\n\n input logic dma_axi_rvalid,\n input logic dma_axi_rready,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,\n input logic [ 63:0] dma_axi_rdata,\n input logic [ 1:0] dma_axi_rresp,\n input logic dma_axi_rlast,\n\n\n //// AHB LITE BUS\n input logic [31:0] haddr,\n input logic [ 2:0] hburst,\n input logic hmastlock,\n input logic [ 3:0] hprot,\n input logic [ 2:0] hsize,\n input logic [ 1:0] htrans,\n input logic hwrite,\n\n input logic [63:0] hrdata,\n input logic hready,\n input logic hresp,\n\n // LSU AHB Master\n input logic [31:0] lsu_haddr,\n input logic [ 2:0] lsu_hburst,\n input logic lsu_hmastlock,\n input logic [ 3:0] lsu_hprot,\n input logic [ 2:0] lsu_hsize,\n input logic [ 1:0] lsu_htrans,\n input logic lsu_hwrite,\n input logic [63:0] lsu_hwdata,\n\n input logic [63:0] lsu_hrdata,\n input logic lsu_hready,\n input logic lsu_hresp,\n\n //System Bus Debug Master\n input logic [31:0] sb_haddr,\n input logic [ 2:0] sb_hburst,\n input logic sb_hmastlock,\n input logic [ 3:0] sb_hprot,\n input logic [ 2:0] sb_hsize,\n input logic [ 1:0] sb_htrans,\n input logic sb_hwrite,\n input logic [63:0] sb_hwdata,\n\n input logic [63:0] sb_hrdata,\n input logic sb_hready,\n input logic sb_hresp,\n\n // DMA Slave\n input logic dma_hsel,\n input logic [31:0] dma_haddr,\n input logic [ 2:0] dma_hburst,\n input logic dma_hmastlock,\n input logic [ 3:0] dma_hprot,\n input logic [ 2:0] dma_hsize,\n input logic [ 1:0] dma_htrans,\n input logic dma_hwrite,\n input logic [63:0] dma_hwdata,\n input logic dma_hreadyin,\n\n input logic [63:0] dma_hrdata,\n input logic dma_hreadyout,\n input logic dma_hresp,\n\n input logic lsu_bus_clk_en,\n input logic ifu_bus_clk_en,\n input logic dbg_bus_clk_en,\n input logic dma_bus_clk_en,\n\n input logic dmi_reg_en, // read or write\n input logic [ 6:0] dmi_reg_addr, // address of DM register\n input logic dmi_reg_wr_en, // write instruction\n input logic [31:0] dmi_reg_wdata, // write data\n input logic [31:0] dmi_reg_rdata,\n\n // ICCM/DCCM ECC status\n input logic iccm_ecc_single_error,\n input logic iccm_ecc_double_error,\n input logic dccm_ecc_single_error,\n input logic dccm_ecc_double_error,\n\n input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,\n input logic timer_int,\n input logic soft_int,\n input logic scan_mode,\n\n // Shadow Core control\n input logic disable_corruption_detection_i,\n input logic lockstep_err_injection_en_i,\n\n // Equivalency Checker output\n output logic corruption_detected_o\n);\n\n localparam int unsigned LockstepDelay = pt.LOCKSTEP_DELAY; // Delay I/O; in clock cycles\n\n // Outputs\n typedef struct packed {\n logic core_rst_l;\n logic [31:0] trace_rv_i_insn_ip;\n logic [31:0] trace_rv_i_address_ip;\n logic trace_rv_i_valid_ip;\n logic trace_rv_i_exception_ip;\n logic [4:0] trace_rv_i_ecause_ip;\n logic trace_rv_i_interrupt_ip;\n logic [31:0] trace_rv_i_tval_ip;\n logic dccm_clk_override;\n logic icm_clk_override;\n logic dec_tlu_core_ecc_disable;\n logic o_cpu_halt_ack;\n logic o_cpu_halt_status;\n logic o_cpu_run_ack;\n logic o_debug_mode_status;\n logic mpc_debug_halt_ack;\n logic mpc_debug_run_ack;\n logic debug_brkpt_status;\n logic dec_tlu_perfcnt0;\n logic dec_tlu_perfcnt1;\n logic dec_tlu_perfcnt2;\n logic dec_tlu_perfcnt3;\n logic dccm_wren;\n logic dccm_rden;\n logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo;\n logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi;\n logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo;\n logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi;\n logic [pt.ICCM_BITS-1:1] iccm_rw_addr;\n logic iccm_wren;\n logic iccm_rden;\n logic [2:0] iccm_wr_size;\n logic [77:0] iccm_wr_data;\n logic iccm_buf_correct_ecc;\n logic iccm_correction_state;\n logic [31:1] ic_rw_addr;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en;\n logic ic_rd_en;\n logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;\n logic [70:0] ic_debug_wr_data;\n logic [63:0] ic_premux_data;\n logic ic_sel_premux_data;\n logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr;\n logic ic_debug_rd_en;\n logic ic_debug_wr_en;\n logic ic_debug_tag_array;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way;\n logic lsu_axi_awvalid;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;\n logic [31:0] lsu_axi_awaddr;\n logic [3:0] lsu_axi_awregion;\n logic [7:0] lsu_axi_awlen;\n logic [2:0] lsu_axi_awsize;\n logic [1:0] lsu_axi_awburst;\n logic lsu_axi_awlock;\n logic [3:0] lsu_axi_awcache;\n logic [2:0] lsu_axi_awprot;\n logic [3:0] lsu_axi_awqos;\n logic lsu_axi_wvalid;\n logic [63:0] lsu_axi_wdata;\n logic [7:0] lsu_axi_wstrb;\n logic lsu_axi_wlast;\n logic lsu_axi_bready;\n logic lsu_axi_arvalid;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;\n logic [31:0] lsu_axi_araddr;\n logic [3:0] lsu_axi_arregion;\n logic [7:0] lsu_axi_arlen;\n logic [2:0] lsu_axi_arsize;\n logic [1:0] lsu_axi_arburst;\n logic lsu_axi_arlock;\n logic [3:0] lsu_axi_arcache;\n logic [2:0] lsu_axi_arprot;\n logic [3:0] lsu_axi_arqos;\n logic lsu_axi_rready;\n logic ifu_axi_awvalid;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;\n logic [31:0] ifu_axi_awaddr;\n logic [3:0] ifu_axi_awregion;\n logic [7:0] ifu_axi_awlen;\n logic [2:0] ifu_axi_awsize;\n logic [1:0] ifu_axi_awburst;\n logic ifu_axi_awlock;\n logic [3:0] ifu_axi_awcache;\n logic [2:0] ifu_axi_awprot;\n logic [3:0] ifu_axi_awqos;\n logic ifu_axi_wvalid;\n logic [63:0] ifu_axi_wdata;\n logic [7:0] ifu_axi_wstrb;\n logic ifu_axi_wlast;\n logic ifu_axi_bready;\n logic ifu_axi_arvalid;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid;\n logic [31:0] ifu_axi_araddr;\n logic [3:0] ifu_axi_arregion;\n logic [7:0] ifu_axi_arlen;\n logic [2:0] ifu_axi_arsize;\n logic [1:0] ifu_axi_arburst;\n logic ifu_axi_arlock;\n logic [3:0] ifu_axi_arcache;\n logic [2:0] ifu_axi_arprot;\n logic [3:0] ifu_axi_arqos;\n logic ifu_axi_rready;\n logic sb_axi_awvalid;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_awid;\n logic [31:0] sb_axi_awaddr;\n logic [3:0] sb_axi_awregion;\n logic [7:0] sb_axi_awlen;\n logic [2:0] sb_axi_awsize;\n logic [1:0] sb_axi_awburst;\n logic sb_axi_awlock;\n logic [3:0] sb_axi_awcache;\n logic [2:0] sb_axi_awprot;\n logic [3:0] sb_axi_awqos;\n logic sb_axi_wvalid;\n logic [63:0] sb_axi_wdata;\n logic [7:0] sb_axi_wstrb;\n logic sb_axi_wlast;\n logic sb_axi_bready;\n logic sb_axi_arvalid;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_arid;\n logic [31:0] sb_axi_araddr;\n logic [3:0] sb_axi_arregion;\n logic [7:0] sb_axi_arlen;\n logic [2:0] sb_axi_arsize;\n logic [1:0] sb_axi_arburst;\n logic sb_axi_arlock;\n logic [3:0] sb_axi_arcache;\n logic [2:0] sb_axi_arprot;\n logic [3:0] sb_axi_arqos;\n logic sb_axi_rready;\n logic dma_axi_awready;\n logic dma_axi_wready;\n logic dma_axi_bvalid;\n logic [1:0] dma_axi_bresp;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid;\n logic dma_axi_arready;\n logic dma_axi_rvalid;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid;\n logic [63:0] dma_axi_rdata;\n logic [1:0] dma_axi_rresp;\n logic dma_axi_rlast;\n logic [31:0] haddr;\n logic [2:0] hburst;\n logic hmastlock;\n logic [3:0] hprot;\n logic [2:0] hsize;\n logic [1:0] htrans;\n logic hwrite;\n logic [31:0] lsu_haddr;\n logic [2:0] lsu_hburst;\n logic lsu_hmastlock;\n logic [3:0] lsu_hprot;\n logic [2:0] lsu_hsize;\n logic [1:0] lsu_htrans;\n logic lsu_hwrite;\n logic [63:0] lsu_hwdata;\n logic [31:0] sb_haddr;\n logic [2:0] sb_hburst;\n logic sb_hmastlock;\n logic [3:0] sb_hprot;\n logic [2:0] sb_hsize;\n logic [1:0] sb_htrans;\n logic sb_hwrite;\n logic [63:0] sb_hwdata;\n logic [63:0] dma_hrdata;\n logic dma_hreadyout;\n logic dma_hresp;\n logic [31:0] dmi_reg_rdata;\n logic iccm_ecc_single_error;\n logic iccm_ecc_double_error;\n logic dccm_ecc_single_error;\n logic dccm_ecc_double_error;\n } veer_outputs_t;\n\n // Inputs\n typedef struct packed {\n logic [31:1] rst_vec;\n logic nmi_int;\n logic [31:1] nmi_vec;\n logic i_cpu_halt_req;\n logic i_cpu_run_req;\n logic [31:4] core_id;\n logic mpc_debug_halt_req;\n logic mpc_debug_run_req;\n logic mpc_reset_run_req;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;\n logic [63:0] iccm_rd_data;\n logic [77:0] iccm_rd_data_ecc;\n logic [63:0] ic_rd_data;\n logic [70:0] ic_debug_rd_data;\n logic [25:0] ictag_debug_rd_data;\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit;\n logic ic_tag_perr;\n logic lsu_axi_awready;\n logic lsu_axi_wready;\n logic lsu_axi_bvalid;\n logic [1:0] lsu_axi_bresp;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;\n logic lsu_axi_arready;\n logic lsu_axi_rvalid;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;\n logic [63:0] lsu_axi_rdata;\n logic [1:0] lsu_axi_rresp;\n logic lsu_axi_rlast;\n logic ifu_axi_awready;\n logic ifu_axi_wready;\n logic ifu_axi_bvalid;\n logic [1:0] ifu_axi_bresp;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid;\n logic ifu_axi_arready;\n logic ifu_axi_rvalid;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid;\n logic [63:0] ifu_axi_rdata;\n logic [1:0] ifu_axi_rresp;\n logic ifu_axi_rlast;\n logic sb_axi_awready;\n logic sb_axi_wready;\n logic sb_axi_bvalid;\n logic [1:0] sb_axi_bresp;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_bid;\n logic sb_axi_arready;\n logic sb_axi_rvalid;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_rid;\n logic [63:0] sb_axi_rdata;\n logic [1:0] sb_axi_rresp;\n logic sb_axi_rlast;\n logic dma_axi_awvalid;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid;\n logic [31:0] dma_axi_awaddr;\n logic [2:0] dma_axi_awsize;\n logic [2:0] dma_axi_awprot;\n logic [7:0] dma_axi_awlen;\n logic [1:0] dma_axi_awburst;\n logic dma_axi_wvalid;\n logic [63:0] dma_axi_wdata;\n logic [7:0] dma_axi_wstrb;\n logic dma_axi_wlast;\n logic dma_axi_bready;\n logic dma_axi_arvalid;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid;\n logic [31:0] dma_axi_araddr;\n logic [2:0] dma_axi_arsize;\n logic [2:0] dma_axi_arprot;\n logic [7:0] dma_axi_arlen;\n logic [1:0] dma_axi_arburst;\n logic dma_axi_rready;\n logic [63:0] hrdata;\n logic hready;\n logic hresp;\n logic [63:0] lsu_hrdata;\n logic lsu_hready;\n logic lsu_hresp;\n logic [63:0] sb_hrdata;\n logic sb_hready;\n logic sb_hresp;\n logic dma_hsel;\n logic [31:0] dma_haddr;\n logic [2:0] dma_hburst;\n logic dma_hmastlock;\n logic [3:0] dma_hprot;\n logic [2:0] dma_hsize;\n logic [1:0] dma_htrans;\n logic dma_hwrite;\n logic [63:0] dma_hwdata;\n logic dma_hreadyin;\n logic lsu_bus_clk_en;\n logic ifu_bus_clk_en;\n logic dbg_bus_clk_en;\n logic dma_bus_clk_en;\n logic dmi_reg_en;\n logic [6:0] dmi_reg_addr;\n logic dmi_reg_wr_en;\n logic [31:0] dmi_reg_wdata;\n logic [pt.PIC_TOTAL_INT:1] extintsrc_req;\n logic timer_int;\n logic soft_int;\n logic scan_mode;\n } veer_inputs_t;\n\n veer_inputs_t main_core_inputs;\n veer_inputs_t [LockstepDelay:0] delay_input_d;\n veer_inputs_t shadow_core_inputs;\n\n veer_outputs_t main_core_outputs;\n veer_outputs_t [LockstepDelay:0] delay_output_d;\n veer_outputs_t delayed_main_core_outputs;\n veer_outputs_t shadow_core_outputs;\n\n assign shadow_core_inputs = delay_input_d[LockstepDelay];\n assign delayed_main_core_outputs = delay_output_d[LockstepDelay];\n\n // Capture input\n assign main_core_inputs.rst_vec = rst_vec;\n assign main_core_inputs.nmi_int = nmi_int;\n assign main_core_inputs.nmi_vec = nmi_vec;\n assign main_core_inputs.i_cpu_halt_req = i_cpu_halt_req;\n assign main_core_inputs.i_cpu_run_req = i_cpu_run_req;\n assign main_core_inputs.core_id = core_id;\n assign main_core_inputs.mpc_debug_halt_req = mpc_debug_halt_req;\n assign main_core_inputs.mpc_debug_run_req = mpc_debug_run_req;\n assign main_core_inputs.mpc_reset_run_req = mpc_reset_run_req;\n assign main_core_inputs.dccm_rd_data_lo = dccm_rd_data_lo;\n assign main_core_inputs.dccm_rd_data_hi = dccm_rd_data_hi;\n assign main_core_inputs.iccm_rd_data = iccm_rd_data;\n assign main_core_inputs.iccm_rd_data_ecc = iccm_rd_data_ecc;\n assign main_core_inputs.ic_rd_data = ic_rd_data;\n assign main_core_inputs.ic_debug_rd_data = ic_debug_rd_data;\n assign main_core_inputs.ictag_debug_rd_data = ictag_debug_rd_data;\n assign main_core_inputs.ic_eccerr = ic_eccerr;\n assign main_core_inputs.ic_parerr = ic_parerr;\n assign main_core_inputs.ic_rd_hit = ic_rd_hit;\n assign main_core_inputs.ic_tag_perr = ic_tag_perr;\n assign main_core_inputs.lsu_axi_awready = lsu_axi_awready;\n assign main_core_inputs.lsu_axi_wready = lsu_axi_wready;\n assign main_core_inputs.lsu_axi_bvalid = lsu_axi_bvalid;\n assign main_core_inputs.lsu_axi_bresp = lsu_axi_bresp;\n assign main_core_inputs.lsu_axi_bid = lsu_axi_bid;\n assign main_core_inputs.lsu_axi_arready = lsu_axi_arready;\n assign main_core_inputs.lsu_axi_rvalid = lsu_axi_rvalid;\n assign main_core_inputs.lsu_axi_rid = lsu_axi_rid;\n assign main_core_inputs.lsu_axi_rdata = lsu_axi_rdata;\n assign main_core_inputs.lsu_axi_rresp = lsu_axi_rresp;\n assign main_core_inputs.lsu_axi_rlast = lsu_axi_rlast;\n assign main_core_inputs.ifu_axi_awready = ifu_axi_awready;\n assign main_core_inputs.ifu_axi_wready = ifu_axi_wready;\n assign main_core_inputs.ifu_axi_bvalid = ifu_axi_bvalid;\n assign main_core_inputs.ifu_axi_bresp = ifu_axi_bresp;\n assign main_core_inputs.ifu_axi_bid = ifu_axi_bid;\n assign main_core_inputs.ifu_axi_arready = ifu_axi_arready;\n assign main_core_inputs.ifu_axi_rvalid = ifu_axi_rvalid;\n assign main_core_inputs.ifu_axi_rid = ifu_axi_rid;\n assign main_core_inputs.ifu_axi_rdata = ifu_axi_rdata;\n assign main_core_inputs.ifu_axi_rresp = ifu_axi_rresp;\n assign main_core_inputs.ifu_axi_rlast = ifu_axi_rlast;\n assign main_core_inputs.sb_axi_awready = sb_axi_awready;\n assign main_core_inputs.sb_axi_wready = sb_axi_wready;\n assign main_core_inputs.sb_axi_bvalid = sb_axi_bvalid;\n assign main_core_inputs.sb_axi_bresp = sb_axi_bresp;\n assign main_core_inputs.sb_axi_bid = sb_axi_bid;\n assign main_core_inputs.sb_axi_arready = sb_axi_arready;\n assign main_core_inputs.sb_axi_rvalid = sb_axi_rvalid;\n assign main_core_inputs.sb_axi_rid = sb_axi_rid;\n assign main_core_inputs.sb_axi_rdata = sb_axi_rdata;\n assign main_core_inputs.sb_axi_rresp = sb_axi_rresp;\n assign main_core_inputs.sb_axi_rlast = sb_axi_rlast;\n assign main_core_inputs.dma_axi_awvalid = dma_axi_awvalid;\n assign main_core_inputs.dma_axi_awid = dma_axi_awid;\n assign main_core_inputs.dma_axi_awaddr = dma_axi_awaddr;\n assign main_core_inputs.dma_axi_awsize = dma_axi_awsize;\n assign main_core_inputs.dma_axi_awprot = dma_axi_awprot;\n assign main_core_inputs.dma_axi_awlen = dma_axi_awlen;\n assign main_core_inputs.dma_axi_awburst = dma_axi_awburst;\n assign main_core_inputs.dma_axi_wvalid = dma_axi_wvalid;\n assign main_core_inputs.dma_axi_wdata = dma_axi_wdata;\n assign main_core_inputs.dma_axi_wstrb = dma_axi_wstrb;\n assign main_core_inputs.dma_axi_wlast = dma_axi_wlast;\n assign main_core_inputs.dma_axi_bready = dma_axi_bready;\n assign main_core_inputs.dma_axi_arvalid = dma_axi_arvalid;\n assign main_core_inputs.dma_axi_arid = dma_axi_arid;\n assign main_core_inputs.dma_axi_araddr = dma_axi_araddr;\n assign main_core_inputs.dma_axi_arsize = dma_axi_arsize;\n assign main_core_inputs.dma_axi_arprot = dma_axi_arprot;\n assign main_core_inputs.dma_axi_arlen = dma_axi_arlen;\n assign main_core_inputs.dma_axi_arburst = dma_axi_arburst;\n assign main_core_inputs.dma_axi_rready = dma_axi_rready;\n assign main_core_inputs.hrdata = hrdata;\n assign main_core_inputs.hready = hready;\n assign main_core_inputs.hresp = hresp;\n assign main_core_inputs.lsu_hrdata = lsu_hrdata;\n assign main_core_inputs.lsu_hready = lsu_hready;\n assign main_core_inputs.lsu_hresp = lsu_hresp;\n assign main_core_inputs.sb_hrdata = sb_hrdata;\n assign main_core_inputs.sb_hready = sb_hready;\n assign main_core_inputs.sb_hresp = sb_hresp;\n assign main_core_inputs.dma_hsel = dma_hsel;\n assign main_core_inputs.dma_haddr = dma_haddr;\n assign main_core_inputs.dma_hburst = dma_hburst;\n assign main_core_inputs.dma_hmastlock = dma_hmastlock;\n assign main_core_inputs.dma_hprot = dma_hprot;\n assign main_core_inputs.dma_hsize = dma_hsize;\n assign main_core_inputs.dma_htrans = dma_htrans;\n assign main_core_inputs.dma_hwrite = dma_hwrite;\n assign main_core_inputs.dma_hwdata = dma_hwdata;\n assign main_core_inputs.dma_hreadyin = dma_hreadyin;\n assign main_core_inputs.lsu_bus_clk_en = lsu_bus_clk_en;\n assign main_core_inputs.ifu_bus_clk_en = ifu_bus_clk_en;\n assign main_core_inputs.dbg_bus_clk_en = dbg_bus_clk_en;\n assign main_core_inputs.dma_bus_clk_en = dma_bus_clk_en;\n assign main_core_inputs.dmi_reg_en = dmi_reg_en;\n assign main_core_inputs.dmi_reg_addr = dmi_reg_addr;\n assign main_core_inputs.dmi_reg_wr_en = dmi_reg_wr_en;\n assign main_core_inputs.dmi_reg_wdata = dmi_reg_wdata;\n assign main_core_inputs.extintsrc_req = extintsrc_req;\n assign main_core_inputs.timer_int = timer_int;\n assign main_core_inputs.soft_int = soft_int;\n assign main_core_inputs.scan_mode = scan_mode;\n\n // Capture output\n assign main_core_outputs.core_rst_l = core_rst_l;\n assign main_core_outputs.trace_rv_i_insn_ip = trace_rv_i_insn_ip;\n assign main_core_outputs.trace_rv_i_address_ip = trace_rv_i_address_ip;\n assign main_core_outputs.trace_rv_i_valid_ip = trace_rv_i_valid_ip;\n assign main_core_outputs.trace_rv_i_exception_ip = trace_rv_i_exception_ip;\n assign main_core_outputs.trace_rv_i_ecause_ip = trace_rv_i_ecause_ip;\n assign main_core_outputs.trace_rv_i_interrupt_ip = trace_rv_i_interrupt_ip;\n assign main_core_outputs.trace_rv_i_tval_ip = trace_rv_i_tval_ip;\n assign main_core_outputs.dccm_clk_override = dccm_clk_override;\n assign main_core_outputs.icm_clk_override = icm_clk_override;\n assign main_core_outputs.dec_tlu_core_ecc_disable = dec_tlu_core_ecc_disable;\n assign main_core_outputs.o_cpu_halt_ack = o_cpu_halt_ack;\n assign main_core_outputs.o_cpu_halt_status = o_cpu_halt_status;\n assign main_core_outputs.o_cpu_run_ack = o_cpu_run_ack;\n assign main_core_outputs.o_debug_mode_status = o_debug_mode_status;\n assign main_core_outputs.mpc_debug_halt_ack = mpc_debug_halt_ack;\n assign main_core_outputs.mpc_debug_run_ack = mpc_debug_run_ack;\n assign main_core_outputs.debug_brkpt_status = debug_brkpt_status;\n assign main_core_outputs.dec_tlu_perfcnt0 = dec_tlu_perfcnt0;\n assign main_core_outputs.dec_tlu_perfcnt1 = dec_tlu_perfcnt1;\n assign main_core_outputs.dec_tlu_perfcnt2 = dec_tlu_perfcnt2;\n assign main_core_outputs.dec_tlu_perfcnt3 = dec_tlu_perfcnt3;\n assign main_core_outputs.dccm_wren = dccm_wren;\n assign main_core_outputs.dccm_rden = dccm_rden;\n assign main_core_outputs.dccm_wr_addr_lo = dccm_wr_addr_lo;\n assign main_core_outputs.dccm_wr_addr_hi = dccm_wr_addr_hi;\n assign main_core_outputs.dccm_rd_addr_lo = dccm_rd_addr_lo;\n assign main_core_outputs.dccm_rd_addr_hi = dccm_rd_addr_hi;\n assign main_core_outputs.dccm_wr_data_lo = dccm_wr_data_lo;\n assign main_core_outputs.dccm_wr_data_hi = dccm_wr_data_hi;\n assign main_core_outputs.iccm_rw_addr = iccm_rw_addr;\n assign main_core_outputs.iccm_wren = iccm_wren;\n assign main_core_outputs.iccm_rden = iccm_rden;\n assign main_core_outputs.iccm_wr_size = iccm_wr_size;\n assign main_core_outputs.iccm_wr_data = iccm_wr_data;\n assign main_core_outputs.iccm_buf_correct_ecc = iccm_buf_correct_ecc;\n assign main_core_outputs.iccm_correction_state = iccm_correction_state;\n assign main_core_outputs.ic_rw_addr = ic_rw_addr;\n assign main_core_outputs.ic_tag_valid = ic_tag_valid;\n assign main_core_outputs.ic_wr_en = ic_wr_en;\n assign main_core_outputs.ic_rd_en = ic_rd_en;\n assign main_core_outputs.ic_wr_data = ic_wr_data;\n assign main_core_outputs.ic_debug_wr_data = ic_debug_wr_data;\n assign main_core_outputs.ic_premux_data = ic_premux_data;\n assign main_core_outputs.ic_sel_premux_data = ic_sel_premux_data;\n assign main_core_outputs.ic_debug_addr = ic_debug_addr;\n assign main_core_outputs.ic_debug_rd_en = ic_debug_rd_en;\n assign main_core_outputs.ic_debug_wr_en = ic_debug_wr_en;\n assign main_core_outputs.ic_debug_tag_array = ic_debug_tag_array;\n assign main_core_outputs.ic_debug_way = ic_debug_way;\n assign main_core_outputs.lsu_axi_awvalid = lsu_axi_awvalid;\n assign main_core_outputs.lsu_axi_awid = lsu_axi_awid;\n assign main_core_outputs.lsu_axi_awaddr = lsu_axi_awaddr;\n assign main_core_outputs.lsu_axi_awregion = lsu_axi_awregion;\n assign main_core_outputs.lsu_axi_awlen = lsu_axi_awlen;\n assign main_core_outputs.lsu_axi_awsize = lsu_axi_awsize;\n assign main_core_outputs.lsu_axi_awburst = lsu_axi_awburst;\n assign main_core_outputs.lsu_axi_awlock = lsu_axi_awlock;\n assign main_core_outputs.lsu_axi_awcache = lsu_axi_awcache;\n assign main_core_outputs.lsu_axi_awprot = lsu_axi_awprot;\n assign main_core_outputs.lsu_axi_awqos = lsu_axi_awqos;\n assign main_core_outputs.lsu_axi_wvalid = lsu_axi_wvalid;\n assign main_core_outputs.lsu_axi_wdata = lsu_axi_wdata;\n assign main_core_outputs.lsu_axi_wstrb = lsu_axi_wstrb;\n assign main_core_outputs.lsu_axi_wlast = lsu_axi_wlast;\n assign main_core_outputs.lsu_axi_bready = lsu_axi_bready;\n assign main_core_outputs.lsu_axi_arvalid = lsu_axi_arvalid;\n assign main_core_outputs.lsu_axi_arid = lsu_axi_arid;\n assign main_core_outputs.lsu_axi_araddr = lsu_axi_araddr;\n assign main_core_outputs.lsu_axi_arregion = lsu_axi_arregion;\n assign main_core_outputs.lsu_axi_arlen = lsu_axi_arlen;\n assign main_core_outputs.lsu_axi_arsize = lsu_axi_arsize;\n assign main_core_outputs.lsu_axi_arburst = lsu_axi_arburst;\n assign main_core_outputs.lsu_axi_arlock = lsu_axi_arlock;\n assign main_core_outputs.lsu_axi_arcache = lsu_axi_arcache;\n assign main_core_outputs.lsu_axi_arprot = lsu_axi_arprot;\n assign main_core_outputs.lsu_axi_arqos = lsu_axi_arqos;\n assign main_core_outputs.lsu_axi_rready = lsu_axi_rready;\n assign main_core_outputs.ifu_axi_awvalid = ifu_axi_awvalid;\n assign main_core_outputs.ifu_axi_awid = ifu_axi_awid;\n assign main_core_outputs.ifu_axi_awaddr = ifu_axi_awaddr;\n assign main_core_outputs.ifu_axi_awregion = ifu_axi_awregion;\n assign main_core_outputs.ifu_axi_awlen = ifu_axi_awlen;\n assign main_core_outputs.ifu_axi_awsize = ifu_axi_awsize;\n assign main_core_outputs.ifu_axi_awburst = ifu_axi_awburst;\n assign main_core_outputs.ifu_axi_awlock = ifu_axi_awlock;\n assign main_core_outputs.ifu_axi_awcache = ifu_axi_awcache;\n assign main_core_outputs.ifu_axi_awprot = ifu_axi_awprot;\n assign main_core_outputs.ifu_axi_awqos = ifu_axi_awqos;\n assign main_core_outputs.ifu_axi_wvalid = ifu_axi_wvalid;\n assign main_core_outputs.ifu_axi_wdata = ifu_axi_wdata;\n assign main_core_outputs.ifu_axi_wstrb = ifu_axi_wstrb;\n assign main_core_outputs.ifu_axi_wlast = ifu_axi_wlast;\n assign main_core_outputs.ifu_axi_bready = ifu_axi_bready;\n assign main_core_outputs.ifu_axi_arvalid = ifu_axi_arvalid;\n assign main_core_outputs.ifu_axi_arid = ifu_axi_arid;\n assign main_core_outputs.ifu_axi_araddr = ifu_axi_araddr;\n assign main_core_outputs.ifu_axi_arregion = ifu_axi_arregion;\n assign main_core_outputs.ifu_axi_arlen = ifu_axi_arlen;\n assign main_core_outputs.ifu_axi_arsize = ifu_axi_arsize;\n assign main_core_outputs.ifu_axi_arburst = ifu_axi_arburst;\n assign main_core_outputs.ifu_axi_arlock = ifu_axi_arlock;\n assign main_core_outputs.ifu_axi_arcache = ifu_axi_arcache;\n assign main_core_outputs.ifu_axi_arprot = ifu_axi_arprot;\n assign main_core_outputs.ifu_axi_arqos = ifu_axi_arqos;\n assign main_core_outputs.ifu_axi_rready = ifu_axi_rready;\n assign main_core_outputs.sb_axi_awvalid = sb_axi_awvalid;\n assign main_core_outputs.sb_axi_awid = sb_axi_awid;\n assign main_core_outputs.sb_axi_awaddr = sb_axi_awaddr;\n assign main_core_outputs.sb_axi_awregion = sb_axi_awregion;\n assign main_core_outputs.sb_axi_awlen = sb_axi_awlen;\n assign main_core_outputs.sb_axi_awsize = sb_axi_awsize;\n assign main_core_outputs.sb_axi_awburst = sb_axi_awburst;\n assign main_core_outputs.sb_axi_awlock = sb_axi_awlock;\n assign main_core_outputs.sb_axi_awcache = sb_axi_awcache;\n assign main_core_outputs.sb_axi_awprot = sb_axi_awprot;\n assign main_core_outputs.sb_axi_awqos = sb_axi_awqos;\n assign main_core_outputs.sb_axi_wvalid = sb_axi_wvalid;\n assign main_core_outputs.sb_axi_wdata = sb_axi_wdata;\n assign main_core_outputs.sb_axi_wstrb = sb_axi_wstrb;\n assign main_core_outputs.sb_axi_wlast = sb_axi_wlast;\n assign main_core_outputs.sb_axi_bready = sb_axi_bready;\n assign main_core_outputs.sb_axi_arvalid = sb_axi_arvalid;\n assign main_core_outputs.sb_axi_arid = sb_axi_arid;\n assign main_core_outputs.sb_axi_araddr = sb_axi_araddr;\n assign main_core_outputs.sb_axi_arregion = sb_axi_arregion;\n assign main_core_outputs.sb_axi_arlen = sb_axi_arlen;\n assign main_core_outputs.sb_axi_arsize = sb_axi_arsize;\n assign main_core_outputs.sb_axi_arburst = sb_axi_arburst;\n assign main_core_outputs.sb_axi_arlock = sb_axi_arlock;\n assign main_core_outputs.sb_axi_arcache = sb_axi_arcache;\n assign main_core_outputs.sb_axi_arprot = sb_axi_arprot;\n assign main_core_outputs.sb_axi_arqos = sb_axi_arqos;\n assign main_core_outputs.sb_axi_rready = sb_axi_rready;\n assign main_core_outputs.dma_axi_awready = dma_axi_awready;\n assign main_core_outputs.dma_axi_wready = dma_axi_wready;\n assign main_core_outputs.dma_axi_bvalid = dma_axi_bvalid;\n assign main_core_outputs.dma_axi_bresp = dma_axi_bresp;\n assign main_core_outputs.dma_axi_bid = dma_axi_bid;\n assign main_core_outputs.dma_axi_arready = dma_axi_arready;\n assign main_core_outputs.dma_axi_rvalid = dma_axi_rvalid;\n assign main_core_outputs.dma_axi_rid = dma_axi_rid;\n assign main_core_outputs.dma_axi_rdata = dma_axi_rdata;\n assign main_core_outputs.dma_axi_rresp = dma_axi_rresp;\n assign main_core_outputs.dma_axi_rlast = dma_axi_rlast;\n assign main_core_outputs.haddr = haddr;\n assign main_core_outputs.hburst = hburst;\n assign main_core_outputs.hmastlock = hmastlock;\n assign main_core_outputs.hprot = hprot;\n assign main_core_outputs.hsize = hsize;\n assign main_core_outputs.htrans = htrans;\n assign main_core_outputs.hwrite = hwrite;\n assign main_core_outputs.lsu_haddr = lsu_haddr;\n assign main_core_outputs.lsu_hburst = lsu_hburst;\n assign main_core_outputs.lsu_hmastlock = lsu_hmastlock;\n assign main_core_outputs.lsu_hprot = lsu_hprot;\n assign main_core_outputs.lsu_hsize = lsu_hsize;\n assign main_core_outputs.lsu_htrans = lsu_htrans;\n assign main_core_outputs.lsu_hwrite = lsu_hwrite;\n assign main_core_outputs.lsu_hwdata = lsu_hwdata;\n assign main_core_outputs.sb_haddr = sb_haddr;\n assign main_core_outputs.sb_hburst = sb_hburst;\n assign main_core_outputs.sb_hmastlock = sb_hmastlock;\n assign main_core_outputs.sb_hprot = sb_hprot;\n assign main_core_outputs.sb_hsize = sb_hsize;\n assign main_core_outputs.sb_htrans = sb_htrans;\n assign main_core_outputs.sb_hwrite = sb_hwrite;\n assign main_core_outputs.sb_hwdata = sb_hwdata;\n assign main_core_outputs.dma_hrdata = dma_hrdata;\n assign main_core_outputs.dma_hreadyout = dma_hreadyout;\n assign main_core_outputs.dma_hresp = dma_hresp;\n assign main_core_outputs.dmi_reg_rdata = dmi_reg_rdata;\n assign main_core_outputs.iccm_ecc_single_error = iccm_ecc_single_error;\n assign main_core_outputs.iccm_ecc_double_error = iccm_ecc_double_error;\n assign main_core_outputs.dccm_ecc_single_error = dccm_ecc_single_error;\n assign main_core_outputs.dccm_ecc_double_error = dccm_ecc_double_error;\n\n // Shadow core enters reset immediately with main core but gets out of reset\n // after the delay\n logic [LockstepDelay:0] rst_shadow_sr, rst_dbg_shadow_sr;\n logic rst_shadow, rst_dbg_shadow;\n assign rst_shadow = &rst_shadow_sr;\n assign rst_dbg_shadow = &rst_dbg_shadow_sr;\n\n always_ff @(posedge clk or negedge rst_l) begin\n if (!rst_l) begin\n rst_shadow_sr <= '0;\n end else begin\n rst_shadow_sr <= (rst_shadow_sr << 1) + 1;\n end\n end\n\n always_ff @(posedge clk or negedge dbg_rst_l) begin\n if (!dbg_rst_l) begin\n rst_dbg_shadow_sr <= '0;\n end else begin\n rst_dbg_shadow_sr <= (rst_dbg_shadow_sr << 1) + 1;\n end\n end\n\n // Delay the inputs and outputs\n always_ff @(posedge clk or negedge rst_l) begin\n if (~rst_l) begin\n delay_input_d[0] <= veer_inputs_t'(0);\n delay_output_d[0] <= veer_outputs_t'(0);\n end else begin\n delay_input_d[0] <= main_core_inputs;\n delay_output_d[0] <= main_core_outputs;\n end\n end\n for (genvar i = 0; i < LockstepDelay; i++) begin\n always_ff @(posedge clk or negedge rst_l) begin\n if (!rst_l) begin\n delay_input_d[i+1] <= veer_inputs_t'(0);\n delay_output_d[i+1] <= veer_outputs_t'(0);\n end else begin\n delay_input_d[i+1] <= delay_input_d[i];\n delay_output_d[i+1] <= delay_output_d[i];\n end\n end\n end\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n el2_regfile_if shadow_core_regfile ();\n\n el2_regfile_if delayed_main_core_regfile[LockstepDelay:0] ();\n\n always_ff @(posedge clk or negedge rst_l) begin\n if (!rst_l) begin\n delayed_main_core_regfile[0].gpr <= '0;\n delayed_main_core_regfile[0].tlu <= '0;\n end else begin\n delayed_main_core_regfile[0].gpr <= main_core_regfile.gpr;\n delayed_main_core_regfile[0].tlu <= main_core_regfile.tlu;\n end\n end\n for (genvar i = 0; i < LockstepDelay; i++) begin\n always_ff @(posedge clk or negedge rst_l) begin\n if (!rst_l) begin\n delayed_main_core_regfile[i+1].gpr <= '0;\n delayed_main_core_regfile[i+1].tlu <= '0;\n end else begin\n delayed_main_core_regfile[i+1].gpr <= delayed_main_core_regfile[i].gpr;\n delayed_main_core_regfile[i+1].tlu <= delayed_main_core_regfile[i].tlu;\n end\n end\n end\n`endif\n\n // Instantiate the el2_veer core\n el2_veer #(\n .pt(pt)\n ) xshadow_core (\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .regfile(shadow_core_regfile.veer_rf_src),\n`endif\n .clk(clk),\n .rst_l(rst_shadow),\n .dbg_rst_l(rst_dbg_shadow),\n .rst_vec(shadow_core_inputs.rst_vec),\n .nmi_int(shadow_core_inputs.nmi_int),\n .nmi_vec(shadow_core_inputs.nmi_vec),\n .core_rst_l(shadow_core_outputs.core_rst_l),\n\n // we use those clocks from main core\n .active_l2clk(),\n .free_l2clk (),\n\n .trace_rv_i_insn_ip(shadow_core_outputs.trace_rv_i_insn_ip),\n .trace_rv_i_address_ip(shadow_core_outputs.trace_rv_i_address_ip),\n .trace_rv_i_valid_ip(shadow_core_outputs.trace_rv_i_valid_ip),\n .trace_rv_i_exception_ip(shadow_core_outputs.trace_rv_i_exception_ip),\n .trace_rv_i_ecause_ip(shadow_core_outputs.trace_rv_i_ecause_ip),\n .trace_rv_i_interrupt_ip(shadow_core_outputs.trace_rv_i_interrupt_ip),\n .trace_rv_i_tval_ip(shadow_core_outputs.trace_rv_i_tval_ip),\n\n .dccm_clk_override(shadow_core_outputs.dccm_clk_override),\n .icm_clk_override(shadow_core_outputs.icm_clk_override),\n .dec_tlu_core_ecc_disable(shadow_core_outputs.dec_tlu_core_ecc_disable),\n\n .i_cpu_halt_req(shadow_core_inputs.i_cpu_halt_req),\n .i_cpu_run_req(shadow_core_inputs.i_cpu_run_req),\n .o_cpu_halt_ack(shadow_core_outputs.o_cpu_halt_ack),\n .o_cpu_halt_status(shadow_core_outputs.o_cpu_halt_status),\n .o_cpu_run_ack(shadow_core_outputs.o_cpu_run_ack),\n .o_debug_mode_status(shadow_core_outputs.o_debug_mode_status),\n\n .core_id(core_id),\n\n .mpc_debug_halt_req(shadow_core_inputs.mpc_debug_halt_req),\n .mpc_debug_run_req (shadow_core_inputs.mpc_debug_run_req),\n .mpc_reset_run_req (shadow_core_inputs.mpc_reset_run_req),\n .mpc_debug_halt_ack(shadow_core_outputs.mpc_debug_halt_ack),\n .mpc_debug_run_ack (shadow_core_outputs.mpc_debug_run_ack),\n .debug_brkpt_status(shadow_core_outputs.debug_brkpt_status),\n\n .dec_tlu_perfcnt0(shadow_core_outputs.dec_tlu_perfcnt0),\n .dec_tlu_perfcnt1(shadow_core_outputs.dec_tlu_perfcnt1),\n .dec_tlu_perfcnt2(shadow_core_outputs.dec_tlu_perfcnt2),\n .dec_tlu_perfcnt3(shadow_core_outputs.dec_tlu_perfcnt3),\n\n .dccm_wren(shadow_core_outputs.dccm_wren),\n .dccm_rden(shadow_core_outputs.dccm_rden),\n .dccm_wr_addr_lo(shadow_core_outputs.dccm_wr_addr_lo),\n .dccm_wr_addr_hi(shadow_core_outputs.dccm_wr_addr_hi),\n .dccm_rd_addr_lo(shadow_core_outputs.dccm_rd_addr_lo),\n .dccm_rd_addr_hi(shadow_core_outputs.dccm_rd_addr_hi),\n .dccm_wr_data_lo(shadow_core_outputs.dccm_wr_data_lo),\n .dccm_wr_data_hi(shadow_core_outputs.dccm_wr_data_hi),\n .dccm_rd_data_lo(shadow_core_inputs.dccm_rd_data_lo),\n .dccm_rd_data_hi(shadow_core_inputs.dccm_rd_data_hi),\n\n .iccm_rw_addr(shadow_core_outputs.iccm_rw_addr),\n .iccm_wren(shadow_core_outputs.iccm_wren),\n .iccm_rden(shadow_core_outputs.iccm_rden),\n .iccm_wr_size(shadow_core_outputs.iccm_wr_size),\n .iccm_wr_data(shadow_core_outputs.iccm_wr_data),\n .iccm_buf_correct_ecc(shadow_core_outputs.iccm_buf_correct_ecc),\n .iccm_correction_state(shadow_core_outputs.iccm_correction_state),\n .iccm_rd_data(shadow_core_inputs.iccm_rd_data),\n .iccm_rd_data_ecc(shadow_core_inputs.iccm_rd_data_ecc),\n\n .ic_rw_addr(shadow_core_outputs.ic_rw_addr),\n .ic_tag_valid(shadow_core_outputs.ic_tag_valid),\n .ic_wr_en(shadow_core_outputs.ic_wr_en),\n .ic_rd_en(shadow_core_outputs.ic_rd_en),\n\n .ic_wr_data(shadow_core_outputs.ic_wr_data),\n .ic_rd_data(shadow_core_inputs.ic_rd_data),\n .ic_debug_rd_data(shadow_core_inputs.ic_debug_rd_data),\n .ictag_debug_rd_data(shadow_core_inputs.ictag_debug_rd_data),\n .ic_debug_wr_data(shadow_core_outputs.ic_debug_wr_data),\n\n .ic_eccerr(shadow_core_inputs.ic_eccerr),\n .ic_parerr(shadow_core_inputs.ic_parerr),\n .ic_premux_data(shadow_core_outputs.ic_premux_data),\n .ic_sel_premux_data(shadow_core_outputs.ic_sel_premux_data),\n\n .ic_debug_addr(shadow_core_outputs.ic_debug_addr),\n .ic_debug_rd_en(shadow_core_outputs.ic_debug_rd_en),\n .ic_debug_wr_en(shadow_core_outputs.ic_debug_wr_en),\n .ic_debug_tag_array(shadow_core_outputs.ic_debug_tag_array),\n .ic_debug_way(shadow_core_outputs.ic_debug_way),\n\n .ic_rd_hit (shadow_core_inputs.ic_rd_hit),\n .ic_tag_perr(shadow_core_inputs.ic_tag_perr),\n\n .lsu_axi_awvalid(shadow_core_outputs.lsu_axi_awvalid),\n .lsu_axi_awready(shadow_core_inputs.lsu_axi_awready),\n .lsu_axi_awid(shadow_core_outputs.lsu_axi_awid),\n .lsu_axi_awaddr(shadow_core_outputs.lsu_axi_awaddr),\n .lsu_axi_awregion(shadow_core_outputs.lsu_axi_awregion),\n .lsu_axi_awlen(shadow_core_outputs.lsu_axi_awlen),\n .lsu_axi_awsize(shadow_core_outputs.lsu_axi_awsize),\n .lsu_axi_awburst(shadow_core_outputs.lsu_axi_awburst),\n .lsu_axi_awlock(shadow_core_outputs.lsu_axi_awlock),\n .lsu_axi_awcache(shadow_core_outputs.lsu_axi_awcache),\n .lsu_axi_awprot(shadow_core_outputs.lsu_axi_awprot),\n .lsu_axi_awqos(shadow_core_outputs.lsu_axi_awqos),\n .lsu_axi_wvalid(shadow_core_outputs.lsu_axi_wvalid),\n .lsu_axi_wready(shadow_core_inputs.lsu_axi_wready),\n .lsu_axi_wdata(shadow_core_outputs.lsu_axi_wdata),\n .lsu_axi_wstrb(shadow_core_outputs.lsu_axi_wstrb),\n .lsu_axi_wlast(shadow_core_outputs.lsu_axi_wlast),\n .lsu_axi_bvalid(shadow_core_inputs.lsu_axi_bvalid),\n .lsu_axi_bready(shadow_core_outputs.lsu_axi_bready),\n .lsu_axi_bresp(shadow_core_inputs.lsu_axi_bresp),\n .lsu_axi_bid(shadow_core_inputs.lsu_axi_bid),\n .lsu_axi_arvalid(shadow_core_outputs.lsu_axi_arvalid),\n .lsu_axi_arready(shadow_core_inputs.lsu_axi_arready),\n .lsu_axi_arid(shadow_core_outputs.lsu_axi_arid),\n .lsu_axi_araddr(shadow_core_outputs.lsu_axi_araddr),\n .lsu_axi_arregion(shadow_core_outputs.lsu_axi_arregion),\n .lsu_axi_arlen(shadow_core_outputs.lsu_axi_arlen),\n .lsu_axi_arsize(shadow_core_outputs.lsu_axi_arsize),\n .lsu_axi_arburst(shadow_core_outputs.lsu_axi_arburst),\n .lsu_axi_arlock(shadow_core_outputs.lsu_axi_arlock),\n .lsu_axi_arcache(shadow_core_outputs.lsu_axi_arcache),\n .lsu_axi_arprot(shadow_core_outputs.lsu_axi_arprot),\n .lsu_axi_arqos(shadow_core_outputs.lsu_axi_arqos),\n .lsu_axi_rvalid(shadow_core_inputs.lsu_axi_rvalid),\n .lsu_axi_rready(shadow_core_outputs.lsu_axi_rready),\n .lsu_axi_rid(shadow_core_inputs.lsu_axi_rid),\n .lsu_axi_rdata(shadow_core_inputs.lsu_axi_rdata),\n .lsu_axi_rresp(shadow_core_inputs.lsu_axi_rresp),\n .lsu_axi_rlast(shadow_core_inputs.lsu_axi_rlast),\n\n .ifu_axi_awvalid(shadow_core_outputs.ifu_axi_awvalid),\n .ifu_axi_awready(shadow_core_inputs.ifu_axi_awready),\n .ifu_axi_awid(shadow_core_outputs.ifu_axi_awid),\n .ifu_axi_awaddr(shadow_core_outputs.ifu_axi_awaddr),\n .ifu_axi_awregion(shadow_core_outputs.ifu_axi_awregion),\n .ifu_axi_awlen(shadow_core_outputs.ifu_axi_awlen),\n .ifu_axi_awsize(shadow_core_outputs.ifu_axi_awsize),\n .ifu_axi_awburst(shadow_core_outputs.ifu_axi_awburst),\n .ifu_axi_awlock(shadow_core_outputs.ifu_axi_awlock),\n .ifu_axi_awcache(shadow_core_outputs.ifu_axi_awcache),\n .ifu_axi_awprot(shadow_core_outputs.ifu_axi_awprot),\n .ifu_axi_awqos(shadow_core_outputs.ifu_axi_awqos),\n .ifu_axi_wvalid(shadow_core_outputs.ifu_axi_wvalid),\n .ifu_axi_wready(shadow_core_inputs.ifu_axi_wready),\n .ifu_axi_wdata(shadow_core_outputs.ifu_axi_wdata),\n .ifu_axi_wstrb(shadow_core_outputs.ifu_axi_wstrb),\n .ifu_axi_wlast(shadow_core_outputs.ifu_axi_wlast),\n .ifu_axi_bvalid(shadow_core_inputs.ifu_axi_bvalid),\n .ifu_axi_bready(shadow_core_outputs.ifu_axi_bready),\n .ifu_axi_bresp(shadow_core_inputs.ifu_axi_bresp),\n .ifu_axi_bid(shadow_core_inputs.ifu_axi_bid),\n .ifu_axi_arvalid(shadow_core_outputs.ifu_axi_arvalid),\n .ifu_axi_arready(shadow_core_inputs.ifu_axi_arready),\n .ifu_axi_arid(shadow_core_outputs.ifu_axi_arid),\n .ifu_axi_araddr(shadow_core_outputs.ifu_axi_araddr),\n .ifu_axi_arregion(shadow_core_outputs.ifu_axi_arregion),\n .ifu_axi_arlen(shadow_core_outputs.ifu_axi_arlen),\n .ifu_axi_arsize(shadow_core_outputs.ifu_axi_arsize),\n .ifu_axi_arburst(shadow_core_outputs.ifu_axi_arburst),\n .ifu_axi_arlock(shadow_core_outputs.ifu_axi_arlock),\n .ifu_axi_arcache(shadow_core_outputs.ifu_axi_arcache),\n .ifu_axi_arprot(shadow_core_outputs.ifu_axi_arprot),\n .ifu_axi_arqos(shadow_core_outputs.ifu_axi_arqos),\n .ifu_axi_rvalid(shadow_core_inputs.ifu_axi_rvalid),\n .ifu_axi_rready(shadow_core_outputs.ifu_axi_rready),\n .ifu_axi_rid(shadow_core_inputs.ifu_axi_rid),\n .ifu_axi_rdata(shadow_core_inputs.ifu_axi_rdata),\n .ifu_axi_rresp(shadow_core_inputs.ifu_axi_rresp),\n .ifu_axi_rlast(shadow_core_inputs.ifu_axi_rlast),\n\n .sb_axi_awvalid(shadow_core_outputs.sb_axi_awvalid),\n .sb_axi_awready(shadow_core_inputs.sb_axi_awready),\n .sb_axi_awid(shadow_core_outputs.sb_axi_awid),\n .sb_axi_awaddr(shadow_core_outputs.sb_axi_awaddr),\n .sb_axi_awregion(shadow_core_outputs.sb_axi_awregion),\n .sb_axi_awlen(shadow_core_outputs.sb_axi_awlen),\n .sb_axi_awsize(shadow_core_outputs.sb_axi_awsize),\n .sb_axi_awburst(shadow_core_outputs.sb_axi_awburst),\n .sb_axi_awlock(shadow_core_outputs.sb_axi_awlock),\n .sb_axi_awcache(shadow_core_outputs.sb_axi_awcache),\n .sb_axi_awprot(shadow_core_outputs.sb_axi_awprot),\n .sb_axi_awqos(shadow_core_outputs.sb_axi_awqos),\n .sb_axi_wvalid(shadow_core_outputs.sb_axi_wvalid),\n .sb_axi_wready(shadow_core_inputs.sb_axi_wready),\n .sb_axi_wdata(shadow_core_outputs.sb_axi_wdata),\n .sb_axi_wstrb(shadow_core_outputs.sb_axi_wstrb),\n .sb_axi_wlast(shadow_core_outputs.sb_axi_wlast),\n .sb_axi_bvalid(shadow_core_inputs.sb_axi_bvalid),\n .sb_axi_bready(shadow_core_outputs.sb_axi_bready),\n .sb_axi_bresp(shadow_core_inputs.sb_axi_bresp),\n .sb_axi_bid(shadow_core_inputs.sb_axi_bid),\n .sb_axi_arvalid(shadow_core_outputs.sb_axi_arvalid),\n .sb_axi_arready(shadow_core_inputs.sb_axi_arready),\n .sb_axi_arid(shadow_core_outputs.sb_axi_arid),\n .sb_axi_araddr(shadow_core_outputs.sb_axi_araddr),\n .sb_axi_arregion(shadow_core_outputs.sb_axi_arregion),\n .sb_axi_arlen(shadow_core_outputs.sb_axi_arlen),\n .sb_axi_arsize(shadow_core_outputs.sb_axi_arsize),\n .sb_axi_arburst(shadow_core_outputs.sb_axi_arburst),\n .sb_axi_arlock(shadow_core_outputs.sb_axi_arlock),\n .sb_axi_arcache(shadow_core_outputs.sb_axi_arcache),\n .sb_axi_arprot(shadow_core_outputs.sb_axi_arprot),\n .sb_axi_arqos(shadow_core_outputs.sb_axi_arqos),\n .sb_axi_rvalid(shadow_core_inputs.sb_axi_rvalid),\n .sb_axi_rready(shadow_core_outputs.sb_axi_rready),\n .sb_axi_rid(shadow_core_inputs.sb_axi_rid),\n .sb_axi_rdata(shadow_core_inputs.sb_axi_rdata),\n .sb_axi_rresp(shadow_core_inputs.sb_axi_rresp),\n .sb_axi_rlast(shadow_core_inputs.sb_axi_rlast),\n\n .dma_axi_awvalid(shadow_core_inputs.dma_axi_awvalid),\n .dma_axi_awready(shadow_core_outputs.dma_axi_awready),\n .dma_axi_awid(shadow_core_inputs.dma_axi_awid),\n .dma_axi_awaddr(shadow_core_inputs.dma_axi_awaddr),\n .dma_axi_awsize(shadow_core_inputs.dma_axi_awsize),\n .dma_axi_awprot(shadow_core_inputs.dma_axi_awprot),\n .dma_axi_awlen(shadow_core_inputs.dma_axi_awlen),\n .dma_axi_awburst(shadow_core_inputs.dma_axi_awburst),\n .dma_axi_wvalid(shadow_core_inputs.dma_axi_wvalid),\n .dma_axi_wready(shadow_core_outputs.dma_axi_wready),\n .dma_axi_wdata(shadow_core_inputs.dma_axi_wdata),\n .dma_axi_wstrb(shadow_core_inputs.dma_axi_wstrb),\n .dma_axi_wlast(shadow_core_inputs.dma_axi_wlast),\n .dma_axi_bvalid(shadow_core_outputs.dma_axi_bvalid),\n .dma_axi_bready(shadow_core_inputs.dma_axi_bready),\n .dma_axi_bresp(shadow_core_outputs.dma_axi_bresp),\n .dma_axi_bid(shadow_core_outputs.dma_axi_bid),\n .dma_axi_arvalid(shadow_core_inputs.dma_axi_arvalid),\n .dma_axi_arready(shadow_core_outputs.dma_axi_arready),\n .dma_axi_arid(shadow_core_inputs.dma_axi_arid),\n .dma_axi_araddr(shadow_core_inputs.dma_axi_araddr),\n .dma_axi_arsize(shadow_core_inputs.dma_axi_arsize),\n .dma_axi_arprot(shadow_core_inputs.dma_axi_arprot),\n .dma_axi_arlen(shadow_core_inputs.dma_axi_arlen),\n .dma_axi_arburst(shadow_core_inputs.dma_axi_arburst),\n .dma_axi_rvalid(shadow_core_outputs.dma_axi_rvalid),\n .dma_axi_rready(shadow_core_inputs.dma_axi_rready),\n .dma_axi_rid(shadow_core_outputs.dma_axi_rid),\n .dma_axi_rdata(shadow_core_outputs.dma_axi_rdata),\n .dma_axi_rresp(shadow_core_outputs.dma_axi_rresp),\n .dma_axi_rlast(shadow_core_outputs.dma_axi_rlast),\n\n .haddr(shadow_core_outputs.haddr),\n .hburst(shadow_core_outputs.hburst),\n .hmastlock(shadow_core_outputs.hmastlock),\n .hprot(shadow_core_outputs.hprot),\n .hsize(shadow_core_outputs.hsize),\n .htrans(shadow_core_outputs.htrans),\n .hwrite(shadow_core_outputs.hwrite),\n .hrdata(shadow_core_inputs.hrdata),\n .hready(shadow_core_inputs.hready),\n .hresp(shadow_core_inputs.hresp),\n\n .lsu_haddr(shadow_core_outputs.lsu_haddr),\n .lsu_hburst(shadow_core_outputs.lsu_hburst),\n .lsu_hmastlock(shadow_core_outputs.lsu_hmastlock),\n .lsu_hprot(shadow_core_outputs.lsu_hprot),\n .lsu_hsize(shadow_core_outputs.lsu_hsize),\n .lsu_htrans(shadow_core_outputs.lsu_htrans),\n .lsu_hwrite(shadow_core_outputs.lsu_hwrite),\n .lsu_hwdata(shadow_core_outputs.lsu_hwdata),\n .lsu_hrdata(shadow_core_inputs.lsu_hrdata),\n .lsu_hready(shadow_core_inputs.lsu_hready),\n .lsu_hresp(shadow_core_inputs.lsu_hresp),\n\n .sb_haddr(shadow_core_outputs.sb_haddr),\n .sb_hburst(shadow_core_outputs.sb_hburst),\n .sb_hmastlock(shadow_core_outputs.sb_hmastlock),\n .sb_hprot(shadow_core_outputs.sb_hprot),\n .sb_hsize(shadow_core_outputs.sb_hsize),\n .sb_htrans(shadow_core_outputs.sb_htrans),\n .sb_hwrite(shadow_core_outputs.sb_hwrite),\n .sb_hwdata(shadow_core_outputs.sb_hwdata),\n .sb_hrdata(shadow_core_inputs.sb_hrdata),\n .sb_hready(shadow_core_inputs.sb_hready),\n .sb_hresp(shadow_core_inputs.sb_hresp),\n\n .dma_hsel(shadow_core_inputs.dma_hsel),\n .dma_haddr(shadow_core_inputs.dma_haddr),\n .dma_hburst(shadow_core_inputs.dma_hburst),\n .dma_hmastlock(shadow_core_inputs.dma_hmastlock),\n .dma_hprot(shadow_core_inputs.dma_hprot),\n .dma_hsize(shadow_core_inputs.dma_hsize),\n .dma_htrans(shadow_core_inputs.dma_htrans),\n .dma_hwrite(shadow_core_inputs.dma_hwrite),\n .dma_hwdata(shadow_core_inputs.dma_hwdata),\n .dma_hreadyin(shadow_core_inputs.dma_hreadyin),\n .dma_hrdata(shadow_core_outputs.dma_hrdata),\n .dma_hreadyout(shadow_core_outputs.dma_hreadyout),\n .dma_hresp(shadow_core_outputs.dma_hresp),\n\n .lsu_bus_clk_en(shadow_core_inputs.lsu_bus_clk_en),\n .ifu_bus_clk_en(shadow_core_inputs.ifu_bus_clk_en),\n .dbg_bus_clk_en(shadow_core_inputs.dbg_bus_clk_en),\n .dma_bus_clk_en(shadow_core_inputs.dma_bus_clk_en),\n\n .dmi_reg_en(shadow_core_inputs.dmi_reg_en),\n .dmi_reg_addr(shadow_core_inputs.dmi_reg_addr),\n .dmi_reg_wr_en(shadow_core_inputs.dmi_reg_wr_en),\n .dmi_reg_wdata(shadow_core_inputs.dmi_reg_wdata),\n .dmi_reg_rdata(shadow_core_outputs.dmi_reg_rdata),\n\n .iccm_ecc_single_error(shadow_core_outputs.iccm_ecc_single_error),\n .iccm_ecc_double_error(shadow_core_outputs.iccm_ecc_double_error),\n .dccm_ecc_single_error(shadow_core_outputs.dccm_ecc_single_error),\n .dccm_ecc_double_error(shadow_core_outputs.dccm_ecc_double_error),\n\n .extintsrc_req(shadow_core_inputs.extintsrc_req),\n .timer_int(shadow_core_inputs.timer_int),\n .soft_int(shadow_core_inputs.soft_int),\n .scan_mode(shadow_core_inputs.scan_mode)\n );\n\n // Equivalence Check\n logic rst_n;\n assign rst_n = rst_shadow & rst_dbg_shadow;\n\n logic corruption_detected, outputs_corrupted;\n assign outputs_corrupted = delayed_main_core_outputs != shadow_core_outputs;\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n logic regfile_corrupted;\n assign regfile_corrupted = (delayed_main_core_regfile[LockstepDelay].gpr != shadow_core_regfile.gpr)\n | (delayed_main_core_regfile[LockstepDelay].tlu != shadow_core_regfile.tlu);\n assign corruption_detected = outputs_corrupted | regfile_corrupted;\n`else\n assign corruption_detected = outputs_corrupted;\n`endif\n\n// Report corruption if all of the below requirements are fulfilled:\n// - IOs of Main Core and Shadow Core differ OR error injection is enabled\n// - Shadow Core is out of reset\n// - Shadow Core is enabled\nassign corruption_detected_o = ((corruption_detected | lockstep_err_injection_en_i) & rst_n) & ~disable_corruption_detection_i;\n\nendmodule : el2_veer_lockstep\n" }, { "path": "design/el2_veer_wrapper.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n// Copyright (c) 2023 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n// Function: Top wrapper file with el2_veer/mem instantiated inside\n// Comments:\n//\n//********************************************************************************\nmodule el2_veer_wrapper\nimport el2_pkg::*;\n #(\n`include \"el2_param.vh\"\n)\n(\n input logic clk,\n input logic rst_l,\n input logic dbg_rst_l,\n // rst_vec is supposed to be tied to constant in the top level\n /*pragma coverage off*/\n input logic [31:1] rst_vec,\n /*pragma coverage on*/\n input logic nmi_int,\n // jtag_id and nmi_vec are supposed to be tied to constants in the top level\n /*pragma coverage off*/\n input logic [31:1] nmi_vec,\n input logic [31:1] jtag_id,\n /*pragma coverage on*/\n\n\n output logic [31:0] trace_rv_i_insn_ip,\n output logic [31:0] trace_rv_i_address_ip,\n output logic trace_rv_i_valid_ip,\n output logic trace_rv_i_exception_ip,\n output logic [4:0] trace_rv_i_ecause_ip,\n output logic trace_rv_i_interrupt_ip,\n output logic [31:0] trace_rv_i_tval_ip,\n\n // Bus signals\n`ifdef RV_BUILD_AXI4\n //-------------------------- LSU AXI signals--------------------------\n // AXI Write Channels\n output logic lsu_axi_awvalid,\n input logic lsu_axi_awready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,\n output logic [31:0] lsu_axi_awaddr,\n output logic [3:0] lsu_axi_awregion,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_awlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_awsize,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_awburst,\n output logic lsu_axi_awlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_awcache,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_awprot,\n output logic [3:0] lsu_axi_awqos,\n /*pragma coverage on*/\n\n output logic lsu_axi_wvalid,\n input logic lsu_axi_wready,\n output logic [63:0] lsu_axi_wdata,\n output logic [7:0] lsu_axi_wstrb,\n output logic lsu_axi_wlast,\n\n input logic lsu_axi_bvalid,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic lsu_axi_bready,\n /*pragma coverage on*/\n input logic [1:0] lsu_axi_bresp,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,\n\n // AXI Read Channels\n output logic lsu_axi_arvalid,\n input logic lsu_axi_arready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,\n output logic [31:0] lsu_axi_araddr,\n output logic [3:0] lsu_axi_arregion,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_arlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_arsize,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_arburst,\n output logic lsu_axi_arlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_arcache,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_arprot,\n output logic [3:0] lsu_axi_arqos,\n /*pragma coverage on*/\n\n input logic lsu_axi_rvalid,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic lsu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,\n input logic [63:0] lsu_axi_rdata,\n input logic [1:0] lsu_axi_rresp,\n input logic lsu_axi_rlast,\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv\n IFU does not use AXI write channel */\n /*pragma coverage off*/\n output logic ifu_axi_awvalid,\n input logic ifu_axi_awready,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,\n output logic [31:0] ifu_axi_awaddr,\n output logic [3:0] ifu_axi_awregion,\n output logic [7:0] ifu_axi_awlen,\n output logic [2:0] ifu_axi_awsize,\n output logic [1:0] ifu_axi_awburst,\n output logic ifu_axi_awlock,\n output logic [3:0] ifu_axi_awcache,\n output logic [2:0] ifu_axi_awprot,\n output logic [3:0] ifu_axi_awqos,\n\n output logic ifu_axi_wvalid,\n input logic ifu_axi_wready,\n output logic [63:0] ifu_axi_wdata,\n output logic [7:0] ifu_axi_wstrb,\n output logic ifu_axi_wlast,\n\n input logic ifu_axi_bvalid,\n output logic ifu_axi_bready,\n input logic [1:0] ifu_axi_bresp,\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,\n /*pragma coverage on*/\n\n // AXI Read Channels\n output logic ifu_axi_arvalid,\n input logic ifu_axi_arready,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,\n output logic [31:0] ifu_axi_araddr,\n output logic [3:0] ifu_axi_arregion,\n /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */\n /*pragma coverage off*/\n output logic [7:0] ifu_axi_arlen,\n output logic [2:0] ifu_axi_arsize,\n output logic [1:0] ifu_axi_arburst,\n output logic ifu_axi_arlock,\n output logic [3:0] ifu_axi_arcache,\n output logic [2:0] ifu_axi_arprot,\n output logic [3:0] ifu_axi_arqos,\n /*pragma coverage on*/\n\n input logic ifu_axi_rvalid,\n /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */\n /*pragma coverage off*/\n output logic ifu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,\n input logic [63:0] ifu_axi_rdata,\n input logic [1:0] ifu_axi_rresp,\n input logic ifu_axi_rlast,\n\n //-------------------------- SB AXI signals--------------------------\n // AXI Write Channels\n output logic sb_axi_awvalid,\n input logic sb_axi_awready,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,\n /*pragma coverage on*/\n output logic [31:0] sb_axi_awaddr,\n output logic [3:0] sb_axi_awregion,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [7:0] sb_axi_awlen,\n /*pragma coverage on*/\n output logic [2:0] sb_axi_awsize,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [1:0] sb_axi_awburst,\n output logic sb_axi_awlock,\n output logic [3:0] sb_axi_awcache,\n output logic [2:0] sb_axi_awprot,\n output logic [3:0] sb_axi_awqos,\n /*pragma coverage on*/\n\n output logic sb_axi_wvalid,\n input logic sb_axi_wready,\n output logic [63:0] sb_axi_wdata,\n output logic [7:0] sb_axi_wstrb,\n output logic sb_axi_wlast,\n\n input logic sb_axi_bvalid,\n output logic sb_axi_bready,\n input logic [1:0] sb_axi_bresp,\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,\n\n // AXI Read Channels\n output logic sb_axi_arvalid,\n input logic sb_axi_arready,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,\n /*pragma coverage on*/\n output logic [31:0] sb_axi_araddr,\n output logic [3:0] sb_axi_arregion,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [7:0] sb_axi_arlen,\n /*pragma coverage on*/\n output logic [2:0] sb_axi_arsize,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic [1:0] sb_axi_arburst,\n output logic sb_axi_arlock,\n output logic [3:0] sb_axi_arcache,\n output logic [2:0] sb_axi_arprot,\n output logic [3:0] sb_axi_arqos,\n /*pragma coverage on*/\n\n input logic sb_axi_rvalid,\n /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */\n /*pragma coverage off*/\n output logic sb_axi_rready,\n /*pragma coverage on*/\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,\n input logic [63:0] sb_axi_rdata,\n input logic [1:0] sb_axi_rresp,\n input logic sb_axi_rlast,\n\n //-------------------------- DMA AXI signals--------------------------\n // AXI Write Channels\n input logic dma_axi_awvalid,\n output logic dma_axi_awready,\n /* exclude signals that are tied to constant value in tb_top.sv */\n /*pragma coverage off*/\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,\n /*pragma coverage on*/\n input logic [31:0] dma_axi_awaddr,\n input logic [2:0] dma_axi_awsize,\n input logic [2:0] dma_axi_awprot,\n input logic [7:0] dma_axi_awlen,\n input logic [1:0] dma_axi_awburst,\n\n\n input logic dma_axi_wvalid,\n output logic dma_axi_wready,\n input logic [63:0] dma_axi_wdata,\n input logic [7:0] dma_axi_wstrb,\n input logic dma_axi_wlast,\n\n output logic dma_axi_bvalid,\n input logic dma_axi_bready,\n output logic [1:0] dma_axi_bresp,\n output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,\n\n // AXI Read Channels\n input logic dma_axi_arvalid,\n output logic dma_axi_arready,\n /* exclude signals that are tied to constant value in tb_top.sv */\n /*pragma coverage off*/\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,\n /*pragma coverage on*/\n input logic [31:0] dma_axi_araddr,\n input logic [2:0] dma_axi_arsize,\n input logic [2:0] dma_axi_arprot,\n input logic [7:0] dma_axi_arlen,\n input logic [1:0] dma_axi_arburst,\n\n output logic dma_axi_rvalid,\n input logic dma_axi_rready,\n output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,\n output logic [63:0] dma_axi_rdata,\n output logic [1:0] dma_axi_rresp,\n output logic dma_axi_rlast,\n`endif\n\n`ifdef RV_BUILD_AHB_LITE\n //// AHB LITE BUS\n output logic [31:0] haddr,\n /* exclude signals that are tied to constant value in axi4_to_ahb.sv */\n /*pragma coverage off*/\n output logic [2:0] hburst,\n output logic hmastlock,\n /*pragma coverage on*/\n output logic [3:0] hprot,\n output logic [2:0] hsize,\n output logic [1:0] htrans,\n output logic hwrite,\n\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n input logic [63:0] hrdata,\n input logic hready,\n input logic hresp,\n /*pragma coverage on*/\n\n // LSU AHB Master\n output logic [31:0] lsu_haddr,\n /* exclude signals that are tied to constant value in axi4_to_ahb.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_hburst,\n output logic lsu_hmastlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_hprot,\n output logic [2:0] lsu_hsize,\n output logic [1:0] lsu_htrans,\n output logic lsu_hwrite,\n output logic [63:0] lsu_hwdata,\n\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n input logic [63:0] lsu_hrdata,\n input logic lsu_hready,\n input logic lsu_hresp,\n /*pragma coverage on*/\n // Debug System Bus AHB\n output logic [31:0] sb_haddr,\n /* exclude signals that are tied to constant value in axi4_to_ahb.sv */\n /*pragma coverage off*/\n output logic [2:0] sb_hburst,\n output logic sb_hmastlock,\n /*pragma coverage on*/\n output logic [3:0] sb_hprot,\n output logic [2:0] sb_hsize,\n output logic [1:0] sb_htrans,\n output logic sb_hwrite,\n output logic [63:0] sb_hwdata,\n\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n input logic [63:0] sb_hrdata,\n input logic sb_hready,\n input logic sb_hresp,\n /*pragma coverage on*/\n\n // DMA Slave\n /* exclude signals that are tied to constant value in tb_top.sv */\n /*pragma coverage off*/\n input logic dma_hsel,\n input logic [31:0] dma_haddr,\n input logic [2:0] dma_hburst,\n input logic dma_hmastlock,\n input logic [3:0] dma_hprot,\n input logic [2:0] dma_hsize,\n input logic [1:0] dma_htrans,\n input logic dma_hwrite,\n input logic [63:0] dma_hwdata,\n /*pragma coverage on*/\n input logic dma_hreadyin,\n\n output logic [63:0] dma_hrdata,\n output logic dma_hreadyout,\n output logic dma_hresp,\n`endif\n // clk ratio signals\n input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface\n input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface\n input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface\n input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface\n\n // ICCM/DCCM ECC status\n output logic iccm_ecc_single_error,\n output logic iccm_ecc_double_error,\n output logic dccm_ecc_single_error,\n output logic dccm_ecc_double_error,\n\n // ICache export interface\n el2_mem_if.veer_icache_src el2_icache_export,\n\n input logic timer_int,\n input logic soft_int,\n input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,\n\n output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc\n output logic dec_tlu_perfcnt1,\n output logic dec_tlu_perfcnt2,\n output logic dec_tlu_perfcnt3,\n\n // ports added by the soc team\n input logic jtag_tck, // JTAG clk\n input logic jtag_tms, // JTAG TMS\n input logic jtag_tdi, // JTAG tdi\n input logic jtag_trst_n, // JTAG Reset\n output logic jtag_tdo, // JTAG TDO\n output logic jtag_tdoEn, // JTAG Test Data Output enable\n\n /*pragma coverage off*/\n input logic [31:4] core_id,\n /*pragma coverage on*/\n\n // Memory Export Interface\n el2_mem_if.veer_sram_src el2_mem_export,\n\n`ifdef RV_LOCKSTEP_ENABLE\n // Shadow Core control\n input logic disable_corruption_detection_i,\n input logic lockstep_err_injection_en_i,\n output logic corruption_detected_o,\n`endif\n\n // external MPC halt/run interface\n input logic mpc_debug_halt_req, // Async halt request\n input logic mpc_debug_run_req, // Async run request\n input logic mpc_reset_run_req, // Run/halt after reset\n output logic mpc_debug_halt_ack, // Halt ack\n output logic mpc_debug_run_ack, // Run ack\n output logic debug_brkpt_status, // debug breakpoint\n\n input logic i_cpu_halt_req, // Async halt req to CPU\n output logic o_cpu_halt_ack, // core response to halt\n output logic o_cpu_halt_status, // 1'b1 indicates core is halted\n output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request\n input logic i_cpu_run_req, // Async restart req to CPU\n output logic o_cpu_run_ack, // Core response to run req\n\n // Excluding scan_mode and mbist_mode from coverage as their usage is determined by the integrator of the VeeR core.\n /* pragma coverage off */\n input logic scan_mode, // To enable scan mode\n input logic mbist_mode, // to enable mbist\n\n // DMI port for uncore\n input logic dmi_core_enable,\n input logic dmi_uncore_enable,\n output logic dmi_uncore_en,\n output logic dmi_uncore_wr_en,\n output logic [ 6:0] dmi_uncore_addr,\n output logic [31:0] dmi_uncore_wdata,\n input logic [31:0] dmi_uncore_rdata,\n output logic dmi_active\n /* pragma coverage on */\n);\n\n logic active_l2clk;\n logic free_l2clk;\n\n // DCCM ports\n logic dccm_wren;\n logic dccm_rden;\n logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo;\n logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi;\n logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo;\n logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi;\n\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;\n\n // PIC ports\n\n // Icache & Itag ports\n logic [31:1] ic_rw_addr;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en ; // Which way to write\n logic ic_rd_en ;\n\n\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid; // Valid from the I$ tag valid outside (in flops).\n\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit; // ic_rd_hit[3:0]\n logic ic_tag_perr; // Ic tag parity error\n\n logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr; // Read/Write addresss to the Icache.\n logic ic_debug_rd_en; // Icache debug rd\n logic ic_debug_wr_en; // Icache debug wr\n logic ic_debug_tag_array; // Debug tag array\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way; // Debug way. Rd or Wr.\n\n logic [25:0] ictag_debug_rd_data; // Debug icache tag.\n logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;\n logic [63:0] ic_rd_data;\n logic [70:0] ic_debug_rd_data; // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n logic [70:0] ic_debug_wr_data; // Debug wr cache.\n\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr; // ecc error per bank\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr; // parity error per bank\n\n logic [63:0] ic_premux_data;\n logic ic_sel_premux_data;\n\n // ICCM ports\n logic [pt.ICCM_BITS-1:1] iccm_rw_addr;\n logic iccm_wren;\n logic iccm_rden;\n logic [2:0] iccm_wr_size;\n logic [77:0] iccm_wr_data;\n logic iccm_buf_correct_ecc;\n logic iccm_correction_state;\n\n logic [63:0] iccm_rd_data;\n logic [77:0] iccm_rd_data_ecc;\n\n logic core_rst_l; // Core reset including rst_l and dbg_rst_l\n\n logic dccm_clk_override;\n logic icm_clk_override;\n logic dec_tlu_core_ecc_disable;\n\n\n // zero out the signals not presented at the wrapper instantiation level\n`ifdef RV_BUILD_AXI4\n // Since all the signals in this block are tied to constant, we exclude this from coverage analysis\n /*pragma coverage off*/\n\n //// AHB LITE BUS\n logic [31:0] haddr;\n logic [2:0] hburst;\n logic hmastlock;\n logic [3:0] hprot;\n logic [2:0] hsize;\n logic [1:0] htrans;\n logic hwrite;\n\n logic [63:0] hrdata;\n logic hready;\n logic hresp;\n\n // LSU AHB Master\n logic [31:0] lsu_haddr;\n logic [2:0] lsu_hburst;\n logic lsu_hmastlock;\n logic [3:0] lsu_hprot;\n logic [2:0] lsu_hsize;\n logic [1:0] lsu_htrans;\n logic lsu_hwrite;\n logic [63:0] lsu_hwdata;\n\n logic [63:0] lsu_hrdata;\n logic lsu_hready;\n logic lsu_hresp;\n // Debug System Bus AHB\n logic [31:0] sb_haddr;\n logic [2:0] sb_hburst;\n logic sb_hmastlock;\n logic [3:0] sb_hprot;\n logic [2:0] sb_hsize;\n logic [1:0] sb_htrans;\n logic sb_hwrite;\n logic [63:0] sb_hwdata;\n\n logic [63:0] sb_hrdata;\n logic sb_hready;\n logic sb_hresp;\n\n // DMA Slave\n logic dma_hsel;\n logic [31:0] dma_haddr;\n logic [2:0] dma_hburst;\n logic dma_hmastlock;\n logic [3:0] dma_hprot;\n logic [2:0] dma_hsize;\n logic [1:0] dma_htrans;\n logic dma_hwrite;\n logic [63:0] dma_hwdata;\n logic dma_hreadyin;\n\n logic [63:0] dma_hrdata;\n logic dma_hreadyout;\n logic dma_hresp;\n\n\n\n // AHB\n assign hrdata[63:0] = '0;\n assign hready = '0;\n assign hresp = '0;\n // LSU\n assign lsu_hrdata[63:0] = '0;\n assign lsu_hready = '0;\n assign lsu_hresp = '0;\n // Debu\n assign sb_hrdata[63:0] = '0;\n assign sb_hready = '0;\n assign sb_hresp = '0;\n\n // DMA\n assign dma_hsel = '0;\n assign dma_haddr[31:0] = '0;\n assign dma_hburst[2:0] = '0;\n assign dma_hmastlock = '0;\n assign dma_hprot[3:0] = '0;\n assign dma_hsize[2:0] = '0;\n assign dma_htrans[1:0] = '0;\n assign dma_hwrite = '0;\n assign dma_hwdata[63:0] = '0;\n assign dma_hreadyin = '0;\n\n /*pragma coverage on*/\n\n`endif // `ifdef RV_BUILD_AXI4\n\n\n`ifdef RV_BUILD_AHB_LITE\n // Since all the signals in this block are tied to constant, we exclude this from coverage analysis\n /*pragma coverage off*/\n wire lsu_axi_awvalid;\n wire lsu_axi_awready;\n wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;\n wire [31:0] lsu_axi_awaddr;\n wire [3:0] lsu_axi_awregion;\n wire [7:0] lsu_axi_awlen;\n wire [2:0] lsu_axi_awsize;\n wire [1:0] lsu_axi_awburst;\n wire lsu_axi_awlock;\n wire [3:0] lsu_axi_awcache;\n wire [2:0] lsu_axi_awprot;\n wire [3:0] lsu_axi_awqos;\n\n\n wire lsu_axi_wvalid;\n wire lsu_axi_wready;\n wire [63:0] lsu_axi_wdata;\n wire [7:0] lsu_axi_wstrb;\n wire lsu_axi_wlast;\n\n wire lsu_axi_bvalid;\n wire lsu_axi_bready;\n wire [1:0] lsu_axi_bresp;\n wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;\n\n // AXI Read Channels\n wire lsu_axi_arvalid;\n wire lsu_axi_arready;\n wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;\n wire [31:0] lsu_axi_araddr;\n wire [3:0] lsu_axi_arregion;\n wire [7:0] lsu_axi_arlen;\n wire [2:0] lsu_axi_arsize;\n wire [1:0] lsu_axi_arburst;\n wire lsu_axi_arlock;\n wire [3:0] lsu_axi_arcache;\n wire [2:0] lsu_axi_arprot;\n wire [3:0] lsu_axi_arqos;\n\n wire lsu_axi_rvalid;\n wire lsu_axi_rready;\n wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;\n wire [63:0] lsu_axi_rdata;\n wire [1:0] lsu_axi_rresp;\n wire lsu_axi_rlast;\n\n assign lsu_axi_awready = '0;\n assign lsu_axi_wready = '0;\n assign lsu_axi_bvalid = '0;\n assign lsu_axi_bresp = '0;\n assign lsu_axi_bid = {pt.LSU_BUS_TAG{1'b0}};\n assign lsu_axi_arready = '0;\n assign lsu_axi_rvalid = '0;\n assign lsu_axi_rid = {pt.LSU_BUS_TAG{1'b0}};\n assign lsu_axi_rdata = '0;\n assign lsu_axi_rresp = '0;\n assign lsu_axi_rlast = '0;\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n wire ifu_axi_awvalid;\n wire ifu_axi_awready;\n wire [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;\n wire [31:0] ifu_axi_awaddr;\n wire [3:0] ifu_axi_awregion;\n wire [7:0] ifu_axi_awlen;\n wire [2:0] ifu_axi_awsize;\n wire [1:0] ifu_axi_awburst;\n wire ifu_axi_awlock;\n wire [3:0] ifu_axi_awcache;\n wire [2:0] ifu_axi_awprot;\n wire [3:0] ifu_axi_awqos;\n\n wire ifu_axi_wvalid;\n wire ifu_axi_wready;\n wire [63:0] ifu_axi_wdata;\n wire [7:0] ifu_axi_wstrb;\n wire ifu_axi_wlast;\n\n wire ifu_axi_bvalid;\n wire ifu_axi_bready;\n wire [1:0] ifu_axi_bresp;\n wire [pt.IFU_BUS_TAG-1:0] ifu_axi_bid;\n\n // AXI Read Channels\n wire ifu_axi_arvalid;\n wire ifu_axi_arready;\n wire [pt.IFU_BUS_TAG-1:0] ifu_axi_arid;\n wire [31:0] ifu_axi_araddr;\n wire [3:0] ifu_axi_arregion;\n wire [7:0] ifu_axi_arlen;\n wire [2:0] ifu_axi_arsize;\n wire [1:0] ifu_axi_arburst;\n wire ifu_axi_arlock;\n wire [3:0] ifu_axi_arcache;\n wire [2:0] ifu_axi_arprot;\n wire [3:0] ifu_axi_arqos;\n\n wire ifu_axi_rvalid;\n wire ifu_axi_rready;\n wire [pt.IFU_BUS_TAG-1:0] ifu_axi_rid;\n wire [63:0] ifu_axi_rdata;\n wire [1:0] ifu_axi_rresp;\n wire ifu_axi_rlast;\n\n assign ifu_axi_bvalid = '0;\n assign ifu_axi_bresp = '0;\n assign ifu_axi_bid = {pt.IFU_BUS_TAG{1'b0}};\n assign ifu_axi_arready = '0;\n assign ifu_axi_rvalid = '0;\n assign ifu_axi_rid = {pt.IFU_BUS_TAG{1'b0}};\n assign ifu_axi_rdata = 0;\n assign ifu_axi_rresp = '0;\n assign ifu_axi_rlast = '0;\n //-------------------------- SB AXI signals--------------------------\n // AXI Write Channels\n wire sb_axi_awvalid;\n wire sb_axi_awready;\n wire [pt.SB_BUS_TAG-1:0] sb_axi_awid;\n wire [31:0] sb_axi_awaddr;\n wire [3:0] sb_axi_awregion;\n wire [7:0] sb_axi_awlen;\n wire [2:0] sb_axi_awsize;\n wire [1:0] sb_axi_awburst;\n wire sb_axi_awlock;\n wire [3:0] sb_axi_awcache;\n wire [2:0] sb_axi_awprot;\n wire [3:0] sb_axi_awqos;\n\n wire sb_axi_wvalid;\n wire sb_axi_wready;\n wire [63:0] sb_axi_wdata;\n wire [7:0] sb_axi_wstrb;\n wire sb_axi_wlast;\n\n wire sb_axi_bvalid;\n wire sb_axi_bready;\n wire [1:0] sb_axi_bresp;\n wire [pt.SB_BUS_TAG-1:0] sb_axi_bid;\n\n // AXI Read Channels\n wire sb_axi_arvalid;\n wire sb_axi_arready;\n wire [pt.SB_BUS_TAG-1:0] sb_axi_arid;\n wire [31:0] sb_axi_araddr;\n wire [3:0] sb_axi_arregion;\n wire [7:0] sb_axi_arlen;\n wire [2:0] sb_axi_arsize;\n wire [1:0] sb_axi_arburst;\n wire sb_axi_arlock;\n wire [3:0] sb_axi_arcache;\n wire [2:0] sb_axi_arprot;\n wire [3:0] sb_axi_arqos;\n\n wire sb_axi_rvalid;\n wire sb_axi_rready;\n wire [pt.SB_BUS_TAG-1:0] sb_axi_rid;\n wire [63:0] sb_axi_rdata;\n wire [1:0] sb_axi_rresp;\n wire sb_axi_rlast;\n\n assign sb_axi_awready = '0;\n assign sb_axi_wready = '0;\n assign sb_axi_bvalid = '0;\n assign sb_axi_bresp = '0;\n assign sb_axi_bid = {pt.SB_BUS_TAG{1'b0}};\n assign sb_axi_arready = '0;\n assign sb_axi_rvalid = '0;\n assign sb_axi_rid = {pt.SB_BUS_TAG{1'b0}};\n assign sb_axi_rdata = '0;\n assign sb_axi_rresp = '0;\n assign sb_axi_rlast = '0;\n //-------------------------- DMA AXI signals--------------------------\n // AXI Write Channels\n wire dma_axi_awvalid;\n wire dma_axi_awready;\n wire [pt.DMA_BUS_TAG-1:0] dma_axi_awid;\n wire [31:0] dma_axi_awaddr;\n wire [2:0] dma_axi_awsize;\n wire [2:0] dma_axi_awprot;\n wire [7:0] dma_axi_awlen;\n wire [1:0] dma_axi_awburst;\n\n\n wire dma_axi_wvalid;\n wire dma_axi_wready;\n wire [63:0] dma_axi_wdata;\n wire [7:0] dma_axi_wstrb;\n wire dma_axi_wlast;\n\n assign dma_axi_awvalid = 1'b0;\n assign dma_axi_awid = {pt.DMA_BUS_TAG{1'b0}};\n assign dma_axi_awaddr = 32'd0;\n assign dma_axi_awsize = 3'd0;\n assign dma_axi_awprot = 3'd0;\n assign dma_axi_awlen = 8'd0;\n assign dma_axi_awburst = 2'd0;\n\n\n assign dma_axi_wvalid = 1'b0;\n assign dma_axi_wdata = 64'd0;\n assign dma_axi_wstrb = 8'd0;\n assign dma_axi_wlast = 1'b0;\n\n\n wire dma_axi_bvalid;\n wire dma_axi_bready;\n wire [1:0] dma_axi_bresp;\n wire [pt.DMA_BUS_TAG-1:0] dma_axi_bid;\n\n assign dma_axi_bready = 1'b0;\n // AXI Read Channels\n wire dma_axi_arvalid;\n wire dma_axi_arready;\n wire [pt.DMA_BUS_TAG-1:0] dma_axi_arid;\n wire [31:0] dma_axi_araddr;\n wire [2:0] dma_axi_arsize;\n wire [2:0] dma_axi_arprot;\n wire [7:0] dma_axi_arlen;\n wire [1:0] dma_axi_arburst;\n\n assign dma_axi_arvalid = 1'b0;\n assign dma_axi_arid = {pt.DMA_BUS_TAG{1'b0}};\n assign dma_axi_araddr = 32'd0;\n assign dma_axi_arsize = 3'd0;\n assign dma_axi_arprot = 3'd0;\n assign dma_axi_arlen = 8'd0;\n assign dma_axi_arburst = 2'd0;\n\n\n\n wire dma_axi_rvalid;\n wire dma_axi_rready;\n wire [pt.DMA_BUS_TAG-1:0] dma_axi_rid;\n wire [63:0] dma_axi_rdata;\n wire [1:0] dma_axi_rresp;\n wire dma_axi_rlast;\n\n assign dma_axi_rready = 1'b0;\n // AXI\n assign ifu_axi_awready = 1'b1;\n assign ifu_axi_wready = 1'b1;\n assign ifu_axi_bvalid = '0;\n assign ifu_axi_bresp[1:0] = '0;\n assign ifu_axi_bid[pt.IFU_BUS_TAG-1:0] = '0;\n \n /*pragma coverage on*/\n\n`endif // `ifdef RV_BUILD_AHB_LITE\n\n // DMI (core)\n logic dmi_en;\n logic [6:0] dmi_addr;\n logic dmi_wr_en;\n logic [31:0] dmi_wdata;\n logic [31:0] dmi_rdata;\n\n // DMI (core)\n logic dmi_reg_en;\n logic [6:0] dmi_reg_addr;\n logic dmi_reg_wr_en;\n logic [31:0] dmi_reg_wdata;\n logic [31:0] dmi_reg_rdata;\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n el2_regfile_if regfile ();\n`endif\n\n // Instantiate the el2_veer core\n el2_veer #(.pt(pt)) veer (\n .clk(clk),\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .regfile(regfile.veer_rf_src),\n`endif\n .*\n );\n\n`ifdef RV_LOCKSTEP_ENABLE\n initial begin\n $display(\"Dual Core Lockstep enabled!\\n\");\n end\n\n el2_veer_lockstep #(.pt(pt)) lockstep (\n .clk(clk),\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .main_core_regfile(regfile.veer_rf_sink),\n`endif // `ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .*\n );\n`endif // `ifdef RV_LOCKSTEP_ENABLE\n\n // Instantiate the mem\n el2_mem #(.pt(pt)) mem (\n .clk(active_l2clk),\n .rst_l(core_rst_l),\n .mem_export(el2_mem_export),\n .icache_export(el2_icache_export),\n .*\n );\n\n\n logic unused_dmi_hard_reset;\n // JTAG/DMI instance\n dmi_wrapper dmi_wrapper (\n // JTAG signals\n .trst_n (jtag_trst_n), // JTAG reset\n .tck (jtag_tck), // JTAG clock\n .tms (jtag_tms), // Test mode select\n .tdi (jtag_tdi), // Test Data Input\n .tdo (jtag_tdo), // Test Data Output\n .tdoEnable (jtag_tdoEn), // Test Data Output enable\n // Processor Signals\n .core_rst_n (dbg_rst_l), // Debug reset, active low\n .core_clk (clk), // Core clock\n .jtag_id (jtag_id), // JTAG ID\n .rd_data (dmi_rdata), // Read data from Processor\n .reg_wr_data (dmi_wdata), // Write data to Processor\n .reg_wr_addr (dmi_addr), // Write address to Processor\n .reg_en (dmi_en), // Write interface bit to Processor\n .reg_wr_en (dmi_wr_en), // Write enable to Processor\n .dmi_hard_reset (unused_dmi_hard_reset)\n );\n\n // DMI core/uncore mux\n dmi_mux dmi_mux (\n .core_enable (dmi_core_enable),\n .uncore_enable (dmi_uncore_enable),\n\n .dmi_en (dmi_en),\n .dmi_wr_en (dmi_wr_en),\n .dmi_addr (dmi_addr),\n .dmi_wdata (dmi_wdata),\n .dmi_rdata (dmi_rdata),\n\n .dmi_core_en (dmi_reg_en),\n .dmi_core_wr_en (dmi_reg_wr_en),\n .dmi_core_addr (dmi_reg_addr),\n .dmi_core_wdata (dmi_reg_wdata),\n .dmi_core_rdata (dmi_reg_rdata),\n\n .dmi_uncore_en (dmi_uncore_en),\n .dmi_uncore_wr_en (dmi_uncore_wr_en),\n .dmi_uncore_addr (dmi_uncore_addr),\n .dmi_uncore_wdata (dmi_uncore_wdata),\n .dmi_uncore_rdata (dmi_uncore_rdata)\n );\n\n always_comb dmi_active = dmi_en;\n\n`ifdef RV_ASSERT_ON\n // to avoid internal assertions failure at time 0\n initial begin\n $assertoff(0, veer);\n @(negedge clk) $asserton(0, veer);\n end\n`endif\n\nendmodule\n" }, { "path": "design/exu/el2_exu.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n\nmodule el2_exu\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n)\n (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Scan control\n /*pragma coverage on*/\n\n input logic [1:0] dec_data_en, // Clock enable {x,r}, one cycle pulse\n input logic [1:0] dec_ctl_en, // Clock enable {x,r}, two cycle pulse\n input logic [31:0] dbg_cmd_wrdata, // Debug data to primary I0 RS1\n input el2_alu_pkt_t i0_ap, // DEC alu {valid,predecodes}\n\n input logic dec_debug_wdata_rs1_d, // Debug select to primary I0 RS1\n\n input el2_predict_pkt_t dec_i0_predict_p_d, // DEC branch predict packet\n input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index\n input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag\n\n input logic [31:0] lsu_result_m, // Load result M-stage\n input logic [31:0] lsu_nonblock_load_data, // nonblock load data\n input logic dec_i0_rs1_en_d, // Qualify GPR RS1 data\n input logic dec_i0_rs2_en_d, // Qualify GPR RS2 data\n input logic [31:0] gpr_i0_rs1_d, // DEC data gpr\n input logic [31:0] gpr_i0_rs2_d, // DEC data gpr\n input logic [31:0] dec_i0_immed_d, // DEC data immediate\n input logic [31:0] dec_i0_result_r, // DEC result in R-stage\n input logic [12:1] dec_i0_br_immed_d, // Branch immediate\n input logic dec_i0_alu_decode_d, // Valid to X-stage ALU\n input logic dec_i0_branch_d, // Branch in D-stage\n input logic dec_i0_select_pc_d, // PC select to RS1\n input logic [31:1] dec_i0_pc_d, // Instruction PC\n input logic [3:0] dec_i0_rs1_bypass_en_d, // DEC bypass select 1 - X-stage, 0 - dec bypass data\n input logic [3:0] dec_i0_rs2_bypass_en_d, // DEC bypass select 1 - X-stage, 0 - dec bypass data\n input logic dec_csr_ren_d, // CSR read select\n input logic [31:0] dec_csr_rddata_d, // CSR read data\n\n input logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands\n input el2_mul_pkt_t mul_p, // DEC {valid, operand signs, low, operand bypass}\n input el2_div_pkt_t div_p, // DEC {valid, unsigned, rem}\n input logic dec_div_cancel, // Cancel the divide operation\n\n input logic [31:1] pred_correct_npc_x, // DEC NPC for correctly predicted branch\n\n input logic dec_tlu_flush_lower_r, // Flush divide and secondary ALUs\n input logic [31:1] dec_tlu_flush_path_r, // Redirect target\n\n\n input logic dec_extint_stall, // External stall mux select\n input logic [31:2] dec_tlu_meihap, // External stall mux data\n\n\n output logic [31:0] exu_lsu_rs1_d, // LSU operand\n output logic [31:0] exu_lsu_rs2_d, // LSU operand\n\n output logic exu_flush_final, // Pipe is being flushed this cycle\n output logic [31:1] exu_flush_path_final, // Target for the oldest flush source\n\n output logic [31:0] exu_i0_result_x, // Primary ALU result to DEC\n output logic [31:1] exu_i0_pc_x, // Primary PC result to DEC\n output logic [31:0] exu_csr_rs1_x, // RS1 source for a CSR instruction\n\n output logic [31:1] exu_npc_r, // Divide NPC\n output logic [1:0] exu_i0_br_hist_r, // to DEC I0 branch history\n output logic exu_i0_br_error_r, // to DEC I0 branch error\n output logic exu_i0_br_start_error_r, // to DEC I0 branch start error\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // to DEC I0 branch index\n output logic exu_i0_br_valid_r, // to DEC I0 branch valid\n output logic exu_i0_br_mp_r, // to DEC I0 branch mispredict\n output logic exu_i0_br_middle_r, // to DEC I0 branch middle\n output logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // to DEC I0 branch fghr\n output logic exu_i0_br_way_r, // to DEC I0 branch way\n\n output el2_predict_pkt_t exu_mp_pkt, // Mispredict branch packet\n output logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // Mispredict global history\n output logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index, // Mispredict index\n output logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag\n\n\n output logic exu_pmu_i0_br_misp, // to PMU - I0 E4 branch mispredict\n output logic exu_pmu_i0_br_ataken, // to PMU - I0 E4 taken\n output logic exu_pmu_i0_pc4, // to PMU - I0 E4 PC\n\n\n output logic [31:0] exu_div_result, // Divide result\n output logic exu_div_wren // Divide write enable to GPR\n );\n\n\n\n\n logic [31:0] i0_rs1_bypass_data_d;\n logic [31:0] i0_rs2_bypass_data_d;\n logic i0_rs1_bypass_en_d;\n logic i0_rs2_bypass_en_d;\n logic [31:0] i0_rs1_d, i0_rs2_d;\n logic [31:0] muldiv_rs1_d;\n logic [31:1] pred_correct_npc_r;\n logic i0_pred_correct_upper_r;\n logic [31:1] i0_flush_path_upper_r;\n logic x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;\n logic x_ctl_en, r_ctl_en;\n\n logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;\n logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;\n logic i0_taken_d;\n logic i0_taken_x;\n logic i0_valid_d;\n logic i0_valid_x;\n logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;\n\n el2_predict_pkt_t final_predict_mp;\n el2_predict_pkt_t i0_predict_newp_d;\n\n logic flush_in_d;\n logic [31:0] alu_result_x;\n\n logic mul_valid_x;\n logic [31:0] mul_result_x;\n\n el2_predict_pkt_t i0_pp_r;\n\n logic i0_flush_upper_d;\n logic [31:1] i0_flush_path_d;\n el2_predict_pkt_t i0_predict_p_d;\n logic i0_pred_correct_upper_d;\n\n logic i0_flush_upper_x;\n logic [31:1] i0_flush_path_x;\n el2_predict_pkt_t i0_predict_p_x;\n logic i0_pred_correct_upper_x;\n logic i0_branch_x;\n\n localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;\n logic [PREDPIPESIZE-1:0] predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;\n\n\n\n\n rvdffpcie #(31) i_flush_path_x_ff (.*, .clk(clk), .en ( x_data_en ), .din ( i0_flush_path_d[31:1] ), .dout( i0_flush_path_x[31:1] ) );\n rvdffe #(32) i_csr_rs1_x_ff (.*, .clk(clk), .en ( x_data_en_q1 ), .din ( i0_rs1_d[31:0] ), .dout( exu_csr_rs1_x[31:0] ) );\n rvdffppe #($bits(el2_predict_pkt_t)) i_predictpacket_x_ff (.*, .clk(clk), .en ( x_data_en ), .din ( i0_predict_p_d ), .dout( i0_predict_p_x ) );\n rvdffe #(PREDPIPESIZE) i_predpipe_x_ff (.*, .clk(clk), .en ( x_data_en_q2 ), .din ( predpipe_d ), .dout( predpipe_x ) );\n rvdffe #(PREDPIPESIZE) i_predpipe_r_ff (.*, .clk(clk), .en ( r_data_en_q2 ), .din ( predpipe_x ), .dout( predpipe_r ) );\n\n rvdffe #(4+pt.BHT_GHR_SIZE) i_x_ff (.*, .clk(clk), .en ( x_ctl_en ), .din ({i0_valid_d,i0_taken_d,i0_flush_upper_d,i0_pred_correct_upper_d,ghr_x_ns[pt.BHT_GHR_SIZE-1:0]} ),\n .dout({i0_valid_x,i0_taken_x,i0_flush_upper_x,i0_pred_correct_upper_x,ghr_x[pt.BHT_GHR_SIZE-1:0]} ) );\n\n rvdffppe #($bits(el2_predict_pkt_t)+1) i_r_ff0 (.*, .clk(clk), .en ( r_ctl_en ), .din ({i0_pred_correct_upper_x, i0_predict_p_x}),\n .dout({i0_pred_correct_upper_r, i0_pp_r }) );\n\n rvdffpcie #(31) i_flush_r_ff (.*, .clk(clk), .en ( r_data_en ), .din ( i0_flush_path_x[31:1] ), .dout( i0_flush_path_upper_r[31:1]) );\n rvdffpcie #(31) i_npc_r_ff (.*, .clk(clk), .en ( r_data_en ), .din ( pred_correct_npc_x[31:1] ), .dout( pred_correct_npc_r[31:1] ) );\n\n rvdffie #(pt.BHT_GHR_SIZE+2,1) i_misc_ff (.*, .clk(clk), .din ({ghr_d_ns[pt.BHT_GHR_SIZE-1:0], mul_p.valid, dec_i0_branch_d}),\n .dout({ghr_d[pt.BHT_GHR_SIZE-1:0] , mul_valid_x, i0_branch_x}) );\n\n\n\n\n\n assign predpipe_d[PREDPIPESIZE-1:0]\n = {i0_predict_fghr_d, i0_predict_index_d, i0_predict_btag_d};\n\n\n assign i0_rs1_bypass_en_d = dec_i0_rs1_bypass_en_d[0] | dec_i0_rs1_bypass_en_d[1] | dec_i0_rs1_bypass_en_d[2] | dec_i0_rs1_bypass_en_d[3];\n assign i0_rs2_bypass_en_d = dec_i0_rs2_bypass_en_d[0] | dec_i0_rs2_bypass_en_d[1] | dec_i0_rs2_bypass_en_d[2] | dec_i0_rs2_bypass_en_d[3];\n\n assign i0_rs1_bypass_data_d[31:0]=({32{dec_i0_rs1_bypass_en_d[0]}} & dec_i0_result_r[31:0] ) |\n ({32{dec_i0_rs1_bypass_en_d[1]}} & lsu_result_m[31:0] ) |\n ({32{dec_i0_rs1_bypass_en_d[2]}} & exu_i0_result_x[31:0] ) |\n ({32{dec_i0_rs1_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]);\n\n assign i0_rs2_bypass_data_d[31:0]=({32{dec_i0_rs2_bypass_en_d[0]}} & dec_i0_result_r[31:0] ) |\n ({32{dec_i0_rs2_bypass_en_d[1]}} & lsu_result_m[31:0] ) |\n ({32{dec_i0_rs2_bypass_en_d[2]}} & exu_i0_result_x[31:0] ) |\n ({32{dec_i0_rs2_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]);\n\n\n assign i0_rs1_d[31:0] = ({32{ i0_rs1_bypass_en_d }} & i0_rs1_bypass_data_d[31:0]) |\n ({32{~i0_rs1_bypass_en_d & dec_i0_select_pc_d }} & {dec_i0_pc_d[31:1],1'b0} ) | // for jal's\n ({32{~i0_rs1_bypass_en_d & dec_debug_wdata_rs1_d }} & dbg_cmd_wrdata[31:0] ) |\n ({32{~i0_rs1_bypass_en_d & ~dec_debug_wdata_rs1_d & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0] );\n\n assign i0_rs2_d[31:0] = ({32{~i0_rs2_bypass_en_d & dec_i0_rs2_en_d}} & gpr_i0_rs2_d[31:0] ) |\n ({32{~i0_rs2_bypass_en_d }} & dec_i0_immed_d[31:0] ) |\n ({32{ i0_rs2_bypass_en_d }} & i0_rs2_bypass_data_d[31:0]);\n\n\n assign exu_lsu_rs1_d[31:0] = ({32{~i0_rs1_bypass_en_d & ~dec_extint_stall & dec_i0_rs1_en_d & dec_qual_lsu_d}} & gpr_i0_rs1_d[31:0] ) |\n ({32{ i0_rs1_bypass_en_d & ~dec_extint_stall & dec_qual_lsu_d}} & i0_rs1_bypass_data_d[31:0]) |\n ({32{ dec_extint_stall & dec_qual_lsu_d}} & {dec_tlu_meihap[31:2],2'b0});\n\n assign exu_lsu_rs2_d[31:0] = ({32{~i0_rs2_bypass_en_d & ~dec_extint_stall & dec_i0_rs2_en_d & dec_qual_lsu_d}} & gpr_i0_rs2_d[31:0] ) |\n ({32{ i0_rs2_bypass_en_d & ~dec_extint_stall & dec_qual_lsu_d}} & i0_rs2_bypass_data_d[31:0]);\n\n\n assign muldiv_rs1_d[31:0] = ({32{~i0_rs1_bypass_en_d & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0] ) |\n ({32{ i0_rs1_bypass_en_d }} & i0_rs1_bypass_data_d[31:0]);\n\n\n assign x_data_en = dec_data_en[1];\n assign x_data_en_q1 = dec_data_en[1] & dec_csr_ren_d;\n assign x_data_en_q2 = dec_data_en[1] & dec_i0_branch_d;\n assign r_data_en = dec_data_en[0];\n assign r_data_en_q2 = dec_data_en[0] & i0_branch_x;\n assign x_ctl_en = dec_ctl_en[1];\n assign r_ctl_en = dec_ctl_en[0];\n\n\n\n\n el2_exu_alu_ctl #(.pt(pt)) i_alu (.*,\n .enable ( x_data_en ), // I\n .pp_in ( i0_predict_newp_d ), // I\n .valid_in ( dec_i0_alu_decode_d ), // I\n .flush_upper_x ( i0_flush_upper_x ), // I\n .flush_lower_r ( dec_tlu_flush_lower_r ), // I\n .a_in ( i0_rs1_d[31:0] ), // I\n .b_in ( i0_rs2_d[31:0] ), // I\n .pc_in ( dec_i0_pc_d[31:1] ), // I\n .brimm_in ( dec_i0_br_immed_d[12:1] ), // I\n .ap ( i0_ap ), // I\n .csr_ren_in ( dec_csr_ren_d ), // I\n .csr_rddata_in ( dec_csr_rddata_d[31:0] ), // I\n .result_ff ( alu_result_x[31:0] ), // O\n .flush_upper_out ( i0_flush_upper_d ), // O\n .flush_final_out ( exu_flush_final ), // O\n .flush_path_out ( i0_flush_path_d[31:1] ), // O\n .predict_p_out ( i0_predict_p_d ), // O\n .pred_correct_out ( i0_pred_correct_upper_d ), // O\n .pc_ff ( exu_i0_pc_x[31:1] )); // O\n\n\n\n el2_exu_mul_ctl #(.pt(pt)) i_mul (.*,\n .mul_p ( mul_p & {$bits(el2_mul_pkt_t){mul_p.valid}} ), // I\n .rs1_in ( muldiv_rs1_d[31:0] & {32{mul_p.valid}} ), // I\n .rs2_in ( i0_rs2_d[31:0] & {32{mul_p.valid}} ), // I\n .result_x ( mul_result_x[31:0] )); // O\n\n\n\n el2_exu_div_ctl #(.pt(pt)) i_div (.*,\n .cancel ( dec_div_cancel ), // I\n .dp ( div_p ), // I\n .dividend ( muldiv_rs1_d[31:0] ), // I\n .divisor ( i0_rs2_d[31:0] ), // I\n .finish_dly ( exu_div_wren ), // O\n .out ( exu_div_result[31:0] )); // O\n\n\n\n assign exu_i0_result_x[31:0] = (mul_valid_x) ? mul_result_x[31:0] : alu_result_x[31:0];\n\n\n\n\n always_comb begin\n i0_predict_newp_d = dec_i0_predict_p_d;\n i0_predict_newp_d.boffset = dec_i0_pc_d[1]; // from the start of inst\n end\n\n\n assign exu_pmu_i0_br_misp = i0_pp_r.misp;\n assign exu_pmu_i0_br_ataken = i0_pp_r.ataken;\n assign exu_pmu_i0_pc4 = i0_pp_r.pc4;\n\n\n assign i0_valid_d = i0_predict_p_d.valid & dec_i0_alu_decode_d & ~dec_tlu_flush_lower_r;\n assign i0_taken_d = (i0_predict_p_d.ataken & dec_i0_alu_decode_d);\n\nif(pt.BTB_ENABLE==1) begin\n // maintain GHR at D\n assign ghr_d_ns[pt.BHT_GHR_SIZE-1:0]\n = ({pt.BHT_GHR_SIZE{~dec_tlu_flush_lower_r & i0_valid_d}} & {ghr_d[pt.BHT_GHR_SIZE-2:0], i0_taken_d}) |\n ({pt.BHT_GHR_SIZE{~dec_tlu_flush_lower_r & ~i0_valid_d}} & ghr_d[pt.BHT_GHR_SIZE-1:0] ) |\n ({pt.BHT_GHR_SIZE{ dec_tlu_flush_lower_r }} & ghr_x[pt.BHT_GHR_SIZE-1:0] );\n\n // maintain GHR at X\n assign ghr_x_ns[pt.BHT_GHR_SIZE-1:0]\n = ({pt.BHT_GHR_SIZE{ i0_valid_x}} & {ghr_x[pt.BHT_GHR_SIZE-2:0], i0_taken_x}) |\n ({pt.BHT_GHR_SIZE{~i0_valid_x}} & ghr_x[pt.BHT_GHR_SIZE-1:0] ) ;\n\n\n assign exu_i0_br_valid_r = i0_pp_r.valid;\n assign exu_i0_br_mp_r = i0_pp_r.misp;\n assign exu_i0_br_way_r = i0_pp_r.way;\n assign exu_i0_br_hist_r[1:0] = {2{i0_pp_r.valid}} & i0_pp_r.hist[1:0];\n assign exu_i0_br_error_r = i0_pp_r.br_error;\n assign exu_i0_br_middle_r = i0_pp_r.pc4 ^ i0_pp_r.boffset;\n assign exu_i0_br_start_error_r = i0_pp_r.br_start_error;\n\n assign {exu_i0_br_fghr_r[pt.BHT_GHR_SIZE-1:0],\n exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]}= predpipe_r[PREDPIPESIZE-1:pt.BTB_BTAG_SIZE];\n\n\n assign final_predict_mp = (i0_flush_upper_x) ? i0_predict_p_x : '0;\n\n assign final_predpipe_mp[PREDPIPESIZE-1:0] = (i0_flush_upper_x) ? predpipe_x : '0;\n\n assign after_flush_eghr[pt.BHT_GHR_SIZE-1:0] = (i0_flush_upper_x & ~dec_tlu_flush_lower_r) ? ghr_d[pt.BHT_GHR_SIZE-1:0] : ghr_x[pt.BHT_GHR_SIZE-1:0];\n\n\n assign exu_mp_pkt.valid = final_predict_mp.valid;\n assign exu_mp_pkt.way = final_predict_mp.way;\n assign exu_mp_pkt.misp = final_predict_mp.misp;\n assign exu_mp_pkt.pcall = final_predict_mp.pcall;\n assign exu_mp_pkt.pja = final_predict_mp.pja;\n assign exu_mp_pkt.pret = final_predict_mp.pret;\n assign exu_mp_pkt.ataken = final_predict_mp.ataken;\n assign exu_mp_pkt.boffset = final_predict_mp.boffset;\n assign exu_mp_pkt.pc4 = final_predict_mp.pc4;\n assign exu_mp_pkt.hist[1:0] = final_predict_mp.hist[1:0];\n assign exu_mp_pkt.toffset[11:0] = final_predict_mp.toffset[11:0];\n assign exu_mp_pkt.br_error = '0;\n assign exu_mp_pkt.br_start_error = '0;\n\n assign exu_mp_fghr[pt.BHT_GHR_SIZE-1:0] = after_flush_eghr[pt.BHT_GHR_SIZE-1:0];\n\n assign {exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],\n exu_mp_btag[pt.BTB_BTAG_SIZE-1:0]} = final_predpipe_mp[PREDPIPESIZE-pt.BHT_GHR_SIZE-1:0];\n\n assign exu_mp_eghr[pt.BHT_GHR_SIZE-1:0] = final_predpipe_mp[PREDPIPESIZE-1:pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+pt.BTB_BTAG_SIZE+1]; // mp ghr for bht write\nend // if (pt.BTB_ENABLE==1)\nelse begin\n assign ghr_d_ns = '0;\n assign ghr_x_ns = '0;\n assign exu_mp_pkt = '0;\n assign exu_mp_eghr = '0;\n assign exu_mp_fghr = '0;\n assign exu_mp_index = '0;\n assign exu_mp_btag = '0;\n assign exu_i0_br_hist_r = '0;\n assign exu_i0_br_error_r = '0;\n assign exu_i0_br_start_error_r = '0;\n assign exu_i0_br_index_r = '0;\n assign exu_i0_br_valid_r = '0;\n assign exu_i0_br_mp_r = '0;\n assign exu_i0_br_middle_r = '0;\n assign exu_i0_br_fghr_r = '0;\n assign exu_i0_br_way_r = '0;\nend // else: !if(pt.BTB_ENABLE==1)\n\n assign exu_flush_path_final[31:1] = ( {31{ dec_tlu_flush_lower_r }} & dec_tlu_flush_path_r[31:1] ) |\n ( {31{~dec_tlu_flush_lower_r & i0_flush_upper_d}} & i0_flush_path_d[31:1] );\n\n assign exu_npc_r[31:1] = (i0_pred_correct_upper_r) ? pred_correct_npc_r[31:1] : i0_flush_path_upper_r[31:1];\n\n\nendmodule // el2_exu\n" }, { "path": "design/exu/el2_exu_alu_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n\nmodule el2_exu_alu_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n)\n (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Scan control\n /*pragma coverage on*/\n\n input logic flush_upper_x, // Branch flush from previous cycle\n input logic flush_lower_r, // Master flush of entire pipeline\n input logic enable, // Clock enable\n input logic valid_in, // Valid\n input el2_alu_pkt_t ap, // predecodes\n input logic csr_ren_in, // CSR select\n input logic [31:0] csr_rddata_in, // CSR data\n input logic signed [31:0] a_in, // A operand\n input logic [31:0] b_in, // B operand\n input logic [31:1] pc_in, // for pc=pc+2,4 calculations\n input el2_predict_pkt_t pp_in, // Predicted branch structure\n input logic [12:1] brimm_in, // Branch offset\n\n\n output logic [31:0] result_ff, // final result\n output logic flush_upper_out, // Branch flush\n output logic flush_final_out, // Branch flush or flush entire pipeline\n output logic [31:1] flush_path_out, // Branch flush PC\n output logic [31:1] pc_ff, // flopped PC\n output logic pred_correct_out, // NPC control\n output el2_predict_pkt_t predict_p_out // Predicted branch structure\n );\n\n\n logic [31:0] zba_a_in;\n logic [31:0] aout;\n logic cout,ov,neg;\n logic [31:0] lout;\n logic [31:0] sout;\n logic sel_shift;\n logic sel_adder;\n logic slt_one;\n logic actual_taken;\n logic [31:1] pcout;\n logic cond_mispredict;\n logic target_mispredict;\n logic eq, ne, lt, ge;\n logic any_jal;\n logic [1:0] newhist;\n logic sel_pc;\n logic [31:0] csr_write_data;\n logic [31:0] result;\n\n\n\n\n // *** Start - BitManip ***\n\n // Zbb\n logic ap_clz;\n logic ap_ctz;\n logic ap_cpop;\n logic ap_sext_b;\n logic ap_sext_h;\n logic ap_min;\n logic ap_max;\n logic ap_rol;\n logic ap_ror;\n logic ap_rev8;\n logic ap_orc_b;\n logic ap_zbb;\n\n // Zbs\n logic ap_bset;\n logic ap_bclr;\n logic ap_binv;\n logic ap_bext;\n\n // Zbp\n logic ap_pack;\n logic ap_packu;\n logic ap_packh;\n\n // Zba\n logic ap_sh1add;\n logic ap_sh2add;\n logic ap_sh3add;\n logic ap_zba;\n\n\n\n if (pt.BITMANIP_ZBB == 1)\n begin\n assign ap_clz = ap.clz;\n assign ap_ctz = ap.ctz;\n assign ap_cpop = ap.cpop;\n assign ap_sext_b = ap.sext_b;\n assign ap_sext_h = ap.sext_h;\n assign ap_min = ap.min;\n assign ap_max = ap.max;\n end\n else\n begin\n assign ap_clz = 1'b0;\n assign ap_ctz = 1'b0;\n assign ap_cpop = 1'b0;\n assign ap_sext_b = 1'b0;\n assign ap_sext_h = 1'b0;\n assign ap_min = 1'b0;\n assign ap_max = 1'b0;\n end\n\n\n if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) )\n begin\n assign ap_rol = ap.rol;\n assign ap_ror = ap.ror;\n assign ap_rev8 = ap.grev & (b_in[4:0] == 5'b11000);\n assign ap_orc_b = ap.gorc & (b_in[4:0] == 5'b00111);\n assign ap_zbb = ap.zbb;\n end\n else\n begin\n assign ap_rol = 1'b0;\n assign ap_ror = 1'b0;\n assign ap_rev8 = 1'b0;\n assign ap_orc_b = 1'b0;\n assign ap_zbb = 1'b0;\n end\n\n\n if (pt.BITMANIP_ZBS == 1)\n begin\n assign ap_bset = ap.bset;\n assign ap_bclr = ap.bclr;\n assign ap_binv = ap.binv;\n assign ap_bext = ap.bext;\n end\n else\n begin\n assign ap_bset = 1'b0;\n assign ap_bclr = 1'b0;\n assign ap_binv = 1'b0;\n assign ap_bext = 1'b0;\n end\n\n\n if (pt.BITMANIP_ZBP == 1)\n begin\n assign ap_packu = ap.packu;\n end\n else\n begin\n assign ap_packu = 1'b0;\n end\n\n\n if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) | (pt.BITMANIP_ZBE == 1) | (pt.BITMANIP_ZBF == 1) )\n begin\n assign ap_pack = ap.pack;\n assign ap_packh = ap.packh;\n end\n else\n begin\n assign ap_pack = 1'b0;\n assign ap_packh = 1'b0;\n end\n\n\n if (pt.BITMANIP_ZBA == 1)\n begin\n assign ap_sh1add = ap.sh1add;\n assign ap_sh2add = ap.sh2add;\n assign ap_sh3add = ap.sh3add;\n assign ap_zba = ap.zba;\n end\n else\n begin\n assign ap_sh1add = 1'b0;\n assign ap_sh2add = 1'b0;\n assign ap_sh3add = 1'b0;\n assign ap_zba = 1'b0;\n end\n\n\n\n\n // *** End - BitManip ***\n\n\n\n\n rvdffpcie #(31) i_pc_ff (.*, .clk(clk), .en(enable), .din(pc_in[31:1]), .dout(pc_ff[31:1])); // any PC is run through here - doesn't have to be alu\n rvdffe #(32) i_result_ff (.*, .clk(clk), .en(enable & valid_in), .din(result[31:0]), .dout(result_ff[31:0]));\n\n\n\n // immediates are just muxed into rs2\n\n // add => add=1;\n // sub => add=1; sub=1;\n\n // and => lctl=3\n // or => lctl=2\n // xor => lctl=1\n\n // sll => sctl=3\n // srl => sctl=2\n // sra => sctl=1\n\n // slt => slt\n\n // lui => lctl=2; or x0, imm20 previously << 12\n // auipc => add; add pc, imm20 previously << 12\n\n // beq => bctl=4; add; add x0, pc, sext(offset[12:1])\n // bne => bctl=3; add; add x0, pc, sext(offset[12:1])\n // blt => bctl=2; add; add x0, pc, sext(offset[12:1])\n // bge => bctl=1; add; add x0, pc, sext(offset[12:1])\n\n // jal => rs1=pc {pc[31:1],1'b0}, rs2=sext(offset20:1]); rd=pc+[2,4]\n // jalr => rs1=rs1, rs2=sext(offset20:1]); rd=pc+[2,4]\n\n\n\n assign zba_a_in[31:0] = ( {32{ ap_sh1add}} & {a_in[30:0],1'b0} ) |\n ( {32{ ap_sh2add}} & {a_in[29:0],2'b0} ) |\n ( {32{ ap_sh3add}} & {a_in[28:0],3'b0} ) |\n ( {32{~ap_zba }} & a_in[31:0] );\n\n logic [31:0] bm;\n\n assign bm[31:0] = ( ap.sub ) ? ~b_in[31:0] : b_in[31:0];\n\n assign {cout, aout[31:0]} = {1'b0, zba_a_in[31:0]} + {1'b0, bm[31:0]} + {32'b0, ap.sub};\n\n assign ov = (~a_in[31] & ~bm[31] & aout[31]) |\n ( a_in[31] & bm[31] & ~aout[31] );\n\n assign lt = (~ap.unsign & (neg ^ ov)) |\n ( ap.unsign & ~cout);\n\n assign eq = (a_in[31:0] == b_in[31:0]);\n assign ne = ~eq;\n assign neg = aout[31];\n assign ge = ~lt;\n\n\n\n assign lout[31:0] = ( {32{csr_ren_in }} & csr_rddata_in[31:0] ) |\n ( {32{ap.land & ~ap_zbb}} & a_in[31:0] & b_in[31:0] ) |\n ( {32{ap.lor & ~ap_zbb}} & (a_in[31:0] | b_in[31:0]) ) |\n ( {32{ap.lxor & ~ap_zbb}} & (a_in[31:0] ^ b_in[31:0]) ) |\n ( {32{ap.land & ap_zbb}} & a_in[31:0] & ~b_in[31:0] ) |\n ( {32{ap.lor & ap_zbb}} & (a_in[31:0] | ~b_in[31:0]) ) |\n ( {32{ap.lxor & ap_zbb}} & (a_in[31:0] ^ ~b_in[31:0]) );\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : ROL,ROR * * * * * * * * * * * * * * * * * *\n // * * * * * * * * * * * * * * * * * * BitManip : ZBEXT * * * * * * * * * * * * * * * * * *\n\n logic [5:0] shift_amount;\n logic [31:0] shift_mask;\n logic [62:0] shift_extend;\n logic [62:0] shift_long;\n\n\n assign shift_amount[5:0] = ( { 6{ap.sll}} & (6'd32 - {1'b0,b_in[4:0]}) ) | // [5] unused\n ( { 6{ap.srl}} & {1'b0,b_in[4:0]} ) |\n ( { 6{ap.sra}} & {1'b0,b_in[4:0]} ) |\n ( { 6{ap_rol}} & (6'd32 - {1'b0,b_in[4:0]}) ) |\n ( { 6{ap_ror}} & {1'b0,b_in[4:0]} ) |\n ( { 6{ap_bext}} & {1'b0,b_in[4:0]} );\n\n\n assign shift_mask[31:0] = ( 32'hffffffff << ({5{ap.sll}} & b_in[4:0]) );\n\n\n assign shift_extend[31:0] = a_in[31:0];\n\n assign shift_extend[62:32] = ( {31{ap.sra}} & {31{a_in[31]}} ) |\n ( {31{ap.sll}} & a_in[30:0] ) |\n ( {31{ap_rol}} & a_in[30:0] ) |\n ( {31{ap_ror}} & a_in[30:0] );\n\n\n assign shift_long[62:0] = 63'( shift_extend[62:0] >> shift_amount[4:0] ); // 62-32 unused\n\n assign sout[31:0] = shift_long[31:0] & shift_mask[31:0];\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : CLZ,CTZ * * * * * * * * * * * * * * * * * *\n\n logic bitmanip_clz_ctz_sel;\n logic [31:0] bitmanip_a_reverse_ff;\n logic [31:0] bitmanip_lzd_in;\n logic [5:0] bitmanip_dw_lzd_enc;\n logic [5:0] bitmanip_clz_ctz_result;\n\n assign bitmanip_clz_ctz_sel = ap_clz | ap_ctz;\n\n assign bitmanip_a_reverse_ff[31:0] = {a_in[0], a_in[1], a_in[2], a_in[3], a_in[4], a_in[5], a_in[6], a_in[7],\n a_in[8], a_in[9], a_in[10], a_in[11], a_in[12], a_in[13], a_in[14], a_in[15],\n a_in[16], a_in[17], a_in[18], a_in[19], a_in[20], a_in[21], a_in[22], a_in[23],\n a_in[24], a_in[25], a_in[26], a_in[27], a_in[28], a_in[29], a_in[30], a_in[31]};\n\n assign bitmanip_lzd_in[31:0] = ( {32{ap_clz}} & a_in[31:0] ) |\n ( {32{ap_ctz}} & bitmanip_a_reverse_ff[31:0]);\n\n logic [31:0] bitmanip_lzd_os;\n integer i;\n logic found;\n\n always_comb\n begin\n bitmanip_lzd_os[31:0] = bitmanip_lzd_in[31:0];\n bitmanip_dw_lzd_enc[5:0]= 6'b0;\n found = 1'b0;\n\n for (int i=0; i<32; i++) begin\n if (bitmanip_lzd_os[31] == 1'b0 && found == 0) begin\n bitmanip_dw_lzd_enc[5:0]= bitmanip_dw_lzd_enc[5:0] + 6'b00_0001;\n bitmanip_lzd_os[31:0] = bitmanip_lzd_os[31:0] << 1;\n end\n else\n found=1'b1;\n end\n end\n\n\n\n assign bitmanip_clz_ctz_result[5:0] = {6{bitmanip_clz_ctz_sel}} & {bitmanip_dw_lzd_enc[5],( {5{~bitmanip_dw_lzd_enc[5]}} & bitmanip_dw_lzd_enc[4:0] )};\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : CPOP * * * * * * * * * * * * * * * * * *\n\n logic [5:0] bitmanip_cpop;\n logic [5:0] bitmanip_cpop_result;\n\n\n integer bitmanip_cpop_i;\n\n always_comb\n begin\n bitmanip_cpop[5:0] = 6'b0;\n\n for (bitmanip_cpop_i=0; bitmanip_cpop_i<32; bitmanip_cpop_i++)\n begin\n bitmanip_cpop[5:0] = bitmanip_cpop[5:0] + {5'b0,a_in[bitmanip_cpop_i]};\n end // FOR bitmanip_cpop_i\n end // ALWAYS_COMB\n\n\n assign bitmanip_cpop_result[5:0] = {6{ap_cpop}} & bitmanip_cpop[5:0];\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : SEXT_B,SEXT_H * * * * * * * * * * * * * * * * *\n\n logic [31:0] bitmanip_sext_result;\n\n assign bitmanip_sext_result[31:0] = ( {32{ap_sext_b}} & { {24{a_in[7]}} ,a_in[7:0] } ) |\n ( {32{ap_sext_h}} & { {16{a_in[15]}},a_in[15:0] } );\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : MIN,MAX,MINU,MAXU * * * * * * * * * * * * * * *\n\n logic bitmanip_minmax_sel;\n logic [31:0] bitmanip_minmax_result;\n\n assign bitmanip_minmax_sel = ap_min | ap_max;\n\n logic bitmanip_minmax_sel_a;\n\n assign bitmanip_minmax_sel_a = ge ^ ap_min;\n\n assign bitmanip_minmax_result[31:0] = ({32{bitmanip_minmax_sel & bitmanip_minmax_sel_a}} & a_in[31:0]) |\n ({32{bitmanip_minmax_sel & ~bitmanip_minmax_sel_a}} & b_in[31:0]);\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : PACK, PACKU, PACKH * * * * * * * * * * * * * * *\n\n logic [31:0] bitmanip_pack_result;\n logic [31:0] bitmanip_packu_result;\n logic [31:0] bitmanip_packh_result;\n\n assign bitmanip_pack_result[31:0] = {32{ap_pack}} & {b_in[15:0], a_in[15:0]};\n assign bitmanip_packu_result[31:0] = {32{ap_packu}} & {b_in[31:16],a_in[31:16]};\n assign bitmanip_packh_result[31:0] = {32{ap_packh}} & {16'b0,b_in[7:0],a_in[7:0]};\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : REV, ORC_B * * * * * * * * * * * * * * * * * *\n\n logic [31:0] bitmanip_rev8_result;\n logic [31:0] bitmanip_orc_b_result;\n\n assign bitmanip_rev8_result[31:0] = {32{ap_rev8}} & {a_in[7:0],a_in[15:8],a_in[23:16],a_in[31:24]};\n\n\n// uint32_t gorc32(uint32_t rs1, uint32_t rs2)\n// {\n// uint32_t x = rs1;\n// int shamt = rs2 & 31; ORC.B ORC16\n// if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1); 1 0\n// if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2); 1 0\n// if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4); 1 0\n// if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8); 0 0\n// if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16); 0 1\n// return x;\n// }\n\n\n// BEFORE 31 , 30 , 29 , 28 , 27 , 26, 25, 24\n// shamt[0] b = a31|a30,a31|a30,a29|a28,a29|a28, a27|a26,a27|a26,a25|a24,a25|a24\n// shamt[1] c = b31|b29,b30|b28,b31|b29,b30|b28, b27|b25,b26|b24,b27|b25,b26|b24\n// shamt[2] d = c31|c27,c30|c26,c29|c25,c28|c24, c31|c27,c30|c26,c29|c25,c28|c24\n//\n// Expand d31 = c31 | c27;\n// = b31 | b29 | b27 | b25;\n// = a31|a30 | a29|a28 | a27|a26 | a25|a24\n\n assign bitmanip_orc_b_result[31:0] = {32{ap_orc_b}} & { {8{| a_in[31:24]}}, {8{| a_in[23:16]}}, {8{| a_in[15:8]}}, {8{| a_in[7:0]}} };\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : ZBSET, ZBCLR, ZBINV * * * * * * * * * * * * * *\n\n logic [31:0] bitmanip_sb_1hot;\n logic [31:0] bitmanip_sb_data;\n\n assign bitmanip_sb_1hot[31:0] = ( 32'h00000001 << b_in[4:0] );\n\n assign bitmanip_sb_data[31:0] = ( {32{ap_bset}} & ( a_in[31:0] | bitmanip_sb_1hot[31:0]) ) |\n ( {32{ap_bclr}} & ( a_in[31:0] & ~bitmanip_sb_1hot[31:0]) ) |\n ( {32{ap_binv}} & ( a_in[31:0] ^ bitmanip_sb_1hot[31:0]) );\n\n\n\n\n\n\n assign sel_shift = ap.sll | ap.srl | ap.sra | ap_rol | ap_ror;\n assign sel_adder = (ap.add | ap.sub | ap_zba) & ~ap.slt & ~ap_min & ~ap_max;\n assign sel_pc = ap.jal | pp_in.pcall | pp_in.pja | pp_in.pret;\n assign csr_write_data[31:0]= (ap.csr_imm) ? b_in[31:0] : a_in[31:0];\n\n assign slt_one = ap.slt & lt;\n\n\n\n assign result[31:0] = lout[31:0] |\n ({32{sel_shift}} & sout[31:0] ) |\n ({32{sel_adder}} & aout[31:0] ) |\n ({32{sel_pc}} & {pcout[31:1],1'b0} ) |\n ({32{ap.csr_write}} & csr_write_data[31:0] ) |\n {31'b0, slt_one} |\n ({32{ap_bext}} & {31'b0, sout[0]} ) |\n {26'b0, bitmanip_clz_ctz_result[5:0]} |\n {26'b0, bitmanip_cpop_result[5:0]} |\n bitmanip_sext_result[31:0] |\n bitmanip_minmax_result[31:0] |\n bitmanip_pack_result[31:0] |\n bitmanip_packu_result[31:0] |\n bitmanip_packh_result[31:0] |\n bitmanip_rev8_result[31:0] |\n bitmanip_orc_b_result[31:0] |\n bitmanip_sb_data[31:0];\n\n\n\n // *** branch handling ***\n\n assign any_jal = ap.jal |\n pp_in.pcall |\n pp_in.pja |\n pp_in.pret;\n\n assign actual_taken = (ap.beq & eq) |\n (ap.bne & ne) |\n (ap.blt & lt) |\n (ap.bge & ge) |\n any_jal;\n\n // for a conditional br pcout[] will be the opposite of the branch prediction\n // for jal or pcall, it will be the link address pc+2 or pc+4\n\n rvbradder ibradder (\n .pc ( pc_in[31:1] ),\n .offset ( brimm_in[12:1] ),\n .dout ( pcout[31:1] ));\n\n\n // pred_correct is for the npc logic\n // pred_correct indicates not to use the flush_path\n // for any_jal pred_correct==0\n\n assign pred_correct_out = (valid_in & ap.predict_nt & ~actual_taken & ~any_jal) |\n (valid_in & ap.predict_t & actual_taken & ~any_jal);\n\n\n // for any_jal adder output is the flush path\n assign flush_path_out[31:1]= (any_jal) ? aout[31:1] : pcout[31:1];\n\n\n // pcall and pret are included here\n assign cond_mispredict = (ap.predict_t & ~actual_taken) |\n (ap.predict_nt & actual_taken);\n\n\n // target mispredicts on ret's\n\n assign target_mispredict = pp_in.pret & (pp_in.prett[31:1] != aout[31:1]);\n\n assign flush_upper_out = (ap.jal | cond_mispredict | target_mispredict) & valid_in & ~flush_upper_x & ~flush_lower_r;\n assign flush_final_out = ( (ap.jal | cond_mispredict | target_mispredict) & valid_in & ~flush_upper_x ) | flush_lower_r;\n\n\n // .i 3\n // .o 2\n // .ilb hist[1] hist[0] taken\n // .ob newhist[1] newhist[0]\n // .type fd\n //\n // 00 0 01\n // 01 0 01\n // 10 0 00\n // 11 0 10\n // 00 1 10\n // 01 1 00\n // 10 1 11\n // 11 1 11\n\n assign newhist[1] = ( pp_in.hist[1] & pp_in.hist[0]) | (~pp_in.hist[0] & actual_taken);\n assign newhist[0] = (~pp_in.hist[1] & ~actual_taken) | ( pp_in.hist[1] & actual_taken);\n\n always_comb begin\n predict_p_out = pp_in;\n\n predict_p_out.misp = ~flush_upper_x & ~flush_lower_r & (cond_mispredict | target_mispredict);\n predict_p_out.ataken = actual_taken;\n predict_p_out.hist[1] = newhist[1];\n predict_p_out.hist[0] = newhist[0];\n\n end\n\n\n\nendmodule // el2_exu_alu_ctl\n" }, { "path": "design/exu/el2_exu_div_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n\nmodule el2_exu_div_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n)\n (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Scan mode\n /*pragma coverage on*/\n\n input el2_div_pkt_t dp, // valid, sign, rem\n input logic [31:0] dividend, // Numerator\n input logic [31:0] divisor, // Denominator\n\n input logic cancel, // Cancel divide\n\n\n output logic finish_dly, // Finish to match data\n output logic [31:0] out // Result\n );\n\n\n logic [31:0] out_raw;\n\n assign out[31:0] = {32{finish_dly}} & out_raw[31:0]; // Qualification added to quiet result bus while divide is iterating\n\n\n\n if (pt.DIV_NEW == 0)\n begin : genblock1\n el2_exu_div_existing_1bit_cheapshortq i_existing_1bit_div_cheapshortq (\n .clk ( clk ), // I\n .rst_l ( rst_l ), // I\n .scan_mode ( scan_mode ), // I\n .cancel ( cancel ), // I\n .valid_in ( dp.valid ), // I\n .signed_in (~dp.unsign ), // I\n .rem_in ( dp.rem ), // I\n .dividend_in ( dividend[31:0] ), // I\n .divisor_in ( divisor[31:0] ), // I\n .valid_out ( finish_dly ), // O\n .data_out ( out_raw[31:0] )); // O\n end\n\n\n if ( (pt.DIV_NEW == 1) & (pt.DIV_BIT == 1) )\n begin : genblock2\n el2_exu_div_new_1bit_fullshortq i_new_1bit_div_fullshortq (\n .clk ( clk ), // I\n .rst_l ( rst_l ), // I\n .scan_mode ( scan_mode ), // I\n .cancel ( cancel ), // I\n .valid_in ( dp.valid ), // I\n .signed_in (~dp.unsign ), // I\n .rem_in ( dp.rem ), // I\n .dividend_in ( dividend[31:0] ), // I\n .divisor_in ( divisor[31:0] ), // I\n .valid_out ( finish_dly ), // O\n .data_out ( out_raw[31:0] )); // O\n end\n\n\n if ( (pt.DIV_NEW == 1) & (pt.DIV_BIT == 2) )\n begin : genblock3\n el2_exu_div_new_2bit_fullshortq i_new_2bit_div_fullshortq (\n .clk ( clk ), // I\n .rst_l ( rst_l ), // I\n .scan_mode ( scan_mode ), // I\n .cancel ( cancel ), // I\n .valid_in ( dp.valid ), // I\n .signed_in (~dp.unsign ), // I\n .rem_in ( dp.rem ), // I\n .dividend_in ( dividend[31:0] ), // I\n .divisor_in ( divisor[31:0] ), // I\n .valid_out ( finish_dly ), // O\n .data_out ( out_raw[31:0] )); // O\n end\n\n\n if ( (pt.DIV_NEW == 1) & (pt.DIV_BIT == 3) )\n begin : genblock4\n el2_exu_div_new_3bit_fullshortq i_new_3bit_div_fullshortq (\n .clk ( clk ), // I\n .rst_l ( rst_l ), // I\n .scan_mode ( scan_mode ), // I\n .cancel ( cancel ), // I\n .valid_in ( dp.valid ), // I\n .signed_in (~dp.unsign ), // I\n .rem_in ( dp.rem ), // I\n .dividend_in ( dividend[31:0] ), // I\n .divisor_in ( divisor[31:0] ), // I\n .valid_out ( finish_dly ), // O\n .data_out ( out_raw[31:0] )); // O\n end\n\n\n if ( (pt.DIV_NEW == 1) & (pt.DIV_BIT == 4) )\n begin : genblock5\n el2_exu_div_new_4bit_fullshortq i_new_4bit_div_fullshortq (\n .clk ( clk ), // I\n .rst_l ( rst_l ), // I\n .scan_mode ( scan_mode ), // I\n .cancel ( cancel ), // I\n .valid_in ( dp.valid ), // I\n .signed_in (~dp.unsign ), // I\n .rem_in ( dp.rem ), // I\n .dividend_in ( dividend[31:0] ), // I\n .divisor_in ( divisor[31:0] ), // I\n .valid_out ( finish_dly ), // O\n .data_out ( out_raw[31:0] )); // O\n end\n\n\n\nendmodule // el2_exu_div_ctl\n\n\n\n\n\n\n// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\nmodule el2_exu_div_existing_1bit_cheapshortq\n (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Scan mode\n /*pragma coverage on*/\n\n input logic cancel, // Flush pipeline\n input logic valid_in,\n input logic signed_in,\n input logic rem_in,\n input logic [31:0] dividend_in,\n input logic [31:0] divisor_in,\n\n output logic valid_out,\n output logic [31:0] data_out\n );\n\n\n logic div_clken;\n logic run_in, run_state;\n logic [5:0] count_in, count;\n logic [32:0] m_ff;\n logic qff_enable;\n logic aff_enable;\n logic [32:0] q_in, q_ff;\n logic [32:0] a_in, a_ff;\n logic [32:0] m_eff;\n logic [32:0] a_shift;\n logic dividend_neg_ff, divisor_neg_ff;\n logic [31:0] dividend_comp;\n logic [31:0] dividend_eff;\n logic [31:0] q_ff_comp;\n logic [31:0] q_ff_eff;\n logic [31:0] a_ff_comp;\n logic [31:0] a_ff_eff;\n logic sign_ff, sign_eff;\n logic rem_ff;\n logic add;\n logic [32:0] a_eff;\n logic [64:0] a_eff_shift;\n logic rem_correct;\n logic valid_ff_x;\n logic valid_x;\n logic finish;\n logic finish_ff;\n\n logic smallnum_case, smallnum_case_ff;\n logic [3:0] smallnum, smallnum_ff;\n logic m_already_comp;\n\n logic [4:0] a_cls;\n logic [4:0] b_cls;\n logic [5:0] shortq_shift;\n logic [5:0] shortq_shift_ff;\n logic [5:0] shortq;\n logic shortq_enable;\n logic shortq_enable_ff;\n logic [32:0] short_dividend;\n logic [3:0] shortq_raw;\n logic [3:0] shortq_shift_xx;\n\n\n\n rvdffe #(23) i_misc_ff (.*, .clk(clk), .en(div_clken), .din ({valid_in & ~cancel,\n finish & ~cancel,\n run_in,\n count_in[5:0],\n (valid_in & dividend_in[31]) | (~valid_in & dividend_neg_ff),\n (valid_in & divisor_in[31] ) | (~valid_in & divisor_neg_ff ),\n (valid_in & sign_eff ) | (~valid_in & sign_ff ),\n (valid_in & rem_in ) | (~valid_in & rem_ff ),\n smallnum_case,\n smallnum[3:0],\n shortq_enable,\n shortq_shift[3:0]}),\n\n .dout({valid_ff_x,\n finish_ff,\n run_state,\n count[5:0],\n dividend_neg_ff,\n divisor_neg_ff,\n sign_ff,\n rem_ff,\n smallnum_case_ff,\n smallnum_ff[3:0],\n shortq_enable_ff,\n shortq_shift_xx[3:0]}));\n\n\n rvdffe #(33) mff (.*, .clk(clk), .en(valid_in), .din({signed_in & divisor_in[31], divisor_in[31:0]}), .dout(m_ff[32:0]));\n rvdffe #(33) qff (.*, .clk(clk), .en(qff_enable), .din(q_in[32:0]), .dout(q_ff[32:0]));\n rvdffe #(33) aff (.*, .clk(clk), .en(aff_enable), .din(a_in[32:0]), .dout(a_ff[32:0]));\n\n rvtwoscomp #(32) i_dividend_comp (.din(q_ff[31:0]), .dout(dividend_comp[31:0]));\n rvtwoscomp #(32) i_q_ff_comp (.din(q_ff[31:0]), .dout(q_ff_comp[31:0]));\n rvtwoscomp #(32) i_a_ff_comp (.din(a_ff[31:0]), .dout(a_ff_comp[31:0]));\n\n\n assign valid_x = valid_ff_x & ~cancel;\n\n\n // START - short circuit logic for small numbers {{\n\n // small number divides - any 4b / 4b is done in 1 cycle (divisor != 0)\n // to generate espresso equations:\n // 1. smalldiv > smalldiv.e\n // 2. espresso -Dso -oeqntott smalldiv.e | addassign > smalldiv\n\n // smallnum case does not cover divide by 0\n assign smallnum_case = ((q_ff[31:4] == 28'b0) & (m_ff[31:4] == 28'b0) & (m_ff[31:0] != 32'b0) & ~rem_ff & valid_x) |\n ((q_ff[31:0] == 32'b0) & (m_ff[31:0] != 32'b0) & ~rem_ff & valid_x);\n\n\n assign smallnum[3] = ( q_ff[3] & ~m_ff[3] & ~m_ff[2] & ~m_ff[1] );\n\n\n assign smallnum[2] = ( q_ff[3] & ~m_ff[3] & ~m_ff[2] & ~m_ff[0]) |\n ( q_ff[2] & ~m_ff[3] & ~m_ff[2] & ~m_ff[1] ) |\n ( q_ff[3] & q_ff[2] & ~m_ff[3] & ~m_ff[2] );\n\n\n assign smallnum[1] = ( q_ff[2] & ~m_ff[3] & ~m_ff[2] & ~m_ff[0]) |\n ( q_ff[1] & ~m_ff[3] & ~m_ff[2] & ~m_ff[1] ) |\n ( q_ff[3] & ~m_ff[3] & ~m_ff[1] & ~m_ff[0]) |\n ( q_ff[3] & ~q_ff[2] & ~m_ff[3] & ~m_ff[2] & m_ff[1] & m_ff[0]) |\n (~q_ff[3] & q_ff[2] & q_ff[1] & ~m_ff[3] & ~m_ff[2] ) |\n ( q_ff[3] & q_ff[2] & ~m_ff[3] & ~m_ff[0]) |\n ( q_ff[3] & q_ff[2] & ~m_ff[3] & m_ff[2] & ~m_ff[1] ) |\n ( q_ff[3] & q_ff[1] & ~m_ff[3] & ~m_ff[1] ) |\n ( q_ff[3] & q_ff[2] & q_ff[1] & ~m_ff[3] & m_ff[2] );\n\n\n assign smallnum[0] = ( q_ff[2] & q_ff[1] & q_ff[0] & ~m_ff[3] & ~m_ff[1] ) |\n ( q_ff[3] & ~q_ff[2] & q_ff[0] & ~m_ff[3] & m_ff[1] & m_ff[0]) |\n ( q_ff[2] & ~m_ff[3] & ~m_ff[1] & ~m_ff[0]) |\n ( q_ff[1] & ~m_ff[3] & ~m_ff[2] & ~m_ff[0]) |\n ( q_ff[0] & ~m_ff[3] & ~m_ff[2] & ~m_ff[1] ) |\n (~q_ff[3] & q_ff[2] & ~q_ff[1] & ~m_ff[3] & ~m_ff[2] & m_ff[1] & m_ff[0]) |\n (~q_ff[3] & q_ff[2] & q_ff[1] & ~m_ff[3] & ~m_ff[0]) |\n ( q_ff[3] & ~m_ff[2] & ~m_ff[1] & ~m_ff[0]) |\n ( q_ff[3] & ~q_ff[2] & ~m_ff[3] & m_ff[2] & m_ff[1] ) |\n (~q_ff[3] & q_ff[2] & q_ff[1] & ~m_ff[3] & m_ff[2] & ~m_ff[1] ) |\n (~q_ff[3] & q_ff[2] & q_ff[0] & ~m_ff[3] & ~m_ff[1] ) |\n ( q_ff[3] & ~q_ff[2] & ~q_ff[1] & ~m_ff[3] & m_ff[2] & m_ff[0]) |\n ( ~q_ff[2] & q_ff[1] & q_ff[0] & ~m_ff[3] & ~m_ff[2] ) |\n ( q_ff[3] & q_ff[2] & ~m_ff[1] & ~m_ff[0]) |\n ( q_ff[3] & q_ff[1] & ~m_ff[2] & ~m_ff[0]) |\n (~q_ff[3] & q_ff[2] & q_ff[1] & q_ff[0] & ~m_ff[3] & m_ff[2] ) |\n ( q_ff[3] & q_ff[2] & m_ff[3] & ~m_ff[2] ) |\n ( q_ff[3] & q_ff[1] & m_ff[3] & ~m_ff[2] & ~m_ff[1] ) |\n ( q_ff[3] & q_ff[0] & ~m_ff[2] & ~m_ff[1] ) |\n ( q_ff[3] & ~q_ff[1] & ~m_ff[3] & m_ff[2] & m_ff[1] & m_ff[0]) |\n ( q_ff[3] & q_ff[2] & q_ff[1] & m_ff[3] & ~m_ff[0]) |\n ( q_ff[3] & q_ff[2] & q_ff[1] & m_ff[3] & ~m_ff[1] ) |\n ( q_ff[3] & q_ff[2] & q_ff[0] & m_ff[3] & ~m_ff[1] ) |\n ( q_ff[3] & ~q_ff[2] & q_ff[1] & ~m_ff[3] & m_ff[1] ) |\n ( q_ff[3] & q_ff[1] & q_ff[0] & ~m_ff[2] ) |\n ( q_ff[3] & q_ff[2] & q_ff[1] & q_ff[0] & m_ff[3] );\n\n\n // END - short circuit logic for small numbers }}\n\n\n // *** Start Short Q *** {{\n\n assign short_dividend[31:0] = q_ff[31:0];\n assign short_dividend[32] = sign_ff & q_ff[31];\n\n\n // A B\n // 210 210 SH\n // --- --- --\n // 1xx 000 0\n // 1xx 001 8\n // 1xx 01x 16\n // 1xx 1xx 24\n // 01x 000 8\n // 01x 001 16\n // 01x 01x 24\n // 01x 1xx 32\n // 001 000 16\n // 001 001 24\n // 001 01x 32\n // 001 1xx 32\n // 000 000 24\n // 000 001 32\n // 000 01x 32\n // 000 1xx 32\n\n assign a_cls[4:3] = 2'b0;\n assign a_cls[2] = (~short_dividend[32] & (short_dividend[31:24] != {8{1'b0}})) | ( short_dividend[32] & (short_dividend[31:23] != {9{1'b1}}));\n assign a_cls[1] = (~short_dividend[32] & (short_dividend[23:16] != {8{1'b0}})) | ( short_dividend[32] & (short_dividend[22:15] != {8{1'b1}}));\n assign a_cls[0] = (~short_dividend[32] & (short_dividend[15:08] != {8{1'b0}})) | ( short_dividend[32] & (short_dividend[14:07] != {8{1'b1}}));\n\n assign b_cls[4:3] = 2'b0;\n assign b_cls[2] = (~m_ff[32] & ( m_ff[31:24] != {8{1'b0}})) | ( m_ff[32] & ( m_ff[31:24] != {8{1'b1}}));\n assign b_cls[1] = (~m_ff[32] & ( m_ff[23:16] != {8{1'b0}})) | ( m_ff[32] & ( m_ff[23:16] != {8{1'b1}}));\n assign b_cls[0] = (~m_ff[32] & ( m_ff[15:08] != {8{1'b0}})) | ( m_ff[32] & ( m_ff[15:08] != {8{1'b1}}));\n\n assign shortq_raw[3] = ( (a_cls[2:1] == 2'b01 ) & (b_cls[2] == 1'b1 ) ) | // Shift by 32\n ( (a_cls[2:0] == 3'b001) & (b_cls[2] == 1'b1 ) ) |\n ( (a_cls[2:0] == 3'b000) & (b_cls[2] == 1'b1 ) ) |\n ( (a_cls[2:0] == 3'b001) & (b_cls[2:1] == 2'b01 ) ) |\n ( (a_cls[2:0] == 3'b000) & (b_cls[2:1] == 2'b01 ) ) |\n ( (a_cls[2:0] == 3'b000) & (b_cls[2:0] == 3'b001) );\n\n assign shortq_raw[2] = ( (a_cls[2] == 1'b1 ) & (b_cls[2] == 1'b1 ) ) | // Shift by 24\n ( (a_cls[2:1] == 2'b01 ) & (b_cls[2:1] == 2'b01 ) ) |\n ( (a_cls[2:0] == 3'b001) & (b_cls[2:0] == 3'b001) ) |\n ( (a_cls[2:0] == 3'b000) & (b_cls[2:0] == 3'b000) );\n\n assign shortq_raw[1] = ( (a_cls[2] == 1'b1 ) & (b_cls[2:1] == 2'b01 ) ) | // Shift by 16\n ( (a_cls[2:1] == 2'b01 ) & (b_cls[2:0] == 3'b001) ) |\n ( (a_cls[2:0] == 3'b001) & (b_cls[2:0] == 3'b000) );\n\n assign shortq_raw[0] = ( (a_cls[2] == 1'b1 ) & (b_cls[2:0] == 3'b001) ) | // Shift by 8\n ( (a_cls[2:1] == 2'b01 ) & (b_cls[2:0] == 3'b000) );\n\n\n assign shortq_enable = valid_ff_x & (m_ff[31:0] != 32'b0) & (shortq_raw[3:0] != 4'b0);\n\n assign shortq_shift[3:0] = ({4{shortq_enable}} & shortq_raw[3:0]);\n\n assign shortq[5:0] = 6'b0;\n assign shortq_shift[5:4] = 2'b0;\n assign shortq_shift_ff[5] = 1'b0;\n\n assign shortq_shift_ff[4:0] = ({5{shortq_shift_xx[3]}} & 5'b1_1111) | // 31\n ({5{shortq_shift_xx[2]}} & 5'b1_1000) | // 24\n ({5{shortq_shift_xx[1]}} & 5'b1_0000) | // 16\n ({5{shortq_shift_xx[0]}} & 5'b0_1000); // 8\n\n // *** End Short *** }}\n\n\n\n\n\n assign div_clken = valid_in | run_state | finish | finish_ff;\n\n assign run_in = (valid_in | run_state) & ~finish & ~cancel;\n\n assign count_in[5:0] = {6{run_state & ~finish & ~cancel & ~shortq_enable}} & (count[5:0] + {1'b0,shortq_shift_ff[4:0]} + 6'd1);\n\n\n assign finish = (smallnum_case | ((~rem_ff) ? (count[5:0] == 6'd32) : (count[5:0] == 6'd33)));\n\n assign valid_out = finish_ff & ~cancel;\n\n assign sign_eff = signed_in & (divisor_in[31:0] != 32'b0);\n\n\n assign q_in[32:0] = ({33{~run_state }} & {1'b0,dividend_in[31:0]}) |\n ({33{ run_state & (valid_ff_x | shortq_enable_ff)}} & ({dividend_eff[31:0], ~a_in[32]} << shortq_shift_ff[4:0])) |\n ({33{ run_state & ~(valid_ff_x | shortq_enable_ff)}} & {q_ff[31:0], ~a_in[32]});\n\n assign qff_enable = valid_in | (run_state & ~shortq_enable);\n\n\n\n\n assign dividend_eff[31:0] = (sign_ff & dividend_neg_ff) ? dividend_comp[31:0] : q_ff[31:0];\n\n\n assign m_eff[32:0] = ( add ) ? m_ff[32:0] : ~m_ff[32:0];\n\n assign a_eff_shift[64:0] = {33'b0, dividend_eff[31:0]} << shortq_shift_ff[4:0];\n\n assign a_eff[32:0] = ({33{ rem_correct }} & a_ff[32:0] ) |\n ({33{~rem_correct & ~shortq_enable_ff}} & {a_ff[31:0], q_ff[32]} ) |\n ({33{~rem_correct & shortq_enable_ff}} & a_eff_shift[64:32] );\n\n assign a_shift[32:0] = {33{run_state}} & a_eff[32:0];\n\n assign a_in[32:0] = {33{run_state}} & (a_shift[32:0] + m_eff[32:0] + {32'b0,~add});\n\n assign aff_enable = valid_in | (run_state & ~shortq_enable & (count[5:0]!=6'd33)) | rem_correct;\n\n\n assign m_already_comp = (divisor_neg_ff & sign_ff);\n\n // if m already complemented, then invert operation add->sub, sub->add\n assign add = (a_ff[32] | rem_correct) ^ m_already_comp;\n\n assign rem_correct = (count[5:0] == 6'd33) & rem_ff & a_ff[32];\n\n\n\n assign q_ff_eff[31:0] = (sign_ff & (dividend_neg_ff ^ divisor_neg_ff)) ? q_ff_comp[31:0] : q_ff[31:0];\n\n assign a_ff_eff[31:0] = (sign_ff & dividend_neg_ff) ? a_ff_comp[31:0] : a_ff[31:0];\n\n assign data_out[31:0] = ({32{ smallnum_case_ff }} & {28'b0, smallnum_ff[3:0]}) |\n ({32{ rem_ff}} & a_ff_eff[31:0] ) |\n ({32{~smallnum_case_ff & ~rem_ff}} & q_ff_eff[31:0] );\n\n\n\n\nendmodule // el2_exu_div_existing_1bit_cheapshortq\n\n\n\n\n\n\n// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\nmodule el2_exu_div_new_1bit_fullshortq\n (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Scan mode\n /*pragma coverage on*/\n\n input logic cancel, // Flush pipeline\n input logic valid_in,\n input logic signed_in,\n input logic rem_in,\n input logic [31:0] dividend_in,\n input logic [31:0] divisor_in,\n\n output logic valid_out,\n output logic [31:0] data_out\n );\n\n\n logic valid_ff_in, valid_ff;\n logic finish_raw, finish, finish_ff;\n logic running_state;\n logic misc_enable;\n logic [2:0] control_in, control_ff;\n logic dividend_sign_ff, divisor_sign_ff, rem_ff;\n logic count_enable;\n logic [6:0] count_in, count_ff;\n\n logic smallnum_case;\n logic [3:0] smallnum;\n\n logic a_enable, a_shift;\n logic [31:0] a_in, a_ff;\n\n logic b_enable, b_twos_comp;\n logic [32:0] b_in, b_ff;\n\n logic [31:0] q_in, q_ff;\n\n logic rq_enable, r_sign_sel, r_restore_sel, r_adder_sel;\n logic [31:0] r_in, r_ff;\n\n logic twos_comp_q_sel, twos_comp_b_sel;\n logic [31:0] twos_comp_in, twos_comp_out;\n\n logic quotient_set;\n logic [32:0] adder_out;\n\n logic [63:0] ar_shifted;\n logic [5:0] shortq;\n logic [4:0] shortq_shift;\n logic [4:0] shortq_shift_ff;\n logic shortq_enable;\n logic shortq_enable_ff;\n logic [32:0] shortq_dividend;\n\n logic by_zero_case;\n logic by_zero_case_ff;\n\n\n\n rvdffe #(19) i_misc_ff (.*, .clk(clk), .en(misc_enable), .din ({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:0], finish, count_in[6:0]}),\n .dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:0], finish_ff, count_ff[6:0]}));\n\n rvdffe #(32) i_a_ff (.*, .clk(clk), .en(a_enable), .din(a_in[31:0]), .dout(a_ff[31:0]));\n rvdffe #(33) i_b_ff (.*, .clk(clk), .en(b_enable), .din(b_in[32:0]), .dout(b_ff[32:0]));\n rvdffe #(32) i_r_ff (.*, .clk(clk), .en(rq_enable), .din(r_in[31:0]), .dout(r_ff[31:0]));\n rvdffe #(32) i_q_ff (.*, .clk(clk), .en(rq_enable), .din(q_in[31:0]), .dout(q_ff[31:0]));\n\n\n\n\n assign valid_ff_in = valid_in & ~cancel;\n\n assign control_in[2] = (~valid_in & control_ff[2]) | (valid_in & signed_in & dividend_in[31]);\n assign control_in[1] = (~valid_in & control_ff[1]) | (valid_in & signed_in & divisor_in[31]);\n assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in);\n\n assign dividend_sign_ff = control_ff[2];\n assign divisor_sign_ff = control_ff[1];\n assign rem_ff = control_ff[0];\n\n\n assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b0);\n\n assign misc_enable = valid_in | valid_ff | cancel | running_state | finish_ff;\n assign running_state = (| count_ff[6:0]) | shortq_enable_ff;\n assign finish_raw = smallnum_case |\n by_zero_case |\n (count_ff[6:0] == 7'd32);\n\n\n assign finish = finish_raw & ~cancel;\n assign count_enable = (valid_ff | running_state) & ~finish & ~finish_ff & ~cancel & ~shortq_enable;\n assign count_in[6:0] = {7{count_enable}} & (count_ff[6:0] + {6'b0,1'b1} + {2'b0,shortq_shift_ff[4:0]});\n\n\n assign a_enable = valid_in | running_state;\n assign a_shift = running_state & ~shortq_enable_ff;\n\n assign ar_shifted[63:0] = { {32{dividend_sign_ff}} , a_ff[31:0]} << shortq_shift_ff[4:0];\n\n assign a_in[31:0] = ( {32{~a_shift & ~shortq_enable_ff}} & dividend_in[31:0] ) |\n ( {32{ a_shift }} & {a_ff[30:0],1'b0} ) |\n ( {32{ shortq_enable_ff}} & ar_shifted[31:0] );\n\n\n\n assign b_enable = valid_in | b_twos_comp;\n assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);\n\n assign b_in[32:0] = ( {33{~b_twos_comp}} & { (signed_in & divisor_in[31]),divisor_in[31:0] } ) |\n ( {33{ b_twos_comp}} & {~divisor_sign_ff,twos_comp_out[31:0] } );\n\n\n assign rq_enable = valid_in | valid_ff | running_state;\n assign r_sign_sel = valid_ff & dividend_sign_ff & ~by_zero_case;\n assign r_restore_sel = running_state & ~quotient_set & ~shortq_enable_ff;\n assign r_adder_sel = running_state & quotient_set & ~shortq_enable_ff;\n\n\n assign r_in[31:0] = ( {32{r_sign_sel }} & 32'hffffffff ) |\n ( {32{r_restore_sel }} & {r_ff[30:0] ,a_ff[31]} ) |\n ( {32{r_adder_sel }} & adder_out[31:0] ) |\n ( {32{shortq_enable_ff}} & ar_shifted[63:32] ) |\n ( {32{by_zero_case }} & a_ff[31:0] );\n\n\n assign q_in[31:0] = ( {32{~valid_ff }} & {q_ff[30:0], quotient_set} ) |\n ( {32{ smallnum_case }} & {28'b0 , smallnum[3:0]} ) |\n ( {32{ by_zero_case }} & {32{1'b1}} );\n\n\n\n assign adder_out[32:0] = {r_ff[31:0],a_ff[31]} + {b_ff[32:0] };\n\n\n assign quotient_set = (~adder_out[32] ^ dividend_sign_ff) | ( (a_ff[30:0] == 31'b0) & (adder_out[32:0] == 33'b0) );\n\n\n\n assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);\n assign twos_comp_q_sel = ~valid_ff & ~rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & ~by_zero_case_ff;\n\n assign twos_comp_in[31:0] = ( {32{twos_comp_q_sel}} & q_ff[31:0] ) |\n ( {32{twos_comp_b_sel}} & b_ff[31:0] );\n\n rvtwoscomp #(32) i_twos_comp (.din(twos_comp_in[31:0]), .dout(twos_comp_out[31:0]));\n\n\n\n assign valid_out = finish_ff & ~cancel;\n\n assign data_out[31:0] = ( {32{~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0] ) |\n ( {32{ rem_ff }} & r_ff[31:0] ) |\n ( {32{ twos_comp_q_sel}} & twos_comp_out[31:0] );\n\n\n\n\n // *** *** *** START : SMALLNUM {{\n\n assign smallnum_case = ( (a_ff[31:4] == 28'b0) & (b_ff[31:4] == 28'b0) & ~by_zero_case & ~rem_ff & valid_ff & ~cancel) |\n ( (a_ff[31:0] == 32'b0) & ~by_zero_case & ~rem_ff & valid_ff & ~cancel);\n\n assign smallnum[3] = ( a_ff[3] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] );\n\n assign smallnum[2] = ( a_ff[3] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[2] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & ~b_ff[2] );\n\n assign smallnum[1] = ( a_ff[2] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[1] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & ~b_ff[3] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & ~a_ff[2] & ~b_ff[3] & ~b_ff[2] & b_ff[1] & b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[1] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[2] );\n\n assign smallnum[0] = ( a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & a_ff[0] & ~b_ff[3] & b_ff[1] & b_ff[0]) |\n ( a_ff[2] & ~b_ff[3] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[1] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[0] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & ~a_ff[1] & ~b_ff[3] & ~b_ff[2] & b_ff[1] & b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & ~b_ff[2] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & ~a_ff[2] & ~b_ff[3] & b_ff[2] & b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[2] & ~b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & a_ff[0] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & ~a_ff[1] & ~b_ff[3] & b_ff[2] & b_ff[0]) |\n ( ~a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[1] & ~b_ff[2] & ~b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[1] & b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[0] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[1] & ~b_ff[3] & b_ff[2] & b_ff[1] & b_ff[0]) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & a_ff[0] & b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[1] ) |\n ( a_ff[3] & a_ff[1] & a_ff[0] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & a_ff[0] & b_ff[3] );\n\n // *** *** *** END : SMALLNUM }}\n\n\n\n\n // *** *** *** Start : Short Q {{\n\n assign shortq_dividend[32:0] = {dividend_sign_ff,a_ff[31:0]};\n\n\n logic [5:0] dw_a_enc;\n logic [5:0] dw_b_enc;\n logic [6:0] dw_shortq_raw;\n\n\n\n el2_exu_div_cls i_a_cls (\n .operand ( shortq_dividend[32:0] ),\n .cls ( dw_a_enc[4:0] ));\n\n el2_exu_div_cls i_b_cls (\n .operand ( b_ff[32:0] ),\n .cls ( dw_b_enc[4:0] ));\n\n assign dw_a_enc[5] = 1'b0;\n assign dw_b_enc[5] = 1'b0;\n\n\n\n assign dw_shortq_raw[6:0] = {1'b0,dw_b_enc[5:0]} - {1'b0,dw_a_enc[5:0]} + 7'd1;\n assign shortq[5:0] = dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0];\n\n assign shortq_enable = valid_ff & ~shortq[5] & ~(shortq[4:1] == 4'b1111) & ~cancel;\n\n assign shortq_shift[4:0] = ~shortq_enable ? 5'd0 : (5'b11111 - shortq[4:0]);\n\n\n // *** *** *** End : Short Q }}\n\n\n\n\n\nendmodule // el2_exu_div_new_1bit_fullshortq\n\n\n\n\n\n\n// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\nmodule el2_exu_div_new_2bit_fullshortq\n (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Scan mode\n /*pragma coverage on*/\n\n input logic cancel, // Flush pipeline\n input logic valid_in,\n input logic signed_in,\n input logic rem_in,\n input logic [31:0] dividend_in,\n input logic [31:0] divisor_in,\n\n output logic valid_out,\n output logic [31:0] data_out\n );\n\n\n logic valid_ff_in, valid_ff;\n logic finish_raw, finish, finish_ff;\n logic running_state;\n logic misc_enable;\n logic [2:0] control_in, control_ff;\n logic dividend_sign_ff, divisor_sign_ff, rem_ff;\n logic count_enable;\n logic [6:0] count_in, count_ff;\n\n logic smallnum_case;\n logic [3:0] smallnum;\n\n logic a_enable, a_shift;\n logic [31:0] a_in, a_ff;\n\n logic b_enable, b_twos_comp;\n logic [32:0] b_in;\n logic [34:0] b_ff;\n\n logic [31:0] q_in, q_ff;\n\n logic rq_enable, r_sign_sel, r_restore_sel, r_adder1_sel, r_adder2_sel, r_adder3_sel;\n logic [31:0] r_in, r_ff;\n\n logic twos_comp_q_sel, twos_comp_b_sel;\n logic [31:0] twos_comp_in, twos_comp_out;\n\n logic [3:1] quotient_raw;\n logic [1:0] quotient_new;\n logic [32:0] adder1_out;\n logic [33:0] adder2_out;\n logic [34:0] adder3_out;\n\n logic [63:0] ar_shifted;\n logic [5:0] shortq;\n logic [4:0] shortq_shift;\n logic [4:1] shortq_shift_ff;\n logic shortq_enable;\n logic shortq_enable_ff;\n logic [32:0] shortq_dividend;\n\n logic by_zero_case;\n logic by_zero_case_ff;\n\n\n\n rvdffe #(18) i_misc_ff (.*, .clk(clk), .en(misc_enable), .din ({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:1], finish, count_in[6:0]}),\n .dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:1], finish_ff, count_ff[6:0]}));\n\n rvdffe #(32) i_a_ff (.*, .clk(clk), .en(a_enable), .din(a_in[31:0]), .dout(a_ff[31:0]));\n rvdffe #(33) i_b_ff (.*, .clk(clk), .en(b_enable), .din(b_in[32:0]), .dout(b_ff[32:0]));\n rvdffe #(32) i_r_ff (.*, .clk(clk), .en(rq_enable), .din(r_in[31:0]), .dout(r_ff[31:0]));\n rvdffe #(32) i_q_ff (.*, .clk(clk), .en(rq_enable), .din(q_in[31:0]), .dout(q_ff[31:0]));\n\n\n\n\n assign valid_ff_in = valid_in & ~cancel;\n\n assign control_in[2] = (~valid_in & control_ff[2]) | (valid_in & signed_in & dividend_in[31]);\n assign control_in[1] = (~valid_in & control_ff[1]) | (valid_in & signed_in & divisor_in[31]);\n assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in);\n\n assign dividend_sign_ff = control_ff[2];\n assign divisor_sign_ff = control_ff[1];\n assign rem_ff = control_ff[0];\n\n\n assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b0);\n\n assign misc_enable = valid_in | valid_ff | cancel | running_state | finish_ff;\n assign running_state = (| count_ff[6:0]) | shortq_enable_ff;\n assign finish_raw = smallnum_case |\n by_zero_case |\n (count_ff[6:0] == 7'd32);\n\n\n assign finish = finish_raw & ~cancel;\n assign count_enable = (valid_ff | running_state) & ~finish & ~finish_ff & ~cancel & ~shortq_enable;\n assign count_in[6:0] = {7{count_enable}} & (count_ff[6:0] + {5'b0,2'b10} + {2'b0,shortq_shift_ff[4:1],1'b0});\n\n\n assign a_enable = valid_in | running_state;\n assign a_shift = running_state & ~shortq_enable_ff;\n\n assign ar_shifted[63:0] = { {32{dividend_sign_ff}} , a_ff[31:0]} << {shortq_shift_ff[4:1],1'b0};\n\n assign a_in[31:0] = ( {32{~a_shift & ~shortq_enable_ff}} & dividend_in[31:0] ) |\n ( {32{ a_shift }} & {a_ff[29:0],2'b0} ) |\n ( {32{ shortq_enable_ff}} & ar_shifted[31:0] );\n\n\n\n assign b_enable = valid_in | b_twos_comp;\n assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);\n\n assign b_in[32:0] = ( {33{~b_twos_comp}} & { (signed_in & divisor_in[31]),divisor_in[31:0] } ) |\n ( {33{ b_twos_comp}} & {~divisor_sign_ff,twos_comp_out[31:0] } );\n\n\n assign rq_enable = valid_in | valid_ff | running_state;\n assign r_sign_sel = valid_ff & dividend_sign_ff & ~by_zero_case;\n assign r_restore_sel = running_state & (quotient_new[1:0] == 2'b00) & ~shortq_enable_ff;\n assign r_adder1_sel = running_state & (quotient_new[1:0] == 2'b01) & ~shortq_enable_ff;\n assign r_adder2_sel = running_state & (quotient_new[1:0] == 2'b10) & ~shortq_enable_ff;\n assign r_adder3_sel = running_state & (quotient_new[1:0] == 2'b11) & ~shortq_enable_ff;\n\n\n assign r_in[31:0] = ( {32{r_sign_sel }} & 32'hffffffff ) |\n ( {32{r_restore_sel }} & {r_ff[29:0] ,a_ff[31:30]} ) |\n ( {32{r_adder1_sel }} & adder1_out[31:0] ) |\n ( {32{r_adder2_sel }} & adder2_out[31:0] ) |\n ( {32{r_adder3_sel }} & adder3_out[31:0] ) |\n ( {32{shortq_enable_ff}} & ar_shifted[63:32] ) |\n ( {32{by_zero_case }} & a_ff[31:0] );\n\n\n assign q_in[31:0] = ( {32{~valid_ff }} & {q_ff[29:0], quotient_new[1:0]} ) |\n ( {32{ smallnum_case }} & {28'b0 , smallnum[3:0]} ) |\n ( {32{ by_zero_case }} & {32{1'b1}} );\n\n\n assign b_ff[34:33] = {b_ff[32],b_ff[32]};\n\n\n assign adder1_out[32:0] = { r_ff[30:0],a_ff[31:30]} + b_ff[32:0];\n assign adder2_out[33:0] = { r_ff[31:0],a_ff[31:30]} + {b_ff[32:0],1'b0};\n assign adder3_out[34:0] = {r_ff[31],r_ff[31:0],a_ff[31:30]} + {b_ff[33:0],1'b0} + b_ff[34:0];\n\n\n assign quotient_raw[1] = (~adder1_out[32] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder1_out[32:0] == 33'b0) );\n assign quotient_raw[2] = (~adder2_out[33] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder2_out[33:0] == 34'b0) );\n assign quotient_raw[3] = (~adder3_out[34] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder3_out[34:0] == 35'b0) );\n\n assign quotient_new[1] = quotient_raw[3] | quotient_raw[2];\n assign quotient_new[0] = quotient_raw[3] |(~quotient_raw[2] & quotient_raw[1]);\n\n\n assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);\n assign twos_comp_q_sel = ~valid_ff & ~rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & ~by_zero_case_ff;\n\n assign twos_comp_in[31:0] = ( {32{twos_comp_q_sel}} & q_ff[31:0] ) |\n ( {32{twos_comp_b_sel}} & b_ff[31:0] );\n\n rvtwoscomp #(32) i_twos_comp (.din(twos_comp_in[31:0]), .dout(twos_comp_out[31:0]));\n\n\n\n assign valid_out = finish_ff & ~cancel;\n\n assign data_out[31:0] = ( {32{~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0] ) |\n ( {32{ rem_ff }} & r_ff[31:0] ) |\n ( {32{ twos_comp_q_sel}} & twos_comp_out[31:0] );\n\n\n\n\n // *** *** *** START : SMALLNUM {{\n\n assign smallnum_case = ( (a_ff[31:4] == 28'b0) & (b_ff[31:4] == 28'b0) & ~by_zero_case & ~rem_ff & valid_ff & ~cancel) |\n ( (a_ff[31:0] == 32'b0) & ~by_zero_case & ~rem_ff & valid_ff & ~cancel);\n\n assign smallnum[3] = ( a_ff[3] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] );\n\n assign smallnum[2] = ( a_ff[3] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[2] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & ~b_ff[2] );\n\n assign smallnum[1] = ( a_ff[2] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[1] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & ~b_ff[3] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & ~a_ff[2] & ~b_ff[3] & ~b_ff[2] & b_ff[1] & b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[1] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[2] );\n\n assign smallnum[0] = ( a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & a_ff[0] & ~b_ff[3] & b_ff[1] & b_ff[0]) |\n ( a_ff[2] & ~b_ff[3] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[1] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[0] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & ~a_ff[1] & ~b_ff[3] & ~b_ff[2] & b_ff[1] & b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & ~b_ff[2] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & ~a_ff[2] & ~b_ff[3] & b_ff[2] & b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[2] & ~b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & a_ff[0] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & ~a_ff[1] & ~b_ff[3] & b_ff[2] & b_ff[0]) |\n ( ~a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[1] & ~b_ff[2] & ~b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[1] & b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[0] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[1] & ~b_ff[3] & b_ff[2] & b_ff[1] & b_ff[0]) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & a_ff[0] & b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[1] ) |\n ( a_ff[3] & a_ff[1] & a_ff[0] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & a_ff[0] & b_ff[3] );\n\n // *** *** *** END : SMALLNUM }}\n\n\n\n\n // *** *** *** Start : Short Q {{\n\n assign shortq_dividend[32:0] = {dividend_sign_ff,a_ff[31:0]};\n\n\n logic [5:0] dw_a_enc;\n logic [5:0] dw_b_enc;\n logic [6:0] dw_shortq_raw;\n\n\n\n el2_exu_div_cls i_a_cls (\n .operand ( shortq_dividend[32:0] ),\n .cls ( dw_a_enc[4:0] ));\n\n el2_exu_div_cls i_b_cls (\n .operand ( b_ff[32:0] ),\n .cls ( dw_b_enc[4:0] ));\n\n assign dw_a_enc[5] = 1'b0;\n assign dw_b_enc[5] = 1'b0;\n\n\n\n assign dw_shortq_raw[6:0] = {1'b0,dw_b_enc[5:0]} - {1'b0,dw_a_enc[5:0]} + 7'd1;\n assign shortq[5:0] = dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0];\n\n assign shortq_enable = valid_ff & ~shortq[5] & ~(shortq[4:1] == 4'b1111) & ~cancel;\n\n assign shortq_shift[4:0] = ~shortq_enable ? 5'd0 : (5'b11111 - shortq[4:0]); // [0] is unused\n\n\n // *** *** *** End : Short Q }}\n\n\n\n\n\nendmodule // el2_exu_div_new_2bit_fullshortq\n\n\n\n\n\n\n// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\nmodule el2_exu_div_new_3bit_fullshortq\n (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Scan mode\n /*pragma coverage on*/\n\n input logic cancel, // Flush pipeline\n input logic valid_in,\n input logic signed_in,\n input logic rem_in,\n input logic [31:0] dividend_in,\n input logic [31:0] divisor_in,\n\n output logic valid_out,\n output logic [31:0] data_out\n );\n\n\n logic valid_ff_in, valid_ff;\n logic finish_raw, finish, finish_ff;\n logic running_state;\n logic misc_enable;\n logic [2:0] control_in, control_ff;\n logic dividend_sign_ff, divisor_sign_ff, rem_ff;\n logic count_enable;\n logic [6:0] count_in, count_ff;\n\n logic smallnum_case;\n logic [3:0] smallnum;\n\n logic a_enable, a_shift;\n logic [32:0] a_in, a_ff;\n\n logic b_enable, b_twos_comp;\n logic [32:0] b_in;\n logic [36:0] b_ff;\n\n logic [31:0] q_in, q_ff;\n\n logic rq_enable;\n logic r_sign_sel;\n logic r_restore_sel;\n logic r_adder1_sel, r_adder2_sel, r_adder3_sel, r_adder4_sel, r_adder5_sel, r_adder6_sel, r_adder7_sel;\n logic [32:0] r_in, r_ff;\n\n logic twos_comp_q_sel, twos_comp_b_sel;\n logic [31:0] twos_comp_in, twos_comp_out;\n\n logic [7:1] quotient_raw;\n logic [2:0] quotient_new;\n logic [33:0] adder1_out;\n logic [34:0] adder2_out;\n logic [35:0] adder3_out;\n logic [36:0] adder4_out;\n logic [36:0] adder5_out;\n logic [36:0] adder6_out;\n logic [36:0] adder7_out;\n\n logic [65:0] ar_shifted;\n logic [5:0] shortq;\n logic [4:0] shortq_shift;\n logic [4:0] shortq_decode;\n logic [4:0] shortq_shift_ff;\n logic shortq_enable;\n logic shortq_enable_ff;\n logic [32:0] shortq_dividend;\n\n logic by_zero_case;\n logic by_zero_case_ff;\n\n\n\n rvdffe #(19) i_misc_ff (.*, .clk(clk), .en(misc_enable), .din ({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:0], finish, count_in[6:0]}),\n .dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:0], finish_ff, count_ff[6:0]}));\n\n rvdffe #(33) i_a_ff (.*, .clk(clk), .en(a_enable), .din(a_in[32:0]), .dout(a_ff[32:0]));\n rvdffe #(33) i_b_ff (.*, .clk(clk), .en(b_enable), .din(b_in[32:0]), .dout(b_ff[32:0]));\n rvdffe #(33) i_r_ff (.*, .clk(clk), .en(rq_enable), .din(r_in[32:0]), .dout(r_ff[32:0]));\n rvdffe #(32) i_q_ff (.*, .clk(clk), .en(rq_enable), .din(q_in[31:0]), .dout(q_ff[31:0]));\n\n\n\n\n assign valid_ff_in = valid_in & ~cancel;\n\n assign control_in[2] = (~valid_in & control_ff[2]) | (valid_in & signed_in & dividend_in[31]);\n assign control_in[1] = (~valid_in & control_ff[1]) | (valid_in & signed_in & divisor_in[31]);\n assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in);\n\n assign dividend_sign_ff = control_ff[2];\n assign divisor_sign_ff = control_ff[1];\n assign rem_ff = control_ff[0];\n\n\n assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b0);\n\n assign misc_enable = valid_in | valid_ff | cancel | running_state | finish_ff;\n assign running_state = (| count_ff[6:0]) | shortq_enable_ff;\n assign finish_raw = smallnum_case |\n by_zero_case |\n (count_ff[6:0] == 7'd33);\n\n\n assign finish = finish_raw & ~cancel;\n assign count_enable = (valid_ff | running_state) & ~finish & ~finish_ff & ~cancel & ~shortq_enable;\n assign count_in[6:0] = {7{count_enable}} & (count_ff[6:0] + {5'b0,2'b11} + {2'b0,shortq_shift_ff[4:0]});\n\n\n assign a_enable = valid_in | running_state;\n assign a_shift = running_state & ~shortq_enable_ff;\n\n assign ar_shifted[65:0] = { {33{dividend_sign_ff}} , a_ff[32:0]} << {shortq_shift_ff[4:0]};\n\n assign a_in[32:0] = ( {33{~a_shift & ~shortq_enable_ff}} & {signed_in & dividend_in[31],dividend_in[31:0]} ) |\n ( {33{ a_shift }} & {a_ff[29:0],3'b0} ) |\n ( {33{ shortq_enable_ff}} & ar_shifted[32:0] );\n\n\n\n assign b_enable = valid_in | b_twos_comp;\n assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);\n\n assign b_in[32:0] = ( {33{~b_twos_comp}} & { (signed_in & divisor_in[31]),divisor_in[31:0] } ) |\n ( {33{ b_twos_comp}} & {~divisor_sign_ff,twos_comp_out[31:0] } );\n\n\n assign rq_enable = valid_in | valid_ff | running_state;\n assign r_sign_sel = valid_ff & dividend_sign_ff & ~by_zero_case;\n assign r_restore_sel = running_state & (quotient_new[2:0] == 3'b000) & ~shortq_enable_ff;\n assign r_adder1_sel = running_state & (quotient_new[2:0] == 3'b001) & ~shortq_enable_ff;\n assign r_adder2_sel = running_state & (quotient_new[2:0] == 3'b010) & ~shortq_enable_ff;\n assign r_adder3_sel = running_state & (quotient_new[2:0] == 3'b011) & ~shortq_enable_ff;\n assign r_adder4_sel = running_state & (quotient_new[2:0] == 3'b100) & ~shortq_enable_ff;\n assign r_adder5_sel = running_state & (quotient_new[2:0] == 3'b101) & ~shortq_enable_ff;\n assign r_adder6_sel = running_state & (quotient_new[2:0] == 3'b110) & ~shortq_enable_ff;\n assign r_adder7_sel = running_state & (quotient_new[2:0] == 3'b111) & ~shortq_enable_ff;\n\n\n assign r_in[32:0] = ( {33{r_sign_sel }} & {33{1'b1}} ) |\n ( {33{r_restore_sel }} & {r_ff[29:0] ,a_ff[32:30]} ) |\n ( {33{r_adder1_sel }} & adder1_out[32:0] ) |\n ( {33{r_adder2_sel }} & adder2_out[32:0] ) |\n ( {33{r_adder3_sel }} & adder3_out[32:0] ) |\n ( {33{r_adder4_sel }} & adder4_out[32:0] ) |\n ( {33{r_adder5_sel }} & adder5_out[32:0] ) |\n ( {33{r_adder6_sel }} & adder6_out[32:0] ) |\n ( {33{r_adder7_sel }} & adder7_out[32:0] ) |\n ( {33{shortq_enable_ff}} & ar_shifted[65:33] ) |\n ( {33{by_zero_case }} & {1'b0,a_ff[31:0]} );\n\n\n assign q_in[31:0] = ( {32{~valid_ff }} & {q_ff[28:0], quotient_new[2:0]} ) |\n ( {32{ smallnum_case}} & {28'b0 , smallnum[3:0]} ) |\n ( {32{ by_zero_case }} & {32{1'b1}} );\n\n\n assign b_ff[36:33] = {b_ff[32],b_ff[32],b_ff[32],b_ff[32]};\n\n\n assign adder1_out[33:0] = { r_ff[30:0],a_ff[32:30]} + b_ff[33:0];\n assign adder2_out[34:0] = { r_ff[31:0],a_ff[32:30]} + {b_ff[33:0],1'b0};\n assign adder3_out[35:0] = { r_ff[32:0],a_ff[32:30]} + {b_ff[34:0],1'b0} + b_ff[35:0];\n assign adder4_out[36:0] = {r_ff[32],r_ff[32:0],a_ff[32:30]} + {b_ff[34:0],2'b0};\n assign adder5_out[36:0] = {r_ff[32],r_ff[32:0],a_ff[32:30]} + {b_ff[34:0],2'b0} + b_ff[36:0];\n assign adder6_out[36:0] = {r_ff[32],r_ff[32:0],a_ff[32:30]} + {b_ff[34:0],2'b0} + {b_ff[35:0],1'b0};\n assign adder7_out[36:0] = {r_ff[32],r_ff[32:0],a_ff[32:30]} + {b_ff[34:0],2'b0} + {b_ff[35:0],1'b0} + b_ff[36:0];\n\n assign quotient_raw[1] = (~adder1_out[33] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder1_out[33:0] == 34'b0) );\n assign quotient_raw[2] = (~adder2_out[34] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder2_out[34:0] == 35'b0) );\n assign quotient_raw[3] = (~adder3_out[35] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder3_out[35:0] == 36'b0) );\n assign quotient_raw[4] = (~adder4_out[36] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder4_out[36:0] == 37'b0) );\n assign quotient_raw[5] = (~adder5_out[36] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder5_out[36:0] == 37'b0) );\n assign quotient_raw[6] = (~adder6_out[36] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder6_out[36:0] == 37'b0) );\n assign quotient_raw[7] = (~adder7_out[36] ^ dividend_sign_ff) | ( (a_ff[29:0] == 30'b0) & (adder7_out[36:0] == 37'b0) );\n\n assign quotient_new[2] = quotient_raw[7] | quotient_raw[6] | quotient_raw[5] | quotient_raw[4];\n assign quotient_new[1] = quotient_raw[7] | quotient_raw[6] | (~quotient_raw[4] & quotient_raw[3]) | (~quotient_raw[3] & quotient_raw[2]);\n assign quotient_new[0] = quotient_raw[7] | (~quotient_raw[6] & quotient_raw[5]) | (~quotient_raw[4] & quotient_raw[3]) | (~quotient_raw[2] & quotient_raw[1]);\n\n\n assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);\n assign twos_comp_q_sel = ~valid_ff & ~rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & ~by_zero_case_ff;\n\n assign twos_comp_in[31:0] = ( {32{twos_comp_q_sel}} & q_ff[31:0] ) |\n ( {32{twos_comp_b_sel}} & b_ff[31:0] );\n\n rvtwoscomp #(32) i_twos_comp (.din(twos_comp_in[31:0]), .dout(twos_comp_out[31:0]));\n\n\n\n assign valid_out = finish_ff & ~cancel;\n\n assign data_out[31:0] = ( {32{~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0] ) |\n ( {32{ rem_ff }} & r_ff[31:0] ) |\n ( {32{ twos_comp_q_sel}} & twos_comp_out[31:0] );\n\n\n\n\n // *** *** *** START : SMALLNUM {{\n\n assign smallnum_case = ( (a_ff[31:4] == 28'b0) & (b_ff[31:4] == 28'b0) & ~by_zero_case & ~rem_ff & valid_ff & ~cancel) |\n ( (a_ff[31:0] == 32'b0) & ~by_zero_case & ~rem_ff & valid_ff & ~cancel);\n\n assign smallnum[3] = ( a_ff[3] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] );\n\n assign smallnum[2] = ( a_ff[3] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[2] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & ~b_ff[2] );\n\n assign smallnum[1] = ( a_ff[2] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[1] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & ~b_ff[3] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & ~a_ff[2] & ~b_ff[3] & ~b_ff[2] & b_ff[1] & b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[1] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[2] );\n\n assign smallnum[0] = ( a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & a_ff[0] & ~b_ff[3] & b_ff[1] & b_ff[0]) |\n ( a_ff[2] & ~b_ff[3] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[1] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[0] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & ~a_ff[1] & ~b_ff[3] & ~b_ff[2] & b_ff[1] & b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & ~b_ff[2] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & ~a_ff[2] & ~b_ff[3] & b_ff[2] & b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[2] & ~b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & a_ff[0] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & ~a_ff[1] & ~b_ff[3] & b_ff[2] & b_ff[0]) |\n ( ~a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[1] & ~b_ff[2] & ~b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[1] & b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[0] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[1] & ~b_ff[3] & b_ff[2] & b_ff[1] & b_ff[0]) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & a_ff[0] & b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[1] ) |\n ( a_ff[3] & a_ff[1] & a_ff[0] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & a_ff[0] & b_ff[3] );\n\n // *** *** *** END : SMALLNUM }}\n\n\n\n\n // *** *** *** Start : Short Q {{\n\n assign shortq_dividend[32:0] = {dividend_sign_ff,a_ff[31:0]};\n\n\n logic [5:0] dw_a_enc;\n logic [5:0] dw_b_enc;\n logic [6:0] dw_shortq_raw;\n\n\n\n el2_exu_div_cls i_a_cls (\n .operand ( shortq_dividend[32:0] ),\n .cls ( dw_a_enc[4:0] ));\n\n el2_exu_div_cls i_b_cls (\n .operand ( b_ff[32:0] ),\n .cls ( dw_b_enc[4:0] ));\n\n assign dw_a_enc[5] = 1'b0;\n assign dw_b_enc[5] = 1'b0;\n\n\n\n assign dw_shortq_raw[6:0] = {1'b0,dw_b_enc[5:0]} - {1'b0,dw_a_enc[5:0]} + 7'd1;\n assign shortq[5:0] = dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0];\n\n assign shortq_enable = valid_ff & ~shortq[5] & ~(shortq[4:2] == 3'b111) & ~cancel;\n\n assign shortq_decode[4:0] = ( {5{shortq[4:0] == 5'd31}} & 5'd00) |\n ( {5{shortq[4:0] == 5'd30}} & 5'd00) |\n ( {5{shortq[4:0] == 5'd29}} & 5'd00) |\n ( {5{shortq[4:0] == 5'd28}} & 5'd00) |\n ( {5{shortq[4:0] == 5'd27}} & 5'd03) |\n ( {5{shortq[4:0] == 5'd26}} & 5'd06) |\n ( {5{shortq[4:0] == 5'd25}} & 5'd06) |\n ( {5{shortq[4:0] == 5'd24}} & 5'd06) |\n ( {5{shortq[4:0] == 5'd23}} & 5'd09) |\n ( {5{shortq[4:0] == 5'd22}} & 5'd09) |\n ( {5{shortq[4:0] == 5'd21}} & 5'd09) |\n ( {5{shortq[4:0] == 5'd20}} & 5'd12) |\n ( {5{shortq[4:0] == 5'd19}} & 5'd12) |\n ( {5{shortq[4:0] == 5'd18}} & 5'd12) |\n ( {5{shortq[4:0] == 5'd17}} & 5'd15) |\n ( {5{shortq[4:0] == 5'd16}} & 5'd15) |\n ( {5{shortq[4:0] == 5'd15}} & 5'd15) |\n ( {5{shortq[4:0] == 5'd14}} & 5'd18) |\n ( {5{shortq[4:0] == 5'd13}} & 5'd18) |\n ( {5{shortq[4:0] == 5'd12}} & 5'd18) |\n ( {5{shortq[4:0] == 5'd11}} & 5'd21) |\n ( {5{shortq[4:0] == 5'd10}} & 5'd21) |\n ( {5{shortq[4:0] == 5'd09}} & 5'd21) |\n ( {5{shortq[4:0] == 5'd08}} & 5'd24) |\n ( {5{shortq[4:0] == 5'd07}} & 5'd24) |\n ( {5{shortq[4:0] == 5'd06}} & 5'd24) |\n ( {5{shortq[4:0] == 5'd05}} & 5'd27) |\n ( {5{shortq[4:0] == 5'd04}} & 5'd27) |\n ( {5{shortq[4:0] == 5'd03}} & 5'd27) |\n ( {5{shortq[4:0] == 5'd02}} & 5'd27) |\n ( {5{shortq[4:0] == 5'd01}} & 5'd27) |\n ( {5{shortq[4:0] == 5'd00}} & 5'd27);\n\n\n assign shortq_shift[4:0] = ~shortq_enable ? 5'd0 : shortq_decode[4:0];\n\n\n // *** *** *** End : Short Q }}\n\n\n\n\n\nendmodule // el2_exu_div_new_3bit_fullshortq\n\n\n\n\n\n\n// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\nmodule el2_exu_div_new_4bit_fullshortq\n (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Scan mode\n /*pragma coverage on*/\n\n input logic cancel, // Flush pipeline\n input logic valid_in,\n input logic signed_in,\n input logic rem_in,\n input logic [31:0] dividend_in,\n input logic [31:0] divisor_in,\n\n output logic valid_out,\n output logic [31:0] data_out\n );\n\n\n logic valid_ff_in, valid_ff;\n logic finish_raw, finish, finish_ff;\n logic running_state;\n logic misc_enable;\n logic [2:0] control_in, control_ff;\n logic dividend_sign_ff, divisor_sign_ff, rem_ff;\n logic count_enable;\n logic [6:0] count_in, count_ff;\n\n logic smallnum_case;\n logic [3:0] smallnum;\n\n logic a_enable, a_shift;\n logic [31:0] a_in, a_ff;\n\n logic b_enable, b_twos_comp;\n logic [32:0] b_in;\n logic [37:0] b_ff;\n\n logic [31:0] q_in, q_ff;\n\n logic rq_enable;\n logic r_sign_sel;\n logic r_restore_sel;\n logic r_adder01_sel, r_adder02_sel, r_adder03_sel;\n logic r_adder04_sel, r_adder05_sel, r_adder06_sel, r_adder07_sel;\n logic r_adder08_sel, r_adder09_sel, r_adder10_sel, r_adder11_sel;\n logic r_adder12_sel, r_adder13_sel, r_adder14_sel, r_adder15_sel;\n logic [32:0] r_in, r_ff;\n\n logic twos_comp_q_sel, twos_comp_b_sel;\n logic [31:0] twos_comp_in, twos_comp_out;\n\n logic [15:1] quotient_raw;\n logic [3:0] quotient_new;\n logic [34:0] adder01_out;\n logic [35:0] adder02_out;\n logic [36:0] adder03_out;\n logic [37:0] adder04_out;\n logic [37:0] adder05_out;\n logic [37:0] adder06_out;\n logic [37:0] adder07_out;\n logic [37:0] adder08_out;\n logic [37:0] adder09_out;\n logic [37:0] adder10_out;\n logic [37:0] adder11_out;\n logic [37:0] adder12_out;\n logic [37:0] adder13_out;\n logic [37:0] adder14_out;\n logic [37:0] adder15_out;\n\n logic [64:0] ar_shifted;\n logic [5:0] shortq;\n logic [4:0] shortq_shift;\n logic [4:0] shortq_decode;\n logic [4:0] shortq_shift_ff;\n logic shortq_enable;\n logic shortq_enable_ff;\n logic [32:0] shortq_dividend;\n\n logic by_zero_case;\n logic by_zero_case_ff;\n\n\n\n rvdffe #(19) i_misc_ff (.*, .clk(clk), .en(misc_enable), .din ({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:0], finish, count_in[6:0]}),\n .dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:0], finish_ff, count_ff[6:0]}));\n\n rvdffe #(32) i_a_ff (.*, .clk(clk), .en(a_enable), .din(a_in[31:0]), .dout(a_ff[31:0]));\n rvdffe #(33) i_b_ff (.*, .clk(clk), .en(b_enable), .din(b_in[32:0]), .dout(b_ff[32:0]));\n rvdffe #(33) i_r_ff (.*, .clk(clk), .en(rq_enable), .din(r_in[32:0]), .dout(r_ff[32:0]));\n rvdffe #(32) i_q_ff (.*, .clk(clk), .en(rq_enable), .din(q_in[31:0]), .dout(q_ff[31:0]));\n\n\n\n\n assign valid_ff_in = valid_in & ~cancel;\n\n assign control_in[2] = (~valid_in & control_ff[2]) | (valid_in & signed_in & dividend_in[31]);\n assign control_in[1] = (~valid_in & control_ff[1]) | (valid_in & signed_in & divisor_in[31]);\n assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in);\n\n assign dividend_sign_ff = control_ff[2];\n assign divisor_sign_ff = control_ff[1];\n assign rem_ff = control_ff[0];\n\n\n assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b0);\n\n assign misc_enable = valid_in | valid_ff | cancel | running_state | finish_ff;\n assign running_state = (| count_ff[6:0]) | shortq_enable_ff;\n assign finish_raw = smallnum_case |\n by_zero_case |\n (count_ff[6:0] == 7'd32);\n\n\n assign finish = finish_raw & ~cancel;\n assign count_enable = (valid_ff | running_state) & ~finish & ~finish_ff & ~cancel & ~shortq_enable;\n assign count_in[6:0] = {7{count_enable}} & (count_ff[6:0] + 7'd4 + {2'b0,shortq_shift_ff[4:0]});\n\n\n assign a_enable = valid_in | running_state;\n assign a_shift = running_state & ~shortq_enable_ff;\n\n assign ar_shifted[64:0] = { {33{dividend_sign_ff}} , a_ff[31:0]} << {shortq_shift_ff[4:0]};\n\n assign a_in[31:0] = ( {32{~a_shift & ~shortq_enable_ff}} & dividend_in[31:0] ) |\n ( {32{ a_shift }} & {a_ff[27:0],4'b0} ) |\n ( {32{ shortq_enable_ff}} & ar_shifted[31:0] );\n\n\n\n assign b_enable = valid_in | b_twos_comp;\n assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);\n\n assign b_in[32:0] = ( {33{~b_twos_comp}} & { (signed_in & divisor_in[31]),divisor_in[31:0] } ) |\n ( {33{ b_twos_comp}} & {~divisor_sign_ff,twos_comp_out[31:0] } );\n\n\n assign rq_enable = valid_in | valid_ff | running_state;\n assign r_sign_sel = valid_ff & dividend_sign_ff & ~by_zero_case;\n assign r_restore_sel = running_state & (quotient_new[3:0] == 4'd00) & ~shortq_enable_ff;\n assign r_adder01_sel = running_state & (quotient_new[3:0] == 4'd01) & ~shortq_enable_ff;\n assign r_adder02_sel = running_state & (quotient_new[3:0] == 4'd02) & ~shortq_enable_ff;\n assign r_adder03_sel = running_state & (quotient_new[3:0] == 4'd03) & ~shortq_enable_ff;\n assign r_adder04_sel = running_state & (quotient_new[3:0] == 4'd04) & ~shortq_enable_ff;\n assign r_adder05_sel = running_state & (quotient_new[3:0] == 4'd05) & ~shortq_enable_ff;\n assign r_adder06_sel = running_state & (quotient_new[3:0] == 4'd06) & ~shortq_enable_ff;\n assign r_adder07_sel = running_state & (quotient_new[3:0] == 4'd07) & ~shortq_enable_ff;\n assign r_adder08_sel = running_state & (quotient_new[3:0] == 4'd08) & ~shortq_enable_ff;\n assign r_adder09_sel = running_state & (quotient_new[3:0] == 4'd09) & ~shortq_enable_ff;\n assign r_adder10_sel = running_state & (quotient_new[3:0] == 4'd10) & ~shortq_enable_ff;\n assign r_adder11_sel = running_state & (quotient_new[3:0] == 4'd11) & ~shortq_enable_ff;\n assign r_adder12_sel = running_state & (quotient_new[3:0] == 4'd12) & ~shortq_enable_ff;\n assign r_adder13_sel = running_state & (quotient_new[3:0] == 4'd13) & ~shortq_enable_ff;\n assign r_adder14_sel = running_state & (quotient_new[3:0] == 4'd14) & ~shortq_enable_ff;\n assign r_adder15_sel = running_state & (quotient_new[3:0] == 4'd15) & ~shortq_enable_ff;\n\n assign r_in[32:0] = ( {33{r_sign_sel }} & {33{1'b1}} ) |\n ( {33{r_restore_sel }} & {r_ff[28:0],a_ff[31:28]} ) |\n ( {33{r_adder01_sel }} & adder01_out[32:0] ) |\n ( {33{r_adder02_sel }} & adder02_out[32:0] ) |\n ( {33{r_adder03_sel }} & adder03_out[32:0] ) |\n ( {33{r_adder04_sel }} & adder04_out[32:0] ) |\n ( {33{r_adder05_sel }} & adder05_out[32:0] ) |\n ( {33{r_adder06_sel }} & adder06_out[32:0] ) |\n ( {33{r_adder07_sel }} & adder07_out[32:0] ) |\n ( {33{r_adder08_sel }} & adder08_out[32:0] ) |\n ( {33{r_adder09_sel }} & adder09_out[32:0] ) |\n ( {33{r_adder10_sel }} & adder10_out[32:0] ) |\n ( {33{r_adder11_sel }} & adder11_out[32:0] ) |\n ( {33{r_adder12_sel }} & adder12_out[32:0] ) |\n ( {33{r_adder13_sel }} & adder13_out[32:0] ) |\n ( {33{r_adder14_sel }} & adder14_out[32:0] ) |\n ( {33{r_adder15_sel }} & adder15_out[32:0] ) |\n ( {33{shortq_enable_ff}} & ar_shifted[64:32] ) |\n ( {33{by_zero_case }} & {1'b0,a_ff[31:0]} );\n\n\n assign q_in[31:0] = ( {32{~valid_ff }} & {q_ff[27:0], quotient_new[3:0]} ) |\n ( {32{ smallnum_case}} & {28'b0 , smallnum[3:0]} ) |\n ( {32{ by_zero_case }} & {32{1'b1}} );\n\n\n assign b_ff[37:33] = {b_ff[32],b_ff[32],b_ff[32],b_ff[32],b_ff[32]};\n\n\n assign adder01_out[34:0] = { r_ff[30:0],a_ff[31:28]} + b_ff[34:0];\n assign adder02_out[35:0] = { r_ff[31:0],a_ff[31:28]} + {b_ff[34:0],1'b0};\n assign adder03_out[36:0] = { r_ff[32:0],a_ff[31:28]} + {b_ff[35:0],1'b0} + b_ff[36:0];\n assign adder04_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[35:0],2'b0};\n assign adder05_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[35:0],2'b0} + b_ff[37:0];\n assign adder06_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[35:0],2'b0} + {b_ff[36:0],1'b0};\n assign adder07_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[35:0],2'b0} + {b_ff[36:0],1'b0} + b_ff[37:0];\n assign adder08_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[34:0],3'b0};\n assign adder09_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[34:0],3'b0} + b_ff[37:0];\n assign adder10_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[34:0],3'b0} + {b_ff[36:0],1'b0};\n assign adder11_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[34:0],3'b0} + {b_ff[36:0],1'b0} + b_ff[37:0];\n assign adder12_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[34:0],3'b0} + {b_ff[35:0],2'b0};\n assign adder13_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[34:0],3'b0} + {b_ff[35:0],2'b0} + b_ff[37:0];\n assign adder14_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[34:0],3'b0} + {b_ff[35:0],2'b0} + {b_ff[36:0],1'b0};\n assign adder15_out[37:0] = {r_ff[32],r_ff[32:0],a_ff[31:28]} + {b_ff[34:0],3'b0} + {b_ff[35:0],2'b0} + {b_ff[36:0],1'b0} + b_ff[37:0];\n\n assign quotient_raw[01] = (~adder01_out[34] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder01_out[34:0] == 35'b0) );\n assign quotient_raw[02] = (~adder02_out[35] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder02_out[35:0] == 36'b0) );\n assign quotient_raw[03] = (~adder03_out[36] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder03_out[36:0] == 37'b0) );\n assign quotient_raw[04] = (~adder04_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder04_out[37:0] == 38'b0) );\n assign quotient_raw[05] = (~adder05_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder05_out[37:0] == 38'b0) );\n assign quotient_raw[06] = (~adder06_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder06_out[37:0] == 38'b0) );\n assign quotient_raw[07] = (~adder07_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder07_out[37:0] == 38'b0) );\n assign quotient_raw[08] = (~adder08_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder08_out[37:0] == 38'b0) );\n assign quotient_raw[09] = (~adder09_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder09_out[37:0] == 38'b0) );\n assign quotient_raw[10] = (~adder10_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder10_out[37:0] == 38'b0) );\n assign quotient_raw[11] = (~adder11_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder11_out[37:0] == 38'b0) );\n assign quotient_raw[12] = (~adder12_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder12_out[37:0] == 38'b0) );\n assign quotient_raw[13] = (~adder13_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder13_out[37:0] == 38'b0) );\n assign quotient_raw[14] = (~adder14_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder14_out[37:0] == 38'b0) );\n assign quotient_raw[15] = (~adder15_out[37] ^ dividend_sign_ff) | ( (a_ff[27:0] == 28'b0) & (adder15_out[37:0] == 38'b0) );\n\n\n assign quotient_new[0] = ( quotient_raw[15:01] == 15'b000_0000_0000_0001 ) | // 1\n ( quotient_raw[15:03] == 13'b000_0000_0000_01 ) | // 3\n ( quotient_raw[15:05] == 11'b000_0000_0001 ) | // 5\n ( quotient_raw[15:07] == 9'b000_0000_01 ) | // 7\n ( quotient_raw[15:09] == 7'b000_0001 ) | // 9\n ( quotient_raw[15:11] == 5'b000_01 ) | // 11\n ( quotient_raw[15:13] == 3'b001 ) | // 13\n ( quotient_raw[ 15] == 1'b1 ); // 15\n\n assign quotient_new[1] = ( quotient_raw[15:02] == 14'b000_0000_0000_001 ) | // 2\n ( quotient_raw[15:03] == 13'b000_0000_0000_01 ) | // 3\n ( quotient_raw[15:06] == 10'b000_0000_001 ) | // 6\n ( quotient_raw[15:07] == 9'b000_0000_01 ) | // 7\n ( quotient_raw[15:10] == 6'b000_001 ) | // 10\n ( quotient_raw[15:11] == 5'b000_01 ) | // 11\n ( quotient_raw[15:14] == 2'b01 ) | // 14\n ( quotient_raw[ 15] == 1'b1 ); // 15\n\n assign quotient_new[2] = ( quotient_raw[15:04] == 12'b000_0000_0000_1 ) | // 4\n ( quotient_raw[15:05] == 11'b000_0000_0001 ) | // 5\n ( quotient_raw[15:06] == 10'b000_0000_001 ) | // 6\n ( quotient_raw[15:07] == 9'b000_0000_01 ) | // 7\n ( quotient_raw[15:12] == 4'b000_1 ) | // 12\n ( quotient_raw[15:13] == 3'b001 ) | // 13\n ( quotient_raw[15:14] == 2'b01 ) | // 14\n ( quotient_raw[ 15] == 1'b1 ); // 15\n\n assign quotient_new[3] = ( quotient_raw[15:08] == 8'b000_0000_1 ) | // 8\n ( quotient_raw[15:09] == 7'b000_0001 ) | // 9\n ( quotient_raw[15:10] == 6'b000_001 ) | // 10\n ( quotient_raw[15:11] == 5'b000_01 ) | // 11\n ( quotient_raw[15:12] == 4'b000_1 ) | // 12\n ( quotient_raw[15:13] == 3'b001 ) | // 13\n ( quotient_raw[15:14] == 2'b01 ) | // 14\n ( quotient_raw[ 15] == 1'b1 ); // 15\n\n\n assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff);\n assign twos_comp_q_sel = ~valid_ff & ~rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & ~by_zero_case_ff;\n\n assign twos_comp_in[31:0] = ( {32{twos_comp_q_sel}} & q_ff[31:0] ) |\n ( {32{twos_comp_b_sel}} & b_ff[31:0] );\n\n rvtwoscomp #(32) i_twos_comp (.din(twos_comp_in[31:0]), .dout(twos_comp_out[31:0]));\n\n\n\n assign valid_out = finish_ff & ~cancel;\n\n assign data_out[31:0] = ( {32{~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0] ) |\n ( {32{ rem_ff }} & r_ff[31:0] ) |\n ( {32{ twos_comp_q_sel}} & twos_comp_out[31:0] );\n\n\n\n\n // *** *** *** START : SMALLNUM {{\n\n assign smallnum_case = ( (a_ff[31:4] == 28'b0) & (b_ff[31:4] == 28'b0) & ~by_zero_case & ~rem_ff & valid_ff & ~cancel) |\n ( (a_ff[31:0] == 32'b0) & ~by_zero_case & ~rem_ff & valid_ff & ~cancel);\n\n assign smallnum[3] = ( a_ff[3] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] );\n\n assign smallnum[2] = ( a_ff[3] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[2] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & ~b_ff[2] );\n\n assign smallnum[1] = ( a_ff[2] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[1] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & ~b_ff[3] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & ~a_ff[2] & ~b_ff[3] & ~b_ff[2] & b_ff[1] & b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[2] & ~b_ff[3] & b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[1] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[2] );\n\n assign smallnum[0] = ( a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & a_ff[0] & ~b_ff[3] & b_ff[1] & b_ff[0]) |\n ( a_ff[2] & ~b_ff[3] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[1] & ~b_ff[3] & ~b_ff[2] & ~b_ff[0]) |\n ( a_ff[0] & ~b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & ~a_ff[1] & ~b_ff[3] & ~b_ff[2] & b_ff[1] & b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & ~b_ff[2] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & ~a_ff[2] & ~b_ff[3] & b_ff[2] & b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[2] & ~b_ff[1] ) |\n (~a_ff[3] & a_ff[2] & a_ff[0] & ~b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & ~a_ff[1] & ~b_ff[3] & b_ff[2] & b_ff[0]) |\n ( ~a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & ~b_ff[1] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[1] & ~b_ff[2] & ~b_ff[0]) |\n (~a_ff[3] & a_ff[2] & a_ff[1] & a_ff[0] & ~b_ff[3] & b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & b_ff[3] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[1] & b_ff[3] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[0] & ~b_ff[2] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[1] & ~b_ff[3] & b_ff[2] & b_ff[1] & b_ff[0]) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & b_ff[3] & ~b_ff[0]) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & a_ff[2] & a_ff[0] & b_ff[3] & ~b_ff[1] ) |\n ( a_ff[3] & ~a_ff[2] & a_ff[1] & ~b_ff[3] & b_ff[1] ) |\n ( a_ff[3] & a_ff[1] & a_ff[0] & ~b_ff[2] ) |\n ( a_ff[3] & a_ff[2] & a_ff[1] & a_ff[0] & b_ff[3] );\n\n // *** *** *** END : SMALLNUM }}\n\n\n\n\n // *** *** *** Start : Short Q {{\n\n assign shortq_dividend[32:0] = {dividend_sign_ff,a_ff[31:0]};\n\n\n logic [5:0] dw_a_enc;\n logic [5:0] dw_b_enc;\n logic [6:0] dw_shortq_raw;\n\n\n\n el2_exu_div_cls i_a_cls (\n .operand ( shortq_dividend[32:0] ),\n .cls ( dw_a_enc[4:0] ));\n\n el2_exu_div_cls i_b_cls (\n .operand ( b_ff[32:0] ),\n .cls ( dw_b_enc[4:0] ));\n\n assign dw_a_enc[5] = 1'b0;\n assign dw_b_enc[5] = 1'b0;\n\n\n assign dw_shortq_raw[6:0] = {1'b0,dw_b_enc[5:0]} - {1'b0,dw_a_enc[5:0]} + 7'd1;\n assign shortq[5:0] = dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0];\n\n assign shortq_enable = valid_ff & ~shortq[5] & ~(shortq[4:2] == 3'b111) & ~cancel;\n\n assign shortq_decode[4:0] = ( {5{shortq[4:0] == 5'd31}} & 5'd00) |\n ( {5{shortq[4:0] == 5'd30}} & 5'd00) |\n ( {5{shortq[4:0] == 5'd29}} & 5'd00) |\n ( {5{shortq[4:0] == 5'd28}} & 5'd00) |\n ( {5{shortq[4:0] == 5'd27}} & 5'd04) |\n ( {5{shortq[4:0] == 5'd26}} & 5'd04) |\n ( {5{shortq[4:0] == 5'd25}} & 5'd04) |\n ( {5{shortq[4:0] == 5'd24}} & 5'd04) |\n ( {5{shortq[4:0] == 5'd23}} & 5'd08) |\n ( {5{shortq[4:0] == 5'd22}} & 5'd08) |\n ( {5{shortq[4:0] == 5'd21}} & 5'd08) |\n ( {5{shortq[4:0] == 5'd20}} & 5'd08) |\n ( {5{shortq[4:0] == 5'd19}} & 5'd12) |\n ( {5{shortq[4:0] == 5'd18}} & 5'd12) |\n ( {5{shortq[4:0] == 5'd17}} & 5'd12) |\n ( {5{shortq[4:0] == 5'd16}} & 5'd12) |\n ( {5{shortq[4:0] == 5'd15}} & 5'd16) |\n ( {5{shortq[4:0] == 5'd14}} & 5'd16) |\n ( {5{shortq[4:0] == 5'd13}} & 5'd16) |\n ( {5{shortq[4:0] == 5'd12}} & 5'd16) |\n ( {5{shortq[4:0] == 5'd11}} & 5'd20) |\n ( {5{shortq[4:0] == 5'd10}} & 5'd20) |\n ( {5{shortq[4:0] == 5'd09}} & 5'd20) |\n ( {5{shortq[4:0] == 5'd08}} & 5'd20) |\n ( {5{shortq[4:0] == 5'd07}} & 5'd24) |\n ( {5{shortq[4:0] == 5'd06}} & 5'd24) |\n ( {5{shortq[4:0] == 5'd05}} & 5'd24) |\n ( {5{shortq[4:0] == 5'd04}} & 5'd24) |\n ( {5{shortq[4:0] == 5'd03}} & 5'd28) |\n ( {5{shortq[4:0] == 5'd02}} & 5'd28) |\n ( {5{shortq[4:0] == 5'd01}} & 5'd28) |\n ( {5{shortq[4:0] == 5'd00}} & 5'd28);\n\n\n assign shortq_shift[4:0] = ~shortq_enable ? 5'd0 : shortq_decode[4:0];\n\n\n // *** *** *** End : Short Q }}\n\n\n\n\n\nendmodule // el2_exu_div_new_4bit_fullshortq\n\n\n\n\n\n\n// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n\nmodule el2_exu_div_cls\n (\n input logic [32:0] operand,\n\n output logic [4:0] cls // Count leading sign bits - \"n\" format ignoring [32]\n );\n\n\n logic [4:0] cls_zeros;\n logic [4:0] cls_ones;\n\n\nassign cls_zeros[4:0] = ({5{operand[31] == { 1'b1} }} & 5'd00) |\n ({5{operand[31:30] == {{ 1{1'b0}},1'b1} }} & 5'd01) |\n ({5{operand[31:29] == {{ 2{1'b0}},1'b1} }} & 5'd02) |\n ({5{operand[31:28] == {{ 3{1'b0}},1'b1} }} & 5'd03) |\n ({5{operand[31:27] == {{ 4{1'b0}},1'b1} }} & 5'd04) |\n ({5{operand[31:26] == {{ 5{1'b0}},1'b1} }} & 5'd05) |\n ({5{operand[31:25] == {{ 6{1'b0}},1'b1} }} & 5'd06) |\n ({5{operand[31:24] == {{ 7{1'b0}},1'b1} }} & 5'd07) |\n ({5{operand[31:23] == {{ 8{1'b0}},1'b1} }} & 5'd08) |\n ({5{operand[31:22] == {{ 9{1'b0}},1'b1} }} & 5'd09) |\n ({5{operand[31:21] == {{10{1'b0}},1'b1} }} & 5'd10) |\n ({5{operand[31:20] == {{11{1'b0}},1'b1} }} & 5'd11) |\n ({5{operand[31:19] == {{12{1'b0}},1'b1} }} & 5'd12) |\n ({5{operand[31:18] == {{13{1'b0}},1'b1} }} & 5'd13) |\n ({5{operand[31:17] == {{14{1'b0}},1'b1} }} & 5'd14) |\n ({5{operand[31:16] == {{15{1'b0}},1'b1} }} & 5'd15) |\n ({5{operand[31:15] == {{16{1'b0}},1'b1} }} & 5'd16) |\n ({5{operand[31:14] == {{17{1'b0}},1'b1} }} & 5'd17) |\n ({5{operand[31:13] == {{18{1'b0}},1'b1} }} & 5'd18) |\n ({5{operand[31:12] == {{19{1'b0}},1'b1} }} & 5'd19) |\n ({5{operand[31:11] == {{20{1'b0}},1'b1} }} & 5'd20) |\n ({5{operand[31:10] == {{21{1'b0}},1'b1} }} & 5'd21) |\n ({5{operand[31:09] == {{22{1'b0}},1'b1} }} & 5'd22) |\n ({5{operand[31:08] == {{23{1'b0}},1'b1} }} & 5'd23) |\n ({5{operand[31:07] == {{24{1'b0}},1'b1} }} & 5'd24) |\n ({5{operand[31:06] == {{25{1'b0}},1'b1} }} & 5'd25) |\n ({5{operand[31:05] == {{26{1'b0}},1'b1} }} & 5'd26) |\n ({5{operand[31:04] == {{27{1'b0}},1'b1} }} & 5'd27) |\n ({5{operand[31:03] == {{28{1'b0}},1'b1} }} & 5'd28) |\n ({5{operand[31:02] == {{29{1'b0}},1'b1} }} & 5'd29) |\n ({5{operand[31:01] == {{30{1'b0}},1'b1} }} & 5'd30) |\n ({5{operand[31:00] == {{31{1'b0}},1'b1} }} & 5'd31) |\n ({5{operand[31:00] == {{32{1'b0}} } }} & 5'd00); // Don't care case as it will be handled as special case\n\n\nassign cls_ones[4:0] = ({5{operand[31:30] == {{ 1{1'b1}},1'b0} }} & 5'd00) |\n ({5{operand[31:29] == {{ 2{1'b1}},1'b0} }} & 5'd01) |\n ({5{operand[31:28] == {{ 3{1'b1}},1'b0} }} & 5'd02) |\n ({5{operand[31:27] == {{ 4{1'b1}},1'b0} }} & 5'd03) |\n ({5{operand[31:26] == {{ 5{1'b1}},1'b0} }} & 5'd04) |\n ({5{operand[31:25] == {{ 6{1'b1}},1'b0} }} & 5'd05) |\n ({5{operand[31:24] == {{ 7{1'b1}},1'b0} }} & 5'd06) |\n ({5{operand[31:23] == {{ 8{1'b1}},1'b0} }} & 5'd07) |\n ({5{operand[31:22] == {{ 9{1'b1}},1'b0} }} & 5'd08) |\n ({5{operand[31:21] == {{10{1'b1}},1'b0} }} & 5'd09) |\n ({5{operand[31:20] == {{11{1'b1}},1'b0} }} & 5'd10) |\n ({5{operand[31:19] == {{12{1'b1}},1'b0} }} & 5'd11) |\n ({5{operand[31:18] == {{13{1'b1}},1'b0} }} & 5'd12) |\n ({5{operand[31:17] == {{14{1'b1}},1'b0} }} & 5'd13) |\n ({5{operand[31:16] == {{15{1'b1}},1'b0} }} & 5'd14) |\n ({5{operand[31:15] == {{16{1'b1}},1'b0} }} & 5'd15) |\n ({5{operand[31:14] == {{17{1'b1}},1'b0} }} & 5'd16) |\n ({5{operand[31:13] == {{18{1'b1}},1'b0} }} & 5'd17) |\n ({5{operand[31:12] == {{19{1'b1}},1'b0} }} & 5'd18) |\n ({5{operand[31:11] == {{20{1'b1}},1'b0} }} & 5'd19) |\n ({5{operand[31:10] == {{21{1'b1}},1'b0} }} & 5'd20) |\n ({5{operand[31:09] == {{22{1'b1}},1'b0} }} & 5'd21) |\n ({5{operand[31:08] == {{23{1'b1}},1'b0} }} & 5'd22) |\n ({5{operand[31:07] == {{24{1'b1}},1'b0} }} & 5'd23) |\n ({5{operand[31:06] == {{25{1'b1}},1'b0} }} & 5'd24) |\n ({5{operand[31:05] == {{26{1'b1}},1'b0} }} & 5'd25) |\n ({5{operand[31:04] == {{27{1'b1}},1'b0} }} & 5'd26) |\n ({5{operand[31:03] == {{28{1'b1}},1'b0} }} & 5'd27) |\n ({5{operand[31:02] == {{29{1'b1}},1'b0} }} & 5'd28) |\n ({5{operand[31:01] == {{30{1'b1}},1'b0} }} & 5'd29) |\n ({5{operand[31:00] == {{31{1'b1}},1'b0} }} & 5'd30) |\n ({5{operand[31:00] == {{32{1'b1}} } }} & 5'd31);\n\n\nassign cls[4:0] = operand[32] ? cls_ones[4:0] : cls_zeros[4:0];\n\nendmodule // el2_exu_div_cls\n" }, { "path": "design/exu/el2_exu_mul_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n\nmodule el2_exu_mul_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Scan mode\n /*pragma coverage on*/\n\n input el2_mul_pkt_t mul_p, // {Valid, RS1 signed operand, RS2 signed operand, Select low 32-bits of result}\n\n input logic [31:0] rs1_in, // A operand\n input logic [31:0] rs2_in, // B operand\n\n\n output logic [31:0] result_x // Result\n );\n\n\n logic mul_x_enable;\n logic bit_x_enable;\n logic signed [32:0] rs1_ext_in;\n logic signed [32:0] rs2_ext_in;\n logic [65:0] prod_x;\n logic low_x;\n\n\n\n // *** Start - BitManip ***\n\n logic bitmanip_sel_d;\n logic bitmanip_sel_x;\n logic [31:0] bitmanip_d;\n logic [31:0] bitmanip_x;\n\n\n\n // ZBE\n logic ap_bcompress;\n logic ap_bdecompress;\n\n // ZBC\n logic ap_clmul;\n logic ap_clmulh;\n logic ap_clmulr;\n\n // ZBP\n logic ap_grev;\n logic ap_gorc;\n logic ap_shfl;\n logic ap_unshfl;\n logic ap_xperm_n;\n logic ap_xperm_b;\n logic ap_xperm_h;\n\n // ZBR\n logic ap_crc32_b;\n logic ap_crc32_h;\n logic ap_crc32_w;\n logic ap_crc32c_b;\n logic ap_crc32c_h;\n logic ap_crc32c_w;\n\n // ZBF\n logic ap_bfp;\n\n\n if (pt.BITMANIP_ZBE == 1)\n begin\n assign ap_bcompress = mul_p.bcompress;\n assign ap_bdecompress = mul_p.bdecompress;\n end\n else\n begin\n assign ap_bcompress = 1'b0;\n assign ap_bdecompress = 1'b0;\n end\n\n if (pt.BITMANIP_ZBC == 1)\n begin\n assign ap_clmul = mul_p.clmul;\n assign ap_clmulh = mul_p.clmulh;\n assign ap_clmulr = mul_p.clmulr;\n end\n else\n begin\n assign ap_clmul = 1'b0;\n assign ap_clmulh = 1'b0;\n assign ap_clmulr = 1'b0;\n end\n\n if (pt.BITMANIP_ZBP == 1)\n begin\n assign ap_grev = mul_p.grev;\n assign ap_gorc = mul_p.gorc;\n assign ap_shfl = mul_p.shfl;\n assign ap_unshfl = mul_p.unshfl;\n assign ap_xperm_n = mul_p.xperm_n;\n assign ap_xperm_b = mul_p.xperm_b;\n assign ap_xperm_h = mul_p.xperm_h;\n end\n else\n begin\n assign ap_grev = 1'b0;\n assign ap_gorc = 1'b0;\n assign ap_shfl = 1'b0;\n assign ap_unshfl = 1'b0;\n assign ap_xperm_n = 1'b0;\n assign ap_xperm_b = 1'b0;\n assign ap_xperm_h = 1'b0;\n end\n\n if (pt.BITMANIP_ZBR == 1)\n begin\n assign ap_crc32_b = mul_p.crc32_b;\n assign ap_crc32_h = mul_p.crc32_h;\n assign ap_crc32_w = mul_p.crc32_w;\n assign ap_crc32c_b = mul_p.crc32c_b;\n assign ap_crc32c_h = mul_p.crc32c_h;\n assign ap_crc32c_w = mul_p.crc32c_w;\n end\n else\n begin\n assign ap_crc32_b = 1'b0;\n assign ap_crc32_h = 1'b0;\n assign ap_crc32_w = 1'b0;\n assign ap_crc32c_b = 1'b0;\n assign ap_crc32c_h = 1'b0;\n assign ap_crc32c_w = 1'b0;\n end\n\n if (pt.BITMANIP_ZBF == 1)\n begin\n assign ap_bfp = mul_p.bfp;\n end\n else\n begin\n assign ap_bfp = 1'b0;\n end\n\n\n // *** End - BitManip ***\n\n\n\n assign mul_x_enable = mul_p.valid;\n assign bit_x_enable = mul_p.valid;\n\n assign rs1_ext_in[32] = mul_p.rs1_sign & rs1_in[31];\n assign rs2_ext_in[32] = mul_p.rs2_sign & rs2_in[31];\n\n assign rs1_ext_in[31:0] = rs1_in[31:0];\n assign rs2_ext_in[31:0] = rs2_in[31:0];\n\n\n\n // --------------------------- Multiply ----------------------------------\n\n\n logic signed [32:0] rs1_x;\n logic signed [32:0] rs2_x;\n\n rvdffe #(34) i_a_x_ff (.*, .clk(clk), .din({mul_p.low,rs1_ext_in[32:0]}), .dout({low_x,rs1_x[32:0]}), .en(mul_x_enable));\n rvdffe #(33) i_b_x_ff (.*, .clk(clk), .din( rs2_ext_in[32:0] ), .dout( rs2_x[32:0] ), .en(mul_x_enable));\n\n\n assign prod_x[65:0] = rs1_x * rs2_x;\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : BCOMPRESS, BDECOMPRESS * * * * * * * * * * * * *\n\n\n // *** BCOMPRESS == \"gather\" ***\n\n logic [31:0] bcompress_d;\n logic bcompress_test_bit_d;\n integer bcompress_i, bcompress_j;\n\n\n always_comb\n begin\n\n bcompress_j = 0;\n bcompress_test_bit_d = 1'b0;\n bcompress_d[31:0] = 32'b0;\n\n for (bcompress_i=0; bcompress_i<32; bcompress_i++)\n begin\n bcompress_test_bit_d = rs2_in[bcompress_i];\n if (bcompress_test_bit_d)\n begin\n bcompress_d[bcompress_j] = rs1_in[bcompress_i];\n bcompress_j = bcompress_j + 1;\n end // IF bcompress_test_bit\n end // FOR bcompress_i\n end // ALWAYS_COMB\n\n\n\n // *** BDECOMPRESS == \"scatter\" ***\n\n logic [31:0] bdecompress_d;\n logic bdecompress_test_bit_d;\n integer bdecompress_i, bdecompress_j;\n\n\n always_comb\n begin\n\n bdecompress_j = 0;\n bdecompress_test_bit_d = 1'b0;\n bdecompress_d[31:0] = 32'b0;\n\n for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)\n begin\n bdecompress_test_bit_d = rs2_in[bdecompress_i];\n if (bdecompress_test_bit_d)\n begin\n bdecompress_d[bdecompress_i] = rs1_in[bdecompress_j];\n bdecompress_j = bdecompress_j + 1;\n end // IF bdecompress_test_bit\n end // FOR bdecompress_i\n end // ALWAYS_COMB\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : CLMUL, CLMULH, CLMULR * * * * * * * * * * * * *\n\n logic [62:0] clmul_raw_d;\n\n\n assign clmul_raw_d[62:0] = ( {63{rs2_in[00]}} & {31'b0,rs1_in[31:0] } ) ^\n ( {63{rs2_in[01]}} & {30'b0,rs1_in[31:0], 1'b0} ) ^\n ( {63{rs2_in[02]}} & {29'b0,rs1_in[31:0], 2'b0} ) ^\n ( {63{rs2_in[03]}} & {28'b0,rs1_in[31:0], 3'b0} ) ^\n ( {63{rs2_in[04]}} & {27'b0,rs1_in[31:0], 4'b0} ) ^\n ( {63{rs2_in[05]}} & {26'b0,rs1_in[31:0], 5'b0} ) ^\n ( {63{rs2_in[06]}} & {25'b0,rs1_in[31:0], 6'b0} ) ^\n ( {63{rs2_in[07]}} & {24'b0,rs1_in[31:0], 7'b0} ) ^\n ( {63{rs2_in[08]}} & {23'b0,rs1_in[31:0], 8'b0} ) ^\n ( {63{rs2_in[09]}} & {22'b0,rs1_in[31:0], 9'b0} ) ^\n ( {63{rs2_in[10]}} & {21'b0,rs1_in[31:0],10'b0} ) ^\n ( {63{rs2_in[11]}} & {20'b0,rs1_in[31:0],11'b0} ) ^\n ( {63{rs2_in[12]}} & {19'b0,rs1_in[31:0],12'b0} ) ^\n ( {63{rs2_in[13]}} & {18'b0,rs1_in[31:0],13'b0} ) ^\n ( {63{rs2_in[14]}} & {17'b0,rs1_in[31:0],14'b0} ) ^\n ( {63{rs2_in[15]}} & {16'b0,rs1_in[31:0],15'b0} ) ^\n ( {63{rs2_in[16]}} & {15'b0,rs1_in[31:0],16'b0} ) ^\n ( {63{rs2_in[17]}} & {14'b0,rs1_in[31:0],17'b0} ) ^\n ( {63{rs2_in[18]}} & {13'b0,rs1_in[31:0],18'b0} ) ^\n ( {63{rs2_in[19]}} & {12'b0,rs1_in[31:0],19'b0} ) ^\n ( {63{rs2_in[20]}} & {11'b0,rs1_in[31:0],20'b0} ) ^\n ( {63{rs2_in[21]}} & {10'b0,rs1_in[31:0],21'b0} ) ^\n ( {63{rs2_in[22]}} & { 9'b0,rs1_in[31:0],22'b0} ) ^\n ( {63{rs2_in[23]}} & { 8'b0,rs1_in[31:0],23'b0} ) ^\n ( {63{rs2_in[24]}} & { 7'b0,rs1_in[31:0],24'b0} ) ^\n ( {63{rs2_in[25]}} & { 6'b0,rs1_in[31:0],25'b0} ) ^\n ( {63{rs2_in[26]}} & { 5'b0,rs1_in[31:0],26'b0} ) ^\n ( {63{rs2_in[27]}} & { 4'b0,rs1_in[31:0],27'b0} ) ^\n ( {63{rs2_in[28]}} & { 3'b0,rs1_in[31:0],28'b0} ) ^\n ( {63{rs2_in[29]}} & { 2'b0,rs1_in[31:0],29'b0} ) ^\n ( {63{rs2_in[30]}} & { 1'b0,rs1_in[31:0],30'b0} ) ^\n ( {63{rs2_in[31]}} & { rs1_in[31:0],31'b0} );\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : GREV * * * * * * * * * * * * * * * * * *\n\n // uint32_t grev32(uint32_t rs1, uint32_t rs2)\n // {\n // uint32_t x = rs1;\n // int shamt = rs2 & 31;\n //\n // if (shamt & 1) x = ( (x & 0x55555555) << 1) | ( (x & 0xAAAAAAAA) >> 1);\n // if (shamt & 2) x = ( (x & 0x33333333) << 2) | ( (x & 0xCCCCCCCC) >> 2);\n // if (shamt & 4) x = ( (x & 0x0F0F0F0F) << 4) | ( (x & 0xF0F0F0F0) >> 4);\n // if (shamt & 8) x = ( (x & 0x00FF00FF) << 8) | ( (x & 0xFF00FF00) >> 8);\n // if (shamt & 16) x = ( (x & 0x0000FFFF) << 16) | ( (x & 0xFFFF0000) >> 16);\n //\n // return x;\n // }\n\n\n logic [31:0] grev1_d;\n logic [31:0] grev2_d;\n logic [31:0] grev4_d;\n logic [31:0] grev8_d;\n logic [31:0] grev_d;\n\n\n assign grev1_d[31:0] = (rs2_in[0]) ? {rs1_in[30],rs1_in[31],rs1_in[28],rs1_in[29],rs1_in[26],rs1_in[27],rs1_in[24],rs1_in[25],\n rs1_in[22],rs1_in[23],rs1_in[20],rs1_in[21],rs1_in[18],rs1_in[19],rs1_in[16],rs1_in[17],\n rs1_in[14],rs1_in[15],rs1_in[12],rs1_in[13],rs1_in[10],rs1_in[11],rs1_in[08],rs1_in[09],\n rs1_in[06],rs1_in[07],rs1_in[04],rs1_in[05],rs1_in[02],rs1_in[03],rs1_in[00],rs1_in[01]} : rs1_in[31:0];\n\n assign grev2_d[31:0] = (rs2_in[1]) ? {grev1_d[29:28],grev1_d[31:30],grev1_d[25:24],grev1_d[27:26],\n grev1_d[21:20],grev1_d[23:22],grev1_d[17:16],grev1_d[19:18],\n grev1_d[13:12],grev1_d[15:14],grev1_d[09:08],grev1_d[11:10],\n grev1_d[05:04],grev1_d[07:06],grev1_d[01:00],grev1_d[03:02]} : grev1_d[31:0];\n\n assign grev4_d[31:0] = (rs2_in[2]) ? {grev2_d[27:24],grev2_d[31:28],grev2_d[19:16],grev2_d[23:20],\n grev2_d[11:08],grev2_d[15:12],grev2_d[03:00],grev2_d[07:04]} : grev2_d[31:0];\n\n assign grev8_d[31:0] = (rs2_in[3]) ? {grev4_d[23:16],grev4_d[31:24],grev4_d[07:00],grev4_d[15:08]} : grev4_d[31:0];\n\n assign grev_d[31:0] = (rs2_in[4]) ? {grev8_d[15:00],grev8_d[31:16]} : grev8_d[31:0];\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : GORC * * * * * * * * * * * * * * * * * *\n\n // uint32_t gorc32(uint32_t rs1, uint32_t rs2)\n // {\n // uint32_t x = rs1;\n // int shamt = rs2 & 31;\n //\n // if (shamt & 1) x |= ( (x & 0x55555555) << 1) | ( (x & 0xAAAAAAAA) >> 1);\n // if (shamt & 2) x |= ( (x & 0x33333333) << 2) | ( (x & 0xCCCCCCCC) >> 2);\n // if (shamt & 4) x |= ( (x & 0x0F0F0F0F) << 4) | ( (x & 0xF0F0F0F0) >> 4);\n // if (shamt & 8) x |= ( (x & 0x00FF00FF) << 8) | ( (x & 0xFF00FF00) >> 8);\n // if (shamt & 16) x |= ( (x & 0x0000FFFF) << 16) | ( (x & 0xFFFF0000) >> 16);\n //\n // return x;\n // }\n\n\n logic [31:0] gorc1_d;\n logic [31:0] gorc2_d;\n logic [31:0] gorc4_d;\n logic [31:0] gorc8_d;\n logic [31:0] gorc_d;\n\n\n assign gorc1_d[31:0] = ( {32{rs2_in[0]}} & {rs1_in[30],rs1_in[31],rs1_in[28],rs1_in[29],rs1_in[26],rs1_in[27],rs1_in[24],rs1_in[25],\n rs1_in[22],rs1_in[23],rs1_in[20],rs1_in[21],rs1_in[18],rs1_in[19],rs1_in[16],rs1_in[17],\n rs1_in[14],rs1_in[15],rs1_in[12],rs1_in[13],rs1_in[10],rs1_in[11],rs1_in[08],rs1_in[09],\n rs1_in[06],rs1_in[07],rs1_in[04],rs1_in[05],rs1_in[02],rs1_in[03],rs1_in[00],rs1_in[01]} ) | rs1_in[31:0];\n\n assign gorc2_d[31:0] = ( {32{rs2_in[1]}} & {gorc1_d[29:28],gorc1_d[31:30],gorc1_d[25:24],gorc1_d[27:26],\n gorc1_d[21:20],gorc1_d[23:22],gorc1_d[17:16],gorc1_d[19:18],\n gorc1_d[13:12],gorc1_d[15:14],gorc1_d[09:08],gorc1_d[11:10],\n gorc1_d[05:04],gorc1_d[07:06],gorc1_d[01:00],gorc1_d[03:02]} ) | gorc1_d[31:0];\n\n assign gorc4_d[31:0] = ( {32{rs2_in[2]}} & {gorc2_d[27:24],gorc2_d[31:28],gorc2_d[19:16],gorc2_d[23:20],\n gorc2_d[11:08],gorc2_d[15:12],gorc2_d[03:00],gorc2_d[07:04]} ) | gorc2_d[31:0];\n\n assign gorc8_d[31:0] = ( {32{rs2_in[3]}} & {gorc4_d[23:16],gorc4_d[31:24],gorc4_d[07:00],gorc4_d[15:08]} ) | gorc4_d[31:0];\n\n assign gorc_d[31:0] = ( {32{rs2_in[4]}} & {gorc8_d[15:00],gorc8_d[31:16]} ) | gorc8_d[31:0];\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : SHFL, UNSHLF * * * * * * * * * * * * * * * * * *\n\n // uint32_t shuffle32_stage (uint32_t src, uint32_t maskL, uint32_t maskR, int N)\n // {\n // uint32_t x = src & ~(maskL | maskR);\n // x |= ((src << N) & maskL) | ((src >> N) & maskR);\n // return x;\n // }\n //\n //\n //\n // uint32_t shfl32(uint32_t rs1, uint32_t rs2)\n // {\n // uint32_t x = rs1;\n // int shamt = rs2 & 15\n //\n // if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);\n // if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);\n // if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0xc0c0c0c0, 2);\n // if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);\n //\n // return x;\n // }\n\n\n logic [31:0] shfl8_d;\n logic [31:0] shfl4_d;\n logic [31:0] shfl2_d;\n logic [31:0] shfl_d;\n\n\n\n assign shfl8_d[31:0] = (rs2_in[3]) ? {rs1_in[31:24],rs1_in[15:08],rs1_in[23:16],rs1_in[07:00]} : rs1_in[31:0];\n\n assign shfl4_d[31:0] = (rs2_in[2]) ? {shfl8_d[31:28],shfl8_d[23:20],shfl8_d[27:24],shfl8_d[19:16],\n shfl8_d[15:12],shfl8_d[07:04],shfl8_d[11:08],shfl8_d[03:00]} : shfl8_d[31:0];\n\n assign shfl2_d[31:0] = (rs2_in[1]) ? {shfl4_d[31:30],shfl4_d[27:26],shfl4_d[29:28],shfl4_d[25:24],\n shfl4_d[23:22],shfl4_d[19:18],shfl4_d[21:20],shfl4_d[17:16],\n shfl4_d[15:14],shfl4_d[11:10],shfl4_d[13:12],shfl4_d[09:08],\n shfl4_d[07:06],shfl4_d[03:02],shfl4_d[05:04],shfl4_d[01:00]} : shfl4_d[31:0];\n\n assign shfl_d[31:0] = (rs2_in[0]) ? {shfl2_d[31],shfl2_d[29],shfl2_d[30],shfl2_d[28],shfl2_d[27],shfl2_d[25],shfl2_d[26],shfl2_d[24],\n shfl2_d[23],shfl2_d[21],shfl2_d[22],shfl2_d[20],shfl2_d[19],shfl2_d[17],shfl2_d[18],shfl2_d[16],\n shfl2_d[15],shfl2_d[13],shfl2_d[14],shfl2_d[12],shfl2_d[11],shfl2_d[09],shfl2_d[10],shfl2_d[08],\n shfl2_d[07],shfl2_d[05],shfl2_d[06],shfl2_d[04],shfl2_d[03],shfl2_d[01],shfl2_d[02],shfl2_d[00]} : shfl2_d[31:0];\n\n\n\n\n // uint32_t unshfl32(uint32_t rs1, uint32_t rs2)\n // {\n // uint32_t x = rs1;\n // int shamt = rs2 & 15\n //\n // if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);\n // if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0xc0c0c0c0, 2);\n // if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);\n // if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);\n //\n // return x;\n // }\n\n\n logic [31:0] unshfl1_d;\n logic [31:0] unshfl2_d;\n logic [31:0] unshfl4_d;\n logic [31:0] unshfl_d;\n\n\n assign unshfl1_d[31:0] = (rs2_in[0]) ? {rs1_in[31],rs1_in[29],rs1_in[30],rs1_in[28],rs1_in[27],rs1_in[25],rs1_in[26],rs1_in[24],\n rs1_in[23],rs1_in[21],rs1_in[22],rs1_in[20],rs1_in[19],rs1_in[17],rs1_in[18],rs1_in[16],\n rs1_in[15],rs1_in[13],rs1_in[14],rs1_in[12],rs1_in[11],rs1_in[09],rs1_in[10],rs1_in[08],\n rs1_in[07],rs1_in[05],rs1_in[06],rs1_in[04],rs1_in[03],rs1_in[01],rs1_in[02],rs1_in[00]} : rs1_in[31:0];\n\n assign unshfl2_d[31:0] = (rs2_in[1]) ? {unshfl1_d[31:30],unshfl1_d[27:26],unshfl1_d[29:28],unshfl1_d[25:24],\n unshfl1_d[23:22],unshfl1_d[19:18],unshfl1_d[21:20],unshfl1_d[17:16],\n unshfl1_d[15:14],unshfl1_d[11:10],unshfl1_d[13:12],unshfl1_d[09:08],\n unshfl1_d[07:06],unshfl1_d[03:02],unshfl1_d[05:04],unshfl1_d[01:00]} : unshfl1_d[31:0];\n\n assign unshfl4_d[31:0] = (rs2_in[2]) ? {unshfl2_d[31:28],unshfl2_d[23:20],unshfl2_d[27:24],unshfl2_d[19:16],\n unshfl2_d[15:12],unshfl2_d[07:04],unshfl2_d[11:08],unshfl2_d[03:00]} : unshfl2_d[31:0];\n\n assign unshfl_d[31:0] = (rs2_in[3]) ? {unshfl4_d[31:24],unshfl4_d[15:08],unshfl4_d[23:16],unshfl4_d[07:00]} : unshfl4_d[31:0];\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : XPERM * * * * * * * * * * * * * * * * *\n\n//\n// These instructions operate on nibbles/bytes/half-words/words.\n// rs1 is a vector of data words and rs2 is a vector of indices into rs1.\n// The result of the instruction is the vector rs2 with each element replaced by the corresponding data word from rs1,\n// or zero then the index in rs2 is out of bounds.\n//\n// uint_xlen_t xperm(uint_xlen_t rs1, uint_xlen_t rs2, int sz_log2)\n// {\n// uint_xlen_t r = 0;\n// uint_xlen_t sz = 1LL << sz_log2;\n// uint_xlen_t mask = (1LL << sz) - 1;\n// for (int i = 0; i < XLEN; i += sz)\n// { uint_xlen_t pos = ((rs2 >> i) & mask) << sz_log2;\n// if (pos < XLEN)\n// r |= ((rs1 >> pos) & mask) << i;\n// }\n// return r;\n// }\n//\n// uint_xlen_t xperm_n (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 2); }\n// uint_xlen_t xperm_b (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 3); }\n// uint_xlen_t xperm_h (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 4); }\n// uint_xlen_t xperm_w (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 5); } Not part of RV32\n//\n// The xperm.[nbhw] instructions can be implemented with an XLEN/4-lane nibble-wide crossbarswitch.\n\n// *** XPERM_B ***\n\n // XLEN = 32\n // SZ_LOG2 = 3\n // SZ = 4'd8;\n // MASK = ( 1 << 8 ) - 1\n // = 8'hFF\n\n // integer xperm_b_i;\n // logic [31:0] xperm_b_r;\n // logic [3:0] xperm_b_sz;\n // logic [7:0] xperm_b_mask;\n // logic [31:0] xperm_b_pos;\n //\n //\n // assign xperm_b_sz[3:0] = 4'd8;\n // assign xperm_b_mask[7:0] = 8'hff;\n //\n // always_comb\n // begin\n // xperm_b_r[31:0] = 32'b0;\n //\n // for (xperm_b_i=0; xperm_b_i<32; xperm_b_i = xperm_b_i + xperm_b_sz) // This code did not work...\n // begin\n // xperm_b_pos[31:0] = ( (rs2_in[31:0] >> xperm_b_i) & {24'h0,xperm_b_mask[7:0]} ) << 3;\n // if (xperm_b_pos[31:0] < 32'd32)\n // xperm_b_r[31:0] = xperm_b_r[31:0] | ( ((rs1_in[31:0] >> xperm_b_pos[4:0]) & {24'h0,xperm_b_mask[7:0]}) << xperm_b_i );\n // end\n // end\n\n logic [31:0] xperm_n;\n logic [31:0] xperm_b;\n logic [31:0] xperm_h;\n\n assign xperm_n[03:00] = { 4{ ~rs2_in[03] }} & 4'( (rs1_in[31:0] >> {rs2_in[02:00],2'b0}) & 4'hf ); // This is a 8:1 mux with qualified selects\n assign xperm_n[07:04] = { 4{ ~rs2_in[07] }} & 4'( (rs1_in[31:0] >> {rs2_in[06:04],2'b0}) & 4'hf );\n assign xperm_n[11:08] = { 4{ ~rs2_in[11] }} & 4'( (rs1_in[31:0] >> {rs2_in[10:08],2'b0}) & 4'hf );\n assign xperm_n[15:12] = { 4{ ~rs2_in[15] }} & 4'( (rs1_in[31:0] >> {rs2_in[14:12],2'b0}) & 4'hf );\n assign xperm_n[19:16] = { 4{ ~rs2_in[19] }} & 4'( (rs1_in[31:0] >> {rs2_in[18:16],2'b0}) & 4'hf );\n assign xperm_n[23:20] = { 4{ ~rs2_in[23] }} & 4'( (rs1_in[31:0] >> {rs2_in[22:20],2'b0}) & 4'hf );\n assign xperm_n[27:24] = { 4{ ~rs2_in[27] }} & 4'( (rs1_in[31:0] >> {rs2_in[26:24],2'b0}) & 4'hf );\n assign xperm_n[31:28] = { 4{ ~rs2_in[31] }} & 4'( (rs1_in[31:0] >> {rs2_in[30:28],2'b0}) & 4'hf );\n\n assign xperm_b[07:00] = { 8{ ~(| rs2_in[07:02]) }} & 8'( (rs1_in[31:0] >> {rs2_in[01:00],3'b0}) & 8'hff ); // This is a 4:1 mux with qualified selects\n assign xperm_b[15:08] = { 8{ ~(| rs2_in[15:10]) }} & 8'( (rs1_in[31:0] >> {rs2_in[09:08],3'b0}) & 8'hff );\n assign xperm_b[23:16] = { 8{ ~(| rs2_in[23:18]) }} & 8'( (rs1_in[31:0] >> {rs2_in[17:16],3'b0}) & 8'hff );\n assign xperm_b[31:24] = { 8{ ~(| rs2_in[31:26]) }} & 8'( (rs1_in[31:0] >> {rs2_in[25:24],3'b0}) & 8'hff );\n\n assign xperm_h[15:00] = {16{ ~(| rs2_in[15:01]) }} & 16'( (rs1_in[31:0] >> {rs2_in[00] ,4'b0}) & 16'hffff ); // This is a 2:1 mux with qualified selects\n assign xperm_h[31:16] = {16{ ~(| rs2_in[31:17]) }} & 16'( (rs1_in[31:0] >> {rs2_in[16] ,4'b0}) & 16'hffff );\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : CRC32, CRC32c * * * * * * * * * * * * * * * * *\n\n // *** computed from https: //crccalc.com ***\n //\n // \"a\" is 8'h61 = 8'b0110_0001 (8'h61 ^ 8'hff = 8'h9e)\n //\n // Input must first be XORed with 32'hffff_ffff\n //\n //\n // CRC32\n //\n // Input Output Input Output\n // ----- -------- -------- --------\n // \"a\" e8b7be43 ffffff9e 174841bc\n // \"aa\" 078a19d7 ffff9e9e f875e628\n // \"aaaa\" ad98e545 9e9e9e9e 5267a1ba\n //\n //\n //\n // CRC32c\n //\n // Input Output Input Output\n // ----- -------- -------- --------\n // \"a\" c1d04330 ffffff9e 3e2fbccf\n // \"aa\" f1f2dac2 ffff9e9e 0e0d253d\n // \"aaaa\" 6a52eeb0 9e9e9e9e 95ad114f\n\n\n logic crc32_all;\n logic [31:0] crc32_poly_rev;\n logic [31:0] crc32c_poly_rev;\n integer crc32_bi, crc32_hi, crc32_wi, crc32c_bi, crc32c_hi, crc32c_wi;\n logic [31:0] crc32_bd, crc32_hd, crc32_wd, crc32c_bd, crc32c_hd, crc32c_wd;\n\n\n assign crc32_all = ap_crc32_b | ap_crc32_h | ap_crc32_w | ap_crc32c_b | ap_crc32c_h | ap_crc32c_w;\n\n assign crc32_poly_rev[31:0] = 32'hEDB88320; // bit reverse of 32'h04C11DB7\n assign crc32c_poly_rev[31:0] = 32'h82F63B78; // bit reverse of 32'h1EDC6F41\n\n\n always_comb\n begin\n crc32_bd[31:0] = rs1_in[31:0];\n\n for (crc32_bi=0; crc32_bi<8; crc32_bi++)\n begin\n crc32_bd[31:0] = (crc32_bd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32{crc32_bd[0]}});\n end // FOR crc32_bi\n end // ALWAYS_COMB\n\n\n always_comb\n begin\n crc32_hd[31:0] = rs1_in[31:0];\n\n for (crc32_hi=0; crc32_hi<16; crc32_hi++)\n begin\n crc32_hd[31:0] = (crc32_hd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32{crc32_hd[0]}});\n end // FOR crc32_hi\n end // ALWAYS_COMB\n\n\n always_comb\n begin\n crc32_wd[31:0] = rs1_in[31:0];\n\n for (crc32_wi=0; crc32_wi<32; crc32_wi++)\n begin\n crc32_wd[31:0] = (crc32_wd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32{crc32_wd[0]}});\n end // FOR crc32_wi\n end // ALWAYS_COMB\n\n\n\n\n always_comb\n begin\n crc32c_bd[31:0] = rs1_in[31:0];\n\n for (crc32c_bi=0; crc32c_bi<8; crc32c_bi++)\n begin\n crc32c_bd[31:0] = (crc32c_bd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32{crc32c_bd[0]}});\n end // FOR crc32c_bi\n end // ALWAYS_COMB\n\n\n always_comb\n begin\n crc32c_hd[31:0] = rs1_in[31:0];\n\n for (crc32c_hi=0; crc32c_hi<16; crc32c_hi++)\n begin\n crc32c_hd[31:0] = (crc32c_hd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32{crc32c_hd[0]}});\n end // FOR crc32c_hi\n end // ALWAYS_COMB\n\n\n always_comb\n begin\n crc32c_wd[31:0] = rs1_in[31:0];\n\n for (crc32c_wi=0; crc32c_wi<32; crc32c_wi++)\n begin\n crc32c_wd[31:0] = (crc32c_wd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32{crc32c_wd[0]}});\n end // FOR crc32c_wi\n end // ALWAYS_COMB\n\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : BFP * * * * * * * * * * * * * * * * * *\n\n\n // uint_xlen_t bfp(uint_xlen_t rs1, uint_xlen_t rs2)\n // {\n // uint_xlen_t cfg = rs2 >> (XLEN/2);\n // if ((cfg >> 30) == 2) cfg = cfg >> 16;\n // int len = (cfg >> 8) & (XLEN/2-1);\n // int off = cfg & (XLEN-1);\n // len = len ? len : XLEN/2;\n // uint_xlen_t mask = slo(0, len) << off;\n // uint_xlen_t data = rs2 << off;\n // return (data & mask) | (rs1 & ~mask);\n\n\n logic [4:0] bfp_len;\n logic [4:0] bfp_off;\n logic [31:0] bfp_len_mask_;\n logic [31:0] bfp_off_mask_;\n logic [15:0] bfp_preshift_data;\n logic [31:0] bfp_shift_data;\n logic [31:0] bfp_shift_mask;\n logic [31:0] bfp_result_d;\n\n\n assign bfp_len[3:0] = rs2_in[27:24];\n assign bfp_len[4] = (bfp_len[3:0] == 4'b0); // If LEN field is zero, then LEN=16\n assign bfp_off[4:0] = rs2_in[20:16];\n\n assign bfp_len_mask_[31:0] = 32'hffff_ffff << bfp_len[4:0];\n assign bfp_off_mask_[31:0] = 32'hffff_ffff << bfp_off[4:0];\n assign bfp_preshift_data[15:0]= rs2_in[15:0] & ~bfp_len_mask_[15:0];\n\n assign bfp_shift_data[31:0] = {16'b0,bfp_preshift_data[15:0]} << bfp_off[4:0];\n assign bfp_shift_mask[31:0] = (bfp_len_mask_[31:0] << bfp_off[4:0]) | ~bfp_off_mask_[31:0];\n\n assign bfp_result_d[31:0] = bfp_shift_data[31:0] | (rs1_in[31:0] & bfp_shift_mask[31:0]);\n\n\n\n\n // * * * * * * * * * * * * * * * * * * BitManip : Common logic * * * * * * * * * * * * * * * * * *\n\n\n assign bitmanip_sel_d = ap_bcompress | ap_bdecompress | ap_clmul | ap_clmulh | ap_clmulr | ap_grev | ap_gorc | ap_shfl | ap_unshfl | crc32_all | ap_bfp | ap_xperm_n | ap_xperm_b | ap_xperm_h;\n\n assign bitmanip_d[31:0] = ( {32{ap_bcompress}} & bcompress_d[31:0] ) |\n ( {32{ap_bdecompress}} & bdecompress_d[31:0] ) |\n ( {32{ap_clmul}} & clmul_raw_d[31:0] ) |\n ( {32{ap_clmulh}} & {1'b0,clmul_raw_d[62:32]} ) |\n ( {32{ap_clmulr}} & clmul_raw_d[62:31] ) |\n ( {32{ap_grev}} & grev_d[31:0] ) |\n ( {32{ap_gorc}} & gorc_d[31:0] ) |\n ( {32{ap_shfl}} & shfl_d[31:0] ) |\n ( {32{ap_unshfl}} & unshfl_d[31:0] ) |\n ( {32{ap_crc32_b}} & crc32_bd[31:0] ) |\n ( {32{ap_crc32_h}} & crc32_hd[31:0] ) |\n ( {32{ap_crc32_w}} & crc32_wd[31:0] ) |\n ( {32{ap_crc32c_b}} & crc32c_bd[31:0] ) |\n ( {32{ap_crc32c_h}} & crc32c_hd[31:0] ) |\n ( {32{ap_crc32c_w}} & crc32c_wd[31:0] ) |\n ( {32{ap_bfp}} & bfp_result_d[31:0] ) |\n ( {32{ap_xperm_n}} & xperm_n[31:0] ) |\n ( {32{ap_xperm_b}} & xperm_b[31:0] ) |\n ( {32{ap_xperm_h}} & xperm_h[31:0] );\n\n\n\n rvdffe #(33) i_bitmanip_ff (.*, .clk(clk), .din({bitmanip_sel_d,bitmanip_d[31:0]}), .dout({bitmanip_sel_x,bitmanip_x[31:0]}), .en(bit_x_enable));\n\n\n\n\n assign result_x[31:0] = ( {32{~bitmanip_sel_x & ~low_x}} & prod_x[63:32] ) |\n ( {32{~bitmanip_sel_x & low_x}} & prod_x[31:0] ) |\n bitmanip_x[31:0];\n\n\n\nendmodule // el2_exu_mul_ctl\n" }, { "path": "design/flist", "content": "$RV_ROOT/design/el2_veer_wrapper.sv\n$RV_ROOT/design/el2_veer_lockstep.sv\n$RV_ROOT/design/el2_mem.sv\n$RV_ROOT/design/el2_pic_ctrl.sv\n$RV_ROOT/design/el2_veer.sv\n$RV_ROOT/design/el2_dma_ctrl.sv\n$RV_ROOT/design/el2_pmp.sv\n$RV_ROOT/design/ifu/el2_ifu_aln_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_compress_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_ifc_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_bp_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_ic_mem.sv\n$RV_ROOT/design/ifu/el2_ifu_mem_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_iccm_mem.sv\n$RV_ROOT/design/ifu/el2_ifu.sv\n$RV_ROOT/design/dec/el2_dec_decode_ctl.sv\n$RV_ROOT/design/dec/el2_dec_gpr_ctl.sv\n$RV_ROOT/design/dec/el2_dec_ib_ctl.sv\n$RV_ROOT/design/dec/el2_dec_pmp_ctl.sv\n$RV_ROOT/design/dec/el2_dec_tlu_ctl.sv\n$RV_ROOT/design/dec/el2_dec_trigger.sv\n$RV_ROOT/design/dec/el2_dec.sv\n$RV_ROOT/design/exu/el2_exu_alu_ctl.sv\n$RV_ROOT/design/exu/el2_exu_mul_ctl.sv\n$RV_ROOT/design/exu/el2_exu_div_ctl.sv\n$RV_ROOT/design/exu/el2_exu.sv\n$RV_ROOT/design/lsu/el2_lsu.sv\n$RV_ROOT/design/lsu/el2_lsu_clkdomain.sv\n$RV_ROOT/design/lsu/el2_lsu_addrcheck.sv\n$RV_ROOT/design/lsu/el2_lsu_lsc_ctl.sv\n$RV_ROOT/design/lsu/el2_lsu_stbuf.sv\n$RV_ROOT/design/lsu/el2_lsu_bus_buffer.sv\n$RV_ROOT/design/lsu/el2_lsu_bus_intf.sv\n$RV_ROOT/design/lsu/el2_lsu_ecc.sv\n$RV_ROOT/design/lsu/el2_lsu_dccm_mem.sv\n$RV_ROOT/design/lsu/el2_lsu_dccm_ctl.sv\n$RV_ROOT/design/lsu/el2_lsu_trigger.sv\n$RV_ROOT/design/dbg/el2_dbg.sv\n$RV_ROOT/design/dmi/dmi_mux.v\n$RV_ROOT/design/dmi/dmi_wrapper.v\n$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v\n$RV_ROOT/design/dmi/rvjtag_tap.v\n$RV_ROOT/design/lib/el2_lib.sv\n$RV_ROOT/design/lib/el2_mem_if.sv\n-v $RV_ROOT/design/lib/beh_lib.sv\n-v $RV_ROOT/design/lib/mem_lib.sv\n$RV_ROOT/design/lib/ahb_to_axi4.sv\n$RV_ROOT/design/lib/axi4_to_ahb.sv\n" }, { "path": "design/flist.formal", "content": "#-*-dotf-*-\n\n$RV_ROOT/design/include/el2_def.sv\n\n+incdir+$RV_ROOT/design/lib\n+incdir+$RV_ROOT/design/include\n+incdir+$RV_ROOT/design/dmi\n\n//|+incdir+$SYNOPSYS_SYN_ROOT/dw/sim_ver\n//|-y $SYNOPSYS_SYN_ROOT/dw/sim_ver\n//|\n//|$SYNOPSYS_SYN_ROOT/dw/sim_ver/DW01_addsub.v\n//|$SYNOPSYS_SYN_ROOT/dw/sim_ver/DW_lzd.v\n//|$SYNOPSYS_SYN_ROOT/dw/sim_ver/DW_minmax.v\n//|$SYNOPSYS_SYN_ROOT/dw/sim_ver/DW02_mult.v\n\n+incdir+/wdc/apps/mentor/questa/formal/2019.2/share/MODIFIED/dw\n+incdir+/wdc/apps/mentor/questa/formal/2019.2/share/MODIFIED/dw/dw_datapath\n /wdc/apps/mentor/questa/formal/2019.2/share/MODIFIED/dw/dw.remodel.v\n\n$RV_ROOT/design/el2_veer_wrapper.sv\n$RV_ROOT/design/el2_veer_lockstep.sv\n$RV_ROOT/design/el2_mem.sv\n$RV_ROOT/design/el2_pic_ctrl.sv\n$RV_ROOT/design/el2_veer.sv\n$RV_ROOT/design/el2_dma_ctrl.sv\n$RV_ROOT/design/el2_pmp.sv\n$RV_ROOT/design/ifu/el2_ifu_aln_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_compress_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_ifc_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_bp_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_ic_mem.sv\n$RV_ROOT/design/ifu/el2_ifu_mem_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_iccm_mem.sv\n$RV_ROOT/design/ifu/el2_ifu.sv\n$RV_ROOT/design/dec/el2_dec_decode_ctl.sv\n$RV_ROOT/design/dec/el2_dec_gpr_ctl.sv\n$RV_ROOT/design/dec/el2_dec_ib_ctl.sv\n$RV_ROOT/design/dec/el2_dec_pmp_ctl.sv\n$RV_ROOT/design/dec/el2_dec_tlu_ctl.sv\n$RV_ROOT/design/dec/el2_dec_trigger.sv\n$RV_ROOT/design/dec/el2_dec.sv\n$RV_ROOT/design/exu/el2_exu_alu_ctl.sv\n$RV_ROOT/design/exu/el2_exu_mul_ctl.sv\n$RV_ROOT/design/exu/el2_exu_div_ctl.sv\n$RV_ROOT/design/exu/el2_exu.sv\n$RV_ROOT/design/lsu/el2_lsu.sv\n$RV_ROOT/design/lsu/el2_lsu_clkdomain.sv\n$RV_ROOT/design/lsu/el2_lsu_addrcheck.sv\n$RV_ROOT/design/lsu/el2_lsu_lsc_ctl.sv\n$RV_ROOT/design/lsu/el2_lsu_stbuf.sv\n$RV_ROOT/design/lsu/el2_lsu_bus_buffer.sv\n$RV_ROOT/design/lsu/el2_lsu_bus_intf.sv\n$RV_ROOT/design/lsu/el2_lsu_ecc.sv\n$RV_ROOT/design/lsu/el2_lsu_dccm_mem.sv\n$RV_ROOT/design/lsu/el2_lsu_dccm_ctl.sv\n$RV_ROOT/design/lsu/el2_lsu_trigger.sv\n$RV_ROOT/design/dbg/el2_dbg.sv\n$RV_ROOT/design/dmi/dmi_mux.v\n$RV_ROOT/design/dmi/dmi_wrapper.v\n$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v\n$RV_ROOT/design/dmi/rvjtag_tap.v\n$RV_ROOT/design/lib/el2_lib.sv\n$RV_ROOT/design/lib/el2_mem_if.sv\n$RV_ROOT/design/lib/beh_lib.sv\n$RV_ROOT/design/lib/mem_lib.sv\n$RV_ROOT/design/lib/ahb_to_axi4.sv\n$RV_ROOT/design/lib/axi4_to_ahb.sv\n" }, { "path": "design/flist.lint", "content": "+libext+.v+.sv\n+define+RV_OPENSOURCE\n+incdir+$RV_ROOT/design/include\n+incdir+$RV_ROOT/design/lib\n+incdir+$RV_ROOT/design/include\n+incdir+$RV_ROOT/snapshots/default\n$RV_ROOT/snapshots/default/common_defines.vh\n$RV_ROOT/design/include/el2_def.sv\n$RV_ROOT/design/el2_veer_wrapper.sv\n$RV_ROOT/design/lib/el2_mem_if.sv\n$RV_ROOT/design/el2_mem.sv\n$RV_ROOT/design/el2_pic_ctrl.sv\n$RV_ROOT/design/el2_veer.sv\n$RV_ROOT/design/el2_dma_ctrl.sv\n$RV_ROOT/design/el2_pmp.sv\n$RV_ROOT/design/ifu/el2_ifu_aln_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_compress_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_ifc_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_bp_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_ic_mem.sv\n$RV_ROOT/design/ifu/el2_ifu_mem_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_iccm_mem.sv\n$RV_ROOT/design/ifu/el2_ifu.sv\n$RV_ROOT/design/dec/el2_dec_decode_ctl.sv\n$RV_ROOT/design/dec/el2_dec_gpr_ctl.sv\n$RV_ROOT/design/dec/el2_dec_ib_ctl.sv\n$RV_ROOT/design/dec/el2_dec_pmp_ctl.sv\n$RV_ROOT/design/dec/el2_dec_tlu_ctl.sv\n$RV_ROOT/design/dec/el2_dec_trigger.sv\n$RV_ROOT/design/dec/el2_dec.sv\n$RV_ROOT/design/exu/el2_exu_alu_ctl.sv\n$RV_ROOT/design/exu/el2_exu_mul_ctl.sv\n$RV_ROOT/design/exu/el2_exu_div_ctl.sv\n$RV_ROOT/design/exu/el2_exu.sv\n$RV_ROOT/design/lsu/el2_lsu.sv\n$RV_ROOT/design/lsu/el2_lsu_clkdomain.sv\n$RV_ROOT/design/lsu/el2_lsu_addrcheck.sv\n$RV_ROOT/design/lsu/el2_lsu_lsc_ctl.sv\n$RV_ROOT/design/lsu/el2_lsu_stbuf.sv\n$RV_ROOT/design/lsu/el2_lsu_bus_buffer.sv\n$RV_ROOT/design/lsu/el2_lsu_bus_intf.sv\n$RV_ROOT/design/lsu/el2_lsu_ecc.sv\n$RV_ROOT/design/lsu/el2_lsu_dccm_mem.sv\n$RV_ROOT/design/lsu/el2_lsu_dccm_ctl.sv\n$RV_ROOT/design/lsu/el2_lsu_trigger.sv\n$RV_ROOT/design/dbg/el2_dbg.sv\n$RV_ROOT/design/dmi/dmi_mux.v\n$RV_ROOT/design/dmi/dmi_wrapper.v\n$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v\n$RV_ROOT/design/dmi/rvjtag_tap.v\n$RV_ROOT/design/lib/el2_lib.sv\n$RV_ROOT/design/lib/beh_lib.sv\n" }, { "path": "design/flist.questa", "content": "#-*-dotf-*-\n\n# $RV_ROOT/workspace/work/snapshots/default/common_defines.vh\n# $RV_ROOT/configs/snapshots/default/common_defines.vh\n$RV_ROOT/workspace/work/snapshots/default/common_defines.vh\n\n\n$RV_ROOT/design/include/el2_def.sv\n\n# +incdir+$RV_ROOT/workspace/work/snapshots/default\n# +incdir+$RV_ROOT/configs/snapshots/default\n+incdir+$RV_ROOT/workspace/work/snapshots/default\n\n+incdir+$RV_ROOT/design/lib\n+incdir+$RV_ROOT/design/include\n+incdir+$RV_ROOT/design/dmi\n+incdir+$SYNOPSYS_SYN_ROOT/dw/sim_ver\n-y $SYNOPSYS_SYN_ROOT/dw/sim_ver\n$RV_ROOT/design/el2_veer_wrapper.sv\n$RV_ROOT/design/el2_veer_lockstep.sv\n$RV_ROOT/design/el2_mem.sv\n$RV_ROOT/design/el2_pic_ctrl.sv\n$RV_ROOT/design/el2_veer.sv\n$RV_ROOT/design/el2_dma_ctrl.sv\n$RV_ROOT/design/el2_pmp.sv\n$RV_ROOT/design/ifu/el2_ifu_aln_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_compress_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_ifc_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_bp_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_ic_mem.sv\n$RV_ROOT/design/ifu/el2_ifu_mem_ctl.sv\n$RV_ROOT/design/ifu/el2_ifu_iccm_mem.sv\n$RV_ROOT/design/ifu/el2_ifu.sv\n$RV_ROOT/design/dec/el2_dec_decode_ctl.sv\n$RV_ROOT/design/dec/el2_dec_gpr_ctl.sv\n$RV_ROOT/design/dec/el2_dec_ib_ctl.sv\n$RV_ROOT/design/dec/el2_dec_pmp_ctl.sv\n$RV_ROOT/design/dec/el2_dec_tlu_ctl.sv\n$RV_ROOT/design/dec/el2_dec_trigger.sv\n$RV_ROOT/design/dec/el2_dec.sv\n$RV_ROOT/design/exu/el2_exu_alu_ctl.sv\n$RV_ROOT/design/exu/el2_exu_mul_ctl.sv\n$RV_ROOT/design/exu/el2_exu_div_ctl.sv\n$RV_ROOT/design/exu/el2_exu.sv\n$RV_ROOT/design/lsu/el2_lsu.sv\n$RV_ROOT/design/lsu/el2_lsu_clkdomain.sv\n$RV_ROOT/design/lsu/el2_lsu_addrcheck.sv\n$RV_ROOT/design/lsu/el2_lsu_lsc_ctl.sv\n$RV_ROOT/design/lsu/el2_lsu_stbuf.sv\n$RV_ROOT/design/lsu/el2_lsu_bus_buffer.sv\n$RV_ROOT/design/lsu/el2_lsu_bus_intf.sv\n$RV_ROOT/design/lsu/el2_lsu_ecc.sv\n$RV_ROOT/design/lsu/el2_lsu_dccm_mem.sv\n$RV_ROOT/design/lsu/el2_lsu_dccm_ctl.sv\n$RV_ROOT/design/lsu/el2_lsu_trigger.sv\n$RV_ROOT/design/dbg/el2_dbg.sv\n$RV_ROOT/design/dmi/dmi_mux.v\n$RV_ROOT/design/dmi/dmi_wrapper.v\n$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v\n$RV_ROOT/design/dmi/rvjtag_tap.v\n$RV_ROOT/design/lib/el2_lib.sv\n$RV_ROOT/design/lib/el2_mem_if.sv\n$RV_ROOT/design/lib/beh_lib.sv\n$RV_ROOT/design/lib/mem_lib.sv\n$RV_ROOT/design/lib/ahb_to_axi4.sv\n$RV_ROOT/design/lib/axi4_to_ahb.sv\n" }, { "path": "design/ifu/el2_ifu.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n//********************************************************************************\n// Function: Top level file for Icache, Fetch, Branch prediction & Aligner\n// BFF -> F1 -> F2 -> A\n//********************************************************************************\n\nmodule el2_ifu\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic rst_l, // reset, active low\n\n input logic dec_i0_decode_d, // Valid instruction at D and not blocked\n\n input logic exu_flush_final, // flush, includes upper and lower\n input logic dec_tlu_i0_commit_cmt , // committed i0\n input logic dec_tlu_flush_err_wb , // flush due to parity error.\n input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final\n input logic [31:1] exu_flush_path_final, // flush fetch address\n\n input logic [31:0] dec_tlu_mrac_ff ,// Side_effect , cacheable for each region\n input logic dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final\n input logic dec_tlu_flush_leak_one_wb, // ignore bp for leak one fetches\n\n input logic dec_tlu_bpred_disable, // disable all branch prediction\n input logic dec_tlu_core_ecc_disable, // disable ecc checking and flagging\n input logic dec_tlu_force_halt, // force halt\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */\n /*pragma coverage off*/\n output logic ifu_axi_awvalid,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,\n output logic [31:0] ifu_axi_awaddr,\n output logic [3:0] ifu_axi_awregion,\n output logic [7:0] ifu_axi_awlen,\n output logic [2:0] ifu_axi_awsize,\n output logic [1:0] ifu_axi_awburst,\n output logic ifu_axi_awlock,\n output logic [3:0] ifu_axi_awcache,\n output logic [2:0] ifu_axi_awprot,\n output logic [3:0] ifu_axi_awqos,\n\n output logic ifu_axi_wvalid,\n output logic [63:0] ifu_axi_wdata,\n output logic [7:0] ifu_axi_wstrb,\n output logic ifu_axi_wlast,\n\n output logic ifu_axi_bready,\n /*pragma coverage on*/\n\n // AXI Read Channels\n output logic ifu_axi_arvalid,\n input logic ifu_axi_arready,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,\n output logic [31:0] ifu_axi_araddr,\n output logic [3:0] ifu_axi_arregion,\n /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */\n /*pragma coverage off*/\n output logic [7:0] ifu_axi_arlen,\n output logic [2:0] ifu_axi_arsize,\n output logic [1:0] ifu_axi_arburst,\n output logic ifu_axi_arlock,\n output logic [3:0] ifu_axi_arcache,\n output logic [2:0] ifu_axi_arprot,\n output logic [3:0] ifu_axi_arqos,\n /*pragma coverage on*/\n\n input logic ifu_axi_rvalid,\n /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */\n /*pragma coverage off*/\n output logic ifu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,\n input logic [63:0] ifu_axi_rdata,\n input logic [1:0] ifu_axi_rresp,\n\n input logic ifu_bus_clk_en,\n\n input logic dma_iccm_req,\n input logic [31:0] dma_mem_addr,\n input logic [2:0] dma_mem_sz,\n input logic dma_mem_write,\n input logic [63:0] dma_mem_wdata,\n input logic [2:0] dma_mem_tag, // DMA Buffer entry number\n\n\n input logic dma_iccm_stall_any,\n output logic iccm_dma_ecc_error,\n output logic iccm_dma_rvalid,\n output logic [63:0] iccm_dma_rdata,\n output logic [2:0] iccm_dma_rtag, // Tag of the DMA req\n output logic iccm_ready,\n\n output logic ifu_pmu_instr_aligned,\n output logic ifu_pmu_fetch_stall,\n output logic ifu_ic_error_start, // has all of the I$ ecc/parity for data/tag\n\n// I$ & ITAG Ports\n output logic [31:1] ic_rw_addr, // Read/Write addresss to the Icache.\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en, // Icache write enable, when filling the Icache.\n output logic ic_rd_en, // Icache read enable.\n\n output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC\n input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [25:0] ictag_debug_rd_data,// Debug icache tag.\n output logic [70:0] ic_debug_wr_data, // Debug wr cache.\n\n output logic [70:0] ifu_ic_debug_rd_data,\n\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, //\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,\n output logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.\n output logic ic_sel_premux_data, // Select the premux data.\n\n output logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.\n output logic ic_debug_rd_en, // Icache debug rd\n output logic ic_debug_wr_en, // Icache debug wr\n output logic ic_debug_tag_array, // Debug tag array\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.\n\n\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid bits when accessing the Icache. One valid bit per way. F2 stage\n\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, // Compare hits from Icache tags. Per way. F2 stage\n input logic ic_tag_perr, // Icache Tag parity error\n\n\n // ICCM ports\n output logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address.\n output logic iccm_wren, // ICCM write enable (through the DMA)\n output logic iccm_rden, // ICCM read enable.\n output logic [77:0] iccm_wr_data, // ICCM write data.\n output logic [2:0] iccm_wr_size, // ICCM write location within DW.\n\n input logic [63:0] iccm_rd_data, // Data read from ICCM.\n input logic [77:0] iccm_rd_data_ecc, // Data + ECC read from ICCM.\n\n // ICCM ECC status\n output logic ifu_iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error.\n output logic ifu_iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.\n output logic ifu_iccm_rd_ecc_double_err, // This fetch has a double ICCM ECC error.\n\n// Perf counter sigs\n output logic ifu_pmu_ic_miss, // ic miss\n output logic ifu_pmu_ic_hit, // ic hit\n output logic ifu_pmu_bus_error, // iside bus error\n output logic ifu_pmu_bus_busy, // iside bus busy\n output logic ifu_pmu_bus_trxn, // iside bus transactions\n\n\n output logic ifu_i0_icaf, // Instruction 0 access fault. From Aligner to Decode\n output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type\n\n output logic ifu_i0_valid, // Instruction 0 valid. From Aligner to Decode\n output logic ifu_i0_icaf_second, // Instruction 0 has access fault on second 2B of 4B inst\n output logic ifu_i0_dbecc, // Instruction 0 has double bit ecc error\n output logic iccm_dma_sb_error, // Single Bit ECC error from a DMA access\n output logic[31:0] ifu_i0_instr, // Instruction 0 . From Aligner to Decode\n output logic[31:1] ifu_i0_pc, // Instruction 0 pc. From Aligner to Decode\n output logic ifu_i0_pc4, // Instruction 0 is 4 byte. From Aligner to Decode\n\n output logic ifu_miss_state_idle, // There is no outstanding miss. Cache miss state is idle.\n\n output el2_br_pkt_t i0_brp, // Instruction 0 branch packet. From Aligner to Decode\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index\n output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR\n output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag\n output logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index\n\n input el2_predict_pkt_t exu_mp_pkt, // mispredict packet\n input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr\n input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index, // Mispredict index\n input logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag\n\n input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt\n input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index\n input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index\n\n input dec_tlu_flush_lower_wb,\n\n output logic [15:0] ifu_i0_cinst,\n\n output logic [31:1] ifu_pmp_addr,\n input logic ifu_pmp_error,\n\n/// Icache debug\n input el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt ,\n output logic ifu_ic_debug_rd_data_valid,\n output logic iccm_buf_correct_ecc,\n output logic iccm_correction_state,\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n );\n\n localparam TAGWIDTH = 2 ;\n localparam IDWIDTH = 2 ;\n\n logic ifu_fb_consume1, ifu_fb_consume2;\n logic [31:1] ifc_fetch_addr_f;\n logic [31:1] ifc_fetch_addr_bf;\n assign ifu_pmp_addr = ifc_fetch_addr_bf;\n\n logic [1:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch\n logic [31:1] ifu_fetch_pc; // starting pc of fetch\n\n logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;\n assign ifu_iccm_dma_rd_ecc_single_err = iccm_dma_rd_ecc_single_err;\n assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err;\n assign ifu_ic_error_start = ic_error_start;\n\n\n logic ic_write_stall;\n logic ic_dma_active;\n logic ifc_dma_access_ok;\n logic [1:0] ic_access_fault_f;\n logic [1:0] ic_access_fault_type_f;\n logic ifu_ic_mb_empty;\n\n logic ic_hit_f;\n\n logic [1:0] ifu_bp_way_f; // way indication; right justified\n logic ifu_bp_hit_taken_f; // kill next fetch; taken target found\n logic [31:1] ifu_bp_btb_target_f; // predicted target PC\n logic ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified\n logic [1:0] ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified\n logic [1:0] ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified\n logic [11:0] ifu_bp_poffset_f; // predicted target\n logic [1:0] ifu_bp_ret_f; // predicted ret ; right justified\n logic [1:0] ifu_bp_pc4_f; // pc4 indication; right justified\n logic [1:0] ifu_bp_valid_f; // branch valid, right justified\n logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;\n logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;\n\n\n logic [1:0] ic_fetch_val_f;\n logic [31:0] ic_data_f;\n logic [31:0] ifu_fetch_data_f;\n logic ifc_fetch_req_f;\n logic ifc_fetch_req_f_raw;\n logic iccm_dma_rd_ecc_double_err;\n logic [1:0] iccm_rd_ecc_double_err; // This fetch has an iccm double error.\n assign ifu_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err || |iccm_dma_rd_ecc_double_err;\n\n logic ifu_async_error_start;\n\n\n assign ifu_fetch_data_f[31:0] = ic_data_f[31:0];\n assign ifu_fetch_val[1:0] = ic_fetch_val_f[1:0];\n assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];\n\n logic ifc_fetch_uncacheable_bf; // The fetch request is uncacheable space. BF stage\n logic ifc_fetch_req_bf; // Fetch request. Comes with the address. BF stage\n logic ifc_fetch_req_bf_raw; // Fetch request without some qualifications. Used for clock-gating. BF stage\n logic ifc_iccm_access_bf; // This request is to the ICCM. Do not generate misses to the bus.\n logic ifc_region_acc_fault_bf; // Access fault. in ICCM region but offset is outside defined ICCM.\n\n // fetch control\n el2_ifu_ifc_ctl #(.pt(pt)) ifc (.*\n );\n\n // branch predictor\n if (pt.BTB_ENABLE==1) begin : bpred\n el2_ifu_bp_ctl #(.pt(pt)) bp (.*);\n end\n else begin : bpred\n assign ifu_bp_hit_taken_f = '0;\n // verif wires\n logic btb_wr_en_way0, btb_wr_en_way1,dec_tlu_error_wb;\n logic [16+pt.BTB_BTAG_SIZE:0] btb_wr_data;\n assign btb_wr_en_way0 = '0;\n assign btb_wr_en_way1 = '0;\n assign btb_wr_data = '0;\n assign dec_tlu_error_wb ='0;\n assign ifu_bp_inst_mask_f = 1'b1;\n end\n\n\n\n // aligner\n\n el2_ifu_aln_ctl #(.pt(pt)) aln (\n .*\n );\n\n\n // icache\n el2_ifu_mem_ctl #(.pt(pt)) mem_ctl\n (.*,\n .ic_data_f(ic_data_f[31:0])\n );\n\n\n\n // Performance debug info\n //\n //\n`ifdef DUMP_BTB_ON\n logic exu_mp_valid; // conditional branch mispredict\n logic exu_mp_way; // conditional branch mispredict\n logic exu_mp_ataken; // direction is actual taken\n logic exu_mp_boffset; // branch offsett\n logic exu_mp_pc4; // branch is a 4B inst\n logic exu_mp_call; // branch is a call inst\n logic exu_mp_ret; // branch is a ret inst\n logic exu_mp_ja; // branch is a jump always\n logic [1:0] exu_mp_hist; // new history\n logic [11:0] exu_mp_tgt; // target offset\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address\n\n assign exu_mp_valid = exu_mp_pkt.misp; // conditional branch mispredict\n assign exu_mp_ataken = exu_mp_pkt.ataken; // direction is actual taken\n assign exu_mp_boffset = exu_mp_pkt.boffset; // branch offset\n assign exu_mp_pc4 = exu_mp_pkt.pc4; // branch is a 4B inst\n assign exu_mp_call = exu_mp_pkt.pcall; // branch is a call inst\n assign exu_mp_ret = exu_mp_pkt.pret; // branch is a ret inst\n assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always\n assign exu_mp_way = exu_mp_pkt.way; // branch is a jump always\n assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history\n assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0] ; // target offset\n assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address\n\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_f;\n `define DEC `CPU_TOP.dec\n `define EXU `CPU_TOP.exu\n el2_btb_addr_hash f2hash(.pc(ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]), .hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));\n logic [31:0] mppc_ns, mppc;\n logic exu_flush_final_d1;\n assign mppc_ns[31:1] = `EXU.i0_flush_upper_x ? `EXU.exu_i0_pc_x : `EXU.dec_i0_pc_d;\n assign mppc_ns[0] = 1'b0;\n rvdff #(33) junk_ff (.*, .clk(active_clk), .din({mppc_ns[31:0], exu_flush_final}), .dout({mppc[31:0], exu_flush_final_d1}));\n logic tmp_bnk;\n assign tmp_bnk = bpred.bp.btb_sel_f[1];\n\n always @(negedge clk) begin\n if(`DEC.tlu.mcyclel[31:0] == 32'h0000_0010) begin\n $display(\"BTB_CONFIG: %d\",pt.BTB_SIZE);\n `ifndef BP_NOGSHARE\n $display(\"BHT_CONFIG: %d gshare: 1\",pt.BHT_SIZE);\n `else\n $display(\"BHT_CONFIG: %d gshare: 0\",pt.BHT_SIZE);\n `endif\n $display(\"RS_CONFIG: %d\", pt.RET_STACK_SIZE);\n end\n if(exu_flush_final_d1 & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error) & (exu_mp_pkt.misp | exu_mp_pkt.ataken))\n $display(\"%7d BTB_MP : index: %0h bank: %0h call: %b ret: %b ataken: %b hist: %h valid: %b tag: %h targ: %h eghr: %b pred: %b ghr_index: %h brpc: %h way: %h\", `DEC.tlu.mcyclel[31:0]+32'ha, exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO], 1'b0, exu_mp_call, exu_mp_ret, exu_mp_ataken, exu_mp_hist[1:0], exu_mp_valid, exu_mp_btag[pt.BTB_BTAG_SIZE-1:0], {exu_flush_path_final[31:1], 1'b0}, exu_mp_eghr[pt.BHT_GHR_SIZE-1:0], exu_mp_valid, bpred.bp.bht_wr_addr0, mppc[31:0], exu_mp_pkt.way);\n\n for(int i = 0; i < 8; i++) begin\n if(ifu_bp_valid_f[i] & ifc_fetch_req_f)\n $display(\"%7d BTB_HIT : index: %0h bank: %0h call: %b ret: %b taken: %b strength: %b tag: %h targ: %0h ghr: %4b ghr_index: %h way: %h\", `DEC.tlu.mcyclel[31:0]+32'ha,btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],bpred.bp.btb_sel_f[1], bpred.bp.btb_rd_call_f, bpred.bp.btb_rd_ret_f, ifu_bp_hist1_f[tmp_bnk], ifu_bp_hist0_f[tmp_bnk], bpred.bp.fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0], {ifu_bp_btb_target_f[31:1], 1'b0}, bpred.bp.fghr[pt.BHT_GHR_SIZE-1:0], bpred.bp.bht_rd_addr_f, ifu_bp_way_f[tmp_bnk]);\n end\n if(dec_tlu_br0_r_pkt.valid & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error))\n $display(\"%7d BTB_UPD0: ghr_index: %0h bank: %0h hist: %h way: %h\", `DEC.tlu.mcyclel[31:0]+32'ha,bpred.bp.br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO],{dec_tlu_br0_r_pkt.middle}, dec_tlu_br0_r_pkt.hist, dec_tlu_br0_r_pkt.way);\n\n if(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error)\n $display(\"%7d BTB_ERR0: index: %0h bank: %0h start: %b rfpc: %h way: %h\", `DEC.tlu.mcyclel[31:0]+32'ha,exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],1'b0, dec_tlu_br0_r_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br0_r_pkt.way);\n end // always @ (negedge clk)\n function [1:0] encode4_2;\n input [3:0] in;\n\n encode4_2[1] = in[3] | in[2];\n encode4_2[0] = in[3] | in[1];\n\n endfunction\n`endif\nendmodule // el2_ifu\n" }, { "path": "design/ifu/el2_ifu_aln_ctl.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n\n//********************************************************************************\n// Function: Instruction aligner\n//********************************************************************************\nmodule el2_ifu_aln_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // Flop scan mode control\n /*pragma coverage on*/\n input logic rst_l, // reset, active low\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n\n input logic ifu_async_error_start, // ecc/parity related errors with current fetch - not sent down the pipe\n\n input logic [1:0] iccm_rd_ecc_double_err, // This fetch has a double ICCM ecc error.\n\n input logic [1:0] ic_access_fault_f, // Instruction access fault for the current fetch.\n input logic [1:0] ic_access_fault_type_f, // Instruction access fault types\n\n input logic exu_flush_final, // Flush from the pipeline.\n\n input logic dec_i0_decode_d, // Valid instruction at D-stage and not blocked\n\n input logic [31:0] ifu_fetch_data_f, // fetch data in memory format - not right justified\n\n input logic [1:0] ifu_fetch_val, // valids on a 2B boundary, right justified\n input logic [31:1] ifu_fetch_pc, // starting pc of fetch\n\n\n\n output logic ifu_i0_valid, // Instruction 0 is valid\n output logic ifu_i0_icaf, // Instruction 0 has access fault\n output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type\n output logic ifu_i0_icaf_second, // Instruction 0 has access fault on second 2B of 4B inst\n\n output logic ifu_i0_dbecc, // Instruction 0 has double bit ecc error\n output logic [31:0] ifu_i0_instr, // Instruction 0\n output logic [31:1] ifu_i0_pc, // Instruction 0 PC\n output logic ifu_i0_pc4,\n\n output logic ifu_fb_consume1, // Consumed one buffer. To fetch control fetch for buffer mass balance\n output logic ifu_fb_consume2, // Consumed two buffers.To fetch control fetch for buffer mass balance\n\n\n input logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch GHR\n input logic [31:1] ifu_bp_btb_target_f, // predicted RET target\n input logic [11:0] ifu_bp_poffset_f, // predicted target offset\n input logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f, // predicted branch index (fully associative option)\n\n input logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 1, right justified\n input logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified\n input logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified\n input logic [1:0] ifu_bp_way_f, // way indication, right justified\n input logic [1:0] ifu_bp_valid_f, // branch valid, right justified\n input logic [1:0] ifu_bp_ret_f, // predicted ret indication, right justified\n\n\n output el2_br_pkt_t i0_brp, // Branch packet for I0.\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index\n output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR\n output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag\n\n output logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index\n\n output logic ifu_pmu_instr_aligned, // number of inst aligned this cycle\n\n output logic [15:0] ifu_i0_cinst // 16b compress inst for i0\n );\n\n\n\n logic ifvalid;\n logic shift_f1_f0, shift_f2_f0, shift_f2_f1;\n logic fetch_to_f0, fetch_to_f1, fetch_to_f2;\n\n logic [1:0] f2val_in, f2val;\n logic [1:0] f1val_in, f1val;\n logic [1:0] f0val_in, f0val;\n logic [1:0] sf1val, sf0val;\n\n logic [31:0] aligndata;\n logic first4B, first2B;\n\n logic [31:0] uncompress0;\n logic i0_shift;\n logic shift_2B, shift_4B;\n logic f1_shift_2B;\n logic f2_valid, sf1_valid, sf0_valid;\n\n logic [31:0] ifirst;\n logic [1:0] alignval;\n logic [31:1] firstpc, secondpc;\n\n logic [11:0] f1poffset;\n logic [11:0] f0poffset;\n logic [pt.BHT_GHR_SIZE-1:0] f1fghr;\n logic [pt.BHT_GHR_SIZE-1:0] f0fghr;\n logic [1:0] f1hist1;\n logic [1:0] f0hist1;\n logic [1:0] f1hist0;\n logic [1:0] f0hist0;\n\n logic [1:0][$clog2(pt.BTB_SIZE)-1:0] f0index, f1index, alignindex;\n\n logic [1:0] f1ictype;\n logic [1:0] f0ictype;\n\n logic [1:0] f1pc4;\n logic [1:0] f0pc4;\n\n logic [1:0] f1ret;\n logic [1:0] f0ret;\n logic [1:0] f1way;\n logic [1:0] f0way;\n\n logic [1:0] f1brend;\n logic [1:0] f0brend;\n\n logic [1:0] alignbrend;\n logic [1:0] alignpc4;\n\n logic [1:0] alignret;\n logic [1:0] alignway;\n logic [1:0] alignhist1;\n logic [1:0] alignhist0;\n logic [1:1] alignfromf1;\n logic i0_ends_f1;\n logic i0_br_start_error;\n\n logic [31:1] f1prett;\n logic [31:1] f0prett;\n logic [1:0] f1dbecc;\n logic [1:0] f0dbecc;\n logic [1:0] f1icaf;\n logic [1:0] f0icaf;\n\n logic [1:0] aligndbecc;\n logic [1:0] alignicaf;\n logic i0_brp_pc4;\n\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] firstpc_hash, secondpc_hash;\n\n logic [1:0] wrptr, wrptr_in;\n logic [1:0] rdptr, rdptr_in;\n logic [2:0] qwen;\n logic [31:0] q2,q1,q0;\n logic q2off_in, q2off;\n logic q1off_in, q1off;\n logic q0off_in, q0off;\n logic f0_shift_2B;\n\n logic [31:0] q0eff;\n logic [31:0] q0final;\n logic q0ptr;\n logic [1:0] q0sel;\n\n logic [31:0] q1eff;\n logic [15:0] q1final;\n logic q1ptr;\n logic [1:0] q1sel;\n\n logic [2:0] qren;\n\n logic consume_fb1, consume_fb0;\n logic [1:0] icaf_eff;\n\n localparam BRDATA_SIZE = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;\n localparam BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 2;\n logic [BRDATA_SIZE-1:0] brdata_in, brdata2, brdata1, brdata0;\n logic [BRDATA_SIZE-1:0] brdata1eff, brdata0eff;\n logic [BRDATA_SIZE-1:0] brdata1final, brdata0final;\n\n localparam MHI = 1+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));\n localparam MSIZE = 2+(pt.BTB_ENABLE * (43+pt.BHT_GHR_SIZE));\n\n logic [MHI:0] misc_data_in, misc2, misc1, misc0;\n logic [MHI:0] misc1eff, misc0eff;\n\n logic [pt.BTB_BTAG_SIZE-1:0] firstbrtag_hash, secondbrtag_hash;\n\n logic error_stall_in, error_stall;\n\n assign error_stall_in = (error_stall | ifu_async_error_start) & ~exu_flush_final;\n\n rvdff #(.WIDTH(7)) bundle1ff (.*,\n .clk(active_clk),\n .din ({wrptr_in[1:0],rdptr_in[1:0],q2off_in,q1off_in,q0off_in}),\n .dout({wrptr[1:0], rdptr[1:0], q2off, q1off, q0off})\n );\n\n rvdffie #(.WIDTH(7),.OVERRIDE(1)) bundle2ff (.*,\n .din ({error_stall_in,f2val_in[1:0],f1val_in[1:0],f0val_in[1:0]}),\n .dout({error_stall, f2val[1:0], f1val[1:0], f0val[1:0] })\n );\n\nif(pt.BTB_ENABLE==1) begin : genblock1\n rvdffe #(BRDATA_SIZE) brdata2ff (.*, .clk(clk), .en(qwen[2]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata2[BRDATA_SIZE-1:0]));\n rvdffe #(BRDATA_SIZE) brdata1ff (.*, .clk(clk), .en(qwen[1]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata1[BRDATA_SIZE-1:0]));\n rvdffe #(BRDATA_SIZE) brdata0ff (.*, .clk(clk), .en(qwen[0]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata0[BRDATA_SIZE-1:0]));\n rvdffe #(MSIZE) misc2ff (.*, .clk(clk), .en(qwen[2]), .din(misc_data_in[MHI:0]), .dout(misc2[MHI:0]));\n rvdffe #(MSIZE) misc1ff (.*, .clk(clk), .en(qwen[1]), .din(misc_data_in[MHI:0]), .dout(misc1[MHI:0]));\n rvdffe #(MSIZE) misc0ff (.*, .clk(clk), .en(qwen[0]), .din(misc_data_in[MHI:0]), .dout(misc0[MHI:0]));\nend\nelse begin : genblock1\n\n rvdffie #((MSIZE*3)+(BRDATA_SIZE*3)) miscff (.*,\n .din({qwen[2] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc2[MHI:0], brdata2[BRDATA_SIZE-1:0]},\n qwen[1] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc1[MHI:0], brdata1[BRDATA_SIZE-1:0]},\n qwen[0] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc0[MHI:0], brdata0[BRDATA_SIZE-1:0]}}),\n .dout({misc2[MHI:0], brdata2[BRDATA_SIZE-1:0],\n misc1[MHI:0], brdata1[BRDATA_SIZE-1:0],\n misc0[MHI:0], brdata0[BRDATA_SIZE-1:0]})\n );\nend\n\n logic [31:1] q2pc, q1pc, q0pc;\n\n rvdffe #(31) q2pcff (.*, .clk(clk), .en(qwen[2]), .din(ifu_fetch_pc[31:1]), .dout(q2pc[31:1]));\n rvdffe #(31) q1pcff (.*, .clk(clk), .en(qwen[1]), .din(ifu_fetch_pc[31:1]), .dout(q1pc[31:1]));\n rvdffe #(31) q0pcff (.*, .clk(clk), .en(qwen[0]), .din(ifu_fetch_pc[31:1]), .dout(q0pc[31:1]));\n\n rvdffe #(32) q2ff (.*, .clk(clk), .en(qwen[2]), .din(ifu_fetch_data_f[31:0]), .dout(q2[31:0]));\n rvdffe #(32) q1ff (.*, .clk(clk), .en(qwen[1]), .din(ifu_fetch_data_f[31:0]), .dout(q1[31:0]));\n rvdffe #(32) q0ff (.*, .clk(clk), .en(qwen[0]), .din(ifu_fetch_data_f[31:0]), .dout(q0[31:0]));\n\n\n // new queue control logic\n\n assign qren[2:0] = { rdptr[1:0] == 2'b10,\n rdptr[1:0] == 2'b01,\n rdptr[1:0] == 2'b00 };\n\n assign qwen[2:0] = { (wrptr[1:0] == 2'b10) & ifvalid,\n (wrptr[1:0] == 2'b01) & ifvalid,\n (wrptr[1:0] == 2'b00) & ifvalid };\n\n\n assign rdptr_in[1:0] = ({2{ qren[0] & ifu_fb_consume1 & ~exu_flush_final}} & 2'b01 ) |\n ({2{ qren[1] & ifu_fb_consume1 & ~exu_flush_final}} & 2'b10 ) |\n ({2{ qren[2] & ifu_fb_consume1 & ~exu_flush_final}} & 2'b00 ) |\n ({2{ qren[0] & ifu_fb_consume2 & ~exu_flush_final}} & 2'b10 ) |\n ({2{ qren[1] & ifu_fb_consume2 & ~exu_flush_final}} & 2'b00 ) |\n ({2{ qren[2] & ifu_fb_consume2 & ~exu_flush_final}} & 2'b01 ) |\n ({2{~ifu_fb_consume1 & ~ifu_fb_consume2 & ~exu_flush_final}} & rdptr[1:0]);\n\n assign wrptr_in[1:0] = ({2{ qwen[0] & ~exu_flush_final}} & 2'b01 ) |\n ({2{ qwen[1] & ~exu_flush_final}} & 2'b10 ) |\n ({2{ qwen[2] & ~exu_flush_final}} & 2'b00 ) |\n ({2{~ifvalid & ~exu_flush_final}} & wrptr[1:0]);\n\n\n\n assign q2off_in = ( ~qwen[2] & (rdptr[1:0]==2'd2) & (q2off | f0_shift_2B) ) |\n ( ~qwen[2] & (rdptr[1:0]==2'd1) & (q2off | f1_shift_2B) ) |\n ( ~qwen[2] & (rdptr[1:0]==2'd0) & q2off );\n\n assign q1off_in = ( ~qwen[1] & (rdptr[1:0]==2'd1) & (q1off | f0_shift_2B) ) |\n ( ~qwen[1] & (rdptr[1:0]==2'd0) & (q1off | f1_shift_2B) ) |\n ( ~qwen[1] & (rdptr[1:0]==2'd2) & q1off );\n\n assign q0off_in = ( ~qwen[0] & (rdptr[1:0]==2'd0) & (q0off | f0_shift_2B) ) |\n ( ~qwen[0] & (rdptr[1:0]==2'd2) & (q0off | f1_shift_2B) ) |\n ( ~qwen[0] & (rdptr[1:0]==2'd1) & q0off );\n\n\n\n assign q0ptr = ( (rdptr[1:0]==2'b00) & q0off ) |\n ( (rdptr[1:0]==2'b01) & q1off ) |\n ( (rdptr[1:0]==2'b10) & q2off );\n\n assign q1ptr = ( (rdptr[1:0]==2'b00) & q1off ) |\n ( (rdptr[1:0]==2'b01) & q2off ) |\n ( (rdptr[1:0]==2'b10) & q0off );\n\n assign q0sel[1:0] = {q0ptr,~q0ptr};\n\n assign q1sel[1:0] = {q1ptr,~q1ptr};\n\n // end new queue control logic\n\n\n // misc data that is associated with each fetch buffer\n\n if(pt.BTB_ENABLE==1)\n assign misc_data_in[MHI:0] = {\n\n ic_access_fault_type_f[1:0],\n ifu_bp_btb_target_f[31:1],\n ifu_bp_poffset_f[11:0],\n ifu_bp_fghr_f[pt.BHT_GHR_SIZE-1:0]\n };\n else\n assign misc_data_in[MHI:0] = {\n ic_access_fault_type_f[1:0]\n };\n\n\n assign {misc1eff[MHI:0],misc0eff[MHI:0]} = (({MSIZE*2{qren[0]}} & {misc1[MHI:0],misc0[MHI:0]}) |\n ({MSIZE*2{qren[1]}} & {misc2[MHI:0],misc1[MHI:0]}) |\n ({MSIZE*2{qren[2]}} & {misc0[MHI:0],misc2[MHI:0]}));\n\n if(pt.BTB_ENABLE==1) begin\n assign {\n f1ictype[1:0],\n f1prett[31:1],\n f1poffset[11:0],\n f1fghr[pt.BHT_GHR_SIZE-1:0]\n } = misc1eff[MHI:0];\n\n assign {\n f0ictype[1:0],\n f0prett[31:1],\n f0poffset[11:0],\n f0fghr[pt.BHT_GHR_SIZE-1:0]\n } = misc0eff[MHI:0];\n\n if(pt.BTB_FULLYA) begin\n assign brdata_in[BRDATA_SIZE-1:0] = {\n ifu_bp_fa_index_f[1], iccm_rd_ecc_double_err[1],ic_access_fault_f[1],ifu_bp_hist1_f[1],ifu_bp_hist0_f[1],ifu_bp_pc4_f[1],ifu_bp_way_f[1],ifu_bp_valid_f[1],ifu_bp_ret_f[1],\n ifu_bp_fa_index_f[0], iccm_rd_ecc_double_err[0],ic_access_fault_f[0],ifu_bp_hist1_f[0],ifu_bp_hist0_f[0],ifu_bp_pc4_f[0],ifu_bp_way_f[0],ifu_bp_valid_f[0],ifu_bp_ret_f[0]\n };\n assign {f0index[1],f0dbecc[1],f0icaf[1],f0hist1[1],f0hist0[1],f0pc4[1],f0way[1],f0brend[1],f0ret[1],\n f0index[0],f0dbecc[0],f0icaf[0],f0hist1[0],f0hist0[0],f0pc4[0],f0way[0],f0brend[0],f0ret[0]} = brdata0final[BRDATA_SIZE-1:0];\n\n assign {f1index[1],f1dbecc[1],f1icaf[1],f1hist1[1],f1hist0[1],f1pc4[1],f1way[1],f1brend[1],f1ret[1],\n f1index[0],f1dbecc[0],f1icaf[0],f1hist1[0],f1hist0[0],f1pc4[0],f1way[0],f1brend[0],f1ret[0]} = brdata1final[BRDATA_SIZE-1:0];\n\n end\n else begin\n assign brdata_in[BRDATA_SIZE-1:0] = {\n iccm_rd_ecc_double_err[1],ic_access_fault_f[1],ifu_bp_hist1_f[1],ifu_bp_hist0_f[1],ifu_bp_pc4_f[1],ifu_bp_way_f[1],ifu_bp_valid_f[1],ifu_bp_ret_f[1],\n iccm_rd_ecc_double_err[0],ic_access_fault_f[0],ifu_bp_hist1_f[0],ifu_bp_hist0_f[0],ifu_bp_pc4_f[0],ifu_bp_way_f[0],ifu_bp_valid_f[0],ifu_bp_ret_f[0]\n };\n assign {f0dbecc[1],f0icaf[1],f0hist1[1],f0hist0[1],f0pc4[1],f0way[1],f0brend[1],f0ret[1],\n f0dbecc[0],f0icaf[0],f0hist1[0],f0hist0[0],f0pc4[0],f0way[0],f0brend[0],f0ret[0]} = brdata0final[BRDATA_SIZE-1:0];\n\n assign {f1dbecc[1],f1icaf[1],f1hist1[1],f1hist0[1],f1pc4[1],f1way[1],f1brend[1],f1ret[1],\n f1dbecc[0],f1icaf[0],f1hist1[0],f1hist0[0],f1pc4[0],f1way[0],f1brend[0],f1ret[0]} = brdata1final[BRDATA_SIZE-1:0];\n\n end\n\n\n\n\n assign {brdata1eff[BRDATA_SIZE-1:0],brdata0eff[BRDATA_SIZE-1:0]} = (({BRDATA_SIZE*2{qren[0]}} & {brdata1[BRDATA_SIZE-1:0],brdata0[BRDATA_SIZE-1:0]}) |\n ({BRDATA_SIZE*2{qren[1]}} & {brdata2[BRDATA_SIZE-1:0],brdata1[BRDATA_SIZE-1:0]}) |\n ({BRDATA_SIZE*2{qren[2]}} & {brdata0[BRDATA_SIZE-1:0],brdata2[BRDATA_SIZE-1:0]}));\n\n assign brdata0final[BRDATA_SIZE-1:0] = (({BRDATA_SIZE{q0sel[0]}} & { brdata0eff[2*BRDATA_WIDTH-1:0]}) |\n ({BRDATA_SIZE{q0sel[1]}} & {{BRDATA_WIDTH{1'b0}},brdata0eff[BRDATA_SIZE-1:BRDATA_WIDTH]}));\n\n assign brdata1final[BRDATA_SIZE-1:0] = (({BRDATA_SIZE{q1sel[0]}} & { brdata1eff[2*BRDATA_WIDTH-1:0]}) |\n ({BRDATA_SIZE{q1sel[1]}} & {{BRDATA_WIDTH{1'b0}},brdata1eff[BRDATA_SIZE-1:BRDATA_WIDTH]}));\n\n end // if (pt.BTB_ENABLE==1)\n else begin\n assign {\n f1ictype[1:0]\n } = misc1eff[MHI:0];\n\n assign {\n f0ictype[1:0]\n } = misc0eff[MHI:0];\n\n assign brdata_in[BRDATA_SIZE-1:0] = {\n iccm_rd_ecc_double_err[1],ic_access_fault_f[1],\n iccm_rd_ecc_double_err[0],ic_access_fault_f[0]\n };\n assign {f0dbecc[1],f0icaf[1],\n f0dbecc[0],f0icaf[0]} = brdata0final[BRDATA_SIZE-1:0];\n\n assign {f1dbecc[1],f1icaf[1],\n f1dbecc[0],f1icaf[0]} = brdata1final[BRDATA_SIZE-1:0];\n\n assign {brdata1eff[BRDATA_SIZE-1:0],brdata0eff[BRDATA_SIZE-1:0]} = (({BRDATA_SIZE*2{qren[0]}} & {brdata1[BRDATA_SIZE-1:0],brdata0[BRDATA_SIZE-1:0]}) |\n ({BRDATA_SIZE*2{qren[1]}} & {brdata2[BRDATA_SIZE-1:0],brdata1[BRDATA_SIZE-1:0]}) |\n ({BRDATA_SIZE*2{qren[2]}} & {brdata0[BRDATA_SIZE-1:0],brdata2[BRDATA_SIZE-1:0]}));\n\n assign brdata0final[BRDATA_SIZE-1:0] = (({BRDATA_SIZE{q0sel[0]}} & { brdata0eff[2*BRDATA_WIDTH-1:0]}) |\n ({BRDATA_SIZE{q0sel[1]}} & {{BRDATA_WIDTH{1'b0}},brdata0eff[BRDATA_SIZE-1:BRDATA_WIDTH]}));\n\n assign brdata1final[BRDATA_SIZE-1:0] = (({BRDATA_SIZE{q1sel[0]}} & { brdata1eff[2*BRDATA_WIDTH-1:0]}) |\n ({BRDATA_SIZE{q1sel[1]}} & {{BRDATA_WIDTH{1'b0}},brdata1eff[BRDATA_SIZE-1:BRDATA_WIDTH]}));\n\n end // else: !if(pt.BTB_ENABLE==1)\n\n\n // possible states of { sf0_valid, sf1_valid, f2_valid }\n //\n // 000 if->f0\n // 100 if->f1\n // 101 illegal\n // 010 if->f1, f1->f0\n // 110 if->f2\n // 001 if->f1, f2->f0\n // 011 if->f2, f2->f1, f1->f0\n // 111 !if, no shift\n\n assign f2_valid = f2val[0];\n assign sf1_valid = sf1val[0];\n assign sf0_valid = sf0val[0];\n\n // interface to fetch\n\n assign consume_fb0 = ~sf0val[0] & f0val[0];\n\n assign consume_fb1 = ~sf1val[0] & f1val[0];\n\n assign ifu_fb_consume1 = consume_fb0 & ~consume_fb1 & ~exu_flush_final;\n assign ifu_fb_consume2 = consume_fb0 & consume_fb1 & ~exu_flush_final;\n\n assign ifvalid = ifu_fetch_val[0];\n\n assign shift_f1_f0 = ~sf0_valid & sf1_valid;\n assign shift_f2_f0 = ~sf0_valid & ~sf1_valid & f2_valid;\n assign shift_f2_f1 = ~sf0_valid & sf1_valid & f2_valid;\n\n assign fetch_to_f0 = ~sf0_valid & ~sf1_valid & ~f2_valid & ifvalid;\n\n assign fetch_to_f1 = (~sf0_valid & ~sf1_valid & f2_valid & ifvalid) |\n (~sf0_valid & sf1_valid & ~f2_valid & ifvalid) |\n ( sf0_valid & ~sf1_valid & ~f2_valid & ifvalid);\n\n assign fetch_to_f2 = (~sf0_valid & sf1_valid & f2_valid & ifvalid) |\n ( sf0_valid & sf1_valid & ~f2_valid & ifvalid);\n\n\n assign f2val_in[1:0] = ({2{ fetch_to_f2 & ~exu_flush_final}} & ifu_fetch_val[1:0]) |\n ({2{~fetch_to_f2 & ~shift_f2_f1 & ~shift_f2_f0 & ~exu_flush_final}} & f2val[1:0] );\n\n\n assign sf1val[1:0] = ({2{ f1_shift_2B}} & {1'b0,f1val[1]}) |\n ({2{~f1_shift_2B}} & f1val[1:0] );\n\n assign f1val_in[1:0] = ({2{ fetch_to_f1 & ~exu_flush_final}} & ifu_fetch_val[1:0]) |\n ({2{ shift_f2_f1 & ~exu_flush_final}} & f2val[1:0] ) |\n ({2{~fetch_to_f1 & ~shift_f2_f1 & ~shift_f1_f0 & ~exu_flush_final}} & sf1val[1:0] );\n\n\n\n assign sf0val[1:0] = ({2{ shift_2B }} & {1'b0,f0val[1]}) |\n ({2{~shift_2B & ~shift_4B}} & f0val[1:0]);\n\n assign f0val_in[1:0] = ({2{fetch_to_f0 & ~exu_flush_final}} & ifu_fetch_val[1:0]) |\n ({2{ shift_f2_f0 & ~exu_flush_final}} & f2val[1:0] ) |\n ({2{ shift_f1_f0 & ~exu_flush_final}} & sf1val[1:0] ) |\n ({2{~fetch_to_f0 & ~shift_f2_f0 & ~shift_f1_f0 & ~exu_flush_final}} & sf0val[1:0] );\n\n assign {q1eff[31:0],q0eff[31:0]} = (({64{qren[0]}} & {q1[31:0],q0[31:0]}) |\n ({64{qren[1]}} & {q2[31:0],q1[31:0]}) |\n ({64{qren[2]}} & {q0[31:0],q2[31:0]}));\n\n assign q0final[31:0] = ({32{q0sel[0]}} & { q0eff[31:0]}) |\n ({32{q0sel[1]}} & {16'b0,q0eff[31:16]});\n\n assign q1final[15:0] = ({16{q1sel[0]}} & q1eff[15:0] ) |\n ({16{q1sel[1]}} & q1eff[31:16]);\n logic [31:1] q0pceff, q0pcfinal;\n logic [31:1] q1pceff;\n\n assign {q1pceff[31:1],q0pceff[31:1]} = (({62{qren[0]}} & {q1pc[31:1],q0pc[31:1]}) |\n ({62{qren[1]}} & {q2pc[31:1],q1pc[31:1]}) |\n ({62{qren[2]}} & {q0pc[31:1],q2pc[31:1]}));\n\n\n assign q0pcfinal[31:1] = ({31{q0sel[0]}} & ( q0pceff[31:1])) |\n ({31{q0sel[1]}} & ( q0pceff[31:1] + 31'd1));\n\n assign aligndata[31:0] = ({32{ f0val[1] }} & {q0final[31:0]}) |\n ({32{~f0val[1] & f0val[0]}} & {q1final[15:0],q0final[15:0]});\n\n assign alignval[1:0] = ({ 2{ f0val[1] }} & {2'b11}) |\n ({ 2{~f0val[1] & f0val[0]}} & {f1val[0],1'b1});\n\n assign alignicaf[1:0] = ({ 2{ f0val[1] }} & f0icaf[1:0] ) |\n ({ 2{~f0val[1] & f0val[0]}} & {f1icaf[0],f0icaf[0]});\n\n assign aligndbecc[1:0] = ({ 2{ f0val[1] }} & f0dbecc[1:0] ) |\n ({ 2{~f0val[1] & f0val[0]}} & {f1dbecc[0],f0dbecc[0]});\n\n if (pt.BTB_ENABLE==1) begin\n\n // for branch prediction\n\n assign alignbrend[1:0] = ({ 2{ f0val[1] }} & f0brend[1:0] ) |\n ({ 2{~f0val[1] & f0val[0]}} & {f1brend[0],f0brend[0]});\n\n assign alignpc4[1:0] = ({ 2{ f0val[1] }} & f0pc4[1:0] ) |\n ({ 2{~f0val[1] & f0val[0]}} & {f1pc4[0],f0pc4[0]});\n\n if(pt.BTB_FULLYA) begin\n assign alignindex[0] = f0index[0];\n assign alignindex[1] = f0val[1] ? f0index[1] : f1index[0];\n end\n\n assign alignret[1:0] = ({ 2{ f0val[1] }} & f0ret[1:0] ) |\n ({ 2{~f0val[1] & f0val[0]}} & {f1ret[0],f0ret[0]});\n\n assign alignway[1:0] = ({ 2{ f0val[1] }} & f0way[1:0] ) |\n ({ 2{~f0val[1] & f0val[0]}} & {f1way[0],f0way[0]});\n\n assign alignhist1[1:0] = ({ 2{ f0val[1] }} & f0hist1[1:0] ) |\n ({ 2{~f0val[1] & f0val[0]}} & {f1hist1[0],f0hist1[0]});\n\n assign alignhist0[1:0] = ({ 2{ f0val[1] }} & f0hist0[1:0] ) |\n ({ 2{~f0val[1] & f0val[0]}} & {f1hist0[0],f0hist0[0]});\n\n assign secondpc[31:1] = ({31{ f0val[1] }} & (q0pceff[31:1] + 31'd1)) |\n // you need the base pc for 2nd one only (4B max, 2B for the 1st and 2B for the 2nd)\n ({31{~f0val[1] & f0val[0]}} & q1pceff[31:1] );\n\n\n assign firstpc[31:1] = q0pcfinal[31:1];\n end // if (pt.BTB_ENABLE==1)\n\n assign alignfromf1[1] = ~f0val[1] & f0val[0];\n\n\n assign ifu_i0_pc[31:1] = q0pcfinal[31:1];\n\n\n assign ifu_i0_pc4 = first4B;\n\n\n assign ifu_i0_cinst[15:0] = aligndata[15:0];\n\n assign first4B = (aligndata[1:0] == 2'b11);\n assign first2B = ~first4B;\n\n assign ifu_i0_valid = (first4B & alignval[1]) |\n (first2B & alignval[0]);\n\n // inst access fault on any byte of inst results in access fault for the inst\n assign ifu_i0_icaf = (first4B & (|alignicaf[1:0])) |\n (first2B & alignicaf[0] );\n\n assign ifu_i0_icaf_type[1:0] = (first4B & ~f0val[1] & f0val[0] & ~alignicaf[0] & ~aligndbecc[0]) ? f1ictype[1:0] : f0ictype[1:0];\n\n\n assign icaf_eff[1:0] = alignicaf[1:0] | aligndbecc[1:0];\n\n assign ifu_i0_icaf_second = first4B & ~icaf_eff[0] & icaf_eff[1];\n\n assign ifu_i0_dbecc = (first4B & (|aligndbecc[1:0])) |\n (first2B & aligndbecc[0] );\n\n\n assign ifirst[31:0] = aligndata[31:0];\n\n\n assign ifu_i0_instr[31:0] = ({32{first4B & alignval[1]}} & ifirst[31:0]) |\n ({32{first2B & alignval[0]}} & uncompress0[31:0]);\n\nif(pt.BTB_ENABLE==1) begin : genblock2\n\n // if you detect br does not start on instruction boundary\n\n el2_btb_addr_hash #(.pt(pt)) firsthash (.pc(firstpc [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),\n .hash(firstpc_hash [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));\n el2_btb_addr_hash #(.pt(pt)) secondhash(.pc(secondpc[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]),\n .hash(secondpc_hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));\n\n if(pt.BTB_FULLYA) begin\n assign firstbrtag_hash = firstpc;\n assign secondbrtag_hash = secondpc;\n end\n else begin\n if(pt.BTB_BTAG_FOLD) begin : btbfold\n el2_btb_tag_hash_fold #(.pt(pt)) first_brhash (.pc(firstpc [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),\n .hash(firstbrtag_hash [pt.BTB_BTAG_SIZE-1:0]));\n el2_btb_tag_hash_fold #(.pt(pt)) second_brhash(.pc(secondpc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),\n .hash(secondbrtag_hash[pt.BTB_BTAG_SIZE-1:0]));\n end\n else begin : btbfold\n el2_btb_tag_hash #(.pt(pt)) first_brhash (.pc(firstpc [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),\n .hash(firstbrtag_hash [pt.BTB_BTAG_SIZE-1:0]));\n el2_btb_tag_hash #(.pt(pt)) second_brhash(.pc(secondpc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]),\n .hash(secondbrtag_hash[pt.BTB_BTAG_SIZE-1:0]));\n end\n end // else: !if(pt.BTB_FULLYA)\n\n\n // start_indexing - you want pc to be based on where the end of branch is prediction\n // normal indexing pc based that's incorrect now for pc4 cases it's pc4 + 2\n\n always_comb begin\n\n i0_brp = '0;\n\n i0_br_start_error = (first4B & alignval[1] & alignbrend[0]);\n\n i0_brp.valid = (first2B & alignbrend[0]) |\n (first4B & alignbrend[1]) |\n i0_br_start_error;\n\n i0_brp_pc4 = (first2B & alignpc4[0]) |\n (first4B & alignpc4[1]);\n\n i0_brp.ret = (first2B & alignret[0]) |\n (first4B & alignret[1]);\n\n i0_brp.way = (first2B | alignbrend[0]) ? alignway[0] : alignway[1];\n\n i0_brp.hist[1] = (first2B & alignhist1[0]) |\n (first4B & alignhist1[1]);\n\n i0_brp.hist[0] = (first2B & alignhist0[0]) |\n (first4B & alignhist0[1]);\n\n i0_ends_f1 = first4B & alignfromf1[1];\n\n i0_brp.toffset[11:0] = (i0_ends_f1) ? f1poffset[11:0] : f0poffset[11:0];\n\n i0_brp.prett[31:1] = (i0_ends_f1) ? f1prett[31:1] : f0prett[31:1];\n\n i0_brp.br_start_error = i0_br_start_error;\n\n i0_brp.bank = (first2B | alignbrend[0]) ? firstpc[1] : secondpc[1];\n\n i0_brp.br_error = (i0_brp.valid & i0_brp_pc4 & first2B) |\n (i0_brp.valid & ~i0_brp_pc4 & first4B);\n\n if(pt.BTB_FULLYA)\n ifu_i0_fa_index = (first2B | alignbrend[0]) ? alignindex[0] : alignindex[1];\n else\n ifu_i0_fa_index = '0;\n\n end\n\n\n assign ifu_i0_bp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = (first2B | alignbrend[0]) ? firstpc_hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] :\n secondpc_hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO];\n\n assign ifu_i0_bp_fghr[pt.BHT_GHR_SIZE-1:0] = (i0_ends_f1) ? f1fghr[pt.BHT_GHR_SIZE-1:0] :\n f0fghr[pt.BHT_GHR_SIZE-1:0];\n\n assign ifu_i0_bp_btag[pt.BTB_BTAG_SIZE-1:0] = (first2B | alignbrend[0]) ? firstbrtag_hash[pt.BTB_BTAG_SIZE-1:0] :\n secondbrtag_hash[pt.BTB_BTAG_SIZE-1:0];\nend\nelse begin\n assign i0_brp = '0;\n assign ifu_i0_bp_index = '0;\n assign ifu_i0_bp_fghr = '0;\n assign ifu_i0_bp_btag = '0;\nend // else: !if(pt.BTB_ENABLE==1)\n\n // decompress\n\n // quiet inputs for 4B inst\n el2_ifu_compress_ctl compress0 (.din((first2B) ? aligndata[15:0] : '0), .dout(uncompress0[31:0]));\n\n\n\n assign i0_shift = dec_i0_decode_d & ~error_stall;\n\n assign ifu_pmu_instr_aligned = i0_shift;\n\n\n // compute how many bytes are being shifted from f0\n\n assign shift_2B = i0_shift & first2B;\n\n assign shift_4B = i0_shift & first4B;\n\n // exact equations for the queue logic\n assign f0_shift_2B = (shift_2B & f0val[0] ) |\n (shift_4B & f0val[0] & ~f0val[1]);\n\n\n // f0 valid states\n // 11\n // 10\n // 00\n\n assign f1_shift_2B = f0val[0] & ~f0val[1] & shift_4B;\n\n\n\nendmodule\n" }, { "path": "design/ifu/el2_ifu_bp_ctl.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n\n//********************************************************************************\n// Function: Branch predictor\n// Comments:\n//\n//\n// Bank3 : Bank2 : Bank1 : Bank0\n// FA C 8 4 0\n//********************************************************************************\n\nmodule el2_ifu_bp_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n\n input logic clk,\n input logic rst_l,\n\n input logic ic_hit_f, // Icache hit, enables F address capture\n\n input logic [31:1] ifc_fetch_addr_f, // look up btb address\n input logic ifc_fetch_req_f, // F1 valid\n\n input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // BP commit update packet, includes errors\n input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index\n\n input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associative btb error index\n\n input logic dec_tlu_flush_lower_wb, // used to move EX4 RS to EX1 and F\n input logic dec_tlu_flush_leak_one_wb, // don't hit for leak one fetches\n\n input logic dec_tlu_bpred_disable, // disable all branch prediction\n\n input el2_predict_pkt_t exu_mp_pkt, // mispredict packet\n\n input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr (for patching fghr)\n input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index, // Mispredict index\n input logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag\n\n input logic exu_flush_final, // all flushes\n\n output logic ifu_bp_hit_taken_f, // btb hit, select target\n output logic [31:1] ifu_bp_btb_target_f, // predicted target PC\n output logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified\n\n output logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f, // fetch ghr\n\n output logic [1:0] ifu_bp_way_f, // way\n output logic [1:0] ifu_bp_ret_f, // predicted ret\n output logic [1:0] ifu_bp_hist1_f, // history counters for all 4 potential branches, bit 1, right justified\n output logic [1:0] ifu_bp_hist0_f, // history counters for all 4 potential branches, bit 0, right justified\n output logic [1:0] ifu_bp_pc4_f, // pc4 indication, right justified\n output logic [1:0] ifu_bp_valid_f, // branch valid, right justified\n output logic [11:0] ifu_bp_poffset_f, // predicted target\n\n output logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f, // predicted branch index (fully associative option)\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n );\n\n\n localparam BTB_DWIDTH = pt.BTB_TOFFSET_SIZE+pt.BTB_BTAG_SIZE+5;\n localparam BTB_DWIDTH_TOP = int'(pt.BTB_TOFFSET_SIZE)+int'(pt.BTB_BTAG_SIZE)+4;\n localparam BTB_FA_INDEX = $clog2(pt.BTB_SIZE)-1;\n localparam FA_CMP_LOWER = $clog2(pt.ICACHE_LN_SZ);\n localparam FA_TAG_END_UPPER= 5+int'(pt.BTB_TOFFSET_SIZE)+int'(FA_CMP_LOWER)-1; // must cast to int or vcs build fails\n localparam FA_TAG_START_LOWER = 3+int'(pt.BTB_TOFFSET_SIZE)+int'(FA_CMP_LOWER);\n localparam FA_TAG_END_LOWER = 5+int'(pt.BTB_TOFFSET_SIZE);\n\n localparam TAG_START=BTB_DWIDTH-1;\n localparam PC4=4;\n localparam BOFF=3;\n localparam CALL=2;\n localparam RET=1;\n localparam BV=0;\n\n localparam LRU_SIZE=pt.BTB_ARRAY_DEPTH;\n localparam NUM_BHT_LOOP = (pt.BHT_ARRAY_DEPTH > 16 ) ? 16 : pt.BHT_ARRAY_DEPTH;\n localparam NUM_BHT_LOOP_INNER_HI = (pt.BHT_ARRAY_DEPTH > 16 ) ?pt.BHT_ADDR_LO+3 : pt.BHT_ADDR_HI;\n localparam NUM_BHT_LOOP_OUTER_LO = (pt.BHT_ARRAY_DEPTH > 16 ) ?pt.BHT_ADDR_LO+4 : pt.BHT_ADDR_LO;\n localparam BHT_NO_ADDR_MATCH = ( pt.BHT_ARRAY_DEPTH <= 16 );\n\n\n logic exu_mp_valid_write;\n logic exu_mp_ataken;\n logic exu_mp_valid; // conditional branch mispredict\n logic exu_mp_boffset; // branch offsett\n logic exu_mp_pc4; // branch is a 4B inst\n logic exu_mp_call; // branch is a call inst\n logic exu_mp_ret; // branch is a ret inst\n logic exu_mp_ja; // branch is a jump always\n logic [1:0] exu_mp_hist; // new history\n logic [11:0] exu_mp_tgt; // target offset\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address\n logic dec_tlu_br0_v_wb; // WB stage history update\n logic [1:0] dec_tlu_br0_hist_wb; // new history\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_tlu_br0_addr_wb; // addr\n logic dec_tlu_br0_error_wb; // error; invalidate bank\n logic dec_tlu_br0_start_error_wb; // error; invalidate all 4 banks in fg\n logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_wb;\n\n logic use_mp_way, use_mp_way_p1;\n logic [pt.RET_STACK_SIZE-1:0][31:0] rets_out, rets_in;\n logic [pt.RET_STACK_SIZE-1:0] rsenable;\n\n\n logic [11:0] btb_rd_tgt_f;\n logic btb_rd_pc4_f, btb_rd_call_f, btb_rd_ret_f;\n logic [1:1] bp_total_branch_offset_f;\n\n logic [31:1] bp_btb_target_adder_f;\n logic [31:1] bp_rs_call_target_f;\n logic rs_push, rs_pop, rs_hold;\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_p1_f, btb_wr_addr, btb_rd_addr_f;\n logic [pt.BTB_BTAG_SIZE-1:0] btb_wr_tag, fetch_rd_tag_f, fetch_rd_tag_p1_f;\n logic [BTB_DWIDTH-1:0] btb_wr_data;\n logic btb_wr_en_way0, btb_wr_en_way1;\n\n\n logic dec_tlu_error_wb, btb_valid, dec_tlu_br0_middle_wb;\n logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_error_addr_wb;\n logic branch_error_collision_f, fetch_mp_collision_f, branch_error_collision_p1_f, fetch_mp_collision_p1_f;\n\n logic branch_error_bank_conflict_f;\n logic [pt.BHT_GHR_SIZE-1:0] merged_ghr, fghr_ns, fghr;\n logic [1:0] num_valids;\n logic [LRU_SIZE-1:0] btb_lru_b0_f, btb_lru_b0_hold, btb_lru_b0_ns,\n fetch_wrindex_dec, fetch_wrindex_p1_dec, fetch_wrlru_b0, fetch_wrlru_p1_b0,\n mp_wrindex_dec, mp_wrlru_b0;\n logic btb_lru_rd_f, btb_lru_rd_p1_f, lru_update_valid_f;\n logic tag_match_way0_f, tag_match_way1_f;\n logic [1:0] way_raw, bht_dir_f, btb_sel_f, wayhit_f, vwayhit_f, wayhit_p1_f;\n logic [1:0] bht_valid_f, bht_force_taken_f;\n\n logic leak_one_f, leak_one_f_d1;\n\n logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_out ;\n\n logic [LRU_SIZE-1:0][BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_out ;\n\n logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_f ;\n logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_f ;\n\n logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way0_p1_f ;\n logic [BTB_DWIDTH-1:0] btb_bank0_rd_data_way1_p1_f ;\n\n logic [BTB_DWIDTH-1:0] btb_vbank0_rd_data_f, btb_vbank1_rd_data_f;\n\n logic final_h;\n logic btb_fg_crossing_f;\n logic middle_of_bank;\n\n\n logic [1:0] bht_vbank0_rd_data_f, bht_vbank1_rd_data_f;\n logic branch_error_bank_conflict_p1_f;\n logic tag_match_way0_p1_f, tag_match_way1_p1_f;\n\n logic [1:0] btb_vlru_rd_f, fetch_start_f, tag_match_vway1_expanded_f, tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f;\n logic [31:2] fetch_addr_p1_f;\n\n\n logic exu_mp_way, exu_mp_way_f, dec_tlu_br0_way_wb, dec_tlu_way_wb;\n logic [BTB_DWIDTH-1:0] btb_bank0e_rd_data_f, btb_bank0e_rd_data_p1_f;\n\n logic [BTB_DWIDTH-1:0] btb_bank0o_rd_data_f;\n\n logic [1:0] tag_match_way0_expanded_f, tag_match_way1_expanded_f;\n\n\n logic [1:0] bht_bank0_rd_data_f;\n logic [1:0] bht_bank1_rd_data_f;\n logic [1:0] bht_bank0_rd_data_p1_f;\n genvar j, i;\n\n assign exu_mp_valid = exu_mp_pkt.misp & ~leak_one_f; // conditional branch mispredict\n assign exu_mp_boffset = exu_mp_pkt.boffset; // branch offset\n assign exu_mp_pc4 = exu_mp_pkt.pc4; // branch is a 4B inst\n assign exu_mp_call = exu_mp_pkt.pcall; // branch is a call inst\n assign exu_mp_ret = exu_mp_pkt.pret; // branch is a ret inst\n assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always\n assign exu_mp_way = exu_mp_pkt.way; // repl way\n assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history\n assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0] ; // target offset\n assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address\n assign exu_mp_ataken = exu_mp_pkt.ataken;\n\n\n assign dec_tlu_br0_v_wb = dec_tlu_br0_r_pkt.valid;\n assign dec_tlu_br0_hist_wb[1:0] = dec_tlu_br0_r_pkt.hist[1:0];\n assign dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO];\n assign dec_tlu_br0_error_wb = dec_tlu_br0_r_pkt.br_error;\n assign dec_tlu_br0_middle_wb = dec_tlu_br0_r_pkt.middle;\n assign dec_tlu_br0_way_wb = dec_tlu_br0_r_pkt.way;\n assign dec_tlu_br0_start_error_wb = dec_tlu_br0_r_pkt.br_start_error;\n assign exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0] = exu_i0_br_fghr_r[pt.BHT_GHR_SIZE-1:0];\n\n\n\n\n // ----------------------------------------------------------------------\n // READ\n // ----------------------------------------------------------------------\n\n // hash the incoming fetch PC, first guess at hashing algorithm\n el2_btb_addr_hash #(.pt(pt)) f1hash(.pc(ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]), .hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));\n\n\n assign fetch_addr_p1_f[31:2] = ifc_fetch_addr_f[31:2] + 30'b1;\n el2_btb_addr_hash #(.pt(pt)) f1hash_p1(.pc(fetch_addr_p1_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]), .hash(btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));\n\n assign btb_sel_f[1] = ~bht_dir_f[0];\n assign btb_sel_f[0] = bht_dir_f[0];\n\n assign fetch_start_f[1:0] = {ifc_fetch_addr_f[1], ~ifc_fetch_addr_f[1]};\n\n // Errors colliding with fetches must kill the btb/bht hit.\n\n assign branch_error_collision_f = dec_tlu_error_wb & (btb_error_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]);\n assign branch_error_collision_p1_f = dec_tlu_error_wb & (btb_error_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]);\n\n assign branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb;\n assign branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb;\n\n // set on leak one, hold until next flush without leak one\n assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb);\n\nlogic exu_flush_final_d1;\n\n if(!pt.BTB_FULLYA) begin : genblock1\n assign fetch_mp_collision_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &\n exu_mp_valid & ifc_fetch_req_f &\n (exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])\n );\n assign fetch_mp_collision_p1_f = ( (exu_mp_btag[pt.BTB_BTAG_SIZE-1:0] == fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]) &\n exu_mp_valid & ifc_fetch_req_f &\n (exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] == btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO])\n );\n // 2 -way SA, figure out the way hit and mux accordingly\n assign tag_match_way0_f = btb_bank0_rd_data_way0_f[BV] & (btb_bank0_rd_data_way0_f[TAG_START:17] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &\n ~(dec_tlu_way_wb & branch_error_bank_conflict_f) & ifc_fetch_req_f & ~leak_one_f;\n\n assign tag_match_way1_f = btb_bank0_rd_data_way1_f[BV] & (btb_bank0_rd_data_way1_f[TAG_START:17] == fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]) &\n ~(dec_tlu_way_wb & branch_error_bank_conflict_f) & ifc_fetch_req_f & ~leak_one_f;\n\n assign tag_match_way0_p1_f = btb_bank0_rd_data_way0_p1_f[BV] & (btb_bank0_rd_data_way0_p1_f[TAG_START:17] == fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]) &\n ~(dec_tlu_way_wb & branch_error_bank_conflict_p1_f) & ifc_fetch_req_f & ~leak_one_f;\n\n assign tag_match_way1_p1_f = btb_bank0_rd_data_way1_p1_f[BV] & (btb_bank0_rd_data_way1_p1_f[TAG_START:17] == fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]) &\n ~(dec_tlu_way_wb & branch_error_bank_conflict_p1_f) & ifc_fetch_req_f & ~leak_one_f;\n\n\n // Both ways could hit, use the offset bit to reorder\n\n assign tag_match_way0_expanded_f[1:0] = {tag_match_way0_f & (btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4]),\n tag_match_way0_f & ~(btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4])};\n\n assign tag_match_way1_expanded_f[1:0] = {tag_match_way1_f & (btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4]),\n tag_match_way1_f & ~(btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4])};\n\n assign tag_match_way0_expanded_p1_f[1:0] = {tag_match_way0_p1_f & (btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4]),\n tag_match_way0_p1_f & ~(btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4])};\n\n assign tag_match_way1_expanded_p1_f[1:0] = {tag_match_way1_p1_f & (btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4]),\n tag_match_way1_p1_f & ~(btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4])};\n\n assign wayhit_f[1:0] = tag_match_way0_expanded_f[1:0] | tag_match_way1_expanded_f[1:0];\n assign wayhit_p1_f[1:0] = tag_match_way0_expanded_p1_f[1:0] | tag_match_way1_expanded_p1_f[1:0];\n\n assign btb_bank0o_rd_data_f[BTB_DWIDTH-1:0] = ( ({17+pt.BTB_BTAG_SIZE{tag_match_way0_expanded_f[1]}} & btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0]) |\n ({17+pt.BTB_BTAG_SIZE{tag_match_way1_expanded_f[1]}} & btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0]) );\n assign btb_bank0e_rd_data_f[BTB_DWIDTH-1:0] = ( ({17+pt.BTB_BTAG_SIZE{tag_match_way0_expanded_f[0]}} & btb_bank0_rd_data_way0_f[BTB_DWIDTH-1:0]) |\n ({17+pt.BTB_BTAG_SIZE{tag_match_way1_expanded_f[0]}} & btb_bank0_rd_data_way1_f[BTB_DWIDTH-1:0]) );\n\n assign btb_bank0e_rd_data_p1_f[BTB_DWIDTH-1:0] = ( ({17+pt.BTB_BTAG_SIZE{tag_match_way0_expanded_p1_f[0]}} & btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH-1:0]) |\n ({17+pt.BTB_BTAG_SIZE{tag_match_way1_expanded_p1_f[0]}} & btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH-1:0]) );\n\n // virtual bank order\n\n assign btb_vbank0_rd_data_f[BTB_DWIDTH-1:0] = ( ({17+pt.BTB_BTAG_SIZE{fetch_start_f[0]}} & btb_bank0e_rd_data_f[BTB_DWIDTH-1:0]) |\n ({17+pt.BTB_BTAG_SIZE{fetch_start_f[1]}} & btb_bank0o_rd_data_f[BTB_DWIDTH-1:0]) );\n assign btb_vbank1_rd_data_f[BTB_DWIDTH-1:0] = ( ({17+pt.BTB_BTAG_SIZE{fetch_start_f[0]}} & btb_bank0o_rd_data_f[BTB_DWIDTH-1:0]) |\n ({17+pt.BTB_BTAG_SIZE{fetch_start_f[1]}} & btb_bank0e_rd_data_p1_f[BTB_DWIDTH-1:0]) );\n\n assign way_raw[1:0] = tag_match_vway1_expanded_f[1:0] | (~vwayhit_f[1:0] & btb_vlru_rd_f[1:0]);\n\n // --------------------------------------------------------------------------------\n // --------------------------------------------------------------------------------\n // update lru\n // mp\n\n // create a onehot lru write vector\n assign mp_wrindex_dec[LRU_SIZE-1:0] = {{LRU_SIZE-1{1'b0}},1'b1} << exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO];\n\n // fetch\n assign fetch_wrindex_dec[LRU_SIZE-1:0] = {{LRU_SIZE-1{1'b0}},1'b1} << btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO];\n assign fetch_wrindex_p1_dec[LRU_SIZE-1:0] = {{LRU_SIZE-1{1'b0}},1'b1} << btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO];\n\n assign mp_wrlru_b0[LRU_SIZE-1:0] = mp_wrindex_dec[LRU_SIZE-1:0] & {LRU_SIZE{exu_mp_valid}};\n\n\n assign btb_lru_b0_hold[LRU_SIZE-1:0] = ~mp_wrlru_b0[LRU_SIZE-1:0] & ~fetch_wrlru_b0[LRU_SIZE-1:0];\n\n // Forward the mp lru information to the fetch, avoids multiple way hits later\n assign use_mp_way = fetch_mp_collision_f;\n assign use_mp_way_p1 = fetch_mp_collision_p1_f;\n\n assign lru_update_valid_f = (vwayhit_f[0] | vwayhit_f[1]) & ifc_fetch_req_f & ~leak_one_f;\n\n\n assign fetch_wrlru_b0[LRU_SIZE-1:0] = fetch_wrindex_dec[LRU_SIZE-1:0] &\n {LRU_SIZE{lru_update_valid_f}};\n assign fetch_wrlru_p1_b0[LRU_SIZE-1:0] = fetch_wrindex_p1_dec[LRU_SIZE-1:0] &\n {LRU_SIZE{lru_update_valid_f}};\n\n assign btb_lru_b0_ns[LRU_SIZE-1:0] = ( (btb_lru_b0_hold[LRU_SIZE-1:0] & btb_lru_b0_f[LRU_SIZE-1:0]) |\n (mp_wrlru_b0[LRU_SIZE-1:0] & {LRU_SIZE{~exu_mp_way}}) |\n (fetch_wrlru_b0[LRU_SIZE-1:0] & {LRU_SIZE{tag_match_way0_f}}) |\n (fetch_wrlru_p1_b0[LRU_SIZE-1:0] & {LRU_SIZE{tag_match_way0_p1_f}}) );\n\n\n\n assign btb_lru_rd_f = use_mp_way ? exu_mp_way_f : |(fetch_wrindex_dec[LRU_SIZE-1:0] & btb_lru_b0_f[LRU_SIZE-1:0]);\n\n assign btb_lru_rd_p1_f = use_mp_way_p1 ? exu_mp_way_f : |(fetch_wrindex_p1_dec[LRU_SIZE-1:0] & btb_lru_b0_f[LRU_SIZE-1:0]);\n\n // rotated\n assign btb_vlru_rd_f[1:0] = ( ({2{fetch_start_f[0]}} & {btb_lru_rd_f, btb_lru_rd_f}) |\n ({2{fetch_start_f[1]}} & {btb_lru_rd_p1_f, btb_lru_rd_f}));\n\n assign tag_match_vway1_expanded_f[1:0] = ( ({2{fetch_start_f[0]}} & {tag_match_way1_expanded_f[1:0]}) |\n ({2{fetch_start_f[1]}} & {tag_match_way1_expanded_p1_f[0], tag_match_way1_expanded_f[1]}) );\n\n\n rvdffe #(LRU_SIZE) btb_lru_ff (.*, .en(ifc_fetch_req_f | exu_mp_valid),\n .din(btb_lru_b0_ns[(LRU_SIZE)-1:0]),\n .dout(btb_lru_b0_f[(LRU_SIZE)-1:0]));\n\n end // if (!pt.BTB_FULLYA)\n // Detect end of cache line and mask as needed\n logic eoc_near;\n logic eoc_mask;\n assign eoc_near = &ifc_fetch_addr_f[pt.ICACHE_BEAT_ADDR_HI:3];\n assign eoc_mask = ~eoc_near| (|(~ifc_fetch_addr_f[2:1]));\n\n\n\n // --------------------------------------------------------------------------------\n // --------------------------------------------------------------------------------\n\n // mux out critical hit bank for pc computation\n // This is only useful for the first taken branch in the fetch group\n logic [16:1] btb_sel_data_f;\n\n assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5];\n assign btb_rd_pc4_f = btb_sel_data_f[4];\n assign btb_rd_call_f = btb_sel_data_f[2];\n assign btb_rd_ret_f = btb_sel_data_f[1];\n\n assign btb_sel_data_f[16:1] = ( ({16{btb_sel_f[1]}} & btb_vbank1_rd_data_f[16:1]) |\n ({16{btb_sel_f[0]}} & btb_vbank0_rd_data_f[16:1]) );\n\n\n logic [1:0] hist0_raw, hist1_raw, pc4_raw, pret_raw;\n\n // a valid taken target needs to kill the next fetch as we compute the target address\n assign ifu_bp_hit_taken_f = |(vwayhit_f[1:0] & hist1_raw[1:0]) & ifc_fetch_req_f & ~leak_one_f_d1 & ~dec_tlu_bpred_disable;\n\n\n // Don't put calls/rets/ja in the predictor, force the bht taken instead\n assign bht_force_taken_f[1:0] = {(btb_vbank1_rd_data_f[CALL] | btb_vbank1_rd_data_f[RET]),\n (btb_vbank0_rd_data_f[CALL] | btb_vbank0_rd_data_f[RET])};\n\n\n // taken and valid, otherwise, branch errors must clear the bht\n assign bht_valid_f[1:0] = vwayhit_f[1:0];\n\n assign bht_vbank0_rd_data_f[1:0] = ( ({2{fetch_start_f[0]}} & bht_bank0_rd_data_f[1:0]) |\n ({2{fetch_start_f[1]}} & bht_bank1_rd_data_f[1:0]) );\n\n assign bht_vbank1_rd_data_f[1:0] = ( ({2{fetch_start_f[0]}} & bht_bank1_rd_data_f[1:0]) |\n ({2{fetch_start_f[1]}} & bht_bank0_rd_data_p1_f[1:0]) );\n\n\n assign bht_dir_f[1:0] = {(bht_force_taken_f[1] | bht_vbank1_rd_data_f[1]) & bht_valid_f[1],\n (bht_force_taken_f[0] | bht_vbank0_rd_data_f[1]) & bht_valid_f[0]};\n\n assign ifu_bp_inst_mask_f = (ifu_bp_hit_taken_f & btb_sel_f[1]) | ~ifu_bp_hit_taken_f;\n\n\n\n\n // Branch prediction info is sent with the 2byte lane associated with the end of the branch.\n // Cases\n // BANK1 BANK0\n // -------------------------------\n // | : | : |\n // -------------------------------\n // <------------> : PC4 branch, offset, should be in B1 (indicated on [2])\n // <------------> : PC4 branch, no offset, indicate PC4, VALID, HIST on [1]\n // <------------> : PC4 branch, offset, indicate PC4, VALID, HIST on [0]\n // <------> : PC2 branch, offset, indicate VALID, HIST on [1]\n // <------> : PC2 branch, no offset, indicate VALID, HIST on [0]\n //\n\n\n\n assign hist1_raw[1:0] = bht_force_taken_f[1:0] | {bht_vbank1_rd_data_f[1],\n bht_vbank0_rd_data_f[1]};\n\n assign hist0_raw[1:0] = {bht_vbank1_rd_data_f[0],\n bht_vbank0_rd_data_f[0]};\n\n\n assign pc4_raw[1:0] = {vwayhit_f[1] & btb_vbank1_rd_data_f[PC4],\n vwayhit_f[0] & btb_vbank0_rd_data_f[PC4]};\n\n assign pret_raw[1:0] = {vwayhit_f[1] & ~btb_vbank1_rd_data_f[CALL] & btb_vbank1_rd_data_f[RET],\n vwayhit_f[0] & ~btb_vbank0_rd_data_f[CALL] & btb_vbank0_rd_data_f[RET]};\n\n // GHR\n\n\n // count the valids with masking based on first taken\n assign num_valids[1:0] = countones(bht_valid_f[1:0]);\n\n // Note that the following property holds\n // P: prior ghr, H: history bit of last valid branch in line (could be 1 or 0)\n // Num valid branches What new GHR must be\n // 2 0H\n // 1 PH\n // 0 PP\n\n assign final_h = |(btb_sel_f[1:0] & bht_dir_f[1:0]);\n\n assign merged_ghr[pt.BHT_GHR_SIZE-1:0] = (\n ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h2}} & {fghr[pt.BHT_GHR_SIZE-3:0], 1'b0, final_h}) | // 0H\n ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h1}} & {fghr[pt.BHT_GHR_SIZE-2:0], final_h}) | // PH\n ({pt.BHT_GHR_SIZE{num_valids[1:0] == 2'h0}} & {fghr[pt.BHT_GHR_SIZE-1:0]}) ); // PP\n\n logic [pt.BHT_GHR_SIZE-1:0] exu_flush_ghr;\n assign exu_flush_ghr[pt.BHT_GHR_SIZE-1:0] = exu_mp_fghr[pt.BHT_GHR_SIZE-1:0];\n\n assign fghr_ns[pt.BHT_GHR_SIZE-1:0] = ( ({pt.BHT_GHR_SIZE{exu_flush_final_d1}} & exu_flush_ghr[pt.BHT_GHR_SIZE-1:0]) |\n ({pt.BHT_GHR_SIZE{~exu_flush_final_d1 & ifc_fetch_req_f & ic_hit_f & ~leak_one_f_d1}} & merged_ghr[pt.BHT_GHR_SIZE-1:0]) |\n ({pt.BHT_GHR_SIZE{~exu_flush_final_d1 & ~(ifc_fetch_req_f & ic_hit_f & ~leak_one_f_d1)}} & fghr[pt.BHT_GHR_SIZE-1:0]));\n\n rvdffie #(.WIDTH(pt.BHT_GHR_SIZE+3),.OVERRIDE(1)) fetchghr (.*,\n .din ({exu_flush_final, exu_mp_way, leak_one_f, fghr_ns[pt.BHT_GHR_SIZE-1:0]}),\n .dout({exu_flush_final_d1, exu_mp_way_f, leak_one_f_d1, fghr[pt.BHT_GHR_SIZE-1:0]}));\n\n assign ifu_bp_fghr_f[pt.BHT_GHR_SIZE-1:0] = fghr[pt.BHT_GHR_SIZE-1:0];\n\n\n assign ifu_bp_way_f[1:0] = way_raw[1:0];\n assign ifu_bp_hist1_f[1:0] = hist1_raw[1:0];\n assign ifu_bp_hist0_f[1:0] = hist0_raw[1:0];\n assign ifu_bp_pc4_f[1:0] = pc4_raw[1:0];\n\n assign ifu_bp_valid_f[1:0] = vwayhit_f[1:0] & ~{2{dec_tlu_bpred_disable}};\n assign ifu_bp_ret_f[1:0] = pret_raw[1:0];\n\n\n // compute target\n // Form the fetch group offset based on the btb hit location and the location of the branch within the 4 byte chunk\n\n// .i 5\n// .o 3\n// .ilb bht_dir_f[1] bht_dir_f[0] fetch_start_f[1] fetch_start_f[0] btb_rd_pc4_f\n// .ob bloc_f[1] bloc_f[0] use_fa_plus\n// .type fr\n//\n//\n// ## rotdir[1:0] fs pc4 off fapl\n// -1 01 - 01 0\n// 10 01 - 10 0\n//\n// -1 10 - 10 0\n// 10 10 0 01 1\n// 10 10 1 01 0\nlogic [1:0] bloc_f;\nlogic use_fa_plus;\nassign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0]\n & fetch_start_f[0]);\nassign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0]\n & ~fetch_start_f[0]);\nassign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0] & ~btb_rd_pc4_f);\n\n\n\n\n assign btb_fg_crossing_f = fetch_start_f[0] & btb_sel_f[0] & btb_rd_pc4_f;\n\n assign bp_total_branch_offset_f = bloc_f[1] ^ btb_rd_pc4_f;\n\n logic [31:2] adder_pc_in_f, ifc_fetch_adder_prior;\n rvdfflie #(.WIDTH(30), .LEFT(19)) faddrf_ff (.*, .en(ifc_fetch_req_f & ~ifu_bp_hit_taken_f & ic_hit_f), .din(ifc_fetch_addr_f[31:2]), .dout(ifc_fetch_adder_prior[31:2]));\n\n\n assign ifu_bp_poffset_f[11:0] = btb_rd_tgt_f[11:0];\n\n assign adder_pc_in_f[31:2] = ( ({30{ use_fa_plus}} & fetch_addr_p1_f[31:2]) |\n ({30{ btb_fg_crossing_f}} & ifc_fetch_adder_prior[31:2]) |\n ({30{~btb_fg_crossing_f & ~use_fa_plus}} & ifc_fetch_addr_f[31:2]));\n\n rvbradder predtgt_addr (.pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}),\n .offset(btb_rd_tgt_f[11:0]),\n .dout(bp_btb_target_adder_f[31:1])\n );\n // mux in the return stack address here for a predicted return assuming the RS is valid, quite if no prediction\n assign ifu_bp_btb_target_f[31:1] = (({31{btb_rd_ret_f & ~btb_rd_call_f & rets_out[0][0] & ifu_bp_hit_taken_f}} & rets_out[0][31:1]) |\n ({31{~(btb_rd_ret_f & ~btb_rd_call_f & rets_out[0][0]) & ifu_bp_hit_taken_f}} & bp_btb_target_adder_f[31:1]) );\n\n\n // ----------------------------------------------------------------------\n // Return Stack\n // ----------------------------------------------------------------------\n\n rvbradder rs_addr (.pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}),\n .offset({11'b0, ~btb_rd_pc4_f}),\n .dout(bp_rs_call_target_f[31:1])\n );\n\n assign rs_push = (btb_rd_call_f & ~btb_rd_ret_f & ifu_bp_hit_taken_f);\n assign rs_pop = (btb_rd_ret_f & ~btb_rd_call_f & ifu_bp_hit_taken_f);\n assign rs_hold = ~rs_push & ~rs_pop;\n\n\n\n // Fetch based (bit 0 is a valid)\n assign rets_in[0][31:0] = ( ({32{rs_push}} & {bp_rs_call_target_f[31:1], 1'b1}) | // target[31:1], valid\n ({32{rs_pop}} & rets_out[1][31:0]) );\n\n assign rsenable[0] = ~rs_hold;\n\n for (i=0; i0) begin\n assign rets_in[i][31:0] = ( ({32{rs_push}} & rets_out[i-1][31:0]) |\n ({32{rs_pop}} & rets_out[i+1][31:0]) );\n assign rsenable[i] = rs_push | rs_pop;\n end\n rvdffe #(32) rets_ff (.*, .en(rsenable[i]), .din(rets_in[i][31:0]), .dout(rets_out[i][31:0]));\n\n end : retstack\n\n // ----------------------------------------------------------------------\n // WRITE\n // ----------------------------------------------------------------------\n\n\n assign dec_tlu_error_wb = dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb;\n\n assign btb_error_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO];\n\n assign dec_tlu_way_wb = dec_tlu_br0_way_wb;\n\n assign btb_valid = exu_mp_valid & ~dec_tlu_error_wb;\n\n assign btb_wr_tag[pt.BTB_BTAG_SIZE-1:0] = exu_mp_btag[pt.BTB_BTAG_SIZE-1:0];\n\n if(!pt.BTB_FULLYA) begin\n\n if(pt.BTB_BTAG_FOLD) begin : btbfold\n el2_btb_tag_hash_fold #(.pt(pt)) rdtagf (.hash(fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]),\n .pc({ifc_fetch_addr_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));\n el2_btb_tag_hash_fold #(.pt(pt)) rdtagp1f(.hash(fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]),\n .pc({fetch_addr_p1_f[ pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));\n end\n else begin : btbfold\n el2_btb_tag_hash #(.pt(pt)) rdtagf(.hash(fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0]),\n .pc({ifc_fetch_addr_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));\n el2_btb_tag_hash #(.pt(pt)) rdtagp1f(.hash(fetch_rd_tag_p1_f[pt.BTB_BTAG_SIZE-1:0]),\n .pc({fetch_addr_p1_f[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1]}));\n end\n\n assign btb_wr_en_way0 = ( ({{~exu_mp_way & exu_mp_valid_write & ~dec_tlu_error_wb}}) |\n ({{~dec_tlu_way_wb & dec_tlu_error_wb}}));\n\n assign btb_wr_en_way1 = ( ({{exu_mp_way & exu_mp_valid_write & ~dec_tlu_error_wb}}) |\n ({{dec_tlu_way_wb & dec_tlu_error_wb}}));\n assign btb_wr_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = dec_tlu_error_wb ? btb_error_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] : exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO];\n\n\n assign vwayhit_f[1:0] = ( ({2{fetch_start_f[0]}} & {wayhit_f[1:0]}) |\n ({2{fetch_start_f[1]}} & {wayhit_p1_f[0], wayhit_f[1]})) & {eoc_mask, 1'b1};\n\n end // if (!pt.BTB_FULLYA)\n\n assign btb_wr_data[BTB_DWIDTH-1:0] = {btb_wr_tag[pt.BTB_BTAG_SIZE-1:0], exu_mp_tgt[pt.BTB_TOFFSET_SIZE-1:0], exu_mp_pc4, exu_mp_boffset,\n exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid} ;\n\n assign exu_mp_valid_write = exu_mp_valid & exu_mp_ataken & ~exu_mp_pkt.valid;\n logic [1:0] bht_wr_data0, bht_wr_data2;\n logic [1:0] bht_wr_en0, bht_wr_en2;\n\n assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset;\n assign bht_wr_en0[1:0] = {2{exu_mp_valid & ~exu_mp_call & ~exu_mp_ret & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank};\n assign bht_wr_en2[1:0] = {2{dec_tlu_br0_v_wb}} & {dec_tlu_br0_middle_wb, ~dec_tlu_br0_middle_wb} ;\n\n // Experiments show this is the best priority scheme for same bank/index writes at the same time.\n assign bht_wr_data0[1:0] = exu_mp_hist[1:0]; // lowest priority\n assign bht_wr_data2[1:0] = dec_tlu_br0_hist_wb[1:0]; // highest priority\n\n\n\n logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] bht_rd_addr_f, bht_rd_addr_p1_f, bht_wr_addr0, bht_wr_addr2;\n\n logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] mp_hashed, br0_hashed_wb, bht_rd_addr_hashed_f, bht_rd_addr_hashed_p1_f;\n el2_btb_ghr_hash #(.pt(pt)) mpghrhs (.hashin(exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_mp_eghr[pt.BHT_GHR_SIZE-1:0]), .hash(mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));\n el2_btb_ghr_hash #(.pt(pt)) br0ghrhs (.hashin(dec_tlu_br0_addr_wb[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(exu_i0_br_fghr_wb[pt.BHT_GHR_SIZE-1:0]), .hash(br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));\n el2_btb_ghr_hash #(.pt(pt)) fghrhs (.hashin(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));\n el2_btb_ghr_hash #(.pt(pt)) fghrhs_p1 (.hashin(btb_rd_addr_p1_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]), .ghr(fghr[pt.BHT_GHR_SIZE-1:0]), .hash(bht_rd_addr_hashed_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO]));\n\n assign bht_wr_addr0[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = mp_hashed[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO];\n assign bht_wr_addr2[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO];\n assign bht_rd_addr_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = bht_rd_addr_hashed_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO];\n assign bht_rd_addr_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = bht_rd_addr_hashed_p1_f[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO];\n\n\n // ----------------------------------------------------------------------\n // Structures. Using FLOPS\n // ----------------------------------------------------------------------\n // BTB\n // Entry -> tag[pt.BTB_BTAG_SIZE-1:0], toffset[11:0], pc4, boffset, call, ret, valid\n\n if(!pt.BTB_FULLYA) begin\n\n for (j=0 ; j direction, strength\n //\n //-----------------------------------------------------------------------------\n\n// logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0] bht_bank_wr_data ;\n logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0] bht_bank_rd_data_out ;\n logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clken ;\n logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clk ;\n// logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0] bht_bank_sel ;\n\n for ( i=0; i<2; i++) begin : BANKS\n wire[pt.BHT_ARRAY_DEPTH-1:0] wr0, wr1;\n assign wr0 = pt.BHT_ARRAY_DEPTH'(bht_wr_en0[i] << bht_wr_addr0);\n assign wr1 = pt.BHT_ARRAY_DEPTH'(bht_wr_en2[i] << bht_wr_addr2);\n for (genvar k=0 ; k < (pt.BHT_ARRAY_DEPTH)/NUM_BHT_LOOP ; k++) begin : BHT_CLK_GROUP\n assign bht_bank_clken[i][k] = (bht_wr_en0[i] & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) |\n (bht_wr_en2[i] & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH));\n`ifndef RV_FPGA_OPTIMIZE\n rvclkhdr bht_bank_grp_cgc ( .en(bht_bank_clken[i][k]), .l1clk(bht_bank_clk[i][k]), .* ); // ifndef RV_FPGA_OPTIMIZE\n`else\n assign bht_bank_clk[i][k] = clk;\n`endif\n\n for (j=0 ; j cdecode.e\n\n// 2) espresso -Dso -oeqntott cdecode.e | addassign > compress_equations\n\n// to generate the legal (16b compressed instruction is legal) equation below:\n\n// 1) coredecode -in cdecode -legal > clegal.e\n\n// 2) espresso -Dso -oeqntott clegal.e | addassign > clegal_equation\n\n\n\n\n\n// espresso decodes\nassign rdrd = (!i[14]&i[6]&i[1]) | (!i[15]&i[14]&i[11]&i[0]) | (!i[14]&i[5]&i[1]) | (\n !i[15]&i[14]&i[10]&i[0]) | (!i[14]&i[4]&i[1]) | (!i[15]&i[14]&i[9]\n &i[0]) | (!i[14]&i[3]&i[1]) | (!i[15]&i[14]&!i[8]&i[0]) | (!i[14]\n &i[2]&i[1]) | (!i[15]&i[14]&i[7]&i[0]) | (!i[15]&i[1]) | (!i[15]\n &!i[13]&i[0]);\n\nassign rdrs1 = (!i[14]&i[12]&i[11]&i[1]) | (!i[14]&i[12]&i[10]&i[1]) | (!i[14]\n &i[12]&i[9]&i[1]) | (!i[14]&i[12]&i[8]&i[1]) | (!i[14]&i[12]&i[7]\n &i[1]) | (!i[14]&!i[12]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]\n &i[12]&i[6]&i[1]) | (!i[14]&i[12]&i[5]&i[1]) | (!i[14]&i[12]&i[4]\n &i[1]) | (!i[14]&i[12]&i[3]&i[1]) | (!i[14]&i[12]&i[2]&i[1]) | (\n !i[15]&!i[14]&!i[13]&i[0]) | (!i[15]&!i[14]&i[1]);\n\nassign rs2rs2 = (i[15]&i[6]&i[1]) | (i[15]&i[5]&i[1]) | (i[15]&i[4]&i[1]) | (\n i[15]&i[3]&i[1]) | (i[15]&i[2]&i[1]) | (i[15]&i[14]&i[1]);\n\nassign rdprd = (i[15]&!i[14]&!i[13]&i[0]);\n\nassign rdprs1 = (i[15]&!i[13]&i[0]) | (i[15]&i[14]&i[0]) | (i[14]&!i[1]&!i[0]);\n\nassign rs2prs2 = (i[15]&!i[14]&!i[13]&i[11]&i[10]&i[0]) | (i[15]&!i[1]&!i[0]);\n\nassign rs2prd = (!i[15]&!i[1]&!i[0]);\n\nassign uimm9_2 = (!i[14]&!i[1]&!i[0]);\n\nassign ulwimm6_2 = (!i[15]&i[14]&!i[1]&!i[0]);\n\nassign ulwspimm7_2 = (!i[15]&i[14]&i[1]);\n\nassign rdeq2 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]);\n\nassign rdeq1 = (!i[14]&i[12]&i[11]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]\n &i[12]&i[10]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[9]\n &!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[8]&!i[6]&!i[5]\n &!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[7]&!i[6]&!i[5]&!i[4]&!i[3]\n &!i[2]&i[1]) | (!i[15]&!i[14]&i[13]);\n\nassign rs1eq2 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]) | (i[14]\n &i[1]) | (!i[14]&!i[1]&!i[0]);\n\nassign sbroffset8_1 = (i[15]&i[14]&i[0]);\n\nassign simm9_4 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]);\n\nassign simm5_0 = (!i[14]&!i[13]&i[11]&!i[10]&i[0]) | (!i[15]&!i[13]&i[0]);\n\nassign sjaloffset11_1 = (!i[14]&i[13]);\n\nassign sluimm17_12 = (!i[15]&i[14]&i[13]&i[7]) | (!i[15]&i[14]&i[13]&!i[8]) | (\n !i[15]&i[14]&i[13]&i[9]) | (!i[15]&i[14]&i[13]&i[10]) | (!i[15]&i[14]\n &i[13]&i[11]);\n\nassign uimm5_0 = (i[15]&!i[14]&!i[13]&!i[11]&i[0]) | (!i[15]&!i[14]&i[1]);\n\nassign uswimm6_2 = (i[15]&!i[1]&!i[0]);\n\nassign uswspimm7_2 = (i[15]&i[14]&i[1]);\n\nassign o[31] = 1'b0;\n\nassign o[30] = (i[15]&!i[14]&!i[13]&i[10]&!i[6]&!i[5]&i[0]) | (i[15]&!i[14]\n &!i[13]&!i[11]&i[10]&i[0]);\n\nassign o[29] = 1'b0;\n\nassign o[28] = 1'b0;\n\nassign o[27] = 1'b0;\n\nassign o[26] = 1'b0;\n\nassign o[25] = 1'b0;\n\nassign o[24] = 1'b0;\n\nassign o[23] = 1'b0;\n\nassign o[22] = 1'b0;\n\nassign o[21] = 1'b0;\n\nassign o[20] = (!i[14]&i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]\n &!i[3]&!i[2]&i[1]);\n\nassign o[19] = 1'b0;\n\nassign o[18] = 1'b0;\n\nassign o[17] = 1'b0;\n\nassign o[16] = 1'b0;\n\nassign o[15] = 1'b0;\n\nassign o[14] = (i[15]&!i[14]&!i[13]&!i[11]&i[0]) | (i[15]&!i[14]&!i[13]&!i[10]\n &i[0]) | (i[15]&!i[14]&!i[13]&i[6]&i[0]) | (i[15]&!i[14]&!i[13]&i[5]\n &i[0]);\n\nassign o[13] = (i[15]&!i[14]&!i[13]&i[11]&!i[10]&i[0]) | (i[15]&!i[14]&!i[13]\n &i[11]&i[6]&i[0]) | (i[14]&!i[0]);\n\nassign o[12] = (i[15]&!i[14]&!i[13]&i[6]&i[5]&i[0]) | (i[15]&!i[14]&!i[13]&!i[11]\n &i[0]) | (i[15]&!i[14]&!i[13]&!i[10]&i[0]) | (!i[15]&!i[14]&i[1]) | (\n i[15]&i[14]&i[13]);\n\nassign o[11] = 1'b0;\n\nassign o[10] = 1'b0;\n\nassign o[9] = 1'b0;\n\nassign o[8] = 1'b0;\n\nassign o[7] = 1'b0;\n\nassign o[6] = (i[15]&!i[14]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[0]) | (!i[14]&i[13]) | (\n i[15]&i[14]&i[0]);\n\nassign o[5] = (i[15]&!i[0]) | (i[15]&i[11]&i[10]) | (i[13]&!i[8]) | (i[13]&i[7]) | (\n i[13]&i[9]) | (i[13]&i[10]) | (i[13]&i[11]) | (!i[14]&i[13]) | (\n i[15]&i[14]);\n\nassign o[4] = (!i[14]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[0]) | (!i[15]&!i[14]\n &!i[0]) | (!i[14]&i[6]&!i[0]) | (!i[15]&i[14]&i[0]) | (!i[14]&i[5]\n &!i[0]) | (!i[14]&i[4]&!i[0]) | (!i[14]&!i[13]&i[0]) | (!i[14]&i[3]\n &!i[0]) | (!i[14]&i[2]&!i[0]);\n\nassign o[3] = (!i[14]&i[13]);\n\nassign o[2] = (!i[14]&i[12]&i[11]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]\n &i[12]&i[10]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[9]\n &!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[8]&!i[6]&!i[5]\n &!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[7]&!i[6]&!i[5]&!i[4]&!i[3]\n &!i[2]&i[1]) | (i[15]&!i[14]&!i[12]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]\n &!i[0]) | (!i[15]&i[13]&!i[8]) | (!i[15]&i[13]&i[7]) | (!i[15]&i[13]\n &i[9]) | (!i[15]&i[13]&i[10]) | (!i[15]&i[13]&i[11]) | (!i[14]&i[13]);\n\n// 32b instruction has lower two bits 2'b11\n\nassign o[1] = 1'b1;\n\nassign o[0] = 1'b1;\n\nassign legal = (!i[13]&!i[12]&i[11]&i[1]&!i[0]) | (!i[13]&!i[12]&i[10]&i[1]&!i[0]) | (\n !i[15]&!i[13]&i[11]&!i[1]) | (!i[13]&!i[12]&i[9]&i[1]&!i[0]) | (\n !i[13]&!i[12]&i[8]&i[1]&!i[0]) | (!i[15]&!i[13]&i[6]&!i[1]) | (i[15]\n &!i[12]&!i[1]&i[0]) | (!i[13]&!i[12]&i[7]&i[1]&!i[0]) | (!i[15]&!i[13]\n &i[5]&!i[1]) | (!i[12]&i[6]&!i[1]&i[0]) | (i[15]&!i[13]&i[6]&i[1]\n &!i[0]) | (!i[15]&!i[13]&i[10]&!i[1]) | (!i[12]&i[5]&!i[1]&i[0]) | (\n i[12]&i[11]&!i[10]&!i[1]&i[0]) | (i[15]&!i[13]&i[5]&i[1]&!i[0]) | (\n !i[15]&!i[13]&i[9]&!i[1]) | (i[13]&i[12]&!i[1]&i[0]) | (i[15]&!i[13]\n &i[4]&i[1]&!i[0]) | (!i[15]&!i[13]&i[8]&!i[1]) | (i[15]&!i[13]&i[3]\n &i[1]&!i[0]) | (i[13]&i[4]&!i[1]&i[0]) | (i[15]&!i[13]&i[2]&i[1]&!i[0]) | (\n !i[15]&!i[13]&i[7]&!i[1]) | (i[13]&i[3]&!i[1]&i[0]) | (i[13]&i[2]\n &!i[1]&i[0]) | (!i[14]&!i[12]&!i[1]&i[0]) | (i[15]&!i[13]&i[12]&i[1]\n &!i[0]) | (i[14]&!i[13]&i[7]&!i[0]) | (i[14]&!i[13]&i[8]&!i[0]) | (\n i[14]&!i[13]&i[9]&!i[0]) | (!i[15]&!i[14]&!i[13]&!i[12]&i[1]&!i[0]) | (\n i[14]&!i[13]&i[10]&!i[0]) | (i[14]&!i[13]&i[11]&!i[0]) | (!i[15]\n &!i[13]&i[12]&!i[1]) | (i[15]&i[14]&!i[13]&!i[0]) | (i[14]&!i[13]\n &!i[1]);\n\n\n\n\nendmodule\n" }, { "path": "design/ifu/el2_ifu_ic_mem.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n////////////////////////////////////////////////////\n// ICACHE DATA & TAG MODULE WRAPPER //\n/////////////////////////////////////////////////////\nmodule el2_ifu_ic_mem\nimport el2_pkg::*;\n #(\n`include \"el2_param.vh\"\n )\n (\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic rst_l, // reset, active low\n input logic clk_override, // Override non-functional clock gating\n input logic dec_tlu_core_ecc_disable, // Disable ECC checking\n\n input logic [31:1] ic_rw_addr,\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en , // Which way to write\n input logic ic_rd_en , // Read enable\n input logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.\n input logic ic_debug_rd_en, // Icache debug rd\n input logic ic_debug_wr_en, // Icache debug wr\n input logic ic_debug_tag_array, // Debug tag array\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.\n input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.\n input logic ic_sel_premux_data, // Select the pre_muxed data\n\n input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC\n output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n output logic [25:0] ictag_debug_rd_data,// Debug icache tag.\n input logic [70:0] ic_debug_wr_data, // Debug wr cache.\n\n output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank\n output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr, // ecc error per bank\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid from the I$ tag valid outside (in flops).\n\n el2_mem_if.veer_icache_src icache_export,\n\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, // ic_rd_hit[3:0]\n output logic ic_tag_perr, // Tag Parity error\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // Flop scan mode control\n /*pragma coverage on*/\n ) ;\n\n // split the veer_icache_src interface into veer_icache_data and veer_icache_tag\n el2_mem_if local_icache_export();\n\n always_comb begin\n // data\n icache_export.ic_b_sb_wren = local_icache_export.ic_b_sb_wren;\n icache_export.ic_b_sb_bit_en_vec = local_icache_export.ic_b_sb_bit_en_vec;\n icache_export.ic_sb_wr_data = local_icache_export.ic_sb_wr_data;\n icache_export.ic_rw_addr_bank_q = local_icache_export.ic_rw_addr_bank_q;\n icache_export.ic_bank_way_clken_final = local_icache_export.ic_bank_way_clken_final;\n icache_export.ic_bank_way_clken_final_up = local_icache_export.ic_bank_way_clken_final_up;\n\n local_icache_export.wb_packeddout_pre = icache_export.wb_packeddout_pre;\n local_icache_export.wb_dout_pre_up = icache_export.wb_dout_pre_up;\n\n // tag\n icache_export.ic_tag_clken_final = local_icache_export.ic_tag_clken_final;\n icache_export.ic_tag_wren_q = local_icache_export.ic_tag_wren_q;\n icache_export.ic_tag_wren_biten_vec = local_icache_export.ic_tag_wren_biten_vec;\n icache_export.ic_tag_wr_data = local_icache_export.ic_tag_wr_data;\n icache_export.ic_rw_addr_q = local_icache_export.ic_rw_addr_q;\n\n local_icache_export.ic_tag_data_raw_pre = icache_export.ic_tag_data_raw_pre;\n local_icache_export.ic_tag_data_raw_packed_pre = icache_export.ic_tag_data_raw_packed_pre;\n end\n\n EL2_IC_TAG #(.pt(pt)) ic_tag_inst\n (\n .*,\n .icache_export(local_icache_export.veer_icache_tag),\n .ic_wr_en (ic_wr_en[pt.ICACHE_NUM_WAYS-1:0]),\n .ic_debug_addr(ic_debug_addr[pt.ICACHE_INDEX_HI:3]),\n .ic_rw_addr (ic_rw_addr[31:3])\n ) ;\n\n EL2_IC_DATA #(.pt(pt)) ic_data_inst\n (\n .*,\n .icache_export(local_icache_export.veer_icache_data),\n .ic_wr_en (ic_wr_en[pt.ICACHE_NUM_WAYS-1:0]),\n .ic_debug_addr(ic_debug_addr[pt.ICACHE_INDEX_HI:3]),\n .ic_rw_addr (ic_rw_addr[31:1])\n ) ;\n\n endmodule\n\n\n/////////////////////////////////////////////////\n////// ICACHE DATA MODULE ////////////////////\n/////////////////////////////////////////////////\nmodule EL2_IC_DATA\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic clk,\n input logic active_clk,\n input logic rst_l,\n input logic clk_override,\n\n input logic [31:1] ic_rw_addr,\n input logic [pt.ICACHE_NUM_WAYS-1:0]ic_wr_en,\n input logic ic_rd_en, // Read enable\n\n input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC\n output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [70:0] ic_debug_wr_data, // Debug wr cache.\n output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,\n output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank\n input logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.\n input logic ic_debug_rd_en, // Icache debug rd\n input logic ic_debug_wr_en, // Icache debug wr\n input logic ic_debug_tag_array, // Debug tag array\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.\n input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.\n input logic ic_sel_premux_data, // Select the pre_muxed data\n\n input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit,\n el2_mem_if.veer_icache_data icache_export,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n\n ) ;\n\n logic [pt.ICACHE_TAG_INDEX_LO-1:1] ic_rw_addr_ff;\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] ic_b_sb_wren; //bank x ways\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] ic_b_sb_rden; //bank x ways\n\n\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_b_rden; //bank\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_b_rden_ff; //bank\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_debug_sel_sb;\n\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][70:0] wb_dout ; // ways x bank\n logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_sb_wr_data, ic_bank_wr_data, wb_dout_ecc_bank;\n logic [pt.ICACHE_NUM_WAYS-1:0] [141:0] wb_dout_way_pre;\n logic [pt.ICACHE_NUM_WAYS-1:0] [63:0] wb_dout_way, wb_dout_way_with_premux;\n logic [141:0] wb_dout_ecc;\n\n logic [pt.ICACHE_BANKS_WAY-1:0] bank_check_en;\n\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] ic_bank_way_clken;\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final_up;\n\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_rd_way_en; // debug wr_way\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_rd_way_en_ff; // debug wr_way\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_wr_way_en; // debug wr_way\n logic [pt.ICACHE_INDEX_HI:1] ic_rw_addr_q;\n\n logic [pt.ICACHE_BANKS_WAY-1:0] [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;\n\n logic [pt.ICACHE_TAG_LO-1 : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_q_inc;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit_q;\n\n\n\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_b_sram_en;\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_b_read_en;\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_b_write_en;\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] [31 : pt.ICACHE_DATA_INDEX_LO] wb_index_hold;\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] write_bypass_en; //bank\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] write_bypass_en_ff; //bank\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] index_valid; //bank\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] ic_b_clear_en;\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] ic_b_addr_match;\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] ic_b_addr_match_index_only;\n\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_b_sram_en_up;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_b_read_en_up;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_b_write_en_up;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] [31 : pt.ICACHE_DATA_INDEX_LO] wb_index_hold_up;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] write_bypass_en_up; //bank\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] write_bypass_en_ff_up; //bank\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] index_valid_up; //bank\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] ic_b_clear_en_up;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] ic_b_addr_match_up;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_BYPASS-1:0] ic_b_addr_match_index_only_up;\n\n\n logic [pt.ICACHE_BANKS_WAY-1:0] [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr;\n logic [pt.ICACHE_BANKS_WAY-1:0] [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only;\n\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] [31 : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_up;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] [pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_b_rw_addr_index_only_up;\n\n\n\n logic ic_rd_en_with_debug;\n logic ic_rw_addr_wrap, ic_cacheline_wrap_ff;\n logic ic_debug_rd_en_ff;\n\n // Use exported ICache interface. Some signals are assigned here, some in the blocks below.\n always_comb begin\n icache_export.ic_b_sb_wren = ic_b_sb_wren;\n icache_export.ic_sb_wr_data = ic_sb_wr_data;\n icache_export.ic_rw_addr_bank_q = ic_rw_addr_bank_q;\n icache_export.ic_bank_way_clken_final =ic_bank_way_clken_final;\n icache_export.ic_bank_way_clken_final_up =ic_bank_way_clken_final_up;\n end\n\n\n//-----------------------------------------------------------\n// ----------- Logic section starts here --------------------\n//-----------------------------------------------------------\n assign ic_debug_rd_way_en[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{ic_debug_rd_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;\n assign ic_debug_wr_way_en[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ~ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ;\n\n logic end_of_cache_line;\n assign end_of_cache_line = (pt.ICACHE_LN_SZ==7'h40) ? (&ic_rw_addr_q[5:4]) : ic_rw_addr_q[4];\n always_comb begin : clkens\n ic_bank_way_clken = '0;\n\n for ( int i=0; i\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n\n//********************************************************************************\n// Icache closely coupled memory --- ICCM\n//********************************************************************************\n\nmodule el2_ifu_iccm_mem\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic rst_l, // reset, active low\n input logic clk_override, // Override non-functional clock gating\n\n input logic iccm_wren, // ICCM write enable\n input logic iccm_rden, // ICCM read enable\n input logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address\n input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle\n input logic iccm_correction_state, // ICCM under a correction - This is needed to guard replacements when hit\n input logic [2:0] iccm_wr_size, // ICCM write size\n input logic [77:0] iccm_wr_data, // ICCM write data\n\n el2_mem_if.veer_iccm iccm_mem_export, // RAM repositioned in testbench and connected by this interface\n\n output logic [63:0] iccm_rd_data, // ICCM read data\n output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // Scan mode control\n /*pragma coverage on*/\n\n);\n\n\n logic [pt.ICCM_NUM_BANKS-1:0] wren_bank;\n logic [pt.ICCM_NUM_BANKS-1:0] rden_bank;\n logic [pt.ICCM_NUM_BANKS-1:0] iccm_clken;\n logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;\n\n logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_dout, iccm_bank_dout_fn;\n logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data;\n logic [pt.ICCM_BITS-1:1] addr_bank_inc;\n logic [pt.ICCM_BANK_HI : 2] iccm_rd_addr_hi_q;\n logic [pt.ICCM_BANK_HI : 1] iccm_rd_addr_lo_q;\n logic [63:0] iccm_rd_data_pre;\n logic [63:0] iccm_data;\n logic [1:0] addr_incr;\n logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data_vec;\n\n // logic to handle hard persisten faults\n logic [1:0] [pt.ICCM_BITS-1:2] redundant_address;\n logic [1:0] [38:0] redundant_data;\n logic [1:0] redundant_valid;\n logic [pt.ICCM_NUM_BANKS-1:0] sel_red1, sel_red0, sel_red1_q, sel_red0_q;\n\n\n logic [38:0] redundant_data0_in, redundant_data1_in;\n logic redundant_lru, redundant_lru_in, redundant_lru_en;\n logic redundant_data0_en;\n logic redundant_data1_en;\n logic r0_addr_en, r1_addr_en;\n\n // Testing persistent flip\n // logic [3:0] not_iccm_bank_dout;\n // logic [15:3] ecc_insert_flip_in, ecc_insert_flip;\n // logic flip_en, flip_match, flip_match_q;\n //\n // assign flip_in = (iccm_rw_addr[3:2] != 2'b00); // dont flip when bank0 - this is to make some progress in DMA streaming cases\n // assign flip_en = iccm_rden;\n //\n // rvdffs #(1) flipmatch (.*,\n // .clk(clk),\n // .din(flip_in),\n // .en(flip_en),\n // .dout(flip_match_q));\n //\n // end of testing flip\n\n\n assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11) ? 2'b10: 2'b01;\n assign addr_bank_inc[pt.ICCM_BITS-1 : 1] = iccm_rw_addr[pt.ICCM_BITS-1 : 1] + addr_incr[1:0];\n\n for (genvar i=0; i> (16*iccm_rd_addr_lo_q[1]))});\n assign iccm_rd_data[63:0] = {iccm_data[63:0]};\n assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:2]][38:0]};\n\nendmodule // el2_ifu_iccm_mem\n" }, { "path": "design/ifu/el2_ifu_ifc_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// el2_ifu_ifc_ctl.sv\n// Function: Fetch pipe control\n//\n// Comments:\n//********************************************************************************\n\nmodule el2_ifu_ifc_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.\n\n input logic rst_l, // reset enable, from core pin\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // scan\n /*pragma coverage on*/\n\n input logic ic_hit_f, // Icache hit\n input logic ifu_ic_mb_empty, // Miss buffer empty\n\n input logic ifu_fb_consume1, // Aligner consumed 1 fetch buffer\n input logic ifu_fb_consume2, // Aligner consumed 2 fetch buffers\n\n input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush\n input logic exu_flush_final, // FLush\n input logic [31:1] exu_flush_path_final, // Flush path\n\n input logic ifu_bp_hit_taken_f, // btb hit, select the target path\n input logic [31:1] ifu_bp_btb_target_f, // predicted target PC\n\n input logic ic_dma_active, // IC DMA active, stop fetching\n input logic ic_write_stall, // IC is writing, stop fetching\n input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access\n\n input logic [31:0] dec_tlu_mrac_ff , // side_effect and cacheable for each region\n\n output logic [31:1] ifc_fetch_addr_f, // fetch addr F\n output logic [31:1] ifc_fetch_addr_bf, // fetch addr BF\n\n output logic ifc_fetch_req_f, // fetch request valid F\n\n output logic ifu_pmu_fetch_stall, // pmu event measuring fetch stall\n\n output logic ifc_fetch_uncacheable_bf, // The fetch request is uncacheable space. BF stage\n output logic ifc_fetch_req_bf, // Fetch request. Comes with the address. BF stage\n output logic ifc_fetch_req_bf_raw, // Fetch request without some qualifications. Used for clock-gating. BF stage\n output logic ifc_iccm_access_bf, // This request is to the ICCM. Do not generate misses to the bus.\n output logic ifc_region_acc_fault_bf, // Access fault. in ICCM region but offset is outside defined ICCM.\n\n output logic ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed\n\n\n );\n\n logic [31:1] fetch_addr_bf;\n logic [31:1] fetch_addr_next;\n logic [3:0] fb_write_f, fb_write_ns;\n\n logic fb_full_f_ns, fb_full_f;\n logic fb_right, fb_right2, fb_left, wfm, idle;\n logic sel_last_addr_bf, sel_next_addr_bf;\n logic miss_f, miss_a;\n logic flush_fb, dma_iccm_stall_any_f;\n logic mb_empty_mod, goto_idle, leave_idle;\n logic fetch_bf_en;\n logic line_wrap;\n logic fetch_addr_next_1;\n\n // FSM assignment\n typedef enum logic [1:0] { IDLE = 2'b00 ,\n FETCH = 2'b01 ,\n STALL = 2'b10 ,\n WFM = 2'b11 } state_t ;\n state_t state ;\n state_t next_state ;\n\n logic dma_stall;\n assign dma_stall = ic_dma_active | dma_iccm_stall_any_f;\n\n\n\n // Fetch address mux\n // - flush\n // - Miss *or* flush during WFM (icache miss buffer is blocking)\n // - Sequential\n\nif(pt.BTB_ENABLE==1) begin : genblock1\n logic sel_btb_addr_bf;\n\n assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f);\n assign sel_btb_addr_bf = ~exu_flush_final & ifc_fetch_req_f & ifu_bp_hit_taken_f & ic_hit_f;\n assign sel_next_addr_bf = ~exu_flush_final & ifc_fetch_req_f & ~ifu_bp_hit_taken_f & ic_hit_f;\n\n\n assign fetch_addr_bf[31:1] = ( ({31{exu_flush_final}} & exu_flush_path_final[31:1]) | // FLUSH path\n ({31{sel_last_addr_bf}} & ifc_fetch_addr_f[31:1]) | // MISS path\n ({31{sel_btb_addr_bf}} & {ifu_bp_btb_target_f[31:1]})| // BTB target\n ({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path\n\n\nend // if (pt.BTB_ENABLE=1)\n else begin\n assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f);\n assign sel_next_addr_bf = ~exu_flush_final & ifc_fetch_req_f & ic_hit_f;\n\n\n assign fetch_addr_bf[31:1] = ( ({31{exu_flush_final}} & exu_flush_path_final[31:1]) | // FLUSH path\n ({31{sel_last_addr_bf}} & ifc_fetch_addr_f[31:1]) | // MISS path\n ({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path\n\nend\n assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 30'b1), fetch_addr_next_1 };\n assign line_wrap = (fetch_addr_next[pt.ICACHE_TAG_INDEX_LO] ^ ifc_fetch_addr_f[pt.ICACHE_TAG_INDEX_LO]);\n\n assign fetch_addr_next_1 = line_wrap ? 1'b0 : ifc_fetch_addr_f[1];\n\n assign ifc_fetch_req_bf_raw = ~idle;\n assign ifc_fetch_req_bf = ifc_fetch_req_bf_raw &\n\n ~(fb_full_f_ns & ~(ifu_fb_consume2 | ifu_fb_consume1)) &\n ~dma_stall &\n ~ic_write_stall &\n ~dec_tlu_flush_noredir_wb;\n\n\n assign fetch_bf_en = exu_flush_final | ifc_fetch_req_f;\n\n assign miss_f = ifc_fetch_req_f & ~ic_hit_f & ~exu_flush_final;\n\n assign mb_empty_mod = (ifu_ic_mb_empty | exu_flush_final) & ~dma_stall & ~miss_f & ~miss_a;\n\n // Halt flushes and takes us to IDLE\n assign goto_idle = exu_flush_final & dec_tlu_flush_noredir_wb;\n // If we're in IDLE, and we get a flush, goto FETCH\n assign leave_idle = exu_flush_final & ~dec_tlu_flush_noredir_wb & idle;\n\n//.i 7\n//.o 2\n//.ilb state[1] state[0] reset_delayed miss_f mb_empty_mod goto_idle leave_idle\n//.ob next_state[1] next_state[0]\n//.type fr\n//\n//# fetch 01, stall 10, wfm 11, idle 00\n//-- 1---- 01\n//-- 0--1- 00\n//00 0--00 00\n//00 0--01 01\n//\n//01 01-0- 11\n//01 00-0- 01\n//\n//11 0-10- 01\n//11 0-00- 11\n\n assign next_state[1] = (~state[1] & state[0] & miss_f & ~goto_idle) |\n (state[1] & ~mb_empty_mod & ~goto_idle);\n\n assign next_state[0] = (~goto_idle & leave_idle) | (state[0] & ~goto_idle);\n\n assign flush_fb = exu_flush_final;\n\n // model fb write logic to mass balance the fetch buffers\n assign fb_right = ( ifu_fb_consume1 & ~ifu_fb_consume2 & (~ifc_fetch_req_f | miss_f)) | // Consumed and no new fetch\n (ifu_fb_consume2 & ifc_fetch_req_f); // Consumed 2 and new fetch\n\n\n assign fb_right2 = (ifu_fb_consume2 & (~ifc_fetch_req_f | miss_f)); // Consumed 2 and no new fetch\n\n assign fb_left = ifc_fetch_req_f & ~(ifu_fb_consume1 | ifu_fb_consume2) & ~miss_f;\n\n// CBH\n assign fb_write_ns[3:0] = ( ({4{(flush_fb)}} & 4'b0001) |\n ({4{~flush_fb & fb_right }} & {1'b0, fb_write_f[3:1]}) |\n ({4{~flush_fb & fb_right2}} & {2'b0, fb_write_f[3:2]}) |\n ({4{~flush_fb & fb_left }} & {fb_write_f[2:0], 1'b0}) |\n ({4{~flush_fb & ~fb_right & ~fb_right2 & ~fb_left}} & fb_write_f[3:0]));\n\n\n assign fb_full_f_ns = fb_write_ns[3];\n\n assign idle = state == IDLE ;\n assign wfm = state == WFM ;\n\n rvdffie #(10) fbwrite_ff (.*, .clk(free_l2clk),\n .din( {dma_iccm_stall_any, miss_f, ifc_fetch_req_bf, next_state[1:0], fb_full_f_ns, fb_write_ns[3:0]}),\n .dout({dma_iccm_stall_any_f, miss_a, ifc_fetch_req_f, state[1:0], fb_full_f, fb_write_f[3:0]}));\n\n assign ifu_pmu_fetch_stall = wfm |\n (ifc_fetch_req_bf_raw &\n ( (fb_full_f & ~(ifu_fb_consume2 | ifu_fb_consume1 | exu_flush_final)) |\n dma_stall));\n\n\n\n assign ifc_fetch_addr_bf[31:1] = fetch_addr_bf[31:1];\n\n rvdffpcie #(31) faddrf1_ff (.*, .en(fetch_bf_en), .din(fetch_addr_bf[31:1]), .dout(ifc_fetch_addr_f[31:1]));\n\n\n if (pt.ICCM_ENABLE) begin : genblock2\n logic iccm_acc_in_region_bf;\n logic iccm_acc_in_range_bf;\n rvrangecheck #( .CCM_SADR (pt.ICCM_SADR),\n .CCM_SIZE (pt.ICCM_SIZE) ) iccm_rangecheck (\n .addr ({ifc_fetch_addr_bf[31:1],1'b0}) ,\n .in_range (iccm_acc_in_range_bf) ,\n .in_region(iccm_acc_in_region_bf)\n );\n\n assign ifc_iccm_access_bf = iccm_acc_in_range_bf ;\n\n assign ifc_dma_access_ok = ( (~ifc_iccm_access_bf |\n (fb_full_f & ~(ifu_fb_consume2 | ifu_fb_consume1)) |\n (wfm & ~ifc_fetch_req_bf) |\n idle ) & ~exu_flush_final) |\n dma_iccm_stall_any_f;\n\n assign ifc_region_acc_fault_bf = ~iccm_acc_in_range_bf & iccm_acc_in_region_bf ;\n end\n else begin\n assign ifc_iccm_access_bf = 1'b0 ;\n assign ifc_dma_access_ok = 1'b0 ;\n assign ifc_region_acc_fault_bf = 1'b0 ;\n end\n\n assign ifc_fetch_uncacheable_bf = ~dec_tlu_mrac_ff[{ifc_fetch_addr_bf[31:28] , 1'b0 }] ; // bit 0 of each region description is the cacheable bit\n\nendmodule // el2_ifu_ifc_ctl\n\n" }, { "path": "design/ifu/el2_ifu_mem_ctl.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n\n\n//********************************************************************************\n// Function: Icache , iccm control\n// BFF -> F1 -> F2 -> A\n//********************************************************************************\n\nmodule el2_ifu_mem_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.\n input logic rst_l, // reset, active low\n\n input logic exu_flush_final, // Flush from the pipeline., includes flush lower\n input logic dec_tlu_flush_lower_wb, // Flush lower from the pipeline.\n input logic dec_tlu_flush_err_wb, // Flush from the pipeline due to perr.\n input logic dec_tlu_i0_commit_cmt, // committed i0 instruction\n input logic dec_tlu_force_halt, // force halt.\n\n input logic [31:1] ifc_fetch_addr_bf, // Fetch Address byte aligned always. F1 stage.\n input logic ifc_fetch_uncacheable_bf, // The fetch request is uncacheable space. F1 stage\n input logic ifc_fetch_req_bf, // Fetch request. Comes with the address. F1 stage\n input logic ifc_fetch_req_bf_raw, // Fetch request without some qualifications. Used for clock-gating. F1 stage\n input logic ifc_iccm_access_bf, // This request is to the ICCM. Do not generate misses to the bus.\n input logic ifc_region_acc_fault_bf, // Access fault. in ICCM region but offset is outside defined ICCM.\n input logic ifc_dma_access_ok, // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).\n input logic dec_tlu_fence_i_wb, // Fence.i instruction is committing. Clear all Icache valids.\n input logic ifu_bp_hit_taken_f, // Branch is predicted taken. Kill the fetch next cycle.\n\n input logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified\n\n output logic ifu_miss_state_idle, // No icache misses are outstanding.\n output logic ifu_ic_mb_empty, // Continue with normal fetching. This does not mean that miss is finished.\n output logic ic_dma_active , // In the middle of servicing dma request to ICCM. Do not make any new requests.\n output logic ic_write_stall, // Stall fetch the cycle we are writing the cache.\n\n/// PMU signals\n output logic ifu_pmu_ic_miss, // IC miss event\n output logic ifu_pmu_ic_hit, // IC hit event\n output logic ifu_pmu_bus_error, // Bus error event\n output logic ifu_pmu_bus_busy, // Bus busy event\n output logic ifu_pmu_bus_trxn, // Bus transaction\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic ifu_axi_awvalid,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,\n output logic [31:0] ifu_axi_awaddr,\n output logic [3:0] ifu_axi_awregion,\n output logic [7:0] ifu_axi_awlen,\n output logic [2:0] ifu_axi_awsize,\n output logic [1:0] ifu_axi_awburst,\n output logic ifu_axi_awlock,\n output logic [3:0] ifu_axi_awcache,\n output logic [2:0] ifu_axi_awprot,\n output logic [3:0] ifu_axi_awqos,\n\n output logic ifu_axi_wvalid,\n output logic [63:0] ifu_axi_wdata,\n output logic [7:0] ifu_axi_wstrb,\n output logic ifu_axi_wlast,\n\n output logic ifu_axi_bready,\n /*pragma coverage on*/\n\n // AXI Read Channels\n output logic ifu_axi_arvalid,\n input logic ifu_axi_arready,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,\n output logic [31:0] ifu_axi_araddr,\n output logic [3:0] ifu_axi_arregion,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [7:0] ifu_axi_arlen,\n output logic [2:0] ifu_axi_arsize,\n output logic [1:0] ifu_axi_arburst,\n output logic ifu_axi_arlock,\n output logic [3:0] ifu_axi_arcache,\n output logic [2:0] ifu_axi_arprot,\n output logic [3:0] ifu_axi_arqos,\n /*pragma coverage on*/\n\n input logic ifu_axi_rvalid,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic ifu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,\n input logic [63:0] ifu_axi_rdata,\n input logic [1:0] ifu_axi_rresp,\n\n input logic ifu_bus_clk_en,\n\n\n input logic dma_iccm_req, // dma iccm command (read or write)\n input logic [31:0] dma_mem_addr, // dma address\n input logic [2:0] dma_mem_sz, // size\n input logic dma_mem_write, // write\n input logic [63:0] dma_mem_wdata, // write data\n input logic [2:0] dma_mem_tag, // DMA Buffer entry number\n\n output logic iccm_dma_ecc_error,// Data read from iccm has an ecc error\n output logic iccm_dma_rvalid, // Data read from iccm is valid\n output logic [63:0] iccm_dma_rdata, // dma data read from iccm\n output logic [2:0] iccm_dma_rtag, // Tag of the DMA req\n output logic iccm_ready, // iccm ready to accept new command.\n\n\n// I$ & ITAG Ports\n output logic [31:1] ic_rw_addr, // Read/Write addresss to the Icache.\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en, // Icache write enable, when filling the Icache.\n output logic ic_rd_en, // Icache read enable.\n\n output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0] ic_wr_data, // Data to fill to the Icache. With ECC\n input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [25:0] ictag_debug_rd_data, // Debug icache tag.\n output logic [70:0] ic_debug_wr_data, // Debug wr cache.\n output logic [70:0] ifu_ic_debug_rd_data, // debug data read\n\n\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, //\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,\n\n output logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.\n output logic ic_debug_rd_en, // Icache debug rd\n output logic ic_debug_wr_en, // Icache debug wr\n output logic ic_debug_tag_array, // Debug tag array\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.\n\n\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid bits when accessing the Icache. One valid bit per way. F2 stage\n\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, // Compare hits from Icache tags. Per way. F2 stage\n input logic ic_tag_perr, // Icache Tag parity error\n\n // ICCM ports\n output logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address.\n output logic iccm_wren, // ICCM write enable (through the DMA)\n output logic iccm_rden, // ICCM read enable.\n output logic [77:0] iccm_wr_data, // ICCM write data.\n output logic [2:0] iccm_wr_size, // ICCM write location within DW.\n\n input logic [63:0] iccm_rd_data, // Data read from ICCM.\n input logic [77:0] iccm_rd_data_ecc, // Data + ECC read from ICCM.\n input logic [1:0] ifu_fetch_val,\n // IFU control signals\n output logic ic_hit_f, // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)\n output logic [1:0] ic_access_fault_f, // Access fault (bus error or ICCM access in region but out of offset range).\n output logic [1:0] ic_access_fault_type_f, // Access fault types\n output logic iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.\n output logic [1:0] iccm_rd_ecc_double_err, // This fetch has a double ICCM ECC error.\n output logic iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error.\n output logic iccm_dma_rd_ecc_double_err, // This fetch has a double ICCM DMA ECC error.\n output logic ic_error_start, // This has any I$ errors ( data/tag/ecc/parity )\n\n output logic ifu_async_error_start, // Or of the sb iccm, and all the icache errors sent to aligner to stop\n output logic iccm_dma_sb_error, // Single Bit ECC error from a DMA access\n output logic [1:0] ic_fetch_val_f, // valid bytes for fetch. To the Aligner.\n output logic [31:0] ic_data_f, // Data read from Icache or ICCM. To the Aligner.\n output logic [63:0] ic_premux_data, // Premuxed data to be muxed with Icache data\n output logic ic_sel_premux_data, // Select premux data.\n\n///// Debug\n input el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt , // Icache/tag debug read/write packet\n input logic dec_tlu_core_ecc_disable, // disable the ecc checking and flagging\n output logic ifu_ic_debug_rd_data_valid, // debug data valid.\n output logic iccm_buf_correct_ecc,\n output logic iccm_correction_state,\n\n input logic ifu_pmp_error,\n\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n );\n\n// Create different defines for ICACHE and ICCM enable combinations\n\n localparam NUM_OF_BEATS = 8 ;\n\n\n\n logic [31:3] ifu_ic_req_addr_f;\n logic uncacheable_miss_in ;\n logic uncacheable_miss_ff;\n\n\n\n logic bus_ifu_wr_en ;\n logic bus_ifu_wr_en_ff ;\n logic bus_ifu_wr_en_ff_q ;\n logic bus_ifu_wr_en_ff_wo_err ;\n logic [pt.ICACHE_NUM_WAYS-1:0] bus_ic_wr_en ;\n\n logic reset_tag_valid_for_miss ;\n\n\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status;\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status_mb_in;\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status_rep_new;\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status_mb_ff;\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status_new;\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status_hit_new;\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status_new_w_debug;\n logic [pt.ICACHE_NUM_WAYS-1:0] tagv_mb_in;\n logic [pt.ICACHE_NUM_WAYS-1:0] tagv_mb_ff;\n\n\n logic ifu_wr_data_comb_err ;\n logic ifu_byp_data_err_new;\n logic [1:0] ifu_byp_data_err_f;\n logic ifu_wr_cumulative_err_data;\n logic ifu_wr_cumulative_err;\n logic ifu_wr_data_comb_err_ff;\n logic scnd_miss_index_match ;\n\n\n logic ifc_dma_access_q_ok;\n logic ifc_iccm_access_f ;\n logic ifc_region_acc_fault_f;\n logic ifc_region_acc_fault_final_f;\n logic [1:0] ifc_bus_acc_fault_f;\n logic ic_act_miss_f;\n logic ic_miss_under_miss_f;\n logic ic_ignore_2nd_miss_f;\n logic ic_act_hit_f;\n logic miss_pending;\n logic [31:1] imb_in , imb_ff ;\n logic [31:pt.ICACHE_BEAT_ADDR_HI+1] miss_addr_in , miss_addr ;\n logic miss_wrap_f ;\n logic flush_final_f;\n logic ifc_fetch_req_f;\n logic ifc_fetch_req_f_raw;\n logic fetch_req_f_qual ;\n logic ifc_fetch_req_qual_bf ;\n logic [pt.ICACHE_NUM_WAYS-1:0] replace_way_mb_any;\n logic last_beat;\n logic reset_beat_cnt ;\n logic [pt.ICACHE_BEAT_ADDR_HI:3] ic_req_addr_bits_hi_3 ;\n logic [pt.ICACHE_BEAT_ADDR_HI:3] ic_wr_addr_bits_hi_3 ;\n logic [31:1] ifu_fetch_addr_int_f ;\n logic [31:1] ifu_ic_rw_int_addr ;\n logic crit_wd_byp_ok_ff ;\n logic ic_crit_wd_rdy_new_ff;\n logic [79:0] ic_byp_data_only_pre_new;\n logic [79:0] ic_byp_data_only_new;\n logic ic_byp_hit_f ;\n logic ic_valid ;\n logic ic_valid_ff;\n logic reset_all_tags;\n logic ic_valid_w_debug;\n\n logic [pt.ICACHE_NUM_WAYS-1:0] ifu_tag_wren,ifu_tag_wren_ff;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_tag_wr_en;\n logic [pt.ICACHE_NUM_WAYS-1:0] ifu_tag_wren_w_debug;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way_ff;\n logic ic_debug_rd_en_ff ;\n logic fetch_bf_f_c1_clken ;\n logic fetch_bf_f_c1_clk;\n logic debug_c1_clken;\n logic debug_c1_clk;\n\n logic reset_ic_in ;\n logic reset_ic_ff ;\n logic [pt.ICACHE_BEAT_ADDR_HI:1] vaddr_f ;\n logic [31:1] ifu_status_wr_addr;\n logic sel_mb_addr ;\n logic sel_mb_addr_ff ;\n logic sel_mb_status_addr ;\n logic [63:0] ic_final_data;\n\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status_new_ff ;\n logic way_status_wr_en_ff ;\n logic [pt.ICACHE_TAG_DEPTH-1:0][pt.ICACHE_STATUS_BITS-1:0] way_status_out ;\n logic [1:0] ic_debug_way_enc;\n\n logic [pt.IFU_BUS_TAG-1:0] ifu_bus_rid_ff;\n\n logic fetch_req_icache_f;\n logic fetch_req_iccm_f;\n logic ic_iccm_hit_f;\n logic fetch_uncacheable_ff;\n logic way_status_wr_en;\n logic sel_byp_data;\n logic sel_ic_data;\n logic sel_iccm_data;\n logic ic_rd_parity_final_err;\n logic ic_act_miss_f_delayed;\n logic bus_ifu_wr_data_error;\n logic bus_ifu_wr_data_error_ff;\n logic way_status_wr_en_w_debug;\n logic ic_debug_tag_val_rd_out;\n logic ifu_pmu_ic_miss_in;\n logic ifu_pmu_ic_hit_in;\n logic ifu_pmu_bus_error_in;\n logic ifu_pmu_bus_trxn_in;\n logic ifu_pmu_bus_busy_in;\n logic ic_debug_ict_array_sel_in;\n logic ic_debug_ict_array_sel_ff;\n logic debug_data_clken;\n logic last_data_recieved_in ;\n logic last_data_recieved_ff ;\n\n logic ifu_bus_rvalid ;\n logic ifu_bus_rvalid_ff ;\n logic ifu_bus_rvalid_unq_ff ;\n logic ifu_bus_arready_unq ;\n logic ifu_bus_arready_unq_ff ;\n logic ifu_bus_arvalid ;\n logic ifu_bus_arvalid_ff ;\n logic ifu_bus_arready ;\n logic ifu_bus_arready_ff ;\n logic [63:0] ifu_bus_rdata_ff ;\n logic [1:0] ifu_bus_rresp_ff ;\n logic ifu_bus_rsp_valid ;\n logic ifu_bus_rsp_ready ;\n logic [pt.IFU_BUS_TAG-1:0] ifu_bus_rsp_tag;\n logic [63:0] ifu_bus_rsp_rdata;\n logic [1:0] ifu_bus_rsp_opc;\n\n logic [pt.ICACHE_NUM_BEATS-1:0] write_fill_data;\n logic [pt.ICACHE_NUM_BEATS-1:0] wr_data_c1_clk;\n logic [pt.ICACHE_NUM_BEATS-1:0] ic_miss_buff_data_valid_in;\n logic [pt.ICACHE_NUM_BEATS-1:0] ic_miss_buff_data_valid;\n logic [pt.ICACHE_NUM_BEATS-1:0] ic_miss_buff_data_error_in;\n logic [pt.ICACHE_NUM_BEATS-1:0] ic_miss_buff_data_error;\n logic [pt.ICACHE_BEAT_ADDR_HI:1] byp_fetch_index;\n logic [pt.ICACHE_BEAT_ADDR_HI:2] byp_fetch_index_0;\n logic [pt.ICACHE_BEAT_ADDR_HI:2] byp_fetch_index_1;\n logic [pt.ICACHE_BEAT_ADDR_HI:3] byp_fetch_index_inc;\n logic [pt.ICACHE_BEAT_ADDR_HI:2] byp_fetch_index_inc_0;\n logic [pt.ICACHE_BEAT_ADDR_HI:2] byp_fetch_index_inc_1;\n logic miss_buff_hit_unq_f ;\n logic stream_hit_f ;\n logic stream_miss_f ;\n logic stream_eol_f ;\n logic crit_byp_hit_f ;\n logic [pt.IFU_BUS_TAG-1:0] other_tag ;\n logic [(2*pt.ICACHE_NUM_BEATS)-1:0] [31:0] ic_miss_buff_data;\n logic [63:0] ic_miss_buff_half;\n logic scnd_miss_req, scnd_miss_req_q;\n logic scnd_miss_req_in;\n\n\n logic [pt.ICCM_BITS-1:2] iccm_ecc_corr_index_ff;\n logic [pt.ICCM_BITS-1:2] iccm_ecc_corr_index_in;\n logic [38:0] iccm_ecc_corr_data_ff;\n logic iccm_ecc_write_status ;\n logic iccm_rd_ecc_single_err_ff ;\n logic iccm_error_start; // start the error fsm\n logic perr_state_en;\n logic miss_state_en;\n\n logic busclk;\n logic busclk_force;\n logic busclk_reset;\n logic bus_ifu_bus_clk_en_ff;\n logic bus_ifu_bus_clk_en ;\n\n logic ifc_bus_ic_req_ff_in;\n logic ifu_bus_cmd_valid ;\n logic ifu_bus_cmd_ready ;\n\n logic bus_inc_data_beat_cnt ;\n logic bus_reset_data_beat_cnt ;\n logic bus_hold_data_beat_cnt ;\n\n logic bus_inc_cmd_beat_cnt ;\n logic bus_reset_cmd_beat_cnt_0 ;\n logic bus_reset_cmd_beat_cnt_secondlast ;\n logic bus_hold_cmd_beat_cnt ;\n\n logic [pt.ICACHE_BEAT_BITS-1:0] bus_new_data_beat_count ;\n logic [pt.ICACHE_BEAT_BITS-1:0] bus_data_beat_count ;\n\n logic [pt.ICACHE_BEAT_BITS-1:0] bus_new_cmd_beat_count ;\n logic [pt.ICACHE_BEAT_BITS-1:0] bus_cmd_beat_count ;\n\n\n logic [pt.ICACHE_BEAT_BITS-1:0] bus_new_rd_addr_count;\n logic [pt.ICACHE_BEAT_BITS-1:0] bus_rd_addr_count;\n\n\n logic bus_cmd_sent ;\n logic bus_last_data_beat ;\n\n\n logic [pt.ICACHE_NUM_WAYS-1:0] bus_wren ;\n\n logic [pt.ICACHE_NUM_WAYS-1:0] bus_wren_last ;\n logic [pt.ICACHE_NUM_WAYS-1:0] wren_reset_miss ;\n logic ifc_dma_access_ok_d;\n logic ifc_dma_access_ok_prev;\n\n logic bus_cmd_req_in ;\n logic bus_cmd_req_hold ;\n\n logic second_half_available ;\n logic write_ic_16_bytes ;\n\n logic ifc_region_acc_fault_final_bf;\n logic ifc_region_acc_fault_memory_bf;\n logic ifc_region_acc_fault_memory_f;\n logic ifc_region_acc_okay;\n\n logic iccm_correct_ecc;\n logic dma_sb_err_state, dma_sb_err_state_ff;\n logic two_byte_instr;\n\n typedef enum logic [2:0] {IDLE=3'b000, CRIT_BYP_OK=3'b001, HIT_U_MISS=3'b010, MISS_WAIT=3'b011,CRIT_WRD_RDY=3'b100,SCND_MISS=3'b101,STREAM=3'b110 , STALL_SCND_MISS=3'b111} miss_state_t;\n miss_state_t miss_state, miss_nxtstate;\n\n typedef enum logic [1:0] {ERR_STOP_IDLE=2'b00, ERR_FETCH1=2'b01 , ERR_FETCH2=2'b10 , ERR_STOP_FETCH=2'b11} err_stop_state_t;\n err_stop_state_t err_stop_state, err_stop_nxtstate;\n logic err_stop_state_en ;\n logic err_stop_fetch ;\n\n logic ic_crit_wd_rdy; // Critical fetch is ready to be bypassed.\n\n logic ifu_bp_hit_taken_q_f;\n logic ifu_bus_rvalid_unq;\n logic bus_cmd_beat_en;\n\n\n// ---- Clock gating section -----\n// c1 clock enables\n\n\n assign fetch_bf_f_c1_clken = ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | exu_flush_final | scnd_miss_req;\n assign debug_c1_clken = ic_debug_rd_en | ic_debug_wr_en ;\n // C1 - 1 clock pulse for data\n`ifdef RV_FPGA_OPTIMIZE\n assign fetch_bf_f_c1_clk = 1'b0;\n assign debug_c1_clk = 1'b0;\n`else\n rvclkhdr fetch_bf_f_c1_cgc ( .en(fetch_bf_f_c1_clken), .l1clk(fetch_bf_f_c1_clk), .* );\n rvclkhdr debug_c1_cgc ( .en(debug_c1_clken), .l1clk(debug_c1_clk), .* );\n`endif\n\n\n// ------ end clock gating section ------------------------\n\n logic [1:0] iccm_single_ecc_error;\n logic dma_iccm_req_f ;\n assign iccm_dma_sb_error = (|iccm_single_ecc_error[1:0] ) & dma_iccm_req_f ;\n assign ifu_async_error_start = iccm_rd_ecc_single_err | ic_error_start;\n\n\n typedef enum logic [2:0] {ERR_IDLE=3'b000, IC_WFF=3'b001 , ECC_WFF=3'b010 , ECC_CORR=3'b011, DMA_SB_ERR=3'b100} perr_state_t;\n perr_state_t perr_state, perr_nxtstate;\n\n\n assign ic_dma_active = iccm_correct_ecc | (perr_state == DMA_SB_ERR) | (err_stop_state == ERR_STOP_FETCH) | err_stop_fetch |\n dec_tlu_flush_err_wb; // The last term is to give a error-correction a chance to finish before refetch starts\n\n assign scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready &\n (&bus_new_data_beat_count[pt.ICACHE_BEAT_BITS-1:0]) &\n ~uncacheable_miss_ff & ((miss_state == SCND_MISS) | (miss_nxtstate == SCND_MISS)) & ~exu_flush_final;\n\n assign ifu_bp_hit_taken_q_f = ifu_bp_hit_taken_f & ic_hit_f ;\n\n //////////////////////////////////// Create Miss State Machine ///////////////////////\n // Create Miss State Machine //\n // Create Miss State Machine //\n // Create Miss State Machine //\n //////////////////////////////////// Create Miss State Machine ///////////////////////\n // FIFO state machine\n always_comb begin : MISS_SM\n miss_nxtstate = IDLE;\n miss_state_en = 1'b0;\n case (miss_state)\n IDLE: begin : idle\n miss_nxtstate = (ic_act_miss_f & ~exu_flush_final) ? CRIT_BYP_OK : HIT_U_MISS ;\n miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt ;\n end\n CRIT_BYP_OK: begin : crit_byp_ok\n miss_nxtstate = (dec_tlu_force_halt ) ? IDLE :\n ( ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff) ? IDLE :\n ( ic_byp_hit_f & ~last_data_recieved_ff & uncacheable_miss_ff) ? MISS_WAIT :\n (~ic_byp_hit_f & ~exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & uncacheable_miss_ff) ? CRIT_WRD_RDY :\n ( (bus_ifu_wr_en_ff & last_beat) & ~uncacheable_miss_ff) ? IDLE :\n ( ic_byp_hit_f & ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~ifu_bp_hit_taken_q_f & ~uncacheable_miss_ff) ? STREAM :\n ( bus_ifu_wr_en_ff & ~exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~ifu_bp_hit_taken_q_f & ~uncacheable_miss_ff) ? STREAM :\n (~ic_byp_hit_f & ~exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & ~uncacheable_miss_ff) ? IDLE :\n ( (exu_flush_final | ifu_bp_hit_taken_q_f) & ~(bus_ifu_wr_en_ff & last_beat) ) ? HIT_U_MISS : IDLE;\n miss_state_en = dec_tlu_force_halt | exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff) ;\n end\n CRIT_WRD_RDY: begin : crit_wrd_rdy\n miss_nxtstate = IDLE ;\n miss_state_en = exu_flush_final | flush_final_f | ic_byp_hit_f | dec_tlu_force_halt ;\n end\n STREAM: begin : stream\n miss_nxtstate = ((exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ) & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS : IDLE ;\n miss_state_en = exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;\n end\n MISS_WAIT: begin : miss_wait\n miss_nxtstate = (exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt) ? HIT_U_MISS : IDLE ;\n miss_state_en = exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | dec_tlu_force_halt ;\n end\n HIT_U_MISS: begin : hit_u_miss\n miss_nxtstate = ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? SCND_MISS :\n ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat) & ~dec_tlu_force_halt ? STALL_SCND_MISS : IDLE ;\n miss_state_en = (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | dec_tlu_force_halt;\n end\n SCND_MISS: begin : scnd_miss\n miss_nxtstate = dec_tlu_force_halt ? IDLE :\n exu_flush_final ? ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : CRIT_BYP_OK;\n miss_state_en = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;\n end\n STALL_SCND_MISS: begin : stall_scnd_miss\n miss_nxtstate = dec_tlu_force_halt ? IDLE :\n exu_flush_final ? ((bus_ifu_wr_en_ff & last_beat) ? IDLE : HIT_U_MISS) : IDLE;\n miss_state_en = (bus_ifu_wr_en_ff & last_beat) | exu_flush_final | dec_tlu_force_halt;\n end\n /*pragma coverage off*/\n default: begin : def_case\n miss_nxtstate = IDLE;\n miss_state_en = 1'b0;\n end\n /*pragma coverage on*/\n endcase\n end\n rvdffs #(($bits(miss_state_t))) miss_state_ff (.clk(active_clk), .din(miss_nxtstate), .dout({miss_state}), .en(miss_state_en), .*);\n\n logic sel_hold_imb ;\n\n assign miss_pending = (miss_state != IDLE) ;\n assign crit_wd_byp_ok_ff = (miss_state == CRIT_BYP_OK) | ((miss_state == CRIT_WRD_RDY) & ~flush_final_f);\n assign sel_hold_imb = (miss_pending & ~(bus_ifu_wr_en_ff & last_beat) & ~((miss_state == CRIT_WRD_RDY) & exu_flush_final) &\n ~((miss_state == CRIT_WRD_RDY) & crit_byp_hit_f) ) | ic_act_miss_f |\n (miss_pending & (miss_nxtstate == CRIT_WRD_RDY)) ;\n\n\n logic sel_hold_imb_scnd;\n logic [31:1] imb_scnd_in;\n logic [31:1] imb_scnd_ff;\n logic uncacheable_miss_scnd_in ;\n logic uncacheable_miss_scnd_ff ;\n\n logic [pt.ICACHE_NUM_WAYS-1:0] tagv_mb_scnd_in;\n logic [pt.ICACHE_NUM_WAYS-1:0] tagv_mb_scnd_ff;\n\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status_mb_scnd_in;\n logic [pt.ICACHE_STATUS_BITS-1:0] way_status_mb_scnd_ff;\n\n assign sel_hold_imb_scnd =((miss_state == SCND_MISS) | ic_miss_under_miss_f) & ~flush_final_f ;\n assign way_status_mb_scnd_in[pt.ICACHE_STATUS_BITS-1:0] = (miss_state == SCND_MISS) ? way_status_mb_scnd_ff[pt.ICACHE_STATUS_BITS-1:0] : {way_status[pt.ICACHE_STATUS_BITS-1:0]} ;\n assign tagv_mb_scnd_in[pt.ICACHE_NUM_WAYS-1:0] = (miss_state == SCND_MISS) ? tagv_mb_scnd_ff[pt.ICACHE_NUM_WAYS-1:0] : ({ic_tag_valid[pt.ICACHE_NUM_WAYS-1:0]} & {pt.ICACHE_NUM_WAYS{~reset_all_tags & ~exu_flush_final}});\n assign uncacheable_miss_scnd_in = sel_hold_imb_scnd ? uncacheable_miss_scnd_ff : ifc_fetch_uncacheable_bf ;\n\n\n rvdff_fpga #(1) unc_miss_scnd_ff (.*, .clk(fetch_bf_f_c1_clk), .clken(fetch_bf_f_c1_clken), .rawclk(clk), .din (uncacheable_miss_scnd_in), .dout(uncacheable_miss_scnd_ff));\n rvdffpcie #(31) imb_f_scnd_ff (.*, .en(fetch_bf_f_c1_clken), .din ({imb_scnd_in[31:1]}), .dout({imb_scnd_ff[31:1]}));\n rvdff_fpga #(pt.ICACHE_STATUS_BITS) mb_rep_wayf2_scnd_ff (.*, .clk(fetch_bf_f_c1_clk), .clken(fetch_bf_f_c1_clken), .rawclk(clk), .din ({way_status_mb_scnd_in[pt.ICACHE_STATUS_BITS-1:0]}), .dout({way_status_mb_scnd_ff[pt.ICACHE_STATUS_BITS-1:0]}));\n rvdff_fpga #(pt.ICACHE_NUM_WAYS) mb_tagv_scnd_ff (.*, .clk(fetch_bf_f_c1_clk), .clken(fetch_bf_f_c1_clken), .rawclk(clk), .din ({tagv_mb_scnd_in[pt.ICACHE_NUM_WAYS-1:0]}), .dout({tagv_mb_scnd_ff[pt.ICACHE_NUM_WAYS-1:0]}));\n\n\n\n\n assign ic_req_addr_bits_hi_3[pt.ICACHE_BEAT_ADDR_HI:3] = bus_rd_addr_count[pt.ICACHE_BEAT_BITS-1:0] ;\n assign ic_wr_addr_bits_hi_3[pt.ICACHE_BEAT_ADDR_HI:3] = ifu_bus_rid_ff[pt.ICACHE_BEAT_BITS-1:0] & {pt.ICACHE_BEAT_BITS{bus_ifu_wr_en_ff}};\n // NOTE: Cacheline size is 16 bytes in this example.\n // Tag Index Bank Offset\n // [31:16] [15:5] [4] [3:0]\n\n\n assign fetch_req_icache_f = ifc_fetch_req_f & ~ifc_iccm_access_f & ~ifc_region_acc_fault_final_f;\n assign fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f;\n\n assign ic_iccm_hit_f = fetch_req_iccm_f & (~miss_pending | (miss_state==HIT_U_MISS) | (miss_state==STREAM));\n assign ic_byp_hit_f = (crit_byp_hit_f | stream_hit_f) & fetch_req_icache_f & miss_pending ;\n assign ic_act_hit_f = (|ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0]) & fetch_req_icache_f & ~reset_all_tags & (~miss_pending | (miss_state==HIT_U_MISS)) & ~sel_mb_addr_ff;\n assign ic_act_miss_f = (((~(|ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0]) | reset_all_tags) & fetch_req_icache_f & ~miss_pending) | scnd_miss_req) & ~ifc_region_acc_fault_final_f;\n assign ic_miss_under_miss_f = (~(|ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0]) | reset_all_tags) & fetch_req_icache_f & (miss_state == HIT_U_MISS) &\n (imb_ff[31:pt.ICACHE_TAG_INDEX_LO] != ifu_fetch_addr_int_f[31:pt.ICACHE_TAG_INDEX_LO]) & ~uncacheable_miss_ff & ~sel_mb_addr_ff & ~ifc_region_acc_fault_final_f;\n assign ic_ignore_2nd_miss_f = (~(|ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0]) | reset_all_tags) & fetch_req_icache_f & (miss_state == HIT_U_MISS) &\n ((imb_ff[31:pt.ICACHE_TAG_INDEX_LO] == ifu_fetch_addr_int_f[31:pt.ICACHE_TAG_INDEX_LO]) | uncacheable_miss_ff) ;\n assign ic_hit_f = ic_act_hit_f | ic_byp_hit_f | ic_iccm_hit_f | (ifc_region_acc_fault_final_f & ifc_fetch_req_f);\n\n assign uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : sel_hold_imb ? uncacheable_miss_ff : ifc_fetch_uncacheable_bf ;\n assign imb_in[31:1] = scnd_miss_req ? imb_scnd_ff[31:1] : sel_hold_imb ? imb_ff[31:1] : {ifc_fetch_addr_bf[31:1]} ;\n\n assign imb_scnd_in[31:1] = sel_hold_imb_scnd ? imb_scnd_ff[31:1] : {ifc_fetch_addr_bf[31:1]} ;\n\n assign scnd_miss_index_match = (imb_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO] == imb_scnd_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]) & scnd_miss_req & ~ifu_wr_cumulative_err_data;\n assign way_status_mb_in[pt.ICACHE_STATUS_BITS-1:0] = (scnd_miss_req & ~scnd_miss_index_match) ? way_status_mb_scnd_ff[pt.ICACHE_STATUS_BITS-1:0] :\n (scnd_miss_req & scnd_miss_index_match) ? way_status_rep_new[pt.ICACHE_STATUS_BITS-1:0] :\n miss_pending ? way_status_mb_ff[pt.ICACHE_STATUS_BITS-1:0] :\n {way_status[pt.ICACHE_STATUS_BITS-1:0]} ;\n assign tagv_mb_in[pt.ICACHE_NUM_WAYS-1:0] = scnd_miss_req ? (tagv_mb_scnd_ff[pt.ICACHE_NUM_WAYS-1:0] | ({pt.ICACHE_NUM_WAYS {scnd_miss_index_match}} & replace_way_mb_any[pt.ICACHE_NUM_WAYS-1:0])) :\n miss_pending ? tagv_mb_ff[pt.ICACHE_NUM_WAYS-1:0] : ({ic_tag_valid[pt.ICACHE_NUM_WAYS-1:0]} & {pt.ICACHE_NUM_WAYS{~reset_all_tags & ~exu_flush_final}}) ;\n\n assign reset_ic_in = miss_pending & ~scnd_miss_req_q & (reset_all_tags | reset_ic_ff) ;\n\n\n\n rvdffpcie #(31) ifu_fetch_addr_f_ff (.*, .en(fetch_bf_f_c1_clken), .din ({ifc_fetch_addr_bf[31:1]}), .dout({ifu_fetch_addr_int_f[31:1]}));\n\n assign vaddr_f[pt.ICACHE_BEAT_ADDR_HI:1] = ifu_fetch_addr_int_f[pt.ICACHE_BEAT_ADDR_HI:1] ;\n\n rvdffpcie #(31) imb_f_ff (.*, .en(fetch_bf_f_c1_clken), .din (imb_in[31:1]), .dout(imb_ff[31:1]));\n rvdff_fpga #(1) unc_miss_ff (.*, .clk(fetch_bf_f_c1_clk), .clken(fetch_bf_f_c1_clken), .rawclk(clk), .din ( uncacheable_miss_in), .dout( uncacheable_miss_ff));\n\n\n assign miss_addr_in[31:pt.ICACHE_BEAT_ADDR_HI+1] = (~miss_pending ) ? imb_ff[31:pt.ICACHE_BEAT_ADDR_HI+1] :\n ( scnd_miss_req_q ) ? imb_scnd_ff[31:pt.ICACHE_BEAT_ADDR_HI+1] : miss_addr[31:pt.ICACHE_BEAT_ADDR_HI+1] ;\n\n\n rvdfflie #(.WIDTH(31-pt.ICACHE_BEAT_ADDR_HI),.LEFT(31-pt.ICACHE_BEAT_ADDR_HI-8)) miss_f_ff (.*, .en(bus_ifu_bus_clk_en | ic_act_miss_f | dec_tlu_force_halt), .din ({miss_addr_in[31:pt.ICACHE_BEAT_ADDR_HI+1]}), .dout({miss_addr[31:pt.ICACHE_BEAT_ADDR_HI+1]}));\n\n\n\n\n\n rvdff_fpga #(pt.ICACHE_STATUS_BITS) mb_rep_wayf2_ff (.*, .clk(fetch_bf_f_c1_clk), .clken(fetch_bf_f_c1_clken), .rawclk(clk), .din ({way_status_mb_in[pt.ICACHE_STATUS_BITS-1:0]}), .dout({way_status_mb_ff[pt.ICACHE_STATUS_BITS-1:0]}));\n rvdff_fpga #(pt.ICACHE_NUM_WAYS) mb_tagv_ff (.*, .clk(fetch_bf_f_c1_clk), .clken(fetch_bf_f_c1_clken), .rawclk(clk), .din ({tagv_mb_in[pt.ICACHE_NUM_WAYS-1:0]}), .dout({tagv_mb_ff[pt.ICACHE_NUM_WAYS-1:0]}));\n\n assign ifc_fetch_req_qual_bf = ifc_fetch_req_bf & ~((miss_state == CRIT_WRD_RDY) & flush_final_f) & ~stream_miss_f ;// & ~exu_flush_final ;\n\n assign ifc_fetch_req_f = ifc_fetch_req_f_raw & ~exu_flush_final ;\n\n rvdff_fpga #(1) ifu_iccm_acc_ff (.*, .clk(fetch_bf_f_c1_clk), .clken(fetch_bf_f_c1_clken), .rawclk(clk), .din(ifc_iccm_access_bf), .dout(ifc_iccm_access_f));\n rvdff_fpga #(1) ifu_iccm_reg_acc_ff (.*, .clk(fetch_bf_f_c1_clk), .clken(fetch_bf_f_c1_clken), .rawclk(clk), .din(ifc_region_acc_fault_final_bf), .dout(ifc_region_acc_fault_final_f));\n rvdff_fpga #(1) rgn_acc_ff (.*, .clk(fetch_bf_f_c1_clk), .clken(fetch_bf_f_c1_clken), .rawclk(clk), .din(ifc_region_acc_fault_bf), .dout(ifc_region_acc_fault_f));\n\n\n assign ifu_ic_req_addr_f[31:3] = {miss_addr[31:pt.ICACHE_BEAT_ADDR_HI+1] , ic_req_addr_bits_hi_3[pt.ICACHE_BEAT_ADDR_HI:3] };\n assign ifu_ic_mb_empty = (((miss_state == HIT_U_MISS) | (miss_state == STREAM)) & ~(bus_ifu_wr_en_ff & last_beat)) | ~miss_pending ;\n assign ifu_miss_state_idle = (miss_state == IDLE) ;\n\n\n assign sel_mb_addr = ((miss_pending & write_ic_16_bytes & ~uncacheable_miss_ff) | reset_tag_valid_for_miss) ;\n assign ifu_ic_rw_int_addr[31:1] = ({31{ sel_mb_addr}} & {imb_ff[31:pt.ICACHE_BEAT_ADDR_HI+1] , ic_wr_addr_bits_hi_3[pt.ICACHE_BEAT_ADDR_HI:3] , imb_ff[2:1]}) |\n ({31{~sel_mb_addr}} & ifc_fetch_addr_bf[31:1] ) ;\n\n assign sel_mb_status_addr = ((miss_pending & write_ic_16_bytes & ~uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q) | reset_tag_valid_for_miss) ;\n assign ifu_status_wr_addr[31:1] = ({31{ sel_mb_status_addr}} & {imb_ff[31:pt.ICACHE_BEAT_ADDR_HI+1] , ic_wr_addr_bits_hi_3[pt.ICACHE_BEAT_ADDR_HI:3] , imb_ff[2:1]}) |\n ({31{~sel_mb_status_addr}} & ifu_fetch_addr_int_f[31:1] ) ;\n\n\n assign ic_rw_addr[31:1] = ifu_ic_rw_int_addr[31:1] ;\n\n\nif (pt.ICACHE_ECC == 1) begin: icache_ecc_1\n logic [6:0] ic_wr_ecc;\n logic [6:0] ic_miss_buff_ecc;\n logic [141:0] ic_wr_16bytes_data ;\n logic [70:0] ifu_ic_debug_rd_data_in ;\n\n rvecc_encode_64 ic_ecc_encode_64_bus (\n .din (ifu_bus_rdata_ff[63:0]),\n .ecc_out(ic_wr_ecc[6:0]));\n rvecc_encode_64 ic_ecc_encode_64_buff (\n .din (ic_miss_buff_half[63:0]),\n .ecc_out(ic_miss_buff_ecc[6:0]));\n\n for (genvar i=0; i < pt.ICACHE_BANKS_WAY ; i++) begin : ic_wr_data_loop\n assign ic_wr_data[i][70:0] = ic_wr_16bytes_data[((71*i)+70): (71*i)];\n end\n\n\n assign ic_debug_wr_data[70:0] = {dec_tlu_ic_diag_pkt.icache_wrdata[70:0]} ;\n assign ic_error_start = ((|ic_eccerr[pt.ICACHE_BANKS_WAY-1:0]) & ic_act_hit_f) | ic_rd_parity_final_err;\n\n\n\n assign ifu_ic_debug_rd_data_in[70:0] = ic_debug_ict_array_sel_ff ? {2'b0,ictag_debug_rd_data[25:21],32'b0,ictag_debug_rd_data[20:0],{7-pt.ICACHE_STATUS_BITS{1'b0}}, way_status[pt.ICACHE_STATUS_BITS-1:0],3'b0,ic_debug_tag_val_rd_out} :\n ic_debug_rd_data[70:0];\n\n rvdffe #(71) ifu_debug_data_ff (.*,\n .en (debug_data_clken),\n .din ({\n ifu_ic_debug_rd_data_in[70:0]\n }),\n .dout({\n ifu_ic_debug_rd_data[70:0]\n })\n );\n\n assign ic_wr_16bytes_data[141:0] = ifu_bus_rid_ff[0] ? {ic_wr_ecc[6:0] , ifu_bus_rdata_ff[63:0] , ic_miss_buff_ecc[6:0] , ic_miss_buff_half[63:0] } :\n {ic_miss_buff_ecc[6:0] , ic_miss_buff_half[63:0] , ic_wr_ecc[6:0] , ifu_bus_rdata_ff[63:0] } ;\n\n\nend\nelse begin : icache_parity_1\n logic [3:0] ic_wr_parity;\n logic [3:0] ic_miss_buff_parity;\n logic [135:0] ic_wr_16bytes_data ;\n logic [70:0] ifu_ic_debug_rd_data_in ;\n for (genvar i=0 ; i < 4 ; i++) begin : DATA_PGEN\n rveven_paritygen #(16) par_bus (.data_in (ifu_bus_rdata_ff[((16*i)+15):(16*i)]),\n .parity_out(ic_wr_parity[i]));\n rveven_paritygen #(16) par_buff (.data_in (ic_miss_buff_half[((16*i)+15):(16*i)]),\n .parity_out(ic_miss_buff_parity[i]));\n end\n\n\n for (genvar i=0; i < pt.ICACHE_BANKS_WAY ; i++) begin : ic_wr_data_loop\n assign ic_wr_data[i][70:0] = {3'b0, ic_wr_16bytes_data[((68*i)+67): (68*i)]};\n end\n\n\n\n\n\n assign ic_debug_wr_data[70:0] = {dec_tlu_ic_diag_pkt.icache_wrdata[70:0]} ;\n assign ic_error_start = ((|ic_parerr[pt.ICACHE_BANKS_WAY-1:0]) & ic_act_hit_f) | ic_rd_parity_final_err;\n\n assign ifu_ic_debug_rd_data_in[70:0] = ic_debug_ict_array_sel_ff ? {6'b0,ictag_debug_rd_data[21],32'b0,ictag_debug_rd_data[20:0],{7-pt.ICACHE_STATUS_BITS{1'b0}},way_status[pt.ICACHE_STATUS_BITS-1:0],3'b0,ic_debug_tag_val_rd_out} :\n ic_debug_rd_data[70:0] ;\n\n rvdffe #(71) ifu_debug_data_ff (.*,\n .en (debug_data_clken),\n .din ({\n ifu_ic_debug_rd_data_in[70:0]\n }),\n .dout({\n ifu_ic_debug_rd_data[70:0]\n })\n );\n\n assign ic_wr_16bytes_data[135:0] = ifu_bus_rid_ff[0] ? {ic_wr_parity[3:0] , ifu_bus_rdata_ff[63:0] , ic_miss_buff_parity[3:0] , ic_miss_buff_half[63:0] } :\n {ic_miss_buff_parity[3:0] , ic_miss_buff_half[63:0] , ic_wr_parity[3:0] , ifu_bus_rdata_ff[63:0] } ;\n\nend\n\n\n assign ifu_wr_data_comb_err = bus_ifu_wr_data_error_ff ;\n assign ifu_wr_cumulative_err = (ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff) & ~reset_beat_cnt;\n assign ifu_wr_cumulative_err_data = ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff ;\n\n\n assign sel_byp_data = (ic_crit_wd_rdy | (miss_state == STREAM) | (miss_state == CRIT_BYP_OK));\n assign sel_ic_data = ~(ic_crit_wd_rdy | (miss_state == STREAM) | (miss_state == CRIT_BYP_OK) | (miss_state == MISS_WAIT)) & ~fetch_req_iccm_f & ~ifc_region_acc_fault_final_f;\n\n if (pt.ICCM_ICACHE==1) begin: iccm_icache\n assign sel_iccm_data = fetch_req_iccm_f ;\n\n assign ic_final_data[63:0] = ({64{sel_byp_data | sel_iccm_data | sel_ic_data}} & {ic_rd_data[63:0]} ) ;\n\n assign ic_premux_data[63:0] = ({64{sel_byp_data }} & {ic_byp_data_only_new[63:0]} ) |\n ({64{sel_iccm_data}} & {iccm_rd_data[63:0]});\n\n assign ic_sel_premux_data = sel_iccm_data | sel_byp_data ;\n end\n\nif (pt.ICCM_ONLY == 1 ) begin: iccm_only\n assign sel_iccm_data = fetch_req_iccm_f ;\n assign ic_final_data[63:0] = ({64{sel_byp_data }} & {ic_byp_data_only_new[63:0]} ) |\n ({64{sel_iccm_data}} & {iccm_rd_data[63:0]});\n assign ic_premux_data = '0 ;\n assign ic_sel_premux_data = '0 ;\nend\n\nif (pt.ICACHE_ONLY == 1 ) begin: icache_only\n assign ic_final_data[63:0] = ({64{sel_byp_data | sel_ic_data}} & {ic_rd_data[63:0]} ) ;\n assign ic_premux_data[63:0] = ({64{sel_byp_data }} & {ic_byp_data_only_new[63:0]} ) ;\n assign ic_sel_premux_data = sel_byp_data ;\nend\n\n\nif (pt.NO_ICCM_NO_ICACHE == 1 ) begin: no_iccm_no_icache\n assign ic_final_data[63:0] = ({64{sel_byp_data }} & {ic_byp_data_only_new[63:0]} ) ;\n assign ic_premux_data = 0 ;\n assign ic_sel_premux_data = '0 ;\nend\n\n\n assign ifc_bus_acc_fault_f[1:0] = {2{ic_byp_hit_f}} & ifu_byp_data_err_f[1:0] ;\n assign ic_data_f[31:0] = ic_final_data[31:0];\n\n\n\nassign fetch_req_f_qual = ic_hit_f & ~exu_flush_final;\nassign ic_access_fault_f[1:0] = ({2{ifc_region_acc_fault_final_f}} | ifc_bus_acc_fault_f[1:0]) & {2{~exu_flush_final}};\nassign ic_access_fault_type_f[1:0] = |iccm_rd_ecc_double_err ? 2'b01 :\n ifc_region_acc_fault_f ? 2'b10 :\n ifc_region_acc_fault_memory_f ? 2'b11 : 2'b00 ;\n\n // right justified\n\nassign ic_fetch_val_f[1] = fetch_req_f_qual & ifu_bp_inst_mask_f & ~(vaddr_f[pt.ICACHE_BEAT_ADDR_HI:1] == {pt.ICACHE_BEAT_ADDR_HI{1'b1}}) & (err_stop_state != ERR_FETCH2);\nassign ic_fetch_val_f[0] = fetch_req_f_qual ;\nassign two_byte_instr = (ic_data_f[1:0] != 2'b11 ) ;\n\n/////////////////////////////////////////////////////////////////////////////////////\n// Create full buffer... //\n/////////////////////////////////////////////////////////////////////////////////////\n logic [63:0] ic_miss_buff_data_in;\n assign ic_miss_buff_data_in[63:0] = ifu_bus_rsp_rdata[63:0];\n\n for (genvar i=0; i=1 & clk_count<=3) rst_l <= 1'b0;\n else rst_l <= 1'b1;\n\n if (clk_count > 3) begin\n\n compressed_din[15:0] <= compressed[clk_count-3]; // c.mv\n expected_val[31:0] <= expected[clk_count-3];\n\n end\n\n if (clk_count == 65000) begin\n $dumpoff;\n $finish;\n end\n end // always @ (posedge clk)\n\n always @(negedge clk) begin\n if (clk_count > 3 & error) begin\n $display(\"clock: %d compressed %h error actual %h expected %h\",clk_count,compressed_din,actual,expected_val);\n end\n end\n\n\n el2_ifu_compress_ctl align (.*,.din(compressed_din[15:0]),.dout(actual[31:0]));\n\n assign error = actual[31:0] != expected_val[31:0];\n\n\n\nendmodule // el2_ifu_tb_memread\n\n\n" }, { "path": "design/include/el2_dec_csr_equ_m.svh", "content": "logic csr_misa;\nlogic csr_mvendorid;\nlogic csr_marchid;\nlogic csr_mimpid;\nlogic csr_mhartid;\nlogic csr_mstatus;\nlogic csr_mtvec;\nlogic csr_mip;\nlogic csr_mie;\nlogic csr_mcyclel;\nlogic csr_mcycleh;\nlogic csr_minstretl;\nlogic csr_minstreth;\nlogic csr_mscratch;\nlogic csr_mepc;\nlogic csr_mcause;\nlogic csr_mscause;\nlogic csr_mtval;\nlogic csr_mrac;\nlogic csr_dmst;\nlogic csr_mdseac;\nlogic csr_meihap;\nlogic csr_meivt;\nlogic csr_meipt;\nlogic csr_meicurpl;\nlogic csr_meicidpl;\nlogic csr_dcsr;\nlogic csr_mcgc;\nlogic csr_mfdc;\nlogic csr_dpc;\nlogic csr_mtsel;\nlogic csr_mtdata1;\nlogic csr_mtdata2;\nlogic csr_mhpmc3;\nlogic csr_mhpmc4;\nlogic csr_mhpmc5;\nlogic csr_mhpmc6;\nlogic csr_mhpmc3h;\nlogic csr_mhpmc4h;\nlogic csr_mhpmc5h;\nlogic csr_mhpmc6h;\nlogic csr_mhpme3;\nlogic csr_mhpme4;\nlogic csr_mhpme5;\nlogic csr_mhpme6;\nlogic csr_mcountinhibit;\nlogic csr_mitctl0;\nlogic csr_mitctl1;\nlogic csr_mitb0;\nlogic csr_mitb1;\nlogic csr_mitcnt0;\nlogic csr_mitcnt1;\n/* exclude signals that are tied to constant value in this file */\n/*pragma coverage off*/\nlogic csr_perfva;\nlogic csr_perfvb;\nlogic csr_perfvc;\nlogic csr_perfvd;\nlogic csr_perfve;\nlogic csr_perfvf;\nlogic csr_perfvg;\nlogic csr_perfvh;\nlogic csr_perfvi;\n/*pragma coverage on*/\nlogic csr_mpmc;\nlogic csr_mcpc;\nlogic csr_meicpct;\nlogic csr_mdeau;\nlogic csr_micect;\nlogic csr_miccmect;\nlogic csr_mdccmect;\nlogic csr_mfdht;\nlogic csr_mfdhs;\nlogic csr_dicawics;\nlogic csr_dicad0h;\nlogic csr_dicad0;\nlogic csr_dicad1;\nlogic csr_dicago;\nlogic csr_pmpcfg;\nlogic csr_pmpaddr0;\nlogic csr_pmpaddr16;\nlogic csr_pmpaddr32;\nlogic csr_pmpaddr48;\nlogic valid_only;\nlogic presync;\nlogic postsync;\nassign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);\n\nassign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_mhartid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[2]);\n\nassign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);\n\nassign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]);\n\nassign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mcyclel = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]);\n\nassign csr_mcycleh = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);\n\nassign csr_minstretl = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_minstreth = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[2]);\n\nassign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]);\n\nassign csr_dmst = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);\n\nassign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]);\n\nassign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[3]);\n\nassign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[2]);\n\nassign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);\n\nassign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mtdata1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);\n\nassign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]);\n\nassign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc6 = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mitctl1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_perfva = 1'b0;\n\nassign csr_perfvb = 1'b0;\n\nassign csr_perfvc = 1'b0;\n\nassign csr_perfvd = 1'b0;\n\nassign csr_perfve = 1'b0;\n\nassign csr_perfvf = 1'b0;\n\nassign csr_perfvg = 1'b0;\n\nassign csr_perfvh = 1'b0;\n\nassign csr_perfvi = 1'b0;\n\nassign csr_mpmc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);\n\nassign csr_mcpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);\n\nassign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);\n\nassign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_miccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);\n\nassign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);\n\nassign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);\n\nassign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);\n\nassign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);\n\nassign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);\n\nassign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[4]);\n\nassign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]);\n\nassign valid_only = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (\n !dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[4]) | (\n !dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (\n !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[3]);\n\nassign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | (\n dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (\n dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nlogic legal;\nassign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]\n &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (\n !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]\n &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (\n dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (\n dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (\n !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (\n dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]);\n\n" }, { "path": "design/include/el2_dec_csr_equ_mu.svh", "content": "logic csr_misa;\nlogic csr_mvendorid;\nlogic csr_marchid;\nlogic csr_mimpid;\nlogic csr_mhartid;\nlogic csr_mstatus;\nlogic csr_mtvec;\nlogic csr_mip;\nlogic csr_mie;\nlogic csr_mcyclel;\nlogic csr_mcycleh;\nlogic csr_minstretl;\nlogic csr_minstreth;\nlogic csr_mscratch;\nlogic csr_mepc;\nlogic csr_mcause;\nlogic csr_mscause;\nlogic csr_mtval;\nlogic csr_mrac;\nlogic csr_dmst;\nlogic csr_mdseac;\nlogic csr_meihap;\nlogic csr_meivt;\nlogic csr_meipt;\nlogic csr_meicurpl;\nlogic csr_meicidpl;\nlogic csr_dcsr;\nlogic csr_mcgc;\nlogic csr_mfdc;\nlogic csr_dpc;\nlogic csr_mtsel;\nlogic csr_mtdata1;\nlogic csr_mtdata2;\nlogic csr_mhpmc3;\nlogic csr_mhpmc4;\nlogic csr_mhpmc5;\nlogic csr_mhpmc6;\nlogic csr_mhpmc3h;\nlogic csr_mhpmc4h;\nlogic csr_mhpmc5h;\nlogic csr_mhpmc6h;\nlogic csr_mhpme3;\nlogic csr_mhpme4;\nlogic csr_mhpme5;\nlogic csr_mhpme6;\nlogic csr_mcounteren;\nlogic csr_mcountinhibit;\nlogic csr_mitctl0;\nlogic csr_mitctl1;\nlogic csr_mitb0;\nlogic csr_mitb1;\nlogic csr_mitcnt0;\nlogic csr_mitcnt1;\n/* exclude signals that are tied to constant value in this file */\n/*pragma coverage off*/\nlogic csr_perfva;\nlogic csr_perfvb;\nlogic csr_perfvc;\nlogic csr_perfvd;\nlogic csr_perfve;\nlogic csr_perfvf;\nlogic csr_perfvg;\nlogic csr_perfvh;\nlogic csr_perfvi;\n/*pragma coverage on*/\nlogic csr_mpmc;\nlogic csr_mcpc;\nlogic csr_meicpct;\nlogic csr_mdeau;\nlogic csr_micect;\nlogic csr_miccmect;\nlogic csr_mdccmect;\nlogic csr_mfdht;\nlogic csr_mfdhs;\nlogic csr_dicawics;\nlogic csr_dicad0h;\nlogic csr_dicad0;\nlogic csr_dicad1;\nlogic csr_dicago;\nlogic csr_menvcfg;\nlogic csr_menvcfgh;\nlogic csr_pmpcfg;\nlogic csr_pmpaddr0;\nlogic csr_pmpaddr16;\nlogic csr_pmpaddr32;\nlogic csr_pmpaddr48;\nlogic csr_cyclel;\nlogic csr_cycleh;\nlogic csr_instretl;\nlogic csr_instreth;\nlogic csr_hpmc3;\nlogic csr_hpmc4;\nlogic csr_hpmc5;\nlogic csr_hpmc6;\nlogic csr_hpmc3h;\nlogic csr_hpmc4h;\nlogic csr_hpmc5h;\nlogic csr_hpmc6h;\nlogic csr_mseccfgl;\nlogic csr_mseccfgh;\nlogic valid_only;\nlogic presync;\nlogic postsync;\nassign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);\n\nassign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_mhartid = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]);\n\nassign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);\n\nassign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mcyclel = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);\n\nassign csr_mcycleh = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);\n\nassign csr_minstretl = (dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_minstreth = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mscause = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[2]);\n\nassign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]);\n\nassign csr_dmst = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);\n\nassign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);\n\nassign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[3]);\n\nassign csr_meivt = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[2]);\n\nassign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);\n\nassign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mtdata1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]);\n\nassign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]);\n\nassign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc6 = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc3h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc4h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc5h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_mhpmc6h = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mhpme4 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mhpme5 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mhpme6 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mcounteren = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);\n\nassign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mitctl0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mitctl1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nassign csr_mitb0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_mitb1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mitcnt0 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[0]);\n\nassign csr_mitcnt1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_perfva = 1'b0;\n\nassign csr_perfvb = 1'b0;\n\nassign csr_perfvc = 1'b0;\n\nassign csr_perfvd = 1'b0;\n\nassign csr_perfve = 1'b0;\n\nassign csr_perfvf = 1'b0;\n\nassign csr_perfvg = 1'b0;\n\nassign csr_perfvh = 1'b0;\n\nassign csr_perfvi = 1'b0;\n\nassign csr_mpmc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]);\n\nassign csr_mcpc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);\n\nassign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mdeau = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3]);\n\nassign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_miccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]);\n\nassign csr_mdccmect = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mfdht = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_mfdhs = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]);\n\nassign csr_dicawics = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);\n\nassign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_menvcfg = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]);\n\nassign csr_menvcfgh = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);\n\nassign csr_pmpcfg = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);\n\nassign csr_pmpaddr0 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]);\n\nassign csr_pmpaddr16 = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]);\n\nassign csr_pmpaddr32 = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[4]);\n\nassign csr_pmpaddr48 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]);\n\nassign csr_cyclel = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);\n\nassign csr_cycleh = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);\n\nassign csr_instretl = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_instreth = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_hpmc3 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_hpmc4 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_hpmc5 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_hpmc6 = (!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);\n\nassign csr_hpmc3h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_hpmc4h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]);\n\nassign csr_hpmc5h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]);\n\nassign csr_hpmc6h = (!dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);\n\nassign csr_mseccfgl = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]);\n\nassign csr_mseccfgh = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[4]);\n\nassign valid_only = (!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]);\n\nassign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (\n dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (\n dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);\n\nassign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (\n dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (\n !dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]);\n\nlogic legal;\nassign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]\n &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]) | (\n dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]\n &!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]\n &!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[9]&!dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (\n !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (\n !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (\n dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]\n &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]\n &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (\n !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]\n &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]\n &dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]\n &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]\n &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (\n !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (\n dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (!dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (\n dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]\n &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]\n &dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]\n &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]\n &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (!dec_csr_rdaddr_d[11]\n &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]\n &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]);\n\n" }, { "path": "design/include/el2_def.sv", "content": "// performance monitor stuff\n//`ifndef EL2_DEF_SV\n//`define EL2_DEF_SV\npackage el2_pkg;\n\n`include \"el2_pdef.vh\"\n\ntypedef struct packed {\n logic trace_rv_i_valid_ip;\n logic [31:0] trace_rv_i_insn_ip;\n logic [31:0] trace_rv_i_address_ip;\n logic trace_rv_i_exception_ip;\n logic [4:0] trace_rv_i_ecause_ip;\n logic trace_rv_i_interrupt_ip;\n logic [31:0] trace_rv_i_tval_ip;\n } el2_trace_pkt_t;\n\n\ntypedef enum logic [3:0] {\n NULL_OP = 4'b0000,\n MUL = 4'b0001,\n LOAD = 4'b0010,\n STORE = 4'b0011,\n ALU = 4'b0100,\n CSRREAD = 4'b0101,\n CSRWRITE = 4'b0110,\n CSRRW = 4'b0111,\n EBREAK = 4'b1000,\n ECALL = 4'b1001,\n FENCE = 4'b1010,\n FENCEI = 4'b1011,\n MRET = 4'b1100,\n CONDBR = 4'b1101,\n JAL = 4'b1110,\n BITMANIPU = 4'b1111\n } el2_inst_pkt_t;\n\ntypedef struct packed {\n logic valid;\n logic wb;\n logic [2:0] tag;\n logic [4:0] rd;\n } el2_load_cam_pkt_t;\n\ntypedef struct packed {\n logic pc0_call;\n logic pc0_ret;\n logic pc0_pc4;\n } el2_rets_pkt_t;\ntypedef struct packed {\n logic valid;\n logic [11:0] toffset;\n logic [1:0] hist;\n logic br_error;\n logic br_start_error;\n logic bank;\n logic [31:1] prett; // predicted ret target\n logic way;\n logic ret;\n } el2_br_pkt_t;\n\ntypedef struct packed {\n logic valid;\n logic [1:0] hist;\n logic br_error;\n logic br_start_error;\n logic way;\n logic middle;\n } el2_br_tlu_pkt_t;\n\ntypedef struct packed {\n logic misp;\n logic ataken;\n logic boffset;\n logic pc4;\n logic [1:0] hist;\n logic [11:0] toffset;\n logic valid;\n logic br_error;\n logic br_start_error;\n logic pcall;\n logic pja;\n logic way;\n logic pret;\n // for power use the pret bit to clock the prett field\n logic [31:1] prett;\n } el2_predict_pkt_t;\n\ntypedef struct packed {\n // unlikely to change\n logic icaf;\n logic icaf_second;\n logic [1:0] icaf_type;\n logic fence_i;\n logic [3:0] i0trigger;\n logic pmu_i0_br_unpred; // pmu\n logic pmu_divide;\n // likely to change\n logic legal;\n logic pmu_lsu_misaligned;\n el2_inst_pkt_t pmu_i0_itype; // pmu - instruction type\n } el2_trap_pkt_t;\n\ntypedef struct packed {\n // unlikely to change\n logic i0div;\n logic csrwen;\n logic csrwonly;\n logic [11:0] csraddr;\n // likely to change\n logic [4:0] i0rd;\n logic i0load;\n logic i0store;\n logic i0v;\n logic i0valid;\n } el2_dest_pkt_t;\n\ntypedef struct packed {\n logic mul;\n logic load;\n logic alu;\n } el2_class_pkt_t;\n\ntypedef struct packed {\n logic [4:0] rs1;\n logic [4:0] rs2;\n logic [4:0] rd;\n } el2_reg_pkt_t;\n\n\ntypedef struct packed {\n logic clz;\n logic ctz;\n logic cpop;\n logic sext_b;\n logic sext_h;\n logic min;\n logic max;\n logic pack;\n logic packu;\n logic packh;\n logic rol;\n logic ror;\n logic grev;\n logic gorc;\n logic zbb;\n logic bset;\n logic bclr;\n logic binv;\n logic bext;\n logic sh1add;\n logic sh2add;\n logic sh3add;\n logic zba;\n logic land;\n logic lor;\n logic lxor;\n logic sll;\n logic srl;\n logic sra;\n logic beq;\n logic bne;\n logic blt;\n logic bge;\n logic add;\n logic sub;\n logic slt;\n logic unsign;\n logic jal;\n logic predict_t;\n logic predict_nt;\n logic csr_write;\n logic csr_imm;\n } el2_alu_pkt_t;\n\ntypedef struct packed {\n logic fast_int;\n/* verilator lint_off SYMRSVDWORD */\n logic stack;\n/* verilator lint_on SYMRSVDWORD */\n logic by;\n logic half;\n logic word;\n logic dword; // for dma\n logic load;\n logic store;\n logic unsign;\n logic dma; // dma pkt\n logic store_data_bypass_d;\n logic load_ldst_bypass_d;\n logic store_data_bypass_m;\n logic valid;\n } el2_lsu_pkt_t;\n\ntypedef struct packed {\n logic inst_type; //0: Load, 1: Store\n //logic dma_valid;\n logic exc_type; //0: MisAligned, 1: Access Fault\n logic [3:0] mscause;\n logic [31:0] addr;\n logic single_ecc_error;\n logic exc_valid;\n } el2_lsu_error_pkt_t;\n\ntypedef struct packed {\n logic clz;\n logic ctz;\n logic cpop;\n logic sext_b;\n logic sext_h;\n logic min;\n logic max;\n logic pack;\n logic packu;\n logic packh;\n logic rol;\n logic ror;\n logic grev;\n logic gorc;\n logic zbb;\n logic bset;\n logic bclr;\n logic binv;\n logic bext;\n logic zbs;\n logic bcompress;\n logic bdecompress;\n logic zbe;\n logic clmul;\n logic clmulh;\n logic clmulr;\n logic zbc;\n logic shfl;\n logic unshfl;\n logic xperm_n;\n logic xperm_b;\n logic xperm_h;\n logic zbp;\n logic crc32_b;\n logic crc32_h;\n logic crc32_w;\n logic crc32c_b;\n logic crc32c_h;\n logic crc32c_w;\n logic zbr;\n logic bfp;\n logic zbf;\n logic sh1add;\n logic sh2add;\n logic sh3add;\n logic zba;\n logic alu;\n logic rs1;\n logic rs2;\n logic imm12;\n logic rd;\n logic shimm5;\n logic imm20;\n logic pc;\n logic load;\n logic store;\n logic lsu;\n logic add;\n logic sub;\n logic land;\n logic lor;\n logic lxor;\n logic sll;\n logic sra;\n logic srl;\n logic slt;\n logic unsign;\n logic condbr;\n logic beq;\n logic bne;\n logic bge;\n logic blt;\n logic jal;\n logic by;\n logic half;\n logic word;\n logic csr_read;\n logic csr_clr;\n logic csr_set;\n logic csr_write;\n logic csr_imm;\n logic presync;\n logic postsync;\n logic ebreak;\n logic ecall;\n logic mret;\n logic mul;\n logic rs1_sign;\n logic rs2_sign;\n logic low;\n logic div;\n logic rem;\n logic fence;\n logic fence_i;\n logic pm_alu;\n logic legal;\n } el2_dec_pkt_t;\n\n\ntypedef struct packed {\n logic valid;\n logic rs1_sign;\n logic rs2_sign;\n logic low;\n logic bcompress;\n logic bdecompress;\n logic clmul;\n logic clmulh;\n logic clmulr;\n logic grev;\n logic gorc;\n logic shfl;\n logic unshfl;\n logic crc32_b;\n logic crc32_h;\n logic crc32_w;\n logic crc32c_b;\n logic crc32c_h;\n logic crc32c_w;\n logic bfp;\n logic xperm_n;\n logic xperm_b;\n logic xperm_h;\n } el2_mul_pkt_t;\n\ntypedef struct packed {\n logic valid;\n logic unsign;\n logic rem;\n } el2_div_pkt_t;\n\ntypedef struct packed {\n logic TEST1;\n logic RME;\n logic [3:0] RM;\n\n logic LS;\n logic DS;\n logic SD;\n logic TEST_RNM;\n logic BC1;\n logic BC2;\n } el2_ccm_ext_in_pkt_t;\n\ntypedef struct packed {\n logic TEST1;\n logic RME;\n logic [3:0] RM;\n logic LS;\n logic DS;\n logic SD;\n logic TEST_RNM;\n logic BC1;\n logic BC2;\n } el2_dccm_ext_in_pkt_t;\n\n\ntypedef struct packed {\n logic TEST1;\n logic RME;\n logic [3:0] RM;\n logic LS;\n logic DS;\n logic SD;\n logic TEST_RNM;\n logic BC1;\n logic BC2;\n } el2_ic_data_ext_in_pkt_t;\n\n\ntypedef struct packed {\n logic TEST1;\n logic RME;\n logic [3:0] RM;\n logic LS;\n logic DS;\n logic SD;\n logic TEST_RNM;\n logic BC1;\n logic BC2;\n } el2_ic_tag_ext_in_pkt_t;\n\n\n\ntypedef struct packed {\n logic select;\n logic match;\n logic store;\n logic load;\n logic execute;\n logic m;\n logic [31:0] tdata2;\n } el2_trigger_pkt_t;\n\n\ntypedef struct packed {\n logic [70:0] icache_wrdata; // {dicad1[1:0], dicad0h[31:0], dicad0[31:0]}\n logic [16:0] icache_dicawics; // Arraysel:24, Waysel:21:20, Index:16:3\n logic icache_rd_valid;\n logic icache_wr_valid;\n } el2_cache_debug_pkt_t;\n\n\n typedef enum logic [2:0] {\n NONE = 3'b000,\n READ = 3'b001,\n WRITE = 3'b010,\n EXEC = 3'b100\n } el2_pmp_type_pkt_t;\n\n\n typedef enum logic [1:0] {\n OFF = 2'b00,\n TOR = 2'b01,\n NA4 = 2'b10,\n NAPOT = 2'b11\n } el2_pmp_mode_pkt_t;\n\n\n typedef struct packed {\n logic lock;\n logic [1:0] reserved;\n el2_pmp_mode_pkt_t mode;\n logic execute;\n logic write;\n logic read;\n } el2_pmp_cfg_pkt_t;\n\n typedef struct packed {\n logic RLB;\n logic MMWP;\n logic MML;\n } el2_mseccfg_pkt_t;\n\n//`endif\n\nendpackage // el2_pkg\n" }, { "path": "design/lib/ahb_to_axi4.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n// $Id$\n//\n// Owner:\n// Function: AHB to AXI4 Bridge\n// Comments:\n//\n//********************************************************************************\nmodule ahb_to_axi4\nimport el2_pkg::*;\n#(\n TAG = 1,\n CHECK_RANGES = 1,\n `include \"el2_param.vh\"\n)\n(\n input clk,\n input rst_l,\n /* pragma coverage off */\n input scan_mode,\n /* pragma coverage on */\n input bus_clk_en,\n input clk_override,\n\n // AXI signals\n // AXI Write Channels\n output logic axi_awvalid,\n input logic axi_awready,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [TAG-1:0] axi_awid,\n /*pragma coverage on*/\n output logic [31:0] axi_awaddr,\n output logic [2:0] axi_awsize,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [2:0] axi_awprot,\n output logic [7:0] axi_awlen,\n output logic [1:0] axi_awburst,\n /*pragma coverage on*/\n\n output logic axi_wvalid,\n input logic axi_wready,\n output logic [63:0] axi_wdata,\n output logic [7:0] axi_wstrb,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic axi_wlast,\n /*pragma coverage on*/\n\n input logic axi_bvalid,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic axi_bready,\n /*pragma coverage on*/\n input logic [1:0] axi_bresp,\n /* Exclude unused AXI rid since it has no equivalent in AHB */\n /*pragma coverage off*/\n input logic [TAG-1:0] axi_bid,\n /*pragma coverage on*/\n\n // AXI Read Channels\n output logic axi_arvalid,\n input logic axi_arready,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [TAG-1:0] axi_arid,\n /*pragma coverage on*/\n output logic [31:0] axi_araddr,\n output logic [2:0] axi_arsize,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [2:0] axi_arprot,\n output logic [7:0] axi_arlen,\n output logic [1:0] axi_arburst,\n /*pragma coverage on*/\n\n input logic axi_rvalid,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic axi_rready,\n /*pragma coverage on*/\n /* Exclude unused AXI rid since it has no equivalent in AHB */\n /*pragma coverage off*/\n input logic [TAG-1:0] axi_rid,\n /*pragma coverage on*/\n input logic [63:0] axi_rdata,\n input logic [1:0] axi_rresp,\n\n // AHB-Lite signals\n input logic [31:0] ahb_haddr, // ahb bus address\n // Exclude input signals that are unused in this file (their AXI equivalents\n // are tied to constants)\n /*pragma coverage off*/\n input logic [2:0] ahb_hburst, // tied to 0\n input logic ahb_hmastlock, // tied to 0\n input logic [3:0] ahb_hprot, // tied to 4'b0011\n /*pragma coverage on*/\n input logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3)\n input logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now)\n input logic ahb_hwrite, // ahb bus write\n input logic [63:0] ahb_hwdata, // ahb bus write data\n input logic ahb_hsel, // this slave was selected\n input logic ahb_hreadyin, // previous hready was accepted or not\n\n output logic [63:0] ahb_hrdata, // ahb bus read data\n output logic ahb_hreadyout, // slave ready to accept transaction\n output logic ahb_hresp // slave response (high indicates erro)\n\n);\n\n logic [7:0] master_wstrb;\n\n typedef enum logic [1:0] { IDLE = 2'b00, // Nothing in the buffer. No commands yet recieved\n WR = 2'b01, // Write Command recieved\n RD = 2'b10, // Read Command recieved\n PEND = 2'b11 // Waiting on Read Data from core\n } state_t;\n state_t buf_state, buf_nxtstate;\n logic buf_state_en;\n\n // Buffer signals (one entry buffer)\n logic buf_read_error_in, buf_read_error;\n logic [63:0] buf_rdata;\n\n logic ahb_hready;\n logic ahb_hready_q;\n logic [1:0] ahb_htrans_in, ahb_htrans_q;\n logic [2:0] ahb_hsize_q;\n logic ahb_hwrite_q;\n logic [31:0] ahb_haddr_q;\n logic ahb_hresp_q;\n\n // signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus\n logic buf_rdata_en;\n\n logic ahb_addr_clk_en, buf_rdata_clk_en;\n logic bus_clk, ahb_addr_clk, buf_rdata_clk;\n // Command buffer is the holding station where we convert to AXI and send to core\n logic cmdbuf_wr_en, cmdbuf_rst;\n logic cmdbuf_full;\n logic cmdbuf_vld, cmdbuf_write;\n logic [1:0] cmdbuf_size;\n logic [7:0] cmdbuf_wstrb;\n logic [31:0] cmdbuf_addr;\n logic [63:0] cmdbuf_wdata;\n\n// FSM to control the bus states and when to block the hready and load the command buffer\n always_comb begin\n buf_nxtstate = IDLE;\n buf_state_en = 1'b0;\n buf_rdata_en = 1'b0; // signal to load the buffer when the core sends read data back\n buf_read_error_in = 1'b0; // signal indicating that an error came back with the read from the core\n cmdbuf_wr_en = 1'b0; // all clear from the gasket to load the buffer with the command for reads, command/dat for writes\n case (buf_state)\n IDLE: begin // No commands recieved\n buf_nxtstate = ahb_hwrite ? WR : RD;\n buf_state_en = ahb_hready & ahb_htrans[1] & ahb_hsel; // only transition on a valid hrtans\n end\n WR: begin // Write command recieved last cycle\n buf_nxtstate = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : ahb_hwrite ? WR : RD;\n buf_state_en = (~cmdbuf_full | ahb_hresp) ;\n cmdbuf_wr_en = ~cmdbuf_full & ~(ahb_hresp | ((ahb_htrans[1:0] == 2'b01) & ahb_hsel)); // Dont send command to the buffer in case of an error or when the master is not ready with the data now.\n end\n RD: begin // Read command recieved last cycle.\n buf_nxtstate = ahb_hresp ? IDLE :PEND; // If error go to idle, else wait for read data\n buf_state_en = (~cmdbuf_full | ahb_hresp); // only when command can go, or if its an error\n cmdbuf_wr_en = ~ahb_hresp & ~cmdbuf_full; // send command only when no error\n end\n PEND: begin // Read Command has been sent. Waiting on Data.\n buf_nxtstate = IDLE; // go back for next command and present data next cycle\n buf_state_en = axi_rvalid & ~cmdbuf_write; // read data is back\n buf_rdata_en = buf_state_en; // buffer the read data coming back from core\n buf_read_error_in = buf_state_en & |axi_rresp[1:0]; // buffer error flag if return has Error ( ECC )\n end\n endcase\n end // always_comb begin\n\n rvdffs_fpga #($bits(state_t)) state_reg (.*, .din(buf_nxtstate), .dout({buf_state}), .en(buf_state_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk));\n\n assign master_wstrb[7:0] = ({8{ahb_hsize_q[2:0] == 3'b0}} & (8'b1 << ahb_haddr_q[2:0])) |\n ({8{ahb_hsize_q[2:0] == 3'b1}} & (8'b11 << ahb_haddr_q[2:0])) |\n ({8{ahb_hsize_q[2:0] == 3'b10}} & (8'b1111 << ahb_haddr_q[2:0])) |\n ({8{ahb_hsize_q[2:0] == 3'b11}} & 8'b1111_1111);\n\n // AHB signals\n assign ahb_hreadyout = ahb_hresp ? (ahb_hresp_q & ~ahb_hready_q) :\n ((~cmdbuf_full | (buf_state == IDLE)) & ~(buf_state == RD | buf_state == PEND) & ~buf_read_error);\n\n assign ahb_hready = ahb_hreadyout & ahb_hreadyin;\n assign ahb_htrans_in[1:0] = {2{ahb_hsel}} & ahb_htrans[1:0];\n assign ahb_hrdata[63:0] = buf_rdata[63:0];\n\n if (CHECK_RANGES) begin\n // Miscellaneous signals\n logic ahb_addr_in_dccm, ahb_addr_in_iccm, ahb_addr_in_pic;\n logic ahb_addr_in_dccm_region_nc, ahb_addr_in_iccm_region_nc, ahb_addr_in_pic_region_nc;\n\n assign ahb_hresp = ((ahb_htrans_q[1:0] != 2'b0) & (buf_state != IDLE) &\n ((~(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM\n ((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & ~((ahb_hsize_q[1:0] == 2'b10) | (ahb_hsize_q[1:0] == 2'b11))) | // ICCM Rd/Wr OR DCCM Wr not the right size\n ((ahb_hsize_q[2:0] == 3'h1) & ahb_haddr_q[0]) | // HW size but unaligned\n ((ahb_hsize_q[2:0] == 3'h2) & (|ahb_haddr_q[1:0])) | // W size but unaligned\n ((ahb_hsize_q[2:0] == 3'h3) & (|ahb_haddr_q[2:0])))) | // DW size but unaligned\n buf_read_error | // Read ECC error\n (ahb_hresp_q & ~ahb_hready_q);\n\n // Address check dccm\n rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),\n .CCM_SIZE(pt.DCCM_SIZE)) addr_dccm_rangecheck (\n .addr(ahb_haddr_q[31:0]),\n .in_range(ahb_addr_in_dccm),\n .in_region(ahb_addr_in_dccm_region_nc)\n );\n\n // Address check iccm\n if (pt.ICCM_ENABLE == 1) begin: GenICCM\n rvrangecheck #(.CCM_SADR(pt.ICCM_SADR),\n .CCM_SIZE(pt.ICCM_SIZE)) addr_iccm_rangecheck (\n .addr(ahb_haddr_q[31:0]),\n .in_range(ahb_addr_in_iccm),\n .in_region(ahb_addr_in_iccm_region_nc)\n );\n end else begin: GenNoICCM\n assign ahb_addr_in_iccm = '0;\n assign ahb_addr_in_iccm_region_nc = '0;\n end\n\n // PIC memory address check\n rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),\n .CCM_SIZE(pt.PIC_SIZE)) addr_pic_rangecheck (\n .addr(ahb_haddr_q[31:0]),\n .in_range(ahb_addr_in_pic),\n .in_region(ahb_addr_in_pic_region_nc)\n );\n end else begin // !CHECK_RANGES\n assign ahb_hresp = ((ahb_htrans_q[1:0] != 2'b0) & (buf_state != IDLE) &\n (((ahb_hsize_q[2:0] == 3'h1) & ahb_haddr_q[0]) | // HW size but unaligned\n ((ahb_hsize_q[2:0] == 3'h2) & (|ahb_haddr_q[1:0])) | // W size but unaligned\n ((ahb_hsize_q[2:0] == 3'h3) & (|ahb_haddr_q[2:0])))) | // DW size but unaligned\n buf_read_error | // Read ECC error\n (ahb_hresp_q & ~ahb_hready_q);\n end // CHECK_RANGES\n\n // Buffer signals - needed for the read data and ECC error response\n rvdff_fpga #(.WIDTH(64)) buf_rdata_ff (.din(axi_rdata[63:0]), .dout(buf_rdata[63:0]), .clk(buf_rdata_clk), .clken(buf_rdata_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(1)) buf_read_error_ff(.din(buf_read_error_in), .dout(buf_read_error), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*); // buf_read_error will be high only one cycle\n\n // All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.\n rvdff_fpga #(.WIDTH(1)) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(1)) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(2)) htrans_ff (.din(ahb_htrans_in[1:0]), .dout(ahb_htrans_q[1:0]), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(3)) hsize_ff (.din(ahb_hsize[2:0]), .dout(ahb_hsize_q[2:0]), .clk(ahb_addr_clk), .clken(ahb_addr_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(1)) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(ahb_addr_clk), .clken(ahb_addr_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(32)) haddr_ff (.din(ahb_haddr[31:0]), .dout(ahb_haddr_q[31:0]), .clk(ahb_addr_clk), .clken(ahb_addr_clk_en), .rawclk(clk), .*);\n\n // Command Buffer - Holding for the commands to be sent for the AXI. It will be converted to the AXI signals.\n assign cmdbuf_rst = (((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)) & ~cmdbuf_wr_en) | (ahb_hresp & ~cmdbuf_write);\n assign cmdbuf_full = (cmdbuf_vld & ~((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)));\n\n rvdffsc_fpga #(.WIDTH(1)) cmdbuf_vldff (.din(1'b1), .dout(cmdbuf_vld), .en(cmdbuf_wr_en), .clear(cmdbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(1)) cmdbuf_writeff (.din(ahb_hwrite_q), .dout(cmdbuf_write), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(2)) cmdbuf_sizeff (.din(ahb_hsize_q[1:0]), .dout(cmdbuf_size[1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(8)) cmdbuf_wstrbff (.din(master_wstrb[7:0]), .dout(cmdbuf_wstrb[7:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffe #(.WIDTH(32)) cmdbuf_addrff (.din(ahb_haddr_q[31:0]), .dout(cmdbuf_addr[31:0]), .en(cmdbuf_wr_en & bus_clk_en), .clk(clk), .*);\n rvdffe #(.WIDTH(64)) cmdbuf_wdataff (.din(ahb_hwdata[63:0]), .dout(cmdbuf_wdata[63:0]), .en(cmdbuf_wr_en & bus_clk_en), .clk(clk), .*);\n\n // AXI Write Command Channel\n assign axi_awvalid = cmdbuf_vld & cmdbuf_write;\n assign axi_awid[TAG-1:0] = '0;\n assign axi_awaddr[31:0] = cmdbuf_addr[31:0];\n assign axi_awsize[2:0] = {1'b0, cmdbuf_size[1:0]};\n assign axi_awprot[2:0] = 3'b0;\n assign axi_awlen[7:0] = '0;\n assign axi_awburst[1:0] = 2'b01;\n // AXI Write Data Channel - This is tied to the command channel as we only write the command buffer once we have the data.\n assign axi_wvalid = cmdbuf_vld & cmdbuf_write;\n assign axi_wdata[63:0] = cmdbuf_wdata[63:0];\n assign axi_wstrb[7:0] = cmdbuf_wstrb[7:0];\n assign axi_wlast = 1'b1;\n // AXI Write Response - Always ready. AHB does not require a write response.\n assign axi_bready = 1'b1;\n // AXI Read Channels\n assign axi_arvalid = cmdbuf_vld & ~cmdbuf_write;\n assign axi_arid[TAG-1:0] = '0;\n assign axi_araddr[31:0] = cmdbuf_addr[31:0];\n assign axi_arsize[2:0] = {1'b0, cmdbuf_size[1:0]};\n assign axi_arprot = 3'b0;\n assign axi_arlen[7:0] = '0;\n assign axi_arburst[1:0] = 2'b01;\n // AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always.\n assign axi_rready = 1'b1;\n\n // Clock header logic\n assign ahb_addr_clk_en = bus_clk_en & (ahb_hready & ahb_htrans[1]);\n assign buf_rdata_clk_en = bus_clk_en & buf_rdata_en;\n\n`ifdef RV_FPGA_OPTIMIZE\n assign bus_clk = 1'b0;\n assign ahb_addr_clk = 1'b0;\n assign buf_rdata_clk = 1'b0;\n`else\n rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);\n rvclkhdr ahb_addr_cgc (.en(ahb_addr_clk_en), .l1clk(ahb_addr_clk), .*);\n rvclkhdr buf_rdata_cgc (.en(buf_rdata_clk_en), .l1clk(buf_rdata_clk), .*);\n`endif\n\n`ifdef RV_ASSERT_ON\n property ahb_error_protocol;\n @(posedge bus_clk) (ahb_hready & ahb_hresp) |-> (~$past(ahb_hready) & $past(ahb_hresp));\n endproperty\n assert_ahb_error_protocol: assert property (ahb_error_protocol) else\n $display(\"Bus Error with hReady isn't preceded with Bus Error without hready\");\n\n`endif\n\nendmodule // ahb_to_axi4\n" }, { "path": "design/lib/axi4_to_ahb.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n// Owner:\n// Function: AXI4 -> AHB Bridge\n// Comments:\n//\n//********************************************************************************\nmodule axi4_to_ahb\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n,parameter TAG = 1) (\n\n input clk,\n input free_clk,\n input rst_l,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input scan_mode,\n /*pragma coverage on*/\n input bus_clk_en,\n input clk_override,\n input dec_tlu_force_halt,\n\n // AXI signals\n // AXI Write Channels\n input logic axi_awvalid,\n output logic axi_awready,\n input logic [TAG-1:0] axi_awid,\n input logic [31:0] axi_awaddr,\n input logic [2:0] axi_awsize,\n input logic [2:0] axi_awprot,\n\n input logic axi_wvalid,\n output logic axi_wready,\n input logic [63:0] axi_wdata,\n input logic [7:0] axi_wstrb,\n input logic axi_wlast,\n\n output logic axi_bvalid,\n input logic axi_bready,\n output logic [1:0] axi_bresp,\n output logic [TAG-1:0] axi_bid,\n\n // AXI Read Channels\n input logic axi_arvalid,\n output logic axi_arready,\n input logic [TAG-1:0] axi_arid,\n input logic [31:0] axi_araddr,\n input logic [2:0] axi_arsize,\n input logic [2:0] axi_arprot,\n\n output logic axi_rvalid,\n input logic axi_rready,\n output logic [TAG-1:0] axi_rid,\n output logic [63:0] axi_rdata,\n output logic [1:0] axi_rresp,\n output logic axi_rlast,\n\n // AHB-Lite signals\n output logic [31:0] ahb_haddr, // ahb bus address\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [2:0] ahb_hburst, // tied to 0\n output logic ahb_hmastlock, // tied to 0\n /*pragma coverage on*/\n output logic [3:0] ahb_hprot, // [3:1] are tied to 3'b001\n output logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3)\n output logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now)\n output logic ahb_hwrite, // ahb bus write\n output logic [63:0] ahb_hwdata, // ahb bus write data\n\n input logic [63:0] ahb_hrdata, // ahb bus read data\n input logic ahb_hready, // slave ready to accept transaction\n input logic ahb_hresp // slave response (high indicates erro)\n\n);\n\n localparam ID = 1;\n localparam PRTY = 1;\n typedef enum logic [3:0] {\n IDLE = 4'b0000,\n CMD_RD = 4'b0001,\n CMD_WR = 4'b1001,\n DATA_RD = 4'b0010,\n DATA_WR = 4'b1010,\n DONE_RD = 4'b0011,\n DONE_WR = 4'b1011,\n STREAM_RD = 4'b0101,\n STREAM_ERR_RD = 4'b0110\n } state_t;\n\n state_t buf_state, buf_nxtstate;\n\n logic slave_valid;\n logic [TAG-1:0] slave_tag;\n logic [63:0] slave_rdata;\n logic [3:0] slave_opc;\n\n logic wrbuf_en, wrbuf_data_en;\n logic wrbuf_cmd_sent, wrbuf_rst;\n logic wrbuf_vld;\n logic wrbuf_data_vld;\n logic [TAG-1:0] wrbuf_tag;\n logic [2:0] wrbuf_size;\n logic [31:0] wrbuf_addr;\n logic [63:0] wrbuf_data;\n logic [7:0] wrbuf_byteen;\n\n logic master_valid;\n logic master_ready;\n logic [TAG-1:0] master_tag;\n logic [31:0] master_addr;\n logic [63:0] master_wdata;\n logic [2:0] master_size;\n logic [2:0] master_opc;\n logic [7:0] master_byteen;\n\n // Buffer signals (one entry buffer)\n logic [31:0] buf_addr;\n logic [1:0] buf_size;\n logic buf_write;\n logic [7:0] buf_byteen;\n logic buf_aligned;\n logic [63:0] buf_data;\n logic [TAG-1:0] buf_tag;\n\n //Miscellaneous signals\n logic buf_rst;\n logic [TAG-1:0] buf_tag_in;\n logic [31:0] buf_addr_in;\n logic [7:0] buf_byteen_in;\n logic [63:0] buf_data_in;\n logic buf_write_in;\n logic buf_aligned_in;\n logic [2:0] buf_size_in;\n\n logic buf_state_en;\n logic buf_wr_en;\n logic buf_data_wr_en;\n logic slvbuf_error_en;\n logic wr_cmd_vld;\n\n logic cmd_done_rst, cmd_done, cmd_doneQ;\n logic trxn_done;\n logic [2:0] buf_cmd_byte_ptr, buf_cmd_byte_ptrQ, buf_cmd_nxtbyte_ptr;\n logic buf_cmd_byte_ptr_en;\n\n logic slave_valid_pre;\n logic ahb_hready_q;\n logic ahb_hresp_q;\n logic [1:0] ahb_htrans_q;\n logic ahb_hwrite_q;\n logic [63:0] ahb_hrdata_q;\n\n\n logic slvbuf_write;\n logic slvbuf_error;\n logic [TAG-1:0] slvbuf_tag;\n\n logic slvbuf_error_in;\n logic slvbuf_wr_en;\n logic bypass_en;\n logic rd_bypass_idle;\n\n logic last_addr_en;\n logic [31:0] last_bus_addr;\n\n // Clocks\n logic buf_clken;\n logic ahbm_data_clken;\n\n logic buf_clk;\n logic bus_clk;\n logic ahbm_data_clk;\n\n logic dec_tlu_force_halt_bus, dec_tlu_force_halt_bus_ns, dec_tlu_force_halt_bus_q;\n\n // Function to get the length from byte enable\n function automatic logic [1:0] get_write_size;\n input logic [7:0] byteen;\n\n logic [1:0] size;\n\n size[1:0] = (2'b11 & {2{(byteen[7:0] == 8'hff)}}) |\n (2'b10 & {2{((byteen[7:0] == 8'hf0) | (byteen[7:0] == 8'h0f))}}) |\n (2'b01 & {2{((byteen[7:0] == 8'hc0) | (byteen[7:0] == 8'h30) | (byteen[7:0] == 8'h0c) | (byteen[7:0] == 8'h03))}});\n\n return size[1:0];\n endfunction // get_write_size\n\n // Function to get the length from byte enable\n function automatic logic [2:0] get_write_addr;\n input logic [7:0] byteen;\n\n logic [2:0] addr;\n\n addr[2:0] = (3'h0 & {3{((byteen[7:0] == 8'hff) | (byteen[7:0] == 8'h0f) | (byteen[7:0] == 8'h03))}}) |\n (3'h2 & {3{(byteen[7:0] == 8'h0c)}}) |\n (3'h4 & {3{((byteen[7:0] == 8'hf0) | (byteen[7:0] == 8'h03))}}) |\n (3'h6 & {3{(byteen[7:0] == 8'hc0)}});\n\n return addr[2:0];\n endfunction // get_write_addr\n\n // Function to get the next byte pointer\n function automatic logic [2:0] get_nxtbyte_ptr (logic [2:0] current_byte_ptr, logic [7:0] byteen, logic get_next);\n logic [2:0] start_ptr;\n logic found;\n found = '0;\n get_nxtbyte_ptr[2:0] = 3'd0; \n start_ptr[2:0] = get_next ? (current_byte_ptr[2:0] + 3'b1) : current_byte_ptr[2:0];\n for (int j=0; j<8; j++) begin\n if (~found) begin\n get_nxtbyte_ptr[2:0] = 3'(j);\n found |= (byteen[j] & (3'(j) >= start_ptr[2:0])) ;\n end\n end\n endfunction // get_nextbyte_ptr\n\n // Create bus synchronized version of force halt\n assign dec_tlu_force_halt_bus = dec_tlu_force_halt | dec_tlu_force_halt_bus_q;\n assign dec_tlu_force_halt_bus_ns = ~bus_clk_en & dec_tlu_force_halt_bus;\n rvdff #(.WIDTH(1)) force_halt_busff(.din(dec_tlu_force_halt_bus_ns), .dout(dec_tlu_force_halt_bus_q), .clk(free_clk), .*);\n\n // Write buffer\n assign wrbuf_en = axi_awvalid & axi_awready & master_ready;\n assign wrbuf_data_en = axi_wvalid & axi_wready & master_ready;\n assign wrbuf_cmd_sent = master_valid & master_ready & (master_opc[2:1] == 2'b01);\n assign wrbuf_rst = (wrbuf_cmd_sent & ~wrbuf_en) | dec_tlu_force_halt_bus;\n\n assign axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent) & master_ready;\n assign axi_wready = ~(wrbuf_data_vld & ~wrbuf_cmd_sent) & master_ready;\n assign axi_arready = ~(wrbuf_vld & wrbuf_data_vld) & master_ready;\n assign axi_rlast = 1'b1;\n\n assign wr_cmd_vld = (wrbuf_vld & wrbuf_data_vld);\n assign master_valid = wr_cmd_vld | axi_arvalid;\n assign master_tag[TAG-1:0] = wr_cmd_vld ? wrbuf_tag[TAG-1:0] : axi_arid[TAG-1:0];\n assign master_opc[2:0] = wr_cmd_vld ? 3'b011 : 3'b0;\n assign master_addr[31:0] = wr_cmd_vld ? wrbuf_addr[31:0] : axi_araddr[31:0];\n assign master_size[2:0] = wr_cmd_vld ? wrbuf_size[2:0] : axi_arsize[2:0];\n assign master_byteen[7:0] = wrbuf_byteen[7:0];\n assign master_wdata[63:0] = wrbuf_data[63:0];\n\n // AXI response channel signals\n assign axi_bvalid = slave_valid & slave_opc[3];\n assign axi_bresp[1:0] = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0);\n assign axi_bid[TAG-1:0] = slave_tag[TAG-1:0];\n\n assign axi_rvalid = slave_valid & (slave_opc[3:2] == 2'b0);\n assign axi_rresp[1:0] = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0);\n assign axi_rid[TAG-1:0] = slave_tag[TAG-1:0];\n assign axi_rdata[63:0] = slave_rdata[63:0];\n\n // FIFO state machine\n always_comb begin\n buf_nxtstate = IDLE;\n buf_state_en = 1'b0;\n buf_wr_en = 1'b0;\n buf_data_wr_en = 1'b0;\n slvbuf_error_in = 1'b0;\n slvbuf_error_en = 1'b0;\n buf_write_in = 1'b0;\n cmd_done = 1'b0;\n trxn_done = 1'b0;\n buf_cmd_byte_ptr_en = 1'b0;\n buf_cmd_byte_ptr[2:0] = '0;\n slave_valid_pre = 1'b0;\n master_ready = 1'b0;\n ahb_htrans[1:0] = 2'b0;\n slvbuf_wr_en = 1'b0;\n bypass_en = 1'b0;\n rd_bypass_idle = 1'b0;\n\n case (buf_state)\n IDLE: begin\n master_ready = 1'b1;\n buf_write_in = (master_opc[2:1] == 2'b01);\n buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;\n buf_state_en = master_valid & master_ready;\n buf_wr_en = buf_state_en;\n buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);\n buf_cmd_byte_ptr_en = buf_state_en;\n buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];\n bypass_en = buf_state_en;\n rd_bypass_idle = bypass_en & (buf_nxtstate == CMD_RD);\n ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;\n end\n CMD_RD: begin\n buf_nxtstate = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;\n buf_state_en = ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) & ~ahb_hwrite_q;\n cmd_done = buf_state_en & ~master_valid;\n slvbuf_wr_en = buf_state_en;\n master_ready = buf_state_en & (buf_nxtstate == STREAM_RD);\n buf_wr_en = master_ready;\n bypass_en = master_ready & master_valid;\n buf_cmd_byte_ptr[2:0] = bypass_en ? master_addr[2:0] : buf_addr[2:0];\n ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en | bypass_en}};\n end\n STREAM_RD: begin\n master_ready = (ahb_hready_q & ~ahb_hresp_q) & ~(master_valid & master_opc[2:1] == 2'b01);\n buf_wr_en = (master_valid & master_ready & (master_opc[2:0] == 3'b000)); // update the fifo if we are streaming the read commands\n buf_nxtstate = ahb_hresp_q ? STREAM_ERR_RD : (buf_wr_en ? STREAM_RD : DATA_RD); // assuming that the master accpets the slave response right away.\n buf_state_en = (ahb_hready_q | ahb_hresp_q);\n buf_data_wr_en = buf_state_en;\n slvbuf_error_in = ahb_hresp_q;\n slvbuf_error_en = buf_state_en;\n slave_valid_pre = buf_state_en & ~ahb_hresp_q; // send a response right away if we are not going through an error response.\n cmd_done = buf_state_en & ~master_valid; // last one of the stream should not send a htrans\n bypass_en = master_ready & master_valid & (buf_nxtstate == STREAM_RD) & buf_state_en;\n buf_cmd_byte_ptr[2:0] = bypass_en ? master_addr[2:0] : buf_addr[2:0];\n ahb_htrans[1:0] = 2'b10 & {2{~((buf_nxtstate != STREAM_RD) & buf_state_en)}};\n slvbuf_wr_en = buf_wr_en; // shifting the contents from the buf to slv_buf for streaming cases\n end // case: STREAM_RD\n STREAM_ERR_RD: begin\n buf_nxtstate = DATA_RD;\n buf_state_en = ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) & ~ahb_hwrite_q;\n slave_valid_pre = buf_state_en;\n slvbuf_wr_en = buf_state_en; // Overwrite slvbuf with buffer\n buf_cmd_byte_ptr[2:0] = buf_addr[2:0];\n ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en}};\n end\n DATA_RD: begin\n buf_nxtstate = DONE_RD;\n buf_state_en = (ahb_hready_q | ahb_hresp_q);\n buf_data_wr_en = buf_state_en;\n slvbuf_error_in= ahb_hresp_q;\n slvbuf_error_en= buf_state_en;\n slvbuf_wr_en = buf_state_en;\n\n end\n CMD_WR: begin\n buf_nxtstate = DATA_WR;\n trxn_done = ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q[1:0] != 2'b0);\n buf_state_en = trxn_done;\n buf_cmd_byte_ptr_en = buf_state_en;\n slvbuf_wr_en = buf_state_en;\n buf_cmd_byte_ptr = trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;\n cmd_done = trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ == 3'b111) |\n (buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0));\n ahb_htrans[1:0] = {2{~(cmd_done | cmd_doneQ)}} & 2'b10;\n end\n DATA_WR: begin\n buf_state_en = (cmd_doneQ & ahb_hready_q) | ahb_hresp_q;\n master_ready = buf_state_en & ~ahb_hresp_q & axi_bready; // Ready to accept new command if current command done and no error\n buf_nxtstate = (ahb_hresp_q | ~axi_bready) ? DONE_WR :\n ((master_valid & master_ready) ? ((master_opc[2:1] == 2'b01) ? CMD_WR : CMD_RD) : IDLE);\n slvbuf_error_in = ahb_hresp_q;\n slvbuf_error_en = buf_state_en;\n\n buf_write_in = (master_opc[2:1] == 2'b01);\n buf_wr_en = buf_state_en & ((buf_nxtstate == CMD_WR) | (buf_nxtstate == CMD_RD));\n buf_data_wr_en = buf_wr_en;\n\n cmd_done = (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) &\n ((buf_cmd_byte_ptrQ == 3'b111) | (buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0))));\n bypass_en = buf_state_en & buf_write_in & (buf_nxtstate == CMD_WR); // Only bypass for writes for the time being\n ahb_htrans[1:0] = {2{(~(cmd_done | cmd_doneQ) | bypass_en)}} & 2'b10;\n slave_valid_pre = buf_state_en & (buf_nxtstate != DONE_WR);\n\n trxn_done = ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q[1:0] != 2'b0);\n buf_cmd_byte_ptr_en = trxn_done | bypass_en;\n buf_cmd_byte_ptr = bypass_en ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) :\n trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;\n end\n DONE_WR: begin\n buf_nxtstate = IDLE;\n buf_state_en = axi_bvalid & axi_bready;\n slvbuf_error_en = 1'b1;\n slave_valid_pre = 1'b1;\n end\n DONE_RD: begin\n buf_nxtstate = IDLE;\n buf_state_en = axi_rvalid & axi_rready; // axi_rlast == 1\n slvbuf_error_en = 1'b1;\n slave_valid_pre = 1'b1;\n end\n // `buf_state` is an enum and all the members are handled above, so the default case is excluded from coverge.\n /*pragma coverage off*/\n default: begin\n buf_nxtstate = IDLE;\n buf_state_en = 1'b1;\n end\n /*pragma coverage on*/\n endcase\n end\n\n assign buf_rst = dec_tlu_force_halt_bus;\n assign cmd_done_rst = slave_valid_pre;\n assign buf_addr_in[31:3] = master_addr[31:3];\n assign buf_addr_in[2:0] = (buf_aligned_in & (master_opc[2:1] == 2'b01)) ? get_write_addr(master_byteen[7:0]) : master_addr[2:0];\n assign buf_tag_in[TAG-1:0] = master_tag[TAG-1:0];\n assign buf_byteen_in[7:0] = wrbuf_byteen[7:0];\n assign buf_data_in[63:0] = (buf_state == DATA_RD) ? ahb_hrdata_q[63:0] : master_wdata[63:0];\n assign buf_size_in[1:0] = (buf_aligned_in & (master_size[1:0] == 2'b11) & (master_opc[2:1] == 2'b01)) ? get_write_size(master_byteen[7:0]) : master_size[1:0];\n assign buf_aligned_in = (master_opc[2:0] == 3'b0) | // reads are always aligned since they are either DW or sideeffects\n (master_size[1:0] == 2'b0) | (master_size[1:0] == 2'b01) | (master_size[1:0] == 2'b10) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned\n ((master_size[1:0] == 2'b11) &\n ((master_byteen[7:0] == 8'h3) | (master_byteen[7:0] == 8'hc) | (master_byteen[7:0] == 8'h30) | (master_byteen[7:0] == 8'hc0) |\n (master_byteen[7:0] == 8'hf) | (master_byteen[7:0] == 8'hf0) | (master_byteen[7:0] == 8'hff)));\n\n // Generate the ahb signals\n assign ahb_haddr[31:3] = bypass_en ? master_addr[31:3] : buf_addr[31:3];\n assign ahb_haddr[2:0] = {3{(ahb_htrans == 2'b10)}} & buf_cmd_byte_ptr[2:0]; // Trxn should be aligned during IDLE\n assign ahb_hsize[2:0] = bypass_en ? {1'b0, ({2{buf_aligned_in}} & buf_size_in[1:0])} :\n {1'b0, ({2{buf_aligned}} & buf_size[1:0])}; // Send the full size for aligned trxn\n assign ahb_hburst[2:0] = 3'b0;\n assign ahb_hmastlock = 1'b0;\n assign ahb_hprot[3:0] = {3'b001,~axi_arprot[2]};\n assign ahb_hwrite = bypass_en ? (master_opc[2:1] == 2'b01) : buf_write;\n assign ahb_hwdata[63:0] = buf_data[63:0];\n\n assign slave_valid = slave_valid_pre;// & (~slvbuf_posted_write | slvbuf_error);\n assign slave_opc[3:2] = slvbuf_write ? 2'b11 : 2'b00;\n assign slave_opc[1:0] = {2{slvbuf_error}} & 2'b10;\n assign slave_rdata[63:0] = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE_RD) ? buf_data[63:0] : ahb_hrdata_q[63:0]);\n assign slave_tag[TAG-1:0] = slvbuf_tag[TAG-1:0];\n\n assign last_addr_en = (ahb_htrans[1:0] != 2'b0) & ahb_hready & ahb_hwrite ;\n\n\n rvdffsc_fpga #(.WIDTH(1)) wrbuf_vldff (.din(1'b1), .dout(wrbuf_vld), .en(wrbuf_en), .clear(wrbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffsc_fpga #(.WIDTH(1)) wrbuf_data_vldff(.din(1'b1), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clear(wrbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(TAG)) wrbuf_tagff (.din(axi_awid[TAG-1:0]), .dout(wrbuf_tag[TAG-1:0]), .en(wrbuf_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(3)) wrbuf_sizeff (.din(axi_awsize[2:0]), .dout(wrbuf_size[2:0]), .en(wrbuf_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffe #(.WIDTH(32)) wrbuf_addrff (.din(axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]), .en(wrbuf_en & bus_clk_en), .clk(clk), .*);\n rvdffe #(.WIDTH(64)) wrbuf_dataff (.din(axi_wdata[63:0]), .dout(wrbuf_data[63:0]), .en(wrbuf_data_en & bus_clk_en), .clk(clk), .*);\n rvdffs_fpga #(.WIDTH(8)) wrbuf_byteenff (.din(axi_wstrb[7:0]), .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n\n rvdffs_fpga #(.WIDTH(32)) last_bus_addrff (.din(ahb_haddr[31:0]), .dout(last_bus_addr[31:0]), .en(last_addr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n\n rvdffsc_fpga #(.WIDTH($bits(state_t))) buf_state_ff (.din(buf_nxtstate), .dout({buf_state}), .en(buf_state_en), .clear(buf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(1)) buf_writeff (.din(buf_write_in), .dout(buf_write), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(TAG)) buf_tagff (.din(buf_tag_in[TAG-1:0]), .dout(buf_tag[TAG-1:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);\n rvdffe #(.WIDTH(32)) buf_addrff (.din(buf_addr_in[31:0]), .dout(buf_addr[31:0]), .en(buf_wr_en & bus_clk_en), .clk(clk), .*);\n rvdffs_fpga #(.WIDTH(2)) buf_sizeff (.din(buf_size_in[1:0]), .dout(buf_size[1:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(1)) buf_alignedff (.din(buf_aligned_in), .dout(buf_aligned), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(8)) buf_byteenff (.din(buf_byteen_in[7:0]), .dout(buf_byteen[7:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);\n rvdffe #(.WIDTH(64)) buf_dataff (.din(buf_data_in[63:0]), .dout(buf_data[63:0]), .en(buf_data_wr_en & bus_clk_en), .clk(clk), .*);\n\n\n rvdffs_fpga #(.WIDTH(1)) slvbuf_writeff (.din(buf_write), .dout(slvbuf_write), .en(slvbuf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(TAG)) slvbuf_tagff (.din(buf_tag[TAG-1:0]), .dout(slvbuf_tag[TAG-1:0]), .en(slvbuf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(1)) slvbuf_errorff (.din(slvbuf_error_in), .dout(slvbuf_error), .en(slvbuf_error_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n\n rvdffsc_fpga #(.WIDTH(1)) buf_cmd_doneff (.din(1'b1), .dout(cmd_doneQ), .en(cmd_done), .clear(cmd_done_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(3)) buf_cmd_byte_ptrff (.din(buf_cmd_byte_ptr[2:0]), .dout(buf_cmd_byte_ptrQ[2:0]), .en(buf_cmd_byte_ptr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n\n rvdff_fpga #(.WIDTH(1)) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(2)) htrans_ff (.din(ahb_htrans[1:0]), .dout(ahb_htrans_q[1:0]), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(1)) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(1)) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(64)) hrdata_ff (.din(ahb_hrdata[63:0]), .dout(ahb_hrdata_q[63:0]), .clk(ahbm_data_clk), .clken(ahbm_data_clken), .rawclk(clk), .*);\n\n // Clock headers\n // clock enables for ahbm addr/data\n assign buf_clken = bus_clk_en & (buf_wr_en | slvbuf_wr_en | clk_override);\n assign ahbm_data_clken = bus_clk_en & ((buf_state != IDLE) | clk_override);\n\n`ifdef RV_FPGA_OPTIMIZE\n assign bus_clk = 1'b0;\n assign buf_clk = 1'b0;\n assign ahbm_data_clk = 1'b0;\n`else\n rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);\n rvclkhdr buf_cgc (.en(buf_clken), .l1clk(buf_clk), .*);\n rvclkhdr ahbm_data_cgc (.en(ahbm_data_clken), .l1clk(ahbm_data_clk), .*);\n`endif\n\n`ifdef RV_ASSERT_ON\n property ahb_trxn_aligned;\n @(posedge bus_clk) ahb_htrans[1] |-> ((ahb_hsize[2:0] == 3'h0) |\n ((ahb_hsize[2:0] == 3'h1) & (ahb_haddr[0] == 1'b0)) |\n ((ahb_hsize[2:0] == 3'h2) & (ahb_haddr[1:0] == 2'b0)) |\n ((ahb_hsize[2:0] == 3'h3) & (ahb_haddr[2:0] == 3'b0)));\n endproperty\n assert_ahb_trxn_aligned: assert property (ahb_trxn_aligned) else\n $display(\"Assertion ahb_trxn_aligned failed: ahb_htrans=2'h%h, ahb_hsize=3'h%h, ahb_haddr=32'h%h\",ahb_htrans[1:0], ahb_hsize[2:0], ahb_haddr[31:0]);\n\n property ahb_error_protocol;\n @(posedge bus_clk) (ahb_hready & ahb_hresp) |-> (~$past(ahb_hready) & $past(ahb_hresp));\n endproperty\n assert_ahb_error_protocol: assert property (ahb_error_protocol) else\n $display(\"Bus Error with hReady isn't preceded with Bus Error without hready\");\n`endif\n\nendmodule // axi4_to_ahb\n" }, { "path": "design/lib/beh_lib.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n// all flops call the rvdff flop\n\n\nmodule rvdff #( parameter WIDTH=1, SHORT=0 )\n (\n input logic [WIDTH-1:0] din,\n input logic clk,\n input logic rst_l,\n\n output logic [WIDTH-1:0] dout\n );\n\nif (SHORT == 1) begin\n assign dout = din;\nend\nelse begin\n`ifdef RV_CLOCKGATE\n always @(posedge tb_top.clk) begin\n #0 $strobe(\"CG: %0t %m din %x dout %x clk %b width %d\",$time,din,dout,clk,WIDTH);\n end\n`endif\n\n always_ff @(posedge clk or negedge rst_l) begin\n if (rst_l == 0)\n dout[WIDTH-1:0] <= 0;\n else\n dout[WIDTH-1:0] <= din[WIDTH-1:0];\n end\n\nend\nendmodule\n\n// rvdff with 2:1 input mux to flop din iff sel==1\nmodule rvdffs #( parameter WIDTH=1, SHORT=0 )\n (\n input logic [WIDTH-1:0] din,\n input logic en,\n input logic clk,\n input logic rst_l,\n output logic [WIDTH-1:0] dout\n );\n\nif (SHORT == 1) begin : genblock\n assign dout = din;\nend\nelse begin : genblock\n rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*);\nend\n\nendmodule\n\n// rvdff with en and clear\nmodule rvdffsc #( parameter WIDTH=1, SHORT=0 )\n (\n input logic [WIDTH-1:0] din,\n input logic en,\n input logic clear,\n input logic clk,\n input logic rst_l,\n output logic [WIDTH-1:0] dout\n );\n\n logic [WIDTH-1:0] din_new;\nif (SHORT == 1) begin : genblock\n assign dout = din;\nend\nelse begin : genblock\n assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]);\n rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*);\nend\nendmodule\n\n// _fpga versions\nmodule rvdff_fpga #( parameter WIDTH=1, SHORT=0 )\n (\n input logic [WIDTH-1:0] din,\n input logic clk,\n input logic clken,\n input logic rawclk,\n input logic rst_l,\n\n output logic [WIDTH-1:0] dout\n );\n\nif (SHORT == 1) begin : genblock\n assign dout = din;\nend\nelse begin : genblock\n `ifdef RV_FPGA_OPTIMIZE\n rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken), .*);\n`else\n rvdff #(WIDTH) dff (.*);\n`endif\nend\nendmodule\n\n// rvdff with 2:1 input mux to flop din iff sel==1\nmodule rvdffs_fpga #( parameter WIDTH=1, SHORT=0 )\n (\n input logic [WIDTH-1:0] din,\n input logic en,\n input logic clk,\n input logic clken,\n input logic rawclk,\n input logic rst_l,\n\n output logic [WIDTH-1:0] dout\n );\n\nif (SHORT == 1) begin : genblock\n assign dout = din;\nend\nelse begin : genblock\n`ifdef RV_FPGA_OPTIMIZE\n rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken & en), .*);\n`else\n rvdffs #(WIDTH) dffs (.*);\n`endif\nend\n\nendmodule\n\n// rvdff with en and clear\nmodule rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )\n (\n input logic [WIDTH-1:0] din,\n input logic en,\n input logic clear,\n input logic clk,\n input logic clken,\n input logic rawclk,\n input logic rst_l,\n\n output logic [WIDTH-1:0] dout\n );\n\n logic [WIDTH-1:0] din_new;\nif (SHORT == 1) begin : genblock\n assign dout = din;\nend\nelse begin : genblock\n`ifdef RV_FPGA_OPTIMIZE\n rvdffs #(WIDTH) dffs (.clk(rawclk), .din(din[WIDTH-1:0] & {WIDTH{~clear}}),.en((en | clear) & clken), .*);\n`else\n rvdffsc #(WIDTH) dffsc (.*);\n`endif\nend\nendmodule\n\n\nmodule rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )\n (\n input logic [WIDTH-1:0] din,\n input logic en,\n input logic clk,\n input logic rst_l,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n output logic [WIDTH-1:0] dout\n );\n\n logic l1clk;\n\nif (SHORT == 1) begin : genblock\n if (1) begin : genblock\n assign dout = din;\n end\nend\nelse begin : genblock\n\n`ifndef RV_PHYSICAL\n if (WIDTH >= 8 || OVERRIDE==1) begin: genblock\n`endif\n\n`ifdef RV_FPGA_OPTIMIZE\n rvdffs #(WIDTH) dff ( .* );\n`else\n rvclkhdr clkhdr ( .* );\n rvdff #(WIDTH) dff (.*, .clk(l1clk));\n`endif\n\n`ifndef RV_PHYSICAL\n end\n else\n $error(\"%m: rvdffe must be WIDTH >= 8\");\n`endif\nend // else: !if(SHORT == 1)\n\nendmodule // rvdffe\n\n\nmodule rvdffpcie #( parameter WIDTH=31 )\n (\n input logic [WIDTH-1:0] din,\n input logic clk,\n input logic rst_l,\n input logic en,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n output logic [WIDTH-1:0] dout\n );\n\n\n\n`ifndef RV_PHYSICAL\n if (WIDTH == 31) begin: genblock\n`endif\n\n`ifdef RV_FPGA_OPTIMIZE\n rvdffs #(WIDTH) dff ( .* );\n`else\n\n rvdfflie #(.WIDTH(WIDTH), .LEFT(19)) dff (.*);\n\n`endif\n\n`ifndef RV_PHYSICAL\n end\n else\n $error(\"%m: rvdffpcie width must be 31\");\n`endif\nendmodule\n\n// format: { LEFT, EXTRA }\n// LEFT # of bits will be done with rvdffie, all else EXTRA with rvdffe\nmodule rvdfflie #( parameter WIDTH=16, LEFT=8 )\n (\n input logic [WIDTH-1:0] din,\n input logic clk,\n input logic rst_l,\n input logic en,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n output logic [WIDTH-1:0] dout\n );\n\n localparam EXTRA = WIDTH-LEFT;\n\n\n\n\n\n\n\n localparam LMSB = WIDTH-1;\n localparam LLSB = LMSB-LEFT+1;\n localparam XMSB = LLSB-1;\n localparam XLSB = LLSB-EXTRA;\n\n\n`ifndef RV_PHYSICAL\n if (WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8) begin: genblock\n`endif\n\n`ifdef RV_FPGA_OPTIMIZE\n rvdffs #(WIDTH) dff ( .* );\n`else\n\n rvdffiee #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));\n\n\n rvdffe #(EXTRA) dff_extra (.*, .din(din[XMSB:XLSB]), .dout(dout[XMSB:XLSB]));\n\n\n\n\n`endif\n\n`ifndef RV_PHYSICAL\n end\n else\n $error(\"%m: rvdfflie musb be WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8\");\n`endif\nendmodule\n\n\n\n\n// special power flop for predict packet\n// format: { LEFT, RIGHT==31 }\n// LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en\nmodule rvdffppe #( parameter integer WIDTH = 39 )\n (\n input logic [WIDTH-1:0] din,\n input logic clk,\n input logic rst_l,\n input logic en,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n output logic [WIDTH-1:0] dout\n );\n\n localparam integer RIGHT = 31;\n localparam integer LEFT = WIDTH - RIGHT;\n\n localparam integer LMSB = WIDTH-1;\n localparam integer LLSB = LMSB-LEFT+1;\n localparam integer RMSB = LLSB-1;\n localparam integer RLSB = LLSB-RIGHT;\n\n\n`ifndef RV_PHYSICAL\n if (WIDTH>=32 && LEFT>=8 && RIGHT>=8) begin: genblock\n`endif\n\n`ifdef RV_FPGA_OPTIMIZE\n rvdffs #(WIDTH) dff ( .* );\n`else\n rvdffe #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));\n\n rvdffe #(RIGHT) dff_right (.*, .din(din[RMSB:RLSB]), .dout(dout[RMSB:RLSB]), .en(en & din[LLSB])); // qualify with pret\n\n\n`endif\n\n`ifndef RV_PHYSICAL\n end\n else\n $error(\"%m: must be WIDTH>=32 && LEFT>=8 && RIGHT>=8\");\n`endif\nendmodule\n\n\n\n\nmodule rvdffie #( parameter WIDTH=1, OVERRIDE=0 )\n (\n input logic [WIDTH-1:0] din,\n\n input logic clk,\n input logic rst_l,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n output logic [WIDTH-1:0] dout\n );\n\n logic l1clk;\n logic en;\n\n\n\n\n\n\n\n\n`ifndef RV_PHYSICAL\n if (WIDTH >= 8 || OVERRIDE==1) begin: genblock\n`endif\n\n assign en = |(din ^ dout);\n\n`ifdef RV_FPGA_OPTIMIZE\n rvdffs #(WIDTH) dff ( .* );\n`else\n rvclkhdr clkhdr ( .* );\n rvdff #(WIDTH) dff (.*, .clk(l1clk));\n`endif\n\n`ifndef RV_PHYSICAL\n end\n else\n $error(\"%m: rvdffie must be WIDTH >= 8\");\n`endif\n\n\nendmodule\n\n// ie flop but it has an .en input\nmodule rvdffiee #( parameter WIDTH=1, OVERRIDE=0 )\n (\n input logic [WIDTH-1:0] din,\n\n input logic clk,\n input logic rst_l,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n input logic en,\n output logic [WIDTH-1:0] dout\n );\n\n logic l1clk;\n logic final_en;\n\n`ifndef RV_PHYSICAL\n if (WIDTH >= 8 || OVERRIDE==1) begin: genblock\n`endif\n\n assign final_en = (|(din ^ dout)) & en;\n\n`ifdef RV_FPGA_OPTIMIZE\n rvdffs #(WIDTH) dff ( .*, .en(final_en) );\n`else\n rvdffe #(WIDTH) dff (.*, .en(final_en));\n`endif\n\n`ifndef RV_PHYSICAL\n end\n else\n $error(\"%m: rvdffie width must be >= 8\");\n`endif\n\nendmodule\n\n\n\nmodule rvsyncss #(parameter WIDTH = 251)\n (\n input logic clk,\n input logic rst_l,\n input logic [WIDTH-1:0] din,\n output logic [WIDTH-1:0] dout\n );\n\n logic [WIDTH-1:0] din_ff1;\n\n rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));\n rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));\n\nendmodule // rvsyncss\n\nmodule rvsyncss_fpga #(parameter WIDTH = 251)\n (\n input logic gw_clk,\n input logic rawclk,\n input logic clken,\n input logic rst_l,\n input logic [WIDTH-1:0] din,\n output logic [WIDTH-1:0] dout\n );\n\n logic [WIDTH-1:0] din_ff1;\n\n rvdff_fpga #(WIDTH) sync_ff1 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));\n rvdff_fpga #(WIDTH) sync_ff2 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));\n\nendmodule // rvsyncss\n\nmodule rvlsadder\n (\n input logic [31:0] rs1,\n input logic [11:0] offset,\n\n output logic [31:0] dout\n );\n\n logic cout;\n logic sign;\n\n logic [31:12] rs1_inc;\n logic [31:12] rs1_dec;\n\n assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};\n\n assign rs1_inc[31:12] = rs1[31:12] + 1;\n\n assign rs1_dec[31:12] = rs1[31:12] - 1;\n\n assign sign = offset[11];\n\n assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) |\n ({20{ ~sign & cout}} & rs1_inc[31:12]) |\n ({20{ sign & ~cout}} & rs1_dec[31:12]);\n\nendmodule // rvlsadder\n\n// assume we only maintain pc[31:1] in the pipe\n\nmodule rvbradder\n (\n input [31:1] pc,\n input [12:1] offset,\n\n output [31:1] dout\n );\n\n logic cout;\n logic sign;\n\n logic [31:13] pc_inc;\n logic [31:13] pc_dec;\n\n assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]};\n\n assign pc_inc[31:13] = pc[31:13] + 1;\n\n assign pc_dec[31:13] = pc[31:13] - 1;\n\n assign sign = offset[12];\n\n\n assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) |\n ({19{ ~sign & cout}} & pc_inc[31:13]) |\n ({19{ sign & ~cout}} & pc_dec[31:13]);\n\n\nendmodule // rvbradder\n\n\n// 2s complement circuit\nmodule rvtwoscomp #( parameter WIDTH=32 )\n (\n input logic [WIDTH-1:0] din,\n\n output logic [WIDTH-1:0] dout\n );\n\n logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din\n\n genvar i;\n\n for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one\n assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i];\n end : flip_after_first_one\n\n assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] };\n\nendmodule // 2'scomp\n\n// find first\nmodule rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) )\n (\n input logic [WIDTH-1:0] din,\n\n output logic [SHIFT-1:0] dout\n );\n logic done;\n\n always_comb begin\n dout[SHIFT-1:0] = {SHIFT{1'b0}};\n done = 1'b0;\n\n for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one\n done |= din[i];\n dout[SHIFT-1:0] += done ? 1'b0 : 1'b1;\n end : find_first_one\n end\nendmodule // rvfindfirst1\n\nmodule rvfindfirst1hot #( parameter WIDTH=32 )\n (\n input logic [WIDTH-1:0] din,\n\n output logic [WIDTH-1:0] dout\n );\n logic done;\n\n always_comb begin\n dout[WIDTH-1:0] = {WIDTH{1'b0}};\n done = 1'b0;\n for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one\n dout[i] = ~done & din[i];\n done |= din[i];\n end : find_first_one\n end\nendmodule // rvfindfirst1hot\n\n// mask and match function matches bits after finding the first 0 position\n// find first starting from LSB. Skip that location and match the rest of the bits\nmodule rvmaskandmatch #( parameter WIDTH=32 )\n (\n input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions\n input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits\n input logic masken, // when 1 : do mask. 0 : full match\n output logic match\n );\n\n logic [WIDTH-1:0] matchvec;\n logic masken_or_fullmask;\n\n assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]);\n\n assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);\n genvar i;\n\n for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero\n assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]);\n end : match_after_first_zero\n\n assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off\n\nendmodule // rvmaskandmatch\n\n\n\n\n// Check if the S_ADDR <= addr < E_ADDR\nmodule rvrangecheck #(CCM_SADR = 32'h0,\n CCM_SIZE = 128) (\n input logic [31:0] addr, // Address to be checked for range\n output logic in_range, // S_ADDR <= start_addr < E_ADDR\n output logic in_region\n);\n\n localparam REGION_BITS = 4;\n localparam MASK_BITS = 10 + $clog2(CCM_SIZE);\n\n logic [31:0] start_addr;\n logic [3:0] region;\n\n assign start_addr[31:0] = CCM_SADR;\n assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)];\n\n assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]);\n if (CCM_SIZE == 48)\n assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]);\n else\n assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]);\n\nendmodule // rvrangechecker\n\n// 16 bit even parity generator\nmodule rveven_paritygen #(WIDTH = 16) (\n input logic [WIDTH-1:0] data_in, // Data\n output logic parity_out // generated even parity\n );\n\n assign parity_out = ^(data_in[WIDTH-1:0]) ;\n\nendmodule // rveven_paritygen\n\nmodule rveven_paritycheck #(WIDTH = 16) (\n input logic [WIDTH-1:0] data_in, // Data\n input logic parity_in,\n output logic parity_err // Parity error\n );\n\n assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ;\n\nendmodule // rveven_paritycheck\n\nmodule rvecc_encode (\n input [31:0] din,\n output [6:0] ecc_out\n );\nlogic [5:0] ecc_out_temp;\n\n assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];\n assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];\n assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];\n assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];\n assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];\n assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31];\n\n assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]};\n\nendmodule // rvecc_encode\n\nmodule rvecc_decode (\n input en,\n input [31:0] din,\n input [6:0] ecc_in,\n input sed_ded, // only do detection and no correction. Used for the I$\n output [31:0] dout,\n output [6:0] ecc_out,\n output single_ecc_error,\n output double_ecc_error\n\n );\n\n logic [6:0] ecc_check;\n logic [38:0] error_mask;\n logic [38:0] din_plus_parity, dout_plus_parity;\n\n // Generate the ecc bits\n assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];\n assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];\n assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];\n assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];\n assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];\n assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31];\n\n // This is the parity bit\n assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded;\n\n assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded\n assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE\n\n // Generate the mask for error correctiong\n for (genvar i=1; i<40; i++) begin\n assign error_mask[i-1] = (ecc_check[5:0] == i);\n end\n\n // Generate the corrected data\n assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]};\n\n assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0];\n assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]};\n assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]};\n\nendmodule // rvecc_decode\n\nmodule rvecc_encode_64 (\n input [63:0] din,\n output [6:0] ecc_out\n );\n assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];\n\n assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63];\n\n assign ecc_out[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63];\n\n assign ecc_out[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];\n\n assign ecc_out[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];\n\n assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];\n\n assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63];\n\nendmodule // rvecc_encode_64\n\n\nmodule rvecc_decode_64 (\n input en,\n input [63:0] din,\n input [6:0] ecc_in,\n output ecc_error\n );\n\n logic [6:0] ecc_check;\n\n // Generate the ecc bits\n assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];\n\n assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63];\n\n assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63];\n\n assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];\n\n assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];\n\n assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];\n\n assign ecc_check[6] = ecc_in[6]^din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63];\n\n assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE\n\n endmodule // rvecc_decode_64\n\n`ifndef TECH_SPECIFIC_EC_RV_ICG\nmodule `TEC_RV_ICG\n (\n input logic SE, EN, CK,\n output Q\n );\n\n logic en_ff;\n logic enable;\n\n assign enable = EN | SE;\n\n always @(CK, enable) begin\n if(!CK)\n en_ff = enable;\n end\n assign Q = CK & en_ff;\n\nendmodule\n`endif\n\n`ifndef RV_FPGA_OPTIMIZE\nmodule rvclkhdr\n (\n input logic en,\n input logic clk,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n output logic l1clk\n );\n\n logic SE;\n assign SE = 0;\n\n`ifdef TECH_SPECIFIC_EC_RV_ICG\n `USER_EC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));\n`else\n `TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));\n`endif\n\nendmodule // rvclkhdr\n`endif\n\nmodule rvoclkhdr\n (\n input logic en,\n input logic clk,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n output logic l1clk\n );\n\n logic SE;\n assign SE = 0;\n\n`ifdef RV_FPGA_OPTIMIZE\n assign l1clk = clk;\n`else\n `ifdef TECH_SPECIFIC_EC_RV_ICG\n `USER_EC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));\n `else\n `TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));\n `endif\n`endif\n\nendmodule\n\n\n\n" }, { "path": "design/lib/el2_lib.sv", "content": "module el2_btb_tag_hash\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n ) (\n input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc,\n output logic [pt.BTB_BTAG_SIZE-1:0] hash\n );\n\n assign hash = {(pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+1] ^\n pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^\n pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])};\nendmodule\n\nmodule el2_btb_tag_hash_fold\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc,\n output logic [pt.BTB_BTAG_SIZE-1:0] hash\n );\n\n assign hash = {(\n pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^\n pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])};\n\nendmodule\n\nmodule el2_btb_addr_hash\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc,\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash\n );\n\n\nif(pt.BTB_FOLD2_INDEX_HASH) begin : fold2\n assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^\n pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO];\nend\n else begin\n assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^\n pc[pt.BTB_INDEX2_HI:pt.BTB_INDEX2_LO] ^\n pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO];\nend\n\nendmodule\n\nmodule el2_btb_ghr_hash\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin,\n input logic [pt.BHT_GHR_SIZE-1:0] ghr,\n output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash\n );\n\n // The hash function is too complex to write in verilog for all cases.\n // The config script generates the logic string based on the bp config.\n if(pt.BHT_GHR_HASH_1) begin : ghrhash_cfg1\n assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { ghr[pt.BHT_GHR_SIZE-1:pt.BTB_INDEX1_HI-1], hashin[pt.BTB_INDEX1_HI:2]^ghr[pt.BTB_INDEX1_HI-2:0]};\n end\n else begin : ghrhash_cfg2\n assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { hashin[pt.BHT_GHR_SIZE+1:2]^ghr[pt.BHT_GHR_SIZE-1:0]};\n end\n\n\nendmodule\n" }, { "path": "design/lib/el2_mem_if.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n// Copyright 2022 Microsoft Corporation\n// Copyright (c) 2023 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n\n\ninterface el2_mem_if\nimport el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) ();\n //////////////////////////////////////////\n // Clock\n logic clk;\n\n\n //////////////////////////////////////////\n // ICCM\n logic [pt.ICCM_NUM_BANKS-1:0] iccm_clken;\n logic [pt.ICCM_NUM_BANKS-1:0] iccm_wren_bank;\n logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;\n\n logic [pt.ICCM_NUM_BANKS-1:0][ 31:0] iccm_bank_wr_data;\n logic [pt.ICCM_NUM_BANKS-1:0][ pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc;\n logic [pt.ICCM_NUM_BANKS-1:0][ 31:0] iccm_bank_dout;\n logic [pt.ICCM_NUM_BANKS-1:0][ pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc;\n\n\n //////////////////////////////////////////\n // DCCM\n logic [pt.DCCM_NUM_BANKS-1:0] dccm_clken;\n logic [pt.DCCM_NUM_BANKS-1:0] dccm_wren_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;\n logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_ECC_WIDTH-1:0] dccm_bank_ecc;\n\n //////////////////////////////////////////\n // ICACHE DATA\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] ic_b_sb_wren;\n logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] ic_b_sb_bit_en_vec;\n logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] wb_packeddout_pre;\n logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_sb_wr_data;\n logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final_up;\n logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][71-1:0] wb_dout_pre_up;\n\n //////////////////////////////////////////\n // ICACHE TAG\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_clken_final;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_wren_q;\n logic [(26*pt.ICACHE_NUM_WAYS)-1 :0] ic_tag_wren_biten_vec;\n logic [(26*pt.ICACHE_NUM_WAYS)-1 :0] ic_tag_data_raw_packed_pre;\n logic [25:0] ic_tag_wr_data;\n logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO] ic_rw_addr_q;\n logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] ic_tag_data_raw_pre;\n\n //////////////////////////////////////////\n // MODPORTS\n modport veer_iccm(\n input clk,\n // ICCM\n output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc,\n input iccm_bank_dout, iccm_bank_ecc\n );\n\n modport veer_dccm(\n input clk,\n // DCCM\n output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank,\n input dccm_bank_dout, dccm_bank_ecc\n );\n\n modport veer_sram_src(\n output clk,\n // ICCM\n output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc,\n input iccm_bank_dout, iccm_bank_ecc,\n // DCCM\n output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank,\n input dccm_bank_dout, dccm_bank_ecc\n );\n\n modport veer_sram_sink(\n input clk,\n // ICCM\n input iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc,\n output iccm_bank_dout, iccm_bank_ecc,\n // DCCM\n input dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank,\n output dccm_bank_dout, dccm_bank_ecc\n );\n\n modport veer_icache_data(\n // data\n output ic_b_sb_wren, ic_b_sb_bit_en_vec, ic_sb_wr_data, ic_rw_addr_bank_q, ic_bank_way_clken_final, ic_bank_way_clken_final_up,\n input wb_packeddout_pre, wb_dout_pre_up\n );\n\n modport veer_icache_tag(\n // tag\n output ic_tag_clken_final, ic_tag_wren_q, ic_tag_wren_biten_vec, ic_tag_wr_data, ic_rw_addr_q,\n input ic_tag_data_raw_packed_pre,ic_tag_data_raw_pre\n );\n\n modport veer_icache_src(\n // cache uses the same clk as sram, we do not define clk port in this modport,\n // assuming the clk will be connected in sram_src\n // data\n output ic_b_sb_wren, ic_b_sb_bit_en_vec, ic_sb_wr_data, ic_rw_addr_bank_q, ic_bank_way_clken_final, ic_bank_way_clken_final_up,\n input wb_packeddout_pre, wb_dout_pre_up,\n // tag\n output ic_tag_clken_final, ic_tag_wren_q, ic_tag_wren_biten_vec, ic_tag_wr_data, ic_rw_addr_q,\n input ic_tag_data_raw_packed_pre,ic_tag_data_raw_pre\n );\n\nendinterface\n" }, { "path": "design/lib/el2_regfile_if.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright (c) 2024 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n\n\ninterface el2_regfile_if\nimport el2_pkg::*;\n();\n typedef struct packed {\n // General Purpose Registers\n logic [31:0] ra; // Return address\n logic [31:0] sp; // Stack pointer\n logic [31:0] fp; // Frame pointer\n logic [31:0] a0, a1; // Function arguments 0-1 / Return values 0-1\n logic [31:0] a2, a3, a4, a5, a6, a7; // Function arguments 2-7\n } el2_regfile_gpr_pkt_t;\n\n typedef struct packed {\n // Important registers chosen for exposure\n logic [31:0] pc, npc; // (Next) Program Counter\n logic [31:0] mstatus; // Machine status\n logic [31:0] mie; // Machine interrupt enable\n logic [31:0] mtvec; // Machine trap-handler base address\n logic [31:0] mscratch; // Scratch register for machine trap handlers\n logic [31:0] mepc; // Machine exception program counter\n logic [31:0] mcause; // Machine trap cause\n logic [31:0] mtval; // Machine bad address or instruction\n logic [31:0] mip; // Machine interrupt pending\n logic [31:0] mcyclel; // Machine cycle counter\n logic [31:0] mcycleh; // Machine cycle counter\n logic [31:0] minstretl; // Machine instructions-retired counter\n logic [31:0] minstreth; // Machine instructions-retired counter\n logic [31:0] mrac; // Region access control\n } el2_regfile_tlu_pkt_t;\n\n el2_regfile_gpr_pkt_t gpr;\n el2_regfile_tlu_pkt_t tlu;\n\n modport veer_gpr_rf(output gpr);\n\n modport veer_tlu_rf(output tlu);\n\n modport veer_rf_src(output gpr, output tlu);\n\n modport veer_rf_sink(input gpr, input tlu);\n\nendinterface\n" }, { "path": "design/lib/mem_lib.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or it's affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n`define EL2_LOCAL_RAM_TEST_IO \\\ninput logic WE, \\\ninput logic ME, \\\ninput logic CLK, \\\ninput logic TEST1, \\\ninput logic RME, \\\ninput logic [3:0] RM, \\\ninput logic LS, \\\ninput logic DS, \\\ninput logic SD, \\\ninput logic TEST_RNM, \\\ninput logic BC1, \\\ninput logic BC2, \\\noutput logic ROP\n\n`define EL2_RAM(depth, width) \\\nmodule ram_``depth``x``width( \\\n input logic [$clog2(depth)-1:0] ADR, \\\n input logic [(width-1):0] D, \\\n output logic [(width-1):0] Q, \\\n `EL2_LOCAL_RAM_TEST_IO \\\n); \\\nreg [(width-1):0] ram_core [(depth-1):0]; \\\n`ifdef GTLSIM \\\ninteger i; \\\ninitial begin \\\n for (i=0; i put in the cam\n output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // the tag of the external non block load\n output logic lsu_nonblock_load_inv_r, // invalidate signal for the cam entry for non block loads\n output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated\n output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam\n output logic lsu_nonblock_load_data_error, // non block load has an error\n output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error\n output logic [31:0] lsu_nonblock_load_data, // Data of the non block load\n\n output logic lsu_pmu_load_external_m, // PMU : Bus loads\n output logic lsu_pmu_store_external_m, // PMU : Bus loads\n output logic lsu_pmu_misaligned_m, // PMU : misaligned\n output logic lsu_pmu_bus_trxn, // PMU : bus transaction\n output logic lsu_pmu_bus_misaligned, // PMU : misaligned access going to the bus\n output logic lsu_pmu_bus_error, // PMU : bus sending error back\n output logic lsu_pmu_bus_busy, // PMU : bus is not ready\n\n // Trigger signals\n input el2_trigger_pkt_t [3:0] trigger_pkt_any, // Trigger info from the decode\n output logic [3:0] lsu_trigger_match_m, // lsu trigger hit (one bit per trigger)\n\n // DCCM ports\n output logic dccm_wren, // DCCM write enable\n output logic dccm_rden, // DCCM read enable\n output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, // DCCM write address low bank\n output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, // DCCM write address hi bank\n output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, // DCCM read address low bank\n output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // DCCM write data for lo bank\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // DCCM write data for hi bank\n\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // DCCM read data low bank\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // DCCM read data hi bank\n\n // PIC ports\n output logic picm_wren, // PIC memory write enable\n output logic picm_rden, // PIC memory read enable\n output logic picm_mken, // Need to read the mask for stores to determine which bits to write/forward\n output logic [31:0] picm_rdaddr, // address for pic read access\n output logic [31:0] picm_wraddr, // address for pic write access\n output logic [31:0] picm_wr_data, // PIC memory write data\n input logic [31:0] picm_rd_data, // PIC memory read/mask data\n\n // AXI Write Channels\n output logic lsu_axi_awvalid,\n input logic lsu_axi_awready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,\n output logic [31:0] lsu_axi_awaddr,\n output logic [3:0] lsu_axi_awregion,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_awlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_awsize,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_awburst,\n output logic lsu_axi_awlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_awcache,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_awprot,\n output logic [3:0] lsu_axi_awqos,\n /*pragma coverage on*/\n\n output logic lsu_axi_wvalid,\n input logic lsu_axi_wready,\n output logic [63:0] lsu_axi_wdata,\n output logic [7:0] lsu_axi_wstrb,\n output logic lsu_axi_wlast,\n\n input logic lsu_axi_bvalid,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic lsu_axi_bready,\n /*pragma coverage on*/\n input logic [1:0] lsu_axi_bresp,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,\n\n // AXI Read Channels\n output logic lsu_axi_arvalid,\n input logic lsu_axi_arready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,\n output logic [31:0] lsu_axi_araddr,\n output logic [3:0] lsu_axi_arregion,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_arlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_arsize,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_arburst,\n output logic lsu_axi_arlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_arcache,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_arprot,\n output logic [3:0] lsu_axi_arqos,\n /*pragma coverage on*/\n\n input logic lsu_axi_rvalid,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic lsu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,\n input logic [63:0] lsu_axi_rdata,\n input logic [1:0] lsu_axi_rresp,\n input logic lsu_axi_rlast,\n\n input logic lsu_bus_clk_en, // external drives a clock_en to control bus ratio\n\n // DMA slave\n input logic dma_dccm_req, // DMA read/write to dccm\n input logic [2:0] dma_mem_tag, // DMA request tag\n input logic [31:0] dma_mem_addr, // DMA address\n input logic [2:0] dma_mem_sz, // DMA access size\n input logic dma_mem_write, // DMA access is a write\n input logic [63:0] dma_mem_wdata, // DMA write data\n\n output logic dccm_dma_rvalid, // lsu data valid for DMA dccm read\n output logic dccm_dma_ecc_error, // DMA load had ecc error\n output logic [2:0] dccm_dma_rtag, // DMA request tag\n output logic [63:0] dccm_dma_rdata, // lsu data for DMA dccm read\n output logic dccm_ready, // lsu ready for DMA access\n\n // DCCM ECC status\n output logic lsu_dccm_rd_ecc_single_err,\n output logic lsu_dccm_rd_ecc_double_err,\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // scan mode\n /*pragma coverage on*/\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic rst_l, // reset, active low\n\n output logic [31:0] lsu_pmp_addr_start,\n output logic [31:0] lsu_pmp_addr_end,\n input logic lsu_pmp_error_start,\n input logic lsu_pmp_error_end,\n output logic lsu_pmp_we,\n output logic lsu_pmp_re\n\n );\n\n logic lsu_dccm_rden_m;\n logic lsu_dccm_rden_r;\n logic [31:0] store_data_m;\n logic [31:0] store_data_r;\n logic [31:0] store_data_hi_r, store_data_lo_r;\n logic [31:0] store_datafn_hi_r, store_datafn_lo_r;\n logic [31:0] sec_data_lo_m, sec_data_hi_m;\n logic [31:0] sec_data_lo_r, sec_data_hi_r;\n\n logic [31:0] lsu_ld_data_m;\n logic [31:0] dccm_rdata_hi_m, dccm_rdata_lo_m;\n logic [6:0] dccm_data_ecc_hi_m, dccm_data_ecc_lo_m;\n logic lsu_single_ecc_error_m;\n logic lsu_double_ecc_error_m;\n\n logic [31:0] lsu_ld_data_r;\n logic [31:0] lsu_ld_data_corr_r;\n logic [31:0] dccm_rdata_hi_r, dccm_rdata_lo_r;\n logic [6:0] dccm_data_ecc_hi_r, dccm_data_ecc_lo_r;\n logic single_ecc_error_hi_r, single_ecc_error_lo_r;\n logic lsu_single_ecc_error_r;\n logic lsu_double_ecc_error_r;\n logic ld_single_ecc_error_r, ld_single_ecc_error_r_ff;\n assign lsu_dccm_rd_ecc_single_err = lsu_single_ecc_error_r;\n assign lsu_dccm_rd_ecc_double_err = lsu_double_ecc_error_r;\n\n logic [31:0] picm_mask_data_m;\n\n logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;\n logic [31:0] end_addr_d, end_addr_m, end_addr_r;\n assign lsu_pmp_addr_start = lsu_addr_d;\n assign lsu_pmp_addr_end = end_addr_d;\n\n el2_lsu_pkt_t lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;\n logic lsu_i0_valid_d, lsu_i0_valid_m, lsu_i0_valid_r;\n assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid;\n assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid;\n\n // Store Buffer signals\n logic store_stbuf_reqvld_r;\n logic ldst_stbuf_reqvld_r;\n\n logic lsu_commit_r;\n logic lsu_exc_m;\n\n logic addr_in_dccm_d, addr_in_dccm_m, addr_in_dccm_r;\n logic addr_in_pic_d, addr_in_pic_m, addr_in_pic_r;\n logic ldst_dual_d, ldst_dual_m, ldst_dual_r;\n logic addr_external_m;\n\n logic stbuf_reqvld_any;\n logic stbuf_reqvld_flushed_any;\n logic [pt.LSU_SB_BITS-1:0] stbuf_addr_any;\n logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any;\n logic [pt.DCCM_ECC_WIDTH-1:0] stbuf_ecc_any;\n logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r_ff, sec_data_hi_r_ff;\n logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_hi_r_ff, sec_data_ecc_lo_r_ff;\n\n logic lsu_cmpen_m;\n logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m;\n logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m;\n logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_m;\n logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_m;\n\n logic lsu_stbuf_commit_any;\n logic lsu_stbuf_empty_any; // This is for blocking loads\n logic lsu_stbuf_full_any;\n\n // Bus signals\n logic lsu_busreq_r;\n logic lsu_bus_buffer_pend_any;\n logic lsu_bus_buffer_empty_any;\n logic lsu_bus_buffer_full_any;\n logic lsu_busreq_m;\n logic [31:0] bus_read_data_m;\n\n logic flush_m_up, flush_r;\n logic is_sideeffects_m;\n logic [2:0] dma_mem_tag_d, dma_mem_tag_m;\n logic ldst_nodma_mtor;\n logic dma_dccm_wen, dma_pic_wen;\n logic [31:0] dma_dccm_wdata_lo, dma_dccm_wdata_hi;\n logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, dma_dccm_wdata_ecc_hi;\n\n // Clocks\n logic lsu_busm_clken;\n logic lsu_bus_obuf_c1_clken;\n logic lsu_c1_m_clk, lsu_c1_r_clk;\n logic lsu_c2_m_clk, lsu_c2_r_clk;\n logic lsu_store_c1_m_clk, lsu_store_c1_r_clk;\n\n logic lsu_stbuf_c1_clk;\n logic lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;\n logic lsu_busm_clk;\n logic lsu_free_c2_clk;\n\n logic lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;\n logic lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;\n\n assign lsu_raw_fwd_lo_m = (|stbuf_fwdbyteen_lo_m[pt.DCCM_BYTE_WIDTH-1:0]);\n assign lsu_raw_fwd_hi_m = (|stbuf_fwdbyteen_hi_m[pt.DCCM_BYTE_WIDTH-1:0]);\n\n el2_lsu_lsc_ctl #(.pt(pt)) lsu_lsc_ctl (.*);\n\n // block stores in decode - for either bus or stbuf reasons\n assign lsu_store_stall_any = lsu_stbuf_full_any | lsu_bus_buffer_full_any | ld_single_ecc_error_r_ff;\n assign lsu_load_stall_any = lsu_bus_buffer_full_any | ld_single_ecc_error_r_ff;\n assign lsu_fastint_stall_any = ld_single_ecc_error_r; // Stall the fastint in decode-1 stage\n\n // Ready to accept dma trxns\n // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m\n assign dma_mem_tag_d[2:0] = dma_mem_tag[2:0];\n assign ldst_nodma_mtor = (lsu_pkt_m.valid & ~lsu_pkt_m.dma & (addr_in_dccm_m | addr_in_pic_m) & lsu_pkt_m.store);\n\n assign dccm_ready = ~(dec_lsu_valid_raw_d | ldst_nodma_mtor | ld_single_ecc_error_r_ff);\n\n assign dma_dccm_wen = dma_dccm_req & dma_mem_write & addr_in_dccm_d & dma_mem_sz[1]; // Perform DMA writes only for word/dword\n assign dma_pic_wen = dma_dccm_req & dma_mem_write & addr_in_pic_d;\n assign {dma_dccm_wdata_hi[31:0], dma_dccm_wdata_lo[31:0]} = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores\n\n\n // Generate per cycle flush signals\n assign flush_m_up = dec_tlu_flush_lower_r;\n assign flush_r = dec_tlu_i0_kill_writeb_r;\n\n // lsu idle\n // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence.\n // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error\n // Store buffer now have only non-dma dccm stores\n // stbuf_empty not needed since it has only dccm stores\n assign lsu_idle_any = ~((lsu_pkt_m.valid & ~lsu_pkt_m.dma) |\n (lsu_pkt_r.valid & ~lsu_pkt_r.dma)) &\n lsu_bus_buffer_empty_any;\n\n assign lsu_active = (lsu_pkt_m.valid | lsu_pkt_r.valid | ld_single_ecc_error_r_ff) | ~lsu_bus_buffer_empty_any; // This includes DMA. Used for gating top clock\n\n // Instantiate the store buffer\n assign store_stbuf_reqvld_r = lsu_pkt_r.valid & lsu_pkt_r.store & addr_in_dccm_r & ~flush_r & (~lsu_pkt_r.dma | ((lsu_pkt_r.by | lsu_pkt_r.half) & ~lsu_double_ecc_error_r));\n\n // Disable Forwarding for now\n assign lsu_cmpen_m = lsu_pkt_m.valid & (lsu_pkt_m.load | lsu_pkt_m.store) & (addr_in_dccm_m | addr_in_pic_m);\n\n // Bus signals\n assign lsu_busreq_m = lsu_pkt_m.valid & ((lsu_pkt_m.load | lsu_pkt_m.store) & addr_external_m) & ~flush_m_up & ~lsu_exc_m & ~lsu_pkt_m.fast_int;\n\n // Dual signals\n assign ldst_dual_d = (lsu_addr_d[2] != end_addr_d[2]);\n assign ldst_dual_m = (lsu_addr_m[2] != end_addr_m[2]);\n assign ldst_dual_r = (lsu_addr_r[2] != end_addr_r[2]);\n\n // PMU signals\n assign lsu_pmu_misaligned_m = lsu_pkt_m.valid & ((lsu_pkt_m.half & lsu_addr_m[0]) | (lsu_pkt_m.word & (|lsu_addr_m[1:0])));\n assign lsu_pmu_load_external_m = lsu_pkt_m.valid & lsu_pkt_m.load & addr_external_m;\n assign lsu_pmu_store_external_m = lsu_pkt_m.valid & lsu_pkt_m.store & addr_external_m;\n\n el2_lsu_dccm_ctl #(.pt(pt)) dccm_ctl (\n .lsu_addr_d(lsu_addr_d[31:0]),\n .end_addr_d(end_addr_d[pt.DCCM_BITS-1:0]),\n .lsu_addr_m(lsu_addr_m[pt.DCCM_BITS-1:0]),\n .lsu_addr_r(lsu_addr_r[31:0]),\n\n .end_addr_m(end_addr_m[pt.DCCM_BITS-1:0]),\n .end_addr_r(end_addr_r[pt.DCCM_BITS-1:0]),\n .*\n );\n\n el2_lsu_stbuf #(.pt(pt)) stbuf (\n .lsu_addr_d(lsu_addr_d[pt.LSU_SB_BITS-1:0]),\n .end_addr_d(end_addr_d[pt.LSU_SB_BITS-1:0]),\n\n .*\n\n );\n\n el2_lsu_ecc #(.pt(pt)) ecc (\n .lsu_addr_r(lsu_addr_r[pt.DCCM_BITS-1:0]),\n .end_addr_r(end_addr_r[pt.DCCM_BITS-1:0]),\n .lsu_addr_m(lsu_addr_m[pt.DCCM_BITS-1:0]),\n .end_addr_m(end_addr_m[pt.DCCM_BITS-1:0]),\n .*\n );\n\n el2_lsu_trigger #(.pt(pt)) trigger (\n .store_data_m(store_data_m[31:0]),\n .*\n );\n\n // Clk domain\n el2_lsu_clkdomain #(.pt(pt)) clkdomain (.*);\n\n // Bus interface\n el2_lsu_bus_intf #(.pt(pt)) bus_intf (\n .lsu_addr_m(lsu_addr_m[31:0] & {32{addr_external_m & lsu_pkt_m.valid}}),\n .lsu_addr_r(lsu_addr_r[31:0] & {32{lsu_busreq_r}}),\n\n .end_addr_m(end_addr_m[31:0] & {32{addr_external_m & lsu_pkt_m.valid}}),\n .end_addr_r(end_addr_r[31:0] & {32{lsu_busreq_r}}),\n\n .store_data_r(store_data_r[31:0] & {32{lsu_busreq_r}}),\n .*\n );\n\n //Flops\n rvdff #(3) dma_mem_tag_mff (.*, .din(dma_mem_tag_d[2:0]), .dout(dma_mem_tag_m[2:0]), .clk(lsu_c1_m_clk));\n rvdff #(2) lsu_raw_fwd_r_ff (.*, .din({lsu_raw_fwd_hi_m, lsu_raw_fwd_lo_m}), .dout({lsu_raw_fwd_hi_r, lsu_raw_fwd_lo_r}), .clk(lsu_c2_r_clk));\n\n`ifdef RV_ASSERT_ON\n logic [1:0] store_data_bypass_sel;\n assign store_data_bypass_sel[1:0] = {lsu_p.store_data_bypass_d, lsu_p.store_data_bypass_m};\n\n property exception_no_lsu_flush;\n @(posedge clk) disable iff(~rst_l) lsu_lsc_ctl.lsu_error_pkt_m.exc_valid |-> ##[1:2] (flush_r );\n endproperty\n assert_exception_no_lsu_flush: assert property (exception_no_lsu_flush) else\n $display(\"No flush within 2 cycles of exception\");\n\n // offset should be zero for fast interrupt\n property offset_0_fastint;\n @(posedge clk) disable iff(~rst_l) (lsu_p.valid & lsu_p.fast_int) |-> (dec_lsu_offset_d[11:0] == 12'b0);\n endproperty\n assert_offset_0_fastint: assert property (offset_0_fastint) else\n $display(\"dec_tlu_offset_d not zero for fast interrupt redirect\");\n\n // DMA req should assert dccm rden/wren\n property dmareq_dccm_wren_or_rden;\n @(posedge clk) disable iff(~rst_l) dma_dccm_req |-> (dccm_rden | dccm_wren | addr_in_pic_d);\n endproperty\n assert_dmareq_dccm_wren_or_rden: assert property(dmareq_dccm_wren_or_rden) else\n $display(\"dccm rden or wren not asserted during DMA request\");\n\n // fastint_stall should cause load/store stall next cycle\n property fastint_stall_imply_loadstore_stall;\n @(posedge clk) disable iff(~rst_l) (lsu_fastint_stall_any & (lsu_commit_r | lsu_pkt_r.dma)) |-> ##1 ((lsu_load_stall_any | lsu_store_stall_any) | ~ld_single_ecc_error_r_ff);\n endproperty\n assert_fastint_stall_imply_loadstore_stall: assert property (fastint_stall_imply_loadstore_stall) else\n $display(\"fastint_stall should be followed by lsu_load/store_stall_any\");\n\n // Single ECC error implies rfnpc flush\n property single_ecc_error_rfnpc_flush;\n @(posedge clk) disable iff(~rst_l) (lsu_error_pkt_r.single_ecc_error & lsu_pkt_r.load) |=> ~lsu_commit_r;\n endproperty\n assert_single_ecc_error_rfnpc_flush: assert property (single_ecc_error_rfnpc_flush) else\n $display(\"LSU commit next cycle after single ecc error\");\n\n`endif\n\nendmodule // el2_lsu\n" }, { "path": "design/lsu/el2_lsu_addrcheck.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n//\n// Owner:\n// Function: Checks the memory map for the address\n// Comments:\n//\n//********************************************************************************\nmodule el2_lsu_addrcheck\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input logic lsu_c2_m_clk, // clock\n input logic rst_l, // reset\n\n input logic [31:0] start_addr_d, // start address for lsu\n input logic [31:0] end_addr_d, // end address for lsu\n input el2_lsu_pkt_t lsu_pkt_d, // packet in d\n input logic [31:0] dec_tlu_mrac_ff, // CSR read\n input logic [3:0] rs1_region_d, // address rs operand [31:28]\n\n input logic [31:0] rs1_d, // address rs operand\n\n output logic is_sideeffects_m, // is sideffects space\n output logic addr_in_dccm_d, // address in dccm\n output logic addr_in_pic_d, // address in pic\n output logic addr_external_d, // address in external\n\n output logic access_fault_d, // access fault\n output logic misaligned_fault_d, // misaligned\n output logic [3:0] exc_mscause_d, // mscause for access/misaligned faults\n\n output logic fir_dccm_access_error_d, // Fast interrupt dccm access error\n output logic fir_nondccm_access_error_d,// Fast interrupt dccm access error\n\n input logic lsu_pmp_error_start,\n input logic lsu_pmp_error_end,\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // Scan mode\n /*pragma coverage on*/\n);\n\n\n logic non_dccm_access_ok;\n logic is_sideeffects_d, is_aligned_d;\n logic start_addr_in_dccm_d, end_addr_in_dccm_d;\n logic start_addr_in_dccm_region_d, end_addr_in_dccm_region_d;\n logic start_addr_in_pic_d, end_addr_in_pic_d;\n logic start_addr_in_pic_region_d, end_addr_in_pic_region_d;\n logic [4:0] csr_idx;\n logic addr_in_iccm;\n logic start_addr_dccm_or_pic;\n logic base_reg_dccm_or_pic;\n logic unmapped_access_fault_d, mpu_access_fault_d, picm_access_fault_d, regpred_access_fault_d;\n logic regcross_misaligned_fault_d, sideeffect_misaligned_fault_d;\n logic [3:0] access_fault_mscause_d;\n logic [3:0] misaligned_fault_mscause_d;\n\n if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable\n // Start address check\n rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),\n .CCM_SIZE(pt.DCCM_SIZE)) start_addr_dccm_rangecheck (\n .addr(start_addr_d[31:0]),\n .in_range(start_addr_in_dccm_d),\n .in_region(start_addr_in_dccm_region_d)\n );\n\n // End address check\n rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),\n .CCM_SIZE(pt.DCCM_SIZE)) end_addr_dccm_rangecheck (\n .addr(end_addr_d[31:0]),\n .in_range(end_addr_in_dccm_d),\n .in_region(end_addr_in_dccm_region_d)\n );\n end else begin: Gen_dccm_disable // block: Gen_dccm_enable\n assign start_addr_in_dccm_d = '0;\n assign start_addr_in_dccm_region_d = '0;\n assign end_addr_in_dccm_d = '0;\n assign end_addr_in_dccm_region_d = '0;\n end\n\n if (pt.ICCM_ENABLE == 1) begin : check_iccm\n assign addr_in_iccm = (start_addr_d[31:28] == pt.ICCM_REGION);\n end else begin\n assign addr_in_iccm = 1'b0;\n end\n\n // PIC memory check\n // Start address check\n rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),\n .CCM_SIZE(pt.PIC_SIZE)) start_addr_pic_rangecheck (\n .addr(start_addr_d[31:0]),\n .in_range(start_addr_in_pic_d),\n .in_region(start_addr_in_pic_region_d)\n );\n\n // End address check\n rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),\n .CCM_SIZE(pt.PIC_SIZE)) end_addr_pic_rangecheck (\n .addr(end_addr_d[31:0]),\n .in_range(end_addr_in_pic_d),\n .in_region(end_addr_in_pic_region_d)\n );\n\n assign start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d;\n assign base_reg_dccm_or_pic = (|((rs1_region_d[3:0] == pt.DCCM_REGION) & pt.DCCM_ENABLE)) | (rs1_region_d[3:0] == pt.PIC_REGION);\n assign addr_in_dccm_d = (start_addr_in_dccm_d & end_addr_in_dccm_d);\n assign addr_in_pic_d = (start_addr_in_pic_d & end_addr_in_pic_d);\n\n assign addr_external_d = ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d);\n assign csr_idx[4:0] = {start_addr_d[31:28], 1'b1};\n assign is_sideeffects_d = dec_tlu_mrac_ff[csr_idx] & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & lsu_pkt_d.valid & (lsu_pkt_d.store | lsu_pkt_d.load); //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions\n assign is_aligned_d = (lsu_pkt_d.word & (start_addr_d[1:0] == 2'b0)) |\n (lsu_pkt_d.half & (start_addr_d[0] == 1'b0)) |\n lsu_pkt_d.by;\n\n logic ACCESS0_STARTOK;\n logic ACCESS1_STARTOK;\n logic ACCESS2_STARTOK;\n logic ACCESS3_STARTOK;\n logic ACCESS4_STARTOK;\n logic ACCESS5_STARTOK;\n logic ACCESS6_STARTOK;\n logic ACCESS7_STARTOK;\n logic ACCESS0_ENDOK;\n logic ACCESS1_ENDOK;\n logic ACCESS2_ENDOK;\n logic ACCESS3_ENDOK;\n logic ACCESS4_ENDOK;\n logic ACCESS5_ENDOK;\n logic ACCESS6_ENDOK;\n logic ACCESS7_ENDOK;\n\n assign ACCESS0_STARTOK = pt.DATA_ACCESS_ENABLE0 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK0)) == (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0);\n assign ACCESS1_STARTOK = pt.DATA_ACCESS_ENABLE1 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK1)) == (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1);\n assign ACCESS2_STARTOK = pt.DATA_ACCESS_ENABLE2 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK2)) == (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2);\n assign ACCESS3_STARTOK = pt.DATA_ACCESS_ENABLE3 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK3)) == (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3);\n assign ACCESS4_STARTOK = pt.DATA_ACCESS_ENABLE4 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK4)) == (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4);\n assign ACCESS5_STARTOK = pt.DATA_ACCESS_ENABLE5 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK5)) == (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5);\n assign ACCESS6_STARTOK = pt.DATA_ACCESS_ENABLE6 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK6)) == (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6);\n assign ACCESS7_STARTOK = pt.DATA_ACCESS_ENABLE7 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK7)) == (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7);\n assign ACCESS0_ENDOK = pt.DATA_ACCESS_ENABLE0 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK0)) == (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0);\n assign ACCESS1_ENDOK = pt.DATA_ACCESS_ENABLE1 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK1)) == (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1);\n assign ACCESS2_ENDOK = pt.DATA_ACCESS_ENABLE2 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK2)) == (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2);\n assign ACCESS3_ENDOK = pt.DATA_ACCESS_ENABLE3 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK3)) == (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3);\n assign ACCESS4_ENDOK = pt.DATA_ACCESS_ENABLE4 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK4)) == (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4);\n assign ACCESS5_ENDOK = pt.DATA_ACCESS_ENABLE5 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK5)) == (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5);\n assign ACCESS6_ENDOK = pt.DATA_ACCESS_ENABLE6 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK6)) == (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6);\n assign ACCESS7_ENDOK = pt.DATA_ACCESS_ENABLE7 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK7)) == (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7);\n\n if (pt.PMP_ENTRIES == 0) begin\n assign non_dccm_access_ok = (~(|{pt.DATA_ACCESS_ENABLE0,pt.DATA_ACCESS_ENABLE1,pt.DATA_ACCESS_ENABLE2,pt.DATA_ACCESS_ENABLE3,pt.DATA_ACCESS_ENABLE4,pt.DATA_ACCESS_ENABLE5,pt.DATA_ACCESS_ENABLE6,pt.DATA_ACCESS_ENABLE7})) |\n (( ACCESS0_STARTOK|\n ACCESS1_STARTOK|\n ACCESS2_STARTOK|\n ACCESS3_STARTOK|\n ACCESS4_STARTOK|\n ACCESS5_STARTOK|\n ACCESS6_STARTOK|\n ACCESS7_STARTOK) &\n ( ACCESS0_ENDOK|\n ACCESS1_ENDOK|\n ACCESS2_ENDOK|\n ACCESS3_ENDOK|\n ACCESS4_ENDOK|\n ACCESS5_ENDOK|\n ACCESS6_ENDOK|\n ACCESS7_ENDOK));\n end\n\n // Access fault logic\n // 0. Unmapped local memory : Addr in dccm region but not in dccm offset OR Addr in picm region but not in picm offset OR DCCM -> PIC cross when DCCM/PIC in same region\n // 1. Uncorrectable (double bit) ECC error\n // 3. Address is not in a populated non-dccm region\n // 5. Region predication access fault: Base Address in DCCM/PIC and Final address in non-DCCM/non-PIC region or vice versa\n // 6. Ld/St access to picm are not word aligned or word size\n assign regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic); // 5. Region predication access fault: Base Address in DCCM/PIC and Final address in non-DCCM/non-PIC region or vice versa\n assign picm_access_fault_d = (addr_in_pic_d & ((start_addr_d[1:0] != 2'b0) | ~lsu_pkt_d.word)); // 6. Ld/St access to picm are not word aligned or word size\n\n if (pt.DCCM_ENABLE & (pt.DCCM_REGION == pt.PIC_REGION)) begin\n assign unmapped_access_fault_d = ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) | // 0. Addr in dccm/pic region but not in dccm/pic offset\n (end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d)) | // 0. Addr in dccm/pic region but not in dccm/pic offset\n (start_addr_in_dccm_d & end_addr_in_pic_d) | // 0. DCCM -> PIC cross when DCCM/PIC in same region\n (start_addr_in_pic_d & end_addr_in_dccm_d)); // 0. DCCM -> PIC cross when DCCM/PIC in same region\n if (pt.PMP_ENTRIES > 0) begin\n assign mpu_access_fault_d = (lsu_pmp_error_start | lsu_pmp_error_end); // X. Address is in blocked region\n end else begin\n assign mpu_access_fault_d = (~start_addr_in_dccm_region_d & ~non_dccm_access_ok); // 3. Address is not in a populated non-dccm region\n end\n end else begin\n assign unmapped_access_fault_d = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | // 0. Addr in dccm region but not in dccm offset\n (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d) | // 0. Addr in dccm region but not in dccm offset\n (start_addr_in_pic_region_d & ~start_addr_in_pic_d) | // 0. Addr in picm region but not in picm offset\n (end_addr_in_pic_region_d & ~end_addr_in_pic_d)); // 0. Addr in picm region but not in picm offset\n if (pt.PMP_ENTRIES > 0) begin\n assign mpu_access_fault_d = (lsu_pmp_error_start | lsu_pmp_error_end); // X. Address is in blocked region\n end else begin\n assign mpu_access_fault_d = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok); // 3. Address is not in a populated non-dccm region\n end\n end\n\n assign access_fault_d = (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & lsu_pkt_d.valid & ~lsu_pkt_d.dma;\n assign access_fault_mscause_d[3:0] = unmapped_access_fault_d ? 4'h2 : mpu_access_fault_d ? 4'h3 : regpred_access_fault_d ? 4'h5 : picm_access_fault_d ? 4'h6 : 4'h0;\n\n // Misaligned happens due to 2 reasons\n // 0. Region cross\n // 1. sideeffects access which are not aligned\n assign regcross_misaligned_fault_d = (start_addr_d[31:28] != end_addr_d[31:28]);\n assign sideeffect_misaligned_fault_d = (is_sideeffects_d & ~is_aligned_d);\n assign misaligned_fault_d = (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & addr_external_d)) & lsu_pkt_d.valid & ~lsu_pkt_d.dma;\n assign misaligned_fault_mscause_d[3:0] = regcross_misaligned_fault_d ? 4'h2 : sideeffect_misaligned_fault_d ? 4'h1 : 4'h0;\n\n assign exc_mscause_d[3:0] = misaligned_fault_d ? misaligned_fault_mscause_d[3:0] : access_fault_mscause_d[3:0];\n\n // Fast interrupt error logic\n assign fir_dccm_access_error_d = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) |\n (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & lsu_pkt_d.valid & lsu_pkt_d.fast_int;\n assign fir_nondccm_access_error_d = ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & lsu_pkt_d.valid & lsu_pkt_d.fast_int;\n\n rvdff #(.WIDTH(1)) is_sideeffects_mff (.din(is_sideeffects_d), .dout(is_sideeffects_m), .clk(lsu_c2_m_clk), .*);\n\nendmodule // el2_lsu_addrcheck\n" }, { "path": "design/lsu/el2_lsu_bus_buffer.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n//\n// Owner:\n// Function: lsu interface with interface queue\n// Comments:\n//\n//********************************************************************************\n\nmodule el2_lsu_bus_buffer\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic clk_override, // Override non-functional clock gating\n input logic rst_l, // reset, active low\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // scan mode\n /*pragma coverage on*/\n input logic dec_tlu_external_ldfwd_disable, // disable load to load forwarding for externals\n input logic dec_tlu_wb_coalescing_disable, // disable write buffer coalescing\n input logic dec_tlu_sideeffect_posted_disable, // Don't block the sideeffect load store to the bus\n input logic dec_tlu_force_halt,\n\n // various clocks needed for the bus reads and writes\n input logic lsu_bus_obuf_c1_clken,\n input logic lsu_busm_clken,\n input logic lsu_c2_r_clk,\n input logic lsu_bus_ibuf_c1_clk,\n input logic lsu_bus_obuf_c1_clk,\n input logic lsu_bus_buf_c1_clk,\n input logic lsu_free_c2_clk,\n input logic lsu_busm_clk,\n\n\n input logic dec_lsu_valid_raw_d, // Raw valid for address computation\n input el2_lsu_pkt_t lsu_pkt_m, // lsu packet flowing down the pipe\n input el2_lsu_pkt_t lsu_pkt_r, // lsu packet flowing down the pipe\n\n input logic [31:0] lsu_addr_m, // lsu address flowing down the pipe\n input logic [31:0] end_addr_m, // lsu address flowing down the pipe\n input logic [31:0] lsu_addr_r, // lsu address flowing down the pipe\n input logic [31:0] end_addr_r, // lsu address flowing down the pipe\n input logic [31:0] store_data_r, // store data flowing down the pipe\n\n input logic no_word_merge_r, // r store doesn't need to wait in ibuf since it will not coalesce\n input logic no_dword_merge_r, // r store doesn't need to wait in ibuf since it will not coalesce\n input logic lsu_busreq_m, // bus request is in m\n output logic lsu_busreq_r, // bus request is in r\n input logic ld_full_hit_m, // load can get all its byte from a write buffer entry\n input logic flush_m_up, // flush\n input logic flush_r, // flush\n input logic lsu_commit_r, // lsu instruction in r commits\n input logic is_sideeffects_r, // lsu attribute is side_effects\n input logic ldst_dual_d, // load/store is unaligned at 32 bit boundary\n input logic ldst_dual_m, // load/store is unaligned at 32 bit boundary\n input logic ldst_dual_r, // load/store is unaligned at 32 bit boundary\n\n input logic [7:0] ldst_byteen_ext_m, // HI and LO signals\n\n output logic lsu_bus_buffer_pend_any, // bus buffer has a pending bus entry\n output logic lsu_bus_buffer_full_any, // bus buffer is full\n output logic lsu_bus_buffer_empty_any, // bus buffer is empty\n\n output logic [3:0] ld_byte_hit_buf_lo, ld_byte_hit_buf_hi, // Byte enables for forwarding data\n output logic [31:0] ld_fwddata_buf_lo, ld_fwddata_buf_hi, // load forwarding data\n\n output logic lsu_imprecise_error_load_any, // imprecise load bus error\n output logic lsu_imprecise_error_store_any, // imprecise store bus error\n output logic [31:0] lsu_imprecise_error_addr_any, // address of the imprecise error\n\n // Non-blocking loads\n output logic lsu_nonblock_load_valid_m, // there is an external load -> put in the cam\n output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // the tag of the external non block load\n output logic lsu_nonblock_load_inv_r, // invalidate signal for the cam entry for non block loads\n output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated\n output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam\n output logic lsu_nonblock_load_data_error, // non block load has an error\n output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error\n output logic [31:0] lsu_nonblock_load_data, // Data of the non block load\n\n // PMU events\n output logic lsu_pmu_bus_trxn,\n output logic lsu_pmu_bus_misaligned,\n output logic lsu_pmu_bus_error,\n output logic lsu_pmu_bus_busy,\n\n // AXI Write Channels\n output logic lsu_axi_awvalid,\n input logic lsu_axi_awready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,\n output logic [31:0] lsu_axi_awaddr,\n output logic [3:0] lsu_axi_awregion,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_awlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_awsize,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_awburst,\n output logic lsu_axi_awlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_awcache,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_awprot,\n output logic [3:0] lsu_axi_awqos,\n /*pragma coverage on*/\n\n output logic lsu_axi_wvalid,\n input logic lsu_axi_wready,\n output logic [63:0] lsu_axi_wdata,\n output logic [7:0] lsu_axi_wstrb,\n output logic lsu_axi_wlast,\n\n input logic lsu_axi_bvalid,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic lsu_axi_bready,\n /*pragma coverage on*/\n input logic [1:0] lsu_axi_bresp,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,\n\n // AXI Read Channels\n output logic lsu_axi_arvalid,\n input logic lsu_axi_arready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,\n output logic [31:0] lsu_axi_araddr,\n output logic [3:0] lsu_axi_arregion,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_arlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_arsize,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_arburst,\n output logic lsu_axi_arlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_arcache,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_arprot,\n output logic [3:0] lsu_axi_arqos,\n /*pragma coverage on*/\n\n input logic lsu_axi_rvalid,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic lsu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,\n input logic [63:0] lsu_axi_rdata,\n input logic [1:0] lsu_axi_rresp,\n\n input logic lsu_bus_clk_en,\n input logic lsu_bus_clk_en_q\n\n);\n\n // For Ld: IDLE -> START_WAIT -> CMD -> RESP -> DONE_PARTIAL(?) -> DONE_WAIT(?) -> DONE -> IDLE\n // For St: IDLE -> START_WAIT -> CMD -> RESP(?) -> IDLE\n typedef enum logic [2:0] {IDLE=3'b000, START_WAIT=3'b001, CMD=3'b010, RESP=3'b011, DONE_PARTIAL=3'b100, DONE_WAIT=3'b101, DONE=3'b110} state_t;\n\n localparam DEPTH = pt.LSU_NUM_NBLOAD;\n localparam DEPTH_LOG2 = pt.LSU_NUM_NBLOAD_WIDTH;\n localparam TIMER = 8; // This can be only power of 2\n localparam TIMER_MAX = TIMER - 1; // Maximum value of timer\n localparam TIMER_LOG2 = (TIMER < 2) ? 1 : $clog2(TIMER);\n\n logic [3:0] ldst_byteen_hi_m, ldst_byteen_lo_m;\n logic [DEPTH-1:0] ld_addr_hitvec_lo, ld_addr_hitvec_hi;\n logic [3:0][DEPTH-1:0] ld_byte_hitvec_lo, ld_byte_hitvec_hi;\n logic [3:0][DEPTH-1:0] ld_byte_hitvecfn_lo, ld_byte_hitvecfn_hi;\n\n logic ld_addr_ibuf_hit_lo, ld_addr_ibuf_hit_hi;\n logic [3:0] ld_byte_ibuf_hit_lo, ld_byte_ibuf_hit_hi;\n\n logic [3:0] ldst_byteen_r;\n logic [3:0] ldst_byteen_hi_r, ldst_byteen_lo_r;\n logic [31:0] store_data_hi_r, store_data_lo_r;\n logic is_aligned_r; // Aligned load/store\n logic ldst_samedw_r;\n\n logic lsu_nonblock_load_valid_r;\n logic [31:0] lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;\n logic [1:0] lsu_nonblock_addr_offset;\n logic [1:0] lsu_nonblock_sz;\n logic lsu_nonblock_unsign;\n logic lsu_nonblock_load_data_ready;\n\n logic [DEPTH-1:0] CmdPtr0Dec, CmdPtr1Dec;\n logic [DEPTH-1:0] RspPtrDec;\n logic [DEPTH_LOG2-1:0] CmdPtr0, CmdPtr1;\n logic [DEPTH_LOG2-1:0] RspPtr;\n logic [DEPTH_LOG2-1:0] WrPtr0_m, WrPtr0_r;\n logic [DEPTH_LOG2-1:0] WrPtr1_m, WrPtr1_r;\n logic found_wrptr0, found_wrptr1, found_cmdptr0, found_cmdptr1;\n logic [3:0] buf_numvld_any, buf_numvld_wrcmd_any, buf_numvld_cmd_any, buf_numvld_pend_any;\n logic any_done_wait_state;\n logic bus_sideeffect_pend;\n logic bus_coalescing_disable;\n\n logic bus_addr_match_pending;\n logic bus_cmd_sent, bus_cmd_ready;\n logic bus_wcmd_sent, bus_wdata_sent;\n logic bus_rsp_read, bus_rsp_write;\n logic [pt.LSU_BUS_TAG-1:0] bus_rsp_read_tag, bus_rsp_write_tag;\n logic bus_rsp_read_error, bus_rsp_write_error;\n logic [63:0] bus_rsp_rdata;\n\n // Bus buffer signals\n state_t [DEPTH-1:0] buf_state;\n logic [DEPTH-1:0][1:0] buf_sz;\n logic [DEPTH-1:0][31:0] buf_addr;\n logic [DEPTH-1:0][3:0] buf_byteen;\n logic [DEPTH-1:0] buf_sideeffect;\n logic [DEPTH-1:0] buf_write;\n logic [DEPTH-1:0] buf_unsign;\n logic [DEPTH-1:0] buf_dual;\n logic [DEPTH-1:0] buf_samedw;\n logic [DEPTH-1:0] buf_nomerge;\n logic [DEPTH-1:0] buf_dualhi;\n logic [DEPTH-1:0][DEPTH_LOG2-1:0] buf_dualtag;\n logic [DEPTH-1:0] buf_ldfwd;\n logic [DEPTH-1:0][DEPTH_LOG2-1:0] buf_ldfwdtag;\n logic [DEPTH-1:0] buf_error;\n logic [DEPTH-1:0][31:0] buf_data;\n logic [DEPTH-1:0][DEPTH-1:0] buf_age, buf_age_younger;\n logic [DEPTH-1:0][DEPTH-1:0] buf_rspage, buf_rsp_pickage;\n\n state_t [DEPTH-1:0] buf_nxtstate;\n logic [DEPTH-1:0] buf_rst;\n logic [DEPTH-1:0] buf_state_en;\n logic [DEPTH-1:0] buf_cmd_state_bus_en;\n logic [DEPTH-1:0] buf_resp_state_bus_en;\n logic [DEPTH-1:0] buf_state_bus_en;\n logic [DEPTH-1:0] buf_dual_in;\n logic [DEPTH-1:0] buf_samedw_in;\n logic [DEPTH-1:0] buf_nomerge_in;\n logic [DEPTH-1:0] buf_sideeffect_in;\n logic [DEPTH-1:0] buf_unsign_in;\n logic [DEPTH-1:0][1:0] buf_sz_in;\n logic [DEPTH-1:0] buf_write_in;\n logic [DEPTH-1:0] buf_wr_en;\n logic [DEPTH-1:0] buf_dualhi_in;\n logic [DEPTH-1:0][DEPTH_LOG2-1:0] buf_dualtag_in;\n logic [DEPTH-1:0] buf_ldfwd_en;\n logic [DEPTH-1:0] buf_ldfwd_in;\n logic [DEPTH-1:0][DEPTH_LOG2-1:0] buf_ldfwdtag_in;\n logic [DEPTH-1:0][3:0] buf_byteen_in;\n logic [DEPTH-1:0][31:0] buf_addr_in;\n logic [DEPTH-1:0][31:0] buf_data_in;\n logic [DEPTH-1:0] buf_error_en;\n logic [DEPTH-1:0] buf_data_en;\n logic [DEPTH-1:0][DEPTH-1:0] buf_age_in;\n logic [DEPTH-1:0][DEPTH-1:0] buf_ageQ;\n logic [DEPTH-1:0][DEPTH-1:0] buf_rspage_set;\n logic [DEPTH-1:0][DEPTH-1:0] buf_rspage_in;\n logic [DEPTH-1:0][DEPTH-1:0] buf_rspageQ;\n\n // Input buffer signals\n logic ibuf_valid;\n logic ibuf_dual;\n logic ibuf_samedw;\n logic ibuf_nomerge;\n logic [DEPTH_LOG2-1:0] ibuf_tag;\n logic [DEPTH_LOG2-1:0] ibuf_dualtag;\n logic ibuf_sideeffect;\n logic ibuf_unsign;\n logic ibuf_write;\n logic [1:0] ibuf_sz;\n logic [3:0] ibuf_byteen;\n logic [31:0] ibuf_addr;\n logic [31:0] ibuf_data;\n logic [TIMER_LOG2-1:0] ibuf_timer;\n\n logic ibuf_byp;\n logic ibuf_wr_en;\n logic ibuf_rst;\n logic ibuf_force_drain;\n logic ibuf_drain_vld;\n logic [DEPTH-1:0] ibuf_drainvec_vld;\n logic [DEPTH_LOG2-1:0] ibuf_tag_in;\n logic [DEPTH_LOG2-1:0] ibuf_dualtag_in;\n logic [1:0] ibuf_sz_in;\n logic [31:0] ibuf_addr_in;\n logic [3:0] ibuf_byteen_in;\n logic [31:0] ibuf_data_in;\n logic [TIMER_LOG2-1:0] ibuf_timer_in;\n logic [3:0] ibuf_byteen_out;\n logic [31:0] ibuf_data_out;\n logic ibuf_merge_en, ibuf_merge_in;\n\n // Output buffer signals\n logic obuf_valid;\n logic obuf_write;\n logic obuf_nosend;\n logic obuf_rdrsp_pend;\n logic obuf_sideeffect;\n logic [31:0] obuf_addr;\n logic [63:0] obuf_data;\n logic [1:0] obuf_sz;\n logic [7:0] obuf_byteen;\n logic obuf_merge;\n logic obuf_cmd_done, obuf_data_done;\n logic [pt.LSU_BUS_TAG-1:0] obuf_tag0;\n logic [pt.LSU_BUS_TAG-1:0] obuf_tag1;\n logic [pt.LSU_BUS_TAG-1:0] obuf_rdrsp_tag;\n\n logic ibuf_buf_byp;\n logic obuf_force_wr_en;\n logic obuf_wr_wait;\n logic obuf_wr_en, obuf_wr_enQ;\n logic obuf_rst;\n logic obuf_write_in;\n logic obuf_nosend_in;\n logic obuf_rdrsp_pend_en;\n logic obuf_rdrsp_pend_in;\n logic obuf_sideeffect_in;\n logic obuf_aligned_in;\n logic [31:0] obuf_addr_in;\n logic [63:0] obuf_data_in;\n logic [1:0] obuf_sz_in;\n logic [7:0] obuf_byteen_in;\n logic obuf_merge_in;\n logic obuf_cmd_done_in, obuf_data_done_in;\n logic [pt.LSU_BUS_TAG-1:0] obuf_tag0_in;\n logic [pt.LSU_BUS_TAG-1:0] obuf_tag1_in;\n logic [pt.LSU_BUS_TAG-1:0] obuf_rdrsp_tag_in;\n\n logic obuf_merge_en;\n logic [TIMER_LOG2-1:0] obuf_wr_timer, obuf_wr_timer_in;\n logic [7:0] obuf_byteen0_in, obuf_byteen1_in;\n logic [63:0] obuf_data0_in, obuf_data1_in;\n\n logic lsu_axi_awvalid_q, lsu_axi_awready_q;\n logic lsu_axi_wvalid_q, lsu_axi_wready_q;\n logic lsu_axi_arvalid_q, lsu_axi_arready_q;\n logic lsu_axi_bvalid_q, lsu_axi_bready_q;\n logic lsu_axi_rvalid_q, lsu_axi_rready_q;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_q, lsu_axi_rid_q;\n logic [1:0] lsu_axi_bresp_q, lsu_axi_rresp_q;\n logic [pt.LSU_BUS_TAG-1:0] lsu_imprecise_error_store_tag;\n logic [63:0] lsu_axi_rdata_q;\n\n //------------------------------------------------------------------------------\n // Load forwarding logic start\n //------------------------------------------------------------------------------\n\n // Function to do 8 to 3 bit encoding\n function automatic logic [2:0] f_Enc8to3;\n input logic [7:0] Dec_value;\n\n logic [2:0] Enc_value;\n Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];\n Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];\n Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];\n\n return Enc_value[2:0];\n endfunction // f_Enc8to3\n\n // Buffer hit logic for bus load forwarding\n assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4];\n assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0];\n for (genvar i=0; i 4'b0) & (obuf_wr_timer < TIMER_MAX)) ? (obuf_wr_timer + 1'b1) : obuf_wr_timer);\n assign obuf_force_wr_en = lsu_busreq_m & ~lsu_busreq_r & ~ibuf_valid & (buf_numvld_cmd_any[3:0] == 4'b1) & (lsu_addr_m[31:2] != buf_addr[CmdPtr0][31:2]); // Entry in m can't merge with entry going to obuf and there is no entry in between\n assign ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any[3:0] == 4'b0) & (~lsu_pkt_r.store | no_dword_merge_r);\n\n assign obuf_wr_en = ((ibuf_buf_byp & lsu_commit_r & ~(is_sideeffects_r & bus_sideeffect_pend)) |\n ((buf_state[CmdPtr0] == CMD) & found_cmdptr0 & ~buf_cmd_state_bus_en[CmdPtr0] & ~(buf_sideeffect[CmdPtr0] & bus_sideeffect_pend) &\n (~(buf_dual[CmdPtr0] & buf_samedw[CmdPtr0] & ~buf_write[CmdPtr0]) | found_cmdptr1 | buf_nomerge[CmdPtr0] | obuf_force_wr_en))) &\n (bus_cmd_ready | ~obuf_valid | obuf_nosend) & ~obuf_wr_wait & ~bus_addr_match_pending & lsu_bus_clk_en;\n\n assign obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & ~obuf_wr_en & lsu_bus_clk_en) | dec_tlu_force_halt;\n\n assign obuf_write_in = ibuf_buf_byp ? lsu_pkt_r.store : buf_write[CmdPtr0];\n assign obuf_sideeffect_in = ibuf_buf_byp ? is_sideeffects_r : buf_sideeffect[CmdPtr0];\n assign obuf_addr_in[31:0] = ibuf_buf_byp ? lsu_addr_r[31:0] : buf_addr[CmdPtr0];\n assign obuf_sz_in[1:0] = ibuf_buf_byp ? {lsu_pkt_r.word, lsu_pkt_r.half} : buf_sz[CmdPtr0];\n assign obuf_merge_in = obuf_merge_en;\n assign obuf_tag0_in[pt.LSU_BUS_TAG-1:0] = ibuf_buf_byp ? (pt.LSU_BUS_TAG)'(WrPtr0_r) : (pt.LSU_BUS_TAG)'(CmdPtr0);\n assign obuf_tag1_in[pt.LSU_BUS_TAG-1:0] = ibuf_buf_byp ? (pt.LSU_BUS_TAG)'(WrPtr1_r) : (pt.LSU_BUS_TAG)'(CmdPtr1);\n\n assign obuf_cmd_done_in = ~(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent);\n assign obuf_data_done_in = ~(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent);\n\n assign obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : ((obuf_sz_in[1:0] == 2'b0) |\n (obuf_sz_in[0] & ~obuf_addr_in[0]) |\n (obuf_sz_in[1] & ~(|obuf_addr_in[1:0])));\n\n assign obuf_rdrsp_pend_in = ((~(obuf_wr_en & ~obuf_nosend_in) & obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag))) | (bus_cmd_sent & ~obuf_write)) & ~dec_tlu_force_halt;\n assign obuf_rdrsp_pend_en = lsu_bus_clk_en | dec_tlu_force_halt;\n assign obuf_rdrsp_tag_in[pt.LSU_BUS_TAG-1:0] = (bus_cmd_sent & ~obuf_write) ? obuf_tag0[pt.LSU_BUS_TAG-1:0] : obuf_rdrsp_tag[pt.LSU_BUS_TAG-1:0];\n // No ld to ld fwd for aligned\n assign obuf_nosend_in = (obuf_addr_in[31:3] == obuf_addr[31:3]) & obuf_aligned_in & ~obuf_sideeffect & ~obuf_write & ~obuf_write_in & ~dec_tlu_external_ldfwd_disable &\n ((obuf_valid & ~obuf_nosend) | (obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag))));\n\n assign obuf_byteen0_in[7:0] = ibuf_buf_byp ? (lsu_addr_r[2] ? {ldst_byteen_lo_r[3:0],4'b0} : {4'b0,ldst_byteen_lo_r[3:0]}) :\n (buf_addr[CmdPtr0][2] ? {buf_byteen[CmdPtr0],4'b0} : {4'b0,buf_byteen[CmdPtr0]});\n assign obuf_byteen1_in[7:0] = ibuf_buf_byp ? (end_addr_r[2] ? {ldst_byteen_hi_r[3:0],4'b0} : {4'b0,ldst_byteen_hi_r[3:0]}) :\n (buf_addr[CmdPtr1][2] ? {buf_byteen[CmdPtr1],4'b0} : {4'b0,buf_byteen[CmdPtr1]});\n assign obuf_data0_in[63:0] = ibuf_buf_byp ? (lsu_addr_r[2] ? {store_data_lo_r[31:0],32'b0} : {32'b0,store_data_lo_r[31:0]}) :\n (buf_addr[CmdPtr0][2] ? {buf_data[CmdPtr0],32'b0} : {32'b0,buf_data[CmdPtr0]});\n assign obuf_data1_in[63:0] = ibuf_buf_byp ? (end_addr_r[2] ? {store_data_hi_r[31:0],32'b0} :{32'b0,store_data_hi_r[31:0]}) :\n (buf_addr[CmdPtr1][2] ? {buf_data[CmdPtr1],32'b0} : {32'b0,buf_data[CmdPtr1]});\n\n for (genvar i=0 ;i<8; i++) begin\n assign obuf_byteen_in[i] = obuf_byteen0_in[i] | (obuf_merge_en & obuf_byteen1_in[i]);\n assign obuf_data_in[(8*i)+7:(8*i)] = (obuf_merge_en & obuf_byteen1_in[i]) ? obuf_data1_in[(8*i)+7:(8*i)] : obuf_data0_in[(8*i)+7:(8*i)];\n end\n\n // No store obuf merging for AXI since all stores are sent non-posted. Can't track the second id right now\n assign obuf_merge_en = ((CmdPtr0 != CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (buf_state[CmdPtr0] == CMD) & (buf_state[CmdPtr1] == CMD) &\n ~buf_cmd_state_bus_en[CmdPtr0] & ~buf_sideeffect[CmdPtr0] &\n (~buf_write[CmdPtr0] & buf_dual[CmdPtr0] & ~buf_dualhi[CmdPtr0] & buf_samedw[CmdPtr0])) | // CmdPtr0/CmdPtr1 are for same load which is within a DW\n (ibuf_buf_byp & ldst_samedw_r & ldst_dual_r);\n\n\n rvdff_fpga #(.WIDTH(1)) obuf_wren_ff (.din(obuf_wr_en), .dout(obuf_wr_enQ), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);\n rvdffsc #(.WIDTH(1)) obuf_valid_ff (.din(1'b1), .dout(obuf_valid), .en(obuf_wr_en), .clear(obuf_rst), .clk(lsu_free_c2_clk), .*);\n rvdffs #(.WIDTH(1)) obuf_nosend_ff (.din(obuf_nosend_in), .dout(obuf_nosend), .en(obuf_wr_en), .clk(lsu_free_c2_clk), .*);\n rvdffs #(.WIDTH(1)) obuf_rdrsp_pend_ff(.din(obuf_rdrsp_pend_in), .dout(obuf_rdrsp_pend), .en(obuf_rdrsp_pend_en), .clk(lsu_free_c2_clk), .*);\n rvdff_fpga #(.WIDTH(1)) obuf_cmd_done_ff (.din(obuf_cmd_done_in), .dout(obuf_cmd_done), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(1)) obuf_data_done_ff (.din(obuf_data_done_in), .dout(obuf_data_done), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);\n rvdff_fpga #(.WIDTH(pt.LSU_BUS_TAG)) obuf_rdrsp_tagff (.din(obuf_rdrsp_tag_in), .dout(obuf_rdrsp_tag), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(pt.LSU_BUS_TAG)) obuf_tag0ff (.din(obuf_tag0_in), .dout(obuf_tag0), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(pt.LSU_BUS_TAG)) obuf_tag1ff (.din(obuf_tag1_in), .dout(obuf_tag1), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(1)) obuf_mergeff (.din(obuf_merge_in), .dout(obuf_merge), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(1)) obuf_writeff (.din(obuf_write_in), .dout(obuf_write), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(1)) obuf_sideeffectff (.din(obuf_sideeffect_in), .dout(obuf_sideeffect), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(2)) obuf_szff (.din(obuf_sz_in[1:0]), .dout(obuf_sz), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);\n rvdffs_fpga #(.WIDTH(8)) obuf_byteenff (.din(obuf_byteen_in[7:0]), .dout(obuf_byteen), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);\n rvdffe #(.WIDTH(32)) obuf_addrff (.din(obuf_addr_in[31:0]), .dout(obuf_addr), .en(obuf_wr_en), .*);\n rvdffe #(.WIDTH(64)) obuf_dataff (.din(obuf_data_in[63:0]), .dout(obuf_data), .en(obuf_wr_en), .*);\n rvdff_fpga #(.WIDTH(TIMER_LOG2)) obuf_timerff (.din(obuf_wr_timer_in), .dout(obuf_wr_timer), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);\n\n\n //------------------------------------------------------------------------------\n // Output buffer logic ends here\n //------------------------------------------------------------------------------\n\n // Find the entry to allocate and entry to send\n always_comb begin\n WrPtr0_m[DEPTH_LOG2-1:0] = '0;\n WrPtr1_m[DEPTH_LOG2-1:0] = '0;\n found_wrptr0 = '0;\n found_wrptr1 = '0;\n\n // Find first write pointer\n for (int i=0; i= (DEPTH-1)) : (buf_numvld_any[3:0] == DEPTH);\n assign lsu_bus_buffer_empty_any = ~(|buf_state[DEPTH-1:0]) & ~ibuf_valid & ~obuf_valid;\n\n\n // Non blocking ports\n assign lsu_nonblock_load_valid_m = lsu_busreq_m & lsu_pkt_m.valid & lsu_pkt_m.load & ~flush_m_up & ~ld_full_hit_m;\n assign lsu_nonblock_load_tag_m[DEPTH_LOG2-1:0] = WrPtr0_m[DEPTH_LOG2-1:0];\n assign lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & ~lsu_commit_r;\n assign lsu_nonblock_load_inv_tag_r[DEPTH_LOG2-1:0] = WrPtr0_r[DEPTH_LOG2-1:0]; // r tag needs to be accurate even if there is no invalidate\n\n always_comb begin\n lsu_nonblock_load_data_ready = '0;\n lsu_nonblock_load_data_error = '0;\n lsu_nonblock_load_data_tag[DEPTH_LOG2-1:0] = '0;\n lsu_nonblock_load_data_lo[31:0] = '0;\n lsu_nonblock_load_data_hi[31:0] = '0;\n for (int i=0; i> 8*lsu_nonblock_addr_offset[1:0]);\n\n assign lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & ~lsu_nonblock_load_data_error;\n assign lsu_nonblock_load_data[31:0] = ({32{ lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b00)}} & {24'b0,lsu_nonblock_data_unalgn[7:0]}) |\n ({32{ lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b01)}} & {16'b0,lsu_nonblock_data_unalgn[15:0]}) |\n ({32{~lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b00)}} & {{24{lsu_nonblock_data_unalgn[7]}}, lsu_nonblock_data_unalgn[7:0]}) |\n ({32{~lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b01)}} & {{16{lsu_nonblock_data_unalgn[15]}},lsu_nonblock_data_unalgn[15:0]}) |\n ({32{(lsu_nonblock_sz[1:0] == 2'b10)}} & lsu_nonblock_data_unalgn[31:0]);\n\n // Determine if there is a pending return to sideeffect load/store\n always_comb begin\n bus_sideeffect_pend = obuf_valid & obuf_sideeffect & dec_tlu_sideeffect_posted_disable;\n for (int i=0; i put in the cam\n output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // the tag of the external non block load\n output logic lsu_nonblock_load_inv_r, // invalidate signal for the cam entry for non block loads\n output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated\n output logic lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam\n output logic lsu_nonblock_load_data_error,// non block load has an error\n output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error\n output logic [31:0] lsu_nonblock_load_data, // Data of the non block load\n\n // PMU events\n output logic lsu_pmu_bus_trxn,\n output logic lsu_pmu_bus_misaligned,\n output logic lsu_pmu_bus_error,\n output logic lsu_pmu_bus_busy,\n\n // AXI Write Channels\n output logic lsu_axi_awvalid,\n input logic lsu_axi_awready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,\n output logic [31:0] lsu_axi_awaddr,\n output logic [3:0] lsu_axi_awregion,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_awlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_awsize,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_awburst,\n output logic lsu_axi_awlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_awcache,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_awprot,\n output logic [3:0] lsu_axi_awqos,\n /*pragma coverage on*/\n\n output logic lsu_axi_wvalid,\n input logic lsu_axi_wready,\n output logic [63:0] lsu_axi_wdata,\n output logic [7:0] lsu_axi_wstrb,\n output logic lsu_axi_wlast,\n\n input logic lsu_axi_bvalid,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic lsu_axi_bready,\n /*pragma coverage on*/\n input logic [1:0] lsu_axi_bresp,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,\n\n // AXI Read Channels\n output logic lsu_axi_arvalid,\n input logic lsu_axi_arready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,\n output logic [31:0] lsu_axi_araddr,\n output logic [3:0] lsu_axi_arregion,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [7:0] lsu_axi_arlen,\n /*pragma coverage on*/\n output logic [2:0] lsu_axi_arsize,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [1:0] lsu_axi_arburst,\n output logic lsu_axi_arlock,\n /*pragma coverage on*/\n output logic [3:0] lsu_axi_arcache,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic [2:0] lsu_axi_arprot,\n output logic [3:0] lsu_axi_arqos,\n /*pragma coverage on*/\n\n input logic lsu_axi_rvalid,\n /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */\n /*pragma coverage off*/\n output logic lsu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,\n input logic [63:0] lsu_axi_rdata,\n input logic [1:0] lsu_axi_rresp,\n\n input logic lsu_bus_clk_en\n\n);\n\n\n\n logic lsu_bus_clk_en_q;\n\n logic [3:0] ldst_byteen_m, ldst_byteen_r;\n logic [7:0] ldst_byteen_ext_m, ldst_byteen_ext_r;\n logic [3:0] ldst_byteen_hi_m, ldst_byteen_hi_r;\n logic [3:0] ldst_byteen_lo_m, ldst_byteen_lo_r;\n logic is_sideeffects_r;\n\n logic [63:0] store_data_ext_r;\n logic [31:0] store_data_hi_r;\n logic [31:0] store_data_lo_r;\n\n logic addr_match_dw_lo_r_m;\n logic addr_match_word_lo_r_m;\n logic no_word_merge_r, no_dword_merge_r;\n\n logic ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;\n logic [3:0] ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;\n\n logic [3:0] ld_byte_hit_lo, ld_byte_rhit_lo;\n logic [3:0] ld_byte_hit_hi, ld_byte_rhit_hi;\n\n logic [31:0] ld_fwddata_rpipe_lo;\n logic [31:0] ld_fwddata_rpipe_hi;\n\n logic [3:0] ld_byte_hit_buf_lo, ld_byte_hit_buf_hi;\n logic [31:0] ld_fwddata_buf_lo, ld_fwddata_buf_hi;\n\n logic [63:0] ld_fwddata_lo, ld_fwddata_hi;\n logic [63:0] ld_fwddata_m;\n\n logic ld_full_hit_hi_m, ld_full_hit_lo_m;\n logic ld_full_hit_m;\n\n assign ldst_byteen_m[3:0] = ({4{lsu_pkt_m.by}} & 4'b0001) |\n ({4{lsu_pkt_m.half}} & 4'b0011) |\n ({4{lsu_pkt_m.word}} & 4'b1111);\n\n // Read/Write Buffer\n el2_lsu_bus_buffer #(.pt(pt)) bus_buffer (\n .*\n );\n\n // Logic to determine if dc5 store can be coalesced or not with younger stores. Bypass ibuf if cannot colaesced\n assign addr_match_dw_lo_r_m = (lsu_addr_r[31:3] == lsu_addr_m[31:3]);\n assign addr_match_word_lo_r_m = addr_match_dw_lo_r_m & ~(lsu_addr_r[2]^lsu_addr_m[2]);\n\n assign no_word_merge_r = lsu_busreq_r & ~ldst_dual_r & lsu_busreq_m & (lsu_pkt_m.load | ~addr_match_word_lo_r_m);\n assign no_dword_merge_r = lsu_busreq_r & ~ldst_dual_r & lsu_busreq_m & (lsu_pkt_m.load | ~addr_match_dw_lo_r_m);\n\n // Create Hi/Lo signals\n assign ldst_byteen_ext_m[7:0] = {4'b0,ldst_byteen_m[3:0]} << lsu_addr_m[1:0];\n assign ldst_byteen_ext_r[7:0] = {4'b0,ldst_byteen_r[3:0]} << lsu_addr_r[1:0];\n\n assign store_data_ext_r[63:0] = {32'b0,store_data_r[31:0]} << {lsu_addr_r[1:0],3'b0};\n\n assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4];\n assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0];\n assign ldst_byteen_hi_r[3:0] = ldst_byteen_ext_r[7:4];\n assign ldst_byteen_lo_r[3:0] = ldst_byteen_ext_r[3:0];\n\n assign store_data_hi_r[31:0] = store_data_ext_r[63:32];\n assign store_data_lo_r[31:0] = store_data_ext_r[31:0];\n\n assign ld_addr_rhit_lo_lo = (lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;\n assign ld_addr_rhit_lo_hi = (end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;\n assign ld_addr_rhit_hi_lo = (lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;\n assign ld_addr_rhit_hi_hi = (end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;\n\n for (genvar i=0; i<4; i++) begin: GenBusBufFwd\n assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i] & ldst_byteen_lo_m[i];\n assign ld_byte_rhit_lo_hi[i] = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i] & ldst_byteen_hi_m[i];\n assign ld_byte_rhit_hi_lo[i] = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i] & ldst_byteen_lo_m[i];\n assign ld_byte_rhit_hi_hi[i] = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[i] & ldst_byteen_hi_m[i];\n\n assign ld_byte_hit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i] |\n ld_byte_hit_buf_lo[i];\n\n assign ld_byte_hit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i] |\n ld_byte_hit_buf_hi[i];\n\n assign ld_byte_rhit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i];\n assign ld_byte_rhit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i];\n\n assign ld_fwddata_rpipe_lo[(8*i)+7:(8*i)] = ({8{ld_byte_rhit_lo_lo[i]}} & store_data_lo_r[(8*i)+7:(8*i)]) |\n ({8{ld_byte_rhit_hi_lo[i]}} & store_data_hi_r[(8*i)+7:(8*i)]);\n\n assign ld_fwddata_rpipe_hi[(8*i)+7:(8*i)] = ({8{ld_byte_rhit_lo_hi[i]}} & store_data_lo_r[(8*i)+7:(8*i)]) |\n ({8{ld_byte_rhit_hi_hi[i]}} & store_data_hi_r[(8*i)+7:(8*i)]);\n\n // Final muxing between m/r\n assign ld_fwddata_lo[(8*i)+7:(8*i)] = ld_byte_rhit_lo[i] ? ld_fwddata_rpipe_lo[(8*i)+7:(8*i)] : ld_fwddata_buf_lo[(8*i)+7:(8*i)];\n\n assign ld_fwddata_hi[(8*i)+7:(8*i)] = ld_byte_rhit_hi[i] ? ld_fwddata_rpipe_hi[(8*i)+7:(8*i)] : ld_fwddata_buf_hi[(8*i)+7:(8*i)];\n\n end\n\n always_comb begin\n ld_full_hit_lo_m = 1'b1;\n ld_full_hit_hi_m = 1'b1;\n for (int i=0; i<4; i++) begin\n ld_full_hit_lo_m &= (ld_byte_hit_lo[i] | ~ldst_byteen_lo_m[i]);\n ld_full_hit_hi_m &= (ld_byte_hit_hi[i] | ~ldst_byteen_hi_m[i]);\n end\n end\n\n // This will be high if all the bytes of load hit the stores in pipe/write buffer (m/r/wrbuf)\n assign ld_full_hit_m = ld_full_hit_lo_m & ld_full_hit_hi_m & lsu_busreq_m & lsu_pkt_m.load & ~is_sideeffects_m;\n\n assign ld_fwddata_m[63:0] = 64'({ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0]));\n assign bus_read_data_m[31:0] = ld_fwddata_m[31:0];\n\n // Fifo flops\n\n rvdff #(.WIDTH(1)) clken_ff (.din(lsu_bus_clk_en), .dout(lsu_bus_clk_en_q), .clk(active_clk), .*);\n\n rvdff #(.WIDTH(1)) is_sideeffects_rff (.din(is_sideeffects_m), .dout(is_sideeffects_r), .clk(lsu_c1_r_clk), .*);\n\n rvdff #(4) lsu_byten_rff (.*, .din(ldst_byteen_m[3:0]), .dout(ldst_byteen_r[3:0]), .clk(lsu_c1_r_clk));\n\n`ifdef RV_ASSERT_ON\n\n // Assertion to check AXI write address is aligned to size\n property lsu_axi_awaddr_aligned;\n @(posedge lsu_busm_clk) disable iff(~rst_l) lsu_axi_awvalid |-> ((lsu_axi_awsize[2:0] == 3'h0) |\n ((lsu_axi_awsize[2:0] == 3'h1) & (lsu_axi_awaddr[0] == 1'b0)) |\n ((lsu_axi_awsize[2:0] == 3'h2) & (lsu_axi_awaddr[1:0] == 2'b0)) |\n ((lsu_axi_awsize[2:0] == 3'h3) & (lsu_axi_awaddr[2:0] == 3'b0)));\n endproperty\n assert_lsu_axi_awaddr_aligned: assert property (lsu_axi_awaddr_aligned) else\n $display(\"Assertion lsu_axi_awaddr_aligned failed: lsu_axi_awvalid=1'b%b, lsu_axi_awsize=3'h%h, lsu_axi_awaddr=32'h%h\",lsu_axi_awvalid, lsu_axi_awsize[2:0], lsu_axi_awaddr[31:0]);\n // Assertion to check awvalid stays stable during entire bus clock\n\n // Assertion to check AXI read address is aligned to size\n property lsu_axi_araddr_aligned;\n @(posedge lsu_busm_clk) disable iff(~rst_l) lsu_axi_arvalid |-> ((lsu_axi_arsize[2:0] == 3'h0) |\n ((lsu_axi_arsize[2:0] == 3'h1) & (lsu_axi_araddr[0] == 1'b0)) |\n ((lsu_axi_arsize[2:0] == 3'h2) & (lsu_axi_araddr[1:0] == 2'b0)) |\n ((lsu_axi_arsize[2:0] == 3'h3) & (lsu_axi_araddr[2:0] == 3'b0)));\n endproperty\n assert_lsu_axi_araddr_aligned: assert property (lsu_axi_araddr_aligned) else\n $display(\"Assertion lsu_axi_araddr_aligned failed: lsu_axi_awvalid=1'b%b, lsu_axi_awsize=3'h%h, lsu_axi_araddr=32'h%h\",lsu_axi_awvalid, lsu_axi_awsize[2:0], lsu_axi_araddr[31:0]);\n\n // Assertion to check awvalid stays stable during entire bus clock\n property lsu_axi_awvalid_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid != $past(lsu_axi_awvalid)) |-> ($past(lsu_bus_clk_en) | dec_tlu_force_halt);\n endproperty\n assert_lsu_axi_awvalid_stable: assert property (lsu_axi_awvalid_stable) else\n $display(\"LSU AXI awvalid changed in middle of bus clock\");\n\n // Assertion to check awid stays stable during entire bus clock\n property lsu_axi_awid_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awid[pt.LSU_BUS_TAG-1:0] != $past(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]))) |-> $past(lsu_bus_clk_en);\n endproperty\n assert_lsu_axi_awid_stable: assert property (lsu_axi_awid_stable) else\n $display(\"LSU AXI awid changed in middle of bus clock\");\n\n // Assertion to check awaddr stays stable during entire bus clock\n property lsu_axi_awaddr_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awaddr[31:0] != $past(lsu_axi_awaddr[31:0]))) |-> $past(lsu_bus_clk_en);\n endproperty\n assert_lsu_axi_awaddr_stable: assert property (lsu_axi_awaddr_stable) else\n $display(\"LSU AXI awaddr changed in middle of bus clock\");\n\n // Assertion to check awsize stays stable during entire bus clock\n property lsu_axi_awsize_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awsize[2:0] != $past(lsu_axi_awsize[2:0]))) |-> $past(lsu_bus_clk_en);\n endproperty\n assert_lsu_axi_awsize_stable: assert property (lsu_axi_awsize_stable) else\n $display(\"LSU AXI awsize changed in middle of bus clock\");\n\n // Assertion to check wstrb stays stable during entire bus clock\n property lsu_axi_wstrb_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_wvalid & (lsu_axi_wstrb[7:0] != $past(lsu_axi_wstrb[7:0]))) |-> $past(lsu_bus_clk_en);\n endproperty\n assert_lsu_axi_wstrb_stable: assert property (lsu_axi_wstrb_stable) else\n $display(\"LSU AXI wstrb changed in middle of bus clock\");\n\n // Assertion to check wdata stays stable during entire bus clock\n property lsu_axi_wdata_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_wvalid & (lsu_axi_wdata[63:0] != $past(lsu_axi_wdata[63:0]))) |-> $past(lsu_bus_clk_en);\n endproperty\n assert_lsu_axi_wdata_stable: assert property (lsu_axi_wdata_stable) else\n $display(\"LSU AXI wdata changed in middle of bus clock\");\n\n // Assertion to check awvalid stays stable during entire bus clock\n property lsu_axi_arvalid_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid != $past(lsu_axi_arvalid)) |-> ($past(lsu_bus_clk_en) | dec_tlu_force_halt);\n endproperty\n assert_lsu_axi_arvalid_stable: assert property (lsu_axi_arvalid_stable) else\n $display(\"LSU AXI awvalid changed in middle of bus clock\");\n\n // Assertion to check awid stays stable during entire bus clock\n property lsu_axi_arid_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid & (lsu_axi_arid[pt.LSU_BUS_TAG-1:0] != $past(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]))) |-> $past(lsu_bus_clk_en);\n endproperty\n assert_lsu_axi_arid_stable: assert property (lsu_axi_arid_stable) else\n $display(\"LSU AXI awid changed in middle of bus clock\");\n\n // Assertion to check awaddr stays stable during entire bus clock\n property lsu_axi_araddr_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid & (lsu_axi_araddr[31:0] != $past(lsu_axi_araddr[31:0]))) |-> $past(lsu_bus_clk_en);\n endproperty\n assert_lsu_axi_araddr_stable: assert property (lsu_axi_araddr_stable) else\n $display(\"LSU AXI awaddr changed in middle of bus clock\");\n\n // Assertion to check awsize stays stable during entire bus clock\n property lsu_axi_arsize_stable;\n @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_arsize[2:0] != $past(lsu_axi_arsize[2:0]))) |-> $past(lsu_bus_clk_en);\n endproperty\n assert_lsu_axi_arsize_stable: assert property (lsu_axi_arsize_stable) else\n $display(\"LSU AXI awsize changed in middle of bus clock\");\n\n`endif\n\nendmodule // el2_lsu_bus_intf\n" }, { "path": "design/lsu/el2_lsu_clkdomain.sv", "content": "// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n//\n// Owner:\n// Function: Clock Generation Block\n// Comments: All the clocks are generate here\n//\n// //********************************************************************************\n\n\nmodule el2_lsu_clkdomain\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n)(\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic rst_l, // reset, active low\n input logic dec_tlu_force_halt, // This will be high till TLU goes to debug halt\n\n // Inputs\n input logic clk_override, // chciken bit to turn off clock gating\n input logic dma_dccm_req, // dma is active\n input logic ldst_stbuf_reqvld_r, // allocating in to the store queue\n\n input logic stbuf_reqvld_any, // stbuf is draining\n input logic stbuf_reqvld_flushed_any, // instruction going to stbuf is flushed\n input logic lsu_busreq_r, // busreq in r\n input logic lsu_bus_buffer_pend_any, // bus buffer has a pending bus entry\n input logic lsu_bus_buffer_empty_any, // external bus buffer is empty\n input logic lsu_stbuf_empty_any, // stbuf is empty\n\n input logic lsu_bus_clk_en, // bus clock enable\n\n input el2_lsu_pkt_t lsu_p, // lsu packet in decode\n input el2_lsu_pkt_t lsu_pkt_d, // lsu packet in d\n input el2_lsu_pkt_t lsu_pkt_m, // lsu packet in m\n input el2_lsu_pkt_t lsu_pkt_r, // lsu packet in r\n\n // Outputs\n output logic lsu_bus_obuf_c1_clken, // obuf clock enable\n output logic lsu_busm_clken, // bus clock enable\n\n output logic lsu_c1_m_clk, // m pipe single pulse clock\n output logic lsu_c1_r_clk, // r pipe single pulse clock\n\n output logic lsu_c2_m_clk, // m pipe double pulse clock\n output logic lsu_c2_r_clk, // r pipe double pulse clock\n\n output logic lsu_store_c1_m_clk, // store in m\n output logic lsu_store_c1_r_clk, // store in r\n\n output logic lsu_stbuf_c1_clk,\n output logic lsu_bus_obuf_c1_clk, // ibuf clock\n output logic lsu_bus_ibuf_c1_clk, // ibuf clock\n output logic lsu_bus_buf_c1_clk, // ibuf clock\n output logic lsu_busm_clk, // bus clock\n\n output logic lsu_free_c2_clk, // free double pulse clock\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // Scan mode\n /*pragma coverage on*/\n);\n\n logic lsu_c1_m_clken, lsu_c1_r_clken;\n logic lsu_c2_m_clken, lsu_c2_r_clken;\n logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;\n logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;\n\n\n logic lsu_stbuf_c1_clken;\n logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;\n\n logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;\n\n //-------------------------------------------------------------------------------------------\n // Clock Enable logic\n //-------------------------------------------------------------------------------------------\n\n assign lsu_c1_m_clken = lsu_p.valid | dma_dccm_req | clk_override;\n assign lsu_c1_r_clken = lsu_pkt_m.valid | lsu_c1_m_clken_q | clk_override;\n\n assign lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | clk_override;\n assign lsu_c2_r_clken = lsu_c1_r_clken | lsu_c1_r_clken_q | clk_override;\n\n assign lsu_store_c1_m_clken = ((lsu_c1_m_clken & lsu_pkt_d.store) | clk_override) ;\n assign lsu_store_c1_r_clken = ((lsu_c1_r_clken & lsu_pkt_m.store) | clk_override) ;\n\n assign lsu_stbuf_c1_clken = ldst_stbuf_reqvld_r | stbuf_reqvld_any | stbuf_reqvld_flushed_any | clk_override;\n assign lsu_bus_ibuf_c1_clken = lsu_busreq_r | clk_override;\n assign lsu_bus_obuf_c1_clken = (lsu_bus_buffer_pend_any | lsu_busreq_r | clk_override) & lsu_bus_clk_en;\n assign lsu_bus_buf_c1_clken = ~lsu_bus_buffer_empty_any | lsu_busreq_r | dec_tlu_force_halt | clk_override;\n\n assign lsu_free_c1_clken = (lsu_p.valid | lsu_pkt_d.valid | lsu_pkt_m.valid | lsu_pkt_r.valid) |\n ~lsu_bus_buffer_empty_any | ~lsu_stbuf_empty_any | clk_override;\n assign lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | clk_override;\n\n // Flops\n rvdff #(1) lsu_free_c1_clkenff (.din(lsu_free_c1_clken), .dout(lsu_free_c1_clken_q), .clk(active_clk), .*);\n\n rvdff #(1) lsu_c1_m_clkenff (.din(lsu_c1_m_clken), .dout(lsu_c1_m_clken_q), .clk(lsu_free_c2_clk), .*);\n rvdff #(1) lsu_c1_r_clkenff (.din(lsu_c1_r_clken), .dout(lsu_c1_r_clken_q), .clk(lsu_free_c2_clk), .*);\n\n // Clock Headers\n rvoclkhdr lsu_c1m_cgc ( .en(lsu_c1_m_clken), .l1clk(lsu_c1_m_clk), .* );\n rvoclkhdr lsu_c1r_cgc ( .en(lsu_c1_r_clken), .l1clk(lsu_c1_r_clk), .* );\n\n rvoclkhdr lsu_c2m_cgc ( .en(lsu_c2_m_clken), .l1clk(lsu_c2_m_clk), .* );\n rvoclkhdr lsu_c2r_cgc ( .en(lsu_c2_r_clken), .l1clk(lsu_c2_r_clk), .* );\n\n rvoclkhdr lsu_store_c1m_cgc (.en(lsu_store_c1_m_clken), .l1clk(lsu_store_c1_m_clk), .*);\n rvoclkhdr lsu_store_c1r_cgc (.en(lsu_store_c1_r_clken), .l1clk(lsu_store_c1_r_clk), .*);\n\n rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), .l1clk(lsu_stbuf_c1_clk), .* );\n rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), .l1clk(lsu_bus_ibuf_c1_clk), .* );\n rvoclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken), .l1clk(lsu_bus_buf_c1_clk), .* );\n\n assign lsu_busm_clken = (~lsu_bus_buffer_empty_any | lsu_busreq_r | clk_override) & lsu_bus_clk_en;\n\n`ifdef RV_FPGA_OPTIMIZE\n assign lsu_busm_clk = 1'b0;\n assign lsu_bus_obuf_c1_clk = 1'b0;\n`else\n rvclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), .l1clk(lsu_bus_obuf_c1_clk), .* );\n rvclkhdr lsu_busm_cgc (.en(lsu_busm_clken), .l1clk(lsu_busm_clk), .*);\n`endif\n\n rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), .l1clk(lsu_free_c2_clk), .*);\n\nendmodule\n\n" }, { "path": "design/lsu/el2_lsu_dccm_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n//\n// Owner:\n// Function: DCCM for LSU pipe\n// Comments: Single ported memory\n//\n//\n// DC1 -> DC2 -> DC3 -> DC4 (Commit)\n//\n// //********************************************************************************\n\nmodule el2_lsu_dccm_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic lsu_c2_m_clk, // clocks\n input logic lsu_c2_r_clk, // clocks\n input logic lsu_c1_r_clk, // clocks\n input logic lsu_store_c1_r_clk, // clocks\n input logic lsu_free_c2_clk, // clocks\n input logic clk_override, // Override non-functional clock gating\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n\n input logic rst_l, // reset, active low\n\n input el2_lsu_pkt_t lsu_pkt_r,// lsu packets\n input el2_lsu_pkt_t lsu_pkt_m,// lsu packets\n input el2_lsu_pkt_t lsu_pkt_d,// lsu packets\n input logic addr_in_dccm_d, // address maps to dccm\n input logic addr_in_pic_d, // address maps to pic\n input logic addr_in_pic_m, // address maps to pic\n input logic addr_in_dccm_m, addr_in_dccm_r, // address in dccm per pipe stage\n input logic addr_in_pic_r, // address in pic per pipe stage\n input logic lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r,\n input logic lsu_commit_r, // lsu instruction in r commits\n input logic ldst_dual_m, ldst_dual_r,// load/store is unaligned at 32 bit boundary per pipe stage\n\n // lsu address down the pipe\n input logic [31:0] lsu_addr_d,\n input logic [pt.DCCM_BITS-1:0] lsu_addr_m,\n input logic [31:0] lsu_addr_r,\n\n // lsu address down the pipe - needed to check unaligned\n input logic [pt.DCCM_BITS-1:0] end_addr_d,\n input logic [pt.DCCM_BITS-1:0] end_addr_m,\n input logic [pt.DCCM_BITS-1:0] end_addr_r,\n\n\n input logic stbuf_reqvld_any, // write enable\n input logic [pt.LSU_SB_BITS-1:0] stbuf_addr_any, // stbuf address (aligned)\n\n input logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any, // the read out from stbuf\n input logic [pt.DCCM_ECC_WIDTH-1:0] stbuf_ecc_any, // the encoded data with ECC bits\n input logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m, // stbuf fowarding to load\n input logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m, // stbuf fowarding to load\n input logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_m, // stbuf fowarding to load\n input logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_m, // stbuf fowarding to load\n\n output logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r, // data from the dccm\n output logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r, // data from the dccm\n output logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_r, // data from the dccm + ecc\n output logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_r,\n output logic [pt.DCCM_DATA_WIDTH-1:0] lsu_ld_data_r, // right justified, ie load byte will have data at 7:0\n output logic [pt.DCCM_DATA_WIDTH-1:0] lsu_ld_data_corr_r, // right justified & ECC corrected, ie load byte will have data at 7:0\n\n input logic lsu_double_ecc_error_r, // lsu has a DED\n input logic single_ecc_error_hi_r, // sec detected on hi dccm bank\n input logic single_ecc_error_lo_r, // sec detected on lower dccm bank\n input logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_r, // corrected dccm data\n input logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r, // corrected dccm data\n input logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_r_ff, // corrected dccm data\n input logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r_ff, // corrected dccm data\n input logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_hi_r_ff, // the encoded data with ECC bits\n input logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_lo_r_ff, // the encoded data with ECC bits\n\n output logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m, // data from the dccm\n output logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m, // data from the dccm\n output logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_m, // data from the dccm + ecc\n output logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_m,\n output logic [pt.DCCM_DATA_WIDTH-1:0] lsu_ld_data_m, // right justified, ie load byte will have data at 7:0\n\n input logic lsu_double_ecc_error_m, // lsu has a DED\n input logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_m, // corrected dccm data\n input logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_m, // corrected dccm data\n\n input logic [31:0] store_data_m, // Store data M-stage\n input logic dma_dccm_wen, // Perform DMA writes only for word/dword\n input logic dma_pic_wen, // Perform PIC writes\n input logic [2:0] dma_mem_tag_m, // DMA Buffer entry number M-stage\n input logic [31:0] dma_mem_addr, // DMA request address\n input logic [63:0] dma_mem_wdata, // DMA write data\n input logic [31:0] dma_dccm_wdata_lo, // Shift the dma data to lower bits to make it consistent to lsu stores\n input logic [31:0] dma_dccm_wdata_hi, // Shift the dma data to lower bits to make it consistent to lsu stores\n input logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_hi, // ECC bits for the DMA wdata\n input logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, // ECC bits for the DMA wdata\n\n output logic [pt.DCCM_DATA_WIDTH-1:0] store_data_hi_r,\n output logic [pt.DCCM_DATA_WIDTH-1:0] store_data_lo_r,\n output logic [pt.DCCM_DATA_WIDTH-1:0] store_datafn_hi_r, // data from the dccm\n output logic [pt.DCCM_DATA_WIDTH-1:0] store_datafn_lo_r, // data from the dccm\n output logic [31:0] store_data_r, // raw store data to be sent to bus\n output logic ld_single_ecc_error_r,\n output logic ld_single_ecc_error_r_ff,\n\n output logic [31:0] picm_mask_data_m, // pic data to stbuf\n output logic lsu_stbuf_commit_any, // stbuf wins the dccm port or is to pic\n output logic lsu_dccm_rden_m, // dccm read\n output logic lsu_dccm_rden_r, // dccm read\n\n output logic dccm_dma_rvalid, // dccm serviving the dma load\n output logic dccm_dma_ecc_error, // DMA load had ecc error\n output logic [2:0] dccm_dma_rtag, // DMA return tag\n output logic [63:0] dccm_dma_rdata, // dccm data to dma request\n\n // DCCM ports\n output logic dccm_wren, // dccm interface -- write\n output logic dccm_rden, // dccm interface -- write\n output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, // dccm interface -- wr addr for lo bank\n output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, // dccm interface -- wr addr for hi bank\n output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, // dccm interface -- read address for lo bank\n output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, // dccm interface -- read address for hi bank\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // dccm write data for lo bank\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // dccm write data for hi bank\n\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // dccm read data back from the dccm\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // dccm read data back from the dccm\n\n // PIC ports\n output logic picm_wren, // write to pic\n output logic picm_rden, // read to pick\n output logic picm_mken, // write to pic need a mask\n output logic [31:0] picm_rdaddr, // address for pic read access\n output logic [31:0] picm_wraddr, // address for pic write access\n output logic [31:0] picm_wr_data, // write data\n input logic [31:0] picm_rd_data, // read data\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // scan mode\n /*pragma coverage on*/\n);\n\n\n localparam DCCM_WIDTH_BITS = $clog2(pt.DCCM_BYTE_WIDTH);\n\n logic lsu_dccm_rden_d, lsu_dccm_wren_d;\n logic ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r;\n logic ld_single_ecc_error_lo_r_ns, ld_single_ecc_error_hi_r_ns;\n logic ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff;\n logic lsu_double_ecc_error_r_ff;\n logic [pt.DCCM_BITS-1:0] ld_sec_addr_lo_r_ff, ld_sec_addr_hi_r_ff;\n logic [pt.DCCM_DATA_WIDTH-1:0] store_data_lo_r_in, store_data_hi_r_in ;\n logic [63:0] picm_rd_data_m;\n\n logic dccm_wr_bypass_d_m_hi, dccm_wr_bypass_d_r_hi;\n logic dccm_wr_bypass_d_m_lo, dccm_wr_bypass_d_r_lo;\n logic kill_ecc_corr_lo_r, kill_ecc_corr_hi_r;\n\n // byte_en flowing down\n logic [3:0] store_byteen_m ,store_byteen_r;\n logic [7:0] store_byteen_ext_m, store_byteen_ext_r;\n\n if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1\n logic [63:0] lsu_rdata_r, lsu_rdata_corr_r;\n logic [63:0] dccm_rdata_r, dccm_rdata_corr_r;\n logic [63:0] stbuf_fwddata_r;\n logic [7:0] stbuf_fwdbyteen_r;\n logic [31:0] stbuf_fwddata_lo_r, stbuf_fwddata_hi_r;\n logic [3:0] stbuf_fwdbyteen_lo_r, stbuf_fwdbyteen_hi_r;\n logic [31:0] lsu_rdata_lo_r, lsu_rdata_hi_r;\n logic [63:0] picm_rd_data_r;\n logic [63:32] lsu_ld_data_r_nc, lsu_ld_data_corr_r_nc;\n logic [2:0] dma_mem_tag_r;\n logic stbuf_fwddata_en;\n\n assign dccm_dma_rvalid = lsu_pkt_r.valid & lsu_pkt_r.load & lsu_pkt_r.dma;\n assign dccm_dma_ecc_error = lsu_double_ecc_error_r;\n assign dccm_dma_rtag[2:0] = dma_mem_tag_r[2:0];\n assign dccm_dma_rdata[63:0] = ldst_dual_r ? lsu_rdata_corr_r[63:0] : {2{lsu_rdata_corr_r[31:0]}};\n assign {lsu_ld_data_r_nc[63:32], lsu_ld_data_r[31:0]} = lsu_rdata_r[63:0] >> 8*lsu_addr_r[1:0];\n assign {lsu_ld_data_corr_r_nc[63:32], lsu_ld_data_corr_r[31:0]} = lsu_rdata_corr_r[63:0] >> 8*lsu_addr_r[1:0];\n\n assign picm_rd_data_r[63:32] = picm_rd_data_r[31:0];\n assign dccm_rdata_r[63:0] = {dccm_rdata_hi_r[31:0],dccm_rdata_lo_r[31:0]};\n assign dccm_rdata_corr_r[63:0] = {sec_data_hi_r[31:0],sec_data_lo_r[31:0]};\n assign stbuf_fwddata_r[63:0] = {stbuf_fwddata_hi_r[31:0], stbuf_fwddata_lo_r[31:0]};\n assign stbuf_fwdbyteen_r[7:0] = {stbuf_fwdbyteen_hi_r[3:0], stbuf_fwdbyteen_lo_r[3:0]};\n assign stbuf_fwddata_en = (|stbuf_fwdbyteen_hi_m[3:0]) | (|stbuf_fwdbyteen_lo_m[3:0]) | clk_override;\n\n for (genvar i=0; i<8; i++) begin: GenDMAData\n assign lsu_rdata_corr_r[(8*i)+7:8*i] = stbuf_fwdbyteen_r[i] ? stbuf_fwddata_r[(8*i)+7:8*i] :\n (addr_in_pic_r ? picm_rd_data_r[(8*i)+7:8*i] : ({8{addr_in_dccm_r}} & dccm_rdata_corr_r[(8*i)+7:8*i]));\n\n assign lsu_rdata_r[(8*i)+7:8*i] = stbuf_fwdbyteen_r[i] ? stbuf_fwddata_r[(8*i)+7:8*i] :\n (addr_in_pic_r ? picm_rd_data_r[(8*i)+7:8*i] : ({8{addr_in_dccm_r}} & dccm_rdata_r[(8*i)+7:8*i]));\n end\n rvdffe #(pt.DCCM_DATA_WIDTH) dccm_rdata_hi_r_ff (.*, .din(dccm_rdata_hi_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(dccm_rdata_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .en((lsu_dccm_rden_m & ldst_dual_m) | clk_override));\n rvdffe #(pt.DCCM_DATA_WIDTH) dccm_rdata_lo_r_ff (.*, .din(dccm_rdata_lo_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(dccm_rdata_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .en(lsu_dccm_rden_m | clk_override));\n rvdffe #(2*pt.DCCM_ECC_WIDTH) dccm_data_ecc_r_ff (.*, .din({dccm_data_ecc_hi_m[pt.DCCM_ECC_WIDTH-1:0], dccm_data_ecc_lo_m[pt.DCCM_ECC_WIDTH-1:0]}),\n .dout({dccm_data_ecc_hi_r[pt.DCCM_ECC_WIDTH-1:0], dccm_data_ecc_lo_r[pt.DCCM_ECC_WIDTH-1:0]}), .en(lsu_dccm_rden_m | clk_override));\n rvdff #(8) stbuf_fwdbyteen_ff (.*, .din({stbuf_fwdbyteen_hi_m[3:0], stbuf_fwdbyteen_lo_m[3:0]}), .dout({stbuf_fwdbyteen_hi_r[3:0], stbuf_fwdbyteen_lo_r[3:0]}), .clk(lsu_c2_r_clk));\n rvdffe #(64) stbuf_fwddata_ff (.*, .din({stbuf_fwddata_hi_m[31:0], stbuf_fwddata_lo_m[31:0]}), .dout({stbuf_fwddata_hi_r[31:0], stbuf_fwddata_lo_r[31:0]}), .en(stbuf_fwddata_en));\n rvdffe #(32) picm_rddata_rff (.*, .din(picm_rd_data_m[31:0]), .dout(picm_rd_data_r[31:0]), .en(addr_in_pic_m | clk_override));\n rvdff #(3) dma_mem_tag_rff (.*, .din(dma_mem_tag_m[2:0]), .dout(dma_mem_tag_r[2:0]), .clk(lsu_c1_r_clk));\n\n end else begin: L2U_Plus1_0\n\n logic [63:0] lsu_rdata_m, lsu_rdata_corr_m;\n logic [63:0] dccm_rdata_m, dccm_rdata_corr_m;\n logic [63:0] stbuf_fwddata_m;\n logic [7:0] stbuf_fwdbyteen_m;\n logic [63:32] lsu_ld_data_m_nc, lsu_ld_data_corr_m_nc;\n logic [31:0] lsu_ld_data_corr_m;\n\n assign lsu_ld_data_r = '0;\n assign dccm_rdata_lo_r = '0;\n assign dccm_rdata_hi_r = '0;\n assign dccm_data_ecc_lo_r = '0;\n assign dccm_data_ecc_hi_r = '0;\n\n assign dccm_dma_rvalid = lsu_pkt_m.valid & lsu_pkt_m.load & lsu_pkt_m.dma;\n assign dccm_dma_ecc_error = lsu_double_ecc_error_m;\n assign dccm_dma_rtag[2:0] = dma_mem_tag_m[2:0];\n assign dccm_dma_rdata[63:0] = ldst_dual_m ? lsu_rdata_corr_m[63:0] : {2{lsu_rdata_corr_m[31:0]}};\n assign {lsu_ld_data_m_nc[63:32], lsu_ld_data_m[31:0]} = 64'(lsu_rdata_m[63:0] >> 8*lsu_addr_m[1:0]);\n assign {lsu_ld_data_corr_m_nc[63:32], lsu_ld_data_corr_m[31:0]} = 64'(lsu_rdata_corr_m[63:0] >> 8*lsu_addr_m[1:0]);\n\n assign dccm_rdata_m[63:0] = {dccm_rdata_hi_m[31:0],dccm_rdata_lo_m[31:0]};\n assign dccm_rdata_corr_m[63:0] = {sec_data_hi_m[31:0],sec_data_lo_m[31:0]};\n assign stbuf_fwddata_m[63:0] = {stbuf_fwddata_hi_m[31:0], stbuf_fwddata_lo_m[31:0]};\n assign stbuf_fwdbyteen_m[7:0] = {stbuf_fwdbyteen_hi_m[3:0], stbuf_fwdbyteen_lo_m[3:0]};\n\n for (genvar i=0; i<8; i++) begin: GenLoop\n assign lsu_rdata_corr_m[(8*i)+7:8*i] = stbuf_fwdbyteen_m[i] ? stbuf_fwddata_m[(8*i)+7:8*i] :\n (addr_in_pic_m ? picm_rd_data_m[(8*i)+7:8*i] : ({8{addr_in_dccm_m}} & dccm_rdata_corr_m[(8*i)+7:8*i]));\n\n assign lsu_rdata_m[(8*i)+7:8*i] = stbuf_fwdbyteen_m[i] ? stbuf_fwddata_m[(8*i)+7:8*i] :\n (addr_in_pic_m ? picm_rd_data_m[(8*i)+7:8*i] : ({8{addr_in_dccm_m}} & dccm_rdata_m[(8*i)+7:8*i]));\n end\n\n rvdffe #(32) lsu_ld_data_corr_rff(.*, .din(lsu_ld_data_corr_m[31:0]), .dout(lsu_ld_data_corr_r[31:0]), .en((lsu_pkt_m.valid & lsu_pkt_m.load & (addr_in_pic_m | addr_in_dccm_m)) | clk_override));\n end\n\n assign kill_ecc_corr_lo_r = (((lsu_addr_d[pt.DCCM_BITS-1:2] == lsu_addr_r[pt.DCCM_BITS-1:2]) | (end_addr_d[pt.DCCM_BITS-1:2] == lsu_addr_r[pt.DCCM_BITS-1:2])) & lsu_pkt_d.valid & lsu_pkt_d.store & lsu_pkt_d.dma & addr_in_dccm_d) |\n (((lsu_addr_m[pt.DCCM_BITS-1:2] == lsu_addr_r[pt.DCCM_BITS-1:2]) | (end_addr_m[pt.DCCM_BITS-1:2] == lsu_addr_r[pt.DCCM_BITS-1:2])) & lsu_pkt_m.valid & lsu_pkt_m.store & lsu_pkt_m.dma & addr_in_dccm_m);\n\n assign kill_ecc_corr_hi_r = (((lsu_addr_d[pt.DCCM_BITS-1:2] == end_addr_r[pt.DCCM_BITS-1:2]) | (end_addr_d[pt.DCCM_BITS-1:2] == end_addr_r[pt.DCCM_BITS-1:2])) & lsu_pkt_d.valid & lsu_pkt_d.store & lsu_pkt_d.dma & addr_in_dccm_d) |\n (((lsu_addr_m[pt.DCCM_BITS-1:2] == end_addr_r[pt.DCCM_BITS-1:2]) | (end_addr_m[pt.DCCM_BITS-1:2] == end_addr_r[pt.DCCM_BITS-1:2])) & lsu_pkt_m.valid & lsu_pkt_m.store & lsu_pkt_m.dma & addr_in_dccm_m);\n\n assign ld_single_ecc_error_lo_r = lsu_pkt_r.load & single_ecc_error_lo_r & ~lsu_raw_fwd_lo_r;\n assign ld_single_ecc_error_hi_r = lsu_pkt_r.load & single_ecc_error_hi_r & ~lsu_raw_fwd_hi_r;\n assign ld_single_ecc_error_r = (ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r) & ~lsu_double_ecc_error_r;\n\n assign ld_single_ecc_error_lo_r_ns = ld_single_ecc_error_lo_r & (lsu_commit_r | lsu_pkt_r.dma) & ~kill_ecc_corr_lo_r;\n assign ld_single_ecc_error_hi_r_ns = ld_single_ecc_error_hi_r & (lsu_commit_r | lsu_pkt_r.dma) & ~kill_ecc_corr_hi_r;\n assign ld_single_ecc_error_r_ff = (ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff) & ~lsu_double_ecc_error_r_ff;\n\n assign lsu_stbuf_commit_any = stbuf_reqvld_any &\n (~(lsu_dccm_rden_d | lsu_dccm_wren_d | ld_single_ecc_error_r_ff) |\n (lsu_dccm_rden_d & ~((stbuf_addr_any[pt.DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS] == lsu_addr_d[pt.DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]) |\n (stbuf_addr_any[pt.DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS] == end_addr_d[pt.DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]))));\n\n // No need to read for aligned word/dword stores since ECC will come by new data completely\n assign lsu_dccm_rden_d = lsu_pkt_d.valid & (lsu_pkt_d.load | (lsu_pkt_d.store & (~(lsu_pkt_d.word | lsu_pkt_d.dword) | (lsu_addr_d[1:0] != 2'b0)))) & addr_in_dccm_d;\n\n // DMA will read/write in decode stage\n assign lsu_dccm_wren_d = dma_dccm_wen;\n\n // DCCM inputs\n assign dccm_wren = lsu_dccm_wren_d | lsu_stbuf_commit_any | ld_single_ecc_error_r_ff;\n assign dccm_rden = lsu_dccm_rden_d & addr_in_dccm_d;\n assign dccm_wr_addr_lo[pt.DCCM_BITS-1:0] = ld_single_ecc_error_r_ff ? (ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff[pt.DCCM_BITS-1:0] : ld_sec_addr_hi_r_ff[pt.DCCM_BITS-1:0]) :\n lsu_dccm_wren_d ? lsu_addr_d[pt.DCCM_BITS-1:0] : stbuf_addr_any[pt.DCCM_BITS-1:0];\n assign dccm_wr_addr_hi[pt.DCCM_BITS-1:0] = ld_single_ecc_error_r_ff ? (ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff[pt.DCCM_BITS-1:0] : ld_sec_addr_lo_r_ff[pt.DCCM_BITS-1:0]) :\n lsu_dccm_wren_d ? end_addr_d[pt.DCCM_BITS-1:0] : stbuf_addr_any[pt.DCCM_BITS-1:0];\n assign dccm_rd_addr_lo[pt.DCCM_BITS-1:0] = lsu_addr_d[pt.DCCM_BITS-1:0];\n assign dccm_rd_addr_hi[pt.DCCM_BITS-1:0] = end_addr_d[pt.DCCM_BITS-1:0];\n assign dccm_wr_data_lo[pt.DCCM_FDATA_WIDTH-1:0] = ld_single_ecc_error_r_ff ? (ld_single_ecc_error_lo_r_ff ? {sec_data_ecc_lo_r_ff[pt.DCCM_ECC_WIDTH-1:0],sec_data_lo_r_ff[pt.DCCM_DATA_WIDTH-1:0]} :\n {sec_data_ecc_hi_r_ff[pt.DCCM_ECC_WIDTH-1:0],sec_data_hi_r_ff[pt.DCCM_DATA_WIDTH-1:0]}) :\n (dma_dccm_wen ? {dma_dccm_wdata_ecc_lo[pt.DCCM_ECC_WIDTH-1:0],dma_dccm_wdata_lo[pt.DCCM_DATA_WIDTH-1:0]} :\n {stbuf_ecc_any[pt.DCCM_ECC_WIDTH-1:0],stbuf_data_any[pt.DCCM_DATA_WIDTH-1:0]});\n assign dccm_wr_data_hi[pt.DCCM_FDATA_WIDTH-1:0] = ld_single_ecc_error_r_ff ? (ld_single_ecc_error_hi_r_ff ? {sec_data_ecc_hi_r_ff[pt.DCCM_ECC_WIDTH-1:0],sec_data_hi_r_ff[pt.DCCM_DATA_WIDTH-1:0]} :\n {sec_data_ecc_lo_r_ff[pt.DCCM_ECC_WIDTH-1:0],sec_data_lo_r_ff[pt.DCCM_DATA_WIDTH-1:0]}) :\n (dma_dccm_wen ? {dma_dccm_wdata_ecc_hi[pt.DCCM_ECC_WIDTH-1:0],dma_dccm_wdata_hi[pt.DCCM_DATA_WIDTH-1:0]} :\n {stbuf_ecc_any[pt.DCCM_ECC_WIDTH-1:0],stbuf_data_any[pt.DCCM_DATA_WIDTH-1:0]});\n\n // DCCM outputs\n assign store_byteen_m[3:0] = {4{lsu_pkt_m.store}} &\n (({4{lsu_pkt_m.by}} & 4'b0001) |\n ({4{lsu_pkt_m.half}} & 4'b0011) |\n ({4{lsu_pkt_m.word}} & 4'b1111));\n\n assign store_byteen_r[3:0] = {4{lsu_pkt_r.store}} &\n (({4{lsu_pkt_r.by}} & 4'b0001) |\n ({4{lsu_pkt_r.half}} & 4'b0011) |\n ({4{lsu_pkt_r.word}} & 4'b1111));\n\n assign store_byteen_ext_m[7:0] = {4'b0,store_byteen_m[3:0]} << lsu_addr_m[1:0]; // The packet in m\n assign store_byteen_ext_r[7:0] = {4'b0,store_byteen_r[3:0]} << lsu_addr_r[1:0];\n\n\n\n assign dccm_wr_bypass_d_m_lo = (stbuf_addr_any[pt.DCCM_BITS-1:2] == lsu_addr_m[pt.DCCM_BITS-1:2]) & addr_in_dccm_m;\n assign dccm_wr_bypass_d_m_hi = (stbuf_addr_any[pt.DCCM_BITS-1:2] == end_addr_m[pt.DCCM_BITS-1:2]) & addr_in_dccm_m;\n\n assign dccm_wr_bypass_d_r_lo = (stbuf_addr_any[pt.DCCM_BITS-1:2] == lsu_addr_r[pt.DCCM_BITS-1:2]) & addr_in_dccm_r;\n assign dccm_wr_bypass_d_r_hi = (stbuf_addr_any[pt.DCCM_BITS-1:2] == end_addr_r[pt.DCCM_BITS-1:2]) & addr_in_dccm_r;\n\n\n if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U1_Plus1_1\n logic dccm_wren_Q;\n logic [31:0] dccm_wr_data_Q;\n logic dccm_wr_bypass_d_m_lo_Q, dccm_wr_bypass_d_m_hi_Q;\n logic [31:0] store_data_pre_hi_r, store_data_pre_lo_r;\n\n assign {store_data_pre_hi_r[31:0], store_data_pre_lo_r[31:0]} = {32'b0,store_data_r[31:0]} << 8*lsu_addr_r[1:0];\n\n for (genvar i=0; i<4; i++) begin\n assign store_data_lo_r[(8*i)+7:(8*i)] = store_byteen_ext_r[i] ? store_data_pre_lo_r[(8*i)+7:(8*i)] : ((dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q) ? dccm_wr_data_Q[(8*i)+7:(8*i)] : sec_data_lo_r[(8*i)+7:(8*i)]);\n assign store_data_hi_r[(8*i)+7:(8*i)] = store_byteen_ext_r[i+4] ? store_data_pre_hi_r[(8*i)+7:(8*i)] : ((dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q) ? dccm_wr_data_Q[(8*i)+7:(8*i)] : sec_data_hi_r[(8*i)+7:(8*i)]);\n\n assign store_datafn_lo_r[(8*i)+7:(8*i)] = store_byteen_ext_r[i] ? store_data_pre_lo_r[(8*i)+7:(8*i)] : ((lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo) ? stbuf_data_any[(8*i)+7:(8*i)] :\n ((dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q) ? dccm_wr_data_Q[(8*i)+7:(8*i)] : sec_data_lo_r[(8*i)+7:(8*i)]));\n assign store_datafn_hi_r[(8*i)+7:(8*i)] = store_byteen_ext_r[i+4] ? store_data_pre_hi_r[(8*i)+7:(8*i)] : ((lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi) ? stbuf_data_any[(8*i)+7:(8*i)] :\n ((dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q) ? dccm_wr_data_Q[(8*i)+7:(8*i)] : sec_data_hi_r[(8*i)+7:(8*i)]));\n end\n\n rvdff #(1) dccm_wren_ff (.*, .din(lsu_stbuf_commit_any), .dout(dccm_wren_Q), .clk(lsu_free_c2_clk)); // ECC load errors writing to dccm shouldn't fwd to stores in pipe\n rvdffe #(32) dccm_wrdata_ff (.*, .din(stbuf_data_any[31:0]), .dout(dccm_wr_data_Q[31:0]), .en(lsu_stbuf_commit_any | clk_override), .clk(clk));\n rvdff #(1) dccm_wrbyp_dm_loff (.*, .din(dccm_wr_bypass_d_m_lo), .dout(dccm_wr_bypass_d_m_lo_Q), .clk(lsu_free_c2_clk));\n rvdff #(1) dccm_wrbyp_dm_hiff (.*, .din(dccm_wr_bypass_d_m_hi), .dout(dccm_wr_bypass_d_m_hi_Q), .clk(lsu_free_c2_clk));\n rvdff #(32) store_data_rff (.*, .din(store_data_m[31:0]), .dout(store_data_r[31:0]), .clk(lsu_store_c1_r_clk));\n\n end else begin: L2U1_Plus1_0\n\n logic [31:0] store_data_hi_m, store_data_lo_m;\n logic [63:0] store_data_mask;\n assign {store_data_hi_m[31:0] , store_data_lo_m[31:0]} = {32'b0,store_data_m[31:0]} << 8*lsu_addr_m[1:0];\n\n for (genvar i=0; i<4; i++) begin\n assign store_data_hi_r_in[(8*i)+7:(8*i)] = store_byteen_ext_m[i+4] ? store_data_hi_m[(8*i)+7:(8*i)] :\n ((lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi) ? stbuf_data_any[(8*i)+7:(8*i)] : sec_data_hi_m[(8*i)+7:(8*i)]);\n assign store_data_lo_r_in[(8*i)+7:(8*i)] = store_byteen_ext_m[i] ? store_data_lo_m[(8*i)+7:(8*i)] :\n ((lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo) ? stbuf_data_any[(8*i)+7:(8*i)] : sec_data_lo_m[(8*i)+7:(8*i)]);\n\n assign store_datafn_lo_r[(8*i)+7:(8*i)] = (lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & ~store_byteen_ext_r[i]) ? stbuf_data_any[(8*i)+7:(8*i)] : store_data_lo_r[(8*i)+7:(8*i)];\n assign store_datafn_hi_r[(8*i)+7:(8*i)] = (lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi & ~store_byteen_ext_r[i+4]) ? stbuf_data_any[(8*i)+7:(8*i)] : store_data_hi_r[(8*i)+7:(8*i)];\n end // for (genvar i=0; i> 8*lsu_addr_r[1:0]) & store_data_mask[31:0];\n\n rvdffe #(pt.DCCM_DATA_WIDTH) store_data_hi_rff (.*, .din(store_data_hi_r_in[pt.DCCM_DATA_WIDTH-1:0]), .dout(store_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .en((ldst_dual_m & lsu_pkt_m.valid & lsu_pkt_m.store) | clk_override), .clk(clk));\n rvdff #(pt.DCCM_DATA_WIDTH) store_data_lo_rff (.*, .din(store_data_lo_r_in[pt.DCCM_DATA_WIDTH-1:0]), .dout(store_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .clk(lsu_store_c1_r_clk));\n\n end\n\n assign dccm_rdata_lo_m[pt.DCCM_DATA_WIDTH-1:0] = dccm_rd_data_lo[pt.DCCM_DATA_WIDTH-1:0]; // for ld choose dccm_out\n assign dccm_rdata_hi_m[pt.DCCM_DATA_WIDTH-1:0] = dccm_rd_data_hi[pt.DCCM_DATA_WIDTH-1:0]; // for ld this is used for ecc\n\n assign dccm_data_ecc_lo_m[pt.DCCM_ECC_WIDTH-1:0] = dccm_rd_data_lo[pt.DCCM_FDATA_WIDTH-1:pt.DCCM_DATA_WIDTH];\n assign dccm_data_ecc_hi_m[pt.DCCM_ECC_WIDTH-1:0] = dccm_rd_data_hi[pt.DCCM_FDATA_WIDTH-1:pt.DCCM_DATA_WIDTH];\n\n // PIC signals. PIC ignores the lower 2 bits of address since PIC memory registers are 32-bits\n assign picm_wren = (lsu_pkt_r.valid & lsu_pkt_r.store & addr_in_pic_r & lsu_commit_r) | dma_pic_wen;\n assign picm_rden = lsu_pkt_d.valid & lsu_pkt_d.load & addr_in_pic_d;\n assign picm_mken = lsu_pkt_d.valid & lsu_pkt_d.store & addr_in_pic_d; // Get the mask for stores\n assign picm_rdaddr[31:0] = pt.PIC_BASE_ADDR | {{32-pt.PIC_BITS{1'b0}},lsu_addr_d[pt.PIC_BITS-1:0]};\n\n assign picm_wraddr[31:0] = pt.PIC_BASE_ADDR | {{32-pt.PIC_BITS{1'b0}},(dma_pic_wen ? dma_mem_addr[pt.PIC_BITS-1:0] : lsu_addr_r[pt.PIC_BITS-1:0])};\n\n assign picm_wr_data[31:0] = dma_pic_wen ? dma_mem_wdata[31:0] : store_datafn_lo_r[31:0];\n\n assign picm_mask_data_m[31:0] = picm_rd_data_m[31:0];\n assign picm_rd_data_m[63:0] = {picm_rd_data[31:0],picm_rd_data[31:0]};\n\n if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable\n rvdff #(1) dccm_rden_mff (.*, .din(lsu_dccm_rden_d), .dout(lsu_dccm_rden_m), .clk(lsu_c2_m_clk));\n rvdff #(1) dccm_rden_rff (.*, .din(lsu_dccm_rden_m), .dout(lsu_dccm_rden_r), .clk(lsu_c2_r_clk));\n\n // ECC correction flops since dccm write happens next cycle\n // We are writing to dccm in r+1 for ecc correction since fast_int needs to be blocked in decode - 1. We can probably write in r for plus0 configuration since we know ecc error in M.\n // In that case these (_ff) flops are needed only in plus1 configuration\n rvdff #(1) ld_double_ecc_error_rff (.*, .din(lsu_double_ecc_error_r), .dout(lsu_double_ecc_error_r_ff), .clk(lsu_free_c2_clk));\n rvdff #(1) ld_single_ecc_error_hi_rff (.*, .din(ld_single_ecc_error_hi_r_ns), .dout(ld_single_ecc_error_hi_r_ff), .clk(lsu_free_c2_clk));\n rvdff #(1) ld_single_ecc_error_lo_rff (.*, .din(ld_single_ecc_error_lo_r_ns), .dout(ld_single_ecc_error_lo_r_ff), .clk(lsu_free_c2_clk));\n rvdffe #(pt.DCCM_BITS) ld_sec_addr_hi_rff (.*, .din(end_addr_r[pt.DCCM_BITS-1:0]), .dout(ld_sec_addr_hi_r_ff[pt.DCCM_BITS-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk));\n rvdffe #(pt.DCCM_BITS) ld_sec_addr_lo_rff (.*, .din(lsu_addr_r[pt.DCCM_BITS-1:0]), .dout(ld_sec_addr_lo_r_ff[pt.DCCM_BITS-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk));\n\n end else begin: Gen_dccm_disable\n assign lsu_dccm_rden_m = '0;\n assign lsu_dccm_rden_r = '0;\n\n assign lsu_double_ecc_error_r_ff = 1'b0;\n assign ld_single_ecc_error_hi_r_ff = 1'b0;\n assign ld_single_ecc_error_lo_r_ff = 1'b0;\n assign ld_sec_addr_hi_r_ff[pt.DCCM_BITS-1:0] = '0;\n assign ld_sec_addr_lo_r_ff[pt.DCCM_BITS-1:0] = '0;\n end\n\n`ifdef RV_ASSERT_ON\n\n // Load single ECC error correction implies commit/dma\n property ld_single_ecc_error_commit;\n @(posedge clk) disable iff(~rst_l) (ld_single_ecc_error_r_ff & dccm_wren) |-> ($past(lsu_commit_r | lsu_pkt_r.dma));\n endproperty\n assert_ld_single_ecc_error_commit: assert property (ld_single_ecc_error_commit) else\n $display(\"No commit or DMA but ECC correction happened\");\n\n\n`endif\n\nendmodule\n" }, { "path": "design/lsu/el2_lsu_dccm_mem.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n// Copyright (c) 2023 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n//\n// Owner:\n// Function: DCCM for LSU pipe\n// Comments: Single ported memory\n//\n//\n// DC1 -> DC2 -> DC3 -> DC4 (Commit)\n//\n// //********************************************************************************\n\nmodule el2_lsu_dccm_mem\n import el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic rst_l, // reset, active low\n input logic clk_override, // Override non-functional clock gating\n\n input logic dccm_wren, // write enable\n input logic dccm_rden, // read enable\n input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, // write address\n input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, // write address\n input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, // read address\n input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data\n el2_mem_if.veer_dccm dccm_mem_export, // RAM repositioned in testbench and connected by this interface\n\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode\n /*pragma coverage on*/\n);\n\n\n localparam logic [5:0] DCCM_WIDTH_BITS = $clog2(pt.DCCM_BYTE_WIDTH);\n localparam logic [7:0] DCCM_INDEX_BITS = 8'(pt.DCCM_BITS - pt.DCCM_BANK_BITS - pt.DCCM_WIDTH_BITS);\n localparam logic [31:0] DCCM_INDEX_DEPTH = ((pt.DCCM_SIZE)*1024)/((pt.DCCM_BYTE_WIDTH)*(pt.DCCM_NUM_BANKS)); // Depth of memory bank\n\n logic [pt.DCCM_NUM_BANKS-1:0] wren_bank;\n logic [pt.DCCM_NUM_BANKS-1:0] rden_bank;\n logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] addr_bank;\n logic rd_unaligned, wr_unaligned;\n logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;\n\n logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0] wr_data_bank;\n\n logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;\n logic [(DCCM_WIDTH_BITS+pt.DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;\n\n logic [pt.DCCM_NUM_BANKS-1:0] dccm_clken;\n\n assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]);\n assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]);\n\n // Align the read data\n assign dccm_rd_data_lo[pt.DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[pt.DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]][pt.DCCM_FDATA_WIDTH-1:0];\n assign dccm_rd_data_hi[pt.DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:pt.DCCM_BANK_BITS]][pt.DCCM_FDATA_WIDTH-1:0];\n\n\n // 8 Banks, 16KB each (2048 x 72)\n for (genvar i=0; i DC2 -> DC3 -> DC4 (Commit)\n//\n//********************************************************************************\nmodule el2_lsu_ecc\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n(\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic lsu_c2_r_clk, // clock\n input logic clk_override, // Override non-functional clock gating\n input logic rst_l, // reset, active low\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode, // scan mode\n /*pragma coverage on*/\n\n input el2_lsu_pkt_t lsu_pkt_m, // packet in m\n input el2_lsu_pkt_t lsu_pkt_r, // packet in r\n input logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any,\n\n input logic dec_tlu_core_ecc_disable, // disables the ecc computation and error flagging\n\n input logic lsu_dccm_rden_r, // dccm rden\n input logic addr_in_dccm_r, // address in dccm\n input logic [pt.DCCM_BITS-1:0] lsu_addr_r, // start address\n input logic [pt.DCCM_BITS-1:0] end_addr_r, // end address\n input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r, // data from the dccm\n input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r, // data from the dccm\n input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_r, // data from the dccm + ecc\n input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_r, // data from the dccm + ecc\n output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_r, // corrected dccm data R-stage\n output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r, // corrected dccm data R-stage\n output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_r_ff, // corrected dccm data R+1 stage\n output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r_ff, // corrected dccm data R+1 stage\n\n input logic ld_single_ecc_error_r, // ld has a single ecc error\n input logic ld_single_ecc_error_r_ff, // ld has a single ecc error\n input logic lsu_dccm_rden_m, // dccm rden\n input logic addr_in_dccm_m, // address in dccm\n input logic [pt.DCCM_BITS-1:0] lsu_addr_m, // start address\n input logic [pt.DCCM_BITS-1:0] end_addr_m, // end address\n input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m, // raw data from mem\n input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m, // raw data from mem\n input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_m, // ecc read out from mem\n input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_m, // ecc read out from mem\n output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_m, // corrected dccm data M-stage\n output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_m, // corrected dccm data M-stage\n\n input logic dma_dccm_wen, // Perform DMA writes only for word/dword\n input logic [31:0] dma_dccm_wdata_lo, // Shifted dma data to lower bits to make it consistent to lsu stores\n input logic [31:0] dma_dccm_wdata_hi, // Shifted dma data to lower bits to make it consistent to lsu stores\n output logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_hi, // ECC bits for the DMA wdata\n output logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, // ECC bits for the DMA wdata\n\n output logic [pt.DCCM_ECC_WIDTH-1:0] stbuf_ecc_any, // Encoded data with ECC bits\n output logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_hi_r_ff, // Encoded data with ECC bits\n output logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_lo_r_ff, // Encoded data with ECC bits\n\n output logic single_ecc_error_hi_r, // sec detected\n output logic single_ecc_error_lo_r, // sec detected on lower dccm bank\n output logic lsu_single_ecc_error_r, // or of the 2\n output logic lsu_double_ecc_error_r, // double error detected\n\n output logic lsu_single_ecc_error_m, // or of the 2\n output logic lsu_double_ecc_error_m // double error detected\n\n );\n\n logic is_ldst_r;\n logic is_ldst_hi_any, is_ldst_lo_any;\n logic [pt.DCCM_DATA_WIDTH-1:0] dccm_wdata_hi_any, dccm_wdata_lo_any;\n logic [pt.DCCM_ECC_WIDTH-1:0] dccm_wdata_ecc_hi_any, dccm_wdata_ecc_lo_any;\n logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_any, dccm_rdata_lo_any;\n logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_any, dccm_data_ecc_lo_any;\n logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_any, sec_data_lo_any;\n logic single_ecc_error_hi_any, single_ecc_error_lo_any;\n logic double_ecc_error_hi_any, double_ecc_error_lo_any;\n\n logic double_ecc_error_hi_m, double_ecc_error_lo_m;\n logic double_ecc_error_hi_r, double_ecc_error_lo_r;\n\n logic [6:0] ecc_out_hi_nc, ecc_out_lo_nc;\n\n\n if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1\n logic ldst_dual_m, ldst_dual_r;\n logic is_ldst_m;\n logic is_ldst_hi_r, is_ldst_lo_r;\n\n assign ldst_dual_r = (lsu_addr_r[2] != end_addr_r[2]);\n assign is_ldst_r = lsu_pkt_r.valid & (lsu_pkt_r.load | lsu_pkt_r.store) & addr_in_dccm_r & lsu_dccm_rden_r;\n assign is_ldst_lo_r = is_ldst_r & ~dec_tlu_core_ecc_disable;\n assign is_ldst_hi_r = is_ldst_r & ldst_dual_r & ~dec_tlu_core_ecc_disable; // Always check the ECC Hi/Lo for DMA since we don't align for DMA\n\n assign is_ldst_hi_any = is_ldst_hi_r;\n assign dccm_rdata_hi_any[pt.DCCM_DATA_WIDTH-1:0] = dccm_rdata_hi_r[pt.DCCM_DATA_WIDTH-1:0];\n assign dccm_data_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_hi_r[pt.DCCM_ECC_WIDTH-1:0];\n assign is_ldst_lo_any = is_ldst_lo_r;\n assign dccm_rdata_lo_any[pt.DCCM_DATA_WIDTH-1:0] = dccm_rdata_lo_r[pt.DCCM_DATA_WIDTH-1:0];\n assign dccm_data_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_lo_r[pt.DCCM_ECC_WIDTH-1:0];\n\n assign sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0] = sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0];\n assign single_ecc_error_hi_r = single_ecc_error_hi_any;\n assign double_ecc_error_hi_r = double_ecc_error_hi_any;\n assign sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0] = sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0];\n assign single_ecc_error_lo_r = single_ecc_error_lo_any;\n assign double_ecc_error_lo_r = double_ecc_error_lo_any;\n\n assign lsu_single_ecc_error_r = single_ecc_error_hi_r | single_ecc_error_lo_r;\n assign lsu_double_ecc_error_r = double_ecc_error_hi_r | double_ecc_error_lo_r;\n\n end else begin: L2U_Plus1_0\n\n logic ldst_dual_m;\n logic is_ldst_m;\n logic is_ldst_hi_m, is_ldst_lo_m;\n\n assign ldst_dual_m = (lsu_addr_m[2] != end_addr_m[2]);\n assign is_ldst_m = lsu_pkt_m.valid & (lsu_pkt_m.load | lsu_pkt_m.store) & addr_in_dccm_m & lsu_dccm_rden_m;\n assign is_ldst_lo_m = is_ldst_m & ~dec_tlu_core_ecc_disable;\n assign is_ldst_hi_m = is_ldst_m & (ldst_dual_m | lsu_pkt_m.dma) & ~dec_tlu_core_ecc_disable; // Always check the ECC Hi/Lo for DMA since we don't align for DMA\n\n assign is_ldst_hi_any = is_ldst_hi_m;\n assign dccm_rdata_hi_any[pt.DCCM_DATA_WIDTH-1:0] = dccm_rdata_hi_m[pt.DCCM_DATA_WIDTH-1:0];\n assign dccm_data_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_hi_m[pt.DCCM_ECC_WIDTH-1:0];\n assign is_ldst_lo_any = is_ldst_lo_m;\n assign dccm_rdata_lo_any[pt.DCCM_DATA_WIDTH-1:0] = dccm_rdata_lo_m[pt.DCCM_DATA_WIDTH-1:0];\n assign dccm_data_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_lo_m[pt.DCCM_ECC_WIDTH-1:0];\n\n assign sec_data_hi_m[pt.DCCM_DATA_WIDTH-1:0] = sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0];\n assign double_ecc_error_hi_m = double_ecc_error_hi_any;\n assign sec_data_lo_m[pt.DCCM_DATA_WIDTH-1:0] = sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0];\n assign double_ecc_error_lo_m = double_ecc_error_lo_any;\n\n assign lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any;\n assign lsu_double_ecc_error_m = double_ecc_error_hi_m | double_ecc_error_lo_m;\n\n // Flops\n rvdff #(1) lsu_single_ecc_err_r (.din(lsu_single_ecc_error_m), .dout(lsu_single_ecc_error_r), .clk(lsu_c2_r_clk), .*);\n rvdff #(1) lsu_double_ecc_err_r (.din(lsu_double_ecc_error_m), .dout(lsu_double_ecc_error_r), .clk(lsu_c2_r_clk), .*);\n rvdff #(.WIDTH(1)) ldst_sec_lo_rff (.din(single_ecc_error_lo_any), .dout(single_ecc_error_lo_r), .clk(lsu_c2_r_clk), .*);\n rvdff #(.WIDTH(1)) ldst_sec_hi_rff (.din(single_ecc_error_hi_any), .dout(single_ecc_error_hi_r), .clk(lsu_c2_r_clk), .*);\n rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_hi_rff (.din(sec_data_hi_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .en(lsu_single_ecc_error_m | clk_override), .*);\n rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_lo_rff (.din(sec_data_lo_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .en(lsu_single_ecc_error_m | clk_override), .*);\n\n end\n\n // Logic for ECC generation during write\n assign dccm_wdata_lo_any[pt.DCCM_DATA_WIDTH-1:0] = ld_single_ecc_error_r_ff ? sec_data_lo_r_ff[pt.DCCM_DATA_WIDTH-1:0] : (dma_dccm_wen ? dma_dccm_wdata_lo[pt.DCCM_DATA_WIDTH-1:0] : stbuf_data_any[pt.DCCM_DATA_WIDTH-1:0]);\n assign dccm_wdata_hi_any[pt.DCCM_DATA_WIDTH-1:0] = ld_single_ecc_error_r_ff ? sec_data_hi_r_ff[pt.DCCM_DATA_WIDTH-1:0] : (dma_dccm_wen ? dma_dccm_wdata_hi[pt.DCCM_DATA_WIDTH-1:0] : 32'h0);\n\n assign sec_data_ecc_hi_r_ff[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0];\n assign sec_data_ecc_lo_r_ff[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0];\n assign stbuf_ecc_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0];\n assign dma_dccm_wdata_ecc_hi[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0];\n assign dma_dccm_wdata_ecc_lo[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0];\n\n // Instantiate ECC blocks\n if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable\n\n //Detect/Repair for Hi\n rvecc_decode lsu_ecc_decode_hi (\n // Inputs\n .en(is_ldst_hi_any),\n .sed_ded (1'b0), // 1 : means only detection\n .din(dccm_rdata_hi_any[pt.DCCM_DATA_WIDTH-1:0]),\n .ecc_in(dccm_data_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0]),\n // Outputs\n .dout(sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0]),\n .ecc_out (ecc_out_hi_nc[6:0]),\n .single_ecc_error(single_ecc_error_hi_any),\n .double_ecc_error(double_ecc_error_hi_any),\n .*\n );\n\n //Detect/Repair for Lo\n rvecc_decode lsu_ecc_decode_lo (\n // Inputs\n .en(is_ldst_lo_any),\n .sed_ded (1'b0), // 1 : means only detection\n .din(dccm_rdata_lo_any[pt.DCCM_DATA_WIDTH-1:0] ),\n .ecc_in(dccm_data_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0]),\n // Outputs\n .dout(sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0]),\n .ecc_out (ecc_out_lo_nc[6:0]),\n .single_ecc_error(single_ecc_error_lo_any),\n .double_ecc_error(double_ecc_error_lo_any),\n .*\n );\n\n rvecc_encode lsu_ecc_encode_hi (\n //Inputs\n .din(dccm_wdata_hi_any[pt.DCCM_DATA_WIDTH-1:0]),\n //Outputs\n .ecc_out(dccm_wdata_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0]),\n .*\n );\n rvecc_encode lsu_ecc_encode_lo (\n //Inputs\n .din(dccm_wdata_lo_any[pt.DCCM_DATA_WIDTH-1:0]),\n //Outputs\n .ecc_out(dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0]),\n .*\n );\n end else begin: Gen_dccm_disable // block: Gen_dccm_enable\n assign sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0] = '0;\n assign sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0] = '0;\n assign single_ecc_error_hi_any = '0;\n assign double_ecc_error_hi_any = '0;\n assign single_ecc_error_lo_any = '0;\n assign double_ecc_error_lo_any = '0;\n end\n\n rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_hi_rplus1ff (.din(sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_hi_r_ff[pt.DCCM_DATA_WIDTH-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk), .*);\n rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_lo_rplus1ff (.din(sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_lo_r_ff[pt.DCCM_DATA_WIDTH-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk), .*);\n\n\nendmodule // el2_lsu_ecc\n" }, { "path": "design/lsu/el2_lsu_lsc_ctl.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n//\n// Owner:\n// Function: LSU control\n// Comments:\n//\n//\n// DC1 -> DC2 -> DC3 -> DC4 (Commit)\n//\n//********************************************************************************\nmodule el2_lsu_lsc_ctl\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input logic rst_l, // reset, active low\n input logic clk_override, // Override non-functional clock gating\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n\n // clocks per pipe\n input logic lsu_c1_m_clk,\n input logic lsu_c1_r_clk,\n input logic lsu_c2_m_clk,\n input logic lsu_c2_r_clk,\n input logic lsu_store_c1_m_clk,\n\n input logic [31:0] lsu_ld_data_r, // Load data R-stage\n input logic [31:0] lsu_ld_data_corr_r, // ECC corrected data R-stage\n input logic lsu_single_ecc_error_r, // ECC single bit error R-stage\n input logic lsu_double_ecc_error_r, // ECC double bit error R-stage\n\n input logic [31:0] lsu_ld_data_m, // Load data M-stage\n input logic lsu_single_ecc_error_m, // ECC single bit error M-stage\n input logic lsu_double_ecc_error_m, // ECC double bit error M-stage\n\n input logic flush_m_up, // Flush M and D stage\n input logic flush_r, // Flush R-stage\n input logic ldst_dual_d, // load/store is unaligned at 32 bit boundary D-stage\n input logic ldst_dual_m, // load/store is unaligned at 32 bit boundary M-stage\n input logic ldst_dual_r, // load/store is unaligned at 32 bit boundary R-stage\n\n input logic [31:0] exu_lsu_rs1_d, // address\n input logic [31:0] exu_lsu_rs2_d, // store data\n\n input el2_lsu_pkt_t lsu_p, // lsu control packet\n input logic dec_lsu_valid_raw_d, // Raw valid for address computation\n input logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses\n\n input logic [31:0] picm_mask_data_m, // PIC data M-stage\n input logic [31:0] bus_read_data_m, // the bus return data\n output logic [31:0] lsu_result_m, // lsu load data\n output logic [31:0] lsu_result_corr_r, // This is the ECC corrected data going to RF\n // lsu address down the pipe\n output logic [31:0] lsu_addr_d,\n output logic [31:0] lsu_addr_m,\n output logic [31:0] lsu_addr_r,\n // lsu address down the pipe - needed to check unaligned\n output logic [31:0] end_addr_d,\n output logic [31:0] end_addr_m,\n output logic [31:0] end_addr_r,\n // store data down the pipe\n output logic [31:0] store_data_m,\n\n input logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control\n output logic lsu_exc_m, // Access or misaligned fault\n output logic is_sideeffects_m, // is sideffects space\n output logic lsu_commit_r, // lsu instruction in r commits\n output logic lsu_single_ecc_error_incr,// LSU inc SB error counter\n output el2_lsu_error_pkt_t lsu_error_pkt_r, // lsu exception packet\n\n output logic [31:1] lsu_fir_addr, // fast interrupt address\n output logic [1:0] lsu_fir_error, // Error during fast interrupt lookup\n\n // address in dccm/pic/external per pipe stage\n output logic addr_in_dccm_d,\n output logic addr_in_dccm_m,\n output logic addr_in_dccm_r,\n\n output logic addr_in_pic_d,\n output logic addr_in_pic_m,\n output logic addr_in_pic_r,\n\n output logic addr_external_m,\n\n // DMA slave\n input logic dma_dccm_req,\n input logic [31:0] dma_mem_addr,\n input logic [2:0] dma_mem_sz,\n input logic dma_mem_write,\n input logic [63:0] dma_mem_wdata,\n\n // Store buffer related signals\n output el2_lsu_pkt_t lsu_pkt_d,\n output el2_lsu_pkt_t lsu_pkt_m,\n output el2_lsu_pkt_t lsu_pkt_r,\n\n input logic lsu_pmp_error_start,\n input logic lsu_pmp_error_end,\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // Scan mode\n /*pragma coverage on*/\n\n );\n\n logic [31:3] end_addr_pre_m, end_addr_pre_r;\n logic [31:0] full_addr_d;\n logic [31:0] full_end_addr_d;\n logic [31:0] lsu_rs1_d;\n logic [11:0] lsu_offset_d;\n logic [31:0] rs1_d;\n logic [11:0] offset_d;\n logic [12:0] end_addr_offset_d;\n logic [2:0] addr_offset_d;\n\n logic [63:0] dma_mem_wdata_shifted;\n logic addr_external_d;\n logic addr_external_r;\n logic access_fault_d, misaligned_fault_d;\n logic access_fault_m, misaligned_fault_m;\n\n logic fir_dccm_access_error_d, fir_nondccm_access_error_d;\n logic fir_dccm_access_error_m, fir_nondccm_access_error_m;\n\n logic [3:0] exc_mscause_d, exc_mscause_m;\n logic [31:0] rs1_d_raw;\n logic [31:0] store_data_d, store_data_pre_m, store_data_m_in;\n logic [31:0] bus_read_data_r;\n\n el2_lsu_pkt_t dma_pkt_d;\n el2_lsu_pkt_t lsu_pkt_m_in, lsu_pkt_r_in;\n el2_lsu_error_pkt_t lsu_error_pkt_m;\n\n\n // Premux the rs1/offset for dma\n assign lsu_rs1_d[31:0] = dec_lsu_valid_raw_d ? exu_lsu_rs1_d[31:0] : dma_mem_addr[31:0];\n assign lsu_offset_d[11:0] = dec_lsu_offset_d[11:0] & {12{dec_lsu_valid_raw_d}};\n assign rs1_d_raw[31:0] = lsu_rs1_d[31:0];\n assign offset_d[11:0] = lsu_offset_d[11:0];\n\n assign rs1_d[31:0] = (lsu_pkt_d.load_ldst_bypass_d) ? lsu_result_m[31:0] : rs1_d_raw[31:0];\n\n // generate the ls address\n rvlsadder lsadder (.rs1(rs1_d[31:0]),\n .offset(offset_d[11:0]),\n .dout(full_addr_d[31:0])\n );\n\n // Module to generate the memory map of the address\n el2_lsu_addrcheck addrcheck (\n .start_addr_d(full_addr_d[31:0]),\n .end_addr_d(full_end_addr_d[31:0]),\n .rs1_region_d(rs1_d[31:28]),\n .*\n );\n\n // Calculate start/end address for load/store\n assign addr_offset_d[2:0] = ({3{lsu_pkt_d.half}} & 3'b01) | ({3{lsu_pkt_d.word}} & 3'b11) | ({3{lsu_pkt_d.dword}} & 3'b111);\n assign end_addr_offset_d[12:0] = {offset_d[11],offset_d[11:0]} + {9'b0,addr_offset_d[2:0]};\n assign full_end_addr_d[31:0] = rs1_d[31:0] + {{19{end_addr_offset_d[12]}},end_addr_offset_d[12:0]};\n assign end_addr_d[31:0] = full_end_addr_d[31:0];\n assign lsu_exc_m = access_fault_m | misaligned_fault_m;\n\n // Goes to TLU to increment the ECC error counter\n assign lsu_single_ecc_error_incr = (lsu_single_ecc_error_r & ~lsu_double_ecc_error_r) & (lsu_commit_r | lsu_pkt_r.dma) & lsu_pkt_r.valid;\n\n if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1\n logic access_fault_r, misaligned_fault_r;\n logic [3:0] exc_mscause_r;\n logic fir_dccm_access_error_r, fir_nondccm_access_error_r;\n\n // Generate exception packet\n assign lsu_error_pkt_r.exc_valid = (access_fault_r | misaligned_fault_r | lsu_double_ecc_error_r) & lsu_pkt_r.valid & ~lsu_pkt_r.dma & ~lsu_pkt_r.fast_int;\n assign lsu_error_pkt_r.single_ecc_error = lsu_single_ecc_error_r & ~lsu_error_pkt_r.exc_valid & ~lsu_pkt_r.dma;\n assign lsu_error_pkt_r.inst_type = lsu_pkt_r.store;\n assign lsu_error_pkt_r.exc_type = ~misaligned_fault_r;\n assign lsu_error_pkt_r.mscause[3:0] = (lsu_double_ecc_error_r & ~misaligned_fault_r & ~access_fault_r) ? 4'h1 : exc_mscause_r[3:0];\n assign lsu_error_pkt_r.addr[31:0] = lsu_addr_r[31:0];\n\n assign lsu_fir_error[1:0] = fir_nondccm_access_error_r ? 2'b11 : (fir_dccm_access_error_r ? 2'b10 : ((lsu_pkt_r.fast_int & lsu_double_ecc_error_r) ? 2'b01 : 2'b00));\n\n rvdff #(1) access_fault_rff (.din(access_fault_m), .dout(access_fault_r), .clk(lsu_c1_r_clk), .*);\n rvdff #(1) misaligned_fault_rff (.din(misaligned_fault_m), .dout(misaligned_fault_r), .clk(lsu_c1_r_clk), .*);\n rvdff #(4) exc_mscause_rff (.din(exc_mscause_m[3:0]), .dout(exc_mscause_r[3:0]), .clk(lsu_c1_r_clk), .*);\n rvdff #(1) fir_dccm_access_error_mff (.din(fir_dccm_access_error_m), .dout(fir_dccm_access_error_r), .clk(lsu_c1_r_clk), .*);\n rvdff #(1) fir_nondccm_access_error_mff (.din(fir_nondccm_access_error_m), .dout(fir_nondccm_access_error_r), .clk(lsu_c1_r_clk), .*);\n\n end else begin: L2U_Plus1_0\n logic [1:0] lsu_fir_error_m;\n\n // Generate exception packet\n assign lsu_error_pkt_m.exc_valid = (access_fault_m | misaligned_fault_m | lsu_double_ecc_error_m) & lsu_pkt_m.valid & ~lsu_pkt_m.dma & ~lsu_pkt_m.fast_int & ~flush_m_up;\n assign lsu_error_pkt_m.single_ecc_error = lsu_single_ecc_error_m & ~lsu_error_pkt_m.exc_valid & ~lsu_pkt_m.dma;\n assign lsu_error_pkt_m.inst_type = lsu_pkt_m.store;\n assign lsu_error_pkt_m.exc_type = ~misaligned_fault_m;\n assign lsu_error_pkt_m.mscause[3:0] = (lsu_double_ecc_error_m & ~misaligned_fault_m & ~access_fault_m) ? 4'h1 : exc_mscause_m[3:0];\n assign lsu_error_pkt_m.addr[31:0] = lsu_addr_m[31:0];\n\n assign lsu_fir_error_m[1:0] = fir_nondccm_access_error_m ? 2'b11 : (fir_dccm_access_error_m ? 2'b10 : ((lsu_pkt_m.fast_int & lsu_double_ecc_error_m) ? 2'b01 : 2'b00));\n\n rvdff #(1) lsu_exc_valid_rff (.*, .din(lsu_error_pkt_m.exc_valid), .dout(lsu_error_pkt_r.exc_valid), .clk(lsu_c2_r_clk));\n rvdff #(1) lsu_single_ecc_error_rff(.*, .din(lsu_error_pkt_m.single_ecc_error), .dout(lsu_error_pkt_r.single_ecc_error), .clk(lsu_c2_r_clk));\n rvdffe #($bits(el2_lsu_error_pkt_t)-2) lsu_error_pkt_rff (.*, .din(lsu_error_pkt_m[$bits(el2_lsu_error_pkt_t)-1:2]), .dout(lsu_error_pkt_r[$bits(el2_lsu_error_pkt_t)-1:2]), .en(lsu_error_pkt_m.exc_valid | lsu_error_pkt_m.single_ecc_error | clk_override));\n rvdff #(2) lsu_fir_error_rff (.*, .din(lsu_fir_error_m[1:0]), .dout(lsu_fir_error[1:0]), .clk(lsu_c2_r_clk));\n end\n\n //Create DMA packet\n always_comb begin\n dma_pkt_d = '0;\n dma_pkt_d.valid = dma_dccm_req;\n dma_pkt_d.dma = 1'b1;\n dma_pkt_d.store = dma_mem_write;\n dma_pkt_d.load = ~dma_mem_write;\n dma_pkt_d.by = (dma_mem_sz[2:0] == 3'b0);\n dma_pkt_d.half = (dma_mem_sz[2:0] == 3'b1);\n dma_pkt_d.word = (dma_mem_sz[2:0] == 3'b10);\n dma_pkt_d.dword = (dma_mem_sz[2:0] == 3'b11);\n end\n\n always_comb begin\n lsu_pkt_d = dec_lsu_valid_raw_d ? lsu_p : dma_pkt_d;\n lsu_pkt_m_in = lsu_pkt_d;\n lsu_pkt_r_in = lsu_pkt_m;\n\n lsu_pkt_d.valid = (lsu_p.valid & ~(flush_m_up & ~lsu_p.fast_int)) | dma_dccm_req;\n lsu_pkt_m_in.valid = lsu_pkt_d.valid & ~(flush_m_up & ~lsu_pkt_d.dma);\n lsu_pkt_r_in.valid = lsu_pkt_m.valid & ~(flush_m_up & ~lsu_pkt_m.dma) ;\n end\n\n // C2 clock for valid and C1 for other bits of packet\n rvdff #(1) lsu_pkt_vldmff (.*, .din(lsu_pkt_m_in.valid), .dout(lsu_pkt_m.valid), .clk(lsu_c2_m_clk));\n rvdff #(1) lsu_pkt_vldrff (.*, .din(lsu_pkt_r_in.valid), .dout(lsu_pkt_r.valid), .clk(lsu_c2_r_clk));\n\n rvdff #($bits(el2_lsu_pkt_t)-1) lsu_pkt_mff (.*, .din(lsu_pkt_m_in[$bits(el2_lsu_pkt_t)-1:1]), .dout(lsu_pkt_m[$bits(el2_lsu_pkt_t)-1:1]), .clk(lsu_c1_m_clk));\n rvdff #($bits(el2_lsu_pkt_t)-1) lsu_pkt_rff (.*, .din(lsu_pkt_r_in[$bits(el2_lsu_pkt_t)-1:1]), .dout(lsu_pkt_r[$bits(el2_lsu_pkt_t)-1:1]), .clk(lsu_c1_r_clk));\n\n\n\n if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U1_Plus1_1\n logic [31:0] lsu_ld_datafn_r, lsu_ld_datafn_corr_r;\n\n assign lsu_ld_datafn_r[31:0] = addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_r[31:0];\n assign lsu_ld_datafn_corr_r[31:0] = addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_corr_r[31:0];\n\n // this is really R stage signal\n assign lsu_result_m[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_r[7:0]}) |\n ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_r[15:0]}) |\n ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_r[7]}}, lsu_ld_datafn_r[7:0]}) |\n ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_r[15]}},lsu_ld_datafn_r[15:0]}) |\n ({32{lsu_pkt_r.word}} & lsu_ld_datafn_r[31:0]);\n\n // this signal is used for gpr update\n assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |\n ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_corr_r[15:0]}) |\n ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]}) |\n ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) |\n ({32{lsu_pkt_r.word}} & lsu_ld_datafn_corr_r[31:0]);\n\n end else begin: L2U1_Plus1_0 // block: L2U1_Plus1_1\n logic [31:0] lsu_ld_datafn_m, lsu_ld_datafn_corr_r;\n\n assign lsu_ld_datafn_m[31:0] = addr_external_m ? bus_read_data_m[31:0] : lsu_ld_data_m[31:0];\n assign lsu_ld_datafn_corr_r[31:0] = addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_corr_r[31:0];\n\n // this result must look at prior stores and merge them in\n assign lsu_result_m[31:0] = ({32{ lsu_pkt_m.unsign & lsu_pkt_m.by }} & {24'b0,lsu_ld_datafn_m[7:0]}) |\n ({32{ lsu_pkt_m.unsign & lsu_pkt_m.half}} & {16'b0,lsu_ld_datafn_m[15:0]}) |\n ({32{~lsu_pkt_m.unsign & lsu_pkt_m.by }} & {{24{ lsu_ld_datafn_m[7]}}, lsu_ld_datafn_m[7:0]}) |\n ({32{~lsu_pkt_m.unsign & lsu_pkt_m.half}} & {{16{ lsu_ld_datafn_m[15]}},lsu_ld_datafn_m[15:0]}) |\n ({32{lsu_pkt_m.word}} & lsu_ld_datafn_m[31:0]);\n\n // this signal is used for gpr update\n assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |\n ({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_corr_r[15:0]}) |\n ({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]}) |\n ({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) |\n ({32{lsu_pkt_r.word}} & lsu_ld_datafn_corr_r[31:0]);\n end\n\n // Fast interrupt address\n assign lsu_fir_addr[31:1] = lsu_ld_data_corr_r[31:1];\n\n // absence load/store all 0's\n assign lsu_addr_d[31:0] = full_addr_d[31:0];\n\n // Interrupt as a flush source allows the WB to occur\n assign lsu_commit_r = lsu_pkt_r.valid & (lsu_pkt_r.store | lsu_pkt_r.load) & ~flush_r & ~lsu_pkt_r.dma;\n\n assign dma_mem_wdata_shifted[63:0] = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores\n assign store_data_d[31:0] = dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0]; // Write to PIC still happens in r stage\n\n assign store_data_m_in[31:0] = (lsu_pkt_d.store_data_bypass_d) ? lsu_result_m[31:0] : store_data_d[31:0];\n\n assign store_data_m[31:0] = (picm_mask_data_m[31:0] | {32{~addr_in_pic_m}}) & ((lsu_pkt_m.store_data_bypass_m) ? lsu_result_m[31:0] : store_data_pre_m[31:0]);\n\n\n rvdff #(32) sdmff (.*, .din(store_data_m_in[31:0]), .dout(store_data_pre_m[31:0]), .clk(lsu_store_c1_m_clk));\n\n rvdff #(32) samff (.*, .din(lsu_addr_d[31:0]), .dout(lsu_addr_m[31:0]), .clk(lsu_c1_m_clk));\n rvdff #(32) sarff (.*, .din(lsu_addr_m[31:0]), .dout(lsu_addr_r[31:0]), .clk(lsu_c1_r_clk));\n\n assign end_addr_m[31:3] = ldst_dual_m ? end_addr_pre_m[31:3] : lsu_addr_m[31:3]; // This is for power saving\n assign end_addr_r[31:3] = ldst_dual_r ? end_addr_pre_r[31:3] : lsu_addr_r[31:3]; // This is for power saving\n\n rvdffe #(29) end_addr_hi_mff (.*, .din(end_addr_d[31:3]), .dout(end_addr_pre_m[31:3]), .en((lsu_pkt_d.valid & ldst_dual_d) | clk_override));\n rvdffe #(29) end_addr_hi_rff (.*, .din(end_addr_m[31:3]), .dout(end_addr_pre_r[31:3]), .en((lsu_pkt_m.valid & ldst_dual_m) | clk_override));\n\n rvdff #(3) end_addr_lo_mff (.*, .din(end_addr_d[2:0]), .dout(end_addr_m[2:0]), .clk(lsu_c1_m_clk));\n rvdff #(3) end_addr_lo_rff (.*, .din(end_addr_m[2:0]), .dout(end_addr_r[2:0]), .clk(lsu_c1_r_clk));\n\n rvdff #(1) addr_in_dccm_mff(.din(addr_in_dccm_d), .dout(addr_in_dccm_m), .clk(lsu_c1_m_clk), .*);\n rvdff #(1) addr_in_dccm_rff(.din(addr_in_dccm_m), .dout(addr_in_dccm_r), .clk(lsu_c1_r_clk), .*);\n\n rvdff #(1) addr_in_pic_mff(.din(addr_in_pic_d), .dout(addr_in_pic_m), .clk(lsu_c1_m_clk), .*);\n rvdff #(1) addr_in_pic_rff(.din(addr_in_pic_m), .dout(addr_in_pic_r), .clk(lsu_c1_r_clk), .*);\n\n rvdff #(1) addr_external_mff(.din(addr_external_d), .dout(addr_external_m), .clk(lsu_c1_m_clk), .*);\n rvdff #(1) addr_external_rff(.din(addr_external_m), .dout(addr_external_r), .clk(lsu_c1_r_clk), .*);\n\n rvdff #(1) access_fault_mff (.din(access_fault_d), .dout(access_fault_m), .clk(lsu_c1_m_clk), .*);\n rvdff #(1) misaligned_fault_mff (.din(misaligned_fault_d), .dout(misaligned_fault_m), .clk(lsu_c1_m_clk), .*);\n rvdff #(4) exc_mscause_mff (.din(exc_mscause_d[3:0]), .dout(exc_mscause_m[3:0]), .clk(lsu_c1_m_clk), .*);\n\n rvdff #(1) fir_dccm_access_error_mff (.din(fir_dccm_access_error_d), .dout(fir_dccm_access_error_m), .clk(lsu_c1_m_clk), .*);\n rvdff #(1) fir_nondccm_access_error_mff (.din(fir_nondccm_access_error_d), .dout(fir_nondccm_access_error_m), .clk(lsu_c1_m_clk), .*);\n\n rvdffe #(32) bus_read_data_r_ff (.*, .din(bus_read_data_m[31:0]), .dout(bus_read_data_r[31:0]), .en(addr_external_m | clk_override));\n\nendmodule\n" }, { "path": "design/lsu/el2_lsu_stbuf.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n//\n// Owner:\n// Function: Store Buffer\n// Comments: Dual writes and single drain\n//\n//\n// DC1 -> DC2 -> DC3 -> DC4 (Commit)\n//\n// //********************************************************************************\n\n\nmodule el2_lsu_stbuf\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n(\n input logic clk, // core clock\n input logic rst_l, // reset\n\n input logic lsu_stbuf_c1_clk, // stbuf clock\n input logic lsu_free_c2_clk, // free clk\n\n // Store Buffer input\n input logic store_stbuf_reqvld_r, // core instruction goes to stbuf\n input logic lsu_commit_r, // lsu commits\n input logic dec_lsu_valid_raw_d, // Speculative decode valid\n input logic [pt.DCCM_DATA_WIDTH-1:0] store_data_hi_r, // merged data from the dccm for stores. This is used for fwding\n input logic [pt.DCCM_DATA_WIDTH-1:0] store_data_lo_r, // merged data from the dccm for stores. This is used for fwding\n input logic [pt.DCCM_DATA_WIDTH-1:0] store_datafn_hi_r, // merged data from the dccm for stores\n input logic [pt.DCCM_DATA_WIDTH-1:0] store_datafn_lo_r, // merged data from the dccm for stores\n\n // Store Buffer output\n output logic stbuf_reqvld_any, // stbuf is draining\n output logic stbuf_reqvld_flushed_any, // Top entry is flushed\n output logic [pt.LSU_SB_BITS-1:0] stbuf_addr_any, // address\n output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any, // stbuf data\n\n input logic lsu_stbuf_commit_any, // pop the stbuf as it commite\n output logic lsu_stbuf_full_any, // stbuf is full\n output logic lsu_stbuf_empty_any, // stbuf is empty\n output logic ldst_stbuf_reqvld_r, // needed for clocking\n\n input logic [pt.LSU_SB_BITS-1:0] lsu_addr_d, // lsu address D-stage\n input logic [31:0] lsu_addr_m, // lsu address M-stage\n input logic [31:0] lsu_addr_r, // lsu address R-stage\n\n input logic [pt.LSU_SB_BITS-1:0] end_addr_d, // lsu end address D-stage - needed to check unaligned\n input logic [31:0] end_addr_m, // lsu end address M-stage - needed to check unaligned\n input logic [31:0] end_addr_r, // lsu end address R-stage - needed to check unaligned\n\n input logic ldst_dual_d, ldst_dual_m, ldst_dual_r,\n input logic addr_in_dccm_m, // address is in dccm\n input logic addr_in_dccm_r, // address is in dccm\n\n // Forwarding signals\n input logic lsu_cmpen_m, // needed for forwarding stbuf - load\n input el2_lsu_pkt_t lsu_pkt_m, // LSU packet M-stage\n input el2_lsu_pkt_t lsu_pkt_r, // LSU packet R-stage\n\n output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m, // stbuf data\n output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m, // stbuf data\n output logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_m, // stbuf data\n output logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_m, // stbuf data\n\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // Scan mode\n /*pragma coverage on*/\n\n);\n\n\n localparam DEPTH = pt.LSU_STBUF_DEPTH;\n localparam DATA_WIDTH = pt.DCCM_DATA_WIDTH;\n localparam BYTE_WIDTH = pt.DCCM_BYTE_WIDTH;\n localparam DEPTH_LOG2 = $clog2(DEPTH);\n\n // These are the fields in the store queue\n logic [DEPTH-1:0] stbuf_vld;\n logic [DEPTH-1:0] stbuf_dma_kill;\n logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addr;\n logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_byteen;\n logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_data;\n\n logic [DEPTH-1:0] sel_lo;\n logic [DEPTH-1:0] stbuf_wr_en;\n logic [DEPTH-1:0] stbuf_dma_kill_en;\n logic [DEPTH-1:0] stbuf_reset;\n logic [DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;\n logic [DEPTH-1:0][DATA_WIDTH-1:0] stbuf_datain;\n logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_byteenin;\n\n logic [7:0] store_byteen_ext_r;\n logic [BYTE_WIDTH-1:0] store_byteen_hi_r;\n logic [BYTE_WIDTH-1:0] store_byteen_lo_r;\n\n logic WrPtrEn, RdPtrEn;\n logic [DEPTH_LOG2-1:0] WrPtr, RdPtr;\n logic [DEPTH_LOG2-1:0] NxtWrPtr, NxtRdPtr;\n logic [DEPTH_LOG2-1:0] WrPtrPlus1, WrPtrPlus2, RdPtrPlus1;\n\n logic dual_stbuf_write_r;\n\n logic isdccmst_m, isdccmst_r;\n logic [3:0] stbuf_numvld_any, stbuf_specvld_any;\n logic [1:0] stbuf_specvld_m, stbuf_specvld_r;\n\n logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;\n\n // variables to detect matching from the store queue\n logic [DEPTH-1:0] stbuf_match_hi, stbuf_match_lo;\n logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_fwdbyteenvec_hi, stbuf_fwdbyteenvec_lo;\n logic [DATA_WIDTH-1:0] stbuf_fwddata_hi_pre_m, stbuf_fwddata_lo_pre_m;\n logic [BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_pre_m, stbuf_fwdbyteen_lo_pre_m;\n\n // logic to detect matching from the pipe - needed for store - load forwarding\n logic [BYTE_WIDTH-1:0] ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;\n logic ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;\n\n logic [BYTE_WIDTH-1:0] ld_byte_hit_lo, ld_byte_rhit_lo;\n logic [BYTE_WIDTH-1:0] ld_byte_hit_hi, ld_byte_rhit_hi;\n\n logic [BYTE_WIDTH-1:0] ldst_byteen_hi_r;\n logic [BYTE_WIDTH-1:0] ldst_byteen_lo_r;\n // byte_en flowing down\n logic [7:0] ldst_byteen_r;\n logic [7:0] ldst_byteen_ext_r;\n // fwd data through the pipe\n logic [31:0] ld_fwddata_rpipe_lo;\n logic [31:0] ld_fwddata_rpipe_hi;\n\n // coalescing signals\n logic [DEPTH-1:0] store_matchvec_lo_r, store_matchvec_hi_r;\n logic store_coalesce_lo_r, store_coalesce_hi_r;\n\n //----------------------------------------\n // Logic starts here\n //----------------------------------------\n // Create high/low byte enables\n assign store_byteen_ext_r[7:0] = ldst_byteen_r[7:0] << lsu_addr_r[1:0];\n assign store_byteen_hi_r[BYTE_WIDTH-1:0] = store_byteen_ext_r[7:4] & {4{lsu_pkt_r.store}};\n assign store_byteen_lo_r[BYTE_WIDTH-1:0] = store_byteen_ext_r[3:0] & {4{lsu_pkt_r.store}};\n\n assign RdPtrPlus1[DEPTH_LOG2-1:0] = RdPtr[DEPTH_LOG2-1:0] + 1'b1;\n assign WrPtrPlus1[DEPTH_LOG2-1:0] = WrPtr[DEPTH_LOG2-1:0] + 1'b1;\n assign WrPtrPlus2[DEPTH_LOG2-1:0] = WrPtr[DEPTH_LOG2-1:0] + 2'b10;\n\n // ecc error on both hi/lo\n assign dual_stbuf_write_r = ldst_dual_r & store_stbuf_reqvld_r;\n assign ldst_stbuf_reqvld_r = ((lsu_commit_r | lsu_pkt_r.dma) & store_stbuf_reqvld_r);\n\n // Store Buffer coalescing\n for (genvar i=0; i= DEPTH) : (stbuf_specvld_any[3:0] >= (DEPTH-1));\n assign lsu_stbuf_empty_any = (stbuf_numvld_any[3:0] == 4'b0);\n\n // Load forwarding logic from the store queue\n assign cmpaddr_hi_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] = end_addr_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)];\n\n assign cmpaddr_lo_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] = lsu_addr_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)];\n\n always_comb begin: GenLdFwd\n stbuf_fwdbyteen_hi_pre_m[BYTE_WIDTH-1:0] = '0;\n stbuf_fwdbyteen_lo_pre_m[BYTE_WIDTH-1:0] = '0;\n\n for (int i=0; i (lsu_pkt_r.valid & lsu_pkt_r.store & addr_in_dccm_r);\n endproperty\n assert_stbuf_wren_store_dccm: assert property (stbuf_wren_store_dccm) else\n $display(\"Illegal store buffer write\");\n\n`endif\n\nendmodule\n\n" }, { "path": "design/lsu/el2_lsu_trigger.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n//********************************************************************************\n// $Id$\n//\n//\n// Owner:\n// Function: LSU Trigger logic\n// Comments:\n//\n//********************************************************************************\nmodule el2_lsu_trigger\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )(\n input el2_trigger_pkt_t [3:0] trigger_pkt_any, // trigger packet from dec\n input el2_lsu_pkt_t lsu_pkt_m, // lsu packet\n input logic [31:0] lsu_addr_m, // address\n input logic [31:0] store_data_m, // store data\n\n output logic [3:0] lsu_trigger_match_m // match result\n);\n\n logic trigger_enable;\n logic [3:0][31:0] lsu_match_data;\n logic [3:0] lsu_trigger_data_match;\n logic [31:0] store_data_trigger_m;\n logic [31:0] ldst_addr_trigger_m;\n\n // Generate the trigger enable (This is for power)\n always_comb begin\n trigger_enable = 1'b0;\n for (int i=0; i<4; i++) begin\n trigger_enable |= trigger_pkt_any[i].m;\n end\n end\n\n assign store_data_trigger_m[31:0] = {({16{lsu_pkt_m.word}} & store_data_m[31:16]),({8{(lsu_pkt_m.half | lsu_pkt_m.word)}} & store_data_m[15:8]), store_data_m[7:0]} & {32{trigger_enable}};\n assign ldst_addr_trigger_m[31:0] = lsu_addr_m[31:0] & {32{trigger_enable}};\n\n\n for (genvar i=0; i<4; i++) begin : genblock\n assign lsu_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select}} & ldst_addr_trigger_m[31:0]) |\n ({32{trigger_pkt_any[i].select & trigger_pkt_any[i].store}} & store_data_trigger_m[31:0]);\n\n rvmaskandmatch trigger_match (.mask(trigger_pkt_any[i].tdata2[31:0]), .data(lsu_match_data[i][31:0]), .masken(trigger_pkt_any[i].match), .match(lsu_trigger_data_match[i]));\n\n assign lsu_trigger_match_m[i] = lsu_pkt_m.valid & ~lsu_pkt_m.dma & trigger_enable &\n ((trigger_pkt_any[i].store & lsu_pkt_m.store) | (trigger_pkt_any[i].load & lsu_pkt_m.load & ~trigger_pkt_any[i].select)) &\n lsu_trigger_data_match[i];\n end\n\n\nendmodule // el2_lsu_trigger\n" }, { "path": "docs/Makefile", "content": "SPHINXOPTS ?=\nSPHINXBUILD ?= sphinx-build\nSOURCEDIR = source\nBUILDDIR = build\n\n# Catch-all target: route all unknown targets to Sphinx using the \"make mode\" option.\n# $(O) is meant as a shortcut for $(SPHINXOPTS).\n%:\n\t@$(SPHINXBUILD) -M $@ \"$(SOURCEDIR)\" \"$(BUILDDIR)\" $(SPHINXOPTS) $(O)\n\t@bash update_styles.sh \"$(BUILDDIR)\"\n\n" }, { "path": "docs/dashboard-styles/gcov.css", "content": "/* All views: initial background and text color */\n@import url('https://fonts.googleapis.com/css2?family=Roboto:wght@400;700&display=swap');\n\nbody\n{\n color: #E9EBFA;\n background-color: #0E1116;\n padding: 0;\n margin: 0;\n font-family: 'Roboto', sans-serif;\n box-sizing: border-box;\n}\n\n/* * {\n\n} */\n\n/* All views: standard link format*/\na:link\n{\n color: #00D0C9;\n text-decoration: underline;\n font-family: 'Roboto', sans-serif;\n}\n\n/* All views: standard link - visited format */\na:visited\n{\n color: #E9EBFA;\n text-decoration: underline;\n}\n\n/* All views: standard link - activated format */\na:active\n{\n color: #00D0C9;\n color: #E9EBFA;\n text-decoration: underline;\n}\n\nth {\n border: 1px solid;\n}\n\ntd {\n color: #E9EBFA;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3)\n{\nheight: 300px;\n}\n\nbody > center > table td:not(.coverBarOutline){\n border: 1px solid #31363C;\n}\n\nbody > center > table > tbody > tr:nth-child(1) {\n display: none;\n}\n\nbody>table:nth-child(1)>tbody>tr:nth-child(3) {\n display: flex;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td {\nalign-self: center;\npadding: 0 95px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(1) > td.headerValue {\n font-size: 35px;\n}\n\nbody>table:nth-child(1)>tbody>tr:nth-child(3)>td>table>tbody>tr:nth-child(1)>td.headerItem {\n font-weight: 300;\n font-size: 35px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(1) > td.headerValue {\n font-size: 35px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(2) > td.headerItem {\n font-size: 22px;\n font-weight: 300;\n}\n\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(2) > td.headerValue {\n font-size: 22px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(3) > td.headerItem {\n font-size: 22px;\n font-weight: 300;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(3) > td.headerValue {\n font-size: 22px;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(1) {\n position: relative;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(1) > td::before {\n content: url(../../../_static/white.svg);\n position: absolute;\n left: 95px;\n transform: translateY(-15%);\n}\n\ntable {\n border-collapse: collapse;\n width: 100%;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody {\n padding: 0 50px;\n}\n\nbody > center > table > tbody tr {\n width: 19px;\n}\n\n/* All views: main title format */\ntd.title\n{\n background-color: #25292E;\n color: #DFE1F1;\n text-align: center;\n padding-bottom: 10px;\n font-size: 20px;\n font-weight: bold;\n padding: 20px 0;\n}\n\n/* All views: header item format */\ntd.headerItem\n{\n text-align: right;\n padding-right: 6px;\n\n font-weight: bold;\n white-space: nowrap;\n}\n\n/* All views: header item value format */\ntd.headerValue\n{\n text-align: left;\n color: #00D0C9;\n\n font-weight: bold;\n white-space: nowrap;\n}\n\nbody > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(1) > td:nth-child(5)::after {\n content: ' ';\n width: 10px;\n}\n\n/* All views: header item coverage table heading */\ntd.headerCovTableHead\n{\n color: #DFE1F1;\n text-align: center;\n padding-right: 6px;\n padding-left: 6px;\n padding-bottom: 0px;\n font-size: 14px;\n white-space: nowrap;\n}\n\n/* All views: header item coverage table entry */\ntd.headerCovTableEntry\n{\n text-align: right;\n color: #DFE1F1;\n text-align: center;\n background-color: #31363C;\n font-weight: bold;\n white-space: nowrap;\n padding-left: 12px;\n padding-right: 4px;\n}\n\n/* All views: header item coverage table entry for high coverage rate */\ntd.headerCovTableEntryHi\n{\n text-align: right;\n color: #000000;\n\n font-weight: bold;\n white-space: nowrap;\n padding-left: 12px;\n padding-right: 4px;\n background-color: #2FC36E;\n}\n\n/* All views: header item coverage table entry for medium coverage rate */\ntd.headerCovTableEntryMed\n{\n text-align: right;\n color: #000000;\n\n font-weight: bold;\n white-space: nowrap;\n padding-left: 12px;\n padding-right: 4px;\n background-color: #EFAC0A;\n}\n\n/* All views: header item coverage table entry for ow coverage rate */\ntd.headerCovTableEntryLo\n{\n text-align: right;\n color: #DFE1F1;\n text-align: center;\n font-weight: bold;\n white-space: nowrap;\n padding-left: 12px;\n padding-right: 4px;\n background-color: #F21E08;\n}\n\n/* All views: header legend value for legend entry */\ntd.headerValueLeg\n{\n text-align: left;\n color: #000000;\n\n font-size: 80%;\n white-space: nowrap;\n padding-top: 4px;\n}\n\nbody>table:nth-child(1)>tbody>tr:nth-child(2)>td {\n display: none;\n}\n\n/* All views: color of horizontal ruler */\ntd.ruler > img\n{\n height: 1px ;\n width: 100% ;\n background-color: rgba(255, 255, 255, 0.3);\n aspect-ratio: 1 / 1;\n}\n\n/* All views: version string format */\ntd.versionInfo\n{\n text-align: center;\n padding-top: 35px;\n font-style: italic;\n}\n\ntd.versionInfo > a\n{\n color: #00D0C9;\n}\n\n/* Directory view/File view (all)/Test case descriptions:\n table headline format */\ntd.tableHead\n{\n text-align: center;\n color: #ffffff;\n background-color: #0E1116;\n\n font-size: 16px;\n font-weight: bold;\n white-space: nowrap;\n padding-left: 4px;\n padding-right: 4px;\n}\n\nspan.tableHeadSort\n{\n padding-right: 4px;\n}\n\ntd\n{\n align-items: center;\n}\n\ncenter {\n padding: 95px;\n}\n\n/* Directory view/File view (all): filename entry format */\ntd.coverFile\n{\n text-align: left;\n padding-left: 10px;\n padding-right: 20px;\n color: #E9EBFA;\n background-color: #0E1116;\n font-family: monospace;\n}\n\n/* Directory view/File view (all): bar-graph entry format*/\ntd.coverBar\n{\n background-color: #0E1116;\n}\n\n/* Directory view/File view (all): bar-graph outline color */\ntd.coverBarOutline\n{\n background-color: #0E1116;\n display: flex;\n justify-content: center;\n}\n\n/* Directory view/File view (all): percentage entry for files with\n high coverage rate */\ntd.coverPerHi\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #0E1116;\n color: #2FC36E;\n font-weight: bold;\n\n}\n\n/* Directory view/File view (all): line count entry for files with\n high coverage rate */\ntd.coverNumHi\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #0E1116;\n white-space: nowrap;\n\n}\n\n/* Directory view/File view (all): percentage entry for files with\n medium coverage rate */\ntd.coverPerMed\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n color: #EFAC0A;\n background-color: #0E1116;\n font-weight: bold;\n\n}\n\n/* Directory view/File view (all): line count entry for files with\n medium coverage rate */\ntd.coverNumMed\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #0E1116;\n white-space: nowrap;\n\n}\n\n/* Directory view/File view (all): percentage entry for files with\n low coverage rate */\ntd.coverPerLo\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n color: #F21E08;\n background-color: #0E1116;\n font-weight: bold;\n\n}\n\n/* Directory view/File view (all): line count entry for files with\n low coverage rate */\ntd.coverNumLo\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #0E1116;\n white-space: nowrap;\n\n}\n\n/* File view (all): \"show/hide details\" link format */\na.detail:link\n{\n color: #B8D0FF;\n font-size:80%;\n}\n\n/* File view (all): \"show/hide details\" link - visited format */\na.detail:visited\n{\n color: #B8D0FF;\n font-size:80%;\n}\n\n/* File view (all): \"show/hide details\" link - activated format */\na.detail:active\n{\n color: #ffffff;\n font-size:80%;\n}\n\n/* File view (detail): test name entry */\ntd.testName\n{\n text-align: right;\n padding-right: 10px;\n background-color: #dae7fe;\n\n}\n\n/* File view (detail): test percentage entry */\ntd.testPer\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #dae7fe;\n\n}\n\n/* File view (detail): test lines count entry */\ntd.testNum\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #dae7fe;\n\n}\n\n/* Test case descriptions: test name format*/\ndt\n{\n\n font-weight: bold;\n}\n\n/* Test case descriptions: description table body */\ntd.testDescription\n{\n padding-top: 10px;\n padding-left: 30px;\n padding-bottom: 10px;\n padding-right: 30px;\n background-color: #dae7fe;\n}\n\n/* Source code view: function entry */\ntd.coverFn\n{\n text-align: left;\n padding-left: 10px;\n padding-right: 20px;\n color: #284fa8;\n background-color: #dae7fe;\n font-family: monospace;\n}\n\n/* Source code view: function entry zero count*/\ntd.coverFnLo\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #ff0000;\n font-weight: bold;\n\n}\n\n/* Source code view: function entry nonzero count*/\ntd.coverFnHi\n{\n text-align: right;\n padding-left: 10px;\n padding-right: 10px;\n background-color: #dae7fe;\n font-weight: bold;\n\n}\n\n/* Source code view: source code format */\npre.source\n{\n font-family: monospace;\n white-space: pre;\n margin-top: 2px;\n}\n\n/* Source code view: line number format */\nspan.lineNum\n{\n background-color: #efe383;\n}\n\n/* Source code view: format for lines which were executed */\ntd.lineCov,\nspan.lineCov\n{\n background-color: #cad7fe;\n}\n\n/* Source code view: format for Cov legend */\nspan.coverLegendCov\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-bottom: 2px;\n background-color: #cad7fe;\n}\n\n/* Source code view: format for lines which were not executed */\ntd.lineNoCov,\nspan.lineNoCov\n{\n background-color: #ff6230;\n}\n\n/* Source code view: format for NoCov legend */\nspan.coverLegendNoCov\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-bottom: 2px;\n background-color: #ff6230;\n}\n\n/* Source code view (function table): standard link - visited format */\ntd.lineNoCov > a:visited,\ntd.lineCov > a:visited\n{\n color: #000000;\n text-decoration: underline;\n}\n\n/* Source code view: format for lines which were executed only in a\n previous version */\nspan.lineDiffCov\n{\n background-color: #b5f7af;\n}\n\n/* Source code view: format for branches which were executed\n * and taken */\nspan.branchCov\n{\n background-color: #cad7fe;\n}\n\n/* Source code view: format for branches which were executed\n * but not taken */\nspan.branchNoCov\n{\n background-color: #ff6230;\n}\n\n/* Source code view: format for branches which were not executed */\nspan.branchNoExec\n{\n background-color: #ff6230;\n}\n\n/* Source code view: format for the source code heading line */\npre.sourceHeading\n{\n white-space: pre;\n font-family: monospace;\n font-weight: bold;\n margin: 0px;\n}\n\n/* All views: header legend value for low rate */\ntd.headerValueLegL\n{\n\n text-align: center;\n white-space: nowrap;\n padding-left: 4px;\n padding-right: 2px;\n background-color: #ff0000;\n font-size: 80%;\n}\n\n/* All views: header legend value for med rate */\ntd.headerValueLegM\n{\n\n text-align: center;\n white-space: nowrap;\n padding-left: 2px;\n padding-right: 2px;\n background-color: #ffea20;\n font-size: 80%;\n}\n\n/* All views: header legend value for hi rate */\ntd.headerValueLegH\n{\n\n text-align: center;\n white-space: nowrap;\n padding-left: 2px;\n padding-right: 4px;\n background-color: #a7fc9d;\n font-size: 80%;\n}\n\n/* All views except source code view: legend format for low coverage */\nspan.coverLegendCovLo\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-top: 2px;\n background-color: #ff0000;\n}\n\n/* All views except source code view: legend format for med coverage */\nspan.coverLegendCovMed\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-top: 2px;\n background-color: #ffea20;\n}\n\n/* All views except source code view: legend format for hi coverage */\nspan.coverLegendCovHi\n{\n padding-left: 10px;\n padding-right: 10px;\n padding-top: 2px;\n background-color: #a7fc9d;\n}" }, { "path": "docs/dashboard-styles/main.css", "content": "[data-md-color-scheme=\"slate\"] {\n --md-hue: 218;\n --md-default-bg-color: hsla(var(--md-hue), 22%, 7%, 1);\n}\n\n[data-md-color-primary=\"teal\"] {\n --md-primary-fg-color: #25292e;\n}\n\n[data-md-color-scheme=\"slate\"][data-md-color-primary=\"teal\"] {\n --md-typeset-a-color: #00d0c9;\n}\n\n.md-social {\n display: none;\n}\n\n.md-header__option {\n display: none;\n}" }, { "path": "docs/requirements.txt", "content": "Sphinx>=8.0.2,<9\r\nhttps://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip\r\n" }, { "path": "docs/source/adaptations.md", "content": "# Standard RISC-V CSRs with Core-Specific Adaptations\n\nA summary of standard RISC-V control/status registers in CSR space with platform-specific adaptations:\n\n* [](adaptations.md#machine-interrupt-enable-mie-and-machine-interrupt-pending-mip-registers)\n* [](adaptations.md#machine-cause-register-mcause)\n* [](adaptations.md#machine-hardware-thread-id-register-mhartid)\n\nAll reserved and unused bits in these control/status registers must be hardwired to '0'.\nUnless otherwise noted, all read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.\n\n## Machine Interrupt Enable (mie) and Machine Interrupt Pending (mip) Registers\n\nThe standard RISC-V `mie` and `mip` registers hold the machine interrupt enable and interrupt pending bits, respectively.\nSince VeeR EL2 only supports machine and user mode, all supervisor-specific bits are not implemented.\nIn addition, the `mie/mip` registers also host the platform-specific local interrupt enable/pending bits (shown with a gray background in {numref}`tab-machine-interrupt-enable-register` and {numref}`tab-machine-interrupt-pending-register` below).\n\nThe `mie` register is a standard read/write CSR.\n\n:::{list-table} Machine Interrupt Enable Register (mie, at CSR 0x304)\n:name: tab-machine-interrupt-enable-register\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31\n - Reserved\n - R\n - 0\n* - mceie\n - 30\n - Correctable error local interrupt enable\n - R/W\n - 0\n* - mitie0\n - 29\n - Internal timer 0 local interrupt enable\n - R/W\n - 0\n* - mitie1\n - 28\n - Internal timer 1 local interrupt enable\n - R/W\n - 0\n* - Reserved\n - 27:12\n - Reserved\n - R\n - 0\n* - meie\n - 11\n - Machine external interrupt enable\n - R/W\n - 0\n* - Reserved\n - 10:8\n - Reserved\n - R\n - 0\n* - mtie\n - 7\n - Machine timer interrupt enable\n - R/W\n - 0\n* - Reserved\n - 6:4\n - Reserved\n - R\n - 0\n* - msie\n - 3\n - Machine software interrupt enable\n - R/W\n - 0\n* - Reserved\n - 2:0\n - Reserved\n - R\n - 0\n:::\n\nThe `mip` register is a standard read/write CSR.\n\n:::{note}\nAll M-mode interrupt pending bits of the read/write `mip` register are read-only.\n:::\n\n:::{list-table} Machine Interrupt Pending Register (mip, at CSR 0x344)\n:name: tab-machine-interrupt-pending-register\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31\n - Reserved\n - R\n - 0\n* - mceip\n - 30\n - Correctable error local interrupt pending\n - R\n - 0\n* - mitip0\n - 29\n - Internal timer 0 local interrupt pending\n - R\n - 0\n* - mitip1\n - 28\n - Internal timer 1 local interrupt pending\n - R\n - 0\n* - Reserved\n - 27:12\n - Reserved\n - R\n - 0\n* - meip\n - 11\n - Machine external interrupt pending\n - R\n - 0\n* - Reserved\n - 10:8\n - Reserved\n - R\n - 0\n* - mtip\n - 7\n - Machine timer interrupt pending\n - R\n - 0\n* - Reserved\n - 6:4\n - Reserved\n - R\n - 0\n* - msip\n - 3\n - Machine software interrupt pending\n - R\n - 0\n* - Reserved\n - 2:0\n - Reserved\n - R\n - 0\n:::\n\n## Machine Cause Register (mcause)\n\nThe standard RISC-V mcause register indicates the cause for a trap as shown in {numref}`tab-machine-cause-register`, including standard exceptions/interrupts, platform-specific local interrupts (with light gray background), and NMI causes (with dark gray background).\n\nAdditional trap information is provided in the mscause register, see [](memory-map.md#machine-secondary-cause-register-mscause) which allows the determination of the exact cause of a trap for cases where multiple, different conditions share a single trap code.\n\nThe `mcause` register has WLRL (Write Legal value, Read Legal value) behavior.\n\nThis register is a standard read/write CSR.\n\n:::{list-table} Machine Cause Register (mcause, at CSR 0x342)\n:name: tab-machine-cause-register\n:header-rows: 1\n\n* - **Type**\n - **Trap Code**\n - **Value mcause[31:0]**\n - **Description**\n - **Section(s)**\n* - **NMI**\n - N/A\n - 0x0000_0000\n - NMI pin assertion\n - [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* - **Exception**\n - 1\n - 0x0000_0001\n - Instruction access fault\n - [](memory-map.md#unmapped-addresses), [](memory-map.md#uncorrectable-ecc-errors), and [](error-protection.md#error-detection-and-handling)\n* -\n - 2\n - 0x0000_0002\n - Illegal instruction\n - \\-\n* -\n - 3\n - 0x0000_0003\n - Breakpoint\n - \\-\n* -\n - 4\n - 0x0000_0004\n - Load address misaligned\n - [](memory-map.md#misaligned-accesses)\n* -\n - 5\n - 0x0000_0005\n - Load access fault\n - [](memory-map.md#unmapped-addresses), [](memory-map.md#uncorrectable-ecc-errors), and [](error-protection.md#error-detection-and-handling)\n* -\n - 6\n - 0x0000_0006\n - Store/AMO address misaligned\n - [](memory-map.md#misaligned-accesses)\n* -\n - 7\n - 0x0000_0007\n - Store/AMO access fault\n - [](memory-map.md#unmapped-addresses), [](memory-map.md#uncorrectable-ecc-errors), and [](error-protection.md#error-detection-and-handling)\n* -\n - 11\n - 0x0000_000B\n - Environment call from M-mode\n - \\-\n* - **Interrupt**\n - 3\n - 0x8000_0003\n - Machine software interrupt\n - [](memory-map.md#software-interrupts)\n* -\n - 7\n - 0x8000_0007\n - Machine timer [^fn-adaptations-1] interrupt\n - \\-\n* -\n - 11\n - 0x8000_000B\n - Machine external interrupt\n - [](interrupts.md)\n* -\n - 28\n - 0x8000_001C\n - Machine internal timer 1 local interrupt\n - [](timers.md#internal-timer-local-interrupts)\n* -\n - 29\n - 0x8000_001D\n - Machine internal timer 0 local interrupt\n - [](timers.md#internal-timer-local-interrupts)\n* -\n - 30\n - 0x8000_001E\n - Machine correctable error local interrupt\n - [](memory-map.md#correctable-error-local-interrupt)\n* - **NMI**\n - N/A\n - 0xF000_0000\n - Machine D-bus store error NMI\n - [](memory-map.md#imprecise-bus-error-non-maskable-interrupt) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* -\n - N/A\n - 0xF000_0001\n - Machine D-bus non-blocking load error NMI\n - [](memory-map.md#imprecise-bus-error-non-maskable-interrupt) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* -\n - N/A\n - 0xF000_1000\n - Machine Fast Interrupt double-bit ECC error NMI\n - [](interrupts.md#fast-interrupt-redirect) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* -\n - N/A\n - 0xF000_1001\n - Machine Fast Interrupt DCCM region access error NMI\n - [](interrupts.md#fast-interrupt-redirect) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* -\n - N/A\n - 0xF000_1002\n - Machine Fast Interrupt non-DCCM region NMI\n - [](interrupts.md#fast-interrupt-redirect) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n:::\n\n[^fn-adaptations-1]: Core external timer\n\n:::{note}\nAll other values are reserved.\n:::\n\n## Machine Hardware Thread ID Register (mhartid)\n\nThe standard RISC-V `mhartid` register provides the integer ID of the hardware thread running the code.\nHart IDs must be unique.\nHart IDs might not necessarily be numbered contiguously in a multiprocessor system, but at least one hart must have a hart ID of zero.\n\n:::{note}\nIn certain cases, it must be ensured that exactly one hart runs some code (e.g., at reset), hence the requirement for one hart to have a known hart ID of zero.\n:::\n\nThe `mhartid` register is split into two fixed-sized fields.\nThe SoC must provide a hardwired core ID on the `core_id[31:4]` bus.\nThe value provided on that bus sources the `mhartid` register's *coreid* field.\nIf the SoC hosts more than one RISC-V core, each core must have its own unique `core_id` value.\nEach hardware thread of the core has a unique, hardwired thread ID which is reflected in the `mhartid` register's *hartid* field starting at 0x0 up to 0xF.\n\nVeeR EL2 implements a single hardware thread with thread ID 0x0.\n\nThis register is a standard read-only CSR.\n\n:::{list-table} Machine Hardware Thread ID Register (mhartid, at CSR 0xF14)\n:name: tab-machine-hw-thread-id-register\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - coreid\n - 31:4\n - Core ID of this VeeR EL2\n - R\n - `core_id[31:4]` bus value (see {numref}`tab-core-complex-signals`)\n* - hartid\n - 3:0\n - Hardwired per-core hart ID: 0x0: thread 0 (master thread)\n - R\n - 0x0\n:::\n" }, { "path": "docs/source/build-args.md", "content": "# Build Arguments\n\n## Memory Protection Build Arguments\n\n### Memory Protection Build Argument Rules\n\nThe rules for valid memory protection address (INST/DATA_ACCESS_ADDRx) and mask (INST/DATA_ACCESS_MASKx) build arguments are:\n\n* INST/DATA_ACCESS_ADDRx must be 64B-aligned (i.e., 6 least significant bits must be '0')\n* INST/DATA_ACCESS_MASKx must be an integer multiple of 64B minus 1 (i.e., 6 least significant bits must be '1')\n* For INST/DATA_ACCESS_MASKx, all '0' bits (if any) must be left-justified and all '1' bits must be right-justified\n* No bit in INST/DATA_ACCESS_ADDRx may be '1' if the corresponding bit in INST/DATA_ACCESS_MASKx is also '1' (i.e., for each bit position, at most one of the bits in INST/DATA_ACCESS_ADDRx and INST/DATA_ACCESS_MASKx may be '1')\n\n### Memory Protection Build Arguments\n\n* **Instructions**\n * Instruction Access Window *x* (*x* = 0..7)\n * Enable (INST_ACCESS_ENABLEx): 0,1 *(0 = window disabled; 1 = window enabled)*\n * Base address (INST_ACCESS_ADDRx): 0x0000_0000..0xFFFF_FFC0, *see [](build-args.md#memory-protection-build-argument-rules)*\n * Mask (INST_ACCESS_MASKx): 0x0000_003F..0xFFFF_FFFF, *see [](build-args.md#memory-protection-build-argument-rules)*\n* **Data**\n * Data Access Window x (x = 0..7)\n * Enable (DATA_ACCESS_ENABLEx): 0,1 *(0 = window disabled; 1 = window enabled)*\n * Base address (DATA_ACCESS_ADDRx): 0x0000_0000..0xFFFF_FFC0, *see [](build-args.md#memory-protection-build-argument-rules)*\n * Mask (DATA_ACCESS_MASKx): 0x0000_003F..0xFFFF_FFFF, *see [](build-args.md#memory-protection-build-argument-rules)*\n\n## Core Memory-Related Build Arguments\n\n### Core Memories and Memory-Mapped Register Blocks Alignment Rules\n\nPlacement of VeeR EL2's core memories and memory-mapped register blocks in the 32-bit address range is very flexible.\nEach memory or register block may be assigned to any region and within the region's 28-bit address range to any start address on a naturally aligned power-of-two address boundary relative to its own size (i.e., *start_address* = *n × size*, whereas n is a positive integer number).\n\nFor example, the start address of an 8KB-sized DCCM may be 0x0000_0000, 0x0000_2000, 0x0000_4000, 0x0000_6000, etc.\nA memory or register block with a non-power-of-two size must be aligned to the next bigger power-of-two size.\nFor example, the starting address of a 48KB-sized DCCM must aligned to a 64KB boundary, i.e., it may be 0x0000_0000, 0x0001_0000, 0x0002_0000, 0x0003_0000, etc.\n\nAlso, no two memories or register blocks may overlap each other, and no memory or register block may cross a region boundary.\n\nThe start address of the memory or register block is specified with an offset relative to the start address of the region.\n\nThis offset must follow the rules described above.\n\n### Memory-Related Build Arguments\n* **ICCM**\n * Enable (RV_ICCM_ENABLE): 0, 1 *(0 = no ICCM; 1 = ICCM enabled)*\n * Region (RV_ICCM_REGION): 0..15\n * Offset (RV_ICCM_OFFSET): *offset in bytes from start of region satisfying rules in [](build-args.md#core-memories-and-memory-mapped-register-blocks-alignment-rules)*\n * Size (RV_ICCM_SIZE): 4, 8, 16, 32, 64, 128, 256, 512 *(in KB)*\n* **DCCM**\n * Region (RV_DCCM_REGION): 0..15\n * Offset (RV_DCCM_OFFSET): *offset in bytes from start of region satisfying rules in [](build-args.md#core-memories-and-memory-mapped-register-blocks-alignment-rules)*\n * Size (RV_DCCM_SIZE): 4, 8, 16, 32, 48, 64, 128, 256, 512 *(in KB)*\n* **I-Cache**\n * Enable (RV_ICACHE_ENABLE): 0, 1 *(0 = no I-cache; 1 = I-cache enabled)*\n * Size (RV_ICACHE_SIZE): 16, 32, 64, 128, 256 *(in KB)*\n * Protection (RV_ICACHE_ECC): 0, 1 *(0 = parity; 1 = ECC)*\n* **PIC Memory-mapped Control Registers**\n * Region (RV_PIC_REGION): 0..15\n * Offset (RV_PIC_OFFSET): *offset in bytes from start of region satisfying rules in [](build-args.md#core-memories-and-memory-mapped-register-blocks-alignment-rules)*\n * Size (RV_PIC_SIZE): 32, 64, 128, 256 *(in KB)*\n" }, { "path": "docs/source/cache.md", "content": "# Cache Control\n\nThis chapter describes the features to control the VeeR EL2 core's instruction cache (I-cache).\n\n## Features\n\nThe VeeR EL2's I-cache control features are:\n* Flushing the I-cache\n* Capability to enable/disable I-cache\n* Diagnostic access to data, tag, and status information of the I-cache\n\n:::{note}\nThe I-cache is an optional core feature. Instantiation of the I-cache is controlled by the RV_ICACHE_ENABLE build argument.\n:::\n\n## Feature Descriptions\n\n### Cache Flushing\n\nAs described in [](memory-map.md#memory-synchronization-trigger-register-dmst), a debugger may initiate an operation that is equivalent to a `fence.i` instruction by writing a '1' to the *fence_i* field of the `dmst` register.\nAs part of executing this operation, the I-cache is flushed (i.e., all entries in the I-cache are invalidated).\n\n### Enabling/Disabling I-Cache\n\nAs described in [](memory-map.md#region-access-control-register-mrac), each of the 16 memory regions has two control bits which are hosted in the `mrac` register.\nOne of these control bits, *cacheable*, controls if accesses to that region may be cached.\nIf the *cacheable* bits of all 16 regions are set to '0', the I-cache is effectively turned off.\n\n### Diagnostic Access\n\nFor firmware as well as hardware debug, direct access to the raw content of the data array, tag array, and status bits of the I-cache may be important.\nInstructions stored in the cache, the tag of a cache line as well as status information including a line's valid bit and a set's LRU bits can be manipulated.\nIt is also possible to inject a parity/ECC error in the data or tag array to check error recovery.\nFive control registers are used to provide read/write diagnostic access to the two arrays and status bits.\nThe `dicawics` register controls the selection of the array, way, and index of a cache line.\nThe `dicad0/0h/1` and `dicago` registers are used to perform a read or write access to the selected array location.\nSee sections [](cache.md#i-cache-arraywayindex-selection-register-dicawics) - [](cache.md#i-cache-array-go-register-dicago) for more detailed information.\n\n:::{note}\nThe instructions and the tags are stored in parity/ECC-protected SRAM arrays. The status bits are stored in flops.\n:::\n\n## Use Cases\n\nThe I-cache control features can be broadly divided into two categories:\n\n1. Debug Support A few examples how diagnostic accesses ([](cache.md#diagnostic-access)) may be useful for debug:\n * Generating an I-cache dump (e.g., to investigate performance issues).\n * Injecting parity/ECC errors in the data or tag array of the I-cache.\n * Diagnosing stuck-at bits in the data or tag array of the I-cache.\n * Preloading the I-cache if a hardware bug prevents instruction fetching from memory.\n\n2. Performance Evaluation\n * To evaluate the performance advantage of the I-cache, it is useful to run code with and without the cache enabled.\n Enabling and disabling the I-cache ([](cache.md#enablingdisabling-i-cache)) is an essential feature for this.\n\n## Theory Of Operation\n\n### Read a Chunk of an I-cache Cache Line\n\nThe following steps must be performed to read a 64-bit chunk of instruction data and its associated 4 parity / 7 ECC bits in an I-cache cache line:\n\n1. Write array/way/address information which location to access in the I-cache to the `dicawics` register:\n * *array* field: 0 (i.e., I-cache data array),\n * *way* field: way to be accessed (i.e., 0..1 for 2-way or 0..3 for 4-way set-associative cache), and\n * *index* field: index of cache line to be accessed.\n2. Read the `dicago` register which causes a read access from the I-cache data array at the location selected by the dicawics register.\n3. Read the `dicad0` and `dicad0h` registers to get the selected 64-bit cache line chunk (*instr* fields), and read the `dicad1` register to get the associated parity/ECC bits (*parity0/1/2/3* / *ecc* fields).\n\n### Write a Chunk of an I-Cache Cache Line\n\nThe following steps must be performed to write a 64-bit chunk of instruction data and its associated 4 parity / 7 ECC bits in an I-cache cache line:\n1. Write array/way/address information which location to access in the I-cache to the `dicawics` register:\n * *array* field: 0 (i.e., I-cache data array),\n * *way* field: way to be accessed (i.e., 0..1 for 2-way or 0..3 for 4-way set-associative cache), and\n * *index* field: index of cache line to be accessed.\n2. Write the new instruction data to the *instr* fields of the `dicad0` and `dicad0h` registers, and write the calculated correct instruction parity/ECC bits (unless error injection should be performed) to the *parity0/1/2/3* / *ecc* and fields of the dicad1 register.\n3. Write a '1' to the go field of the dicago register which causes a write access to the I-cache data array copying the information stored in the `dicad0/0h/1` registers to the location selected by the `dicawics` register.\n\n### Read or Write a Full I-Cache Cache Line\n\nThe following steps must be performed to read or write instruction data and associated parity/ECC bits of a full Icache cache line:\n\n1. Start with an index naturally aligned to the 64- or 32-byte cache line size (i.e., *index[5:3]* = '000' for 64-byte or *index[4:3]* = '00' for 32-byte).\n2. Perform steps in [](cache.md#read-a-chunk-of-an-i-cache-cache-line) to read or [](cache.md#write-a-chunk-of-an-i-cache-cache-line) to write.\n3. Increment the index.\n4. Go back to step 2.) for a total of 8 (for 64-byte line size) or 4 (for 32-byte line size) iterations.\n\n### Read a Tag and Status Information of an I-cache Cache Line\n\nThe following steps must be performed to read the tag, tag's parity/ECC bit(s), and status information of an I-cache cache line:\n1. Write array/way/address information which location to access in the I-cache to the `dicawics` register:\n * *array* field: 1 (i.e., I-cache tag array and status),\n * *way* field: way to be accessed (i.e., 0..1 for 2-way or 0..3 for 4-way set-associative cache), and\n * *index* field: index of cache line to be accessed.\n2. Read the `dicago` register which causes a read access from the I-cache tag array and status bits at the location selected by the `dicawics` register.\n3. Read the `dicad0` register to get the selected cache line's tag (*tag* field) and valid bit (*valid* field) as well as the set's LRU bits (*lru* field), and read the `dicad1` register to get the tag's parity/ECC bit(s) (*parity0* / *ecc* field).\n\n### Write a Tag and Status Information of an I-Cache Cache Line\n\nThe following steps must be performed to write the tag, tag's parity/ECC bit, and status information of an I-cache cache line:\n\n1. Write array/way/address information which location to access in the I-cache to the `dicawics` register:\n * *array* field: 1 (i.e., I-cache tag array and status),\n * *way* field: way to be accessed (i.e., 0..1 for 2-way or 0..3 for 4-way set-associative cache), and\n * *index* field: index of cache line to be accessed.\n2. Write the new tag, valid, and LRU information to the *tag, valid*, and *lru* fields of the `dicad0` register, and write the calculated correct tag parity/ECC bit (unless error injection should be performed) to the *parity0* / *ecc* field of the `dicad1` register.\n3. Write a '1' to the *go* field of the `dicago` register which causes a write access to the I-cache tag array and status bits copying the information stored in the dicad0/1 registers to the location selected by the `dicawics` register.\n\n## I-Cache Control/Status Registers\n\nA summary of the I-cache control/status registers in CSR address space:\n* [](cache.md#i-cache-arraywayindex-selection-register-dicawics)\n* [](cache.md#i-cache-array-data-0-register-dicad0)\n* [](cache.md#i-cache-array-data-0-high-register-dicad0h)\n* [](cache.md#i-cache-array-data-1-register-dicad1)\n* [](cache.md#i-cache-array-go-register-dicago)\n\nAll reserved and unused bits in these control/status registers must be hardwired to '0'.\nUnless otherwise noted, all read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.\n\n### I-Cache Array/Way/Index Selection Register (dicawics)\n\nThe `dicawics` register is used to select a specific location in either the data array or the tag array / status of the Icache.\nIn addition to selecting the array, the location in the array must be specified by providing the way, and index.\nOnce selected, the `dicad0/0h/1` registers (see [](cache.md#i-cache-array-data-0-register-dicad0), [](cache.md#i-cache-array-data-0-high-register-dicad0h), and [](cache.md#i-cache-array-data-1-register-dicad1)) hold the information read from or to be written to the specified location, and the dicago register (see [](cache.md#i-cache-array-go-register-dicago)) is used to control the read/write access to the specified I-cache array.\n\nThe cache line size of the I-cache is either 64 or 32 bytes.\nThe `dicawics` register addresses a 64-bit chunk of instruction data or a cache line tag with its associated status.\nEach 64-bit instruction data chunk is protected either with four parity bits (each covering 16 consecutive instruction data bits) or with 7-bit ECC (covering all 64 instruction data bits).\nThere are 8 such chunks in a 64-byte or 4 such chunks in a 32-byte cache line.\nEach cache line tag is protected either with a single parity bit or with 5-bit ECC.\n\n:::{note}\nThis register is accessible in **Debug Mode only**. Attempting to access this register in machine mode raises an illegal instruction exception.\n:::\n\nThis register is mapped to the non-standard read-write CSR address space.\n\n:::{list-table} I-Cache Array/Way/Index Selection Register (dicawics, at CSR 0x7C8)\n:name: tab-cache-array-dicawics\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:25\n - Reserved\n - R\n - 0\n* - array\n - 24\n - Array select:\n\n 0: I-cache data array (incl. parity/ECC bits)\n\n 1: I-cache tag array (incl. parity/ECC bits) and status (incl. valid and LRU bits)\n - R/W\n - 0\n* - Reserved\n - 23:22\n - Reserved\n - R\n - 0\n* - way\n - 21:20\n - Way select:\n\n Four-way set-associative cache: *way[21:20]*\n\n Two-way set-associative cache: *way[20]* (*way[21]* reserved, must be 0)\n - R/W\n - 0\n* - Reserved\n - 19:17\n - Reserved\n - R\n - 0\n* - index [^fn-cache-1]\n - 16:3\n - Index address bits select\n\n **Notes:**\n\n - Index bits are right-justified:\n\n \t- For 4-way set-associative cache, *index[16]* and other unused upper bits (for I-cache sizes smaller than 256KB) must be 0\n\n \t- For 2-way set-associative cache, unused upper bits (for I-cache sizes smaller than 256KB) must be 0\n\n - For tag array and status access:\n\n \t- For 64-byte cache line size, bits 5..3 are ignored by hardware\n\n \t- For 32-byte cache line size, bits 4..3 are ignored by hardware\n\n - This field does not have WARL behavior\n - R/W\n - 0\n* - Reserved\n - 2:0\n - Reserved\n - R\n - 0\n:::\n\n[^fn-cache-1]: VeeR EL2’s I-cache supports four- or two-way set-associativity and cache line sizes of 64 or 32 bytes. Each way is subdivided into 2 banks, and each bank is 8 bytes wide. A bank is selected by index[3], and index[2:0] address a byte of the 8-byte wide bank.\n\n### I-Cache Array Data 0 Register (dicad0)\n\nThe `dicad0` register, in combination with the `dicad0h/1` registers (see [](cache.md#i-cache-array-data-0-high-register-dicad0h) and [](cache.md#i-cache-array-data-1-register-dicad1)), is used to store information read from or to be written to the I-cache array location specified with the `dicawics` register (see [](cache.md#i-cache-arraywayindex-selection-register-dicawics)).\nTriggering a read or write access of the I-cache array is controlled by the `dicago` register (see [](cache.md#i-cache-array-go-register-dicago)).\n\nThe layout of the dicad0 register is different for the data array and the tag array / status, as described in {numref}`tab-cache-array-dicad0` below.\n\n:::{note}\nDuring normal operation, the parity/ECC bits over the 64-bit instruction data as well as the tag are generated and checked by hardware.\nHowever, to enable error injection, the parity/ECC bits must be computed by software for I-cache data and tag array diagnostic writes.\n:::\n\n:::{note}\nThis register is accessible in **Debug Mode only**.\nAttempting to access this register in machine mode raises an illegal instruction exception.\n:::\n\nThis register is mapped to the non-standard read-write CSR address space.\n\n:::{list-table} I-Cache Array Data 0 Register (dicad0, at CSR 0x7C9)\n:name: tab-cache-array-dicad0\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset|**\n* - **I-cache data array**\n -\n -\n -\n -\n* - instr\n - 31:0\n - Instruction data\n\n 31:16: instruction data bytes 3/2 (protected by *parity1* / *ecc*)\n\n 15:0: instruction data bytes 1/0 (protected by *parity0* / *ecc*)\n - R/W\n - 0\n* - **I-cache tag array and status bits**\n -\n -\n -\n -\n* - tag\n - 31:11\n - Tag\n\n **Note:**\n\n Tag bits are right-justified; unused higher bits (for I-cache sizes larger than 8KB) must be 0\n - R/W\n - 0\n* - Unused\n - 10:7\n - Unused\n - R/W\n - 0\n* - lru\n - 6:4\n - Pseudo LRU bits (same bits are accessed independent of selected way):\n\n Four-way set-associative cache:\n\n - *lru[4]*: way0/1 / way2/3 selection\n\n \t - 0: way0/1\n\n \t - 1: way2/3\n\n - *lru[5]*: way0 / way1 selection\n\n \t - 0: way0\n\n \t - 1: way1\n\n \t - *lru[6]*: way2 / way3 selection\n\n \t - 0: way2\n\n \t - 1: way3\n\n Two-way set-associative cache:\n\n - *lru[4]*: way0 / way1 selection\n\n \t - 0: way0\n\n \t - 1: way1\n\n\t - *lru[6:5]*: Reserved (must be 0)\n - R/W\n - 0\n* - Unused\n - 3:1\n - Unused\n - R/W\n - 0\n* - valid\n - 0\n - Cache line valid/invalid:\n\n \t - 0: cache line invalid\n\n - 1: cache line valid\n - R/W\n - 0\n:::\n\n### I-Cache Array Data 0 High Register (dicad0h)\n\nThe `dicad0h` register, in combination with the `dicad0` and `dicad1` registers (see [](cache.md#i-cache-array-data-0-register-dicad0) and [](cache.md#i-cache-array-data-1-register-dicad1)), is used to store information read from or to be written to the I-cache array location specified with the `dicawics` register (see [](cache.md#i-cache-arraywayindex-selection-register-dicawics)).\nTriggering a read or write access of the I-cache array is controlled by the dicago register (see [](cache.md#i-cache-array-go-register-dicago)).\nThe layout of the `dicad0h` register is described in {numref}`tab-cache-array-dicad0h` below.\n\n:::{note}\nDuring normal operation, the parity/ECC bits over the 64-bit instruction data as well as the tag are generated and checked by hardware.\nHowever, to enable error injection, the parity/ECC bits must be computed by software for I-cache data and tag array diagnostic writes.\n:::\n\n:::{note}\nThis register is accessible in **Debug Mode only**.\nAttempting to access this register in machine mode raises an illegal instruction exception.\n:::\n\nThis register is mapped to the non-standard read-write CSR address space.\n\n:::{list-table} I-Cache Array Data 0 High Register (dicad0h, at CSR 0x7CC)\n:name: tab-cache-array-dicad0h\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - instr\n - 31:0\n - Instruction data\n\n 31:16: instruction data bytes 7/6 (protected by *parity3* / *ecc*)\n\n 15:0: instruction data bytes 5/4 (protected by *parity2* / *ecc*)\n - R/W\n - 0\n:::\n\n### I-Cache Array Data 1 Register (dicad1)\n\nThe `dicad1` register, in combination with the `dicad0/0h` registers (see [](cache.md#i-cache-array-data-0-register-dicad0) and [](cache.md#i-cache-array-data-0-high-register-dicad0h)), is used to store information read from or to be written to the I-cache array location specified with the `dicawics` register (see [](cache.md#i-cache-arraywayindex-selection-register-dicawics)).\nTriggering a read or write access of the I-cache array is controlled by the `dicago` register (see [](cache.md#i-cache-array-go-register-dicago)).\n\nThe layout of the `dicad1` register is described in {numref}`tab-cache-array-dicad1` below.\n\n:::{note}\nDuring normal operation, the parity/ECC bits over the 64-bit instruction data as well as the tag are generated and checked by hardware.\nHowever, to enable error injection, the parity/ECC bits must be computed by software for I-cache data and tag array diagnostic writes.\n:::\n\n:::{note}\nThis register is accessible in **Debug Mode only**.\nAttempting to access this register in machine mode raises an illegal instruction exception.\n:::\n\nThis register is mapped to the non-standard read-write CSR address space.\n\n:::{list-table} I-Cache Array Data 1 Register (dicad1, at CSR 0x7CA).\n:name: tab-cache-array-dicad1\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - **Parity**\n -\n -\n -\n -\n* - **Instruction data**\n -\n -\n -\n -\n* - Reserved\n - 31:4\n - Reserved\n - R\n - 0\n* - parity3\n - 3\n - Even parity for I-cache data bytes 7/6 (*instr[31:16]* in `dicad0h`)\n - R/W\n - 0\n* - parity2\n - 2\n - Even parity for I-cache data bytes 5/4 (*instr[15:0]* in `dicad0h`)\n - R/W\n - 0\n* - parity1\n - 1\n - Even parity for I-cache data bytes 3/2 (*instr[31:16]* in `dicad0`)\n - R/W\n - 0\n* - parity0\n - 0\n - Even parity for I-cache data bytes 1/0 (*instr[15:0]* in `dicad0`)\n - R/W\n - 0\n* - **Tag**\n -\n -\n -\n -\n* - Reserved\n - 31:1\n - Reserved\n - R\n - 0\n* - parity0\n - 0\n - Even parity for I-cache tag (tag)\n - R/W\n - 0\n* - **ECC**\n -\n -\n -\n -\n* - **Instruction data**\n -\n -\n -\n -\n* - Reserved\n - 31:7\n - Reserved\n - R\n - 0\n* - ecc\n - 6:0\n - ECC for I-cache data bytes 7/6/5/4/3/2/1/0 (*instr[31:0]* in `dicad0h` and *instr[31:0]* in `dicad0`)\n - R/W\n - 0\n* - **Tag**\n -\n -\n -\n -\n* - Reserved\n - 31:5\n - Reserved\n - R\n - 0\n* - ecc\n - 4:0\n - ECC for I-cache tag (tag)\n - R/W\n - 0\n:::\n\n### I-Cache Array Go Register (dicago)\n\nThe `dicago` register is used to trigger a read from or write to the I-cache array location specified with the `dicawics` register (see [](cache.md#i-cache-arraywayindex-selection-register-dicawics)).\nReading the `dicago` register populates the `dicad0/dicad0h/dicad1` registers (see [](cache.md#i-cache-array-data-0-register-dicad0), [](cache.md#i-cache-array-data-0-high-register-dicad0h), and [](cache.md#i-cache-array-data-1-register-dicad1)) with the information read from the I-cache array.\nWriting a '1' to the go field of the dicago register copies the information stored in the dicad0/dicad0h /dicad1 registers to the I-cache array.\nThe layout of the dicago register is described in {numref}`tab-cache-array-dicago` below.\n\n:::{note}\nThis register is accessible in **Debug Mode only**. Attempting to access this register in machine mode raises an illegal instruction exception.\n:::\n\nThe *go* field of the `dicago` register has W1R0 (Write 1, Read 0) behavior, as also indicated in the 'Access' column.\n\nThis register is mapped to the non-standard read-write CSR address space.\n\n:::{list-table} I-Cache Array Go Register (dicago, at CSR 0x7CB)\n:name: tab-cache-array-dicago\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:1\n - Reserved\n - R\n - 0\n* - go\n - 0\n - Read triggers an I-cache read, write-1 triggers an I-cache write\n - R0/W1\n - 0\n:::\n" }, { "path": "docs/source/clocks.md", "content": "# Clock And Reset\n\nThis chapter describes clocking and reset signals used by the VeeR EL2 core complex.\n\n## Features\n\nThe VeeR EL2 core complex's clock and reset features are:\n\n* Support for independent clock ratios for four separate system bus interfaces\n * System bus clock ratios controlled by SoC\n* Single core complex clock input\n * System bus clock ratios controlled by enable signals\n* Single core complex reset signal\n * Ability to reset to Debug Mode\n* Separate Debug Module reset signal\n * Allows to interact with Debug Module when core complex is still in reset\n\n## Clocking\n\n### Regular Operation\n\nThe VeeR EL2 core complex is driven by a single clock (`clk`).\nAll input and output signals, except those listed in {numref}`tab-core-complex-async-signals`, are synchronous to `clk`.\n\nThe core complex provides three master system bus interfaces (for instruction fetch, load/store data, and debug) as well as one slave (DMA) system bus interface.\nThe SoC controls the clock ratio for each system bus interface via the clock enable signal (`*_bus_clk_en`).\nThe clock ratios selected by the SoC may be the same or different for each system bus.\n\n{numref}`fig-data-timing-relationship` depicts the conceptual relationship of the clock (`clk`), system bus enable (`*_bus_clk_en`) used to select the clock ratio for each system bus, and the data (`*data`) of the respective system bus.\n\n:::{figure-md} fig-data-timing-relationship\n![Data Timing Relationship](img/clock_timing.png)\n\nConceptual Clock, Clock-Enable, and Data Timing Relationship\n:::\n\nNote that the clock net is not explicitly buffered, as the clock tree is expected to be synthesized during place-androute.\nThe achievable clock frequency depends on the configuration, the sizes and configuration of I-cache and I/DCCMs, and the silicon implementation technology.\n\n### System Bus-to-Core Clock Ratios\n\n{numref}`fig-1-1-bus2core-clock-ratio` to {numref}`fig-1-8-bus2core-clock-ratio` depict the timing relationships of clock, clock-enable, and data for the supported system bus clock ratios from 1:1 (i.e. the system bus and core run at the same rate) to 1:8 (i.e. the system bus runs eight times slower than the core).\n\n:::{figure-md} fig-1-1-bus2core-clock-ratio\n![1 1 Bus-to-Core Clock Ratio](img/1_1_bus2core_clock_ratio.png)\n\n1:1 System Bus-to-Core Clock Ratio\n:::\n\n:::{figure-md} fig-1-2-bus2core-clock-ratio\n![1 2 Bus-to-Core Clock Ratio](img/1_2_bus2core_clock_ratio.png)\n\n1:2 System Bus-to-Core Clock Ratio\n:::\n\n:::{figure-md} fig-1-3-bus2core-clock-ratio\n![1 3 Bus-to-Core Clock Ratio](img/1_3_bus2core_clock_ratio.png)\n\n1:3 System Bus-to-Core Clock Ratio\n:::\n\n:::{figure-md} fig-1-4-bus2core-clock-ratio\n![1 4 Bus-to-Core Clock Ratio](img/1_4_bus2core_clock_ratio.png)\n\n1:4 System Bus-to-Core Clock Ratio\n:::\n\n:::{figure-md} fig-1-5-bus2core-clock-ratio\n![1 5 Bus-to-Core Clock Ratio](img/1_5_bus2core_clock_ratio.png)\n\n1:5 System Bus-to-Core Clock Ratio\n:::\n\n:::{figure-md} fig-1-6-bus2core-clock-ratio\n![1 6 Bus-to-Core Clock Ratio](img/1_6_bus2core_clock_ratio.png)\n\n1:6 System Bus-to-Core Clock Ratio\n:::\n\n:::{figure-md} fig-1-7-bus2core-clock-ratio\n![1 7 Bus-to-Core Clock Ratio](img/1_7_bus2core_clock_ratio.png)\n\n1:7 System Bus-to-Core Clock Ratio\n:::\n\n:::{figure-md} fig-1-8-bus2core-clock-ratio\n![1 8 Bus-to-Core Clock Ratio](img/1_8_bus2core_clock_ratio.png)\n\n1:8 System Bus-to-Core Clock Ratio\n:::\n\n### Asynchronous Signals\n\n{numref}`tab-core-complex-async-signals` provides a list of signals which are asynchronous to the core clock (`clk`).\nSignals which are inputs to the core complex are synchronized to `clk` in the core complex logic.\nSignals which are outputs of the core complex must be synchronized outside of the core complex logic if the respective receiving clock domain is driven by a different clock than `clk`.\n\nNote that each asynchronous input passes through a two-stage synchronizer.\nThe signal must be asserted for at least two full `clk` cycles to guarantee it is detected by the core complex logic.\nShorter pulses might be dropped by the synchronizer circuit.\n\n:::{list-table} Core Complex Asynchronous Signals\n:name: tab-core-complex-async-signals\n:header-rows: 1\n\n- * Signal\n * Dir\n * Description\n- * **Interrupts**\n *\n *\n- * extintsrc_req[pt.PIC_TOTAL_INT:1]\n * in\n * External interrupts\n- * soft_int\n * in\n * Standard RISC-V software interrupt\n- * timer_int\n * in\n * Standard RISC-V timer interrupt\n- * nmi_int\n * in\n * Non-Maskable Interrupt|\n- * **Power Management Unit (PMU) Interface**\n *\n *\n- * i_cpu_halt_req\n * in\n * PMU halt request to core\n- * i_cpu_run_req\n * in\n * PMU run request to core\n- * **Multi-Processor Controller (MPC) Debug Interface**\n *\n *\n- * mpc_debug_halt_req\n * in\n * MPC debug halt request to core\n- * mpc_debug_run_req\n * in\n * MPC debug run request to core\n- * **JTAG**\n *\n *\n- * jtag_tck\n * in\n * JTAG Test Clock\n- * jtag_tms\n * in\n * JTAG Test Mode Select (synchronous to jtag_tck)\n- * jtag_tdi\n * in\n * JTAG Test Data In (synchronous to jtag_tck)\n- * jtag_trst_n\n * in\n * JTAG Test Reset\n- * jtag_tdo\n * out\n * JTAG Test Data Out (synchronous to jtag_tck)\n:::\n\n## Reset\n\nThe VeeR EL2 core complex provides two reset signals, the core complex reset, see [](#core-complex-reset-rst_l) and the Debug Module reset, see [](#debug-module-reset-dbg_rst_l).\n\n### Core Complex Reset (rst_l)\n\nAs shown in {numref}`fig-clock-reset-timing`, the core complex reset signal (`rst_l`) is active-low, may be asynchronously asserted, but must be synchronously deasserted to avoid any glitches.\nThe `rst_l` input signal is not synchronized to the core clock (`clk`) inside the core complex logic.\nAll core complex flops are reset asynchronously.\n\n:::{figure-md} fig-clock-reset-timing\n![Clock Reset Timing](img/clock_reset_timing.png)\n\nConceptual Clock and Reset Timing Relationship\n:::\n\nNote that the core complex clock (`clk`) must be stable before the core complex reset (`rst_l`) is deasserted.\n\n:::{note}\nFrom a backend perspective, care should be taken during place-and-route optimization steps to adequately build buffer tree and distribution network of the `rst_l` signal. Slew (transition time) targets should be in the same range as functional signals and distribution delays should be closely matched to clock delays, to maintain reasonable latencies and skews. Further, `rst_l` specific timing checks can be performed during final signoff timing to ensure proper functionality, though they are more complex and challenging to model through static timing analysis.\n:::\n\n:::{note}\nThe core complex reset signal resets the entire VeeR EL2 core complex, except the Debug Module.\n:::\n\n### Debug Module Reset (dbg_rst_l)\n\nThe Debug Module reset signal (`dbg_rst_l`) is an active-low signal which resets the VeeR EL2 core complex's Debug Module as well as the synchronizers between the JTAG interface and the core complex.\nThe Debug Module reset signal may be connected to the power-on reset signal of the SoC.\nThis allows an external debugger to interact with the Debug Module when the core complex reset signal (`rst_l`) is still asserted.\n\nIf this layered reset functionality is not required, the `dbg_rst_l` signal may be tied to the `rst_l` signal outside the core complex.\n\n### Debugger Initiating Reset via JTAG Interface\n\nA debugger may also initiate a reset of the core complex logic via the JTAG interface.\nNote that such a reset assertion is not visible to the SoC.\nResetting the core complex while the core is accessing any SoC memory locations may result in unpredictable behavior.\nRecovery may require an assertion of the SoC master reset.\n\n### Core Complex Reset to Debug Mode\n\nThe RISC-V Debug specification [[3]](intro.md#ref-3) states a requirement that the debugger must be able to be in control from the first executed instruction of a program after a reset.\n\nThe `dmcontrol` register, see [](debugging.md#debug-module-control-register-dmcontrol), of the Debug Module controls the core-complex-internal ndmreset (non-debug module reset) signal.\nThis signal resets the core complex (except for the Debug Module and Debug Transport Module).\n\nThe following sequence is used to reset the core and execute the first instruction in Debug Mode (i.e., db-halt state):\n1. Take Debug Module out of reset\n * Set *dmactive* bit of `dmcontrol` register (`dmcontrol` = 0x0000_0001)\n2. Reset core complex\n * Set *ndmreset* bit of `dmcontrol` register (`dmcontrol` = 0x0000_0003)\n3. While in reset, assert halt request with ndmreset still asserted\n * Set *haltreq* bit of `dmcontrol` register (`dmcontrol` = 0x8000_0003)\n4. Take core complex out of reset with halt request still asserted\n * Clear *ndmreset* bit of `dmcontrol` register (`dmcontrol` = 0x8000_0001)\n" }, { "path": "docs/source/complex-ports.md", "content": "# Complex Port List\n\n{numref}`tab-core-complex-signals` lists the core complex signals.\nNot all signals are present in a given instantiation.\nFor example, a core complex can only have one bus interface type (AXI4 or AHB-Lite).\nSignals which are asynchronous to the core complex clock (`clk`) are marked with \"(async)\" in the 'Description' column.\n\n:::{list-table} Core Complex Signals\n:name: tab-core-complex-signals\n\n* - **Signal**\n - **Dir**\n - **Description**\n* - **Clock and Clock Enables**\n -\n -\n* - clk\n - in\n - Core complex clock\n* - ifu_bus_clk_en\n - in\n - IFU master system bus clock enable\n* - lsu_bus_clk_en\n - in\n - LSU master system bus clock enable\n* - dbg_bus_clk_en\n - in\n - Debug master system bus clock enable\n* - dma_bus_clk_en\n - in\n - DMA slave system bus clock enable\n* - **Reset**\n -\n -\n* - rst_l\n - in\n - Core complex reset (excl. Debug Module)\n* - rst_vec[31:1]\n - in\n - Core reset vector\n* - dbg_rst_l\n - in\n - Debug Module reset (incl. JTAG synchronizers)\n* - **Interrupts**\n -\n -\n* - nmi_int\n - in\n - Non-Maskable Interrupt (async)\n* - nmi_vec[31:1]\n - in\n - Non-Maskable Interrupt vector\n* - soft_int\n - in\n - Standard RISC-V software interrupt (async)\n* - timer_int\n - in\n - Standard RISC-V timer interrupt (async)\n* - extintsrc_req[pt.PIC_TOTAL_INT:1]\n - in\n - External interrupts (async)\n* - **Core ID**\n -\n -\n* - core_id[31:4]\n - in\n - Core ID (mapped to `mhartid[31:4]`)\n* - **System Bus Interfaces**\n -\n -\n* - ***AXI4***\n -\n -\n* - ***Instruction Fetch Unit Master AXI4*** [^fn-complex-ports-1]\n -\n -\n* - *Write address channel signals*\n -\n -\n* - ifu_axi_awvalid\n - out\n - Write address valid (hardwired to 0)\n* - ifu_axi_awready\n - in\n - Write address ready\n* - ifu_axi_awid[pt.IFU_BUS_TAG-1:0]\n - out\n - Write address ID\n* - ifu_axi_awaddr[31:0]\n - out\n - Write address\n* - ifu_axi_awlen[7:0]\n - out\n - Burst length\n* - ifu_axi_awsize[2:0]\n - out\n - Burst size\n* - ifu_axi_awburst[1:0]\n - out\n - Burst type\n* - ifu_axi_awlock\n - out\n - Lock type\n* - ifu_axi_awcache[3:0]\n - out\n - Memory type\n* - ifu_axi_awprot[2:0]\n - out\n - Protection type\n* - ifu_axi_awqos[3:0]\n - out\n - Quality of Service (QoS)\n* - ifu_axi_awregion[3:0]\n - out\n - Region identifier\n* - *Write data channel signals*\n -\n -\n* - ifu_axi_wvalid\n - out\n - Write valid (hardwired to 0)\n* - ifu_axi_wready\n - in\n - Write ready\n* - ifu_axi_wdata[63:0]\n - out\n - Write data\n* - ifu_axi_wstrb[7:0]\n - out\n - Write strobes\n* - ifu_axi_wlast\n - out\n - Write last\n* - *Write response channel signals*\n -\n -\n* - ifu_axi_bvalid\n - in\n - Write response valid\n* - ifu_axi_bready\n - out\n - Write response ready (hardwired to 0)\n* - ifu_axi_bid[pt.IFU_BUS_TAG-1:0]\n - in\n - Response ID tag\n* - ifu_axi_bresp[1:0]\n - in\n - Write response\n* - *Read address channel signals*\n -\n -\n* - ifu_axi_arvalid\n - out\n - Read address valid\n* - ifu_axi_arready\n - in\n - Read address ready\n* - ifu_axi_arid[pt.IFU_BUS_TAG-1:0]\n - out\n - Read address ID\n* - ifu_axi_araddr[31:0]\n - out\n - Read address\n* - ifu_axi_arlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - ifu_axi_arsize[2:0]\n - out\n - Burst size (hardwired to 0b011)\n* - ifu_axi_arburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - ifu_axi_arlock\n - out\n - Lock type (hardwired to 0)\n* - ifu_axi_arcache[3:0]\n - out\n - Memory type (hardwired to 0b1111)\n* - ifu_axi_arprot[2:0]\n - out\n - Protection type (hardwired to 0b100)\n* - ifu_axi_arqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - ifu_axi_arregion[3:0]\n - out\n - Region identifier\n* - *Read data channel signals*\n -\n -\n* - ifu_axi_rvalid\n - in\n - Read valid\n* - ifu_axi_rready\n - out\n - Read ready\n* - ifu_axi_rid[pt.IFU_BUS_TAG-1:0]\n - in\n - Read ID tag\n* - ifu_axi_rdata[63:0]\n - in\n - Read data\n* - ifu_axi_rresp[1:0]\n - in\n - Read response\n* - ifu_axi_rlast\n - in\n - Read last\n* - ***Load/Store Unit Master AXI4***\n -\n -\n* - *Write address channel signals*\n -\n -\n* - lsu_axi_awvalid\n - out\n - Write address valid\n* - lsu_axi_awready\n - in\n - Write address ready\n* - lsu_axi_awid[pt.LSU_BUS_TAG-1:0]\n - out\n - Write address ID\n* - lsu_axi_awaddr[31:0]\n - out\n - Write address\n* - lsu_axi_awlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - lsu_axi_awsize[2:0]\n - out\n - Burst size\n* - lsu_axi_awburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - lsu_axi_awlock\n - out\n - Lock type (hardwired to 0)\n* - lsu_axi_awcache[3:0]\n - out\n - Memory type\n* - lsu_axi_awprot[2:0]\n - out\n - Protection type (hardwired to 0b000)\n* - lsu_axi_awqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - lsu_axi_awregion[3:0]\n - out\n - Region identifier\n* - *Write data channel signals*\n -\n -\n* - lsu_axi_wvalid\n - out\n - Write valid\n* - lsu_axi_wready\n - in\n - Write ready\n* - lsu_axi_wdata[63:0]\n - out\n - Write data\n* - lsu_axi_wstrb[7:0]\n - out\n - Write strobes\n* - lsu_axi_wlast\n - out\n - Write last\n* - *Write response channel signals*\n -\n -\n* - lsu_axi_bvalid\n - in\n - Write response valid\n* - lsu_axi_bready\n - out\n - Write response ready\n* - lsu_axi_bid[pt.LSU_BUS_TAG-1:0]\n - in\n - Response ID tag\n* - lsu_axi_bresp[1:0]\n - in\n - Write response\n* - *Read address channel signals*\n -\n -\n* - lsu_axi_arvalid\n - out\n - Read address valid\n* - lsu_axi_arready\n - in\n - Read address ready\n* - lsu_axi_arid[pt.LSU_BUS_TAG-1:0]\n - out\n - Read address ID\n* - lsu_axi_araddr[31:0]\n - out\n - Read address\n* - lsu_axi_arlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - lsu_axi_arsize[2:0]\n - out\n - Burst size\n* - lsu_axi_arburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - lsu_axi_arlock\n - out\n - Lock type (hardwired to 0)\n* - lsu_axi_arcache[3:0]\n - out\n - Memory type\n* - lsu_axi_arprot[2:0]\n - out\n - Protection type (hardwired to 0b000)\n* - lsu_axi_arqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - lsu_axi_arregion[3:0]\n - out\n - Region identifier\n* - *Read data channel signals*\n -\n -\n* - lsu_axi_rvalid\n - in\n - Read valid\n* - lsu_axi_rready\n - out\n - Read ready\n* - lsu_axi_rid[pt.LSU_BUS_TAG-1:0]\n - in\n - Read ID tag\n* - lsu_axi_rdata[63:0]\n - in\n - Read data\n* - lsu_axi_rresp[1:0]\n - in\n - Read response\n* - lsu_axi_rlast\n - in\n - Read last\n* - ***System Bus (Debug) Master AXI4***\n -\n -\n* - *Write address channel signals*\n -\n -\n* - sb_axi_awvalid\n - out\n - Write address valid\n* - sb_axi_awready\n - in\n - Write address ready\n* - sb_axi_awid[pt.SB_BUS_TAG-1:0]\n - out\n - Write address ID (hardwired to 0)\n* - sb_axi_awaddr[31:0]\n - out\n - Write address\n* - sb_axi_awlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - sb_axi_awsize[2:0]\n - out\n - Burst size\n* - sb_axi_awburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - sb_axi_awlock\n - out\n - Lock type (hardwired to 0)\n* - sb_axi_awcache[3:0]\n - out\n - Memory type (hardwired to 0b1111)\n* - sb_axi_awprot[2:0]\n - out\n - Protection type (hardwired to 0b000)\n* - sb_axi_awqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - sb_axi_awregion[3:0]\n - out\n - Region identifier\n* - *Write data channel signals*\n -\n -\n* - sb_axi_wvalid\n - out\n - Write valid\n* - sb_axi_wready\n - in\n - Write ready\n* - sb_axi_wdata[63:0]\n - out\n - Write data\n* - sb_axi_wstrb[7:0]\n - out\n - Write strobes\n* - sb_axi_wlast\n - out\n - Write last\n* - *Write response channel signals*\n -\n -\n* - sb_axi_bvalid\n - in\n - Write response valid\n* - sb_axi_bready\n - out\n - Write response ready\n* - sb_axi_bid[pt.SB_BUS_TAG-1:0]\n - in\n - Response ID tag\n* - sb_axi_bresp[1:0]\n - in\n - Write response\n* - *Read address channel signals*\n -\n -\n* - sb_axi_arvalid\n - out\n - Read address valid\n* - sb_axi_arready\n - in\n - Read address ready\n* - sb_axi_arid[pt.SB_BUS_TAG-1:0]\n - out\n - Read address ID (hardwired to 0)\n* - sb_axi_araddr[31:0]\n - out\n - Read address\n* - sb_axi_arlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - sb_axi_arsize[2:0]\n - out\n - Burst size\n* - sb_axi_arburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - sb_axi_arlock\n - out\n - Lock type (hardwired to 0)\n* - sb_axi_arcache[3:0]\n - out\n - Memory type (hardwired to 0b0000)\n* - sb_axi_arprot[2:0]\n - out\n - Protection type (hardwired to 0b000)\n* - sb_axi_arqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - sb_axi_arregion[3:0]\n - out\n - Region identifier\n* - *Read data channel signals*\n -\n -\n* - sb_axi_rvalid\n - in\n - Read valid\n* - sb_axi_rready\n - out\n - Read ready\n* - sb_axi_rid[pt.SB_BUS_TAG-1:0]\n - in\n - Read ID tag\n* - sb_axi_rdata[63:0]\n - in\n - Read data\n* - sb_axi_rresp[1:0]\n - in\n - Read response\n* - sb_axi_rlast\n - in\n - Read last\n* - ***DMA Slave AXI4***\n -\n -\n* - *Write address channel signals*\n -\n -\n* - dma_axi_awvalid\n - in\n - Write address valid\n* - dma_axi_awready\n - out\n - Write address ready\n* - dma_axi_awid[pt.DMA_BUS_TAG-1:0]\n - in\n - Write address ID\n* - dma_axi_awaddr[31:0]\n - in\n - Write address\n* - dma_axi_awlen[7:0]\n - in\n - Burst length\n* - dma_axi_awsize[2:0]\n - in\n - Burst size\n* - dma_axi_awburst[1:0]\n - in\n - Burst type\n* - dma_axi_awprot[2:0]\n - in\n - Protection type\n* - *Write data channel signals*\n -\n -\n* - dma_axi_wvalid\n - in\n - Write valid\n* - dma_axi_wready\n - out\n - Write ready\n* - dma_axi_wdata[63:0]\n - in\n - Write data\n* - dma_axi_wstrb[7:0]\n - in\n - Write strobes\n* - dma_axi_wlast\n - in\n - Write last\n* - *Write response channel signals*\n -\n -\n* - dma_axi_bvalid\n - out\n - Write response valid\n* - dma_axi_bready\n - in\n - Write response ready\n* - dma_axi_bid[pt.DMA_BUS_TAG-1:0]\n - out\n - Response ID tag\n* - dma_axi_bresp[1:0]\n - out\n - Write response\n* - *Read address channel signals*\n -\n -\n* - dma_axi_arvalid\n - in\n - Read address valid\n* - dma_axi_arready\n - out\n - Read address ready\n* - dma_axi_arid[pt.DMA_BUS_TAG-1:0]\n - in\n - Read address ID\n* - dma_axi_araddr[31:0]\n - in\n - Read address\n* - dma_axi_arlen[7:0]\n - in\n - Burst length\n* - dma_axi_arsize[2:0]\n - in\n - Burst size\n* - dma_axi_arburst[1:0]\n - in\n - Burst type\n* - dma_axi_arprot[2:0]\n - in\n - Protection type\n* - *Read data channel signals*\n -\n -\n* - dma_axi_rvalid\n - out\n - Read valid\n* - dma_axi_rready\n - in\n - Read ready\n* - dma_axi_rid[pt.DMA_BUS_TAG-1:0]\n - out\n - Read ID tag\n* - dma_axi_rdata[63:0]\n - out\n - Read data\n* - dma_axi_rresp[1:0]\n - out\n - Read response\n* - dma_axi_rlast\n - out\n - Read last\n* - ***AHB-Lite***\n -\n -\n* - ***Instruction Fetch Unit Master AHB-Lite***\n -\n -\n* - *Master signals*\n -\n -\n* - haddr[31:0]\n - out\n - System address\n* - hburst[2:0]\n - out\n - Burst type (hardwired to 0b000)\n* - hmastlock\n - out\n - Locked transfer (hardwired to 0)\n* - hprot[3:0]\n - out\n - Protection control\n* - hsize[2:0]\n - out\n - Transfer size\n* - htrans[1:0]\n - out\n - Transfer type\n* - hwrite\n - out\n - Write transfer\n* - *Slave signals*\n -\n -\n* - hrdata[63:0]\n - in\n - Read data\n* - hready\n - in\n - Transfer finished\n* - hresp\n - in\n - Slave transfer response\n* - ***Load/Store Unit Master AHB-Lite***\n -\n -\n* - *Master signals*\n -\n -\n* - lsu_haddr[31:0]\n - out\n - System address\n* - lsu_hburst[2:0]\n - out\n - Burst type (hardwired to 0b000)\n* - lsu_hmastlock\n - out\n - Locked transfer (hardwired to 0)\n* - lsu_hprot[3:0]\n - out\n - Protection control\n* - lsu_hsize[2:0]\n - out\n - Transfer size\n* - lsu_htrans[1:0]\n - out\n - Transfer type\n* - lsu_hwdata[63:0]\n - out\n - Write data\n* - lsu_hwrite\n - out\n - Write transfer\n* - *Slave signals*\n -\n -\n* - lsu_hrdata[63:0]\n - in\n - Read data\n* - lsu_hready\n - in\n - Transfer finished\n* - lsu_hresp\n - in\n - Slave transfer response\n* - ***System Bus (Debug) Master AHB-Lite***\n -\n -\n* - *Master signals*\n -\n -\n* - sb_haddr[31:0]\n - out\n - System address\n* - sb_hburst[2:0]\n - out\n - Burst type (hardwired to 0b000)\n* - sb_hmastlock\n - out\n - Locked transfer (hardwired to 0)\n* - sb_hprot[3:0]\n - out\n - Protection control\n* - sb_hsize[2:0]\n - out\n - Transfer size\n* - sb_htrans[1:0]\n - out\n - Transfer type\n* - sb_hwdata[63:0]\n - out\n - Write data\n* - sb_hwrite\n - out\n - Write transfer\n* - *Slave signals*\n -\n -\n* - sb_hrdata[63:0]\n - in\n - Read data\n* - sb_hready\n - in\n - Transfer finished\n* - sb_hresp\n - in\n - Slave transfer response\n* - ***DMA Slave AHB-Lite***\n -\n -\n* - *Slave signals*\n -\n -\n* - dma_haddr[31:0]\n - in\n - System address\n* - dma_hburst[2:0]\n - in\n - Burst type\n* - dma_hmastlock\n - in\n - Locked transfer\n* - dma_hprot[3:0]\n - in\n - Protection control\n* - dma_hsize[2:0]\n - in\n - Transfer size\n* - dma_htrans[1:0]\n - in\n - Transfer type\n* - dma_hwdata[63:0]\n - in\n - Write data\n* - dma_hwrite\n - in\n - Write transfer\n* - dma_hsel\n - in\n - Slave select\n* - dma_hreadyin\n - in\n - Transfer finished in\n* - *Master signals*\n -\n -\n* - dma_hrdata[63:0]\n - out\n - Read data\n* - dma_hreadyout\n - out\n - Transfer finished\n* - dma_hresp\n - out\n - Slave transfer response\n* - **Power Management Unit (PMU) Interface**\n -\n -\n* - i_cpu_halt_req\n - in\n - PMU halt request to core (async)\n* - o_cpu_halt_ack\n - out\n - Core acknowledgement for PMU halt request\n* - o_cpu_halt_status\n - out\n - Core halted indication\n* - i_cpu_run_req\n - in\n - PMU run request to core (async)\n* - o_cpu_run_ack\n - out\n - Core acknowledgement for PMU run request\n* - **Multi-Processor Controller (MPC) Debug Interface**\n -\n -\n* - mpc_debug_halt_req\n - in\n - MPC debug halt request to core (async)\n* - mpc_debug_halt_ack\n - out\n - Core acknowledgement for MPC debug halt request\n* - mpc_debug_run_req\n - in\n - MPC debug run request to core (async)\n* - mpc_debug_run_ack\n - out\n - Core acknowledgement for MPC debug run request\n* - mpc_reset_run_req\n - in\n - Core start state control out of reset\n* - o_debug_mode_status\n - out\n - Core in Debug Mode indication\n* - debug_brkpt_status\n - out\n - Hardware/software breakpoint indication\n* - **Performance Counter Activity**\n -\n -\n* - dec_tlu_perfcnt0\n - out\n - Performance counter 0 incrementing\n* - dec_tlu_perfcnt1\n - out\n - Performance counter 1 incrementing\n* - dec_tlu_perfcnt2\n - out\n - Performance counter 2 incrementing\n* - dec_tlu_perfcnt3\n - out\n - Performance counter 3 incrementing\n* - **Trace Port** [^fn-complex-ports-2]\n -\n -\n* - trace_rv_i_insn_ip[31:0]\n - out\n - Instruction opcode\n* - trace_rv_i_address_ip[31:0]\n - out\n - Instruction address\n* - trace_rv_i_valid_ip\n - out\n - Instruction trace valid\n* - trace_rv_i_exception_ip\n - out\n - Exception\n* - trace_rv_i_ecause_ip[4:0]\n - out\n - Exception cause\n* - trace_rv_i_interrupt_ip\n - out\n - Interrupt exception\n* - trace_rv_i_tval_ip[31:0]\n - out\n - Exception trap value\n* - **Debug JTAG Port**\n -\n -\n* - jtag_tck\n - in\n - JTAG Test Clock (async)\n* - jtag_tms\n - in\n - JTAG Test Mode Select (async, sync to jtag_tck)\n* - jtag_tdi\n - in\n - JTAG Test Data In (async, sync to jtag_tck)\n* - jtag_trst_n\n - in\n - JTAG Test Reset (async)\n* - jtag_tdo\n - out\n - JTAG Test Data Out (async, sync to jtag_tck)\n* - jtag_id[31:1]\n - in\n - JTAG IDCODE register value (bit 0 tied internally to 1)\n* - **Testing**\n -\n -\n* - scan_mode\n - in\n - May be used to enable logic scan test, if implemented (must be ‘0’ for normal core operation)\n* - mbist_mode\n - in\n - May be used to enable MBIST for core-internal memories, if implemented (should be tied to ‘0’ if not used)\n:::\n\n[^fn-complex-ports-1]: The IFU issues only read, but no write transactions.\nHowever, the IFU write address, data, and response channels are present, but the valid/ready signals are tied off to disable those channels.\n\n[^fn-complex-ports-2]: The core provides trace information for a maximum of one instruction and one interrupt/exception per clock cycle.\nNote that the only information provided for interrupts/exceptions is the cause, the interrupt/exception flag, and the trap value.\nThe core’s trace port busses are minimally sized, but wide enough to deliver all trace information the core may produce in one clock cycle.\nNot provided signals for the upper bits of the interface related to the interrupt slot might have to be tied off in the SoC.\n" }, { "path": "docs/source/conf.py", "content": "from datetime import datetime\n\nfrom antmicro_sphinx_utils.defaults import (\n extensions as default_extensions,\n myst_enable_extensions as default_myst_enable_extensions,\n myst_fence_as_directive as default_myst_fence_as_directive,\n antmicro_html,\n)\n\n# General information about the project.\nproject = u'RISC-V VeeR EL2 Programmer\\'s Reference Manual'\nbasic_filename = u'riscv-veer-el2-prm'\nauthors = u'CHIPS Alliance The Linux Foundation®'\ncopyright = f'{datetime.now().year} {authors}'\n\n# The short X.Y version.\nversion = ''\n# The full version, including alpha/beta/rc tags.\nrelease = ''\n\n# This is temporary before the clash between myst-parser and immaterial is\n# fixed\nsphinx_immaterial_override_builtin_admonitions = False\n\nnumfig = True\n\n# If you need to add extensions just add to those lists\nextensions = default_extensions\nmyst_enable_extensions = default_myst_enable_extensions\nmyst_fence_as_directive = default_myst_fence_as_directive\n\nmyst_substitutions = {\n \"project\": project\n}\n\nmyst_heading_anchors = 4\n\ntoday_fmt = '%Y-%m-%d'\n\ntodo_include_todos=False\n\n# -- Options for HTML output ---------------------------------------------------\n\nhtml_theme = 'sphinx_immaterial'\n\nhtml_last_updated_fmt = today_fmt\n\nhtml_show_sphinx = False\n\n(\n html_logo,\n html_theme_options,\n html_context\n) = antmicro_html()\n\nhtml_theme_options[\"palette\"][0].update({\n \"scheme\": \"slate\",\n \"primary\": \"teal\",\n \"accent\": \"white\",\n})\n\ndef setup(app):\n app.add_css_file('main.css')\n" }, { "path": "docs/source/core-control.md", "content": "# Low-Level Core Control\n\nThis chapter describes some low-level core control registers.\n\n## Control/Status Registers\n\nA summary of platform-specific control/status registers in CSR space:\n\n* Feature Disable Control Register (mfdc), see [](core-control.md#feature-disable-control-register-mfdc)\n* Clock Gating Control Register (mcgc), see [](core-control.md#clock-gating-control-register-mcgc)\n\nAll reserved and unused bits in these control/status registers must be hardwired to '0'.\nUnless otherwise noted, all read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.\n\n### Feature Disable Control Register (mfdc)\n\nThe `mfdc` register hosts low-level core control bits to disable specific features.\nThis may be useful in case a feature intended to increase core performance should prove to have problems.\n\n:::{note}\n`fence.i` instructions are required before and after writes to the `mfdc` register.\n:::\n\n:::{note}\nThe default state of the controllable features is 'enabled'. Firmware may turn off a feature if needed.\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Feature Disable Control Register (mfdc, at CSR 0x7F9). Field Bits Description\n:name: tab-feature-disable-cr\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:19\n - Reserved\n - R\n - 0\n* - dqc\n - 18:16\n - DMA QoS control, see [](memory-map.md#quality-of-service)\n - R/W\n - 7\n* - Reserved\n - 15:13\n - Reserved\n - R\n - 0\n* - td\n - 12\n - Trace disable:\n - 0: enable trace\n - 1: disable trace\n - R/W\n - 0\n* - elfd\n - 11\n - External load-to-load forwarding disable:\n - 0: enable external load-to-load forwarding\n - 1: disable external load-to-load forwarding\n - R/W\n - 0\n* - Reserved\n - 10:9\n - Reserved\n - R\n - 0\n* - cecd\n - 8\n - Core ECC check disable:\n - 0: ICCM/DCCM ECC checking enabled\n - 1: ICCM/DCCM ECC checking disabled\n - R/W\n - 0\n* - Reserved\n - 7\n - Reserved\n - R\n - 0\n* - sepd\n - 6\n - Side effect pipelining disable:\n - 0: side effect loads/stores are pipelined\n - 1: side effect loads/stores block all subsequent bus transactions until load/store response with default value received.\n\n **Note**: Reset value depends on selected bus core build argument\n - R/W\n - 0 (*AHB-Lite*) / 1 (*AXI4*)\n* - Reserved\n - 5:4\n - Reserved\n - R\n - 0\n* - bpd\n - 3\n - Branch prediction disable:\n - 0: enable branch prediction and return address stack\n - 1: disable branch prediction and return address stack\n - R/W\n - 0\n* - wbcd\n - 2\n - Write Buffer (WB) coalescing disable:\n - 0: enable Write Buffer coalescing\n - 1: disable Write Buffer coalescing\n - R/W\n - 0\n* - Reserved\n - 1\n - Reserved\n - R\n - 0\n* - pd\n - 0\n - Pipelining disable:\n - 0: pipelined execution\n - 1: single instruction execution\n - R/W\n - 0\n:::\n\n### Clock Gating Control Register (mcgc)\n\nThe `mcgc` register hosts low-level core control bits to override clock gating for specific units.\nThis may be useful in case a unit intended to be clock gated should prove to have problems when in lower power mode.\n\n:::{note}\nExcept for PIC I/O, the default state of the clock gating overrides is 'disabled'.\nFirmware may turn off clock gating (i.e., set the clock gating override bit) for a specific unit if needed.\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Clock Gating Control Register (mcgc, at CSR 0x7F8). Field Bits Description\n:name: tab-clock-gating-cr\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:10\n - Reserved\n - R\n - 0\n* - picio\n - 9\n - PIC I/O clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 1\n* - misc\n - 8\n - Miscellaneous clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 0\n* - dec\n - 7\n - DEC clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 0\n* - exu\n - 6\n - EXU clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 0\n* - ifu\n - 5\n - IFU clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 0\n* - lsu\n - 4\n - LSU clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 0\n* - bus\n - 3\n - Bus clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 0\n* - pic\n - 2\n - PIC clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 0\n* - dccm\n - 1\n - DCCM clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 0\n* - iccm\n - 0\n - ICCM clock gating override:\n - 0: enable clock gating\n - 1: clock gating override\n - R/W\n - 0\n:::\n" }, { "path": "docs/source/csrs.md", "content": "# CSR Address Map\n\n## Standard RISC-V CSRs\n\n{numref}`tab-veer-el2-core-specific-std-rv-machine-information-csrs` lists the VeeR EL2 core-specific standard RISC-V Machine Information CSRs.\n\n:::{list-table} VeeR EL2 Core-Specific Standard RISC-V Machine Information CSRs\n:name: tab-veer-el2-core-specific-std-rv-machine-information-csrs\n\n* - **Number**\n - **Privilege**\n - **Name**\n - **Description**\n - **Value**\n* - 0x301\n - MRW\n - misa\n - ISA and extensions\n\n **Note**: writes ignored\n - 0x4000_1104\n* - 0xF11\n - MRO\n - mvendorid\n - Vendor ID\n - 0x0000_0045\n* - 0xF12\n - MRO\n - marchid\n - Architecture ID\n - 0x0000_0010\n* - 0xF13\n - MRO\n - mimpid\n - Implementation ID\n - 0x0000_0004\n* - 0xF14\n - MRO\n - mhartid\n - Hardware thread ID\n - see [](adaptations.md#machine-hardware-thread-id-register-mhartid)\n:::\n\n{numref}`tab-veer-el2-std-risc-v-csr-address-map` lists the VeeR EL2 standard RISC-V CSR address map.\n\n:::{list-table} VeeR EL2 Standard RISC-V CSR Address Map\n:name: tab-veer-el2-std-risc-v-csr-address-map\n\n* - **Number**\n - **Privilege**\n - **Name**\n - **Description**\n - **Section**\n* - 0x300\n - MRW\n - mstatus\n - Machine status\n - \\-\n* - 0x304\n - MRW\n - mie\n - Machine interrupt enable\n - [](adaptations.md#machine-interrupt-enable-mie-and-machine-interrupt-pending-mip-registers)\n* - 0x305\n - MRW\n - mtvec\n - Machine trap-handler base address\n - \\-\n* - 0x320\n - MRW\n - mcountinhibit\n - Machine counter-inhibit register\n - [](performance.md#standard-risc-v-registers)\n* - 0x323\n - MRW\n - mhpmevent3\n - Machine performance-monitoring event selector 3\n - [](performance.md#standard-risc-v-registers)\n* - 0x324\n - MRW\n - mhpmevent4\n - Machine performance-monitoring event selector 4\n - [](performance.md#standard-risc-v-registers)\n* - 0x325\n - MRW\n - mhpmevent5\n - Machine performance-monitoring event selector 5\n - [](performance.md#standard-risc-v-registers)\n* - 0x326\n - MRW\n - mhpmevent6\n - Machine performance-monitoring event selector 6\n - [](performance.md#standard-risc-v-registers)\n* - 0x340\n - MRW\n - mscratch\n - Scratch register for machine trap handlers\n - \\-\n* - 0x341\n - MRW\n - mepc\n - Machine exception program counter\n - \\-\n* - 0x342\n - MRW\n - mcause\n - Machine trap cause\n - [](adaptations.md#machine-cause-register-mcause)\n* - 0x343\n - MRW\n - mtval\n - Machine bad address or instruction\n - \\-\n* - 0x344\n - MRW\n - mip\n - Machine interrupt pending\n - [](adaptations.md#machine-interrupt-enable-mie-and-machine-interrupt-pending-mip-registers)\n* - 0x7A0\n - MRW\n - tselect\n - Debug/Trace trigger register select\n - [](debugging.md#trigger-select-register-tselect)\n* - 0x7A1\n - MRW\n - tdata1\n - First Debug/Trace trigger data\n - [](debugging.md#trigger-data-1-register-tdata1)\n* - 0x7A1\n - MRW\n - mcontrol\n - Match control\n - [](debugging.md#match-control-register-mcontrol)\n* - 0x7A2\n - MRW\n - tdata2\n - Second Debug/Trace trigger data\n - [](debugging.md#trigger-data-2-register-tdata2)\n* - 0x7B0\n - DRW\n - dcsr\n - Debug control and status register\n - [](debugging.md#debug-control-and-status-register-dcsr)\n* - 0x7B1\n - DRW\n - dpc\n - Debug PC\n - [](debugging.md#debug-pc-register-dpc)\n* - 0xB00\n - MRW\n - mcycle\n - Machine cycle counter\n - [](performance.md#standard-risc-v-registers)\n* - 0xB02\n - MRW\n - minstret\n - Machine instructions-retired counter\n - [](performance.md#standard-risc-v-registers)\n* - 0xB03\n - MRW\n - mhpmcounter3\n - Machine performance-monitoring counter 3\n - [](performance.md#standard-risc-v-registers)\n* - 0xB04\n - MRW\n - mhpmcounter4\n - Machine performance-monitoring counter 4\n - [](performance.md#standard-risc-v-registers)\n* - 0xB05\n - MRW\n - mhpmcounter5\n - Machine performance-monitoring counter 5\n - [](performance.md#standard-risc-v-registers)\n* - 0xB06\n - MRW\n - mhpmcounter6\n - Machine performance-monitoring counter 6\n - [](performance.md#standard-risc-v-registers)\n* - 0xB80\n - MRW\n - mcycleh\n - Upper 32 bits of mcycle, RV32I only\n - [](performance.md#standard-risc-v-registers)\n* - 0xB82\n - MRW\n - minstreth\n - Upper 32 bits of minstret, RV32I only\n - [](performance.md#standard-risc-v-registers)\n* - 0xB83\n - MRW\n - mhpmcounter3h\n - Upper 32 bits of mhpmcounter3, RV32I only\n - [](performance.md#standard-risc-v-registers)\n* - 0xB84\n - MRW\n - mhpmcounter4h\n - Upper 32 bits of mhpmcounter4, RV32I only\n - [](performance.md#standard-risc-v-registers)\n* - 0xB85\n - MRW\n - mhpmcounter5h\n - Upper 32 bits of mhpmcounter5, RV32I only\n - [](performance.md#standard-risc-v-registers)\n* - 0xB86\n - MRW\n - mhpmcounter6h\n - Upper 32 bits of mhpmcounter6, RV32I only\n - [](performance.md#standard-risc-v-registers)\n:::\n\n## Non-Standard RISC-V CSRs\n\n{numref}`tab-veer-el2-non-std-risc-v-csr-address-map` summarizes the VeeR EL2 non-standard RISC-V CSR address map.\n\n:::{list-table} VeeR EL2 Non-Standard RISC-V CSR Address Map\n:name: tab-veer-el2-non-std-risc-v-csr-address-map\n\n* - **Number**\n - **Privilege**\n - **Name**\n - **Description**\n - **Section**\n* - 0x7C0\n - MRW\n - mrac\n - Region access control\n - [](memory-map.md#region-access-control-register-mrac)\n* - 0x7C2\n - MRW\n - mcpc\n - Core pause control\n - [](power.md#core-pause-control-register-mcpc)\n* - 0x7C4\n - DRW\n - dmst\n - Memory synchronization trigger (Debug Mode only)\n - [](memory-map.md#memory-synchronization-trigger-register-dmst)\n* - 0x7C6\n - MRW\n - mpmc\n - Power management control\n - [](power.md#power-management-control-register-mpmc)\n* - 0x7C8\n - DRW\n - dicawics\n - I-cache array/way/index selection (Debug Mode only)\n - [](cache.md#i-cache-arraywayindex-selection-register-dicawics)\n* - 0x7C9\n - DRW\n - dicad0\n - I-cache array data 0 (Debug Mode only)\n - [](cache.md#i-cache-array-data-0-register-dicad0)\n* - 0x7CA\n - DRW\n - dicad1\n - I-cache array data 1 (Debug Mode only)\n - [](cache.md#i-cache-array-data-1-register-dicad1)\n* - 0x7CB\n - DRW\n - dicago\n - I-cache array go (Debug Mode only)\n - [](cache.md#i-cache-array-go-register-dicago)\n* - 0x7CC\n - DRW\n - dicad0h\n - I-cache array data 0 high (Debug Mode only)\n - [](cache.md#i-cache-array-data-0-high-register-dicad0h)\n* - 0x7CE\n - MRW\n - mfdht\n - Force debug halt threshold\n - [](power.md#forced-debug-halt-threshold-register-mfdht)\n* - 0x7CF\n - MRW\n - mfdhs\n - Force debug halt status\n - [](power.md#forced-debug-halt-status-register-mfdhs)\n* - 0x7D2\n - MRW\n - mitcnt0\n - Internal timer counter 0\n - [](timers.md#internal-timer-counter-0--1-register-mitcnt01)\n* - 0x7D3\n - MRW\n - mitb0\n - Internal timer bound 0\n - [](timers.md#internal-timer-bound-0--1-register-mitb01)\n* - 0x7D4\n - MRW\n - mitctl0\n - Internal timer control 0\n - [](timers.md#internal-timer-control-0--1-register-mitctl01)\n* - 0x7D5\n - MRW\n - mitcnt1\n - Internal timer counter 1\n - [](timers.md#internal-timer-counter-0--1-register-mitcnt01)\n* - 0x7D6\n - MRW\n - mitb1\n - Internal timer bound 1\n - [](timers.md#internal-timer-bound-0--1-register-mitb01)\n* - 0x7D7\n - MRW\n - mitctl1\n - Internal timer control 1\n - [](timers.md#internal-timer-control-0--1-register-mitctl01)\n* - 0x7F0\n - MRW\n - micect\n - I-cache error counter/threshold\n - [](error-protection.md#i-cache-error-counterthreshold-register-micect)\n* - 0x7F1\n - MRW\n - miccmect\n - ICCM correctable error counter/threshold\n - [](error-protection.md#iccm-correctable-error-counterthreshold-register-miccmect)\n* - 0x7F2\n - MRW\n - mdccmect\n - DCCM correctable error counter/threshold\n - [](error-protection.md#dccm-correctable-error-counterthreshold-register-mdccmect)\n* - 0x7F8\n - MRW\n - mcgc\n - Clock gating control\n - [](core-control.md#clock-gating-control-register-mcgc)\n* - 0x7F9\n - MRW\n - mfdc\n - Feature disable control\n - [](core-control.md#feature-disable-control-register-mfdc)\n* - 0x7FF\n - MRW\n - mscause\n - Machine secondary cause\n - [](memory-map.md#machine-secondary-cause-register-mscause)\n* - 0xBC0\n - MRW\n - mdeau\n - D-Bus error address unlock\n - [](memory-map.md#d-bus-error-address-unlock-register-mdeau)\n* - 0xBC8\n - MRW\n - meivt\n - External interrupt vector table\n - [](interrupts.md#external-interrupt-vector-table-register-meivt)\n* - 0xBC9\n - MRW\n - meipt\n - External interrupt priority threshold\n - [](interrupts.md#external-interrupt-priority-threshold-register-meipt)\n* - 0xBCA\n - MRW\n - meicpct\n - External interrupt claim ID / priority level capture trigger\n - [](interrupts.md#external-interrupt-claim-id--priority-level-capture-trigger-register-meicpct)\n* - 0xBCB\n - MRW\n - meicidpl\n - External interrupt claim ID's priority level\n - [](interrupts.md#external-interrupt-claim-ids-priority-level-register-meicidpl)\n* - 0xBCC\n - MRW\n - meicurpl\n - External interrupt current priority level\n - [](interrupts.md#external-interrupt-current-priority-level-register-meicurpl)\n* - 0xFC0\n - MRO\n - mdseac\n - D-bus first error address capture\n - [](memory-map.md#d-bus-first-error-address-capture-register-mdseac)\n* - 0xFC8\n - MRO\n - meihap\n - External interrupt handler address pointer\n - [](interrupts.md#external-interrupt-handler-address-pointer-register-meihap)\n:::\n" }, { "path": "docs/source/debugging.md", "content": "# Debug Support\n\nThe VeeR EL2 core conforms to the \"RISC-V Debug Specification 0.13.2, with JTAG DTM\" document [[3]](intro.md#ref-3).\nThis chapter provides a description of the implemented debug-related control and status register definitions.\nFor a RISC-V debug overview and detailed feature descriptions, refer to corresponding sections in [[3]](intro.md#ref-3).\n\n## Control/Status Registers\n\nThe RISC-V Debug architecture defines three separate address spaces: JTAG, Debug Module Interface, and RISC-V CSR.\nThe registers associated with these three address spaces are described in the following sections:\n* [](debugging.md#controlstatus-registers-in-jtag-address-space)\n* [](debugging.md#controlstatus-registers-in-debug-module-interface-address-space)\n* [](debugging.md#controlstatus-registers-in-risc-v-csr-address-space)\n\n### Control/Status Registers in JTAG Address Space\n\n{numref}`tab-registers-jtag` summarizes the control/status registers in the JTAG Debug Transport Module address space.\n\nAddresses shown below are in the 5-bit JTAG address space.\nA control/status register is addressed by setting the 5bit JTAG IR register.\n\n:::{note}\nThe core complex clock (`clk`) frequency must be at least twice the JTAG clock (`jtag_tck`) frequency for the JTAG data to pass correctly through the clock domain crossing synchronizers.\n:::\n\n:::{list-table} Registers in JTAG Debug Transport Module Address Space\n:name: tab-registers-jtag\n:header-rows: 1\n\n* - **JTAG DTM Address**\n - **Name**\n - **Description**\n - **Section**\n* - 0x01\n - IDCODE\n - TAG IDCODE\n - [](debugging.md#idcode-register-idcode)\n* - 0x10\n - dtmcs\n - DTM control and status\n - [](debugging.md#dtm-control-and-status-register-dtmcs)\n* - 0x11\n - dmi\n - Debug module interface access\n - [](debugging.md#debug-module-interface-access-register-dmi)\n* - 0x1F\n - BYPASS\n - JTAG BYPASS\n - [](debugging.md#bypass-register-bypass)\n:::\n\n#### IDCODE Register (IDCODE)\n\nThe `IDCODE` register is a standard JTAG register.\nIt is selected in the JTAG TAP controller's IR register when the TAP state machine is reset.\nThe `IDCODE` register's definition is exactly as defined in IEEE Std 1149.1-2013.\n\nThis register is read-only.\n\nThis register is mapped to the 5-bit JTAG address space.\n\n:::{list-table} IDCODE Register (IDCODE, at JTAG 0x01)\n:name: tab-idcode-registers\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - version\n - 31:28\n - Identifies release version of this part\n - R\n - `jtag_id[31:28]` value\n\n (see [](complex-ports.md))\n* - partnum\n - 27:12\n - Identifies designer's part number of this part\n - R\n - `jtag_id[27:12]` value\n\n (see [](complex-ports.md))\n* - manufid\n - 11:1\n - Identifies designer/manufacturer of this part\n - R\n - `jtag_id[11:1]` value\n\n (see [](complex-ports.md))\n* - 1\n - 0\n - Must be '1'\n - R\n - 1\n:::\n\n#### DTM Control and Status Register (dtmcs)\n\nThe `dtmcs` register controls and provides status of the Debug Transport Module (DTM).\n\nThis register is mapped to the 5-bit JTAG address space.\n\n:::{list-table} DTM Control and Status Register (dtmcs, at JTAG 0x10)\n:name: tab-dtmcs\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:18\n - Reserved\n - R\n - 0\n* - dmihardreset\n - 17\n - Not implemented\n\n **Note**: Hard reset of DTM not required in VeeR EL2 because DMI accesses always succeed. Writes to this bit ignored.\n - R\n - 0\n* - dmireset\n - 16\n - Not implemented\n\n **Note**: Reset of DTM’s error state not required in VeeR EL2 because DMI accesses always succeed. Writes to this bit ignored.\n - R\n - 0\n* - Reserved\n - 15\n - Reserved\n - R\n - 0\n* - idle\n - 14:12\n - Hint to debugger of minimum number of cycles debugger should spend in Run-Test/Idle after every DMI scan to avoid a ‘busy’ return code (*dmistat* of 3). Debugger must still check *dmistat* when necessary:\n - 0: Not necessary to enter Run-Test/Idle at all.\n\n Other values not implemented.\n - R\n - 0\n* - dmistat\n - 11:10\n - DMI status:\n - 0: No error\n - 1: Reserved\n - 2..3: Not implemented (DMI accesses always succeed)\n - R\n - 0\n* - abits\n - 9:4\n - Size of address field in `dmi` register (see {numref}`tab-dmi`)\n - R\n - 7\n* - version\n - 3:0\n - Conforming to RISC-V Debug specification Version 0.13.2\n - R\n - 1\n:::\n\n#### Debug Module Interface Access Register (dmi)\n\nThe dmi register allows access to the Debug Module Interface (DMI).\nIn the JTAG TAP controller's Update-DR state, the DTM starts the operation specified in the *op* field.\nIn the JTAG TAP controller's Capture-DR state, the DTM updates the *data* field with the result from that operation.\n\n:::{note}\nNo status is reported in the op field. Therefore, debuggers should refrain from batching together multiple scans.\n:::\n\nThis register is mapped to the 5-bit JTAG address space.\n\n:::{list-table} Debug Module Interface Access Register (dmi, at JTAG 0x11)\n:name: tab-dmi\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - address\n - 40:34\n - Address used for DMI access. In Update-DR, value used to access DM over DMI.\n - R/W\n - 0\n* - data\n - 33:2\n - Data to send to DM over DMI during Update-DR, and data returned from DM as result of previous operation.\n - R/W\n - 0\n* - op\n - 1:0\n - For write:\n * 0: Ignore data and address (nop)\n * 1: Read from address (read)\n * 2: Write data to address (write)\n * 3: Not implemented (do not use)\n\n For read:\n * 0: Previous operation completed successfully\n * 1..3: Not implemented (DMI accesses always succeed)\n - R/W\n - 0\n:::\n\n#### BYPASS Register (BYPASS)\n\nThe BYPASS register is a standard JTAG register.\nIt is implemented as a 1-bit register which has no functional effect, except adding a 1-bit delay.\nIt allows a debugger to not communicate with this TAP (i.e., bypass it).\n\n:::{note}\nAll unused addresses in the 5-bit JTAG address space (i.e., all addresses except 0x01 (`IDCODE`), 0x10 (`dtmcs`), and 0x11 (`dmi`)) select the BYPASS register as well.\n:::\n\nThis register is mapped to the 5-bit JTAG address space.\n\n:::{list-table} BYPASS Register (BYPASS, at JTAG 0x1F)\n:name: tab-bypass\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - bypass\n - 0\n - Bypass\n - \\-\n - 0\n:::\n\n### Control/Status Registers in Debug Module Interface Address Space\n\n{numref}`tab-registers-dmi` Summarizes The Control/Status Registers In The Debug Module Interface Address Space.\n\nRegisters in the Debug Module Interface address space are accessed through the `dmi` register in the JTAG address space (see [](debugging.md#debug-module-interface-access-register-dmi)).\nThe *address* field of the `dmi` register selects the Debug Module Interface register to be accessed, the *data* field either provides the value to be written to the selected register or captures that register's value, and the *op* field selects the operation to be performed.\n\nAddresses shown below are offsets relative to the Debug Module base address. VeeR EL2 supports a single Debug Module with a base address of 0x00.\n\n:::{list-table} Registers in Debug Module Interface Address Space\n:name: tab-registers-dmi\n:header-rows: 1\n\n* - **DMI Address**\n - **Name**\n - **Description**\n - **Section**\n* - 0x04\n - data0\n - Abstract data 0\n - [Abstract Data 0 / 1 Registers (data0/1)](debugging.md#abstract-data-0-1-registers-data01)\n* - 0x05\n - data1\n - Abstract data 1\n - [Abstract Data 0 / 1 Registers (data0/1)](debugging.md#abstract-data-0-1-registers-data01)\n* - 0x10\n - dmcontrol\n - Debug module control\n - [System Bus Address 31:0 Register (sbaddress0)](debugging.md#debug-module-control-register-dmcontrol)\n* - 0x11\n - dmstatus\n - Debug module status\n - [](debugging.md#debug-module-status-register-dmstatus)\n* - 0x16\n - abstractcs\n - Abstract control and status\n - [](debugging.md#abstract-control-and-status-register-abstractcs)\n* - 0x17\n - command\n - Abstract command\n - [](debugging.md#abstract-command-register-command)\n* - 0x18\n - abstractauto\n - Abstract command autoexec\n - [](debugging.md#abstract-command-autoexec-register-abstractauto)\n* - 0x38\n - sbcs\n - System bus access control and status\n - [](debugging.md#system-bus-access-control-and-status-register-sbcs)\n* - 0x39\n - sbaddress0\n - System bus address 31:0\n - [](debugging.md#system-bus-address-310-register-sbaddress0)\n* - 0x3C\n - sbdata0\n - System bus data 31:0\n - [](debugging.md#system-bus-data-310-register-sbdata0)\n* - 0x3D\n - sbdata1\n - System bus data 63:32\n - [](debugging.md#system-bus-data-6332-register-sbdata1)\n* - 0x40\n - haltsum0\n - Halt summary 0\n - [](debugging.md#halt-summary-0-register-haltsum0)\n:::\n\n:::{note}\nICCM, DCCM, and PIC memory ranges are only accessible using the access memory abstract command.\n:::\n\n### Debug Module Control Register (dmcontrol)\n\nThe `dmcontrol` register controls the overall Debug Module as well as the hart.\n\n:::{note}\nOn any given write, a debugger may only write '1' to either the *resumereq* or *ackhavereset* bit. The other bit must be written to '0'.\n:::\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} Debug Module Control Register (dmcontrol, at Debug Module Offset 0x10)\n:name: tab-dmcontrol\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - haltreq\n - 31\n - Halt request:\n - 0: Clears halt request bit.\n\n **Note**: May cancel outstanding halt request.\n - 1: Sets halt request bit.\n\n **Note**: Running hart halts whenever halt request bit is set.\n - R0/W\n - 0\n* - resumereq\n - 30\n - Resume request:\n - 0: No effect\n - 1: Causes hart to resume, if halted\n\n **Note**: Also clears resume ack bit for hart.\n\n **Note**: Setting *resumereq* bit is ignored if *haltreq* bit is set.\n - R0/W1\n - 0\n* - hartreset\n - 29\n - Not implemented (i.e., 0: Deasserted)\n - R\n - 0\n* - ackhavereset\n - 28\n - Reset core-internal, sticky `havereset` state:\n - 0: No effect\n - 1: Clear `havereset` state\n - R0/W1\n - 0\n* - Reserved\n - 27\n - Reserved\n - R\n - 0\n* - hasel\n - 26\n - Selects definition of currently selected harts:\n * 0: Single currently selected hart (VeeR EL2 is single-thread)\n - R\n - 0\n* - hartsello\n - 25:16\n - Not implemented (VeeR EL2 is single-thread)\n - R\n - 0\n* - hartselhi\n - 15:6\n - Not implemented (VeeR EL2 is single-thread)\n - R\n - 0\n* - Reserved\n - 5:4\n - Reserved\n - R\n - 0\n* - setresethaltreq\n - 3\n - Not implemented\n\n **Note**: *hasresethaltreq* bit in `dmstatus` register ({numref}`tab-dmstatus`) is ‘0’.\n - R\n - 0\n* - clrresethaltreq\n - 2\n - Not implemented\n\n **Note**: *hasresethaltreq* bit in `dmstatus` register ({numref}`tab-dmstatus`) is ‘0’.\n - R\n - 0\n* - ndmreset\n - 1\n - Controls reset signal from DM to VeeR EL2 core. Signal resets hart, but not DM. To perform a reset, debugger writes ‘1’, and then writes ‘0’ to deassert reset.\n - R/W\n - 0\n* - dmactive\n - 0\n - Reset signal for Debug Module (DM):\n - 0: Module's state takes its reset values\n\n **Note**: Only *dmactive* bit may be written to value other than its reset value. Writes to all other bits of this register are ignored.\n - 1: Module functions normally\n\n Debugger may pulse this bit low to get Debug Module into known state.\n\n **Note**: The core complex’s `dbg_rst_l` signal (see [](complex-ports.md)) resets the Debug Module. It should only be used to reset the Debug Module at power up or possibly with a global reset signal which resets the entire platform.\n - R/W\n - 0\n:::\n\n#### Debug Module Status Register (dmstatus)\n\nThe `dmstatus` register reports status for the overall Debug Module as well as the hart.\n\nThis register is read-only.\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} Debug Module Status Register (dmstatus, at Debug Module Offset 0x11)\n:name: tab-dmstatus\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:23\n - Reserved\n - R\n - 0\n* - impebreak\n - 22\n - Not implemented\n\n **Note**: VeeR EL2 does not implement a Program Buffer.\n - R\n - 0\n* - Reserved\n - 21:20\n - Reserved\n - R\n - 0\n* - allhavereset\n - 19\n - '1' when hart has been reset and reset has not been acknowledged\n - R\n - \\-\n* - anyhavereset\n - 18\n - '1' when hart has been reset and reset has not been acknowledged\n - R\n - \\-\n* - allresumeack\n - 17\n - '1' when hart has acknowledged last resume request\n - R\n - \\-\n* - anyresumeack\n - 16\n - '1' when hart has acknowledged last resume request\n - R\n - \\-\n* - allnonexistent\n - 15\n - Not implemented (VeeR EL2 is single-thread)\n - R\n - 0\n* - anynonexistent\n - 14\n - Not implemented (VeeR EL2 is single-thread)\n - R\n - 0\n* - allunavail\n - 13\n - '1' when hart is unavailable [^fn-debugging-1]\n - R\n - \\-\n* - anyunavail\n - 12\n - '1' when hart is unavailable [^fn-debugging-1]\n - R\n - \\-\n* - allrunning\n - 11\n - '1' when hart is running\n - R\n - \\-\n* - anyrunning\n - 10\n - '1' when hart is running\n - R\n - \\-\n* - allhalted\n - 9\n - '1' when hart is halted\n - R\n - \\-\n* - anyhalted\n - 8\n - '1' when hart is halted\n - R\n - \\-\n* - authenticated\n - 7\n - Not implemented (i.e., 1: Always authenticated)\n - R\n - 1\n* - authbusy\n - 6\n - Not implemented (i.e., 0: Authentication module never busy)\n - R\n - 0\n* - hasresethaltreq\n - 5\n - Not implemented\n\n **Note**: VeeR EL2 implements halt-on-reset with *haltreq* set out of reset method.\n - R\n - 0\n* - confstrptrvalid\n - 4\n - Not implemented\n\n **Note**: VeeR EL2 does not provide information relevant to configuration string.\n - R\n - 0\n* - version\n - 3:0\n - Debug Module present, conforming to RISC-V Debug specification Version 0.13.2\n - R\n - 2\n:::\n\n[^fn-debugging-1]: Hart is in reset or ndmreset bit of dmstatus register is ‘1’.\n\n#### Halt Summary 0 Register (haltsum0)\n\nEach bit in the `haltsum0` register indicates whether a specific hart is halted or not.\nSince VeeR EL2 is singlethreaded, only one bit is implemented.\n\n:::{note}\nUnavailable/nonexistent harts are not considered to be halted.\n:::\n\nThis register is read-only.\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} Halt Summary 0 Register (haltsum0, at Debug Module Offset 0x40)\n:name: tab-haltsum0\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:1\n - Reserved\n - R\n - 0\n* - halted\n - 0\n - '1' when hart halted\n - R\n - 0\n:::\n\n#### Abstract Control and Status Register (abstractcs)\n\nThe `abstractcs` register provides status information of the abstract command interface and enables clearing of detected command errors.\n\n:::{note}\nWriting this register while an abstract command is executing causes its *cmderr* field to be set to '1' (i.e., 'busy'), if it is '0'.\n:::\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} Abstract Control and Status Register (abstractcs, at Debug Module Offset 0x16)\n:name: tab-abstractcs\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:29\n - Reserved\n - R\n - 0\n* - progbufsize\n - 28:24\n - Not implemented\n\n **Note**: VeeR EL2 does not implement a Program Buffer.\n - R\n - 0\n* - Reserved\n - 23:13\n - Reserved\n - R\n - 0\n* - busy\n - 12\n - Abstract command interface activity:\n\n - 0: Abstract command interface idle\n\n - 1: Abstract command currently being executed\n\n **Note**: ‘Busy’ indication set when command register (see [](debugging.md#abstract-command-register-command)) is written, cleared after command has completed.\n - R\n - 0\n* - Reserved\n - 11\n - Reserved\n - R\n - 0\n* - cmderr\n - 10:8\n - Set if abstract command fails.\n\n Reason for failure:\n - 0 (none): No error\n - 1 (busy): Abstract command was executing when `command`, `abstractcs`, or `abstractauto` register was written, or when `data0` or `data1` register was read or written\n - 2 (not supported): Requested command or option not supported, regardless of whether hart is running or not (i.e., illegal command, access register command not word-sized or postexec bit set, or access memory command size larger than word)\n - 3 (exception): Exception occurred while executing abstract command (i.e., illegal register address, address outside of ICCM/DCCM/PIC memory range but in internal memory region, ICCM/DCCM uncorrectable ECC error, or ICCM/PIC access not word-sized)\n - 4 (halt/resume): Abstract command couldn't execute because hart wasn't in required state (running/halted), or unavailable\n - 5 (bus): Abstract command failed for SoC memory access due to bus error (e.g., unmapped address, uncorrectable error, incorrect alignment, or unsupported access size)\n - 6: Reserved\n - 7 (other): Register or memory access size not 32 bits wide or unaligned\n\n **Note**: Bits in this field remain set until cleared by writing ‘111’.\n\n **Note**: Next abstract command not started until value is reset to ‘0’.\n\n **Note**: Only contains valid value if *busy* is ‘0’.\n - R/W1C\n - 0\n* - Reserved\n - 7:4\n - Reserved\n - R\n - 0\n* - datacount\n - 3:0\n - 2 data registers implemented as part of abstract command interface\n - R\n - 2\n:::\n\n### Abstract Command Register (command)\n\nWrites to the command register `cause` the corresponding abstract command to be executed.\n\nWriting this register while an abstract command is executing causes the *cmderr* field in the abstractcs register (see [](debugging.md#abstract-control-and-status-register-abstractcs)) to be set to '1' (i.e., 'busy'), if it is '0'.\nIf the *cmderr* field is non-zero, writes to the command register are ignored.\n\n:::{note}\nA non-zero *cmderr* field inhibits starting a new abstract command to accommodate debuggers which, for performance reasons, may send several commands to be executed in a row without checking the *cmderr* field in between. Checking the *cmderr* field only at the end of a sequence of commands is safe because later commands which might depend on a previous, but failed command are not executed.\n:::\n\n:::{note}\nAccess register and access memory abstract commands may only be executed when the core is in the debug halt (db-halt) state. If the debugger is requesting the execution of an abstract command while the core is not in the debug halt state, the command is aborted and the *cmderr* field is set to '4' (i.e., 'halt/resume'), if it is '0'.\n:::\n\n:::{note}\nThe access memory abstract command method provides access to ICCM, DCCM, and PIC memory ranges as well as to SoC memories.\n:::\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} Abstract Command Register (command, at Debug Module Offset 0x17)\n:name: tab-command\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - cmdtype\n - 31:24\n - Abstract command type:\n - 0: Access Register Command\n - 2: Access Memory Command\n\n **Note**: Other values not implemented or reserved for future use. Writing this field to value different than ‘0’ or ‘2’ causes abstract command to fail and *cmderr* field of `abstractcs` register to be set to ‘2’.\n - R0/W\n - 0\n* - **Access Register Command**\n -\n -\n -\n -\n* - Reserved\n - 23\n - Reserved\n - R\n - 0\n* - aarsize\n - 22:20\n - Register access size:\n - 2: 32-bit access\n\n **Note**: Other size values not implemented. Writing this field to value different than ‘2’ causes abstract command to fail and *cmderr* field of `abstractcs` register to be set to ‘2’, except if transfer is ‘0’.\n - R/W\n - 2\n* - aarpostincrement\n - 19\n - Access register post-increment control:\n - 0: No post-increment\n - 1: After every successful access register command completion, increment *regno* field (wrapping around to 0)\n - R/W\n - 0\n* - postexec\n - 18\n - Not implemented (i.e., 0: No effect)\n\n **Note**: Writing to ‘1’ causes abstract command to fail and *cmderr* field of `abstractcs` register to be set to ‘2’.\n - R\n - 0\n* - transfer\n - 17\n - Transfer:\n - 0: Do not perform operation specified by write\n\n **Note**: Selection of unimplemented options (except for *aarsize* and *regno* fields) causes cmderr field of `abstractcs` register to be set to ‘2’.\n - 1: Perform operation specified by write\n\n **Note**: Selection of unimplemented options causes abstract command to fail and *cmderr* field of `abstractcs` register to be set to ‘2’.\n - R\n - 1\n* - write\n - 16\n - Read or write register:\n - 0 (read): Copy data from register specified in *regno* field into `data0` register ([Abstract Data 0 / 1 Registers (data0/1)](debugging.md#abstract-data-0-1-registers-data0-1))\n - 1 (write): Copy data from `data0` register ([Abstract Data 0 / 1 Registers (data0/1)](debugging.md#abstract-data-0-1-registers-data0-1)) into register specified in *regno* field\n - R0/W\n - 0\n* - regno\n - 15:0\n - Register access:\n - 0x0000 - 0x0FFF: CSRs\n - 0x1000 - 0x101F: GPRs\n - 0x1020 - 0xFFFF: Not implemented or reserved\n\n **Note**: Selecting illegal register address causes abstract command to fail and *cmderr* field of `abstractcs` register to be set to ‘3’, except if transfer is ‘0’.\n - R0/W\n - 0\n* - **Access Memory Command (ICCM, DCCM, PIC, and SoC Memories)**\n -\n -\n -\n -\n* - aamvirtual\n - 23\n - Not implemented (i.e., 0: Addresses are physical)\n\n **Note**: VeeR EL2 supports physical addresses only. Since physical and virtual address are identical, no error is flagged [^fn-debugging-2] even if written to ‘1’.\n - R\n - 0\n* - aamsize\n - 22:20\n - Memory access size:\n - 0: 8-bit access (for DCCM and SoC memories)\n - 1: 16-bit access (for DCCM and SoC memories)\n - 2: 32-bit access (for ICCM, DCCM, PIC, and SoC memories)\n\n **Note**: Writing this field to value ‘0’ or ‘1’ for ICCM or PIC memory access causes abstract command to fail and *cmderr* field of `abstractcs` register to be set to ‘3’.\n\n **Note**: Other size values not implemented. Writing this field to value higher than ‘2’ causes abstract command to fail and *cmderr* field of `abstractcs` register to be set to ‘2’.\n - R/W\n - 2\n* - aampostincrement\n - 19\n - Access memory post-increment control:\n - 0: No post-increment\n - 1: After every successful access memory command completion, increment `data1` register (which contains memory address, see [Abstract Data 0 / 1 Registers (data0/1)](debugging.md#abstract-data-0-1-registers-data0-1)) by number of bytes encoded in *aamsize* field\n - R/W\n - 0\n* - Reserved\n - 18:17\n - Reserved\n - R\n - 0\n* - write\n - 16\n - Read or write memory location:\n * 0 (read): Copy data from memory location specified in data1 register (i.e., address) into data0 register (i.e., data) ([Abstract Data 0 / 1 Registers (data0/1)](debugging.md#abstract-data-0-1-registers-data0-1))\n * 1 (write): Copy data from data0 register (i.e., data) into memory location specified in data1 register (i.e., address) ([Abstract Data 0 / 1 Registers (data0/1)](debugging.md#abstract-data-0-1-registers-data0-1))\n - R0/W\n - 0\n* - target-specific\n - 15:14\n - Not implemented\n\n **Note**: VeeR EL2 does not use target-specific bits.\n - R\n - 0\n* - Reserved\n - 13:0\n - Reserved\n - R\n - 0\n:::\n\n[^fn-debugging-2]: The RISC-V Debug specification [[3]](intro.md#ref-3) states that an implementation must fail accesses that it does not support.\nHowever, the Debug Task Group community agreed in an email exchange on the group’s reflector as well as in a group meeting that not reporting an error is acceptable for implementations without address translation (i.e., the physical address equals the virtual address).\n\n#### Abstract Command Autoexec Register (abstractauto)\n\nThe `abstractauto` register controls if reading or writing the `data0/1` registers (see [Abstract Data 0 / 1 Registers (data0/1)](debugging.md#abstract-data-0-1-registers-data0-1)) automatically triggers the next execution of the abstract command in the `command` register (see [](debugging.md#abstract-command-register-command)).\nThis feature allows more efficient burst accesses.\n\nWriting this register while an abstract command is executing causes the *cmderr* field in the abstractcs register (see [](debugging.md#abstract-control-and-status-register-abstractcs)) to be set to '1' (i.e., 'busy'), if it is '0'.\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} Abstract Command Autoexec Register (abstractauto, at Debug Module Offset 0x18)\n:name: tab-abstractauto\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:2\n - Reserved\n - R\n - 0\n* - autoexecdata1\n - 1\n - Auto-execution control for `data1` register:\n * 0: No automatic triggering of abstract command execution\n * 1: Reading or writing `data1` causes abstract command to be executed again\n - R/W\n - 0\n* - autoexecdata0\n - 0\n - Auto-execution control for `data0` register:\n - 0: No automatic triggering of abstract command execution\n - 1: Reading or writing `data0` causes abstract command to be executed again\n - R/W\n - 0\n:::\n\n### Abstract Data 0 / 1 Registers (data0/1)\n\nThe `data0/1` registers are basic read/write registers which may be read or changed by abstract commands.\n\n:::{note}\nThe *datacount* field of the `abstractcs` register (see {numref}`tab-abstractcs`) indicates that 2 (out of possible 12) registers are implemented in VeeR EL2.\n:::\n\nThe `data0` register sources the value for and provides the return value of an abstract command.\nThe `data1` register provides the address for an access memory abstract command.\n\n:::{note}\nSelecting an address outside of the ICCM, DCCM, or PIC memory range but in one of the core-internal memory regions causes the abstract command to fail and the *cmderr* field of the `abstractcs` register to be set to '3'. Similarly, selecting an unmapped SoC memory address causes the abstract command to fail, provided the SoC responds with a bus error, and the *cmderr* field of the `abstractcs` register to be set to '5'.\n:::\n\nAccessing these registers while an abstract command is executing causes the *cmderr* field of the `abstractcs` register (see {numref}`tab-abstractcs`) to be set to '1' (i.e., 'busy'), if it was '0'.\n\nAttempts to write the `data0/1` registers while the *busy* bit of the abstractcs register (see {numref}`tab-abstractcs`) is set does not change their value.\n\nThe values in these registers may not be preserved after an abstract command has been executed.\nThe only guarantees on their contents are the ones offered by the executed abstract command.\nIf the abstract command fails, no assumptions should be made about the contents of these registers.\n\nThese registers are mapped to the Debug Module Interface address space.\n\n:::{list-table} Abstract Data 0 / 1 Register (data0/1, at Debug Module Offset 0x04 / 0x05)\n:name: tab-data-0-1\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - data\n - 31:0\n - Abstract command data:\n - data0: data value (access register and access memory command)\n - data1: address (access memory command)\n - R/W\n - 0\n:::\n\n#### System Bus Access Control and Status Register (sbcs)\n\nThe `sbcs` register provides controls and status information of the system bus access interface.\n\n:::{note}\nThe system bus access method provides access to SoC memories only. Access to ICCM, DCCM, and PIC memory ranges is only available using the access memory abstract command method.\n:::\n\n:::{note}\nThe operation of the system bus access method does not depend on the core's state. SoC memory locations may be accessed using this method even when the core is running.\n:::\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} System Bus Access Control and Status Register (sbcs, at Debug Module Offset 0x38)\n:name: tab-sbcs\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - sbversion\n - 31:29\n - System Bus interface conforms to RISC-V Debug specification, Version 0.13.2\n - R\n - 1\n* - Reserved\n - 28:23\n - Reserved\n - R\n - 0\n* - sbbusyerror\n - 22\n - Set when debugger attempts to read data while a read is in progress, or when debugger initiates a new access while one is still in progress (i.e., while *sbbusy* bit is set). Remains set until explicitly cleared by debugger.\n\n **Note**: When set, Debug Module cannot initiate more system bus accesses.\n - R/W1C\n - 0\n* - sbbusy\n - 21\n - System bus master interface status:\n * 0: System bus master idle\n * 1: System bus master busy (Set when read or write access requested, remains set until access fully completed)\n\n **Note**: Writes to this register while *sbbusy* bit is set result in undefined behavior. Debugger must not write this register until it reads *sbbusy* bit as ‘0’.\n\n **Note**: Bit reflects if system bus master interface is busy, not status of system bus itself.\n - R\n - 0\n* - sbreadonaddr\n - 20\n - Auto-read on address write:\n - 0: No auto-read on address write\n - 1: Every write to `sbaddress0` (see [](debugging.md#system-bus-address-310-register-sbaddress0)) automatically triggers system bus read at new address\n - R/W\n - 0\n* - sbaccess\n - 19:17\n - Access size for system bus access:\n - 0: 8-bit access\n - 1: 16-bit access\n - 2: 32-bit access\n - 3: 64-bit access\n\n **Note**: Other values not supported. No access performed, *sberror* field set to ‘4’.\n - R/W\n - 2\n* - sbautoincrement\n - 16\n - Auto-address increment:\n - 0: No auto-address increment\n - 1: `sbaddress0` register (see [](debugging.md#system-bus-address-310-register-sbaddress0)) incremented by access size (in bytes) selected in sbaccess field after every successful system bus access\n - R/W\n - 0\n* - sbreadondata\n - 15\n - Auto-read on data read:\n - 0: No auto-read on data read\n - 1: Every read from `sbdata0` register (see [](debugging.md#system-bus-data-310-register-sbdata0)) automatically triggers new system bus read at (possibly auto- incremented) address\n - R/W\n - 0\n* - sberror\n - 14:12\n - Set when Debug Module's system bus master encounters an error: While this field is non-zero, no more system bus accesses can be initiated by the Debug Module.\n - 0: No bus error\n - 1: Not implemented (no timeout)\n - 2: Bad address accessed\n - 3: Alignment error\n - 4: Access of unsupported size requested\n - 5..7: Not implemented (no other error conditions)\n\n **Note**: Bits in this field remain set until cleared by writing ‘111’.\n\n **Note**: Debug Module may not initiate next system bus access until value is reset to ‘0’.\n - R/W1C\n - 0\n* - sbasize\n - 11:5\n - Width of system bus addresses (in bits)\n - R\n - 32\n* - sbaccess128\n - 4\n - 128-bit system bus accesses not supported\n - R\n - 0\n* - sbaccess64\n - 3\n - 64-bit system bus accesses supported\n - R\n - 1\n* - sbaccess32\n - 2\n - 32-bit system bus accesses supported\n - R\n - 1\n* - sbaccess16\n - 1\n - 16-bit system bus accesses supported\n - R\n - 1\n* - sbaccess8\n - 0\n - 8-bit system bus accesses supported\n - R\n - 1\n:::\n\n#### System Bus Address 31:0 Register (sbaddress0)\n\nThe `sbaddress0` register provides the address of the system bus access.\n\nIf the *sbreadonaddr* bit of the `sbcs` register is '1', writing the `sbaddress0` register triggers a system bus read access from the new address.\n\n:::{note}\nThe *sberror* and *sbbusyerror* fields of the `sbcs` register must both be '0' for a system bus read operation to be performed.\n:::\n\n:::{note}\nIf the system bus master interface is busy (i.e., *sbbusy* bit of the `sbcs` register is '1') when a write access to this register is performed, the *sbbusyerror* bit in the `sbcs` register is set and the access is aborted.\n:::\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} System Bus Address 31:0 Register (sbaddress0, at Debug Module Offset 0x39)\n:name: tab-sbaddress0\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - address\n - 31:0\n - System bus address\n - R/W\n - 0\n:::\n\n#### System Bus Data 31:0 Register (sbdata0)\n\nThe `sbdata0` register holds the right-justified lower bits for system bus read and write accesses.\n\nA successful system bus read updates the `sbdata0/1` registers with the value read from the system bus at the memory location addressed by the sbaddress0 register.\nIf the width of the read access is less than 64 bits, the remaining high bits may take on any value.\n\nReading the `sbdata0` register provides the current value of this register.\nIf the *sbreadondata* bit of the sbcs register is '1', reading this register also triggers a system bus read access which updates the `sbdata0/1` registers with the value read from the memory location addressed by the `sbaddress0` register.\n\nWriting the `sbdata0` register triggers a system bus write access which updates the memory location addressed by the `sbaddress0` register with the new values in the `sbdata0/1` registers.\n\n:::{note}\nOnly the `sbdata0` register has this behavior. Accessing the `sbdata1` register has no side effects.\nA debugger must access the `sbdata1` register first, before accessing the sbdata0 register.\n:::\n\n:::{note}\nThe *sberror* and *sbbusyerror* fields of the `sbcs` register must both be '0' for a system bus read or write operation to be performed.\n:::\n\n:::{note}\nIf the system bus master interface is busy (i.e., *sbbusy* bit of the sbcs register is '1') when a read or write access to this register is performed, the *sbbusyerror* bit in the `sbcs` register is set and the access is aborted.\n:::\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} System Bus Data 31:0 Register (sbdata0, at Debug Module Offset 0x3C)\n:name: tab-sbdata0\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - data\n - 31:0\n - System bus data[31:0] for system bus read and write accesses\n - R/W\n - 0\n:::\n\n#### System Bus Data 63:32 Register (sbdata1)\n\nThe `sbdata1` register holds the upper 32 bits of the 64-bit wide system bus for read and write accesses.\n\n:::{note}\nIf the system bus master interface is busy (i.e., *sbbusy* bit of the sbcs register is '1') when a read or write access to this register is performed, the *sbbusyerror* bit in the `sbcs` register is set and the access is aborted.\n:::\n\nThis register is mapped to the Debug Module Interface address space.\n\n:::{list-table} System Bus Data 63:32 Register (sbdata1, at Debug Module Offset 0x3D)\n:name: tab-sbdata1\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - data\n - 31:0\n - System bus data[63:32] for system bus read and write accesses\n - R/W\n - 0\n:::\n\n### Control/Status Registers in RISC-V CSR Address Space\n\nA summary of standard RISC-V control/status registers with platform-specific adaptations in CSR space:\n\n* [](debugging.md#trigger-select-register-tselect)\n* [](debugging.md#trigger-data-1-register-tdata1)\n* [](debugging.md#match-control-register-mcontrol)\n* [](debugging.md#trigger-data-2-register-tdata2)\n* [](debugging.md#debug-control-and-status-register-dcsr)\n* [](debugging.md#debug-pc-register-dpc)\n\nAll reserved and unused bits in these control/status registers must be hardwired to '0'.\nUnless otherwise noted, all read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.\n\n#### Trigger Select Register (tselect)\n\n:::{note}\nSince triggers can be used both by Debug Mode and M-mode, the debugger must restore this register if it modified it.\n:::\n\nThis register is mapped to the standard read/write CSR address space.\n\n:::{list-table} Trigger Select Register (tselect, at CSR 0x7A0)\n:name: tab-tselect\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:2\n - Reserved\n - R\n - 0\n* - index\n - 1:0\n - Index of trigger 0..3\n\n **Note**: Triggers 0 and 2 may be chained, triggers 1 and 3 not.\n - R/W\n - 0\n:::\n\n#### Trigger Data 1 Register (tdata1)\n\nThis register is mapped to the standard read/write CSR address space.\n\n:::{list-table} Trigger Data 1 Register (tdata1, at CSR 0x7A1)\n:name: tab-tdata1\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - type\n - 31:28\n - See {numref}`tab-mcontrol` below.\n - R\n - 2\n* - dmode\n - 27\n - See {numref}`tab-mcontrol` below.\n - See {numref}`tab-mcontrol` below.\n - See {numref}`tab-mcontrol` below.\n* - data\n - 26:0\n - See {numref}`tab-mcontrol` below.\n - See {numref}`tab-mcontrol` below.\n - See {numref}`tab-mcontrol` below. \n:::\n\n#### Match Control Register (mcontrol)\n\n:::{note}\nVeeR EL2 does not support triggering on the data of a load or on the opcode of an executed instruction.\n:::\n\nThis register is mapped to the standard read/write CSR address space.\n\n:::{list-table} Match Control Register (mcontrol, at CSR 0x7A1)\n:name: tab-mcontrol\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - type\n - 31:28\n - Address/data match trigger (= mcontrol)\n - R\n - 2\n* - dmode\n - 27\n - Mode write privileges to `tdata1/2` registers ([](debugging.md#trigger-data-1-register-tdata1) and [](debugging.md#trigger-data-2-register-tdata2)) selected by `tselect` register ([](debugging.md#trigger-select-register-tselect)):\n - 0: Both Debug Mode and M-mode may write `tdata1/2` registers selected by `tselect` register\n - 1: Only Debug Mode may write `tdata1/2` registers selected by `tselect` register. Writes from M-mode are ignored.\n\n **Note**: Only writable from Debug Mode.\n - R/W\n - 0\n* - maskmax\n - 26:21\n - {math}`2^{31}` bytes is largest naturally aligned powers-of-two (NAPOT) range supported by hardware when match field is ‘1’.\n - R\n - 31\n* - hit\n - 20\n - Set by hardware when this trigger matches. Allows to determine which trigger(s) matched. May be set or cleared by trigger’s user at any time.\n\n **Note**: For chained triggers, *hit* bit of a matching second trigger is not set unless first trigger matches as well.\n - R/W\n - 0\n* - select\n - 19\n - Match selection:\n\n 0: Perform match on address\n\n 1: Perform match on store data value\n - R/W\n - 0\n* - timing\n - 18\n - Action for this trigger is taken just before instruction that triggered it is committed, but after all preceding instructions are committed.\n\n **Note**: No bus transaction is issued for an execute address trigger hit on a load to a side-effect address.\n - R\n - 0\n* - sizelo\n - 17:16\n - Match size:\n - 0: Trigger attempts to match against access of any size.\n - Match against address (if select bit is ‘0’)\n - Match against store data (if select bit is ‘1’)\n\n **Note**: Data is zero extended for byte or halfword stores.\n\n **Note**: If *match* bit is ‘1’, the mask in the `tdata2` register is applied independent of the *select* bit value (i.e., in address or data matches).\n\n **Note**: Other match size values not implemented.\n - R\n - 0\n* - action\n - 15:12\n - Action to take when trigger fires:\n - 0: Raise breakpoint exception (used when software wants to use trigger module without external debugger attached)\n - 1: Enter Debug Mode (only supported when trigger's *dmode* bit is ‘1’)\n\n **Note**: Other values reserved for future use.\n\n **Note**: Triggers do not fire if this field is ‘0’ and interrupts are disabled [^fn-debugging-3] (i.e., *mie* bit of `mstatus` standard RISC-V register is ‘0’).\n - R/W\n - 0\n* - chain\n - 11\n - Trigger chaining:\n * 0: When this trigger matches, the configured action is taken.\n * 1: While this trigger does not match, it prevents the trigger with the next index from matching.\n\n **Note**: Supported for triggers 0 and 2 only, attempts to set this bit for triggers 1 and 3 are ignored.\n\n **Note**: In VeeR EL2, only pairs of triggers (i.e., triggers 0/1 and triggers 2/3) are chainable.\n\n **Note**: If *chain* bit of trigger 0/2 is ‘1’, it is chained to trigger 1/3. Only *action* field of trigger 1/3 is used (i.e., *action* field of trigger 0/2 is ignored). The action on second trigger is taken if and only if both triggers in chain match at the same time.\n\n **Note**: Because the *chain* bit affects the next trigger, hardware resets it to ‘0’ for `mcontrol` register writes with *dmode* bit of ‘0’ if the next trigger has a dmode bit of ‘1’. In addition, hardware ignores writes to the mcontrol register which would set the *dmode* bit to ‘1’ if the previous trigger has both a *dmode* bit of ‘0’ and a *chain* bit of ‘1’. Debuggers must avoid the latter case by checking the *chain* bit of the previous trigger when writing the `mcontrol` register.\n - R/W (for triggers 0 and 2) R (for triggers 1 and 3)\n - 0\n* - match\n - 10:7\n - Match control:\n - 0: Matches when value equals `tdata2` register’s ([](debugging.md#trigger-data-2-register-tdata2)) value [^fn-debugging-4]\n - 1: Matches when top *M* bits of value match top *M* bits of `tdata2` register’s ([](debugging.md#trigger-data-2-register-tdata2)) value (*M* is 31 minus the index of least-significant bit containing 0 in `tdata2` register)\n\n **Note**: Other values not implemented or reserved for future use.\n - R/W\n - 0\n* - m\n - 6\n - When set, enable this trigger in M-mode\n - R/W\n - 0\n* - Reserved\n - 5\n - Reserved\n - R\n - 0\n* - s\n - 4\n - Not implemented\n - R\n - 0\n* - u\n - 3\n - Not implemented\n - R\n - 0\n* - execute\n - 2\n - When set, trigger fires on address of executed instruction\n\n **Note**: For writes, written to ‘0’ if *select* bit is written to ‘1’.\n - R/W\n - 0\n* - store\n - 1\n - When set, trigger fires on address or data of store\n - R/W\n - 0\n* - load\n - 0\n - When set, trigger fires on address of load\n\n **Note**: For writes, written to ‘0’ if *select* bit is written to ‘1’.\n - R/W\n - 0\n:::\n\n[^fn-debugging-3]: To enable native debugging of M-mode code, VeeR EL2 implements the simpler but more restrictive solution of preventing triggers with the *action* field set to '0' (i.e., breakpoint exception) while interrupts are disabled, as described in Section 5.1, 'Native M-Mode Triggers' of the RISC-V Debug specification [[3]](intro.md#ref-3).\n[^fn-debugging-4]: Bit 0 of tdata2 register is ignored for instruction address matches.\n\n#### Trigger Data 2 Register (tdata2)\n\nThis register is mapped to the standard read/write CSR address space.\n\n:::{list-table} Trigger Data 2 Register (tdata2, at CSR 0x7A2)\n:name: tab-tdata2\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - value\n - 31:0\n - Match value:\n - Address or data value for match:\n - Address of load, store, or executed instruction [^fn-debugging-4]\n - Data value of store\n - Match mask (see *match* field of `mcontrol` register ({numref}`tab-mcontrol`) set to '1')\n - R/W\n - 0\n:::\n\n#### Debug Control and Status Register (dcsr)\n\nThe `dcsr` register controls the behavior and provides status of the hart in Debug Mode.\n\nThe RISC-V Debug specification [[3]](intro.md#ref-3), Section 4.8.1 documents some required and several optional features.\n{numref}`tab-dcsr` describes the required features, the partial support of optional features in VeeR EL2, and indicates features not supported with \"Not implemented\".\n\n:::{note}\nThis register is accessible in **Debug Mode only**.\nAttempting to access this register in machine mode raises an illegal instruction exception.\n:::\n\nThis register is mapped to the standard read/write CSR address space.\n\n:::{list-table} Debug Control and Status Register (dcsr, at CSR 0x7B0)\n:name: tab-dcsr\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - xdebugver\n - 31:28\n - External debug support exists as described in this chapter and [[3]](intro.md#ref-3)\n - R\n - 4\n* - Reserved\n - 27:16\n - Reserved\n - R\n - 0\n* - ebreakm\n - 15\n -\n * 0: `ebreak` in M-mode behaves as described in RISC-V Privileged specification [[2]](intro.md#ref-2)\n * 1: `ebreak` in M-mode enters Debug Mode\n - R/W\n - 0\n* - Reserved\n - 14\n - Reserved\n - R\n - 0\n* - ebreaks\n - 13\n - Not implemented\n - R\n - 0\n* - ebreaku\n - 12\n - Not implemented\n - R\n - 0\n* - stepie\n - 11\n -\n * 0: Interrupts disabled during single stepping\n * 1: Interrupts enabled during single stepping\n * **Note**: Debugger must not change value while hart is running.\n - R/W\n - 0\n* - stopcount\n - 10\n -\n * 0: Increment counters as usual\n * 1: Don't increment any counters (incl. `cycle` and `instret`) while in Debug Mode or on `ebreak` entering Debug Mode (referred value for most debugging scenarios)\n - R/W\n - 0\n* - stoptime\n - 9\n - Increment timers same as in non-debug mode\n - R\n - 0\n* - cause\n - 8:6\n - Reason for Debug Mode entry (if multiple reasons in single cycle, set cause to highest priority):\n * 1: `ebreak` instruction was executed (*priority 3*)\n * 2: Trigger Module caused a breakpoint exception (*priority 4, highest*)\n * 3: Debugger or MPC interface (see {numref}`tab-veer-el2-multi-core-debug-ctrl-status-signals`) requested entry to ebug Mode using haltreq (*priority 1*)\n * 4: Hart single-stepped because *step* was set (*priority 0, lowest*)\n * 5: Hart halted directly out of reset due to resethaltreq (also acceptable to report '3') (*priority 2*) Other values reserved for future use.\n - R\n - 0\n* - Reserved\n - 5\n - Reserved\n - R\n - 0\n* - mprven\n - 4\n - Not implemented (i.e., 0: *mprv* field in `mstatus` register ignored in Debug Mode)\n - R\n - 0\n* - nmip\n - 3\n - Non-Maskable Interrupt (NMI) pending for hart when set\n\n **Note**: NMI may indicate a hardware error condition, reliable debugging may no longer be possible once bit is set.\n - R\n - 0\n* - step\n - 2\n - When set and not in Debug Mode, hart only executes single instruction and enters Debug Mode. If instruction does not complete due to exception, hart immediately enters Debug Mode before executing trap handler, with appropriate exception registers set.\n\n **Note**: Debugger must not change value while hart is running.\n - R/W\n - 0\n* - prv\n - 1:0\n - Indicates privilege level hart was operating in when Debug Mode was entered (3 = M-mode)\n - R\n - 3\n:::\n\n#### Debug PC Register (dpc)\n\nThe `dpc` register provides the debugger information about the program counter (PC) when entering Debug Mode and control where to resume (RISC-V Debug specification [[3]](intro.md#ref-3), Section 4.8.2).\n\nUpon entry to Debug Mode, the `dpc` register is updated with the address of the next instruction to be executed.\nThe behavior is described in more detail in {numref}`tab-dpc` below.\n\nWhen resuming, the hart's PC is updated to the address stored in the dpc register. A debugger may write the `dpc` register to change where the hart resumes.\n\n:::{note}\nThis register is accessible in **Debug Mode only**. Attempting to access this register in machine mode raises an illegal instruction exception.\n:::\n\nThis register is mapped to the standard read/write CSR address space.\n\n:::{list-table} Debug PC Register (dpc, at CSR 0x7B1)\n:name: tab-dpc\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - dpc\n - 31:0\n - Address captured for:\n\n `ebreak`:\n\n - Address of `ebreak` instruction\n\n Single step:\n\n - Address of instruction which would be executed next if not in Debug Mode (i.e., PC + 4 for 32-bit instructions which don't change program flow, destination PC on taken jumps/branches, etc.)\n\n Trigger module:\n\n If timing (see *timing* bit in `mcontrol` register in {numref}`tab-mcontrol`) is:\n\n - 0: Address of instruction which caused trigger to fire\n\n - 1: Address of next instruction to be executed when Debug Mode was entered\n\n Halt request:\n\n - Address of next instruction to be executed when Debug Mode was entered\n - R/W\n - 0\n:::\n" }, { "path": "docs/source/dual-core-lock-step.md", "content": "# Dual-Core Lockstep (DCLS)\n\nThis chapter describes the proposed Dual-Core Lockstep functionality and its future implementation in the VeeR EL2 Core, as required by Caliptra 2.0 for side-channel mitigation scenarios, although it may be useful for other applications like rad-hardening or other safety related-scenarios which DCLS is often also used for.\n\n## VeeR EL2 DCLS Overview\n\nThe lockstep feature will be added as an optional feature of VeeR EL2, disabled by default.\nIf enabled, another copy of the VeeR EL2 CPU core will be additionally instantiated in the design.\nThis second core will be referred to as a Shadow Core in this chapter.\n\nThe Shadow Core is delayed by a constant, configurable `DELAY` number of clock cycles with regards to the main core.\n\nThe `DCCM` and `ICCM` memories are not duplicated, and only the main VeeR EL2 CPU core has access to them.\nThe Shadow Core is only supplied with the delayed inputs of the main core, including the relevant `DCCM` and `ICCM` data, without any ability to read from or write to those memories by itself.\n\nSimilarly, `Icache` is not duplicated with only the main VeeR EL2 CPU core having direct access.\nThe Shadow Core will receive a delayed copy of main core's `Icache` inputs.\nThe copy of main core's `Icache` outputs will be passed into the `Equivalency Checker` to be validated against the Shadow Core's `Icache` outputs.\n\nThe diagram below outlines the architecture of the proposed solution.\n\n![VeeR DCLS Overview](img/dcls_block_diagram.png)\n\nOutputs and the register file from the main core are delayed by `DELAY` cycles and passed to the `Equivalency Checker` for verification against the outputs and the register file of the Shadow Core.\n\n### Error Policy\n\nThe Dual Core Lockstep module will report an error when detected by asserting a single bit output signal.\nIt is up to the integrator to provide a logic to handle the detected error.\nThe error can be artifficially injected by using [Shadow Core Control](#shadow-core-control) capabilities.\nThe corruption error will be reported always when all of the following requirements are met:\n* Input and Output signals of both Main Core and Shadow Core differ OR an error injection feature is enabled,\n* The Shadow Core is out of reset,\n* The Shadow Core is not disabled.\n\n### Monitored Registers\n\nThe Shadow Core can have its internal copy of the register file by setting a proper VeeR EL2 configuration flag.\nEven though every discrepancy between register files of the Main Core and Shadow Core will eventually lead to difference between IOs of these modules, it might take some time for the mismatch to manifest.\nTo determine whether a discrepancy has occurred immediately, the register files from both cores will be compared taking into account a reasonable subset of the VeeR EL2 registers, as defined in the table below:\n\n:::{list-table} Monitored VeeR EL2 Registers\n:header-rows: 0\n:name: tab-dcls-monitored-veer-el2-registers\n:align: center\n\n* - **Name**\n - **Description**\n* - x1 (ra)\n - Return address\n* - x2 (sp)\n - Stack pointer\n* - x8 (s0/fp)\n - Saved register / frame pointer\n* - x10-x11 (a0-a1)\n - Function arguments / return values\n* - x12-17 (a2-7)\n - Function arguments\n* - pc\n - Program Counter\n* - npc\n - Next Program Counter\n* - mstatus\n - Machine status\n* - [mie](adaptations.md#machine-interrupt-enable-mie-and-machine-interrupt-pending-mip-registers)\n - Machine interrupt enable\n* - mtvec\n - Machine trap-handler base address\n* - mscratch\n - Scratch register for machine trap handlers\n* - mepc\n - Machine exception program counter\n* - [mcause](adaptations.md#machine-cause-register-mcause)\n - Machine trap cause\n* - mtval\n - Machine bad address or instruction\n* - [mip](adaptations.md#machine-interrupt-enable-mie-and-machine-interrupt-pending-mip-registers)\n - Machine interrupt pending\n* - [mcycle](performance.md#standard-risc-v-registers)\n - Machine cycle counter\n* - [minstret](performance.md#standard-risc-v-registers)\n - Machine instructions-retired counter\n* - [mrac](memory-map.md#region-access-control-register-mrac)\n - Region access control\n:::\n\n```{note}\nShould the monitored registers be dependent on the VeeR configuration?\n```\n\n### Monitored IOs\n\nSince the Shadow Core module must replicate the behavior of the Main Core without any differences, it contains the same input and output ports.\nInput ports are delayed and routed to the copy of the VeeR EL2 CPU, output ports are compared with the delayed output ports of the Main Core.\nRefer to {ref}`tab-shadow-core-tracked-signals` for list of ports routed to the Shadow Core.\n\n:::{list-table} Core Complex signals tracked by the Shadow Core\n:name: tab-shadow-core-tracked-signals\n\n* - **Signal**\n - **Dir**\n - **Description**\n* - **Clock Enables**\n -\n -\n* - ifu_bus_clk_en\n - in\n - IFU master system bus clock enable\n* - lsu_bus_clk_en\n - in\n - LSU master system bus clock enable\n* - dbg_bus_clk_en\n - in\n - Debug master system bus clock enable\n* - dma_bus_clk_en\n - in\n - DMA slave system bus clock enable\n* - **Reset**\n -\n -\n* - rst_vec[31:1]\n - in\n - Core reset vector\n* - **Interrupts**\n -\n -\n* - nmi_int\n - in\n - Non-Maskable Interrupt (async)\n* - nmi_vec[31:1]\n - in\n - Non-Maskable Interrupt vector\n* - soft_int\n - in\n - Standard RISC-V software interrupt (async)\n* - timer_int\n - in\n - Standard RISC-V timer interrupt (async)\n* - extintsrc_req[pt.PIC_TOTAL_INT:1]\n - in\n - External interrupts (async)\n* - **Core ID**\n -\n -\n* - core_id[31:4]\n - in\n - Core ID (mapped to `mhartid[31:4]`)\n* - **System Bus Interfaces**\n -\n -\n* - ***AXI4***\n -\n -\n* - ***Instruction Fetch Unit Master AXI4***\n -\n -\n* - *Write address channel signals*\n -\n -\n* - ifu_axi_awvalid\n - out\n - Write address valid (hardwired to 0)\n* - ifu_axi_awready\n - in\n - Write address ready\n* - ifu_axi_awid[pt.IFU_BUS_TAG-1:0]\n - out\n - Write address ID\n* - ifu_axi_awaddr[31:0]\n - out\n - Write address\n* - ifu_axi_awlen[7:0]\n - out\n - Burst length\n* - ifu_axi_awsize[2:0]\n - out\n - Burst size\n* - ifu_axi_awburst[1:0]\n - out\n - Burst type\n* - ifu_axi_awlock\n - out\n - Lock type\n* - ifu_axi_awcache[3:0]\n - out\n - Memory type\n* - ifu_axi_awprot[2:0]\n - out\n - Protection type\n* - ifu_axi_awqos[3:0]\n - out\n - Quality of Service (QoS)\n* - ifu_axi_awregion[3:0]\n - out\n - Region identifier\n* - *Write data channel signals*\n -\n -\n* - ifu_axi_wvalid\n - out\n - Write valid (hardwired to 0)\n* - ifu_axi_wready\n - in\n - Write ready\n* - ifu_axi_wdata[63:0]\n - out\n - Write data\n* - ifu_axi_wstrb[7:0]\n - out\n - Write strobes\n* - ifu_axi_wlast\n - out\n - Write last\n* - *Write response channel signals*\n -\n -\n* - ifu_axi_bvalid\n - in\n - Write response valid\n* - ifu_axi_bready\n - out\n - Write response ready (hardwired to 0)\n* - ifu_axi_bid[pt.IFU_BUS_TAG-1:0]\n - in\n - Response ID tag\n* - ifu_axi_bresp[1:0]\n - in\n - Write response\n* - *Read address channel signals*\n -\n -\n* - ifu_axi_arvalid\n - out\n - Read address valid\n* - ifu_axi_arready\n - in\n - Read address ready\n* - ifu_axi_arid[pt.IFU_BUS_TAG-1:0]\n - out\n - Read address ID\n* - ifu_axi_araddr[31:0]\n - out\n - Read address\n* - ifu_axi_arlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - ifu_axi_arsize[2:0]\n - out\n - Burst size (hardwired to 0b011)\n* - ifu_axi_arburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - ifu_axi_arlock\n - out\n - Lock type (hardwired to 0)\n* - ifu_axi_arcache[3:0]\n - out\n - Memory type (hardwired to 0b1111)\n* - ifu_axi_arprot[2:0]\n - out\n - Protection type (hardwired to 0b100)\n* - ifu_axi_arqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - ifu_axi_arregion[3:0]\n - out\n - Region identifier\n* - *Read data channel signals*\n -\n -\n* - ifu_axi_rvalid\n - in\n - Read valid\n* - ifu_axi_rready\n - out\n - Read ready\n* - ifu_axi_rid[pt.IFU_BUS_TAG-1:0]\n - in\n - Read ID tag\n* - ifu_axi_rdata[63:0]\n - in\n - Read data\n* - ifu_axi_rresp[1:0]\n - in\n - Read response\n* - ifu_axi_rlast\n - in\n - Read last\n* - ***Load/Store Unit Master AXI4***\n -\n -\n* - *Write address channel signals*\n -\n -\n* - lsu_axi_awvalid\n - out\n - Write address valid\n* - lsu_axi_awready\n - in\n - Write address ready\n* - lsu_axi_awid[pt.LSU_BUS_TAG-1:0]\n - out\n - Write address ID\n* - lsu_axi_awaddr[31:0]\n - out\n - Write address\n* - lsu_axi_awlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - lsu_axi_awsize[2:0]\n - out\n - Burst size\n* - lsu_axi_awburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - lsu_axi_awlock\n - out\n - Lock type (hardwired to 0)\n* - lsu_axi_awcache[3:0]\n - out\n - Memory type\n* - lsu_axi_awprot[2:0]\n - out\n - Protection type (hardwired to 0b000)\n* - lsu_axi_awqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - lsu_axi_awregion[3:0]\n - out\n - Region identifier\n* - *Write data channel signals*\n -\n -\n* - lsu_axi_wvalid\n - out\n - Write valid\n* - lsu_axi_wready\n - in\n - Write ready\n* - lsu_axi_wdata[63:0]\n - out\n - Write data\n* - lsu_axi_wstrb[7:0]\n - out\n - Write strobes\n* - lsu_axi_wlast\n - out\n - Write last\n* - *Write response channel signals*\n -\n -\n* - lsu_axi_bvalid\n - in\n - Write response valid\n* - lsu_axi_bready\n - out\n - Write response ready\n* - lsu_axi_bid[pt.LSU_BUS_TAG-1:0]\n - in\n - Response ID tag\n* - lsu_axi_bresp[1:0]\n - in\n - Write response\n* - *Read address channel signals*\n -\n -\n* - lsu_axi_arvalid\n - out\n - Read address valid\n* - lsu_axi_arready\n - in\n - Read address ready\n* - lsu_axi_arid[pt.LSU_BUS_TAG-1:0]\n - out\n - Read address ID\n* - lsu_axi_araddr[31:0]\n - out\n - Read address\n* - lsu_axi_arlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - lsu_axi_arsize[2:0]\n - out\n - Burst size\n* - lsu_axi_arburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - lsu_axi_arlock\n - out\n - Lock type (hardwired to 0)\n* - lsu_axi_arcache[3:0]\n - out\n - Memory type\n* - lsu_axi_arprot[2:0]\n - out\n - Protection type (hardwired to 0b000)\n* - lsu_axi_arqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - lsu_axi_arregion[3:0]\n - out\n - Region identifier\n* - *Read data channel signals*\n -\n -\n* - lsu_axi_rvalid\n - in\n - Read valid\n* - lsu_axi_rready\n - out\n - Read ready\n* - lsu_axi_rid[pt.LSU_BUS_TAG-1:0]\n - in\n - Read ID tag\n* - lsu_axi_rdata[63:0]\n - in\n - Read data\n* - lsu_axi_rresp[1:0]\n - in\n - Read response\n* - lsu_axi_rlast\n - in\n - Read last\n* - ***System Bus (Debug) Master AXI4***\n -\n -\n* - *Write address channel signals*\n -\n -\n* - sb_axi_awvalid\n - out\n - Write address valid\n* - sb_axi_awready\n - in\n - Write address ready\n* - sb_axi_awid[pt.SB_BUS_TAG-1:0]\n - out\n - Write address ID (hardwired to 0)\n* - sb_axi_awaddr[31:0]\n - out\n - Write address\n* - sb_axi_awlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - sb_axi_awsize[2:0]\n - out\n - Burst size\n* - sb_axi_awburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - sb_axi_awlock\n - out\n - Lock type (hardwired to 0)\n* - sb_axi_awcache[3:0]\n - out\n - Memory type (hardwired to 0b1111)\n* - sb_axi_awprot[2:0]\n - out\n - Protection type (hardwired to 0b000)\n* - sb_axi_awqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - sb_axi_awregion[3:0]\n - out\n - Region identifier\n* - *Write data channel signals*\n -\n -\n* - sb_axi_wvalid\n - out\n - Write valid\n* - sb_axi_wready\n - in\n - Write ready\n* - sb_axi_wdata[63:0]\n - out\n - Write data\n* - sb_axi_wstrb[7:0]\n - out\n - Write strobes\n* - sb_axi_wlast\n - out\n - Write last\n* - *Write response channel signals*\n -\n -\n* - sb_axi_bvalid\n - in\n - Write response valid\n* - sb_axi_bready\n - out\n - Write response ready\n* - sb_axi_bid[pt.SB_BUS_TAG-1:0]\n - in\n - Response ID tag\n* - sb_axi_bresp[1:0]\n - in\n - Write response\n* - *Read address channel signals*\n -\n -\n* - sb_axi_arvalid\n - out\n - Read address valid\n* - sb_axi_arready\n - in\n - Read address ready\n* - sb_axi_arid[pt.SB_BUS_TAG-1:0]\n - out\n - Read address ID (hardwired to 0)\n* - sb_axi_araddr[31:0]\n - out\n - Read address\n* - sb_axi_arlen[7:0]\n - out\n - Burst length (hardwired to 0b0000_0000)\n* - sb_axi_arsize[2:0]\n - out\n - Burst size\n* - sb_axi_arburst[1:0]\n - out\n - Burst type (hardwired to 0b01)\n* - sb_axi_arlock\n - out\n - Lock type (hardwired to 0)\n* - sb_axi_arcache[3:0]\n - out\n - Memory type (hardwired to 0b0000)\n* - sb_axi_arprot[2:0]\n - out\n - Protection type (hardwired to 0b000)\n* - sb_axi_arqos[3:0]\n - out\n - Quality of Service (QoS) (hardwired to 0b0000)\n* - sb_axi_arregion[3:0]\n - out\n - Region identifier\n* - *Read data channel signals*\n -\n -\n* - sb_axi_rvalid\n - in\n - Read valid\n* - sb_axi_rready\n - out\n - Read ready\n* - sb_axi_rid[pt.SB_BUS_TAG-1:0]\n - in\n - Read ID tag\n* - sb_axi_rdata[63:0]\n - in\n - Read data\n* - sb_axi_rresp[1:0]\n - in\n - Read response\n* - sb_axi_rlast\n - in\n - Read last\n* - ***DMA Slave AXI4***\n -\n -\n* - *Write address channel signals*\n -\n -\n* - dma_axi_awvalid\n - in\n - Write address valid\n* - dma_axi_awready\n - out\n - Write address ready\n* - dma_axi_awid[pt.DMA_BUS_TAG-1:0]\n - in\n - Write address ID\n* - dma_axi_awaddr[31:0]\n - in\n - Write address\n* - dma_axi_awlen[7:0]\n - in\n - Burst length\n* - dma_axi_awsize[2:0]\n - in\n - Burst size\n* - dma_axi_awburst[1:0]\n - in\n - Burst type\n* - dma_axi_awprot[2:0]\n - in\n - Protection type\n* - *Write data channel signals*\n -\n -\n* - dma_axi_wvalid\n - in\n - Write valid\n* - dma_axi_wready\n - out\n - Write ready\n* - dma_axi_wdata[63:0]\n - in\n - Write data\n* - dma_axi_wstrb[7:0]\n - in\n - Write strobes\n* - dma_axi_wlast\n - in\n - Write last\n* - *Write response channel signals*\n -\n -\n* - dma_axi_bvalid\n - out\n - Write response valid\n* - dma_axi_bready\n - in\n - Write response ready\n* - dma_axi_bid[pt.DMA_BUS_TAG-1:0]\n - out\n - Response ID tag\n* - dma_axi_bresp[1:0]\n - out\n - Write response\n* - *Read address channel signals*\n -\n -\n* - dma_axi_arvalid\n - in\n - Read address valid\n* - dma_axi_arready\n - out\n - Read address ready\n* - dma_axi_arid[pt.DMA_BUS_TAG-1:0]\n - in\n - Read address ID\n* - dma_axi_araddr[31:0]\n - in\n - Read address\n* - dma_axi_arlen[7:0]\n - in\n - Burst length\n* - dma_axi_arsize[2:0]\n - in\n - Burst size\n* - dma_axi_arburst[1:0]\n - in\n - Burst type\n* - dma_axi_arprot[2:0]\n - in\n - Protection type\n* - *Read data channel signals*\n -\n -\n* - dma_axi_rvalid\n - out\n - Read valid\n* - dma_axi_rready\n - in\n - Read ready\n* - dma_axi_rid[pt.DMA_BUS_TAG-1:0]\n - out\n - Read ID tag\n* - dma_axi_rdata[63:0]\n - out\n - Read data\n* - dma_axi_rresp[1:0]\n - out\n - Read response\n* - dma_axi_rlast\n - out\n - Read last\n* - ***AHB-Lite***\n -\n -\n* - ***Instruction Fetch Unit Master AHB-Lite***\n -\n -\n* - *Master signals*\n -\n -\n* - haddr[31:0]\n - out\n - System address\n* - hburst[2:0]\n - out\n - Burst type (hardwired to 0b000)\n* - hmastlock\n - out\n - Locked transfer (hardwired to 0)\n* - hprot[3:0]\n - out\n - Protection control\n* - hsize[2:0]\n - out\n - Transfer size\n* - htrans[1:0]\n - out\n - Transfer type\n* - hwrite\n - out\n - Write transfer\n* - *Slave signals*\n -\n -\n* - hrdata[63:0]\n - in\n - Read data\n* - hready\n - in\n - Transfer finished\n* - hresp\n - in\n - Slave transfer response\n* - ***Load/Store Unit Master AHB-Lite***\n -\n -\n* - *Master signals*\n -\n -\n* - lsu_haddr[31:0]\n - out\n - System address\n* - lsu_hburst[2:0]\n - out\n - Burst type (hardwired to 0b000)\n* - lsu_hmastlock\n - out\n - Locked transfer (hardwired to 0)\n* - lsu_hprot[3:0]\n - out\n - Protection control\n* - lsu_hsize[2:0]\n - out\n - Transfer size\n* - lsu_htrans[1:0]\n - out\n - Transfer type\n* - lsu_hwdata[63:0]\n - out\n - Write data\n* - lsu_hwrite\n - out\n - Write transfer\n* - *Slave signals*\n -\n -\n* - lsu_hrdata[63:0]\n - in\n - Read data\n* - lsu_hready\n - in\n - Transfer finished\n* - lsu_hresp\n - in\n - Slave transfer response\n* - ***System Bus (Debug) Master AHB-Lite***\n -\n -\n* - *Master signals*\n -\n -\n* - sb_haddr[31:0]\n - out\n - System address\n* - sb_hburst[2:0]\n - out\n - Burst type (hardwired to 0b000)\n* - sb_hmastlock\n - out\n - Locked transfer (hardwired to 0)\n* - sb_hprot[3:0]\n - out\n - Protection control\n* - sb_hsize[2:0]\n - out\n - Transfer size\n* - sb_htrans[1:0]\n - out\n - Transfer type\n* - sb_hwdata[63:0]\n - out\n - Write data\n* - sb_hwrite\n - out\n - Write transfer\n* - *Slave signals*\n -\n -\n* - sb_hrdata[63:0]\n - in\n - Read data\n* - sb_hready\n - in\n - Transfer finished\n* - sb_hresp\n - in\n - Slave transfer response\n* - ***DMA Slave AHB-Lite***\n -\n -\n* - *Slave signals*\n -\n -\n* - dma_haddr[31:0]\n - in\n - System address\n* - dma_hburst[2:0]\n - in\n - Burst type\n* - dma_hmastlock\n - in\n - Locked transfer\n* - dma_hprot[3:0]\n - in\n - Protection control\n* - dma_hsize[2:0]\n - in\n - Transfer size\n* - dma_htrans[1:0]\n - in\n - Transfer type\n* - dma_hwdata[63:0]\n - in\n - Write data\n* - dma_hwrite\n - in\n - Write transfer\n* - dma_hsel\n - in\n - Slave select\n* - dma_hreadyin\n - in\n - Transfer finished in\n* - *Master signals*\n -\n -\n* - dma_hrdata[63:0]\n - out\n - Read data\n* - dma_hreadyout\n - out\n - Transfer finished\n* - dma_hresp\n - out\n - Slave transfer response\n* - **Memory interfaces**\n -\n -\n* - ***Data Close-Coupled Memory***\n -\n -\n* - dccm_clk_override\n -\n -\n* - dccm_ecc_double_error\n -\n -\n* - dccm_ecc_single_error\n -\n -\n* - dccm_rd_addr_hi\n -\n -\n* - dccm_rd_addr_lo\n -\n -\n* - dccm_rd_data_hi\n -\n -\n* - dccm_rd_data_lo\n -\n -\n* - dccm_rden\n -\n -\n* - dccm_wr_addr_hi\n -\n -\n* - dccm_wr_addr_lo\n -\n -\n* - dccm_wr_data_hi\n -\n -\n* - dccm_wr_data_lo\n -\n -\n* - dccm_wren\n -\n -\n* - dec_tlu_core_ecc_disable\n - out\n - Disable core ECC\n* - ***Inctruction Close-Coupled Memory***\n -\n -\n* - iccm_buf_correct_ecc\n -\n -\n* - iccm_correction_state\n -\n -\n* - iccm_ecc_double_error\n -\n -\n* - iccm_ecc_single_error\n -\n -\n* - iccm_rd_data\n -\n -\n* - iccm_rd_data_ecc\n -\n -\n* - iccm_rden\n -\n -\n* - iccm_rw_addr\n -\n -\n* - iccm_wr_data\n -\n -\n* - iccm_wr_size\n -\n -\n* - iccm_wren\n -\n -\n* - icm_clk_override\n -\n -\n* - ***Instruction Cache Memory***\n -\n -\n* - ic_debug_addr\n -\n -\n* - ic_debug_rd_data\n -\n -\n* - ic_debug_rd_en\n -\n -\n* - ic_debug_tag_array\n -\n -\n* - ic_debug_way\n -\n -\n* - ic_debug_wr_data\n -\n -\n* - ic_debug_wr_en\n -\n -\n* - ic_eccerr\n -\n -\n* - ic_parerr\n -\n -\n* - ic_premux_data\n -\n -\n* - ic_rd_data\n -\n -\n* - ic_rd_en\n -\n -\n* - ic_rd_hit\n -\n -\n* - ic_rw_addr\n -\n -\n* - ic_sel_premux_data\n -\n -\n* - ic_tag_perr\n -\n -\n* - ic_tag_valid\n -\n -\n* - ic_wr_data\n -\n -\n* - ic_wr_en\n -\n -\n* - ictag_debug_rd_data\n -\n -\n* - **Power Management Unit (PMU) Interface**\n -\n -\n* - i_cpu_halt_req\n - in\n - PMU halt request to core (async)\n* - o_cpu_halt_ack\n - out\n - Core acknowledgement for PMU halt request\n* - o_cpu_halt_status\n - out\n - Core halted indication\n* - i_cpu_run_req\n - in\n - PMU run request to core (async)\n* - o_cpu_run_ack\n - out\n - Core acknowledgement for PMU run request\n* - **Multi-Processor Controller (MPC) Debug Interface**\n -\n -\n* - mpc_debug_halt_req\n - in\n - MPC debug halt request to core (async)\n* - mpc_debug_halt_ack\n - out\n - Core acknowledgement for MPC debug halt request\n* - mpc_debug_run_req\n - in\n - MPC debug run request to core (async)\n* - mpc_debug_run_ack\n - out\n - Core acknowledgement for MPC debug run request\n* - mpc_reset_run_req\n - in\n - Core start state control out of reset\n* - o_debug_mode_status\n - out\n - Core in Debug Mode indication\n* - debug_brkpt_status\n - out\n - Hardware/software breakpoint indication\n* - **Performance Counter Activity**\n -\n -\n* - dec_tlu_perfcnt0\n - out\n - Performance counter 0 incrementing\n* - dec_tlu_perfcnt1\n - out\n - Performance counter 1 incrementing\n* - dec_tlu_perfcnt2\n - out\n - Performance counter 2 incrementing\n* - dec_tlu_perfcnt3\n - out\n - Performance counter 3 incrementing\n* - **Trace Port**\n -\n -\n* - trace_rv_i_insn_ip[31:0]\n - out\n - Instruction opcode\n* - trace_rv_i_address_ip[31:0]\n - out\n - Instruction address\n* - trace_rv_i_valid_ip\n - out\n - Instruction trace valid\n* - trace_rv_i_exception_ip\n - out\n - Exception\n* - trace_rv_i_ecause_ip[4:0]\n - out\n - Exception cause\n* - trace_rv_i_interrupt_ip\n - out\n - Interrupt exception\n* - trace_rv_i_tval_ip[31:0]\n - out\n - Exception trap value\n* - **Debug Module Interface**\n -\n -\n* - dmi_reg_addr\n -\n -\n* - dmi_reg_en\n -\n -\n* - dmi_reg_rdata\n -\n -\n* - dmi_reg_wdata\n -\n -\n* - dmi_reg_wr_en\n -\n -\n* - **Debug JTAG Port**\n -\n -\n* - jtag_tck\n - in\n - JTAG Test Clock (async)\n* - jtag_tms\n - in\n - JTAG Test Mode Select (async, sync to jtag_tck)\n* - jtag_tdi\n - in\n - JTAG Test Data In (async, sync to jtag_tck)\n* - jtag_trst_n\n - in\n - JTAG Test Reset (async)\n* - jtag_tdo\n - out\n - JTAG Test Data Out (async, sync to jtag_tck)\n* - jtag_id[31:1]\n - in\n - JTAG IDCODE register value (bit 0 tied internally to 1)\n* - **Testing**\n -\n -\n* - scan_mode\n - in\n - May be used to enable logic scan test, if implemented (must be ‘0’ for normal core operation)\n* - mbist_mode\n - in\n - May be used to enable MBIST for core-internal memories, if implemented (should be tied to ‘0’ if not used)\n:::\n\nSignals not compared due to their special meaning:\n* `clk` - [core complex clock](clocks.md#clocking),\n* `free_l2clk` - core complex clock always enabled, routed through one clock header,\n* `active_l2clk` - core complex clock enabled when the core is active, routed through one clock header,\n* `rst_l` - [core complex reset](clocks.md#core-complex-reset-rst-l),\n* `dbg_rst_l` - [debug module reset](clocks.md#debug-module-reset-dbg-rst-l).\n\n## Shadow Core Control\n\nThe DCLS module exposes control logic that can be potentially connected to the external CSR.\nSpecific signals available as the module ports are described in the {ref}`tab-shadow-core-control-signals`.\nThe error injection logic is a part of the Shadow Core and its purpose is to test whether the lockstep module operates correctly and to disable it if needed.\nError is injected by asserting the `corruption_detected_o` output signal even if there is no corruption error detected between the Shadow Core and the Main Core.\n\n:::{list-table} Shadow Core Control Signals\n:name: tab-shadow-core-control-signals\n\n* - **Signal**\n - **Direction**\n - **Width**\n - **Description**\n* - disable_corruption_detection_i\n - input\n - 1\n - Disable all error injection features\n* - lockstep_err_injection_en_i\n - input\n - 1\n - Activate an error injection to the Shadow Core\n* - corruption_detected_o\n - output\n - 1\n - Indicate that a Shadow Core detected an error (corruption in comparison to the Main Core)\n:::\n\n## Configuration\n\n```{warning}\nThe DCLS feature is not supported in Debug Mode.\nEntering Debug Mode with DCLS enabled will disable DCLS until the next reset.\n```\n\nThe DCLS feature can be enabled via `-set lockstep_enable=1` option.\nThere are two configuration options:\n* `-set lockstep_delay={2, 3, 4}` - the delay applied on the Shadow Core between 2 and 4 cycles,\n* `-set lockstep_regfile_enable=1` - enable exposing the VeeR Register File so the Shadow Core will have an internal copy to compare with the Main Core Register File.\n\nThe configuration options are ignored and their macros are not generated if the Dual Core Lockstep feature is disabled.\n\n## Validation Plan\n\nThe DCLS feature will be tested within:\n\n* Software DCLS [smoke test](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/testbench/tests/dcls/dcls.c) - covers VeeR CPU core with the Shadow Core execution flow.\n* RTL `el2_veer_lockstep` [module tests](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/verification/block/dcls) - covers the Shadow Core by itself.\n\n:::{list-table} Validation Plan\n:name: vp-block-name-list-table\n:header-rows: 0\n:align: center\n\n* - **Function**\n - **VeeR EL2 CPU core input corruption detection**\n* - Reference Document\n -\n* - Check description\n - Verify the panic signal is raised only upon core states' mismatch. Introduce corruption via VeeR EL2 CPU core inputs directed to the Shadow Core.\n* - Coverage groups\n - Each output of the VeeR EL2 CPU Core is reached when detecting the mismatch by `Equivalence Checker`. All bounds of configurable delay are reached.\n* - Assertions\n - Detection bit is asserted upon encountered corruption. Error behavior follows the error handling policy. No action is taken if no corruption was introduced.\n* - Comments\n -\n* - Test Name\n -\n* -\n -\n* - **Function**\n - **VeeR EL2 CPU core output corruption detection**\n* - Reference Document\n -\n* - Check description\n - Verify the panic signal is raised only upon core states' mismatch. Introduce corruption via the outputs of the main VeeR CPU core directed to `Equivalence Checker` in the Shadow Core.\n* - Coverage groups\n - Each output of the VeeR EL2 CPU Core is reached when detecting the mismatch by `Equivalence Checker`. All bounds of configurable delay are reached.\n* - Assertions\n - Detection bit is asserted upon encountered corruption. Error behavior follows the relevant error handling policy. No action is taken if no corruption was introduced.\n* - Comments\n -\n* - Test Name\n -\n* -\n -\n* - **Function**\n - **Internal state corruption detection**\n* - Reference Document\n -\n* - Check description\n - Verify the panic signal is raised only upon core states' mismatch. Introduce corruption via exposed registers of the Shadow Core.\n* - Coverage groups\n - Each [monitored register](#monitored-registers) is detected by the `Equivalence Checker`. All bounds of configurable delay are reached.\n* - Assertions\n - Detection bit is asserted upon encountered corruption. Error behavior follows the relevant error handling policy. No action is taken if no corruption was introduced.\n* - Comments\n - The default path will likely be more easily testable with the help of the software testbench. It should be possible to simulate a fault injection via mailbox see: [top_tb.sv](https://github.com/chipsalliance/Cores-VeeR-EL2/blob/795eb588e34b6815033b769d54fcf7cfac4aae3a/testbench/tb_top.sv#L727).\n* - Test Name\n -\n* -\n -\n* - **Function**\n - **DCLS default execution**\n* - Reference Document\n -\n* - Check description\n - Verify the DCLS feature behavior during non-obstructed execution.\n* - Coverage groups\n -\n* - Assertions\n - Detection bit is not raised. Detection interrupt is not asserted. The test provides the same results as the VeeR EL2 CPU core without the DCLS feature enabled.\n* - Comments\n - It might be beneficial to use a software test with a program that will produce a result that can by easily compared to an alternative flow and also engage the VeeR EL2 core. Consider matrix multiplication.\n* - Test Name\n -\n* -\n -\n* - **Function**\n - **Error reporting**\n* - Reference Document\n -\n* - Check description\n - Verify error reporting policy upon detected corruption.\n* - Coverage groups\n - Each error policy is covered.\n* - Assertions\n -\n* - Comments\n -\n* - Test Name\n -\n* -\n -\n* - **Function**\n - **Reset**\n* - Reference Document\n -\n* - Check description\n - Verify the behavior in reset. Ensure normal execution upon leaving reset.\n* - Coverage groups\n -\n* - Assertions\n - Shadow Core enters reset at the same time the main VeeR core does. Shadow Core exits reset after a predefined delay following the main core. Detected corruption and interrupts are deasserted upon entering the reset.\n* - Comments\n -\n* - Test Name\n -\n* -\n -\n:::\n" }, { "path": "docs/source/errata.md", "content": "# Errata\n\n## Back-To-Back Write Transactions Not Supported on AHB-Lite Bus\n\n* **Description**:\nThe AHB-Lite bus interface for LSU is not optimized for write performance.\nEach aligned store is issued to the bus as a single write transaction followed by an idle cycle.\nEach unaligned store is issued to the bus as multiple backto-back byte write transactions followed by an idle cycle.\nThese idle cycles limit the achievable bus utilization for writes.\n* **Symptoms**: Potential performance impact for writes with AHB-Lite bus.\n* **Workaround**: None.\n\n## Debug Abstract Command Register May Return Non-Zero Value On Read\n\n* **Description**:\nThe RISC-V External Debug specification specifies the abstract command (`command`) register as write-only (see Section 3.14.7 in [[3]](intro.md#ref-3)).\nHowever, the VeeR EL2 implementation supports write as well as read operations to this register.\nThis may help a debugger's feature discovery process, but is not fully compliant with the RISC-V External Debug specification.\nBecause the expected return value for reading this register is always zero, it is unlikely that a debugger expecting a zero value would attempt to read it.\n* **Symptoms**: Reading the debug abstract command (`command`) register may return a non-zero value.\n* **Workaround**: A debugger should avoid reading the abstract command register if it cannot handle non-zero data.\n" }, { "path": "docs/source/error-protection.md", "content": "# Memory Error Protection\n## General Description\n### Parity\n\nParity is a simple and relatively cheap protection scheme generally used when the corrupted data can be restored from some other location in the system.\nA single parity check bit typically covers several data bits.\nTwo parity schemes are used: even and odd parity.\nThe total number of '1' bits are counted in the protected data word, including the parity bit.\nFor even parity, the data is deemed to be correct if the total count is an even number.\n\nSimilarly, for odd parity if the total count is an odd number. Note that double-bit errors cannot be detected.\n\n### Error Correcting Code (ECC)\n\nA robust memory hierarchy design often includes ECC functions to detect and, if possible, correct corrupted data.\n\nThe ECC functions described are made possible by Hamming code, a relatively simple yet powerful ECC code.\nIt involves storing and transmitting data with multiple check bits (parity) and decoding the associated check bits when retrieving or receiving data to detect and correct errors.\n\nThe ECC feature can be implemented with Hamming based SECDED (Single-bit Error Correction and Double-bit Error Detection) algorithm.\nThe design can use the (39, 32) code - 32 data bits and 7 parity bits depicted in {numref}`fig-ecc-mem-diag` below.\nIn other words, the Hamming code word width is 39 bits, comprised of 32 data bits and 7 check bits.\nThe minimum number of check bits needed for correcting a single-bit error in a 32-bit word is six.\nThe extra check bit expands the function to detect double-bit errors as well.\n\nECC codes may also be used for error detection only if other means exist to correct the data.\nFor example, the Icache stores exact copies of cache lines which are also residing in SoC memory.\nInstead of correcting corrupted data fetched from the I-cache, erroneous cache lines may also be invalidated in the I-cache and refetched from SoC memory.\nA SEDDED (Single-bit Error Detection and Double-bit Error Detection) code is sufficient in that case and provides even better protection than a SECDED code since double-bit errors are corrected as well but requires fewer bits to protect each codeword.\nNote that flushing and refetching is the industry standard mechanism for recovering from I-cache errors, though commonly still referred to as 'SECDED'.\n\n:::{figure-md} fig-ecc-mem-diag\n![ECC in a Memory System](img/ecc_mem_diag.png)\n\nConceptual Block Diagram – ECC in a Memory System\n:::\n\n## Selecting the Proper Error Protection Level\n\nChoosing a protection level that is too weak might lead to loss of data or silent data corrupted, choosing a level that is too strong incurs additional chip die area (i.e., cost) and power dissipation.\nSupporting multiple protection schemes for the same design increases the design and verification effort.\nSources of errors can be divided into two major categories:\n\n* Hard errors (e.g., stuck-at bits), and\n* Soft errors (e.g., weak bits, cosmic-induced soft errors)\nSelecting an adequate error protection level - e.g., none, parity, or ECC -- depends on the probability of an error to occur, which depends on several factors:\n* Technology node\n* SRAM structure size\n* SRAM cell design\n* Type of stored information\n * E.g., instructions in I-cache can be refetched, but data might be lost if not adequately protected\n* Stored information being used again after corruption\n\nTypically, a FIT (Failure In Time) rate analysis is done to determine the proper protection level of each memory in a system.\nThis analysis is based on FIT rate information for a given process and SRAM cell design which are typically available from chip manufacturer.\n\nAlso important is the SRAM array design. The SRAM layout can have an impact on if an error is correctable or not.\n\nFor example, a single cosmic-induced soft error event may destroy the content of multiple bit cells in an array.\nIf the destroyed bits are covered by the same codeword, the data cannot be corrected or possibly even detected.\n\nTherefore, the bits of each codeword should be physically spread in the array as far apart as feasibly possible. In a properly laid out SRAM array, multiple corrupted bits may result in several single-bit errors of different codewords which are correctable.\n\n## Memory Hierarchy\n\n{numref}`tab-memory-hierarchy-components-and-protection` summarizes the components of the VeeR EL2 memory hierarchy and their respective protection scheme.\n\n:::{list-table} Memory Hierarchy Components and Protection\n:name: tab-memory-hierarchy-components-and-protection\n* - **Memory Type**\n - **Abbreviation**\n - **Protection**\n - **Reason/Justification**\n* - Instruction Cache\n - I-cache\n - Parity or SEDDED ECC (data and tag) [^fn-error-protection-1]\n - Instructions can be refetched if error is detected\n* - Instruction Closely-Coupled Memory\n - ICCM\n - SECDED ECC\n -\n - Large SRAM arrays\n - Data could be modified and is only valid copy\n* - Data Closely-Coupled Memory\n - DCCM\n - SECDED ECC\n -\n - Large SRAM arrays\n - Data could be modified and is only valid copy\n* - Core-complex-external Memories\n - SoC memories\n - SECDED ECC\n -\n - Large SRAM arrays\n - Data could be modified and is only valid copy\n:::\n\n[^fn-error-protection-1]: Some highly reliable/available applications (e.g., automotive) might want to use an ECC-protected I-cache, instead of parity\nprotection. Therefore, SEDDED ECC protection is optionally provided in VeeR EL2 as well, selectable as a core build argument.\nNote that the I-cache area increases significantly if ECC protection is used.\n\n## Error Detection and Handling\n\n{numref}`tab-error-detection-recovery-logging` summarizes the detection of errors, the recovery steps taken, and the logging of error events for each of the VeeR EL2 memories.\n\n:::{note}\n Memories with parity or ECC protection must be initialized with correct parity or ECC. Otherwise, a read access to an uninitialized memory may report an error. The method of initialization depends on the organization and capabilities of the memory. Initialization might be performed by a memory self-test or depend on firmware to overwrite the entire memory range (e.g., via DMA accesses).\n:::\n\n:::{note}\n If the DCCM is uninitialized, a load following a store to the same DCCM address may get incorrect data. If firmware initializes the DCCM, aligned word-sized stores should be used (because they don't check ECC), followed by a fence, before any load instructions to DCCM addresses are executed.\n:::\n\nEmpty fields shall be ignored as they provide structure information for the table\n\n:::{list-table} Error Detection, Recovery, and Logging\n:name: tab-error-detection-recovery-logging\n\n* - **Memory Type**\n - **Detection**\n - **Recovery**\n - **Recovery**\n - **Logging**\n - **Logging**\n* -\n -\n - **Single-bit Error**\n - **Double-bit Error**\n - **Single-bit Error**\n - **Double-bit Error**\n* - I-cache\n -\n - Each 64-bit chunk of instructions protected with 4 parity bits (one per 16 consecutive bits) or 7 ECC bits\n - Each cache line tag protected with 1 parity bit or 5 ECC bits\n - Parity/ECC bits checked in pipeline\n -\n -\n -\n -\n* -\n -\n - **For parity**\n -\n -\n -\n* -\n -\n -\n - For instruction and tag parity errors, invalidate all cache lines of set\n - Refetch cache line from SoC memory\n - Undetected\n -\n - Increment I- cache correctable error counter [^fn-error-protection-2]\n - If error counter has reached threshold, signal correctable error local interrupt (see [](error-protection.md#i-cache-error-counter-threshold-register-micect))\n - No action\n* -\n -\n - **For ECC**\n -\n -\n -\n* -\n -\n -\n - For instruction and tag single- and double ECC errors, invalidate all cache lines of set\n - Refetch cache line from SoC memory [^fn-error-protection-3]\n -\n - For instruction and tag single- and double ECC errors, invalidate all cache lines of set\n - Refetch cache line from SoC memory [^fn-error-protection-3]\n -\n - Increment I-cache correctable error counter [^fn-error-protection-2]\n - If error counter has reached threshold, signal correctable error local interrupt (see [](error-protection.md#i-cache-error-counter-threshold-register-micect))\n -\n - Increment I-cache correctable error counter [^fn-error-protection-2]\n - If error counter has reached threshold, signal correctable error local interrupt (see [](error-protection.md#i-cache-error-counter-threshold-register-micect))\n* - ICCM\n -\n - Each 32-bit chunk protected with 7 ECC bits\n - ECC checked in pipeline\n -\n - For fetches [^fn-error-protection-4]:\n - Write corrected data/ECC back to ICCM\n - Refetch instruction from ICCM [^fn-error-protection-3]\n - For DMA reads:\n - Correct error in-line\n - Write corrected data/ECC back to ICCM\n - Fatal error [^fn-error-protection-5] (uncorrectable)\n -\n - Increment [^fn-error-protection-4] ICCM single- bit error counter\n - If error counter has reached threshold, signal correctable error local interrupt (see [](error-protection.md#iccm-correctable-error-counter-threshold-register-miccmect))\n -\n - For fetches [^fn-error-protection-5]:\n - Instruction access fault exception\n - For DMA reads:\n - Send error response on DMA slave bus to master\n* - DCCM\n -\n - Each 32-bit chunk protected with 7 ECC bits\n - ECC checked in pipeline\n -\n - Correct error in-line\n - Write [^fn-error-protection-6] corrected data/ECC back to DCCM\n - Fatal error [^fn-error-protection-7] (uncorrectable)\n -\n - Increment [^fn-error-protection-6] DCCM single- bit error counter\n - If error counter has reached threshold, signal correctable error local interrupt (see [](error-protection.md#dccm-correctable-error-counter-threshold-register-mdccmect))\n -\n - For loads [^fn-error-protection-7]:\n - Load access fault exception\n - For stores [^fn-error-protection-7]:\n - Store/AMO access fault exception\n - For DMA reads:\n - Send error response on DMA slave bus to master\n* - SoC memories\n - ECC checked at SoC memory boundary\n -\n - Correct error\n - Send corrected data on bus\n - Write corrected data/ECC back to SRAM array\n -\n - Fatal error (uncorrectable)\n - Data sent on bus with error indication\n - Core must ignore sent data\n -\n - Increment SoC single-bit error counter local to memory\n - If error counter has reached threshold, signal external interrupt\n -\n - For fetches:\n - Instruction access fault exception\n - For loads:\n - Non-blocking load bus error NMI (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n - For stores:\n - Store bus error NMI (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n:::\n\nGeneral comments:\n\n* No address information of each individual correctable error is captured.\n* Stuck-at faults:\n * Stuck-at bits would cause the correctable error threshold to be reached relatively quickly but are only reported if interrupts are enabled.\n * Use MBIST to determine exact location of the bad bit.\n * Because ICCM single-bit errors on fetches are not in-line corrected, VeeR EL2's ICCM implements two row's worth of redundant memory which is transparently managed in hardware.\n These extra rows help to avoid that a stuck-at bit may hang the core.\n\n[^fn-error-protection-2]: It is unlikely, but possible that multiple I-cache parity/ECC errors are detected on a cache line in a single cycle, however, the Icache single-bit error counter is incremented only by one.\n[^fn-error-protection-3]: A RFPC (ReFetch PC) flush is performed since in-line correction would create timing issues and require an additional clock cycle as well as a different architecture.\n[^fn-error-protection-4]: All single-bit errors detected on fetches are corrected, written back to the ICCM, and counted, independent of actual instruction execution.\n[^fn-error-protection-5]: For oldest instruction in pipeline only.\n[^fn-error-protection-6]: For load/store accesses, the corrected data is written back to the DCCM and counted only if the load/store instruction retires (i.e., access is non-speculative and has no exception).\n[^fn-error-protection-7]: For non-speculative accesses only.\n\n## Core Error Counter/Threshold Registers\n\nA summary of platform-specific core error counter/threshold control/status registers in CSR space:\n\n* [](error-protection.md#i-cache-error-counterthreshold-register-micect)\n* [](error-protection.md#iccm-correctable-error-counterthreshold-register-miccmect)\n* [](error-protection.md#dccm-correctable-error-counterthreshold-register-mdccmect)\n\nAll read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.\n\n### I-Cache Error Counter/Threshold Register (micect)\n\nThe `micect` register holds the I-cache error counter and its threshold.\nThe *count* field of the `micect` register is incremented, if a parity/ECC error is detected on any of the cache line tags of the set or the instructions fetched from the I-cache.\nThe *thresh* field of the `micect` register holds a pointer to a bit position of the *count* field.\nIf the selected bit of the *count* field transitions from '0' to '1', the threshold is reached, and a correctable error local interrupt (see [](memory-map.md#correctable-error-local-interrupt)) is signaled.\n\nHardware increments the *count* field on a detected error.\nFirmware can non-destructively read the current *count* and *thresh* values or write to both these fields (e.g., to change the threshold and reset the counter).\n\n:::{note}\nThe counter may overflow if not serviced and reset by firmware.\n:::\n\n:::{note}\nThe correctable error local interrupt is not latched (i.e., \"sticky\"), but it stays pending until the counter overflows (i.e., as long as the *count* value is equal to or greater than the threshold value (= {math}`2^{thresh}`)). When firmware resets the counter, the correctable error local interrupt condition is cleared.\n:::\n\n:::{note}\nThe `micect` register is instantiated, accessible, and has the same functional behavior even if the core is built without an I-cache.\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} I-Cache Error Counter/Threshold Register (micect, at CSR 0x7F0)\n:name: tab-i-cache-error-counter-threshold-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - thresh\n - 31:27\n - I-cache parity/ECC error threshold:\n - 0..26: Value i selects *count[i]* bit\n - 27..31: Invalid (when written, mapped by hardware to 26)\n - R/W\n - 0\n* - count\n - 26:0\n - Counter incremented if I-cache parity/ECC error(s) detected. If *count[thresh]* transitions from '0' to '1', signal correctable error local interrupt (see [](memory-map.md#correctable-error-local-interrupt)).\n - R/W\n - 0\n:::\n\n### ICCM Correctable Error Counter/Threshold Register (miccmect)\n\nThe `miccmect` register holds the ICCM correctable error counter and its threshold.\nThe *count* field of the `miccmect` register is incremented, if a correctable ECC error is detected on either an instruction fetch or a DMA read from the ICCM.\nThe *thresh* field of the `miccmect` register holds a pointer to a bit position of the *count* field.\nIf the selected bit of the *count* field transitions from '0' to '1', the threshold is reached, and a correctable error local interrupt (see [](memory-map.md#correctable-error-local-interrupt)) is signaled.\n\nHardware increments the *count* field on a detected single-bit error.\nFirmware can non-destructively read the current count and *thresh* values or write to both these fields (e.g., to change the threshold and reset the counter).\n\n:::{note}\nThe counter may overflow if not serviced and reset by firmware.\n:::\n\n:::{note}\nThe correctable error local interrupt is not latched (i.e., \"sticky\"), but it stays pending until the counter overflows (i.e., as long as the *count* value is equal to or greater than the threshold value (= {math}`2^{thresh}`)). When firmware resets the counter, the correctable error local interrupt condition is cleared.\n:::\n\n:::{note}\nDMA accesses while in power management Sleep (pmu/fw-halt) or debug halt (db-halt) state may encounter ICCM single-bit errors. Correctable errors are counted in the `miccmect` error counter irrespective of the core's power state.\n:::\n\n:::{note}\nIn the unlikely case of a persistent single-bit error in the ICCM on a location needed for execution of the beginning of the ICCM correctable error local interrupt handler and the counter threshold is set to lower than 16 errors, forward progress may not be guaranteed.\n:::\n\n:::{note}\nThe `miccmect` register is instantiated, accessible, and has the same functional behavior even if the core is built without an ICCM.\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} ICCM Correctable Error Counter/Threshold Register (miccmect, at CSR 0x7F1)\n:name: tab-iccm-correctable-error-counter-threshold-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - thresh\n - 31:27\n - ICCM correctable ECC error threshold:\n - 0..26: Value i selects *count[i]* bit\n - 27..31: Invalid (when written, mapped by hardware to 26)\n - R/W\n - 0\n* - count\n - 26:0\n - Counter incremented for each detected ICCM correctable ECC error. If *count[thresh]* transitions from '0' to '1', signal correctable error local interrupt (see [](memory-map.md#correctable-error-local-interrupt)).\n - R/W\n - 0\n:::\n\n### DCCM Correctable Error Counter/Threshold Register (mdccmect)\n\nThe `mdccmect` register holds the DCCM correctable error counter and its threshold.\nThe *count* field of the `mdccmect` register is incremented, if a correctable ECC error is detected on either a retired load/store instruction or a DMA read access to the DCCM.\nThe *thresh* field of the `mdccmect` register holds a pointer to a bit position of the *count* field.\nIf the selected bit of the *count* field transitions from '0' to '1', the threshold is reached, and a correctable error local interrupt (see [](memory-map.md#correctable-error-local-interrupt)) is signaled.\n\nHardware increments the *count* field on a detected single-bit error for a retired load or store instruction (i.e., a nonspeculative access with no exception) or a DMA read.\nFirmware can non-destructively read the current *count* and *thresh* values or write to both these fields (e.g., to change the threshold and reset the counter).\n\n:::{note}\nThe counter may overflow if not serviced and reset by firmware.\n:::\n\n:::{note}\nThe correctable error local interrupt is not latched (i.e., \"sticky\"), but it stays pending until the counter overflows (i.e., as long as the *count* value is equal to or greater than the threshold value (= {math}`2^{thresh}`)).\nWhen firmware resets the counter, the correctable error local interrupt condition is cleared.\n:::\n\n:::{note}\nDMA accesses while in power management Sleep (pmu/fw-halt) or debug halt (db-halt) state may encounter DCCM single-bit errors.\nCorrectable errors are counted in the `mdccmect` error counter irrespective of the core's power state.\n:::\n\n:::{note}\nThe `mdccmect` register is instantiated, accessible, and has the same functional behavior even if the core is built without a DCCM.\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} DCCM Correctable Error Counter/Threshold Register (mdccmect, at CSR 0x7F2)\n:name: tab-mdccmect\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - thresh\n - 31:27\n - DCCM correctable ECC error threshold:\n - 0..26: Value i selects *count[i]* bit\n - 27..31: Invalid (when written, mapped by hardware to 26)\n - R/W\n - 0\n* - count\n - 26:0\n - Counter incremented for each detected DCCM correctable ECC error. If *count[thresh]* transitions from '0' to '1', signal correctable error local interrupt (see [](memory-map.md#correctable-error-local-interrupt)).\n - R/W\n - 0\n:::\n" }, { "path": "docs/source/index.md", "content": "# {{project}}\n\n```{toctree}\n:maxdepth: 2\n:numbered:\n\nintro\noverview\nmemory-map\nerror-protection\ndual-core-lock-step\ntimers\npower\ninterrupts\nperformance\ncache\ndebugging\ncore-control\nadaptations\ncsrs\ninterrupt-priority\nclocks\ncomplex-ports\nbuild-args\ntests\nerrata\nphysical-memory-protection\nuser-mode\nverification\nsimulation-debugging\ntock\n```\n" }, { "path": "docs/source/interrupt-priority.md", "content": "# Interrupt Priorities\n\n{numref}`tab-veer-el2-platform-specific-and-std-risc-v-interrupt-priorities` summarizes the VeeR EL2 platform-specific (Local) and standard RISC-V (External, Software, and Timer) relative interrupt priorities.\n\n:::{list-table} VeeR EL2 Platform-specific and Standard RISC-V Interrupt Priorities. Table is sorted from highest Interrupt priority to lowest Interrupt priority\n:name: tab-veer-el2-platform-specific-and-std-risc-v-interrupt-priorities\n\n* - **Interrupt**\n - **Section**\n* - *Non-Maskable Interrupt (standard RISC-V)*\n - [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* - *External interrupt (standard RISC-V)*\n - [](interrupts.md)\n* - Correctable error (local interrupt)\n - [](memory-map.md#correctable-error-local-interrupt)\n* - *Software interrupt (standard RISC-V)*\n - [](memory-map.md#software-interrupts)\n* - *Timer interrupt (standard RISC-V)*\n - [](performance.md#standard-risc-v-registers)\n* - Internal timer 0 (local interrupt)\n - [](timers.md#internal-timer-local-interrupts)\n* - Internal timer 1 (local interrupt)\n - [](timers.md#internal-timer-local-interrupts)\n:::\n" }, { "path": "docs/source/interrupts.md", "content": "# External Interrupts\n\nSee *Chapter 7, Platform-Level Interrupt Controller (PLIC)* in [[2 (PLIC)]](intro.md#ref-2-plic) for general information.\n\n:::{note}\nEven though this specification is modeled to a large extent after the RISC-V PLIC (Platform-Level Interrupt Controller) specification, this interrupt controller is associated with the core, not the platform.\nTherefore, the more general term PIC (Programmable Interrupt Controller) is used.\n:::\n\n## Features\n\nThe PIC provides these core-level external interrupt features:\n\n* Up to 255 global (core-external) interrupt sources (from 1 (highest) to 255 (lowest)) with separate enable control for each source\n* 15 priority levels (numbered 1 (lowest) to 15 (highest)), separately programmable for each interrupt source\n* Programmable reverse priority order (14 (lowest) to 0 (highest))\n* Programmable priority threshold to disable lower-priority interrupts\n* Wake-up priority threshold (hardwired to highest priority level) to wake up core from power-saving (Sleep) mode if interrupts are enabled\n* One interrupt target (RISC-V hart M-mode context)\n* Support for vectored external interrupts\n* Support for fast interrupt redirection in hardware (selectable by build argument)\n* Support for interrupt chaining and nested interrupts\n* Power reduction feature for disabled external interrupts\n\n## Naming Convention\n\n### Unit, Signal, and Register Naming\n\n**S suffix:** Unit, signal, and register names which have an S suffix indicate an entity specific to an interrupt source.\n\n**X suffix:** Register names which have an X suffix indicate a consolidated register for multiple interrupt sources.\n\n### Address Map Naming\n\n**Control/status register:** A control/status register mapped to either the memory or the CSR address space.\n\n**Memory-mapped register:** Register which is mapped to RISC-V's 32-bit memory address space.\n\n**Register in CSR address space:** Register which is mapped to RISC-V's 12-bit CSR address space.\n\n## Overview of Major Functional Units\n\n### External Interrupt Source\n\nAll functional units on the chip which generate interrupts to be handled by the RISC-V core are referred to as external interrupt sources.\nExternal interrupt sources indicate an interrupt request by sending an asynchronous signal to the PIC.\n\n### Gateway\n\nEach external interrupt source connects to a dedicated gateway.\nThe gateway is responsible for synchronizing the interrupt request to the core's clock domain, and for converting the request signal to a common interrupt request format (i.e., active-high and level-triggered) for the PIC.\nThe PIC core can only handle one single interrupt request per interrupt source at a time.\n\nAll current SoC IP interrupts are asynchronous and level-triggered.\nTherefore, the gateway's only function for SoC IP interrupts is to synchronize the request to the core clock domain.\nThere is no state kept in the gateway.\n\nA gateway suitable for ASIC-external interrupts must provide programmability for interrupt type (i.e., edge- vs. leveltriggered) as well as interrupt signal polarity (i.e., low-to-high vs. high-to-low transition for edge-triggered interrupts, active-high vs. -low for level-triggered interrupts).\nFor edge-triggered interrupts, the gateway must latch the interrupt request in an interrupt pending (IP) flop to convert the edge- to a level-triggered interrupt signal.\nFirmware must clear the IP flop while handling the interrupt.\n\n:::{note}\nWhile an interrupt is disabled, spurious changes of the interrupt source input may be captured in the IP flop.\nTo reduce the probability of reporting spurious interrupts, firmware should clear the IP flop before reenabling interrupts.\n:::\n\n:::{note}\nThe gateway does not implement any edge-detection logic (e.g., an edge-triggered flop) to convert the interrupt request to a level-triggered interrupt signal (see {numref}`fig-configurable-gatewat-diagram`).\nTherefore, the interrupt request input signal must be set to the inactive level (i.e., to '0' for an active-high interrupt and to '1' for an active-low interrupt) to avoid an interrupt request being continuously reported as pending, even after the gateway's IP latch has been cleared.\nConsequently, if the gateway of an unused interrupt request input is programmed to an \"active-high\" polarity, the interrupt input signal must be tied off to '0'.\nSimilarly, if the polarity is programmed to \"active-low\", the interrupt input signal must be tied off to '1'.\n:::\n\n:::{note}\nFor asynchronous interrupt sources, the pulse duration of an interrupt request must be at least two full clock cycles of the receiving (i.e., PIC core) clock domain to guarantee it will be recognized as an interrupt request.\nShorter pulses might be dropped by the synchronizer circuit.\n:::\n\n### PIC Core\n\nThe PIC core's responsibility is to evaluate all pending and enabled interrupt requests and to pick the highest-priority request with the lowest interrupt source ID.\nIt then compares this priority with a programmable priority threshold and, to support nested interrupts, the priority of the interrupt handler if one is currently running.\nIf the picked request's priority is higher than both thresholds, it sends an interrupt notification to the core.\nIn addition, it compares the picked request's priority with the wake-up threshold (highest priority level) and sends a wake-up signal to the core, if the priorities match.\nThe PIC core also provides the interrupt source ID of the picked request in a status register.\n\n:::{note}\nDifferent levels in the evaluation tree may be staged wherever necessary to meet timing, provided that all signals of a request (ID, priority, etc.) are equally staged.\n:::\n\n### Interrupt Target\n\nThe interrupt target is a specific RISC-V hart context. For the VeeR EL2 core, the interrupt target is the M privilege mode of the hart.\n\n## PIC Block Diagram\n\n{numref}`fig-pic-block-diagram` depicts a high-level view of the PIC.\nA simple gateway for asynchronous, level-triggered interrupt sources is shown in {numref}`fig-gateway-for-asynchronous`, whereas {numref}`fig-configurable-gatewat-diagram` depicts conceptually the internal functional blocks of a configurable gateway.\n{numref}`fig-comparator` shows a single comparator which is the building block to form the evaluation tree logic in the PIC core.\n\n:::{figure-md} fig-pic-block-diagram\n![PIC Block Diagram](img/pic_diagram.png)\n\nPIC Block Diagram\n:::\n\n:::{note}\nFor R/W control/status registers with double-borders in {numref}`fig-pic-block-diagram`, the outputs of the registers are conditionally bit-wise inverted, depending on the priority order set in the *`priord`* bit of the `mpiccfg` register. This is necessary to support the reverse priority order feature.\n:::\n\n:::{note}\nThe PIC logic always operates in regular priority order. When in reverse priority order mode, firmware reads and writes the control/status registers with reverse priority order values. The values written to and read from the control/status registers are inverted. Therefore, from the firmware's perspective, the PIC operates in reverse priority order.\n:::\n\n:::{figure-md} fig-gateway-for-asynchronous\n![Gateway for Asynchronous, Level-triggered Interrupt sources](img/gateway.png)\n\nGateway for Asynchronous, Level-triggered Interrupt Sources\n:::\n\n:::{figure-md} fig-configurable-gatewat-diagram\n![Configurable Gateway Diagram](img/gateway_diagram.png)\n\nConceptual Block Diagram of a Configurable Gateway\n:::\n\n:::{figure-md} fig-comparator\n![Comparator](img/comparator.png)\n\nComparator\n:::\n\n## Theory Of Operation\n\n:::{note}\nInterrupts must be disabled (i.e., the *`mie`* bit in the standard RISC-V `mstatus` register must be cleared) before changing the standard RISC-V `mtvec` register or the PIC's `meicurpl` and `meipt` registers, or unexpected behavior may occur.\n:::\n\n### Initialization\n\nThe control registers must be initialized in the following sequence:\n\n1. Configure the priority order by writing the *`priord`* bit of the `mpiccfg` register.\n2. For each configurable gateway S, set the polarity (*polarity* field) and type (*type* field) in the `meigwctrlS` register and clear the IP bit by writing to the gateway's `meigwclrS` register.\n3. Set the base address of the external vectored interrupt address table by writing the *base* field of the `meivt` register.\n4. Set the priority level for each external interrupt source S by writing the corresponding *priority* field of the `meiplS` registers.\n5. Set the priority threshold by writing *prithresh* field of the `meipt` register.\n6. Initialize the nesting priority thresholds by writing '0' (or '15' for reversed priority order) to the *clidpri* field of the `meicidpl` and the *currpri* field of the `meicurpl` registers.\n7. Enable interrupts for the appropriate external interrupt sources by setting the *inten* bit of the `meieS` registers for each interrupt source S.\n\n### Regular Operation\n\nA step-by-step description of interrupt control and delivery:\n\n1. The external interrupt source S signals an interrupt request to its gateway by activating the corresponding `exintsrc_req[S]` signal.\n2. The gateway synchronizes the interrupt request from the asynchronous interrupt source's clock domain to the PIC core clock domain (`pic_clk`).\n3. For edge-triggered interrupts, the gateway also converts the request to a level-triggered interrupt signal by setting its internal interrupt pending (IP) bit.\n4. The gateway then signals the level-triggered request to the PIC core by asserting its interrupt request signal.\n5. The pending interrupt is visible to firmware by reading the corresponding intpend bit of the `meipX` register.\n6. With the pending interrupt, the source's interrupt priority (indicated by the priority field of the `meiplS` register) is forwarded to the evaluation logic.\n7. If the corresponding interrupt enable (i.e., *inten* bit of the `meieS` register is set), the pending interrupt's priority is sent to the input of the first-level 2-input comparator.\n8. The priorities of a pair of interrupt sources are compared:\n 1. If the two priorities are different, the higher priority and its associated hardwired interrupt source ID are forwarded to the second-level comparator.\n 1. If the two priorities are the same, the priority and the lower hardwired interrupt source ID are forwarded to the second-level comparator.\n9. Each subsequent level of comparators compares the priorities from two comparator outputs of the previous level:\n 1. If the two priorities are different, the higher priority and its associated interrupt source ID are forwarded to the next-level comparator.\n 1. If the two priorities are the same, the priority and the lower interrupt source ID are forwarded to the next-level comparator.\n10. The output of the last-level comparator indicates the highest priority (maximum priority) and lowest interrupt source ID (interrupt ID) of all currently pending and enabled interrupts.\n11. Maximum priority is compared to the higher of the two priority thresholds (i.e., *prithresh* field of the `meipt` and *currpri* field of the `meicurpl` registers):\n 1. If maximum priority is higher than the two priority thresholds, the `mexintirq` signal is asserted.\n 1. If maximum priority is the same as or lower than the two priority thresholds, the `mexintirq` signal is deasserted.\n12. The `mexintirq` signal's state is then reflected in the meip bit of the RISC-V hart's `mip` register.\n13. In addition, maximum priority is compared to the wake-up priority level:\n 1. If maximum priority is 15 (or 0 for reversed priority order), the wake-up notification (WUN) bit is set.\n 1. If maximum priority is lower than 15 (or 0 for reversed priority order), the wake-up notification (WUN) bit is not set.\n14. The WUN state is indicated to the target hart with the `mhwakeup` signal [^fn-interrupts-1].\n15. When the target hart takes the external interrupt, it disables all interrupts (i.e., clears the *mie* bit of the RISCV hart's `mstatus` register) and jumps to the external interrupt handler.\n16. The external interrupt handler writes to the `meicpct`register to trigger the capture of the interrupt source ID of the currently highest-priority pending external interrupt (in the meihap register) and its corresponding priority (in the `meicidpl` register). Note that the captured content of the claimid field of the meihap register and its corresponding priority in the `meicidpl` register is neither affected by the priority thresholds (prithresh field of the meipt and currpri field of the `meicurpl` registers) nor by the core's external interrupt enable bit (meie bit of the RISC-V hart's `mie` register).\n17. The handler then reads the meihap register to obtain the interrupt source ID provided in the *claimid* field. Based on the content of the meihap register, the external interrupt handler jumps to the handler specific to this external interrupt source.\n18. The source-specific interrupt handler services the external interrupt, and then:\n 1. For level-triggered interrupt sources, the interrupt handler clears the state in the SoC IP which initiated the interrupt request.\n 1. For edge-triggered interrupt sources, the interrupt handler clears the IP bit in the source's gateway by writing to the `meigwclrS` register.\n19. The clearing deasserts the source's interrupt request to the PIC core and stops this external interrupt source from participating in the highest priority evaluation.\n20. In the background, the PIC core continuously evaluates the next pending interrupt with highest priority and lowest interrupt source ID:\n 1. If there are other interrupts pending, enabled, and with a priority level higher than *prithresh* field of the `meipt` and *currpri* field of the `meicurpl` registers, `mexintirq` stays asserted.\n 1. If there are no further interrupts pending, enabled, and with a priority level higher than *prithresh* field of the `meipt` and *currpri* field of the `meicurpl` registers, `mexintirq` is deasserted.\n21. Firmware may update the content of the `meihap` and `meicidpl` registers by writing to the `meicpct` register to trigger a new capture.\n\n[^fn-interrupts-1]: Note that the core is only woken up from the power management Sleep (pmu/fw-halt) state if the `mie` bit of the `mstatus` and the meie bit of the `mie` standard RISC-V registers are both set.\n\n## Support for Vectored External Interrupts\n\n:::{note}\nThe RISC-V standard defines support for vectored interrupts down to an interrupt class level (i.e., timer, software, and external interrupts for each privilege level), but not to the granularity of individual external interrupt sources (as described in this section).\nThe two mechanisms are independent of each other and should be used together for lowest interrupt latency.\nFor more information on the standard RISC-V vectored interrupt support, see Section 3.1.7 in [[2]](intro.md#ref-2).\n:::\n\nThe VeeR EL2 PIC implementation provides support for vectored external interrupts.\nThe content of the `meihap` register is a full 32-bit pointer to the specific vector to the handler of the external interrupt source which needs service.\nThis pointer consists of a 22-bit base address (*base*) of the external interrupt vector table, the 8-bit claim ID (*claimid*), and a 2-bit '0' field.\nThe *claimid* field is adjusted with 2 bits of zeros to construct the offset into the vector table containing 32-bit vectors.\nThe external interrupt vector table resides either in the DCCM, SoC memory, or a dedicated flop array in the core.\n\n:::{figure-md} fig-vectored-external-interrupts\n![Vectored External Interrupts](img/vei.png)\n\nVectored External Interrupts\n:::\n\n{numref}`fig-vectored-external-interrupts` depicts the steps from taking the external interrupt to starting to execute the interrupt source-specific handler. When the core takes an external interrupt, the initiated external interrupt handler executes the following operations:\n\n1. Save register(s) used in this handler on the stack\n2. Store to the `meicpct` control/status register to capture a consistent claim ID / priority level pair\n3. Load the `meihap` control/status register into *`regX`*\n4. Load memory location at address in *`regX`* into *`regY`*\n5. Jump to address in *`regY`* (i.e., start executing the interrupt source-specific handler)\n\n:::{note}\nTwo registers (*`regX`* and *`regY`*) are shown above for clarification only. The same register can be used.\n:::\n\n:::{note}\nThe interrupt source-specific handler must restore the register(s) saved in step 1. above before executing the `mret` instruction.\n:::\n\nIt is possible in some corner cases that the captured claim ID read from the meihap register is 0 (i.e., no interrupt request is pending).\nTo keep the interrupt latency at a minimum, the external interrupt handler above should not check for this condition.\nInstead, the pointer stored at the base address of the external interrupt vector table (i.e., pointer 0) must point to a 'no-interrupt' handler, as shown in {numref}`fig-vectored-external-interrupts` above.\nThat handler can be as simple as executing a return from interrupt (i.e., `mret`) instruction.\n\nNote that it is possible for multiple interrupt sources to share the same interrupt handler by populating their respective interrupt vector table entries with the same pointer to that handler.\n\n### Fast Interrupt Redirect\n\nVeeR EL2 provides fast interrupt handing through interrupt redirection by hardware.\nThe fast interrupt redirect feature is configured with a build argument to the core.\n\nIf this feature is instantiated, hardware automatically captures a consistent claim ID / priority level pair once at least one qualifying external interrupt is pending and external interrupts are enabled (i.e., the *meie* bit in the `mie` register and the *mie* bit in the `mstatus` register are set).\nFollowing conceptually the same flow as shown in {numref}`fig-vectored-external-interrupts`, hardware uses the content of the meihap register to lookup the start address of the corresponding Interrupt Service Routine (ISR) by stalling decode and creating a bubble in the LSU pipeline.\nThis bubble allows the core to access the external interrupt vector table in the DCCM to get the start address of the interrupt source-specific ISR.\nOnce the start address of the ISR is known, hardware creates an interrupt flush and redirects directly to the corresponding ISR.\nIf the hardware lookup of the ISR's start address fails for any reason, a non-maskable interrupt (NMI, see [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)) is taken.\nThe reason for the lookup failure is reported in the mcause register (see {numref}`tab-machine-cause-register`) so firmware may determine which error condition has occurred.\n\nThe fast-interrupt-redirect-related NMI failure modes are:\n\n* Double-bit uncorrectable ECC error on access (`mcause` value: 0xF000_1000)\n* Access not entirely contained within the DCCM, but within DCCM region (`mcause` value: 0xF000_1001)\n* Access to non-DCCM region (`mcause` value: 0xF000_1002)\n\n:::{note}\nThe fast interrupt redirect mechanism is independent of the standard RISC-V direct and vectored interrupt modes.\nHowever, when fast interrupt redirect is enabled, external interrupts are bypassing the standard RISC-V interrupt mechanism.\nAll other interrupts are still following the standard flow.\n:::\n\n:::{note}\nThe fast interrupt redirect feature is not compatible with interrupt chaining concept described in [](interrupts.md#interrupt-chaining) below.\nThe `meicpct` register (see [External Interrupt Claim ID / Priority Level Capture Trigger Register (meicpct)](interrupts.md#external-interrupt-claim-id-priority-level-capture-trigger-register-meicpct)) to capture the latest interrupt evaluation result is not present if the fast interrupt redirect mechanism is instantiated because the capturing of the claim ID / priority level pair is initiated in hardware, instead of firmware.\n:::\n\n## Interrupt Chaining\n\n{numref}`fig-interrupt-chaining` depicts the concept of chaining interrupts.\nThe goal of chaining is to reduce the overhead of pushing and popping state to and from the stack while handling a series of Interrupt Service Routines (ISR) of the same priority level.\nThe first ISR of the chain saves the state common to all interrupt handlers of this priority level to the stack and then services its interrupt.\nIf this handler needs to save additional state, it does so immediately after saving the common state and then restores only the additional state when done.\nAt the end of the handler routine, the ISR writes to the `meicpct` register to capture the latest interrupt evaluation result, then reads the meihap register to determine if any other interrupts of the same priority level are pending.\n\nIf no, it restores the state from the stack and exits.\nIf yes, it immediately jumps into the next interrupt handler skipping the restoring of state in the finished handler as well as the saving of the same state in the next handler.\nThe chaining continues until no other ISRs of the same priority level are pending, at which time the last ISR of the chain restores the original state from the stack again.\n\n:::{note}\nInterrupt chaining is not compatible with the fast interrupt redirect feature (see [](interrupts.md#fast-interrupt-redirect)).\nIf the fast interrupt redirect mechanism is instantiated, interrupt chaining cannot be used.\n:::\n\n:::{figure-md} fig-interrupt-chaining\n![Interrupt Chaining](img/interrupt_chaining.png)\n\nConcept of Interrupt Chaining\n:::\n\n## Interrupt Nesting\n\nSupport for multiple levels of nested interrupts helps to provide a more deterministic interrupt latency at higher priority levels.\nTo achieve this, a running interrupt handler with lower priority must be preemptable by a higher-priority interrupt.\nThe state of the preempted handler is saved before the higher priority interrupt is executed, so that it can continue its execution at the point it was interrupted.\n\nVeeR EL2 and its PIC provide supported for up to 15 nested interrupts, one interrupt handler at each priority level.\n\nThe conceptual steps of nesting are:\n\n1. The external interrupt is taken as described in step 15. of [](interrupts.md#regular-operation). When the core takes the external interrupt, it automatically disables all interrupts.\n2. The external interrupt handler executes the following steps to get into the source-specific interrupt handler, as described in [](interrupts.md#support-for-vectored-external-interrupts):\n ```\n st meicpct // atomically captures winning claim ID and priority level\n ld meihap // get pointer to interrupt handler starting address\n ld isr_addr // load interrupt handler starting address\n jmp isr_addr // jump to source-specific interrupt handler\n ```\n3. The source-specific interrupt handler then saves the state of the code it interrupted (including the priority level in case it was an interrupt handler) to the stack, sets the priority threshold to its own priority, and then reenables interrupts:\n ```\n push mepc, mstatus, mie, …\n push meicurpl // save interrupted code's priority level\n ld meicidpl // read interrupt handler's priority level\n st meicurpl // change threshold to handler's priority\n mstatus.mei=1 // reenable interrupts\n ```\n4. Any external interrupt with a higher priority can now safely preempt the currently executing interrupt handler.\n5. Once the interrupt handler finished its task, it disables any interrupts and restores the state of the code it interrupted:\n ```\n mstatus.mei=0 // disable all interrupts\n pop meicurpl // get interrupted code's priority level\n st meicurpl // set threshold to previous priority\n pop mepc, mstatus, mie, …\n mret // return from interrupt, reenable interrupts\n ```\n6. The interrupted code continues to execute.\n\n## Power Reduction\n\nThe synchronizer and interrupt capture flops in the gateway of each external interrupt source are clocked every clock cycle even if the external interrupt request input signal is not changing.\nThese few flops cumulatively may consume a noticeable amount of the overall power of the VeeR EL2 core.\nVeeR EL2 implements a clock gating feature which turns off the clock to the synchronizer and interrupt capture flops for disabled external interrupt to reduce power consumption.\nHowever, the overhead to clock gate the flops associated with a single external interrupt source is significant enough that the potential power savings would be considerably reduced.\n\nTherefore, to maximize the power reduction, the gateways of four external interrupt sources are clock gated together as a group (i.e., external interrupt sources 1..3 (since 0 is not a valid interrupt source), 4..7, 8..11, and so on).\n\nIf at least one external interrupt of a group is enabled, the synchronizer and interrupt capture flops of all four gateways in that group are clocked every clock cycle.\nBut if all four external interrupts of a group are disabled, the synchronizer and interrupt capture flops of all four gateways in that group are clock gated.\n\nHowever, this change in functionality of the PIC has a software-visible impact.\nThe current status of pending external interrupt requests which are disabled may no longer be visible in the `meipX` registers (see [](interrupts.md#external-interrupt-pending-registers-meipx)).\n\nDepending on the interrupt servicing method, this may be of no consequence.\nHowever, for example, reliably polling the interrupt status of disabled interrupts periodically is no longer possible.\n\nThe *picio* bit of the `mcgc` register (see {numref}`tab-clock-gating-cr`) controls this power saving feature. Setting the *picio* control bit to '0' turns this feature on.\n\nNote that the default value of this clock gating feature is off (i.e., the *picio* bit is '1').\nIf the current status of pending external interrupt requests must be continuously reported in the meipX registers even for external interrupts which are disabled, this feature must remain turned off.\n\n## Performance Targets\n\nThe target latency through the PIC, including the clock domain crossing latency incurred by the gateway, is 4 core clock cycles.\n\n## Configurability\n\nTypical implementations require fewer than 255 external interrupt sources.\nCode should only be generated for functionality needed by the implementation.\n\n### Rules\n* The IDs of external interrupt sources must start at 1 and be contiguous.\n* All unused register bits must be hardwired to '0'.\n\n### Build Arguments\n\nThe PIC build arguments are:\n* **PIC base address for memory-mapped control/status registers (PIC_base_addr)**\n * See [](build-args.md#memory-related-build-arguments)\n* **Number of external interrupt sources**\n * Total interrupt sources (RV_PIC_TOTAL_INT): 2..255\n\n### Impact on Generated Code\n\n#### External Interrupt Sources\n\nThe number of required external interrupt sources has an impact on the following:\n\n* General impact:\n * Signal pins:\n * `extintsrc_req[S]`\n * Registers:\n * `meiplS`\n * `meipX`\n * Logic:\n * Gateway `S`\n* Target PIC core impact:\n * Registers:\n * `meieS`\n * Logic:\n * Gating of priority level with interrupt enable\n * Number of first-level comparators\n * Unnecessary levels of the comparator tree\n\n#### Further Optimizations\n\nRegister fields, bus widths, and comparator MUXs are sized to cover the maximum external interrupt source IDs of 255.\nFor approximately every halving of the number of interrupt sources, it would be possible to reduce the number of register fields holding source IDs, bus widths carrying source IDs, and source ID MUXs in the comparators by one.\nHowever, the overall reduction in logic is quite small, so it might not be worth the effort.\n\n## PIC Control/Status Registers\n\nA summary of the PIC control/status registers in CSR address space:\n\n* [](interrupts.md#external-interrupt-priority-threshold-register-meipt)\n* [](interrupts.md#external-interrupt-vector-table-register-meivt)\n* [](interrupts.md#external-interrupt-handler-address-pointer-register-meihap)\n* [External Interrupt Claim ID / Priority Level Capture Trigger Register (meicpct)](interrupts.md#external-interrupt-claim-id-priority-level-capture-trigger-register-meicpct)\n* [](interrupts.md#external-interrupt-claim-ids-priority-level-register-meicidpl)\n* [](interrupts.md#external-interrupt-current-priority-level-register-meicurpl)\n\nA summary of the PIC memory-mapped control/status registers:\n\n* [](interrupts.md#pic-configuration-register-mpiccfg)\n* [](interrupts.md#external-interrupt-priority-level-registers-meipls)\n* [](interrupts.md#external-interrupt-pending-registers-meipx)\n* [](interrupts.md#external-interrupt-enable-registers-meies)\n* [](interrupts.md#external-interrupt-gateway-configuration-registers-meigwctrls)\n* [](interrupts.md#external-interrupt-gateway-clear-registers-meigwclrs)\n\nAll reserved and unused bits in these control/status registers must be hardwired to '0'. Unless otherwise noted, all read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.\n\n:::{note}\nAll memory-mapped register writes must be followed by a fence instruction to enforce ordering and synchronization.\n:::\n\n:::{note}\nAll memory-mapped control/status register accesses must be word-sized and word-aligned. Non-word sized/aligned loads cause a load access fault exception, and non-word sized/aligned stores cause a store/AMO access fault exception.\n:::\n\n:::{note}\nAccessing unused addresses within the 32KB PIC address range do not trigger an unmapped address exception. Reads to unmapped addresses return 0, writes to unmapped addresses are silently dropped.\n:::\n\n### PIC Configuration Register (mpiccfg)\n\nThe PIC configuration register is used to select the operational parameters of the PIC.\n\nThis 32-bit register is an idempotent memory-mapped control register.\n\n:::{list-table} PIC Configuration Register (mpiccfg, at PIC_base_addr+0x3000)\n:name: tab-pic-configuration-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:1\n - Reserved\n - R\n - 0\n* - priord\n - 0\n - Priority order:\n - 0: RISC-V standard compliant priority order (0=lowest to 15=highest)\n - 1: Reverse priority order (15=lowest to 0=highest)\n - R/W\n - 0\n:::\n\n### External Interrupt Priority Level Registers (meiplS)\n\nThere are 255 priority level registers, one for each external interrupt source.\nImplementing individual priority level registers allows a debugger to autonomously discover how many priority level bits are supported for this interrupt source.\nFirmware must initialize the priority level for each used interrupt source.\nFirmware may also read the priority level.\n\n:::{note}\nThe read and write paths between the core and the `meiplS` registers must support direct and inverted accesses, depending on the priority order set in the *priord* bit of the `mpiccfg` register.\nThis is necessary to support the reverse priority order feature.\n:::\n\nThese 32-bit registers are idempotent memory-mapped control registers.\n\n:::{list-table} External Interrupt Priority Level Register S=1..255 (meiplS, at PIC_base_addr+S*4)\n:name: tab-external-interrupt-priority-level-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:4\n - Reserved\n - R\n - 0\n* - priority\n - 3:0\n - External interrupt priority level for interrupt source ID S\n - RISC-V standard compliant priority order:\n - 0: Never interrupt\n - 1..15: Interrupt priority level (1 is lowest, 15 is highest)\n - Reverse priority order:\n - 15: Never interrupt\n - 14..0: Interrupt priority level (14 is lowest, 0 is highest)\n - R/W\n - 0\n:::\n\n### External Interrupt Pending Registers (meipX)\n\nEight external interrupt pending registers are needed to report the current status of up to 255 independent external interrupt sources.\nEach bit of these registers corresponds to an interrupt pending indication of a single external interrupt source.\nThese registers only provide the status of pending interrupts and cannot be written.\n\n:::{note}\nIn VeeR EL2, by default, the status of disabled external interrupt requests are continuously reported in these registers.\nTo reduce power, the gateway's synchronizer and interrupt capture flops of disabled external interrupts may be gated (see [](interrupts.md#power-reduction)).\nHowever, if an up-to-date status of all pending interrupt requests is important, this clock gating feature controlled by the *picio* bit in the `mcgc` register (see {numref}`tab-clock-gating-cr`) must remain off.\n:::\n\nThese 32-bit registers are idempotent memory-mapped status registers.\n\n:::{list-table} External Interrupt Pending Register X=0..7 (meipX, at PIC_base_addr+0x1000+X*4)\n:name: tab-external-interrupt-pending-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - `X = 0, Y = 1..31 and X = 1..7, Y = 0..31`\n -\n -\n -\n -\n* - intpendX*32+Y\n - Y\n - External interrupt pending for interrupt source ID X*32+Y:\n - 0: Interrupt not pending\n - 1: Interrupt pending\n - R\n - 0\n* - `X = 0, Y = 0`\n -\n -\n -\n -\n* - Reserved\n - 0\n - Reserved\n - R\n - 0\n:::\n\n### External Interrupt Enable Registers (meieS)\n\nEach of the up to 255 independently controlled external interrupt sources has a dedicated interrupt enable register.\n\nSeparate registers per interrupt source were chosen for ease-of-use and compatibility with existing controllers.\n\n:::{note}\nNot packing together interrupt enable bits as bit vectors results in context switching being a more expensive operation.\n:::\n\nThese 32-bit registers are idempotent memory-mapped control registers.\n\n:::{list-table} External Interrupt Enable Register *S=1..255* (meieS, at PIC_base_addr+0x2000+S*4)\n:name: tab-external-interrupt-enable-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:1\n - Reserved\n - R\n - 0\n* - inten\n - 0\n - External interrupt enable for interrupt source ID S:\n - 0: Interrupt disabled\n - 1: Interrupt enabled\n - R/W\n - 0\n:::\n\n### External Interrupt Priority Threshold Register (meipt)\n\nThe `meipt` register is used to set the interrupt target's priority threshold.\nInterrupt notifications are sent to a target only for external interrupt sources with a priority level strictly higher than this target's threshold.\nHosting the threshold in a separate register allows a debugger to autonomously discover how many priority threshold level bits are supported.\n\n:::{note}\nThe read and write paths between the core and the `meipt` register must support direct and inverted accesses, depending on the priority order set in the *priord* bit of the `mpiccfg` register.\nThis is necessary to support the reverse priority order feature.\n:::\n\nThis 32-bit register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} External Interrupt Priority Threshold Register (`meipt`, at CSR 0xBC9)\n:name: tab-external-interrupt-priority-threshold-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:4\n - Reserved\n - R\n - 0\n* - prithresh\n - 3:0\n - External interrupt priority threshold:\n - RISC-V standard compliant priority order:\n - 0: No interrupts masked\n - 1..14: Mask interrupts with priority strictly lower than or equal to this threshold\n - 15: Mask all interrupts\n - Reverse priority order:\n - 15: No interrupts masked\n - 14..1: Mask interrupts with priority strictly lower than or equal to this threshold\n - 0: Mask all interrupts\n - R/W\n - 0\n:::\n\n### External Interrupt Vector Table Register (meivt)\n\nThe `meivt` register is used to set the base address of the external vectored interrupt address table.\nThe value written to the *base* field of the meivt register appears in the *base* field of the `meihap` register.\n\nThis 32-bit register is mapped to the non-standard read-write CSR address space.\n\n:::{list-table} External Interrupt Vector Table Register (meivt, at CSR 0xBC8)\n:name: tab-external-interrupt-vector-table-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - base\n - 31:10\n - Base address of external interrupt vector table\n - R/W\n - 0\n* - Reserved\n - 9:0\n - Reserved\n - R\n - 0\n:::\n\n### External Interrupt Handler Address Pointer Register (meihap)\n\nThe meihap register provides a pointer into the vectored external interrupt table for the highest-priority pending external interrupt.\nThe winning claim ID is captured in the *claimid* field of the meihap register when firmware writes to the `meicpct` register to claim an external interrupt.\nThe priority level of the external interrupt source corresponding to the *claimid* field of this register is simultaneously captured in the *clidpri* field of the `meicidpl` register.\nSince the PIC core is constantly evaluating the currently highest-priority pending interrupt, this mechanism provides a consistent snapshot of the highest-priority source requesting an interrupt and its associated priority level.\n\nThis is important to support nested interrupts.\n\nThe `meiha`p register contains the full 32-bit address of the pointer to the starting address of the specific interrupt handler for this external interrupt source.\nThe external interrupt handler then loads the interrupt handler's starting address and jumps to that address.\n\nAlternatively, the external interrupt source ID indicated by the *claimid* field of the `meihap` register may be used by the external interrupt handler to calculate the address of the interrupt handler specific to this external interrupt source.\n\n:::{note}\nThe *base* field in the meihap register reflects the current value of the *base* field in the `meivt` register. I.e., *base* is not stored in the `meihap` register.\n:::\n\nThis 32-bit register is mapped to the non-standard read-only CSR address space.\n\n:::{list-table} External Interrupt Handler Address Pointer Register (meihap, at CSR 0xFC8)\n:name: tab-external-interrupt-handler-address-pointer-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - base\n - 31:10\n - Base address of external interrupt vector table (i.e., *base* field of `meivt` register)\n - R\n - 0\n* - claimid\n - 9:2\n - External interrupt source ID of highest-priority pending interrupt (i.e., lowest source ID with highest priority)\n - R\n - 0\n* - 00\n - 1:0\n - Must read as '00'\n - R\n - 0\n:::\n\n### External Interrupt Claim ID / Priority Level Capture Trigger Register (meicpct)\n\nThe `meicpct` register is used to trigger the simultaneous capture of the currently highest-priority interrupt source ID (in the *claimid* field of the `meihap` register) and its corresponding priority level (in the *clidpri* field of the `meicidpl` register) by writing to this register.\nSince the PIC core is constantly evaluating the currently highest-priority pending interrupt, this mechanism provides a consistent snapshot of the highest-priority source requesting an interrupt and its associated priority level.\nThis is important to support nested interrupts.\n\n:::{note}\nThe `meicpct` register to capture the latest interrupt evaluation result is not present (i.e., an invalid CSR address) if the fast interrupt redirect mechanism (see [](interrupts.md#fast-interrupt-redirect)) is instantiated.\nWith that feature, capturing the claim ID / priority level pair is initiated in hardware, instead of firmware.\n:::\n\nThe `meicpct` register has WAR0 (Write Any value, Read 0) behavior. Writing '0' is recommended.\n\n:::{note}\nThe `meicpct` register does not have any physical storage elements associated with it.\nIt is write-only and solely serves as the trigger to simultaneously capture the winning claim ID and corresponding priority level.\n:::\n\nThis 32-bit register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} External Interrupt Claim ID / Priority Level Capture Trigger Register (`meicpct`, at CSR 0xBCA)\n:name: tab-external-interrupt-claim-id\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:0\n - Reserved\n - R0/WA\n - 0\n:::\n\n### External Interrupt Claim ID's Priority Level Register (meicidpl)\n\nThe `meicidpl` register captures the priority level corresponding to the interrupt source indicated in the *claimid* field of the `meihap` register when firmware writes to the `meicpct` register.\nSince the PIC core is constantly evaluating the currently highest-priority pending interrupt, this mechanism provides a consistent snapshot of the highest-priority source requesting an interrupt and its associated priority level.\nThis is important to support nested interrupts.\n\n:::{note}\nThe read and write paths between the core and the `meicidpl` register must support direct and inverted accesses, depending on the priority order set in the *priord* bit of the `mpiccfg` register.\nThis is necessary to support the reverse priority order feature.\n:::\n\nThis 32-bit register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} External Interrupt Claim ID’s Priority Level Register (`meicidpl`, at CSR 0xBCB)\n:name: tab-external-interrupt-claim-id-priority-level-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:4\n - Reserved\n - R\n - 0\n* - clidpri\n - 3:0\n - Priority level of preempting external interrupt source (corresponding to source ID read from *claimid* field of `meihap` register)\n - R/W\n - 0\n:::\n\n### External Interrupt Current Priority Level Register (meicurpl)\n\nThe `meicurpl` register is used to set the interrupt target's priority threshold for nested interrupts.\nInterrupt notifications are signaled to the core only for external interrupt sources with a priority level strictly higher than the thresholds indicated in this register and the `meipt` register.\n\nThe `meicurpl` register is written by firmware, and not updated by hardware.\nThe interrupt handler should read its own priority level from the *clidpri* field of the `meicidpl` register and write it to the *currpri* field of the `meicurpl` register.\nThis avoids potentially being interrupted by another interrupt request with lower or equal priority once interrupts are reenabled.\n\n:::{note}\n Providing the `meicurpl` register in addition to the meipt threshold register enables an interrupt service routine to temporarily set the priority level threshold to its own priority level. Therefore, only new interrupt requests with a strictly higher priority level are allowed to preempt the current handler, without modifying the longer-term threshold set by firmware in the `meipt` register.\n:::\n\n:::{note}\nThe read and write paths between the core and the `meicurpl` register must support direct and inverted accesses, depending on the priority order set in the *priord* bit of the `mpiccfg` register.\nThis is necessary to support the reverse priority order feature.\n:::\n\nThis 32-bit register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} External Interrupt Current Priority Level Register (meicurpl, at CSR 0xBCC)\n:name: tab-external-interrupt-current-priority-level-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:4\n - Reserved\n - R\n - 0\n* - currpri\n - 3:0\n - Priority level of current interrupt service routine (managed by firmware)\n - R/W\n - 0\n:::\n\n### External Interrupt Gateway Configuration Registers (meigwctrlS)\n\nEach configurable gateway has a dedicated configuration register to control the interrupt type (i.e., edge- vs. level-triggered) as well as the interrupt signal polarity (i.e., low-to-high vs. high-to-low transition for edge-triggered interrupts, active-high vs. -low for level-triggered interrupts).\n\n:::{note}\nA register is only present for interrupt source S if a configurable gateway is instantiated.\n:::\n\nThese 32-bit registers are idempotent memory-mapped control registers.\n\n:::{list-table} External Interrupt Gateway Configuration Register S=1..255 (meigwctrlS, at PIC_base_addr+0x4000+S*4)\n:name: tab-external-interrupt-gateway-configuration-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:2\n - Reserved\n - R\n - 0\n* - type\n - 1\n - External interrupt type for interrupt source ID S:\n - 0: Level-triggered interrupt\n - 1: Edge-triggered interrupt\n - R/W\n - 0\n* - polarity\n - 0\n - External interrupt polarity for interrupt source ID S:\n - 0: Active-high interrupt\n - 1: Active-low interrupt\n - R/W\n - 0\n:::\n\n### External Interrupt Gateway Clear Registers (meigwclrS)\n\nEach configurable gateway has a dedicated clear register to reset its interrupt pending (IP) bit.\nFor edge-triggered interrupts, firmware must clear the gateway's IP bit while servicing the external interrupt of source ID S by writing to the `meigwclrS` register.\n\n:::{note}\nA register is only present for interrupt source S if a configurable gateway is instantiated.\n:::\n\nThe `meigwclrS` register has WAR0 (Write Any value, Read 0) behavior. Writing '0' is recommended.\n\n:::{note}\nThe `meigwclrS` register does not have any physical storage elements associated with it.\nIt is write-only and solely serves as the trigger to clear the interrupt pending (IP) bit of the configurable gateway S.\n:::\n\nThese 32-bit registers are idempotent memory-mapped control registers.\n\n:::{list-table} External Interrupt Gateway Clear Register *S=1..255* (meigwclrS, at PIC_base_addr+0x5000+S*4)\n:name: tab-external-interrupt-gateway-clear-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:0\n - Reserved\n - R0/WA\n - 0\n:::\n\n## PIC CSR Address Map\n\n{numref}`tab-pic-non-standard-risc-v-csr-address-map` summarizes the PIC non-standard RISC-V CSR address map.\n\n:::{list-table} PIC Non-standard RISC-V CSR Address Map\n:name: tab-pic-non-standard-risc-v-csr-address-map\n\n* - **Number**\n - **Privilege**\n - **Name**\n - **Description**\n - **Section**\n* - 0xBC8\n - MRW\n - meivt\n - External interrupt vector table register\n - [](interrupts.md#external-interrupt-vector-table-register-meivt)\n* - 0xBC9\n - MRW\n - meipt\n - External interrupt priority threshold register\n - [](interrupts.md#external-interrupt-priority-threshold-register-meipt)\n* - 0xBCA\n - MRW\n - meicpct\n - External interrupt claim ID / priority level capture trigger register\n - [External Interrupt Claim ID / Priority Level Capture Trigger Register (meicpct)](interrupts.md#external-interrupt-claim-id-priority-level-capture-trigger-register-meicpct)\n* - 0xBCB\n - MRW\n - meicidpl\n - External interrupt claim ID’s priority level register\n - [External Interrupt Claim ID’s Priority Level Register (meicidpl)](interrupts.md#external-interrupt-claim-id-s-priority-level-register-meicidpl)\n* - 0xBCC\n - MRW\n - meicurpl\n - External interrupt current priority level register\n - [](interrupts.md#external-interrupt-current-priority-level-register-meicurpl)\n* - 0xFC8\n - MRO\n - meihap\n - External interrupt handler address pointer register\n - [](interrupts.md#external-interrupt-handler-address-pointer-register-meihap)\n:::\n\n## PIC Memory-Mapped Register Address Map\n\n{numref}`tab-pic-memory-mapped-register-address-map` summarizes the PIC memory-mapped register address map.\n\n:::{list-table} PIC Memory-mapped Register Address Map\n:name: tab-pic-memory-mapped-register-address-map\n\n* - **Address Offset from PIC_base_addr**\n - **Address Offset from PIC_base_addr**\n -\n -\n -\n* - **Start**\n - **End**\n - **Name**\n - **Description**\n - **Section**\n* - + 0x0000\n - + 0x0003\n - Reserved\n - Reserved\n -\n* - + 0x0004\n - + 0x0004 + {math}`S_{max}`*4-1\n - meiplS\n - External interrupt priority level register\n - [](interrupts.md#external-interrupt-priority-level-registers-meipls)\n* - + 0x0004 + {math}`S_{max}`*4\n - + 0x0FFF\n - Reserved\n - Reserved\n -\n* - + 0x1000\n - + 0x1000 + ({math}`X_{max}`+1)*4-1\n - meipX\n - External interrupt pending register\n - [](interrupts.md#external-interrupt-pending-registers-meipx)\n* - + 0x1000 + ({math}`X_{max}`+1)*4\n - + 0x1FFF\n - Reserved\n - Reserved\n -\n* - + 0x2000\n - + 0x2003\n - Reserved\n - Reserved\n -\n* - + 0x2004\n - + 0x2004 + {math}`S_{max}`*4-1\n - meieS\n - External interrupt enable register\n - [](interrupts.md#external-interrupt-enable-registers-meies)\n* - + 0x2004 + {math}`S_{max}`*4\n - + 0x2FFF\n - Reserved\n - Reserved\n -\n* - + 0x3000\n - + 0x3003\n - mpiccfg\n - External interrupt PIC configuration register\n - [](interrupts.md#pic-configuration-register-mpiccfg)\n* - + 0x3004\n - + 0x3FFF\n - Reserved\n - Reserved\n -\n* - + 0x4000\n - + 0x4003\n - Reserved\n - Reserved\n -\n* - + 0x4004\n - + 0x4004 + {math}`S_{max}`*4-1\n - meigwctrlS\n - External interrupt gateway configuration register (for configurable gateways only)\n - [](interrupts.md#external-interrupt-gateway-configuration-registers-meigwctrls)\n* - + 0x4004 + {math}`S_{max}`*4\n - + 0x4FFF\n - Reserved\n - Reserved\n -\n* - + 0x5000\n - + 0x5003\n - Reserved\n - Reserved\n -\n* - + 0x5004\n - + 0x5004 + {math}`S_{max}`*4-1\n - meigwclrS\n - External interrupt gateway clear register (for configurable gateways only)\n - [](interrupts.md#external-interrupt-gateway-clear-registers-meigwclrs)\n* - + 0x5004 + {math}`S_{max}`*4\n - + 0x7FFF\n - Reserved\n - Reserved\n -\n:::\n\n:::{note}\n {math}`X_{max}` = ({math}`S_{max}` + 31) // 32, whereas // is an integer division ignoring the remainder\n:::\n\n## Interrupt Enable/Disable Code Samples\n\n### Example Interrupt Flows\n\n* Macro flow to enable interrupt source id 5 with priority set to 7, threshold set to 1, and gateway configured for edge-triggered/active-low interrupt source:\n ```asm\n disable_ext_int // Disable interrupts (MIE[meip]=0)\n set_threshold 1 // Program global threshold to 1\n init_gateway 5, 1, 1 // Configure gateway id=5 to edge-triggered/low\n clear_gateway 5 // Clear gateway id=5\n set_priority 5, 7 // Set id=5 threshold at 7\n enable_interrupt 5 // Enable id=5\n enable_ext_int // Enable interrupts (MIE[meip]=1)\n ```\n* Macro flow to initialize priority order:\n * To RISC-V standard order:\n ```asm\n init_priorityorder 0 // Set priority to standard RISC-V order\n init_nstthresholds 0 // Initialize nesting thresholds to 0\n ```\n * To reverse priority order:\n ```asm\n init_priorityorder 1 // Set priority to reverse order\n init_nstthresholds 15 // Initialize nesting thresholds to 15\n ```\n* Code to jump to the interrupt handler from the RISC-V trap vector:\n ```asm\n trap_vector: // Interrupt trap starts here when MTVEC[mode]=1\n csrwi meicpct, 1 // Capture winning claim id and priority\n csrr t0, meihap // Load pointer index\n lw t1, 0(t0) // Load vector address\n jr t1 // Go there\n ```\n\n* Code to handle the interrupt:\n ```asm\n eint_handler:\n : // Do some useful interrupt handling\n mret // Return from ISR\n ```\n\n### Example Interrupt Macros\n\n* Disable external interrupt:\n ```asm\n .macro disable_ext_int\n // Clear MIE[miep]\n disable_ext_int_\\@:\n li a0, (1<<11)\n csrrc zero, mie, a0\n .endm\n ```\n* Enable external interrupt:\n ```asm\n .macro enable_ext_int\n enable_ext_int_\\@:\n // Set MIE[miep]\n li a0, (1<<11)\n csrrs zero, mie, a0\n .endm\n ```\n* Initialize external interrupt priority order:\n ```asm\n .macro init_priorityorder priord\n init_priorityorder_\\@:\n li tp, (RV_PIC_BASE_ADDR + RV_PIC_MPICCFG_OFFSET)\n li t0, \\priord\n sw t0, 0(tp)\n .endm\n ```\n* Initialize external interrupt nesting priority thresholds:\n ```asm\n .macro init_nstthresholds threshold\n init_nstthresholds_\\@:\n li t0, \\threshold li tp, (RV_PIC_BASE_ADDR + RV_PIC_MEICIDPL_OFFSET)\n sw t0, 0(tp)\n li tp, (RV_PIC_BASE_ADDR + RV_PIC_MEICURPL_OFFSET)\n sw t0, 0(tp)\n .endm\n ```\n* Set external interrupt priority threshold:\n ```asm\n .macro set_threshold threshold\n set_threshold_\\@:\n li tp, (RV_PIC_BASE_ADDR + RV_PIC_MEIPT_OFFSET)\n li t0, \\threshold\n sw t0, 0(tp)\n .endm\n ```\n* Enable interrupt for source *id*:\n ```asm\n .macro enable_interrupt id\n enable_interrupt_\\@:\n li tp, (RV_PIC_BASE_ADDR + RV_PIC_MEIE_OFFSET + (\\id <<2))\n li t0, 1\n sw t0, 0(tp)\n .endm\n ```\n* Set priority of source *id*:\n ```asm\n .macro set_priority id, priority\n set_priority_\\@:\n li tp, (RV_PIC_BASE_ADDR + RV_PIC_MEIPL_OFFSET + (\\id <<2))\n li t0, \\priority\n sw t0, 0(tp)\n .endm\n ```\n* Initialize gateway of source *id*:\n ```asm\n .macro init_gateway id, polarity, type\n init_gateway_\\@:\n li tp, (RV_PIC_BASE_ADDR + RV_PIC_MEIGWCTRL_OFFSET + (\\id <<2))\n li t0, ((\\type<<1) | \\polarity)\n sw t0, 0(tp)\n .endm\n ```\n* Clear gateway of source *id*:\n ```asm\n .macro clear_gateway id\n clear_gateway_\\@:\n li tp, (RV_PIC_BASE_ADDR + RV_PIC_MEIGWCLR_OFFSET + (\\id <<2))\n sw zero, 0(tp)\n .endm\n ```\n" }, { "path": "docs/source/intro.md", "content": "# RISC-V VeeR EL2 Programmer's Reference Manual\n\n**Revision:** 2.0 January 14, 2025\n\n![CHIPS Alliance logo](img/logo.png)\n![VeeR project logo](img/VeeR-logo-white-rgb.png)\n\n```\nSPDX-License-Identifier: Apache-2.0 Copyright © 2022 CHIPS Alliance.\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n https://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software distributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and limitations under the License.\n```\n\n## Document Revision History\n\n:::{list-table} Revision History\n:name: tab-revision-history\n:header-rows: 1\n\n* - Revision\n - Date\n - Contents\n* - 1.0\n - Jan 23, 2020\n - Changes:\n - initial revision\n* - 1.1\n - Mar 4, 2020\n - Changes:\n - added note that mscause values are subject to change (section [](memory-map.md#machine-secondary-cause-register-mscause))\n - added note that uninitialized DCCM may cause loads to get incorrect data (section []( error-protection.md#error-detection-and-handling))\n - added Debug Module reset description (section [Debug Module Reset (dbg_rst_l)](clocks.md#debug-module-reset-dbg-rst-l))\n - updated port list ({numref}`tab-core-complex-signals`):\n - added dbg_rst_l signal\n - added footnote clarifying trace port signals\n - fixed width of trace_rv_i_interrupt_ip bus\n - added 'Compliance Test Suite Failures' chapter [](tests.md)\n* - 1.2\n - Mar 29, 2020\n - Changes:\n - fixed note how writing illegal value to mrac register is handled by hardware in [](memory-map.md#region-access-control-register-mrac)\n - removed note that mscause values are subject to change in [](memory-map.md#machine-secondary-cause-register-mscause)\n - updated mscause values ({numref}`tab-machine-secondary-cause-register`)\n - added [Internal Timers chapter](timers.md) and references throughout document\n - incremented mimpid register value from '1' to '2' ({numref}`tab-veer-el2-core-specific-std-rv-machine-information-csrs`)\n* - 1.3\n - Nov 16, 2020\n - Changes:\n - updated versions of RISC-V Base ISA [[1]](ref-1) and Privileged [[2]](ref-2) and link to RISC-V Debug [[3]](ref-3) specifications (Reference Documents)\n - added RISC-V Bit-manipulation sub-extensions (Reference Documents, sections [](overview.md#features) and [](overview.md#standard-extensions), and {numref}`tab-list-of-countable-events`)\n - added footnote that misaligned accesses to side-effect regions trigger a misaligned exception instead of the recommended access fault exception ({numref}`tab-handling-misaligned-addresses`)\n - added note to mdseac register description clarifying captured address in [](memory-map.md#d-bus-first-error-address-capture-register-mdseac)\n - clarified that mscause value of '0' indicates no additional information available ([](memory-map.md#machine-secondary-cause-register-mscause))\n - added description of SoC access expectation ([](memory-map.md#expected-soc-behavior-for-accesses))\n - added note that NMIs are fatal ([](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector))\n - added note that mitcnt0/1 register is not cleared if write to it coincides with internal timer interrupt ([Internal Timer Counter 0 / 1 Register (mitcnt0/1)](timers.md#internal-timer-counter-0-1-register-mitcnt0-1))\n - clarified note that debug single-step action is delayed while MPC debug halted ([](power.md#power-states))\n - added cross-references to debug CSR descriptions ({numref}`tab-core-activity-states`, {numref}`tab-veer-el2-multi-core-debug-ctrl-status-signals`, {numref}`tab-veer-el2-std-risc-v-csr-address-map`, and sections [](performance.md#count-impacting-conditions) and [](clocks.md#core-complex-reset-to-debug-mode))\n - added note that debug single-stepping stays pending while MPC debug halted ([](power.md#single-stepping))\n - removed note that PMU halt or run request may not be acknowledged if already in requested activity state ([](power.md#power-control-and-status-signals))\n - amended debug_mode_status signal description ({numref}`tab-veer-el2-multi-core-debug-ctrl-status-signals`)\n - added note that mpc_debug_run_req is required to exit Debug Mode if entered after reset using mpc_reset_run_req ([](power.md#multi-core-debug-control-and-status-signals))\n - added PIC I/O power reduction feature description (sections [](interrupts.md#features), [](interrupts.md#power-reduction), and [](interrupts.md#external-interrupt-pending-registers-meipx) and {numref}`tab-clock-gating-cr`)\n - added note that spurious interrupts may be captured for disabled external interrupts ([](interrupts.md#gateway))\n - added note that edge-triggered interrupt lines must be tied off to inactive state ([](interrupts.md#gateway))\n - fixed gateway initialization macro example ([](interrupts.md#example-interrupt-macros))\n - added note that mtime and mtimecmp registers must be provided by SoC ([](performance.md#standard-risc-v-registers))\n - changed value when writing unsupported event number to mhpmevent3-6 registers to '0' ([](performance.md#events))\n - added note that index field does not have WARL behavior ({numref}`tab-cache-array-dicawics`)\n - added [Debug Support chapter](debugging.md)\n - added 'trace disable' bit to mfdc register ({numref}`tab-feature-disable-cr`)\n - clarified effect of sepd bit of mfdc register ({numref}`tab-feature-disable-cr`)\n - added note regarding physical design considerations for rst_l signal ([Core Complex Reset (rst_l)](clocks.md#core-complex-reset-rst-l))\n - updated 'Reset to Debug-Mode' description ([](clocks.md#core-complex-reset-to-debug-mode))\n - updated trace port interrupt/exception signaling to new optimized scheme ({numref}`tab-core-complex-signals`)\n - added erratum for abstract command register read capability ([](errata.md#debug-abstract-command-register-may-return-non-zero-value-on-read))\n - incremented mimpid register value from '2' to '3' ({numref}`tab-veer-el2-core-specific-std-rv-machine-information-csrs`)\n* - 1.4\n - Apr 19, 2022\n - Changes:\n - updated version and link of RISC-V Bit-manipulation [[4]](ref-4) specification (Reference Documents)\n - updated list of sub-extension instructions to RISC-V Bitmanip Extension specification version 0.94-draft (1/20/21) ([](overview.md#standard-extensions))\n - updated note regarding priority of simultaneous store and non-blocking load bus errors ([](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n - fixed register name and added cross-reference (Footnote 20)\n - added footnote that load/store access crossing upper boundary of DCCM or PIC memory range report base address of access in mtval register (Footnote 22)\n - clarified that correctable error counter/threshold registers are always instantiated (sections [I-Cache Error Counter/Threshold Register (micect)](error-protection.md#i-cache-error-counter-threshold-register-micect), [Iccm Correctable Error Counter/Threshold Register (miccmect)](error-protection.md#iccm-correctable-error-counter-threshold-register-miccmect), and [Dccm Correctable Error Counter/Threshold Register (mdccmect)](error-protection.md#dccm-correctable-error-counter-threshold-register-mdccmect))\n - corrected PIC I/O power reduction feature description ([](interrupts.md#power-reduction))\n - incremented mimpid register value from '3' to '4' ({numref}`tab-veer-el2-core-specific-std-rv-machine-information-csrs`)\n* - 2.0\n - Jan 14, 2025\n - Changes:\n - Added description of PMP and ePMP functionalities\n - Added description of RISC-V User privilege level\n - Added information on verification, debugging and running Tock\n:::\n\n## Reference Documents\n\n:::{list-table} Reference Documents\n:name: tab-reference-documents\n:header-rows: 1\n\n* - **Item #**\n - **Document**\n - **Revision Used**\n - **Comment**\n* - 1\n - The RISC-V Instruction Set Manual Volume I: User-Level ISA\n - 20190608-Base-Ratified\n - Specification ratified\n* - 2\n - The RISC-V Instruction Set Manual Volume II: Privileged Architecture\n - 20190608-Priv-MSU-Ratified\n - Specification ratified\n* - 2 (PLIC)\n - The RISC-V Instruction Set Manual Volume II: Privileged Architecture\n - 1.11-draft\n\n December 1, 2018\n - Last specification version with PLIC chapter\n* - 3\n - RISC-V External Debug Support\n - 0.13.2\n - Specification ratified\n* - 4\n - RISC-V Bitmanip Extension\n - 0.94-draft (January 20, 2021)\n - Zba, Zbb, Zbc, and Zbs subextensions are \"frozen\"\n* - 5\n - The RISC-V Instruction Set Manual Volume II: Privileged Architecture\n - Document Version 20211203\n - Specification ratified\n* - 6\n - PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)\n - Version 1.0, 12/2021\n - Specification ratified\n\n:::\n\n## Abbreviations\n\n:::{table} Abbreviations\n:name: tab-abbreviations\n:header-rows: 1\n\n| Abbreviation | Description |\n|----------------|--------------------------------------------------------|\n| AHB | Advanced High-performance Bus (by ARM) |\n| AMBA | Advanced Microcontroller Bus Architecture (by ARM) |\n| ASIC | Application Specific Integrated Circuit |\n| AXI | Advanced eXtensible Interface (by ARM) |\n| CCM | Closely Coupled Memory (= TCM) |\n| CPU | Central Processing Unit |\n| CSR | Control and Status Register |\n| DCCM | Data Closely Coupled Memory (= DTCM) |\n| DEC | DECoder unit (part of core) |\n| DMA | Direct Memory Access |\n| DTCM | Data Tightly Coupled Memory (= DCCM) |\n| ECC | Error Correcting Code |\n| EXU | EXecution Unit (part of core) |\n| ICCM | Instruction Closely Coupled Memory (= ITCM) |\n| IFU | Instruction Fetch Unit |\n| ITCM | Instruction Tightly Coupled Memory (= ICCM) |\n| JTAG | Joint Test Action Group |\n| LSU | Load/Store Unit (part of core) |\n| MPC | Multi-Processor Controller |\n| MPU | Memory Protection Unit |\n| NMI | Non-Maskable Interrupt |\n| PIC | Programmable Interrupt Controller |\n| PLIC | Platform-Level Interrupt Controller |\n| POR | Power-On Reset |\n| RAM | Random Access Memory |\n| RAS | Return Address Stack |\n| ROM | Read-Only Memory |\n| SECDED | Single-bit Error Correction/Double-bit Error Detection |\n| SEDDED | Single-bit Error Detection/Double-bit Error Detection |\n| SoC | System on Chip |\n| TBD | To Be Determined |\n| TCM | Tightly Coupled Memory (= CCM) |\n:::\n" }, { "path": "docs/source/memory-map.md", "content": "# Memory Map\n\nThis chapter describes the memory map as well as the various memories and their properties of the VeeR EL2 core.\n\n## Address Regions\n\nThe 32-bit address space is subdivided into sixteen fixed-sized, contiguous 256MB regions.\nEach region has a set of access control bits associated with it ([](memory-map.md#region-access-control-register-mrac)).\n\n## Access Properties\n\nEach region has two access properties which can be independently controlled. They are:\n\n* **Cacheable:** Indicates if this region is allowed to be cached or not.\n* **Side effect:** Indicates if read/write accesses to this region may have side effects (i.e., non-idempotent accesses which may potentially have side effects on any read/write access; typical for I/O, speculative or redundant accesses must be avoided) or have no side effects (i.e., idempotent accesses which have no side effects even if the same access is performed multiple times; typical for memory).\n Note that stores with potential side effects (i.e., to non-idempotent addresses) cannot be combined with other stores in the core's unified read/write buffer.\n\n## Memory Types\n\nThere are two different classes of memory types mapped into the core's 32-bit address range, core local and system bus attached.\n\n### Core Local\n\n#### ICCM and DCCM\n\nTwo dedicated memories, one for instruction and the other for data, are tightly coupled to the core.\nThese memories provide low-latency access and SECDED ECC protection.\nTheir respective sizes (4, 8, 16, 32, 48 [^fn-iccm-dccm-1], 64, 128, 256, or 512KB) are set as arguments at build time of the core.\n\n[^fn-iccm-dccm-1]: DCCM only\n\n#### Local Memory-Mapped Control/Status Registers\n\nTo provide control for regular operation, the core requires a number of memory-mapped control/status registers.\nFor example, some external interrupt functions are controlled and serviced with accesses to various registers while the system is running.\n\n### Accessed via System Bus\n\n#### System ROMs\nThe SoC may host ROMs which are mapped to the core's memory address range and accessed via the system bus.\nBoth instruction and data accesses are supported to system ROMs.\n\n#### System SRAMs\nThe SoC hosts a variety of SRAMs which are mapped to the core's memory address range and accessed via the system bus.\n\n#### System Memory-Mapped I/O\n\nThe SoC hosts a variety of I/O device interfaces which are mapped to the core's memory address range and accessed via the system bus.\n\n### Mapping Restrictions\n\nCore-local memories and system bus-attached memories must be mapped to different regions. Mapping both classes of memory types to the same region is not allowed.\n\nFurthermore, it is recommended that all core-local memories are mapped to the same region.\n\n## Memory Type Access Properties\n\n{numref}`tab-access-properites-memory-type` specifies the access properties of each memory type. During system boot, firmware must initialize the properties of each region based on the memory type present in that region.\n\n:::{note}\nSome memory-mapped I/O and control/status registers may have no side effects (i.e., are idempotent), but characterizing all these registers as having potentially side effects (i.e., are non-idempotent) is safe.\n:::\n\n:::{list-table} Access Properties for each Memory Type\n:name: tab-access-properites-memory-type\n:header-rows: 1\n\n* - **Region**\n - **Memory Type**\n - **Cacheable**\n - **Side Effect**\n* - **Core Local**\n - ICCM\n - No\n - No\n* - Core Local\n - DCCM\n - No\n - No\n* - Core Local\n - Memory-mapped control/status registers\n - No\n - Yes\n* - Accessed via System Bus\n - ROMs\n - Yes\n - No\n* - Accessed via System Bus\n - SRAMs\n - Yes\n - No\n* - Accessed via System Bus\n - I/Os\n - No\n - Yes\n* - Accessed via System Bus\n - Memory-mapped control/status registers\n - No\n - Yes\n:::\n\n:::{note}\n 'Cacheable = Yes' and 'Side Effect = Yes' is an illegal combination.\n:::\n\n## Memory Access Ordering\n\nLoads and stores to system bus-attached memory (i.e. accesses with no side effects, idempotent) and devices (i.e. accesses with potential side effects, non-idempotent) pass through a unified read/write buffer.\nThe buffer is implemented as a FIFO.\n\n### Load-To-Load and Store-To-Store Ordering\n\nAll loads are sent to the system bus interface in program order. Also, all stores are sent to the system bus interface in program order.\n\n### Load/Store Ordering\n\n#### Accesses with Potential Side Effects (i.e., Non-Idempotent)\n\nWhen a load with potential side effects (i.e., non-idempotent) enters the buffer, the entire unified buffer is emptied, i.e., both stores with no side effects (i.e., idempotent) and with potential side effects (i.e., non-idempotent) are drained out.\nLoads with potential side effects (i.e., non-idempotent) are sent out to the system bus with their exact size.\n\nStores with potential side effects (i.e., non-idempotent) are neither coalesced nor forwarded to a load.\n\n#### Accesses with No Side Effects (i.e., Idempotent)\n\nLoads with no side effects (i.e., idempotent) are always issued as double-words and check the contents of the unified buffer:\n\n1. **Full address match** (all load bytes present in the unified buffer): Data is forwarded from the unified buffer.\n The load does not go out to the system bus.\n2. **Partial address match** (some of the load bytes are in the unified buffer): The entire unified buffer is emptied, then the load request goes to the system bus.\n3. **No match** (none of the bytes are in the unified buffer): The load is presented to the system bus interface without waiting for the stores to drain.\n\n#### Ordering of Store - Load with No Side Effects (i.e., Idempotent)\n\nA `fence` instruction is required to order an older store before a younger load with no side effects (i.e., idempotent).\n\n:::{note}\n All memory-mapped register writes must be followed by a `fence` instruction to enforce ordering and synchronization.\n:::\n\n### Fencing\n\n#### Instructions\n\nThe `fence.i` instruction operates on the instruction memory and/or I-cache.\nThis instruction causes a flush, a flash invalidation of the I-cache, and a refetch of the next program counter (RFNPC).\nThe refetch is guaranteed to miss the I-cache.\nNote that since the `fence.i` instruction is used to synchronize the instruction and data streams, it also includes the functionality of the `fence` instruction (see [](memory-map.md#data)).\n\n#### Data\n\nThe `fence` instruction is implemented conservatively in VeeR EL2 to keep the implementation simple.\nIt always performs the most conservative fencing, independent of the instruction's arguments.\nThe `fence` instruction is presynced to make sure that there are no instructions in the LSU pipe.\nIt stalls until the LSU indicates that the store buffer and unified buffer have been fully drained (i.e., are empty).\nThe `fence` instruction is only committed after all LSU buffers are idle and all outstanding bus transactions are completed.\n\n### Imprecise Data Bus Errors\n\nAll store errors as well as non-blocking load errors on the system bus are imprecise.\nThe address of the first occurring imprecise data system bus error is logged and a non-maskable interrupt (NMI) is flagged for the first reported error only.\nFor stores, if there are other stores in the unified buffer behind the store which had the error, these stores are sent out on the system bus and any error responses are ignored.\nSimilarly, for non-blocking loads, any error responses on subsequent loads sent out on the system bus are ignored.\nNMIs are fatal, architectural state is lost, and the core needs to be reset.\nThe reset also unlocks the first error address capture register again.\n\n:::{note}\n It is possible to unlock the first error address capture register with a write to an unlock register as well (see [](memory-map.md#d-bus-error-address-unlock-register-mdeau) for more details), but this may result in unexpected behavior.\n:::\n\n## Memory Protection\n\nTo eliminate issuing speculative accesses to the IFU and LSU bus interfaces, VeeR EL2 provides a rudimentary memory protection mechanism for instruction and data accesses outside of the ICCM and DCCM memory regions.\nSeparate core build arguments for instructions and data are provided by the Memory Protection Unit (MPU) to enable and configure up to 8 address windows each.\n\nAn instruction fetch to a non-ICCM region must fall within the address range of at least one instruction access window for the access to be forwarded to the IFU bus interface.\nIf at least one instruction access window is enabled, nonspeculative fetch requests which are not within the address range of any enabled instruction access window cause a precise instruction access fault exception.\nIf none of the 8 instruction access windows is enabled, the memory protection mechanism for instruction accesses is turned off.\nFor the ICCM region, accesses within the ICCM's address range are allowed.\nHowever, any access not within the ICCM's address range results in a precise instruction access fault exception.\n\nSimilarly, a load/store access to a non-DCCM or non-PIC memory-mapped control register region must fall within the address range of at least one data access window for the access to be forwarded to the LSU bus interface.\nIf at least one data access window is enabled, non-speculative load/store requests which are not within the address range of any enabled data access window cause a precise load/store address misaligned or access fault exception.\nIf none of the 8 data access windows is enabled, the memory protection mechanism for data accesses is turned off.\nFor the DCCM and PIC memory-mapped control register region(s), accesses within the DCCM's or the PIC memory-mapped control register's address range are allowed.\nHowever, any access not within the DCCM's or PIC memory-mapped control register's address range results in a precise load/store address misaligned or access fault exception.\n\nThe configuration parameters for each of the 8 instruction and 8 data access windows are:\n\n* Enable/disable instruction/data access window 0..7,\n* a base address of the window (which must be 64B-aligned), and\n* a mask specifying the size of the window (which must be an integer-multiple of 64 bytes minus 1).\n\nSee [](build-args.md#memory-protection-build-arguments) for more information.\n\n## Exception Handling\n\nCapturing the faulting effective address causing an exception helps assist firmware in handling the exception and/or provides additional information for firmware debugging.\nFor precise exceptions, the faulting effective address is captured in the standard RISC-V `mtval` register (see Section 3.1.17 in [[2]](intro.md#ref-2)).\nFor imprecise exceptions, the address of the first occurrence of the error is captured in a platform-specific error address capture register (see [](memory-map.md#d-bus-first-error-address-capture-register-mdseac)).\n\n### Imprecise Bus Error Non-Maskable Interrupt\n\nStore bus errors are fatal and cause a non-maskable interrupt (NMI).\nThe store bus error NMI has an `mcause` value of 0xF000_0000.\n\nLikewise, non-blocking load bus errors are fatal and cause a non-maskable interrupt (NMI).\nThe non-blocking load bus error NMI has an `mcause` value of 0xF000_0001.\n\n:::{note}\nThe address of the first store or non-blocking load error on the D-bus is captured in the `mdseac` register (see [](memory-map.md#d-bus-first-error-address-capture-register-mdseac)).\nThe register is unlocked either by resetting the core after the NMI has been handled or by a write to the `mdeau` register (see [](memory-map.md#d-bus-error-address-unlock-register-mdeau)).\nWhile the `mdseac` register is locked, subsequent D-bus errors are gated (i.e., they do not cause another NMI), but NMI requests originating external to the core are still honored.\n:::\n\n:::{note}\nThe AXI4 bus is able to report a load bus error and a store bus error simultaneously.\nIf store and non-blocking load bus errors are reported in the same clock cycle, the store bus error has higher priority.\n:::\n\n### Correctable Error Local Interrupt\n\nI-cache parity/ECC errors, ICCM correctable ECC errors, and DCCM correctable ECC errors are counted in separate correctable error counters (see sections [I-Cache Error Counter/Threshold Register (micect)](error-protection.md#i-cache-error-counter-threshold-register-micect), [Iccm Correctable Error Counter/Threshold Register (miccmect)](error-protection.md#iccm-correctable-error-counter-threshold-register-miccmect), and [Dccm Correctable Error Counter/Threshold Register (mdccmect)](error-protection.md#dccm-correctable-error-counter-threshold-register-mdccmect), respectively).\nEach counter also has its separate programmable error threshold.\nIf any of these counters has reached its threshold, a correctable error local interrupt is signaled.\nFirmware should determine which of the counters has reached the threshold and reset that counter.\n\nA local-to-the-core interrupt for correctable errors has pending (*mceip*) and enable (*mceie*) bits in bit position 30 of the standard RISC-V `mip` (see {numref}`tab-machine-interrupt-pending-register`) and `mie` (see {numref}`tab-machine-interrupt-enable-register`) registers, respectively.\nThe priority is lower than the RISC-V External interrupt, but higher than the RISC-V Software and Timer interrupts, (see {numref}`tab-veer-el2-platform-specific-and-std-risc-v-interrupt-priorities`).\nThe correctable error local interrupt has an `mcause` value of 0x8000_001E (see {numref}`tab-machine-cause-register`).\n\n### Rules for Core-Local Memory Accesses\n\nThe rules for instruction fetch and load/store accesses to core-local memories are:\n\n1. An instruction fetch access to a region\n 1. containing one or more ICCM sub-region(s)causes an exception if\n 1. the access is not completely within the ICCM sub-region, or\n 1. the boundary of an ICCM to a non-ICCM sub-region and vice versa is crossed, even if the region contains a DCCM/PIC memory-mapped control register sub-region.\n 1. not containing an ICCM sub-region goes out to the system bus, even if the region contains a DCCM/PIC memory-mapped control register sub-region.\n\n1. A load/store access to a region\n 1. containing one or more DCCM/PIC memory-mapped control register sub-region(s) causes an exception if\n 1. the access is not completely within the DCCM/PIC memory-mapped control register subregion, or\n 1. the boundary of\n 1. a DCCM to a non-DCCM sub-region and vice versa, or\n 1. a PIC memory-mapped control register sub-region is crossed, even if the region contains an ICCM sub-region.\n 1. not containing a DCCM/PIC memory-mapped control register sub-region goes out to the system bus, even if the region contains an ICCM sub-region.\n\n### Core-Local / D-Bus Access Prediction\n\nIn VeeR EL2, a prediction is made early in the pipeline if the access is to a core-local address (i.e., DCCM or PIC memory-mapped register) or to the D-bus (i.e., a memory or register address of the SoC).\nThe prediction is based on the base address (i.e., value of register *rs1*) of the load/store instruction.\nLater in the pipeline, the actual address is calculated also taking the offset into account (i.e., value of register *rs1 + offset*).\nA mismatch of the predicted and the actual destination (i.e., a core-local or a D-bus access) results in a load/store access fault exception.\n\n### Unmapped Addresses\n\n:::{list-table} Handling of Unmapped Addresses\n:name: tab-handling-unmapped-addresses\n:header-rows: 1\n\n* - **Access**\n - **Core/Bus**\n - **Side Effect**\n - **Action**\n - **Comments**\n* - Fetch\n - Core\n - N/A\n - Instruction access fault exception [^fn-unmapped-address-1], [^fn-unmapped-address-2]\n - Precise exception (e.g., address out-of-range)\n* - Fetch\n - Bus\n - N/A\n - Instruction access fault exception [^fn-unmapped-address-1]\n - Precise exception (e.g., address out-of-range)\n* - Load\n - Core\n - No\n - Load access fault exception [^fn-unmapped-address-3], [^fn-unmapped-address-4]\n - Precise exception (e.g., address out-of-range)\n* - Load\n - Bus\n - No\n - non-blocking load bus error nmi (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n -\n - imprecise, fatal\n - capture load address in core bus interface\n* - Load\n - Bus\n - Yes\n - non-blocking load bus error nmi (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n -\n - imprecise, fatal\n - capture load address in core bus interface\n* - Store\n - Core\n - No\n - Store/AMO [^fn-unmapped-address-5] access fault exception [^fn-unmapped-address-3], [^fn-unmapped-address-4]\n - Precise exception\n* - Store\n - Bus\n - No\n - Store bus error NMI (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n -\n - Imprecise, fatal\n - Capture store address in core bus interface\n* - Store\n - Bus\n - Yes\n - Store bus error NMI (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n -\n - Imprecise, fatal\n - Capture store address in core bus interface\n* - DMA Read / DMA Write\n - Bus\n - N/A\n - DMA slave bus error\n - Send error response to master\n:::\n\n:::{note}\n It is recommended to provide address gaps between different memories to ensure unmapped address\n:::\n\n[^fn-unmapped-address-1]: If any byte of an instruction is from an unmapped address, an instruction access fault precise exception is flagged.\n[^fn-unmapped-address-2]: Exception also flagged for fetches to the DCCM address range if located in the same region, or if located in different regions and no SoC address is a match.\n[^fn-unmapped-address-3]: Exception also flagged for PIC load/store not word-sized or address not word-aligned.\n[^fn-unmapped-address-4]: Exception also flagged for loads/stores to the ICCM address range if located in the same region, or if located in different regions and no SoC address is a match.\n[^fn-unmapped-address-5]: AMO refers to the RISC-V \"A\" (atomics) extension, which is not implemented in VeeR EL2.\n\n### Misaligned Accesses\n\nGeneral notes:\n* The core performs a misalignment check during the address calculation.\n* Accesses across region boundaries always cause a misaligned exception.\n* Splitting a load/store from/to an address with no side effects (i.e., idempotent) is not of concern for VeeR EL2.\n\n:::{list-table} Handling of Misaligned Accesses\n:name: tab-handling-misaligned-addresses\n:header-rows: 1\n\n* - **Access**\n - **Core/Bus**\n - **Side Effect**\n - **Region Cross**\n - **Action**\n - **Comments**\n* - Fetch\n - Core\n - N/A\n - No\n - N/A\n - Not possible [^fn-misaligned-accesses-1]\n* - Fetch\n - Bus\n - N/A\n - No\n - N/A\n - Not possible [^fn-misaligned-accesses-1]\n* - Load\n - Core\n - No\n - No\n - Load split into multiple DCCM read accesses\n - Split performed by core\n* - Load\n - Bus\n - No\n - No\n - Load split into multiple bus transactions\n - Split performed by core\n* - Load\n - Bus\n - Yes [^fn-misaligned-accesses-2]\n - No\n - Load address misaligned exception\n - Precise exception\n* - Store\n - Core\n - No\n - No\n - Store split into multiple DCCM write accesses\n - Split performed by core\n* - Store\n - Bus\n - No\n - No\n - Store split into multiple bus transactions\n - Split performed by core\n* - Store\n - Bus\n - Yes [^fn-misaligned-accesses-2]\n - No\n - Store/AMO address misaligned exception\n - Precise exception\n* - Fetch\n - N/A\n - N/A\n - Yes\n - N/A\n - Not possible [^fn-misaligned-accesses-1]\n* - Load\n - N/A\n - N/A\n - Yes\n - Load address misaligned exception\n - Precise exception\n* - Store\n - N/A\n - N/A\n - Yes\n - Store/AMO address misaligned exception\n - Precise exception\n* - DMA Read\n - Bus\n - N/A\n - N/A\n - DMA slave bus error\n - Send error response to master\n* - DMA Write [^fn-misaligned-accesses-3]\n - Bus\n - N/A\n - N/A\n - DMA slave bus error\n - Send error response to master\n:::\n\n[^fn-misaligned-accesses-1]: Accesses to the I-cache or ICCM initiated by fetches never cross 16B boundaries. I-cache fills are always aligned to 64B. Misaligned accesses are therefore not possible.\n[^fn-misaligned-accesses-2]: The RISC-V Privileged specification recommends that misaligned accesses to regions with potential side-effects should trigger an access fault exception, instead of a misaligned exception (see Section 3.5.6 in [[2]](intro.md#ref-2)). Note that VeeR EL2 triggers a misaligned exception in this case. To avoid potential side-effects, the exception handler should not emulate a misaligned access using multiple smaller aligned accesses.\n[^fn-misaligned-accesses-3]: This case is in violation with the write alignment rules specified in section [](memory-map.md#write-alignment-rules).\n\n### Uncorrectable Ecc Errors\n\n:::{list-table} Handling of Uncorrectable ECC Errors\n:name: tab-handling-uncorrectable-ecc-errors\n:header-rows: 1\n\n* - **Access**\n - **Core/Bus**\n - **Side Effect**\n - **Action**\n - **Comments**\n* - Fetch\n - Core\n - N/A\n - Instruction access fault exception\n - Precise exception (i.e., for oldest instruction in pipeline only)\n* - Fetch\n - Bus\n - N/A\n - Instruction access fault exception\n - Precise exception (i.e., for oldest instruction in pipeline only)\n* - Load\n - Core\n - No\n - Load access fault exception\n - Precise exception (i.e., for non-speculative load only)\n* - Load\n - Core\n - Yes\n - Load access fault exception\n - Precise exception (i.e., for non-speculative load only)\n* - Load\n - Bus\n - No\n - Non-blocking load bus error NMI (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n -\n - Imprecise, fatal\n - Capture load address in core bus interface\n* - Load\n - Bus\n - Yes\n - Non-blocking load bus error NMI (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n -\n - Imprecise, fatal\n - Capture load address in core bus interface\n* - Store\n - Core\n - No\n - Store/AMO access fault exception\n - Precise exception (i.e., for non-speculative store only)\n* - Store\n - Core\n - Yes\n - Store/AMO access fault exception\n - Precise exception (i.e., for non-speculative store only)\n* - Store\n - Bus\n - No\n - Store bus error NMI (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n -\n - Imprecise, fatal\n - Capture store address in core bus interface\n* - Store\n - Bus\n - Yes\n - Store bus error NMI (see [](memory-map.md#imprecise-bus-error-non-maskable-interrupt))\n -\n - Imprecise, fatal\n - Capture store address in core bus interface\n* - DMA Read\n - Bus\n - N/A\n - DMA slave bus error\n - Send error response to master\n:::\n\n:::{note}\nDMA write accesses to the ICCM or DCCM always overwrite entire 32-bit words and their corresponding ECC bits.\nTherefore, ECC bits are never checked and errors not detected on DMA writes.\n:::\n\n### Correctable Ecc/Parity Errors\n\n:::{list-table} Handling of Correctable ECC/Parity Errors Access Core/Bus Side Effect Action\n:name: tab-handling-correctable-ecc-errors\n:header-rows: 1\n\n* - **Access**\n - **Core/Bus**\n - **Side Effect**\n - **Action**\n - **Comments**\n* - Fetch\n - Core\n - N/A\n - For I-cache accesses:\n - Increment correctable I-cache error counter in core\n - If I-cache error threshold reached, signal correctable error local interrupt (see [I-Cache Error Counter/Threshold Register (micect)](error-protection.md#i-cache-error-counter-threshold-register-micect))\n - Invalidate all cache lines of set\n - Perform RFPC flush\n - Flush core pipeline\n - Refetch cache line from SoC memory\n -\n - For all fetches from I-cache (i.e., out of pipeline, independent of actual instruction execution)\n - For I-cache with tag/instruction ECC protection, single- and double-bit errors are recoverable\n* - Fetch\n - Core\n - N/A\n - For ICCM accesses:\n - Increment correctable ICCM error counter in core\n - If ICCM error threshold reached, signal correctable error local interrupt (see [Iccm Correctable Error Counter/Threshold Register (miccmect)](error-protection.md#iccm-correctable-error-counter-threshold-register-miccmect))\n - Perform RFPC flush\n - Flush core pipeline\n - Write corrected data back to ICCM\n - Refetch instruction(s) from ICCM\n -\n - For all fetches from ICCM (i.e., out of pipeline, independent of actual instruction execution)\n - ICCM errors trigger an RFPC (ReFetch PC) flush since in-line correction would require an additional cycle\n* - Fetch\n - Bus\n - N/A\n -\n - Increment correctable error counter in SoC\n - If error threshold reached, signal external interrupt\n - Write corrected data back to SoC memory\n - Errors in SoC memories are corrected at memory boundary and autonomously written back to memory array\n* - Load\n - Core\n - No\n -\n - Increment correctable DCCM error counter in core\n - If DCCM error threshold reached, signal correctable error local interrupt (see [Dccm Correctable Error Counter/Threshold Register (mdccmect)](error-protection.md#dccm-correctable-error-counter-threshold-register-mdccmect))\n - Write corrected data back to DCCM\n -\n - For non-speculative accesses only\n - DCCM errors are in-line corrected and written back to DCCM\n* - Load\n - Core\n - Yes\n -\n - Increment correctable DCCM error counter in core\n - If DCCM error threshold reached, signal correctable error local interrupt (see [Dccm Correctable Error Counter/Threshold Register (mdccmect)](error-protection.md#dccm-correctable-error-counter-threshold-register-mdccmect))\n - Write corrected data back to DCCM\n -\n - For non-speculative accesses only\n - DCCM errors are in-line corrected and written back to DCCM\n* - Load\n - Bus\n - No\n -\n - Increment correctable error counter in SoC\n - If error threshold reached, signal external interrupt\n - Write corrected data back to SoC memory\n - Errors in SoC memories are corrected at memory boundary and autonomously written back to memory array\n* - Load\n - Bus\n - Yes\n -\n - Increment correctable error counter in SoC\n - If error threshold reached, signal external interrupt\n - Write corrected data back to SoC memory\n - Errors in SoC memories are corrected at memory boundary and autonomously written back to memory array\n* - Store\n - Core\n - No\n -\n - Increment correctable dccm error counter in core\n - If dccm error threshold reached, signal correctable error local interrupt (see [Dccm Correctable Error Counter/Threshold Register (mdccmect)](error-protection.md#dccm-correctable-error-counter-threshold-register-mdccmect))\n - Write corrected data back to dccm\n -\n - For non-speculative accesses only\n - Dccm errors are in-line corrected and written back to dccm\n* - Store\n - Core\n - Yes\n -\n - Increment correctable dccm error counter in core\n - If dccm error threshold reached, signal correctable error local interrupt (see [Dccm Correctable Error Counter/Threshold Register (mdccmect)](error-protection.md#dccm-correctable-error-counter-threshold-register-mdccmect))\n - Write corrected data back to dccm\n -\n - For non-speculative accesses only\n - Dccm errors are in-line corrected and written back to dccm\n* - Store\n - Bus\n - No\n -\n - Increment correctable error counter in SoC\n - If error threshold reached, signal external interrupt\n - Write corrected data back to SoC memory\n - Errors in SoC memories are corrected at memory boundary and autonomously written back to memory array\n* - Store\n - Bus\n - Yes\n -\n - Increment correctable error counter in SoC\n - If error threshold reached, signal external interrupt\n - Write corrected data back to SoC memory\n - Errors in SoC memories are corrected at memory boundary and autonomously written back to memory array\n* - DMA Read\n - Bus\n - N/A\n - For ICCM accesses:\n - Increment correctable ICCM error counter in core\n - If ICCM error threshold reached, signal correctable error local interrupt (see [Iccm Correctable Error Counter/Threshold Register (miccmect)](error-protection.md#iccm-correctable-error-counter-threshold-register-miccmect))\n - Write corrected data back to ICCM\n - DMA read access errors to ICCM are in-line corrected and written back to ICCM\n* - DMA Read\n - Bus\n - N/A\n - For DCCM accesses:\n - Increment correctable DCCM error counter in core\n - If DCCM error threshold reached, signal correctable error local interrupt (see [Dccm Correctable Error Counter/Threshold Register (mdccmect)](error-protection.md#dccm-correctable-error-counter-threshold-register-mdccmect))\n - Write corrected data back to DCCM\n - DMA read access errors to DCCM are in-line corrected and written back to DCCM\n:::\n\n:::{note}\nCounted errors could be from different, unknown memory locations.\n:::\n\n:::{note}\nDMA write accesses to the ICCM or DCCM always overwrite entire 32-bit words and their corresponding ECC bits.\nTherefore, ECC bits are never checked and errors not detected on DMA writes.\n:::\n\n## Control/Status Registers\n\nA summary of platform-specific control/status registers in CSR space:\n\n* [](memory-map.md#region-access-control-register-mrac)\n* [](memory-map.md#memory-synchronization-trigger-register-dmst)\n* [](memory-map.md#d-bus-first-error-address-capture-register-mdseac)\n* [](memory-map.md#d-bus-error-address-unlock-register-mdeau)\n* [](memory-map.md#machine-secondary-cause-register-mscause)\n\nAll reserved and unused bits in these control/status registers must be hardwired to '0'. Unless otherwise noted, all read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.\n\n### Region Access Control Register (mrac)\n\nA single region access control register is sufficient to provide independent control for 16 address regions.\n\n:::{note}\nTo guarantee that updates to the `mrac` register are in effect, if a region being updated is in the load/store space, a `fence` instruction is required.\nLikewise, if a region being updated is in the instruction space, a `fence.i` instruction (which flushes the I-cache) is required.\n:::\n\n:::{note}\nThe *sideeffect* access control bits are ignored by the core for load/store accesses to addresses mapped to core-local memories (i.e., DCCM and ICCM) and PIC memory-mapped control registers as well as for all instruction fetch accesses.\nThe *cacheable* access control bits are ignored for instruction fetch accesses from addresses mapped to the ICCM, but not for any other addresses.\n:::\n\n:::{note}\nThe combination '11' (i.e., side effect and cacheable) is illegal. Writing '11' is mapped by hardware to the legal value '10' (i.e., side effect and non-cacheable).\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Region Access Control Register (mrac, at CSR 0x7C0)\n:name: tab-region-access-control-register\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Y = 0..15 (= Region)\n -\n -\n -\n -\n* - sideeffectY\n - Y*2+1\n - Side effect indication for region Y:\n - 0: No side effects (idempotent)\n - 1: Side effects possible (non-idempotent)\n - R/W\n - 0\n* - cacheableY\n - Y*2\n - Caching control for region Y:\n - 0: Caching not allowed\n - 1: Caching allowed\n - R/W\n - 0\n:::\n\n### Memory Synchronization Trigger Register (dmst)\n\nThe `dmst` register provides triggers to force the synchronization of memory accesses. Specifically, it allows a debugger to initiate operations that are equivalent to the `fence.i` (see [](memory-map.md#instructions)) and `fence` (see [](memory-map.md#data)) instructions.\n\n:::{note}\n This register is accessible in **Debug Mode only**. Attempting to access this register in machine mode raises an illegal instruction exception.\n:::\n\nThe *fence_i* and *fence* fields of the `dmst` register have W1R0 (Write 1, Read 0) behavior, as also indicated in the\n'Access' column.\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Memory Synchronization Trigger Register (dmst, at CSR 0x7C4)\n:name: tab-memory-synchronization-trigger-register\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:2\n - Reserved\n - R\n - 0\n* - fence\n - 1\n - Trigger operation equivalent to `fence` instruction\n - R0/W1\n - 0\n* - fence_i\n - 0\n - Trigger operation equivalent to `fence.i` instruction\n - R0/W1\n - 0\n:::\n\n### D-Bus First Error Address Capture Register (mdseac)\n\nThe address of the first occurrence of a store or non-blocking load error on the D-bus is captured in the `mdseac` register. Latching the address also locks the register. \nWhile the `mdseac` register is locked, subsequent D-bus errors are gated (i.e., they do not cause another NMI), but NMI requests originating external to the core are still honored.\n\nThe `mdseac` register is unlocked by either a core reset (which is the safer option) or by writing to the `mdeau` register (see [](memory-map.md#d-bus-error-address-unlock-register-mdeau)).\n\n:::{note}\nThe address captured in this register is the target (i.e., base) address of the store or non-blocking load which experienced an error.\n:::\n\n:::{note}\nThe NMI handler may use the value stored in the `mcause` register to differentiate between a D-bus store error, a D-bus non-blocking load error, and a core-external event triggering an NMI.\n:::\n\n:::{note}\nCapturing an address of a store or non-blocking load D-bus error in the `mdseac` register is independent of the actual taking of an NMI due to the bus error.\nFor example, if a request on the NMI pin arrives just prior to the detection of a store or non-blocking load error on the D-bus, the address of the bus error may still be logged in the `mdseac` register.\n:::\n\nThis register is mapped to the non-standard read-only CSR address space.\n\n:::{list-table} D-Bus First Error Address Capture Register (mdseac, at CSR 0xFC0)\n:name: tab-d-bus-first-error-address-capture-register\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - erraddr\n - 31:0\n - Address of first occurrence of D-bus store or non-blocking load error\n - R\n - 0\n:::\n\n### D-Bus Error Address Unlock Register (mdeau)\n\nWriting to the `mdeau` register unlocks the `mdseac` register (see [](memory-map.md#d-bus-first-error-address-capture-register-mdseac)) after a D-bus error address has been captured.\nThis write access also reenables the signaling of an NMI for a subsequent D-bus error.\n\n:::{note}\nNested NMIs might destroy core state and, therefore, receiving an NMI should still be considered fatal.\nIssuing a core reset is a safer option to deal with a D-bus error.\n:::\n\nThe `mdeau` register has WAR0 (Write Any value, Read 0) behavior.\nWriting '0' is recommended.\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} D-Bus Error Address Unlock Register (mdeau, at CSR 0xBC0)\n:name: tab-d-bus-error-address-unlock-register\n:header-rows: 1\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - erraddr\n - 31:0\n - Address of first occurrence of D-bus store or non-blocking load error\n - R\n - 0\n:::\n\n### Machine Secondary Cause Register (mscause)\n\nThe `mscause` register, in conjunction with the standard RISC-V `mcause` register (see [](adaptations.md#machine-cause-register-mcause)), allows the determination of the exact cause of a trap for cases where multiple, different conditions share a single trap code.\nThe standard RISC-V mcause register provides the trap code and the `mscause` register provides supporting information about the trap to disambiguate different sources.\nA value of '0' indicates that there is no additional information available.\n{numref}`tab-machine-secondary-cause-register` lists VeeR EL2's standard exceptions/interrupts (regular text), platform-specific local interrupts (italic text), and NMI causes (bold text).\n\nThe `mscause` register has WLRL (Write Legal value, Read Legal value) behavior.\n\n:::{note}\nVeeR EL2 implements only the 4 least-significant bits of the mscause register (i.e., `mscause[3:0]`).\nWrites to all higher bits are ignored, reads return 0 for those bits.\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Machine Secondary Cause Register (mscause, at CSR 0x7FF)\n:name: tab-machine-secondary-cause-register\n:header-rows: 1\n\n* - **mcause**\n - **mcause Description**\n - **mscause (Rel. Priority)** [^fn-mscause-register-1]\n - **mscause Description**\n - **Section(s)**\n* - **Exceptions**\n -\n -\n -\n -\n* - 0x1\n - Instruction access fault\n - 0x9 (2)\n - I-side fetch precise bus error\n - [](memory-map.md#unmapped-addresses) and [](error-protection.md#error-detection-and-handling)\n* - 0x1\n - Instruction access fault\n - 0x1 (3)\n - I-side ICCM double-bit ECC error\n - [](memory-map.md#uncorrectable-ecc-errors) and [](error-protection.md#error-detection-and-handling)\n* - 0x1\n - Instruction access fault\n - 0x2 (0)\n - I-side core-local [^fn-mscause-register-2] unmapped address error\n - [](memory-map.md#unmapped-addresses) and [](error-protection.md#error-detection-and-handling)\n* - 0x1\n - Instruction access fault\n - 0x3 (1)\n - I-side access out of MPU range\n - [](memory-map.md#memory-protection)\n* - 0x2\n - Illegal instruction\n - 0x0\n - None\n - N/A\n* - 0x3\n - Breakpoint\n - 0x2\n - ebreak (not to Debug Mode)\n - N/A\n* - 0x3\n - Breakpoint\n - 0x1\n - Trigger hit [^fn-mscause-register-3] (not to Debug Mode)\n - N/A\n* - 0x4\n - Load address misaligned\n - 0x2 (0)\n - D-side load across region boundary\n - [](memory-map.md#misaligned-accesses)\n* - 0x4\n - Load address misaligned\n - 0x1 (1)\n - D-side size-misaligned load to non-idempotent address\n - [](memory-map.md#misaligned-accesses)\n* - 0x5\n - Load access fault\n - 0x2 (0)\n - D-side core-local [^fn-mscause-register-4], [^fn-mscause-register-5] load unmapped address error\n - [](memory-map.md#unmapped-addresses) and [](error-protection.md#error-detection-and-handling)\n* - 0x5\n - Load access fault\n - 0x1 (4)\n - D-side DCCM load double-bit ECC error\n - [](memory-map.md#uncorrectable-ecc-errors) and [](error-protection.md#error-detection-and-handling)\n* - 0x5\n - Load access fault\n - 0x3 (1)\n - D-side load access out of MPU range\n - [](memory-map.md#memory-protection)\n* - 0x5\n - Load access fault\n - 0x5 (2)\n - D-side load region prediction error\n - [Core-Local / D-Bus Access Prediction](memory-map.md#core-local-d-bus-access-prediction)\n* - 0x5\n - Load access fault\n - 0x6 (3)\n - D-side PIC [^fn-mscause-register-6] load access error\n - [](memory-map.md#unmapped-addresses)\n* - 0x6\n - Store/AMO address misaligned\n - 0x2 (0)\n - D-side store across region boundary\n - [](memory-map.md#misaligned-accesses)\n* - 0x6\n - Store/AMO address misaligned\n - 0x1 (1)\n - D-side size-misaligned store to non-idempotent address\n - [](memory-map.md#misaligned-accesses)\n* - 0x7\n - Store/AMO access fault\n - 0x2 (0)\n - D-side core-local [^fn-mscause-register-4], [^fn-mscause-register-5] store unmapped address error\n - [](memory-map.md#unmapped-addresses) and [](error-protection.md#error-detection-and-handling)\n* - 0x7\n - Store/AMO access fault\n - 0x1 (4)\n - D-side DCCM store double- bit ECC error\n - [](memory-map.md#uncorrectable-ecc-errors) and [](error-protection.md#error-detection-and-handling)\n* - 0x7\n - Store/AMO access fault\n - 0x3 (1)\n - D-side store access out of MPU range\n - [](memory-map.md#memory-protection)\n* - 0x7\n - Store/AMO access fault\n - 0x5 (2)\n - D-side store region prediction error\n - [Core-Local / D-Bus Access Prediction](memory-map.md#core-local-d-bus-access-prediction)\n* - 0x7\n - Store/AMO access fault\n - 0x6 (3)\n - D-side PIC [^fn-mscause-register-6] store access error\n - [](memory-map.md#unmapped-addresses)\n* - 0xB\n - Environment call from M- mode\n - 0x0\n - None\n - N/A\n* - **Interrupts**\n -\n -\n -\n -\n* - 0x8000_0003\n - Machine software interrupt\n - 0x0\n - Machine software\n - [](memory-map.md#software-interrupts)\n* - 0x8000_0007\n - Machine timer [^fn-mscause-register-7] interrupt\n - 0x0\n - Machine timer\n - N/A\n* - 0x8000_000B\n - Machine external interrupt\n - 0x0\n - External interrupt\n - [](interrupts.md)\n* - *0x8000_001C*\n - *Machine internal timer 1 local interrupt*\n - 0x0\n - *Internal timer 1 local interrupt*\n - [](timers.md#internal-timer-local-interrupts)\n* - *0x8000_001D*\n - *Machine internal timer 0 local interrupt*\n - 0x0\n - *Internal timer 0 local interrupt*\n - [](timers.md#internal-timer-local-interrupts)\n* - *0x8000_001E*\n - *Machine correctable error local interrupt*\n - 0x0\n - *Correctable error local interrupt*\n - [](memory-map.md#correctable-error-local-interrupt)\n* - **0x0000_0000**\n - **NMI**\n - **0x0**\n - **NMI pin assertion**\n - [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* - **0xF000_0000**\n - **NMI**\n - **0x0**\n - **D-bus store error**\n - [](memory-map.md#imprecise-bus-error-non-maskable-interrupt) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* - **0xF000_0001**\n - **NMI**\n - **0x0**\n - **D-bus non-blocking load error**\n - [](memory-map.md#imprecise-bus-error-non-maskable-interrupt) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* - **0xF000_1000**\n - **NMI**\n - **0x0**\n - **Fast Interrupt double-bit ECC error**\n - [](interrupts.md#fast-interrupt-redirect) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* - **0xF000_1001**\n - **NMI**\n - **0x0**\n - **Fast Interrupt DCCM region access error**\n - [](interrupts.md#fast-interrupt-redirect) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n* - **0xF000_1002**\n - **NMI**\n - **0x0**\n - **Fast Interrupt non-DCCM region**\n - [](interrupts.md#fast-interrupt-redirect) and [](memory-map.md#non-maskable-interrupt-nmi-signal-and-vector)\n:::\n\n:::{note}\n All other values are reserved.\n:::\n\n[^fn-mscause-register-1]: Relative priority of load/store exceptions (0: highest priority).\n[^fn-mscause-register-2]: Fetch access not within ICCM address range.\n[^fn-mscause-register-3]: Trigger hit can also be observed in *hit* bit of mcontrol register (see {numref}`tab-mcontrol`).\n[^fn-mscause-register-4]: Load/store access not within DCCM or PIC memory-mapped register address ranges.\n[^fn-mscause-register-5]: If a load or store access crosses the upper boundary of either the DCCM or PIC memory-mapped register address range, the error address reported in the mtval register is the base address of the access, not the address of the first byte outside the DCCM or PIC range. Note that firmware cannot recover from this access fault independent of which address is reported.\n[^fn-mscause-register-6]: PIC load/store not word-sized or address not word-aligned.\n[^fn-mscause-register-7]: Core external timer\n\n## Memory Address Map\n\n{numref}`tab-veer-el2-memory-address-map` summarizes an example of the VeeR EL2 memory address map, including regions as well as start and end addresses for the various memory types.\n\n:::{list-table} VeeR EL2 Memory Address Map (Example)\n:name: tab-veer-el2-memory-address-map\n:header-rows: 1\n\n* - **Region**\n - **Start Address**\n - **End Address**\n - **Memory Type**\n* - 0x0\n - 0x0000_0000\n - 0x0003_FFFF\n - Reserved\n* - 0x0\n - 0x0004_0000\n - 0x0005_FFFF\n - ICCM (region: 0, offset: 0x4000, size: 128KB)\n* - 0x0\n - 0x0006_0000\n - 0x0007_FFFF\n - Reserved\n* - 0x0\n - 0x0008_0000\n - 0x0009_FFFF\n - DCCM (region: 0, offset: 0x8000, size: 128KB)\n* - 0x0\n - 0x000A_0000\n - 0x0FFF_FFFF\n - Reserved\n* - 0x1\n - 0x1000_0000\n - 0x1FFF_FFFF\n - System memory-mapped CSRs\n* - 0x2\n - 0x2000_0000\n - 0x2FFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0x3\n - 0x3000_0000\n - 0x3FFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0x4\n - 0x4000_0000\n - 0x4FFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0x5\n - 0x5000_0000\n - 0x5FFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0x6\n - 0x6000_0000\n - 0x6FFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0x7\n - 0x7000_0000\n - 0x7FFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0x8\n - 0x8000_0000\n - 0x8FFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0x9\n - 0x9000_0000\n - 0x9FFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0xA\n - 0xA000_0000\n - 0xAFFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0xB\n - 0xB000_0000\n - 0xBFFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0xC\n - 0xC000_0000\n - 0xCFFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0xD\n - 0xD000_0000\n - 0xDFFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0xE\n - 0xE000_0000\n - 0xEFFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n* - 0xF\n - 0xF000_0000\n - 0xFFFF_FFFF\n - System SRAMs, system ROMs, and system memory-mapped I/O device interfaces\n:::\n\n## Behavior of Loads to Side-Effect Addresses\n\nLoads with potential side-effects do not stall the pipeline and may be committed before the data is returned from the system bus.\nOther loads and stores in the pipeline continue to be executed unless an instruction uses data from a pending side-effect load.\nStalling the instruction control flow until a side-effect load has completed may be accomplished by either issuing a fence instruction or by generating a dependency on the load's data.\n\n## Partial Writes\n\nRules for partial writes handling are:\n\n* **Core-local addresses:** The core performs a read-modify-write operation and updates ECC to core-local memories (i.e., I- and DCCMs).\n* **SoC addresses:** The core indicates the valid bytes for each bus write transaction.\n The addressed SoC memory or device performs a read-modify-write operation and updates its ECC.\n\n## Expected SoC Behavior for Accesses\n\nThe VeeR EL2 core expects that the SoC responds to all system bus access requests it receives from the core.\nSystem bus accesses include instruction fetches, load/store data accesses as well as debug system bus accesses.\nA response may either be returning the requested data (e.g., instructions sent back to the core for fetches or data for loads), an acknowledgement indicating the successful completion of a bus transaction (e.g., acknowledging a store), an error response (e.g., an error indication in response to an attempt to access an unmapped address).\nIf the SoC does not respond to every single bus transaction, the core may hang.\n\n## Speculative Bus Accesses\n\nDeep core pipelines require a certain degree of speculation to maximize performance.\nThe sections below describe instruction and data speculation in the VeeR EL2 core.\nNote that speculative accesses to memory addresses with side effects may be entirely avoided by adding the buildargument-selected and -configured memory protection mechanism described in [](memory-map.md#memory-protection).\n\n### Instructions\n\nInstruction cache misses on VeeR EL2 are speculative in nature.\nThe core may issue speculatively fetch accesses on the IFU bus interface for an instruction cache miss in the following cases:\n\n* due to an earlier exception or interrupt,\n* due to an earlier branch mispredict,\n* due to an incorrect branch prediction, and\n* due to an incorrect Return Address Stack (RAS) prediction.\n\nIssuing speculative accesses on the IFU bus interface is benign as long as the platform is able to handle accesses to unimplemented memory and to prevent accesses to SoC components with read side effects by returning random data and/or a bus error condition.\nThe decision of which addresses are unimplemented and which addresses with potential side effects need to be protected is left to the platform.\n\nInstruction fetch speculation can be limited, though not entirely avoided, by turning off the core's branch predictor including the return address stack.\nWriting a '1' to the *bpd* bit in the `mfdc` register (see {numref}`tab-feature-disable-cr`) disables branch prediction including RAS.\n\n### Data\n\nThe VeeR EL2 core does not issue any speculative data accesses on the LSU bus interface.\n\n## DMA Slave Port\n\nThe Direct Memory Access (DMA) slave port is used for read/write accesses to core-local memories initiated by external masters.\nFor example, external masters could be DMA controllers or other CPU cores located in the SoC.\n\n### Access\n\nThe DMA slave port allows read/write access to the core's ICCM and DCCM.\nHowever, the PIC memory-mapped control registers are not accessible via the DMA port.\n\n### Write Alignment Rules\n\nFor writes to the ICCM and DCCM through the DMA slave port, accesses must be 32- or 64-bit aligned, and 32 bits (word) or 64 bits (double-word), respectively, wide to avoid read-modify-write operations for ECC generation.\n\nMore specifically, DMA write accesses to the ICCM or DCCM must have a 32- or 64-bit access size and be aligned to their respective size.\nThe only write byte enable values allowed for AXI4 are 0x0F, 0xF0, and 0xFF.\n\n### Quality Of Service\n\nAccesses to the ICCM and DCCM by the core have higher priority if the DMA FIFO is not full.\nHowever, to avoid starvation, the DMA slave port's DMA controller may periodically request a stall to get access to the pipe if a DMA request is continuously blocked.\n\nThe *dqc* field in the `mfdc` register (see {numref}`tab-feature-disable-cr`) specifies the maximum number of clock cycles a DMA access request waits at the head of the DMA FIFO before requesting a bubble to access the pipe.\nFor example, if *dqc* is 0, a DMA access requests a bubble immediately (i.e., in the same cycle); if *dqc* is 7 (the default value), a waiting DMA access requests a bubble on the 8th cycle.\nFor a DMA access to the ICCM, it may take up to 3 additional cycles25 before the access is granted.\nSimilarly, for a DMA access to the DCCM, it may take up to 4 additional cycles before the access is granted.\n\n### Ordering Of Core and DMA Accesses\n\nAccesses to the DCCM or ICCM by the core and the DMA slave port are asynchronous events relative to one another.\nThere are no ordering guarantees between the core and the DMA slave port accessing the same or different addresses.\n\n## Reset Signal and Vector\n\nThe core provides a 31-bit wide input bus at its periphery for a reset vector.\nThe SoC must provide the reset vector on the `rst_vec[31:1]` bus, which could be hardwired or from a register.\nThe `rst_l` input signal is active-low, asynchronously asserted, and synchronously deasserted (see also [](clocks.md#reset)).\nWhen the core is reset, it fetches the first instruction to be executed from the address provided on the reset vector bus.\nNote that the applied reset vector must be pointing to the ICCM, if enabled, or a valid memory address, which is within an enabled instruction access window if the memory protection mechanism (see [](memory-map.md#memory-protection)) is used.\n\n:::{note}\nThe core's 31 general-purpose registers (`x1 - x31`) are cleared on reset.\n:::\n\n## Non-Maskable Interrupt (NMI) Signal and Vector\n\nThe core provides a 31-bit wide input bus at its periphery for a non-maskable interrupt (NMI) vector.\nThe SoC must provide the NMI vector on the `nmi_vec[31:1]` bus, either hardwired or sourced from a register.\n\n:::{note}\nNMI is entirely separate from the other interrupts and not affected by the selection of Direct vs Vectored mode.\n:::\n\nThe SoC may trigger an NMI by asserting the low-to-high edge-triggered, `asynchronous nmi_int` input signal.\nThis signal must be asserted for at least two full core clock cycles to guarantee it is detected by the core since shorter pulses might be dropped by the synchronizer circuit.\nFurthermore, the `nmi_int` signal must be deasserted for a minimum of two full core clock cycles and then reasserted to signal the next NMI request to the core.\nIf the SoC does not use the pin-asserted NMI feature, it must hardwire the `nmi_int` input signal to 0.\n\nIn addition to NMIs triggered by the SoC, a core-internal NMI request is signaled when a D-bus store or non-blocking load error has been detected.\n\nWhen the core receives either an SoC-triggered or a core-internal NMI request, it fetches the next instruction to be executed from the address provided on the NMI vector bus.\nThe reason for the NMI request is reported in the `mcause` register according to {numref}`tab-summary-nmi-mcause-values`.\n\n:::{list-table} Summary of NMI mcause Values\n:name: tab-summary-nmi-mcause-values\n:header-rows: 1\n\n* - **Value mcause[31:0]**\n - **Description**\n - **Section**\n* - 0x0000_0000\n - NMI pin assertion (`nmi_int` input signal)\n - see above\n* - 0xF000_0000\n - Machine D-bus store error NMI\n - [](memory-map.md#imprecise-bus-error-non-maskable-interrupt)\n* - 0xF000_0001\n - Machine D-bus non-blocking load error NMI\n - [](memory-map.md#imprecise-bus-error-non-maskable-interrupt)\n* - 0xF000_1000\n - Machine Fast Interrupt double-bit ECC error NMI\n - [](interrupts.md#fast-interrupt-redirect)\n* - 0xF000_1001\n - Machine Fast Interrupt DCCM region access error NMI\n - [](interrupts.md#fast-interrupt-redirect)\n* - 0xF000_1002\n - Machine Fast Interrupt non-DCCM region NMI\n - [](interrupts.md#fast-interrupt-redirect)\n:::\n\n:::{note}\n NMIs are typically fatal! Section 3.4 of the RISC-V Privileged specification [[2]](intro.md#ref-2) states that NMIs are only used for hardware error conditions and cause an immediate jump to the address at the NMI vector running in M-mode regardless of the state of a hart's interrupt enable bits. The NMI can thus overwrite state in an active M-mode interrupt handler and normal program execution cannot resume. Unlike resets, NMIs do not reset hart state, enabling diagnosis, reporting, and possible containment of the hardware error. Because NMIs are not maskable, the NMI handling routine performing diagnosis and reporting is itself susceptible to further NMIs, possibly making any such activity meaningless and erroneous in the face of error storms.\n:::\n\n## Software Interrupts\n\nThe VeeR EL2 core provides a software-interrupt input signal for its hart (see `soft_int` in {numref}`tab-core-complex-signals`).\nThe `soft_int` signal is an active-high, level-sensitive, asynchronous input signal which feeds the *msip* (machine software-interrupt pending) bit of the standard RISC-V `mip` register (see {numref}`tab-machine-interrupt-pending-register`).\nWhen the *msie* (machine software-interrupt enable) bit of the standard RISC-V `mie` register (see {numref}`tab-machine-interrupt-enable-register`) is set, a machine software interrupt occurs if the *msip* bit of the `mip` register is asserted.\n\nThe SoC must implement Machine Software Interrupt (MSI) memory-mapped I/O registers.\nThese registers provide interrupt control bits which are directly connected to the respective `soft_int` pins of each core.\nWriting to the corresponding bit of one of these registers enables remote harts to trigger machine-mode interprocessor interrupts.\n\nEach hart can read its own `mhartid` register (see [](adaptations.md#machine-hardware-thread-id-register-mhartid)) to determine the memory address of the associated memory-mapped MSI register within the platform.\nIn this manner, an interrupt service routine can reset the corresponding memory-mapped MSI register bit before returning from a software interrupt.\n" }, { "path": "docs/source/overview.md", "content": "# Core Overview\n\nThis chapter provides a high-level overview of the VeeR EL2 core and core complex. VeeR EL2 is a machinemode (M-mode) and usermode (U-mode), 32-bit CPU small core which supports RISC-V's integer (I), compressed instruction (C), multiplication and division (M), and instruction-fetch fence, CSR, and subset of bit manipulation instructions (Z) extensions. The core contains a 4-stage, scalar, in-order pipeline.\n\n## Features\n\nThe VeeR EL2 core complex's feature set includes:\n- RV32IMC-compliant RISC-V core with branch predictor\n- Optional instruction and data closely-coupled memories with ECC protection (load-to-use latency of 1 cycle for smaller and 2 cycles for larger memories)\n- Optional 2- or 4-way set-associative instruction cache with parity or ECC protection (32- or 64-byte line size)\n- Optional programmable interrupt controller supporting up to 255 external interrupts\n- Four system bus interfaces for instruction fetch, data accesses, debug accesses, and external DMA accesses to closely-coupled memories (configurable as 64-bit AXI4 or AHB-Lite)\n- Core debug unit compliant with the RISC-V Debug specification [[3]](intro.md#ref-3)\n- 600MHz target frequency (for 16nm technology node)\n\n## Core Complex\n\n{numref}`fig-core-complex` depicts the core complex and its functional blocks which are described further in section [](overview.md#functional-blocks).\n\n:::{figure-md} fig-core-complex\n![VeeR Core Complex](img/core_complex.png)\n\nVeeR Core Complex\n:::\n\n## Functional Blocks\n\nThe VeeR EL2 core complex's functional blocks are described in the following sections in more detail.\n\n### Core\n\n{numref}`fig-core-pipeline` depicts the scalar 4-stage core with one execution pipeline, one load/store pipeline, one multiplier pipeline, and one out-of-pipeline divider. There are two stall points in the pipeline: 'Fetch' and 'Decode'. The diagram also shows how VeeR EH1's logic stages have been shifted up and merged into 4 stages named Fetch (F), Decode (D), Execute/Memory (X/M), and Retire (R). Also shown is additional logic such as a new branch adder in the D stage. The branch mispredict penalty is either 1 or 2 cycles in VeeR EL2.\n\nThe merged F stage performs the program counter calculation and the I-cache/ICCM memory access in parallel. The load pipeline has been moved up so that the DC1 memory address generation (AGU) logic is now combined with align and decode logic to enable a DCCM memory access to start at the beginning of the M stage. The design supports a load-to-use of 1 cycle for smaller memories and a load-to-use of 2 cycles for larger memories. For 1-cycle load-to-use, the memory is accessed and the load data aligned and formatted for the register file and forwarding paths, all in the single-cycle M stage. For 2-cycle load-to-use, almost the entire M stage is allocated to the memory access, and the DC3/DC4 logic combined into the R stage is used to perform the load align and formatting for the register file and forwarding paths. EX3 and EX4/WB are combined into the R stage and primarily used for commit and writeback to update the architectural registers.\n\n:::{figure-md} fig-core-pipeline\n![VeeR EL2 Core Pipeline](img/core_pipeline.png)\n\nVeeR EL2 Core Pipeline\n:::\n\n## Standard Extensions\n\nThe VeeR EL2 core implements the following RISC-V standard extensions:\n\n:::{list-table} VeeR EL2's RISC-V Standard Extensions\n:name: tab-riscv-std-ext\n:header-rows: 1\n\n* - Extension\n - Description\n - References\n* - M\n - Integer multiplication and division\n - Chapter 7 in [[1]](intro.md#ref-1)\n* - C\n - Compressed instructions\n - Chapter 16 in [[1]](intro.md#ref-1)\n* - Zicsr\n - Control and status register (CSR) instructions\n - Chapter 9 in [[1]](intro.md#ref-1)\n* - Zifencei\n - Instruction-fetch fence\n - Chapter 3 in [[1]](intro.md#ref-1)\n* - Zba [^fn-standard-extensions-1] (address calculation) (frozen)\n - Bit manipulation instructions\n - Chapter 2 in [[4]](intro.md#ref-4)\n* - Zbb [^fn-standard-extensions-2] (base) (frozen)\n - Bit manipulation instructions\n - Chapter 2 in [[4]](intro.md#ref-4)\n* - Zbc [^fn-standard-extensions-3] (carry-less multiply) (frozen)\n - Bit manipulation instructions\n - Chapter 2 in [[4]](intro.md#ref-4)\n* - Zbs [^fn-standard-extensions-4] (single-bit) (frozen)\n - Bit manipulation instructions\n - Chapter 2 in [[4]](intro.md#ref-4)\n* - Zbe [^fn-standard-extensions-5] (bit compress/ decompress) (stable)\n - Bit manipulation instructions\n - Chapter 2 in [[4]](intro.md#ref-4)\n* - Zbf [^fn-standard-extensions-6] (bit-field place) (stable)\n - Bit manipulation instructions\n - Chapter 2 in [[4]](intro.md#ref-4)\n* - Zbp [^fn-standard-extensions-7] (bit permutation) (stable)\n - Bit manipulation instructions\n - Chapter 2 in [[4]](intro.md#ref-4)\n* - Zbr [^fn-standard-extensions-8] (CRC) (stable)\n - Bit manipulation instructions\n - Chapter 2 in [[4]](intro.md#ref-4)\n:::\n\n* `frozen` specified means that the extensions are not expected to change.\n* `stable` mean that the marked extension may still change.\n\n[^fn-standard-extensions-1]: List of Zba instructions (as of 1/20/21, \"frozen\"): sh1add, sh2add, sh3add\n[^fn-standard-extensions-2]: List of Zbb instructions (as of 1/20/21, \"frozen\"): clz, ctz, cpop, min, minu, max, maxu, sext.b, sext.h, zext.h, andn, orn, xnor, rol, ror, rori, rev8, orc.b\n[^fn-standard-extensions-3]: List of Zbc instructions (as of 1/20/21, \"frozen\"): clmul, clmulh, clmulr\n[^fn-standard-extensions-4]: List of Zbs instructions (as of 1/20/21, \"frozen\"): bset, bseti, bclr, bclri, binv, binvi, bext, bexti\n[^fn-standard-extensions-5]: List of Zbe instructions (as of 1/20/21, \"stable\"): bcompress, bdecompress, pack, packh\n[^fn-standard-extensions-6]: List of Zbf instructions (as of 1/20/21, \"stable\"): bfp, pack, packh\n[^fn-standard-extensions-7]: List of Zbp instructions (as of 1/20/21, \"stable\"): andn, orn, xnor, pack, packu, packh, rol, ror, rori, grev, grevi, gorc, gorci, shfl, shfli, unshfl, unshfli, xperm.n, xperm.b, xperm.h\n[^fn-standard-extensions-8]: List of Zbr instructions (as of 1/20/21, \"stable\"): crc32.b, crc32c.b, crc32.h, crc32c.h, crc32.w, crc32c.w\n" }, { "path": "docs/source/performance.md", "content": "# Performance Monitoring\n\nThis chapter describes the performance monitoring features of the VeeR EL2 core.\n\n## Features\n\nVeeR EL2 provides these performance monitoring features:\n\n* Four standard 64-bit wide event counters\n* Standard separate event selection for each counter\n* Standard selective count enable/disable controllability\n* Standard synchronized counter enable/disable controllability\n* Standard cycle counter\n* Standard retired instructions counter\n* Support for standard SoC-based machine timer registers\n\n## Control/Status Registers\n\n### Standard RISC-V Registers\n\nA list of performance monitoring-related standard RISC-V CSRs with references to their definitions:\n\n* Machine Hardware Performance Monitor (`mcycle{|h}`, `minstret{|h}`, `mhpmcounter3{|h}`- `mhpmcounter31{|h}`, and `mhpmevent3`-`mhpmevent31`) (see Section 3.1.11 in [[2]](intro.md#ref-2))\n* Machine Counter-Inhibit Register [^fn-performance-1] (`mcountinhibit`) (see Section 3.1.13 in [[2]](intro.md#ref-2))\n* Machine Timer Registers (`mtime` and `mtimecmp`) (see Section 3.1.10 in [[2]](intro.md#ref-2))\n\n:::{note}\n`mtime` and `mtimecmp` are memory-mapped registers which must be provided by the SoC.\n:::\n\n[^fn-performance-1]: The standard `mcountinhibit` register which was recently added to [[2]](intro.md#ref-2) replaces the non-standard mgpmc register of the previous VeeR generation. The `mcountinhibit` register provides the same functionality as the `mgpmc` register did, but at a much finer granularity (i.e., an enable/disable control bit per standard hardware performance counter instead of a single control bit for the `mhpmcounter3` - `mhpmcounter6` counters).\n\n## Counters\n\nOnly event counters 3 to 6 (`mhpmcounter3{|h}`-`mhpmcounter6{|h}`) and their corresponding event selectors (`mhpmevent3`-`mhpmevent6`) are functional on VeeR EL2.\n\nEvent counters 7 to 31 (`mhpmcounter7{|h}`-`mhpmcounter31{|h}`) and their corresponding event selectors (`mhpmevent7`-`mhpmevent31`) are hardwired to '0'.\n\n## Count-Impacting Conditions\n\nA few comments to consider on conditions that have an impact on the performance monitor counting:\n* While in the pmu/fw-halt power management state, performance counters (including the `mcycle` counter) are disabled.\n* While in debug halt (db-halt) state, the *stopcount* bit of the `dcsr` register (see [](debugging.md#debug-control-and-status-register-dcsr)) determines if performance counters are enabled.\n* While in the pmu/fw-halt power management state or the debug halt (db-halt) state with the stopcount bit set, DMA accesses are allowed, but not counted by the performance counters. It would be up to the bus master to count accesses while the core is in a halt state.\n* While executing PAUSE, performance counters are enabled.\n\nAlso, it is recommended that the performance counters are disabled (using the `mcountinhibit` register) before the counters and event selectors are modified, and then reenabled again.\nThis minimizes the impact of reading and writing the counter and event selector CSRs on the event count values, specifically for the CSR read/write events (i.e., events #16 and #17).\nIn general, performance counters are incremented after a read access to the counter CSRs, but before a write access to the counter CSRs.\n\n## Events\n\n{numref}`tab-list-of-countable-events` provides a list of the countable events.\n\n:::{note}\nThe event selector registers `mhpmevent3`-`mhpmevent6` have WARL behavior. When writing either a value marked as 'Reserved' or larger than the highest supported event number, the event selector is set to '0' (i.e., no event counted).\n:::\n\n:::{list-table} List of Countable Events\n:name: tab-list-of-countable-events\n\n* - **Event No**\n - **Event Name**\n - **Description**\n* - 0\n -\n - Reserved (no event counted)\n* - **Events counted while in Active (C0) state**\n -\n -\n* - Legend: IP = In-Pipe; OOP = Out-Of-Pipe\n -\n -\n* - 1\n - cycles clocks active\n - Number of cycles clock active (OOP)\n* - 2\n - I-cache hits\n - Number of I-cache hits (OOP, speculative, valid fetch & hit)\n* - 3\n - I-cache misses\n - Number of I-cache misses (OOP, valid fetch & miss)\n* - 4\n - instr committed - all\n - Number of all (16b+32b) instructions committed (IP, non-speculative, 0/1)\n* - 5\n - instr committed - 16b\n - Number of 16b instructions committed (IP, non-speculative, 0/1)\n* - 6\n - instr committed - 32b\n - Number of 32b instructions committed (IP, non-speculative, 0/1)\n* - 7\n - instr aligned - all\n - Number of all (16b+32b) instructions aligned (OOP, speculative, 0/1)\n* - 8\n - instr decoded - all\n - Number of all (16b+32b) instructions decoded (OOP, speculative, 0/1)\n* - 9\n - muls committed\n - Number of multiplications committed (IP, 0/1)\n* - 10\n - divs committed\n - Number of divisions and remainders committed (IP, 0/1)\n* - 11\n - loads committed\n - Number of loads committed (IP, 0/1)\n* - 12\n - stores committed\n - Number of stores committed (IP, 0/1)\n* - 13\n - misaligned loads\n - Number of misaligned loads (IP, 0/1)\n* - 14\n - misaligned stores\n - Number of misaligned stores (IP, 0/1)\n* - 15\n - alus committed\n - Number of ALU [^fn-performance-2] operations committed (IP, 0/1)\n* - 16\n - CSR read\n - Number of CSR read instructions committed (IP, 0/1)\n* - 17\n - CSR read/write\n - Number of CSR read/write instructions committed (IP, 0/1)\n* - 18\n - CSR write rd==0\n - Number of CSR write rd==0 instructions committed (IP, 0/1)\n* - 19\n - `ebreak`\n - Number of ebreak instructions committed (IP, 0/1)\n* - 20\n - `ecall`\n - Number of ecall instructions committed (IP, 0/1)\n* - 21\n - `fence`\n - Number of fence instructions committed (IP, 0/1)\n* - 22\n - `fence.i`\n - Number of fence.i instructions committed (IP, 0/1)\n* - 23\n - `mret`\n - Number of mret instructions committed (IP, 0/1)\n* - 24\n - branches committed\n - Number of branches committed (IP)\n* - 25\n - branches mispredicted\n - Number of branches mispredicted (IP)\n* - 26\n - branches taken\n - Number of branches taken (IP)\n* - 27\n - unpredictable branches\n - Number of unpredictable branches (IP)\n* - 28\n - cycles fetch stalled\n - Number of cycles fetch ready but stalled (OOP)\n* - 29\n -\n - Reserved\n* - 30\n - cycles decode stalled\n - Number of cycles one or more instructions valid in IB but decode stalled (OOP)\n* - 31\n - cycles postsync stalled\n - Number of cycles postsync stalled at decode (OOP)\n* - 32\n - cycles presync stalled\n - Number of cycles presync stalled at decode (OOP)\n* - 33\n -\n - Reserved\n* - 34\n - cycles SB/WB stalled (lsu_store_stall_any)\n - Number of cycles decode stalled due to SB or WB full (OOP)\n* - 35\n - cycles DMA DCCM transaction stalled (dma_dccm_stall_any)\n - Number of cycles DMA stalled due to decode for load/store (OOP)\n* - 36\n - cycles DMA ICCM transaction stalled (dma_iccm_stall_any)\n - Number of cycles DMA stalled due to fetch (OOP)\n* - 37\n - exceptions taken\n - Number of exceptions taken (IP)\n* - 38\n - timer interrupts taken\n - Number of timer [^fn-performance-3] interrupts taken (IP)\n* - 39\n - external interrupts taken\n - Number of external interrupts taken (IP)\n* - 40\n - TLU flushes (flush lower)\n - Number of TLU flushes (flush lower) (IP)\n* - 41\n - branch error flushes\n - Number of branch error flushes (IP)\n* - 42\n - I-bus transactions - instr\n - Number of instr transactions on I-bus interface (OOP)\n* - 43\n - D-bus transactions - ld/st\n - Number of ld/st transactions on D-bus interface (OOP)\n* - 44\n - D-bus transactions - misaligned\n - Number of misaligned transactions on D-bus interface (OOP)\n* - 45\n - I-bus errors\n - Number of transaction errors on I-bus interface (OOP)\n* - 46\n - D-bus errors\n - Number of transaction errors on D-bus interface (OOP)\n* - 47\n - cycles stalled due to I- bus busy\n - Number of cycles stalled due to AXI4 or AHB-Lite I-bus busy (OOP)\n* - 48\n - cycles stalled due to D- bus busy\n - Number of cycles stalled due to AXI4 or AHB-Lite D-bus busy (OOP)\n* - 49\n - cycles interrupts disabled\n - Number of cycles interrupts disabled (MSTATUS.MIE==0) (OOP)\n* - 50\n - cycles interrupts stalled while disabled\n - Number of cycles interrupts stalled while disabled (MSTATUS.MIE==0) (OOP)\n* - 51 - 53\n -\n - Reserved\n* - 54\n - bitmanip committed\n - Number of bit-manipulation operations committed (IP, 0/1)\n* - 55\n - D-bus loads committed\n - Number of load instructions to D-bus committed (IP, 0/1)\n* - 56\n - D-bus stores committed\n - Number of store instructions to D-bus committed (IP, 0/1)\n* - 57 - 511\n -\n - Reserved\n* - **Events counted while in Active (C0) or Sleep (C3) states**\n -\n -\n* - 512\n - cycles in Sleep (C3) state\n - Number of cycles in Sleep (C3) state (OOP)\n* - 513\n - DMA reads (all)\n - Total number of DMA slave read transactions (OOP)\n* - 514\n - DMA writes (all)\n - Total number of DMA slave write transactions (OOP)\n* - 515\n - DMA reads to DCCM\n - Number of DMA slave read transactions to DCCM (OOP)\n* - 516\n - DMA writes to DCCM\n - Number of DMA slave write transactions to DCCM (OOP)\n:::\n\n:::{note}\nIf an event shown as 'Reserved' is selected, no error is reported but counter is not incrementing.\n:::\n\n[^fn-performance-2]: NOP is an ALU operation. WFI is implemented as a NOP in VeeR EL2 and, hence, counted as an ALU operation was well.\n[^fn-performance-3]: Events counted include interrupts triggered by the standard RISC-V platform-level timer as well as by the two internal timers.\n" }, { "path": "docs/source/physical-memory-protection.md", "content": "# Physical Memory Protection\n\nThe Physical Memory Protection unit implemented in the VeeR EL2 Core is compliant with \"Section 3.7 Physical Memory Protection\" of [[5]](intro.md#ref-5).\n\nRISC-V introduces additional regulatory documents regarding memory protection:\n\n- [Supervisor mode PMP (SPMP)](https://github.com/riscv/riscv-spmp/blob/main/rv-spmp-spec.pdf)\n- [PMP enhancements (Smepmp)](https://github.com/riscv/riscv-tee/blob/main/Smepmp/Smepmp.pdf)\n\n## Theory of Operation\n\nThe PMP module adds a set of CSRs which define memory regions and Read/Write/Execute (RWX) access permissions.\nFor each memory access, the PMP module checks if accessed memory is on the allowlist.\nIn case of impermissible memory access, a precise exception is thrown and execution flow is switched to the trap handler.\nThe PMP distinguishes 3 types of memory accesses: instruction fetch, data load and data store.\n\n## Physical Memory Protection CSRs\n\nThe `pmpcfgX` and `pmpaddrX` CSRs are implemented in the [*el2_dec_tlu_ctl* module](../../design/dec/el2_dec_tlu_ctl.sv).\nCSR address decoding is generated from either [*csrdecode_m*](../../design/dec/csrdecode_m) (Machine mode) or [*csrdecode_mu*](../../design/dec/csrdecode_mu) (Machine and User mode) description file.\n\nThe number of `pmpcfgX` registers is always 4 times smaller than the number of PMP entries, which are configurable using the `-set=pmp_entires=N` option, where *N* can be 0, 16 or 64.\n\n:::{list-table} CSR configurations for RV-32\n:name: tab-riscv-pmp-csr-configuration-table\n:header-rows: 1\n:align: left\n* - Number of PMP entries\n - Number of *pmpcfgX* CSRs\n - Number of *pmpaddrX* CSRs\n* - 0\n - 0\n - 0\n* - 16\n - 4\n - 16\n* - 64\n - 16\n - 64\n:::\n\n### Configuration Registers (pmpcfgX)\n\nEach `pmpcfgX` register holds a configuration for four PMP entries, with a byte used for each entry.\n\n:::{list-table} Decoding of the *pmpcfgX* register\n:name: tab-riscv-pmpcfgx-register\n:header-rows: 1\n:align: left\n* - **Bit**\n - 7\n - 6\n - 5\n - 4\n - 3\n - 2\n - 1\n - 0\n* - **Flag**\n - *L*\n - *0*\n - *0*\n - *A[1]*\n - *A[0]*\n - *X*\n - *W*\n - *R*\n:::\n\nMeaning of bit flags:\n - *L* - lock bit; when set to *1*, given entry cannot be changed (both configuration and address) until hart reset\n - *0* - unused bits, always set to *0*\n - *A[1:0]* - encodes address matching mode (*OFF*, *TOR*, *NA4*, *NAPOT*)\n - *X* - execute permission; when set to *1*, allows instruction fetch from the corresponding address region; otherwise memory access will result in an instruction access-fault exception\n - *W* - write permission; when set to *1*, allows data store to the corresponding address region; otherwise memory access will result in a store access-fault exception\n - *R* - read permission; when set to *1*, allows data load from the corresponding address region; otherwise memory access will result in a load access-fault exception.\n\n### Address Registers (pmpaddrX)\n\nPMP address registers (`pmpaddrX`) encode bits 33 to 2 (`address[33:2]`) in physical memory.\nThis address defines protected memory region boundaries, further interpreted according to address matching values encoded by bits 4 and 3 of the `pmpcfgX` register:\n\n- *00* OFF Null region (disabled)\n- *01* TOR Top of range\n- *10* NA4 Naturally aligned four-byte region\n- *11* NAPOT Naturally aligned power-of-two region, >=8 bytes\n\n## Exceptions\n\nIn case of impermissible memory access, an exception is raised and the exception code is stored in the `mcause` CSR register (*0x342*).\n\n:::{list-table} PMP related exception codes\n:name: tab-riscv-pmp-exceptions\n:header-rows: 1\n:widths: 14 14 36\n* - **Interrupt flag (*mcause[MXLEN-1]*)**\n - **Exception Code (*mcause[MXLEN-2:0]*)**\n - **Exception description**\n* - *0*\n - *1*\n - Instruction access fault (cannot read instruction from protected region)\n* - *0*\n - *5*\n - Load access fault (cannot load data from protected region)\n* - *0*\n - *7*\n - Store/Atomic Memory Operation access fault (cannot store data to protected region)\n:::\n\nWhenever a PMP access fault exception is raised, the machine secondary cause register (`mscause`) value is *0x03* indicating \"access out of MPU range\".\n\n## PMP module\n\nThe PMP module is implemented in [el2_pmp.sv](../../design/el2_pmp.sv).\nIt is meant to be connected to the:\n\n- CSR configuration table\n- CSR addresses table\n- configuration inputs for each channel (marking permissions to be checked on a given channel)\n- address inputs for each channel (one for IFU, one for LSU)\n- error outputs for each channel\n\nThe following functionality has been implemented:\n\n- decoding address ranges (start address and mask) from address CSRs depending on the address matching mode for a given entry\n- comparing addresses coming from a channel to defined ranges\n- asserting error flags for given channels depending on permissions from the first matching range.\n\nError handling is performed using existing logic in IFU and LSU modules, reusing previously implemented mechanisms.\n\n:::{figure-md} riscv_pmp_block_diagram\n![riscv_pmp_block_diagram](img/19-riscv_pmp_block_diagram.png)\n\nPMP integration with other modules of the VeeR EL2 core.\n:::\n\n## Verification\n\nThe PMP module is tested with:\n\n* [RTL tests](../../verification/block/pmp/testbench.py)\n* [software smoke tests](../../testbench/tests/pmp/main.c)\n* [RISC-V DV tests](../../.github/workflows/test-riscv-dv.yml)\n\n## PMP check example\n\nIn this example we enforce the following permissions:\n\n- *0x00000000* - *0x00000FFF* - deny reads, writes, execution\n- *0x00001000* - *0x00001FFF* - allow reads, writes, execution\n\nFirst, let's configure the 2 address regions by writing 2 bytes to the lower 16 bits of the `pmpcfg0` register (each region configuration uses a byte)\nPMP configuration registers should be set to:\n\n- `pmpcfg0[7:0]` = *0b00001000* - non-locked entry, top-of-range address matching, all memory access denied.\n- `pmpcfg0[15:8]` = *0b00001111* - non-locked entry, top-of-range address matching, all memory access permitted.\n\nTo select top-of-range matching, bits 3 and 4 of the configuration field are set to *0b01*, which creates a region starting with the address from the previous entry `pmpaddrX-1` and ending at an address in the `pmpaddrX` register, decremented by one.\nIn case of the first entry on the list, the *0x00000000* address is used as boundary.\n\nAfter selecting the addressing mode, we can calculate values of `pmpaddr0` and `pmpaddr1` registers, which will define boundaries of regions.\nAddresses stored in `pmpaddrX` CSRs contain bits *[33:2]* of the memory address.\nThus to select a specific address, it must be shifted by 2 bits to the right before writing the value to the register:\n\n* `pmpaddr0` should be `(0x00001000 >> 2) = 0x00000400`, so that it matches the memory region from *0x00000000* to *0x00000FFF*.\n* `pmpaddr1` should be `(0x00002000 >> 2) = 0x00000800`, so that it matches the memory region from *0x00001000* (which is the top address of the previous entry) to *0x00001FFF*.\n\nWith this configuration, all memory accesses to the first region (*0x00000000* - *0x00000FFF*) will fail and trigger an exception.\nThe exception code can be read to determine the type of the failed operation (instruction fetch, data load or data store).\nOn the other hand, all memory accesses to the second region (*0x00001000* - *0x00001FFF*) will be executed without errors.\n" }, { "path": "docs/source/power.md", "content": "# Power Management and Multi-Core Debug Control\n\nThis chapter specifies the power management and multi-core debug control functionality provided or supported by the VeeR EL2 core. Also documented in this chapter is how debug may interfere with core power management.\n\n## Features\n\nVeeR EL2 supports and provides the following power management and multi-core debug control features:\n\n* Support for three system-level power states: Active (C0), Sleep (C3), Power Off (C6)\n* Firmware-initiated halt to enter sleep state\n* Fine-grain clock gating in active state\n* Enhanced clock gating in sleep state\n* Halt/run control interface to/from SoC Power Management Unit (PMU)\n* Signal indicating that core is halted\n* Halt/run control interface to/from SoC debug Multi-Processor Controller (MPC) to enable cross-triggering in multi-core chips\n* Timeout-based mechanism to force Debug Halt state by terminating hung bus transactions\n* Signals indicating that core is in Debug Mode and core hit a breakpoint\n* PAUSE feature to help avoid firmware spinning\n\n## Core Control Interfaces\n\nVeeR EL2 provides two control interfaces, one for power management and one for multi-core debug control, which enable the core to be controlled by other SoC blocks.\n\n### Power Management\n\nThe power management interface enables an SoC-based Power Management Unit (PMU) to:\n\n* Halt (i.e., enter low-power sleep state) or restart (i.e., resume execution) the core, and\n* get an indication when the core has gracefully entered the sleep state.\n\nThe power management interface signals are described in {numref}`tab-veer-el2-power-ctrl-status-signals`.\n\n### Multi-Core Debug Control\n\nThe multi-core debug control interface enables an SoC-based Multi-Processor Controller (MPC) to:\n\n* Control the reset state of the core (i.e., either start executing or enter Debug Mode),\n* halt (i.e., enter Debug Mode) or restart (i.e., resume execution) the core,\n* get an indication when the core is in Debug Mode, and\n* cross-trigger other cores when this core has entered Debug Mode due to a software or a hardware breakpoint.\n\nThe multi-core debug control interface signals are described in {numref}`tab-veer-el2-multi-core-debug-ctrl-status-signals`.\n\n## Power States\n\nFrom a system's perspective, the core may be placed in one of three power states: Active (C0), Sleep (C3), and Power Off (C6).\nActive and Sleep states require hardware support from the core, but in the Power Off state the core is power-gated so no special hardware support is needed.\n\n{numref}`fig-activity-states` depicts and {numref}`tab-core-activity-states` describes the core activity states as well as the events to transition between them.\n\n:::{figure-md} fig-activity-states\n![Activity states](img/activity_states.png)\n\nVeeR EL2 Core Activity States\n:::\n\n:::{note}\n'Core Quiesced' implies that no new instructions are executed and all outstanding core-initiated bus transactions are completed (i.e., the unified buffer is empty, and all outstanding I-cache misses are finished).\nNote that the store queue and the DMA FIFO might not be empty due to on-going DMA transactions.\n:::\n\n:::{list-table} Debug Resume Requests\n:name: tab-debug-resume-requests\n:header-rows: 1\n\n* - Core-Internal State\n -\n -\n -\n -\n -\n - **Comments**\n* - **Debug Resume**\n - **Debug Halt**\n - **MPC Halt**\n - **MPC Run**\n - **Halted (This Cycle)**\n - **Halted (Next Cycle)**\n -\n* - 0\n - 0\n - 0\n - 0\n - 0\n - 0\n - No request for Debug Mode entry\n* - 0\n - 0\n - 0\n - 1\n -\n -\n - No action required from core (requires coordination outside of core)\n* - 0\n - 0\n - 1\n - 0\n - 1\n - 1\n - Waiting for MPC Run (core remains in ‘db-halt’ state)\n* - 0\n - 0\n - 1\n - 1\n - 1\n - 0\n - MPC Run Ack\n* - 0\n - 1\n - 0\n - 0\n - 1\n - 1\n - Waiting for Debug Resume (core remains in ‘db-halt’ state)\n* - 0\n - 1\n - 0\n - 1\n -\n -\n - No action required from core (requires coordination outside of core)\n* - 0\n - 1\n - 1\n - 0\n - 1\n - 1\n - Waiting for both MPC Run and Debug Resume (core remains in ‘db-halt’ state)\n* - 0\n - 1\n - 1\n - 1\n - 1\n - 1\n - Waiting for Debug Resume (core remains in ‘db-halt’ state)\n* - 1\n - 0\n - 0\n - 0\n -\n -\n - No action required from core (requires coordination outside of core)\n* - 1\n - 0\n - 0\n - 1\n -\n -\n - No action required from core (requires coordination outside of core)\n* - 1\n - 0\n - 1\n - 0\n -\n -\n - No action required from core (requires coordination outside of core)\n* - 1\n - 0\n - 1\n - 1\n -\n -\n - No action required from core (requires coordination outside of core)\n* - 1\n - 1\n - 0\n - 0\n - 1\n - 0\n - Debug Resume Ack\n* - 1\n - 1\n - 0\n - 1\n -\n -\n - No action required from core (requires coordination outside of core)\n* - 1\n - 1\n - 1\n - 0\n - 1\n - 1\n - Waiting for MPC Run (core remains in ‘db-halt’ state)\n* - 1\n - 1\n - 1\n - 1\n - 1\n - 0\n - Debug Resume Ack and MPC Run Ack\n:::\n\n:::{note}\nWhile in 'db-halt' state, hardware ignores Debug Resume requests if the corresponding 'Debug Halt' state is not '1'.\nLikewise, hardware ignores MPC Debug Run requests if the corresponding 'MPC Halt' state is not '1'.\n:::\n\n:::{note}\nThe core-internal state bits are cleared upon exiting Debug Mode.\n:::\n\n:::{note}\nIn the time period between an MPC Debug Halt request and an MPC Debug Run request, a core debug singlestep action is stalled but stays pending.\n:::\n\n:::{note}\nEven if the core is already in Debug Mode due to a previous MPC Debug Halt request, a core debugger must initiate a debug halt (i.e., Core Debug Halt request) before it may start issuing other debug commands. However, if Debug Mode was entered due to a core debug breakpoint, a Core Debug Halt request is not required.\n:::\n\n:::{note}\nAn MPC Debug Halt request may only be signaled when the core is either not in Debug Mode or is already in Debug Mode due to a previous Core Debug Halt request or a debug breakpoint or trigger. Also, an MPC Debug Run request may only be signaled when the core is in Debug Mode due to either a previous MPC Debug Halt request, a previous Core Debug Halt request, or a debug breakpoint or trigger. Issuing more than one MPC Debug Halt requests in succession or more than one MPC Debug Run requests in succession is a protocol violation.\n:::\n\n:::{list-table} Core Activity States\n:name: tab-core-activity-states\n:header-rows: 1\n\n* -\n - **Active (C0)**\n - **Active (C0)**\n - **Sleep (C3)**\n* -\n - **Running**\n - **Halted**\n - **Halted**\n* -\n -\n - **db-halt**\n - **pmu/fw-halt**\n* - **State Description**\n - Core operating normally\n - Core halted in Debug Mode\n - Core halted by PMU halt request or by core firmware-initiated halt\n* - **Power Savings**\n - Fine-grain clock gating integrated in core minimizes power consumption during regular operation\n - Fine-grain clock gating\n - Enhanced clock gating in addition to fine-grain clock gating\n* - **DMA Access**\n - DMA accesses allowed\n - DMA accesses allowed\n - DMA accesses allowed\n* - **State Indication**\n -\n - `cpu_halt_status` is low\n - `debug_mode_status` is low (except for Core Debug Resume request with Single Step action)\n -\n - `cpu_halt_status` is low\n - `debug_mode_status` is high\n -\n - `cpu_halt_status` is high\n - `debug_mode_status` is low\n* - **Internal Timer Counters**\n - `mitcnt0/1` incremented every core clock cycle (also during execution of instructions while single-stepping in Debug Mode)\n - `mitcnt0/1` not incremented\n - Depends on *halt_en* bit in `mitctl0/1` registers:\n - 0: `mitcnt0/1` not incremented\n - 1: `mitcnt0/1` incremented every core clock cycle\n* - **Machine Cycle Performance- Monitoring Counter**\n - `mcycle` incremented every core clock cycle\n - Depends on *stopcount* bit of `dcsr` register (see [](debugging.md#debug-control-and-status-register-dcsr)):\n - 0: `mcycle` incremented every core clock cycle\n - 1: `mcycle` not incremented\n - `mcycle` not incremented\n:::\n\n## Power Control\n\nThe priority order of simultaneous halt requests is as follows:\n1. Any core debug halt action:\n * Core debug halt request\n * Core debug single step\n * Core debug breakpoint\n * Core debug trigger\n- or MPC debug halt request\n2. PMU halt request or core firmware-initiated halt\n\nIf the PMU sends a halt request while the core is in Debug Mode, the core disregards the halt request.\nIf the PMU's halt request is still pending when the core exits Debug Mode, the request is honored at that time.\nSimilarly, core firmware can't initiate a halt while in Debug Mode.\nHowever, it is not possible for a core firmware-initiated halt request to be pending when the core exits Debug Mode.\n\n:::{important}\nThere are two separate sources of debug operations: the core itself which conforms to the standard RISC-V Debug specification [[3]](intro.md#ref-3), and the Multi-Processor Controller (MPC) IP block which provides multi-core debug capabilities.\nThese two sources may interfere with each other and need to be carefully coordinated on a higher level outside the core.\nUnintended behavior might occur if simultaneous debug operations from these two sources are not synchronized (e.g., MPC requesting a resume during the execution of an abstract command initiated by the debugger attached to the JTAG port).\n:::\n\n### Debug Mode\n\nDebug Mode must be able to seize control of the core.\nTherefore, debug has higher priority than power control.\n\nDebug Mode is entered under any of the following conditions:\n* Core debug halt request\n* Core debug single step\n* Core debug breakpoint with halt action\n* Core debug trigger with halt action\n* Multi-core debug halt request (from MPC)\n\nDebug Mode is exited with:\n* Core debug resume request with no single step action\n* Multi-core debug run request (from MPC)\n\nThe state 'db-halt' is the only halt state allowed while in Debug Mode.\n\n#### Single Stepping\n\nA few notes about executing single-stepped instructions:\n* Executing instructions which attempt to exit Debug Mode are ignored (e.g., writing to the `mpmc` register requesting to halt the core does not transition the core to the pmu/fw-halt state).\n* Accesses to D-mode registers are illegal, even though the core is in Debug Mode.\n* A core debug single-step action initiated in the time period between an MPC Debug Halt request and an MPC Debug Run request is stalled but stays pending until an MPC Debug Run request is issued.\n\n#### Forced Debug Halt\n\nUpon receiving a debug halt request (i.e., either a Core Debug or MPC Debug Halt request, or a breakpoint or trigger to Debug Mode), the core is typically quiesced before the Debug Halt (db-halt) state is entered.\nHowever, LSU or IFU bus transactions may not complete due to SoC or other issues outside the core which may stop the core from executing.\nThis may prevent the core from entering the Debug Halt state after a debug halt request has been received.\nTo enable a debugger taking control of the core, ongoing LSU and IFU bus transactions may be terminated after a programmable timeout period (see [](power.md#forced-debug-halt-threshold-register-mfdht)) has passed, forcing the core into the Debug Halt state.\nOnce the debugger has control of the core, it may read a status register (see [](power.md#forced-debug-halt-status-register-mfdhs)) to inquire if LSU or IFU bus transactions have been terminated and data might have been lost.\n\n:::{note}\n This feature is targeted at allowing a debugger to take control of a hung core. Therefore, the timeout period should be set high enough to cover any reasonable delay incurred by any access to SoC memory locations and devices. This should include potential additional delays due to congestion in the interconnect and other possible temporary conditions. If the timeout period is long enough for all outstanding transactions to gracefully finish, program execution may be resumed after debugging has been performed. However, if any outstanding transactions are prematurely forced to terminate, successfully resuming program execution after debug should not be expected because the data of terminated transactions may have been lost and possibly even a reset of the SoC might be necessary to bring the system back into a consistent state.\n:::\n\n### Core Power and Multi-Core Debug Control and Status Signals\n\n{numref}`fig-debug-csrs` depicts the power and multi-core debug control and status signals which connect the VeeR EL2 core to the PMU and MPC IPs.\nSignals from the PMU and MPC to the core are asynchronous and must be synchronized to the core clock domain.\nSimilarly, signals from the core are asynchronous to the PMU and MPC clock domains and must be synchronized to the PMU's or MPC's clock, respectively.\n\n:::{note}\nThe synchronizer of the `cpu_run_req` signal may not be clock-gated. Otherwise, the core may not be woken up again via the PMU interface.\n:::\n\n:::{figure-md} fig-debug-csrs\n![Debug CSRS](img/debug_csrs.png)\n\nVeeR EL2 Power and Multi-Core Debug Control and Status Signals\n:::\n\n#### Power Control and Status Signals\n\nThere are three types of signals between the Power Management Unit and the VeeR EL2 core, as described in {numref}`tab-veer-el2-power-ctrl-status-signals`. All signals are active-high.\n\n:::{list-table} VeeR EL2 Power Control and Status Signals\n:name: tab-veer-el2-power-ctrl-status-signals\n\n* - **Signal(s)**\n - **Description**\n* - `cpu_halt_req` and `cpu_halt_ack`\n - Full handshake to request the core to halt.\n \n The PMU requests the core to halt (i.e., enter pmu/fw-halt) by asserting the `cpu_halt_req` signal. The core is quiesced before halting. The core then asserts the `cpu_halt_ack` signal. When the PMU detects the asserted `cpu_halt_ack` signal, it deasserts the `cpu_halt_req` signal. Finally, when the core detects the deasserted `cpu_halt_req` signal, it deasserts the `cpu_halt_ack` signal.\n \n **Note:** `cpu_halt_req` must be tied to '0' if PMU interface is not used.\n* - `cpu_run_req` and `cpu_run_ack`\n - Full handshake to request the core to run.\n \n The PMU requests the core to run by asserting the `cpu_run_req` signal. The core exits the halt state and starts execution again. The core then asserts the `cpu_run_ack` signal. When the PMU detects the asserted `cpu_run_ack` signal, it deasserts the `cpu_run_req` signal. Finally, when the core detects the deasserted `cpu_run_req` signal, it deasserts the `cpu_run_ack` signal.\n \n **Note:** `cpu_run_req` must be tied to '0' if PMU interface is not used.\n* - `cpu_halt_status`\n - Indication from the core to the PMU that the core has been gracefully halted.\n:::\n\n:::{note}\nPower control protocol violations (e.g., simultaneously sending a run and a halt request) may lead to unexpected behavior.\n:::\n\n{numref}`fig-csr-timing` depicts conceptual timing diagrams of a halt and a run request. Note that entering Debug Mode is an asynchronous event relative to power control commands sent by the PMU. Debug Mode has higher priority and can interrupt and override PMU requests.\n\n:::{figure-md} fig-csr-timing\n![CSR Timing](img/csr_timing.png)\n\nVeeR EL2 Power Control and Status Interface Timing Diagrams\n:::\n\n#### Multi-Core Debug Control and Status Signals\n\nThere are five types of signals between the Multi-Processor Controller and the VeeR EL2 core, as described in {numref}`tab-veer-el2-multi-core-debug-ctrl-status-signals`. All signals are active-high.\n\n:::{list-table} VeeR EL2 Multi-Core Debug Control and Status Signals\n:name: tab-veer-el2-multi-core-debug-ctrl-status-signals\n\n* - **Signal(s)**\n - **Description**\n* - `mpc_debug_halt_req` and `mpc_debug_halt_ack`\n - Full handshake to request the core to debug halt.\n \n The MPC requests the core to halt (i.e., enter ‘db-halt’) by asserting the `mpc_debug_halt_req` signal. The core is quiesced before halting. The core then asserts the `mpc_debug_halt_ack` signal. When the MPC detects the asserted `mpc_debug_halt_ack` signal, it deasserts the `mpc_debug_halt_req` signal. Finally, when the core detects the deasserted `mpc_debug_halt_req` signal, it deasserts the `mpc_debug_halt_ack` signal.\n \n For as long as the `mpc_debug_halt_req` signal is asserted, the core must assert and hold the `mpc_debug_halt_ack` signal whether it was already in ‘db-halt’ or just transitioned into ‘db-halt’ state.\n \n **Note:** The *cause* field of the core’s `dcsr` register (see [](debugging.md#debug-control-and-status-register-dcsr)) is set to 3 (i.e., the same value as a debugger-requested entry to Debug Mode due to a Core Debug Halt request). Similarly, the `dpc` register (see [](debugging.md#debug-pc-register-dpc)) is updated with the address of the next instruction to be executed at the time that Debug Mode was entered.\n \n **Note:** Signaling more than one MPC Debug Halt request in succession is a protocol violation.\n \n **Note:** `mpc_debug_halt_req` must be tied to ‘0’ if MPC interface is not used.\n* - `mpc_debug_run_req` and `mpc_debug_run_ack`\n - Full handshake to request the core to run.\n \n The MPC requests the core to run by asserting the `mpc_debug_run_req` signal. The core exits the halt state and starts execution again. The core then asserts the `mpc_debug_run_ack` signal. When the MPC detects the asserted `mpc_debug_run_ack` signal, it deasserts the `mpc_debug_run_req` signal. Finally, when the core detects the deasserted `mpc_debug_run_req` signal, it deasserts the `mpc_debug_run_ack` signal.\n \n For as long as the `mpc_debug_run_req` signal is asserted, the core must assert and hold the `mpc_debug_run_ack` signal whether it was already in ‘Running’ or after transitioning into ‘Running’ state.\n \n **Note:** The core remains in the ‘db-halt’ state if a core debug request is also still active.\n \n **Note:** Signaling more than one MPC Debug Run request in succession is a protocol violation.\n \n **Note:** `mpc_debug_run_req` must be tied to ‘0’ if MPC interface is not used.\n* - `mpc_reset_run_req`\n - Core start state control out of reset:\n - 1: Normal Mode (‘Running’ or ‘pmu/fw-halt’ state)\n - 0: Debug Mode halted (‘db-halt’ state)\n \n **Note:** The core complex does not implement a synchronizer for this signal because the timing of the first clock is critical. It must be synchronized to the core clock domain outside the core in the SoC.\n \n **Note:** `mpc_reset_run_req` must be tied to ‘1’ if MPC interface is not used.\n* - `debug_mode_status`\n - Indication from the core to the MPC that it is currently transitioning to or already in Debug Mode.\n* - `debug_brkpt_status`\n - Indication from the core to the MPC that a software (i.e., ebreak instruction) or hardware (i.e., trigger hit) breakpoint has been triggered in the core. The breakpoint signal is only asserted for breakpoints and triggers with debug halt action. The signal is deasserted on exiting Debug Mode.\n:::\n\n:::{note}\nMulti-core debug control protocol violations (e.g., simultaneously sending a run and a halt request) may lead to unexpected behavior.\n:::\n\n:::{note}\nIf the core is either not in the db-halt state (i.e., `debug_mode_status` indication is not asserted) or is already in the db-halt state due to a previous Core Debug Halt request or a debug breakpoint or trigger (i.e., `debug_mode_status` indication is already asserted), asserting the `mpc_debug_halt_req` signal is allowed and acknowledged with the assertion of the `mpc_debug_halt_ack` signal. Also, asserting the `mpc_debug_run_req` signal is only allowed if the core is in the db-halt state (i.e., `debug_mode_status` indication is asserted), but the core asserts the `mpc_debug_run_ack` signal only after the `cpu_run_req` signal on the PMU interface has been asserted as well, if a PMU Halt request was still pending.\n:::\n\n:::{note}\nIf the MPC is requesting the core to enter Debug Mode out of reset by activating the `mpc_reset_run_req` signal, the `mpc_debug_run_req` signal may not be asserted until the core is out of reset and has entered Debug Mode. Violating this rule may lead to unexpected core behavior.\n:::\n\n:::{note}\nIf Debug Mode is entered at reset by setting the `mpc_reset_run_req` signal to '0', only a run request issued on the `mpc_debug_run_req/ack` interface allows the core to exit Debug Mode. A core debug resume request issued by the debugger does not transition the core out of Debug Mode.\n:::\n\n{numref}`fig-multicore-csr-timing` depicts conceptual timing diagrams of a halt and a run request.\n\n:::{figure-md} fig-multicore-csr-timing\n![Multi-Core CSR Timing](img/multicore_csr_timing.png)\n\nVeeR EL2 Multi-Core Debug Control and Status Interface Timing Diagrams\n:::\n\n{numref}`fig-breakpoint-timing` depicts conceptual timing diagrams of the breakpoint indication.\n\n:::{figure-md} fig-breakpoint-timing\n![Breakpoint Indication Timing](img/breakpoint_timing.png)\n\nVeeR EL2 Breakpoint Indication Timing Diagrams\n:::\n\n### Debug Scenarios\n\nThe following mixed core debug and MPC debug scenarios are supported by the core:\n\n#### Scenario 1: Core Halt → MPC Halt → MPC Run → Core Resume\n1. Core debugger asserts a Debug Halt request which results in the core transitioning into Debug Halt state (db-halt).\n2. In the system, another processor hits a breakpoint. The MPC signals a Debug Halt request to all processors to halt.\n3. Core acknowledges this Debug Halt request as it is already in Debug Halt state (db-halt).\n4. MPC signals a Debug Run request, but core is in the middle of a core debugger operation (e.g., an Abstract Command-based access) which requires it to remain in Debug Halt state.\n5. Core completes debugger operation and waits for Core Debug Resume request from the core debugger.\n6. When core debugger sends a Debug Resume request, the core then transitions to the Running state and deasserts the `debug_mode_status` signal.\n7. Finally, core acknowledges MPC Debug Run request.\n\n#### Scenario 2: Core Halt → MPC Halt → Core Resume → MPC Run\n1. Core debugger asserts a Debug Halt request which results in the core transitioning into Debug Halt state (db-halt).\n2. In the system, another processor hits a breakpoint. The MPC signals Debug Halt request to all processors to halt.\n3. Core acknowledges this Debug Halt request as it is already in Debug Halt state (db-halt).\n4. Core debugger completes its operations and sends a Debug Resume request to the core.\n5. Core remains in Halted state as MPC has not yet asserted its Debug Run request.\n The `debug_mode_status` signal remains asserted.\n6. When MPC signals a Debug Run request, the core then transitions to the Running state and deasserts the `debug_mode_status` signal.\n7. Finally, core acknowledges MPC Debug Run request.\n\n#### Scenario 3: Mpc Halt → Core Halt → Core Resume → Mpc Run\n\n1. MPC asserts a Debug Halt request which results in the core transitioning into Debug Halt state (db-halt).\n2. Core acknowledges this Debug Halt request.\n3. Core debugger signals a Debug Halt request to the core. Core is already in Debug Halt state (db-halt).\n4. Core debugger completes its operations and sends a Debug Resume request to the core.\n5. Core remains in Halted state as MPC has not yet asserted its Debug Run request. The `debug_mode_status` signal remains asserted.\n6. When MPC signals a Debug Run request, the core then transitions to the Running state and deasserts the `debug_mode_status` signal.\n7. Finally, core acknowledges MPC Debug Run request.\n\n#### Scenario 4: MPC Halt → Core Halt → MPC Run → Core Resume\n\n1. MPC asserts a Debug Halt request which results in the core transitioning into Debug Halt state (db-halt).\n2. Core acknowledges this Debug Halt request.\n3. Core debugger signals a Debug Halt request to the core. Core is already in Debug Halt state (db-halt).\n4. MPC signals a Debug Run request, but core debugger operations are still in progress. Core remains in Halted state. The `debug_mode_status` signal remains asserted.\n5. Core debugger completes operations and signals a Debug Resume request to the core.\n6. The core then transitions to the Running state and deasserts the `debug_mode_status` signal.\n7. Finally, core acknowledges MPC Debug Run request.\n\n#### Summary\n\nFor the core to exit out of Debug Halt state (db-halt) in cases where it has received debug halt requests from both core debugger and MPC, it must receive debug run requests from both the core debugger as well as the MPC, irrespective of the order in which debug halt requests came from both sources.\nUntil then, the core remains halted and the `debug_mode_status` signal remains asserted.\n\n### Core Wake-Up Events\n\nWhen not in Debug Mode (i.e., the core is in pmu/fw-halt state), the core is woken up on several events:\n* PMU run request\n* Highest-priority external interrupt (`mhwakeup` signal from PIC) and core interrupts are enabled\n* Software interrupt\n* Timer interrupt\n* Internal timer interrupt\n* Non-maskable interrupt (NMI) (`nmi_int` signal)\n\nThe PIC is part of the core logic and the `mhwakeup` signal is connected directly inside the core.\nThe internal timers are part of the core and internally connected as well.\nThe standard RISC-V software and timer interrupt as well as NMI signals are external to the core and originate in the SoC.\nIf desired, these signals can be routed through the PMU and further qualified there.\n\n### Core Firmware-Initiated Halt\n\nThe firmware running on the core may also initiate a halt by writing a '1' to the *halt* field of the `mpmc` register (see [](power.md#power-management-control-register-mpmc)).\nThe core is quiesced before indicating that it has gracefully halted.\n\n### DMA Operations While Halted\n\nWhen the core is halted in the 'pmu/fw-halt' or the 'db-halt' state, DMA operations are supported.\n\n### External Interrupts While Halted\n\nAll non-highest-priority external interrupts are temporarily ignored while halted.\nOnly external interrupts which activate the `mhwakeup` signal (see [](interrupts.md#regular-operation), Steps 13 and 14) are honored, if the core is enabled to service external interrupts (i.e., the *mie* bit of the `mstatus` and the *meie* bit of the `mie` standard RISC-V registers are both set, otherwise the core remains in the 'pmu/fw-halt' state).\nExternal interrupts which are still pending and have a sufficiently high priority to be signaled to the core are serviced once the core is back in the Running state.\n\n## Control/Status Registers\n\nA summary of platform-specific control/status registers in CSR space:\n* [](power.md#power-management-control-register-mpmc)\n* [](power.md#core-pause-control-register-mcpc)\n* [](power.md#forced-debug-halt-threshold-register-mfdht)\n* [](power.md#forced-debug-halt-status-register-mfdhs)\n\nAll reserved and unused bits in these control/status registers must be hardwired to '0'.\nUnless otherwise noted, all read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.\n\n### Power Management Control Register (mpmc)\n\nThe `mpmc` register provides core power management control functionality.\nIt allows the firmware running on the core to initiate a transition to the Halted (pmu/fw-halt) state.\nWhile entering the Halted state, interrupts may optionally be enabled atomically.\n\nThe *halt* field of the `mpmc` register has W1R0 (Write 1, Read 0) behavior, as also indicated in the 'Access' column.\n\n:::{note}\nWriting a '1' to the *haltie* field of the `mpmc` register without also setting the *halt* field has no immediate effect on the *mie* bit of the `mstatus` register.\nHowever, the *haltie* field of the `mpmc` register is updated accordingly.\n:::\n\n:::{note}\nOnce the *mie* bit of the `mstatus` register is set via the *haltie* field of the `mpmc` register, it remains set until other operations clear it.\nExiting the Halted (pmu/fw-halt) state does not clear the *mie* bit of the `mstatus` register set by entering the Halted state.\n:::\n\n:::{note}\nIn Debug Mode, writing (i.e., setting or clearing) *haltie* has no effect on the `mstatus` register's *mie* bit since the core does not transition to the Halted (pmu/fw-halt) state.\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Power Management Control Register (mpmc, at CSR 0x7C6)\n:name: tab-power-mgmt-ctrl-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:2\n - Reserved\n - R\n - 0\n* - haltie\n - 1\n - Control interrupt enable (i.e., *mie* bit of `mstatus` register) when transitioning to Halted (pmu/fw-halt) state by setting halt bit below:\n - 0: Don't change *mie* bit of `mstatus` register\n - 1: Set *mie* bit of `mstatus` register (i.e., atomically enable interrupts)\n - R/W\n - 1\n* - halt\n - 0\n - Initiate core halt (i.e., transition to Halted (pmu/fw-halt) state)\n \n **Note:** Write ignored if in Debug Mode\n - R0/W1\n - 0\n:::\n\n### Core Pause Control Register (mcpc)\n\nThe `mcpc` register supports functions to temporarily stop the core from executing instructions.\nThis helps to save core power since busy-waiting loops can be avoided in the firmware.\n\nPAUSE stops the core from executing instructions for a specified number [^fn-power-1] of clock ticks or until an interrupt is received.\n\n[^fn-power-1]: The field width provided by the mcpc register allows to pause execution for about 4 seconds at a 1 GHz core clock.\n\n:::{note}\nPAUSE is a long-latency, interruptible instruction and does not change the core's activity state (i.e., the core remains in the Running state).\nTherefore, even though this function may reduce core power, it is not part of core power management.\n:::\n\n:::{note}\nPAUSE has a skid of several cycles.\nTherefore, instruction execution might not be stopped for precisely the number of cycles specified in the *pause* field of the mcpc register.\nHowever, this is acceptable for the intended use case of this function.\n:::\n\n:::{note}\nDepending on the *pause_en* bit of the `mitctl0/1` registers, the internal timers might be incremented while executing PAUSE.\nIf an internal timer interrupt is signaled, PAUSE is terminated and normal execution resumes.\n:::\n\n:::{note}\nIf the PMU sends a halt request while PAUSE is still executing, the core enters the Halted (pmu/fw-halt) state and the *pause* clock counter stops until the core is back in the Running state.\n:::\n\n:::{note}\nWFI is another candidate for a function that stops the core temporarily.\nCurrently, the WFI instruction is implemented as NOP, which is a fully RISC-V-compliant option.\n:::\n\nThe *pause* field of the `mcpc` register has WAR0 (Write Any value, Read 0) behavior, as also indicated in the 'Access' column.\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Core Pause Control Register (mcpc, at CSR 0x7C2)\n:name: tab-core-pause-ctrl-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - pause\n - 31:0\n - Pause execution for number of core clock cycles specified\n \n **Note:** *pause* is decremented by 1 for each core clock cycle. Execution continues either when *pause* is 0 or any interrupt is received.\n - R0/W\n - 0\n:::\n\n### Forced Debug Halt Threshold Register (mfdht)\n\nThe `mfdht` register hosts the enable bit of the forced debug halt mechanism as well as the power-of-two exponent of the timeout threshold.\nWhen enabled, if a debug halt request is received and LSU and/or IFU bus transactions are pending, an internal timeout counter starts incrementing with each core clock and keeps incrementing until the Debug Halt *(db-halt)* state is entered.\nIf all ongoing bus transactions complete within the timeout period and the core is quiesced, the Debug Halt state is entered as usual.\nHowever, if the timeout counter *value* is equal to or greater than the threshold value (= {math}`2^{thresh}` core clocks), all in-progress LSU and IFU bus transactions are terminated and the Debug Halt state is entered (i.e. the core may be forced to the Debug Halt state before it is fully quiesced).\nIn addition, when entering the Debug Halt state in either case, the `mfdhs` register (see [](power.md#forced-debug-halt-status-register-mfdhs) below) latches the status if any LSU or IFU bus transactions have been prematurely terminated.\n\n:::{note}\nThe internal timeout counter is cleared at reset as well as when the Debug Halt (db-halt) state is exited.\n:::\n\n:::{note}\nThe 5-bit threshold (*thresh* field) allows a timeout period of up to {math}`2^{31}` core clock cycles (i.e., about 2.1 seconds at a 1GHz core clock frequency).\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Forced Debug Halt Threshold Register (mfdht, at CSR 0x7CE)\n:name: tab-forced-debug-halt-thld-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:6\n - Reserved\n - R\n - 0\n* - thresh\n - 5:1\n - Power-of-two exponent of timeout threshold (= {math}`2^{thresh}` core clock cycles)\n - R/W\n - 0\n* - enable\n - 0\n - Enable/disable forced debug halt timeout:\n - 0: Timeout mechanism disabled (default)\n - 1: Timeout mechanism enabled\n - R/W\n - 0\n:::\n\n### Forced Debug Halt Status Register (mfdhs)\n\nThe mfdhs register provides status information if any LSU and/or IFU bus transactions have been prematurely terminated when the Debug Halt (db-halt) state has been entered.\nA debugger may read this register to inquire if any bus transactions have been terminated and data may have been lost while entering the Debug Halt state.\nIf both status bits are '0' indicates that the core was properly quiesced.\n\n:::{note}\nA debugger may also clear the status bits if desired, but clearing is not required for proper operation.\n:::\n\nThis register is mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Forced Debug Halt Status Register (mfdhs, at CSR 0x7CF)\n:name: tab-forced-debug-halt-status-register\n\n* - **Field**\n - **Bits**\n - **Description**\n - **Access**\n - **Reset**\n* - Reserved\n - 31:2\n - Reserved\n - R\n - 0\n* - lsu\n - 1\n - LSU bus transaction termination status:\n - 0: No transactions have been prematurely terminated\n - 1: One or more transactions have been prematurely terminated\n - R/W\n - 0\n* - ifu\n - 0\n - IFU bus transaction termination status:\n - 0: No transactions have been prematurely terminated\n - 1: One or more transactions have been prematurely terminated\n - R/W\n - 0\n:::\n" }, { "path": "docs/source/simulation-debugging.md", "content": "# Interactive Debugging in Simulation\n\nIt is possible to perform a debugging session through a virtual JTAG interface with the VeeR EL2 Core running in simulation.\nThis allows the user to exercise JTAG usage scenarios using actual debugging tools instead of unit tests written for JTAG logic.\nThe feature was added to the VeeR EL2 Core with [Pull Request #211](https://github.com/chipsalliance/Cores-VeeR-EL2/pull/211).\n\nThe principle of operation is a JTAG probe RTL model which communicates with the host via DPI.\nThis is illustrated in {numref}`fig-openocd-jtag`:\n\n:::{figure-md} fig-openocd-jtag\n![](img/openocd-jtag.png)\n\nOpenOCD JTAG\n:::\n\nCurrently the probe model implements the `remote_bitbang` protocol of [OpenOCD](https://openocd.org/), allowing the tool to interact with simulation.\nThe protocol operates over a TCP/IP connection or a UNIX socket.\nAn appropriate server and protocol decoder runs on the host machine and communicates with the simulation via DPI to set/read JTAG signal states.\nThe entire flow is transparent to the debugging tools and to the user.\n\nThe probe model has been integrated into the testbench.\nIt is active every time the testbench is run; there is no need for any additional action.\nTo run a testbench, execute, for example:\n\n```bash\nmake -C run -f ${RV_ROOT}/tools/Makefile verilator-build program.hex TEST=infinite_loop \\\n CONF_PARAMS=\"-set openocd_test\"\n```\n\nThe `RV_ROOT` variable in the snippet above is the path to the root of the Cores-VeeR-EL2 repository.\n\nTo keep the simulation running continuously, the `infinite_loop` test program has been added.\nThe program consists of two nested loops running continuously.\n\nThen, to connect to a running simulation via OpenOCD, you can use the configs available in the `testbench/openocd_scripts` directory:\n\n```bash\ncd testbench/openocd_scripts\nopenocd -d2 -f verilator-rst.cfg jtag_cg.tcl\n```\n\n`jtag_cg.ctl` is an OpenOCD script that performs JTAG access tests.\nThese include core register access and memory access.\nThe configuration is passed by `verilator-rst.cfg`.\nIt includes `sim-jtagdpi.cfg` and `veer-el2-rst.cfg`.\n`sim-jtagdpi.cfg` contains a JTAG adapter configuration.\n`veer-el2-rst.cfg` configures the target for OpenOCD.\nThe test involves the CPU core held permanently in reset.\nMoreover, a [customized version of OpenOCD](https://github.com/antmicro/openocd/tree/riscv-nohalt) had to be used, as the stock version performs target CPU examination by default which is not possible when in reset.\n\n### Automation\n\nIn the `.github/scripts` directory of the [VeeR](https://github.com/chipsalliance/Cores-VeeR-EL2) repository, you can find a helper `openocd_test.sh` script that is responsible for launching simulation, executing an OpenOCD script as a test and terminating it.\nThe script is used in CI.\n\nThe script assumes that both the verilated simulation and the CPU program binary are already built.\nYou can find a usage example in the GitHub Action workflow definition: `.github/workflows/test-openocd.yml`.\n" }, { "path": "docs/source/tests.md", "content": "# Compliance Test Suite Failures\n\n## *I-MISALIGN_LDST-01*\n\n* **Test Location**: [https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S](https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S)\n* **Reason for Failure**:\n * The VeeR EL2 core supports unaligned accesses to memory addresses which are not marked as having side effects (i.e., to idempotent memory).\n Load and store accesses to non-idempotent memory addresses take misalignment exceptions.\n * Note that this is a known issue with the test suite ([https://github.com/riscv/riscv-compliance/issues/22](https://github.com/riscv/riscv-compliance/issues/22)) and is expected to eventually be fixed.\n* **Workaround**:\n * Configure the address range used by this test to \"non-idempotent\" in the `mrac` register.\n\n## *I-MISALIGN_JMP-01*\n\n* **Test location**: [https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S](https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S)\n* **Reason for Failure**:\n * The VeeR EL2 core supports the standard \"C\" 16-bit compressed instruction extension.\n Compressed instruction execution cannot be turned off.\n Therefore, branch and jump instructions to 16-bit aligned memory addresses do not trigger misalignment exceptions.\n * Note that this is a known issue with the test suite ([https://github.com/riscv/riscv-compliance/issues/16](https://github.com/riscv/riscv-compliance/issues/16)) and is expected to eventually be fixed.\n* **Workaround**:\n * None.\n\n## *I-FENCE.I-01 and fence_i*\n\n* **Test location**:\n * [https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S](https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S) and\n * [https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32ui/src/fence_i.S](https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32ui/src/fence_i.S)\n* **Reason for Failure**:\n * The VeeR EL2 core implements separate instruction and data buses to the system interconnect (i.e., Harvard architecture).\n The latencies to memory through the system interconnect may be different for the two interfaces and the order is therefore not guaranteed.\n* **Workaround**:\n * Configuring the address range used by this test to \"non-idempotent\" in the `mrac` register forces the core to wait for a write response before fetching the updated line.\n Alternatively, the system interconnect could provide ordering guarantees between requests sent to the instruction fetch and load/store bus interfaces (e.g., matching latencies through the interconnect).\n\n## *Breakpoint*\n\n* **Test Location**:\n * [https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32mi/src/breakpoint.S](https://github.com/riscv/riscv-compliance/blob/master/riscv-test-suite/rv32mi/src/breakpoint.S)\n* **Reason for Failure**:\n * The VeeR EL2 core disables breakpoints when the *mie* bit in the standard `mstatus` register is cleared.\n * Note that this behavior is compliant with the RISC-V External Debug Support specification, Version 0.13.2. See Section 5.1, 'Native M-Mode Triggers' in [[3]](intro.md#ref-3) for more details.\n* **Workaround**:\n * None.\n" }, { "path": "docs/source/timers.md", "content": "# Internal Timers\n\nThis chapter describes the internal timer feature of the VeeR EL2 core.\n\n## Features\n\nThe VeeR EL2's internal timer features are:\n\n* Two independently controlled 32-bit timers\n * Dedicated counter\n * Dedicated bound\n * Dedicated control to enable/disable incrementing generally, during power management Sleep, and while executing PAUSE\n * Enable/disable local interrupts (in standard RISC-V `mie` register)\n* Cascade mode to form a single 64-bit timer\n\n## Description\n\nThe VeeR EL2 core implements two internal timers.\nThe `mitcnt0` and `mitcnt1` registers (see [Internal Timer Counter 0 / 1 Register (mitcnt0/1)](timers.md#internal-timer-counter-0-1-register-mitcnt0-1)) are 32-bit unsigned counters.\nEach counter also has a corresponding 32-bit unsigned bound register (i.e., `mitb0` and `mitb1`, see [Internal Timer Bound 0 / 1 Register (mitb0/1)](timers.md#internal-timer-bound-0-1-register-mitb0-1)) and control register (i.e., `mitctl0` and `mitctl1`, see [Internal Timer Control 0 / 1 Register (mitctl0/1)](timers.md#internal-timer-control-0-1-register-mitctl0-1)).\n\nAll registers are cleared at reset unless otherwise noted.\nAfter reset, the counters start incrementing the next clock cycle if the increment conditions are met.\nAll registers can be read as well as written at any time.\nThe `mitcnt0/1` and `mitb0/1` registers may be written to any 32-bit value.\nIf the conditions to increment are met, the corresponding counter `mitcnt0/1` increments every clock cycle.\n\nCascade mode (see [Internal Timer Control 0 / 1 Register (mitctl0/1)](timers.md#internal-timer-control-0-1-register-mitctl0-1)) links the two counters together.\nThe `mitcnt1` register is only incremented when the conditions to increment `mitcnt1` are met and the `mitcnt0` register is greater than or equal to the bound in its `mitb0` register.\n\nFor each timer, a local interrupt (see [](timers.md#internal-timer-local-interrupts)) is triggered when that counter is at or above its bound.\nWhen a counter is at or above its bound, it gets cleared the next clock cycle (i.e., the interrupt condition is not sticky).\n\n:::{note}\nIf the core is in Debug Mode and being single-stepped, it may take multiple clock cycles to execute a single instruction. If the conditions to increment are met, the counter increments for every clock cycle it takes to execute a single instruction. Therefore, every executed single-stepped instruction in Debug Mode may result in multiple counter increments.\n:::\n\n:::{note}\nIf the core is in the Debug Mode's Halted (i.e., db-halt) state, an internal timer interrupt does not transition the core back to the Active (i.e., Running) state.\n:::\n\n## Internal Timer Local Interrupts\n\nLocal-to-the-core interrupts for internal timer 0 and 1 have pending [^fn-timers-1] (*mitip0/1*) and enable (*mitie0/1*) bits in bit positions 29 (for internal timer 0) and 28 (for internal timer 1) of the standard RISC-V `mip` (see {numref}`tab-machine-interrupt-pending-register`) and `mie` (see {numref}`tab-machine-interrupt-enable-register`) registers, respectively.\nThe priority is lower than the RISC-V External, Software, and Timer interrupts (see {numref}`tab-veer-el2-platform-specific-and-std-risc-v-interrupt-priorities`).\nThe internal timer 0 and 1 local interrupts have an mcause value of 0x8000_001D (for internal timer 0) and 0x8000_001C (for internal timer 1) (see {numref}`tab-machine-cause-register`).\n\n:::{note}\nIf both internal timer interrupts occur in the same cycle, internal timer 0's interrupt has higher priority than internal timer 1's interrupt.\n:::\n\n:::{note}\nA common interrupt service routine may be used for both interrupts.\nThe `mcause` register value differentiates the two local interrupts.\n:::\n\n[^fn-timers-1]: Since internal timer interrupts are not latched (i.e., not “sticky”) and these local interrupts are only signaled for one core clock cycle, it is unlikely that they are detected by firmware in the `mip` register.\n\n## Control/Status Registers\n\nA summary of platform-specific internal timer control/status registers in CSR space:\n\n- [Internal Timer Counter 0 / 1 Register (mitcnt0/1)](timers.md#internal-timer-counter-0-1-register-mitcnt0-1)\n- [Internal Timer Bound 0 / 1 Register (mitb0/1)](timers.md#internal-timer-bound-0-1-register-mitb0-1)\n- [Internal Timer Control 0 / 1 Register (mitctl0/1)](timers.md#internal-timer-control-0-1-register-mitctl0-1)\n\nAll reserved and unused bits in these control/status registers must be hardwired to '0'.\nUnless otherwise noted, all read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.\n\n### Internal Timer Counter 0 / 1 Register (mitcnt0/1)\n\nThe `mitcnt0` and `mitcnt1` registers are the counters of the internal timer 0 and 1, respectively.\n\nThe conditions to increment a counter are:\n\n- The *enable* bit in the corresponding mitctl0/1 register is '1',\n- if the core is in Sleep (i.e., pmu/fw-halt) state, the *halt_en* bit in the corresponding `mitctl0/1` register is '1',\n- if the core is paused, the *pause_en* bit in the corresponding `mitctl0/1` register is '1', and\n- the core is not in Debug Mode, except while executing a single-stepped instruction.\n\nA counter is cleared if its value is greater than or equal to its corresponding mitb0/1 register.\n\n:::{note}\nIf a write to the `mitcnt0/1` register is committed in the same clock cycle as the timer interrupt condition is met, the internal timer local interrupt is triggered, if enabled, but the counter is not cleared in this case. Instead, the counter is set to the written value.\n:::\n\nThese registers are mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Internal Timer Counter 0 / 1 Register (mitcnt0/1, at CSR 0x7D2 / 0x7D5)\n:name: tab-internal-timer-counter-register\n:header-rows: 1\n:align: left\n\n* - Field\n - Bits\n - Description\n - Access\n - Reset\n* - count\n - 31:0\n - Counter\n - R/W\n - 0\n:::\n\n### Internal Timer Bound 0 / 1 Register (mitb0/1)\n\nThe `mitb0` and `mitb1` registers hold the upper bounds of the internal timer 0 and 1, respectively.\n\nThese registers are mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Internal Timer Bound 0 / 1 Register (mitb0/1, at CSR 0x7D3 / 0x7D6)\n:name: tab-internal-timer-bound-register\n:header-rows: 1\n:align: left\n\n* - Field\n - Bits\n - Description\n - Access\n - Reset\n* - bound\n - 31:0\n - Bound\n - R/W\n - 0xFFFF_FFFF\n:::\n\n### Internal Timer Control 0 / 1 Register (mitctl0/1)\n\nThe `mitctl0` and `mitctl1` registers provide the control bits of the internal timer 0 and 1, respectively.\n\n:::{note}\nWhen in cascade mode, it is highly recommended to program the enable, *halt_en*, and *pause_en* control bits of the `mitctl1` register the same as the `mitctl0` register.\n:::\n\nThese registers are mapped to the non-standard read/write CSR address space.\n\n:::{list-table} Internal Timer Control 0 / 1 Register (mitctl0/1, at CSR 0x7D4 / 0x7D7)\n:name: tab-internal-timer-control-register\n:header-rows: 1\n:align: left\n\n* - Field\n - Bits\n - Description\n - Access\n - Reset\n* - Reserved\n - 31:4\n - Reserved\n - R\n - 0\n* - cascade **(mitctl1 only)**\n - 3\n - Cascade mode:\n - 0: Disable cascading (i.e., both internal timers operate independently) (default)\n - 1: Enable cascading (i.e., internal timer 0 and 1 are combined into a single 64-bit timer)\n - R/W\n - 0\n* - pause_en\n - 2\n - Enable/disable incrementing timer counter while executing PAUSE:\n - 0: Disable incrementing (default)\n - 1: Enable incrementing \n \n **Note:** If ‘1’ and the core is pausing (see [](power.md#core-pause-control-register-mcpc)), an internal timer interrupt terminates PAUSE and regular execution is resumed.\n - R/W\n - 0\n* - halt_en\n - 1\n - Enable/disable incrementing timer counter while in Sleep (i.e., pmu/fw- halt) state:\n - 0: Disable incrementing (default)\n - 1: Enable incrementing \n \n **Note:** If ‘1’ and the core is in Sleep (i.e., pmu/fw-halt) state, an internal timer interrupt transitions the core back to the Active (i.e., Running) state and regular execution is resumed.\n - R/W\n - 0\n* - enable\n - 0\n - Enable/disable incrementing timer counter:\n - 0: Disable incrementing\n - 1: Enable incrementing (default)\n - R/W\n - 1\n:::\n" }, { "path": "docs/source/tock.md", "content": "# Running Tock OS\n\nThis chapter describes the steps necessary to build a [Tock OS](https://github.com/tock/tock) application for the VeeR EL2 core, along with instructions for running it in simulation using [Verilator](https://github.com/verilator/verilator).\n\n## Prerequisites\n\nInstall build dependencies:\n\n```\napt install curl make build-essential gcc-riscv64-unknown-elf wget unzip python3-pip\n```\n\nTo compile Tock, you need a Rust toolchain installer called `rustup`:\n\n```\ncurl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh\n```\n\nFor detailed information on installing Tock OS, refer to the project's [documentation](https://book.tockos.org/).\n\n## Fetching sources\n\n```\ngit clone https://github.com/tock/tock.git\ncd tock\n```\n\n## Running simulation in Verilator\n\nIn order to compile Tock OS and start simulation, run:\n\n```\nmake -C boards/veer_el2_sim sim\n```\n\nThe expected output is:\n\n```\nVerilatorTB: Start of sim\nmem_signature_begin = 00000000\nmem_signature_end = 00000000\nmem_mailbox = D0580000\nVeeR EL2 initialisation complete.\nEntering main loop.\n```\n\n## Running simulation in Verilator with applications\n\n### Building Tock\n\nIn order to compile Tock, run:\n\n```\nmake -C boards/veer_el2_sim\n```\n\n### Building an application\n\n```\ngit clone https://github.com/tock/libtock-c.git\nmake -C libtock-c/examples/c_hello -j$(nproc)\n```\n\n### Providing a verilog file for simulation\n\nThe testbench for Verilator requires a single file with a program (`program.hex`), so it's necessary to combine the kernel and applications into a single binary first.\n\nYou can use Tockloader to create a binary file representing flash with the kernel, and then install the application:\n\n```\ntockloader flash --board veer_el2_sim --flash-file ./veer_el2_sim.bin --address 0x20000000 ./target/riscv32imc-unknown-none-elf/release/veer_el2_sim.bin\ntockloader install --board veer_el2_sim --arch rv32imc --flash-file ./veer_el2_sim.bin libtock-c/examples/c_hello/build/c_hello.tab\nriscv64-unknown-elf-objcopy --change-addresses 0x20000000 -I binary -O verilog veer_el2_sim.bin program.hex\n```\n\nNow `program.hex` is ready for use in simulation.\n\n### Starting simulation in Verilator\n\nClone the Cores-VeeR-EL2 repository:\n\n```\ngit clone https://github.com/chipsalliance/Cores-VeeR-EL2.git\ncd Cores-VeeR-EL2\ngit switch --detach da1042557\n```\n\nIncrease the maximum number of cycles in simulation:\n\n```\nsed -i 's/parameter MAX_CYCLES = 2_000_000;/parameter MAX_CYCLES = 10_000_000;/g' testbench/tb_top.sv\n```\n\nYou can build a testbench using these commands:\n\n```\nexport RV_ROOT=$(pwd)\nmake -C tools CONF_PARAMS='-set build-axi4 -set user_mode=1 -set reset_vec=0x20000000' verilator-build\n```\n\nMake sure the program you want to run is placed in the current working directory and named `program.hex`:\n\n```\ncp ../program.hex .\n```\n\nIn order to start the simulation, run:\n\n```\n./tools/obj_dir/Vtb_top\n```\n\nThe output should look like this:\n\n```\nVerilatorTB: Start of sim\n\nmem_signature_begin = 00000000\nmem_signature_end = 00000000\nmem_mailbox = D0580000\nVeeR EL2 initialisation complete.\nEntering main loop.\nHello World!\n```\n\nThe execution trace will be located in `exec.log`.\n" }, { "path": "docs/source/user-mode.md", "content": "# User Mode\n\nOriginally, VeeR EL2 only implemented machine mode, and user mode support was added for the Caliptra project.\nBy default the VeeR EL2 Core is configured in machine mode only, so to enable user mode, use the `-set` option in [the config script](../../configs/veer.config):\n\n```\nveer.config -set=user_mode=1\n```\n\nWith this option enabled, the *RV_USER_MODE* macro is defined.\nAll code related to user mode is guarded by *ifdef RV_USER_MODE* / *endif* blocks.\n\n## Machine ISA Register (misa)\n\nThe read-only `misa` register provides information about features and instruction sets supported by the core.\nIn the user mode configuration, the U bit (20) is set.\n\n## Machine Status Register (mstatus)\n\nThe `mstatus` register is extended with the following fields:\n\n- *MPP* - 2-bit wide field - stores the previous core operating mode after entering an exception handler. It is implemented with a single FF (permissible if supervisor mode is not present in the design). The FF stores an inverted value, so that upon core reset, the field indicates machine mode (*2'b11*)\n- *MPEV* - allows temporarily changing the effective privilege mode for load and store instructions\n\n## Machine Environment Configuration Registers (menvcfg,menvcfgh)\n\nThe `menvcfg` and `menvcfgh` registers control the behavior of *FENCE* instruction flavors and contain bits relevant to the Sstc, Zicboz and Zicbom extensions.\nNone of these extensions are supported by the VeeR EL2 core and the core is in-order, so this register pair is read-only and all-zero.\n\n## User Mode Performance Counters (cycle, cycleh, instret, instreth)\n\nIn order to enable performance monitoring in user mode, unprivileged shadow copies of `mcycle` and `minstret` registers are implemented: `cycle` and `instret`.\nThese are read-only registers accessible from user mode.\nAccess to the shadow copies can be restricted by the `mcounteren` CSR.\nThe `cycleh` and `instreth` registers are upper 32-bits of the `cycle` and `instret` registers, respectively.\n\n## Machine Counter-Enable Register (mcounteren)\n\nThe `mcounteren` register controls access to the user mode shadow copies of the performance counters.\nOnly software running in machine mode can change the `mcounteren` register, so that it can grant/deny permission to specific counters for user mode applications.\n\n## Machine Security Configuration Register (mseccfg, mseccfgh)\n\nThe `mseccfg` and `mseccfgh` registers control PMP's behavior when Smepmp is enabled.\nThe *RLB*, *MMWP* and *MML* bits are implemented, whereas others are read-only zero.\n\n## Privilege Mode Transitions and Exception Handling\n\nThe VeeR EL2 core only implements machine and user mode, so only 2 mode transitions are possible:\n\n- When `mret` is executed, the operating mode is changed to the value of the *mstatus.MPP* field.\n- When an exception is entered, the core enters machine mode.\n\nWhen the core enters a trap, it immediately switches mode to machine and the pipeline is flushed.\n\nThe introduction of user mode adds 2 new *mcause* codes for a trap caused by the *ECALL* instruction:\n\n- 11 (0xb) for *ECALL.M*, if ECALL is executed in machine mode\n- 8 (0x8) for *ECALL.U*, if ECALL is executed in user mode\n\n## PMP Enhancements for Memory Access and Execution Prevention on Machine Mode\n\nDocument [[6]](intro.md#ref-6) defines an extension to PMP's behavior.\n\nSmepmp (extended PMP) support is enabled with the `-set=smepmp=1` option:\n\n```\nveer.config -set=user_mode=1 -set=smepmp=1\n```\n\nWhen the flag is set, the *RV_SMEPMP* macro is defined.\nThe Smepmp extension can only be used together with the user mode configuration.\n" }, { "path": "docs/source/verification.md", "content": "# Verification\n\nThis chapter documents verification of the VeeR EL2 Core and coverage data collection, including RTL-level tests designed to exercise parts of the core's logic, software execution tests, randomized code generator tests, as well as verification coverage.\n\nTests listed in this chapter are run in [Continuous Integration pipelines](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/.github/workflows) of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2) via GitHub Actions.\n\n## RTL-level tests\n\nVerification of the VeeR EL2 Core includes an RTL test suite created to exercise details of the core's internal architecture.\nThese tests complement the software execution tests described in [later section of this chapter](#software-execution-tests).\n\nRTL-level tests include block-level as well as top-level tests developed for the VeeR EL2 Core:\n* Block-level tests are located in the [`verification/block` directory](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/verification/block) of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2).\n* Top-level tests are located in the [`verification/top` directory](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/verification/top) of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2).\n\n### Cocotb tests\n\nThe main group of RTL tests were implemented using [cocotb](https://www.cocotb.org/), a popular co-simulation testbench library for Python, allowing for re-use of the extensive Python testing ecosystem for design verification.\n\nThe test files are located in the [`verification/block/`](https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/verification/block/) directory of the [`Cores-VeeR-EL2 repository`](https://github.com/chipsalliance/Cores-VeeR-EL2/).\n\nThe verification environment is extended by a PyUVM (Universal Verification Methodology implemented in Python instead of SystemVerilog) test with a corresponding CI workflow.\nIt implements a basic PyUVM structure to test the core's behavior when interrupt pins are stimulated.\n\n### UVM verification\n\nUVM tests are run as the `Test-UVM` job in the CI pipelines of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2).\nThe test files are located in the [`testbench/uvm` directory](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/testbench/uvm) of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2).\n\n## Software execution tests\n\n### Regression tests\n\nRegression tests are run as the `Test-Regression` job in the CI pipelines of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2).\n\nRegression testing involves execution of rudimentary software that was executed correctly on previous runs.\nThe regression test executes `.hex` files of the following pieces of software:\n\n* A `hello_world` program\n* A Dhrystone benchmark program\n* A Coremark benchmark program\n\nRegression tests include verification of privilege mode switching.\nThe test files are located in the [`testbench/tests/modesw` directory](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/testbench/tests/modesw) of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2) and described in more detail in the [README file](https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/testbench/tests/modesw/README.md).\n\n### Renode tests\n\n[Renode](https://renode.io/) is a deterministic simulation framework used to verify proper software execution.\nThe tests are defined in the [`testbench/tests` directory](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/testbench/tests) of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2).\n\nRenode uses [Robot Framework](https://robotframework.org/), an open source automation framework for test automation and robotic process automation (RPA).\nA testing script to execute test binaries is defined in the [`veer.robot` file](https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/tools/renode/veer.robot).\n\nFor detailed information regarding verification of the VeeR EL2 core with Renode, refer to the [VeeR EL2 Support in Renode README](https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/tools/renode/README.md).\n\n### RISCOF Verification\n\n[RISCOF](https://riscof.readthedocs.io/en/stable/index.html) is a RISC-V core test framework.\nIt uses [official architectural assembly test programs](https://github.com/riscv-non-isa/riscv-arch-test) where the core memory state is compared against a reference.\nThe comparison happens between the simulated core under test and a reference ISS, similar to [tests with RISCV-DV](#riscv-dv-verification) described below.\n\nThe RISCOF framework exercises the VeeR core with tests that use the Spike ISS and Verilator.\nLike with RISCV-DV, a mismatch in memory signature comparison is reported as a CI failure.\n\nThe compared memory region is known as the memory signature.\nIts boundaries are defined by special symbols defined in each test program.\nIt is the responsibility of the simulator / ISS to dump the memory signature for comparison by RISCOF.\n\nFor more detailed information about verification of the VeeR EL2 core with RISCOF, refer to the [README](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/tools/riscof).\n\n#### Adaptation of VeeR simulation and testbench to RISCOF\n\nAdaptation of VeeR for RISCOF required implementing the memory signature dump.\nThanks to the use of Verilator it was possible to automatically load and parse the symbol map extracted from the binary ELF file and inject signature boundary addresses to the RTL simulation.\nThe simulation executable accepts the `--symbols` argument which specifies the symbol map file obtained using the `nm` utility.\nThe addresses can also be provided manually via the `--mem-signature` argument as two hexadecimal numbers.\n\nThe memory dump itself is implemented as a SystemVerilog task called from the RTL code right before the simulation ends.\nThe output file name is fixed to `veer.signature`.\nThe task automatically assures access to the correct memory - data is loaded from DCCM by default.\nOtherwise, it is taken from the generic RAM present in the testbench.\nWhen no signature range is defined, the dump is not written.\n\n#### RISCOF model plugin\n\nRISCOF uses Python plugins to interface with simulated cores and ISSs.\nThe task of a plugin is to build and link assembly test programs in a way suitable for core / ISS use and to run the simulation.\nThe plugin may also provide dedicated code snippets used by test programs to communicate with the simulation (eg. signal program end).\nCurrently plugins are available for the Spike ISS and the SAIL ISS.\nSince every RTL simulation framework for a core is different, it requires a dedicated plugin.\n\nThe VeeR plugin, located in the [`/tools/riscof/veer`](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/tools/riscof/veer) directory of this repository, performs the following tasks:\n\n* Code compilation and linking\n* Symbol dump (to get the memory signature address range)\n* Simulation run\n* Result collection (moving / renaming the output memory signature dump file)\n\nThe VeeR RTL needs to be \"Verilated\" upfront as the plugin assumes that the simulation binary is already present.\n\n## RISCV-DV verification\n\n[RISCV-DV](https://github.com/chipsalliance/riscv-dv) is a verification framework (originally from Google, now also in CHIPS Alliance) designed to test and (co-)verify RISC-V CPU cores.\n\nRISCV-DV tests are run as the `Test-RISCV-DV` job in the CI pipelines of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2).\n\nPre-generated RISCV-DV test programs for fallback in case of failure in generation in CI pipelines are stored in the [`.github/assets/riscv-dv` directory](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/.github/assets/riscv_dv).\n\nThe framework generates random instruction chains to exercise certain core features and relies on the [Universal Verification Methodology (UVM)](https://www.accellera.org/community/uvm) for code generation.\nThese instructions are then simultaneously executed by the core (RTL simulation) and by a reference RISC-V ISS (instruction set simulator), for example [Spike](https://github.com/riscv-software-src/riscv-isa-sim).\nThe core states of both are then compared and an error is reported in case of a mismatch.\n\nRISCV-DV tests are run as the `Test-RISCV-DV` job in the CI pipelines of the [`cores-veer-el2` repository](https://github.com/chipsalliance/Cores-VeeR-EL2).\nThis job is responsible for running the RISCV-DV test suite on the VeeR core, downloading Renode and building the VeeR ISS.\n\nA mismatch between an ISS trace and the RTL trace reported by RISCV-DV framework immediately triggers a CI error.\n\n### RISCV-DV Test flow\n\nThe RISCV-DV test flow for the VeeR EL2 Core looks as follows:\n\n* Generate a program using a `RISCV-DV` generator\n* Run the program in a RISC-V ISS, collect the trace\n* Run the program inside a simulation of the VeeR EL2 core using [Verilator](https://www.veripool.org/verilator/) and collect the trace\n* Compare both execution trace files\n* If no mismatches are found, the test is successful\n\n{numref}`riscv-dv-flow` below illustrates this flow.\n\n:::{figure-md} riscv-dv-flow\n![riscv-dv-flow](img/riscv-dv-flow.png)\n\nRISCV-DV flow\n:::\n\nFor more detailed information about verification of the VeeR EL2 core with RISCV-DV, refer to the [README](https://github.com/chipsalliance/Cores-VeeR-EL2/tree/main/tools/riscv-dv).\n\nIn a physical design, external stimulus, e.g. from interrupt source or debugging requests, causes relevant CSRs to be updated automatically, which is not always the case for tests relying solely on generated streams of instructions.\nIn the future, tests to verify these features will be implemented using the [RISCV-DV handshaking mechanism](https://github.com/chipsalliance/riscv-dv/blob/master/docs/source/handshake.rst), a feature put in place specifically to update the core's internal state properly.\n\n### Current implementation\n\nSince RISCV-DV does not provide a generic way of simulating RISC-V cores at RTL level, this implementation runs the existing testbench for VeeR EL2 in Verilator.\nRISCV-DV requires execution traces in its own standardized format, so we developed a Python script which parses the VeeR EL2 execution log and converts it to the [CSV format](https://htmlpreview.github.io/?https://github.com/google/riscv-dv/blob/master/docs/build/singlehtml/index.html#trace-csv-format) accepted by RISCV-DV.\n\nThe end-to-end flow is implemented by the Makefile in `tools/riscv-dv`.\nThe RISCV-DV `run.py` script is used for random code generation, compilation and ISS execution.\nA set of Makefile rules implements building the verilated testbench, running it, converting trace logs and trace comparison.\nThe comparison itself is done by `instr_trace_compare.py` in RISCV-DV.\n\nThe flow currently supports three ISSs:\n\n* [Spike](https://github.com/riscv-software-src/riscv-isa-sim)\n* [Renode](https://renode.io/)\n\nThe CI workflow for RISCV-DV builds or downloads the prerequisites (Verilator, Spike, Renode) and invokes the test flow.\nA failure of any of RISCV-DV tests is reported as CI failure.\n\n### Renode integration\n\n[Renode](https://renode.io/) is Antmicro's open source development framework which allows debugging and testing unmodified embedded software on your PC - from bare System-on-Chips, through complete devices, to multi-node systems.\n\nAs a part of the the project, we extended the RISCV-DV framework [with Renode ISS support](https://github.com/chipsalliance/riscv-dv/pull/935).\nThe work also included defining a virtual Renode platform for VeeR EL2, executing RISCV-DV pseudo-random programs on it and collecting execution trace logs.\nBasic level VeeR EL2 support in Renode opens up the potential to simulate the Caliptra RoT as well as the RoT in the context of a larger SoC in conjunction with Renode's support for e.g. ARM and RISC-V cores and peripherals or OpenTitan peripherals (some of which are used in Caliptra)\n\n## Verification coverage\n\nFor each of the tests described in this chapter, data is collected and processed to determine verification coverage.\n\n### Coverage analysis\n\nTo verify whether all parts of a design have been tested, you can get coverage reports from simulation runs which inform about a percentage of possible design states that were simulated.\nYou can then use this information to prepare new testing scenarios that test previously untested design states.\n\nResults for verification coverage of the entire design as well as its parts are available in the [VeeR EL2 coverage dashboard](https://chipsalliance.github.io/Cores-VeeR-EL2/html/main.html).\nThe results are updated with each Pull Request, as visible in the [Active pull request list](https://chipsalliance.github.io/Cores-VeeR-EL2/html/dev.html).\nData is only available for open Pull Requests and is removed once a Pull Request is closed or merged.\n\n### Coverage analysis with open source tools\n\nVerilator supports certain method of test [coverage analysis](https://veripool.org/guide/latest/simulating.html#coverage-analysis).\nThere are three ways in which Verilator collects coverage data:\n\n* Line coverage\n\n Verilator automatically counts changes to the RTL code flow at all possible branch points.\n\n* Toggle coverage\n\n Automatic toggle count for each signal. Does not apply to certain signal types as described in [Verilator's documentation](https://veripool.org/guide/latest/simulating.html#coverage-analysis).\n\n* Functional coverage\n\n Verilator automatically counts events defined by the `cover property`, which are implemented in the source code.\n\nTo enable coverage collection with Verilator, simply add the following lines to the C++ testbench:\n\n```\n // Write coverage data\n#if VM_COVERAGE\n Verilated::threadContextp()->coveragep()->write(\"coverage.dat\");\n#endif\n```\nThe `genhtml` utility from the `lcov` package is used to convert the data collected from the verification into `.html` files present it in the form of [the VeeR EL2 coverage dashboard](https://chipsalliance.github.io/Cores-VeeR-EL2/html/main/coverage_dashboard/all/index.html).\n\n### Identification of signals without coverage\n\nThe recommended way to identify signals with low coverage is to use the annotation mechanism.\nThe annotation mechanism is provided by the [verilator_coverage](https://github.com/verilator/verilator/blob/master/bin/verilator_coverage) tool and is capable of writing source files with annotations next to each coverage point.\n\nCoverage reports in the form of `.dat` files can be combined using the following command:\n\n```\nverilator_coverage coverage_test_*.dat --write combined.dat\n```\n\nIn order to annotate the coverage results back to the source files, run the command:\n\n```\nverilator_coverage coverage_test.dat --annotate \n```\n\n```{note}\n`annotate-all`, `annotate-min` and `annotate-points` can be used to modify the behavior of the `annotate` option.\nFor more details, see [Verilator Argument Reference](https://verilator.org/guide/latest/exe_verilator_coverage.html)\n```\n\nThe result of the command should be a copy of the source files used in the simulation, located in the output directory of choice.\nIn the annotated source files, you will find that annotations are placed at the beginning of lines, e.g.:\n\n```\n 153724 input logic en;\n %000000 input logic scan_mode;\n```\n\nInterpretations of these results are placed inline:\n\n```\n 153724 input logic en; // there were 153724 coverage hits\n %000000 input logic scan_mode; // signal never toggled, so line starts with '%'\n```\n\nIf a single line contains more than one signal definition (or a multi-bit signal), it may be useful to run with the `annotate-points` argument, so that the annotation resembles:\n\n```\n 153888 input logic SE, EN, CK,\n -000000 point: comment=SE\n +153888 point: comment=EN\n +2636790 point: comment=CK\n```\n\nIn this mode, '+' and '-' are used to indicate whether a coverage point is above or below the threshold.\n\nTo read more about coverage in Verilator, see:\n* [Coverage analysis](https://verilator.org/guide/latest/simulating.html#coverage-analysis)\n* [verilator_coverage executable documentation](https://verilator.org/guide/latest/exe_verilator_coverage.html)\n" }, { "path": "docs/update_styles.sh", "content": "#!/bin/bash\n\nSELF_DIR=\"$(dirname $(readlink -f ${BASH_SOURCE[0]}))\"\ncheck_args_count(){\n # Check argument count function is meant to be used to check if\n # the number of received arguments is equal to the expected.\n # If they are unequal, the function returns with error\n # Args:\n # argc_got - Number of received arguments, e.g.: $#\n # argc_expected - Number of expected arguments, e.g.: 2\n argc_got=$1\n argc_expected=$2\n if [ ${argc_got} -ne ${argc_expected} ]; then\n echo -e \"${COLOR_WHITE}Expected ${argc_expected} arguments, but received ${argc_got} ${COLOR_RED}FAIL${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE}Caller:${COLOR_CLEAR}\" `caller`\n exit 1\n fi\n}\n\nupdate_styles(){\n # Update styles for Sphinx theme\n # Args:\n # BUILDDIR - path to where the webpage is made\n BUILD_DIR=$1\n echo -e \"${COLOR_WHITE}========== Update styles =========${COLOR_CLEAR}\"\n echo -e \"${COLOR_WHITE} BUILD_DIR = ${BUILD_DIR}${COLOR_CLEAR}\"\n\n # Replace styles for sphinx build\n cp dashboard-styles/main.css ${BUILD_DIR}/html/_static/\n\n # Add CHIPs logo\n cp dashboard-styles/assets/chips-alliance-logo-mono.svg ${BUILD_DIR}/html/_static/white.svg\n\n # Replace undesired CSS and progress bar sprites with desired style for LCOV reports\n copy_files(){\n check_args_count $# 2\n SOURCE=$1\n SEARCH=$2\n FILES=`find ${BUILD_DIR}/ -name ${SEARCH}`\n\n for FILE in ${FILES}; do\n echo \"Copy ${SOURCE} to ${FILE}\"\n cp $SOURCE $FILE\n done\n }\n\n CHIPS_GCOV_CSS=dashboard-styles/gcov.css\n AMBER=dashboard-styles/assets/amber.png\n RUBY=dashboard-styles/assets/ruby.png\n SNOW=dashboard-styles/assets/snow.png\n EMERALD=dashboard-styles/assets/emerald.png\n\n for ASSET in $CHIPS_GCOV_CSS $AMBER $RUBY $SNOW $EMERALD; do\n copy_files $ASSET $(basename \"$ASSET\")\n done\n echo -e \"${COLOR_WHITE}Update styles ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}\"\n}\n\ncheck_args_count $# 1\nupdate_styles \"$@\"\n" }, { "path": "release-notes.md", "content": "# Release notes\n\n## 2.0\n\n* Extended the core with support for RISC-V User privilege level\n* Extended the core with support for PMP and ePMP functionalities\n* ICache memory is now exported from the main core and can be provided at SoC integration level\n* Many smaller changes and bugfixes\n* Extended the repository with an array of tests and CI covering various core configurations\n\n## 1.4\n\n* Upgraded bit-manipulation support for Zba, Zbb, Zbc, Zbe, Zbf, Zbp, Zbr, Zbs to `0.94` draft spec.\n * Zba, Zbb, Zbc and Zbs are enabled by default. Use `-set=bitmanip_zb*=1` to enable other sub-extensions.\n* Simulation performance improvement coding style changes in branch predictor and PIC\n* Several corner case and exotic bug fixes :\n * MPC run ack timing\n * Force halt mechanism and MPC\n * Store data collision with DCCM DMA error when address is 0x0\n * RAW hazard on mtdata1\n * Errors on DMA access could leak into Dbg abstract cmd ocurring at same time\n * Icache parity error and branch error collision leading to fwd progress issue\n* Fixed linter warning for async reset\n \n\n## 1.3\n\n* Multiple debug module compliance deviations and bugs reported by Codasip\n* Updates to debug module to level compliance to version 0.13.2 of debug spec\n* Trigger chaining compliance fixes\n* Power optimization improvements and clock gating improvements\n * Significantly lower power in sleep as well as normal operation.\n* Enhanced debug memory abstract command to access internal as well as external memories\n* Added bit-manipulation support for Zba, Zbb, Zbc, Zbe, Zbf, Zbp, Zbr, Zbs (Jan 29, 2020 Draft spec).\n * Zbs and Zbb are enabled by default. Use `-set=bitmanip_zb*=1` to enable other sub-extensions.\n* Enhancements and additional configurations options for a faster divider\n* JTAG bypass register intial state issue fixed\n* New branch predictor fully-associative option with 8,16,32 entries.\n* Corner case bugs fixes related to \n * Bus protocol corner cases (ahb)\n * Fetch bus error recording improved accuracy\n * Branch predictor pathological timing cases fixes\n * Fast interrupt with DCCM ECC errors priority bug\n * MPC & PMU protocol cleanup\n * Performance counter bug fixes (counting branch prediction events)\n * Triggers and ECC correctable error overflows bug fixes\n\n* Demo test-bench updates\n * Handling bigger test sizes using associative arrays in external memory slaves, \n * simplified test building process and CCM loading functions (only program.hex is generated, no data.hex)\n * Improved Makefile and example tests (see README)\n * Generating link.ld with veer.config\n \n## 1.2\n\n* Modified MSCAUSE encoding to be consistent with current internal specification\n* Added internal timers\n\n## 1.1\n\n* Several bug fixes in debug module\n * Added new `dbg_rst_l` input for system wide reset to debug module. If debug module operation during core reset is not needed, this can be connected to `rst_l`.\n* Trace port width adjusted\n* Demo testbench has a synthesizable bridge to allow accessing the ICCM with load/stores via the DMA port. (*This only works with the AXI4 build*)\n\n## 1.0\n\nInitial release\n" }, { "path": "requirements.txt", "content": "# Build and Workflow Tools\nnox\nmeson\n\n# Linters\nisort\nblack\nflake8\n\n# Documentation\nSphinx>=8.0.2,<9\n# Sphinx utilities\nhttps://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip\n\n# Verification - Core\n# Note: Custom cocotb might be required for some flows\n# ./third_party/cocotb\ncocotb==1.8.0\ncocotb-bus==0.2.1\ncocotb-coverage==1.1.0\ncocotb-test==0.2.4\npyuvm==2.9.1\n\n# Verification - Testing & Reporting\npytest==9.0.3\npytest-html==3.2.0\npytest-timeout==2.1.0\npytest-md==0.2.0\n\n# Scientific/Math (used in some block tests)\nscipy==1.13.1\n" }, { "path": "testbench/ahb_lite_2to1_mux.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2024 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n\n// -------------------------------------------------------------\n// AHB Lite 2:1 Mux\n// -------------------------------------------------------------\n\nmodule ahb_lite_2to1_mux #(\n parameter AHB_LITE_ADDR_WIDTH = 32,\n parameter AHB_LITE_DATA_WIDTH = 32,\n parameter AHB_NO_OPT = 0\n) (\n // ---------------------------------------\n // Global clock/reset\n // ---------------------------------------\n input logic hclk,\n input logic hreset_n,\n input logic force_bus_idle,\n\n // ---------------------------------------\n // From Initiator 0\n // ---------------------------------------\n input logic hsel_i_0,\n input logic [AHB_LITE_ADDR_WIDTH-1:0] haddr_i_0,\n input logic [AHB_LITE_DATA_WIDTH-1:0] hwdata_i_0,\n input logic hwrite_i_0,\n input logic [1:0] htrans_i_0, \n input logic [2:0] hsize_i_0,\n input logic hready_i_0,\n\n output logic hresp_o_0,\n output logic hready_o_0,\n output logic [AHB_LITE_DATA_WIDTH-1:0] hrdata_o_0,\n\n // ---------------------------------------\n // From Initiator 1\n // ---------------------------------------\n input logic hsel_i_1,\n input logic [AHB_LITE_ADDR_WIDTH-1:0] haddr_i_1,\n input logic [AHB_LITE_DATA_WIDTH-1:0] hwdata_i_1,\n input logic hwrite_i_1,\n input logic [1:0] htrans_i_1, \n input logic [2:0] hsize_i_1,\n input logic hready_i_1,\n\n output logic hresp_o_1,\n output logic hready_o_1,\n output logic [AHB_LITE_DATA_WIDTH-1:0] hrdata_o_1,\n\n // ---------------------------------------\n // To Responder Interface Port\n // ---------------------------------------\n input logic hresp_i,\n input logic [AHB_LITE_DATA_WIDTH-1:0] hrdata_i, \n input logic hreadyout_i,\n\n output logic [AHB_LITE_ADDR_WIDTH-1:0] haddr_o, \n output logic [AHB_LITE_DATA_WIDTH-1:0] hwdata_o, \n output logic hsel_o, \n output logic hwrite_o, \n output logic hready_o,\n output logic [1:0] htrans_o,\n output logic [2:0] hsize_o\n\n);\n\n//This is a fixed priority 2:1 mux for AHB-Lite protocol\n//Initiator 0 always takes priority\n\nlogic initiator0_address_ph, initiator1_address_ph;\nlogic initiator0_data_ph_nq, initiator1_data_ph_nq;\nlogic initiator0_data_ph, initiator1_data_ph;\nlogic initiator0_pend_addr_ph_nq, initiator1_pend_addr_ph_nq;\nlogic initiator0_pend_addr_ph, initiator1_pend_addr_ph;\nlogic initiator0_gnt, initiator1_gnt;\nlogic [AHB_LITE_ADDR_WIDTH-1:0] initiator0_pend_haddr, initiator1_pend_haddr;\nlogic [AHB_LITE_ADDR_WIDTH-1:0] initiator0_haddr, initiator1_haddr;\nlogic [1:0] initiator0_pend_htrans, initiator1_pend_htrans;\nlogic [1:0] initiator0_htrans, initiator1_htrans;\nlogic [2:0] initiator0_pend_hsize, initiator1_pend_hsize;\nlogic [2:0] initiator0_hsize, initiator1_hsize;\nlogic initiator0_pend_hwrite, initiator1_pend_hwrite;\nlogic initiator0_hwrite, initiator1_hwrite;\n\n//Detect address phase\nalways_comb initiator0_address_ph = hsel_i_0 & hready_i_0 & htrans_i_0 inside {2'b10, 2'b11} & ~force_bus_idle;\nalways_comb initiator1_address_ph = hsel_i_1 & hready_i_1 & htrans_i_1 inside {2'b10, 2'b11} & ~force_bus_idle;\n\nalways_ff @(posedge hclk or negedge hreset_n) begin\n if (~hreset_n) begin\n initiator0_pend_haddr <= '0;\n initiator1_pend_haddr <= '0;\n initiator0_pend_htrans <= '0;\n initiator1_pend_htrans <= '0;\n initiator0_pend_hsize <= '0;\n initiator1_pend_hsize <= '0;\n initiator0_pend_hwrite <= '0;\n initiator1_pend_hwrite <= '0;\n initiator0_pend_addr_ph_nq <= '0;\n initiator1_pend_addr_ph_nq <= '0;\n initiator0_data_ph_nq <= '0;\n initiator1_data_ph_nq <= '0;\n end\n else begin\n //Capture the address during the address phase for each initiator\n initiator0_pend_haddr <= initiator0_address_ph & ~initiator0_pend_addr_ph ? haddr_i_0 : initiator0_pend_haddr;\n initiator1_pend_haddr <= initiator1_address_ph & ~initiator1_pend_addr_ph ? haddr_i_1 : initiator1_pend_haddr;\n initiator0_pend_htrans <= initiator0_address_ph & ~initiator0_pend_addr_ph ? htrans_i_0 : initiator0_pend_htrans;\n initiator1_pend_htrans <= initiator1_address_ph & ~initiator1_pend_addr_ph ? htrans_i_1 : initiator1_pend_htrans;\n initiator0_pend_hsize <= initiator0_address_ph & ~initiator0_pend_addr_ph ? hsize_i_0 : initiator0_pend_hsize;\n initiator1_pend_hsize <= initiator1_address_ph & ~initiator1_pend_addr_ph ? hsize_i_1 : initiator1_pend_hsize;\n initiator0_pend_hwrite <= initiator0_address_ph & ~initiator0_pend_addr_ph ? hwrite_i_0 : initiator0_pend_hwrite;\n initiator1_pend_hwrite <= initiator1_address_ph & ~initiator1_pend_addr_ph ? hwrite_i_1 : initiator1_pend_hwrite;\n\n //Capture pending address phase when initiators collide\n initiator0_pend_addr_ph_nq <= (initiator0_address_ph | initiator0_pend_addr_ph) & ~(hreadyout_i & initiator0_gnt);\n initiator1_pend_addr_ph_nq <= (initiator1_address_ph | initiator1_pend_addr_ph) & ~(hreadyout_i & initiator1_gnt); \n\n //Transition to data phase when endpoint accepts address phase, hold when not ready\n initiator0_data_ph_nq <= (initiator0_gnt) | (initiator0_data_ph & ~hreadyout_i);\n initiator1_data_ph_nq <= (initiator1_gnt) | (initiator1_data_ph & ~hreadyout_i);\n end\nend\n\nalways_comb initiator0_data_ph = initiator0_data_ph_nq & ~force_bus_idle;\nalways_comb initiator1_data_ph = initiator1_data_ph_nq & ~force_bus_idle;\nalways_comb initiator0_pend_addr_ph = initiator0_pend_addr_ph_nq & ~force_bus_idle;\nalways_comb initiator1_pend_addr_ph = initiator1_pend_addr_ph_nq & ~force_bus_idle;\n\nalways_comb initiator0_haddr = initiator0_pend_addr_ph ? initiator0_pend_haddr : haddr_i_0;\nalways_comb initiator0_htrans = initiator0_pend_addr_ph ? initiator0_pend_htrans : htrans_i_0;\nalways_comb initiator0_hsize = initiator0_pend_addr_ph ? initiator0_pend_hsize : hsize_i_0;\nalways_comb initiator0_hwrite = initiator0_pend_addr_ph ? initiator0_pend_hwrite : hwrite_i_0;\n\nalways_comb initiator1_haddr = initiator1_pend_addr_ph ? initiator1_pend_haddr : haddr_i_1;\nalways_comb initiator1_htrans = initiator1_pend_addr_ph ? initiator1_pend_htrans : htrans_i_1;\nalways_comb initiator1_hsize = initiator1_pend_addr_ph ? initiator1_pend_hsize : hsize_i_1;\nalways_comb initiator1_hwrite = initiator1_pend_addr_ph ? initiator1_pend_hwrite : hwrite_i_1;\n\n//Select the appropriate initiator\ngenerate\n if (AHB_NO_OPT) begin\n //no optimization, data phase must complete before driving new address phase\n //Initiator 0 gets priority\n //Stall the grant only if initiator 1 is on its data phase\n always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph) & ~initiator1_data_ph;\n\n //Initiator 1 gets through only if initiator 0 address phase isn't getting gnt, or in data phase\n always_comb initiator1_gnt = (initiator1_address_ph | initiator1_pend_addr_ph) & ~initiator0_data_ph & ~initiator0_gnt;\n end else begin\n //optimized to allow addr phase to overlap data phase, assumes no stalls\n //Initiator 0 gets priority\n //Stall the grant if initiator 1 is processing a data phase and address phase b2b\n always_comb initiator0_gnt = (initiator0_address_ph | initiator0_pend_addr_ph);\n\n //Initiator 1 gets through only if initiator 0 isn't getting granted\n always_comb initiator1_gnt = (initiator1_address_ph | initiator1_pend_addr_ph) & ~initiator0_gnt;\n end\nendgenerate\n\n//Mux the appropriate initiator and send out\n//Keep driving initiator 1 controls on data phase if init0 isn't getting a grant in that cycle\nalways_comb haddr_o = initiator1_gnt | (initiator1_data_ph & ~initiator0_gnt) ? initiator1_haddr : initiator0_haddr;\nalways_comb htrans_o = initiator1_gnt | (initiator1_data_ph & ~initiator0_gnt) ? initiator1_htrans : initiator0_htrans;\nalways_comb hsize_o = initiator1_gnt | (initiator1_data_ph & ~initiator0_gnt) ? initiator1_hsize : initiator0_hsize;\nalways_comb hwrite_o = initiator1_gnt | (initiator1_data_ph & ~initiator0_gnt) ? initiator1_hwrite : initiator0_hwrite;\nalways_comb hsel_o = initiator1_gnt | (initiator1_data_ph & ~initiator0_gnt) ? hsel_i_1 : hsel_i_0;\nalways_comb hwdata_o = initiator1_gnt | (initiator1_data_ph & ~initiator0_gnt) ? hwdata_i_1 : hwdata_i_0;\nalways_comb hready_o = initiator1_gnt | (initiator1_data_ph & ~initiator0_gnt) ? (hready_i_1 | initiator1_pend_addr_ph) : (hready_i_0 | initiator0_pend_addr_ph);\n\n//Send response to the initiator\n//Mask the ready when it's a pending address phase\n//Send the data coming from responder when selected\nalways_comb hresp_o_0 = initiator0_data_ph ? hresp_i : '0;\nalways_comb hrdata_o_0 = initiator0_data_ph ? hrdata_i : '0;\nalways_comb hready_o_0 = initiator0_data_ph ? hreadyout_i :\n initiator0_pend_addr_ph ? '0 : '1;\n\nalways_comb hresp_o_1 = initiator1_data_ph? hresp_i: '0;\nalways_comb hrdata_o_1 = initiator1_data_ph ? hrdata_i: '0;\nalways_comb hready_o_1 = initiator1_data_ph ? hreadyout_i :\n initiator1_pend_addr_ph ? '0 : '1;\n\n//Coverage\n`ifndef VERILATOR\n`ifdef FCOV\n\ncovergroup ahb_lite_2to1_mux_cov_grp @(posedge hclk iff hreset_n);\n option.per_instance = 1;\n \n init0_addr_cp: coverpoint initiator0_address_ph;\n init0_pend_addr_cp: coverpoint initiator0_pend_addr_ph;\n init0_data_cp: coverpoint initiator0_data_ph;\n init0_gnt_cp : coverpoint initiator0_gnt;\n\n init1_addr_cp: coverpoint initiator1_address_ph;\n init1_pend_addr_cp: coverpoint initiator1_pend_addr_ph;\n init1_data_cp: coverpoint initiator1_data_ph;\n init1_gnt_cp : coverpoint initiator1_gnt;\n\n init0_pend_addr_not_ready: coverpoint initiator0_pend_addr_ph & ~hreadyout_i;\n init1_pend_addr_not_ready: coverpoint initiator1_pend_addr_ph & ~hreadyout_i;\n\n init0_data_not_ready: coverpoint initiator0_data_ph & ~hreadyout_i;\n init1_data_not_ready: coverpoint initiator1_data_ph & ~hreadyout_i;\n\n init0_dataXinit1_gnt: cross init0_data_cp, init1_gnt_cp;\n init1_dataXinit0_gnt: cross init1_data_cp, init0_gnt_cp;\n\n init0_addrXpend: cross init0_addr_cp, init0_pend_addr_cp;\n init1_addrXpend: cross init1_addr_cp, init1_pend_addr_cp;\n init0Xinit1_addr: cross init0_addr_cp, init1_addr_cp;\n init0Xinit1_pend_addr: cross init0_pend_addr_cp, init1_pend_addr_cp;\n\nendgroup\n\n ahb_lite_2to1_mux_cov_grp ahb_lite_2to1_mux_cov_grp1 = new();\n\n`endif\n`endif \nendmodule\n" }, { "path": "testbench/ahb_lsu_dma_bridge.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2024 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n\n// connects LSU master (AHB) to external AXI slave and DMA slave (AHB)\nmodule ahb_lsu_dma_bridge\n#(\n TAG = 1,\n `include \"el2_param.vh\"\n)\n(\n input clk,\n input reset_l,\n\n // AHB master interface (LSU)\n input logic [31:0] m_ahb_haddr, // ahb bus address\n input logic [2:0] m_ahb_hburst, // tied to 0\n input logic m_ahb_hmastlock, // tied to 0\n input logic [3:0] m_ahb_hprot, // tied to 4'b0011\n input logic [2:0] m_ahb_hsize, // size of bus transaction (possible values 0,1,2,3)\n input logic [1:0] m_ahb_htrans, // Transaction type (possible values 0,2 only right now)\n input logic m_ahb_hwrite, // ahb bus write\n input logic [63:0] m_ahb_hwdata, // ahb bus write data\n input logic m_ahb_hsel, // this slave was selected\n input logic m_ahb_hreadyin, // previous hready was accepted or not\n output logic [63:0] m_ahb_hrdata, // ahb bus read data\n output logic m_ahb_hreadyout, // slave ready to accept transaction\n output logic m_ahb_hresp, // slave response (high indicates erro)\n\n // AHB slave interface (lmem)\n output logic s0_ahb_hsel, // ahb bus slave select\n output logic [31:0] s0_ahb_haddr, // ahb bus address\n output logic [2:0] s0_ahb_hburst, // tied to 0\n output logic s0_ahb_hmastlock, // tied to 0\n output logic [3:0] s0_ahb_hprot, // [3:1] are tied to 3'b001\n output logic [2:0] s0_ahb_hsize, // size of bus transaction (possible values 0,1,2,3)\n output logic [1:0] s0_ahb_htrans, // Transaction type (possible values 0,2 only right now)\n output logic s0_ahb_hwrite, // ahb bus write\n output logic [63:0] s0_ahb_hwdata, // ahb bus write data\n input logic [63:0] s0_ahb_hrdata, // ahb bus read data\n input logic s0_ahb_hready, // connect to veer's dma_hreadyout\n input logic s0_ahb_hresp, // slave response (high indicates erro)\n\n // AHB slave interface (dma)\n output logic s1_ahb_hsel, // ahb bus slave select\n output logic [31:0] s1_ahb_haddr, // ahb bus address\n output logic [2:0] s1_ahb_hburst, // tied to 0\n output logic s1_ahb_hmastlock, // tied to 0\n output logic [3:0] s1_ahb_hprot, // [3:1] are tied to 3'b001\n output logic [2:0] s1_ahb_hsize, // size of bus transaction (possible values 0,1,2,3)\n output logic [1:0] s1_ahb_htrans, // Transaction type (possible values 0,2 only right now)\n output logic s1_ahb_hwrite, // ahb bus write\n output logic [63:0] s1_ahb_hwdata, // ahb bus write data\n input logic [63:0] s1_ahb_hrdata, // ahb bus read data\n input logic s1_ahb_hready, // connect to veer's dma_hreadyout\n input logic s1_ahb_hresp // slave response (high indicates erro)\n);\n\nparameter ICCM_BASE = `RV_ICCM_BITS; // in LSBs\nbit[31:0] iccm_real_base_addr = `RV_ICCM_SADR ;\n\nwire bus_active;\nwire slave_select;\n\nreg slave_select_dly;\n\nassign bus_active = m_ahb_htrans inside {2'b10, 2'b11};\nassign slave_select = m_ahb_haddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];\n\nassign s0_ahb_hsel = bus_active & ~slave_select;\nassign s0_ahb_haddr = m_ahb_haddr;\nassign s0_ahb_hburst = m_ahb_hburst;\nassign s0_ahb_hmastlock = m_ahb_hmastlock;\nassign s0_ahb_hprot = m_ahb_hprot;\nassign s0_ahb_hsize = m_ahb_hsize;\nassign s0_ahb_htrans = m_ahb_htrans;\nassign s0_ahb_hwrite = m_ahb_hwrite;\nassign s0_ahb_hwdata = m_ahb_hwdata;\n\nassign s1_ahb_hsel = bus_active & slave_select;\nassign s1_ahb_haddr = m_ahb_haddr;\nassign s1_ahb_hburst = m_ahb_hburst;\nassign s1_ahb_hmastlock = m_ahb_hmastlock;\nassign s1_ahb_hprot = m_ahb_hprot;\nassign s1_ahb_hsize = m_ahb_hsize;\nassign s1_ahb_htrans = m_ahb_htrans;\nassign s1_ahb_hwrite = m_ahb_hwrite;\nassign s1_ahb_hwdata = m_ahb_hwdata;\n\nassign m_ahb_hreadyout = &{s0_ahb_hready, s1_ahb_hready};\nassign m_ahb_hrdata = slave_select_dly ? s1_ahb_hrdata : s0_ahb_hrdata;\nassign m_ahb_hresp = slave_select_dly ? s1_ahb_hresp : s0_ahb_hresp;\n\nalways_ff @(posedge clk or negedge reset_l) begin\n if(~reset_l) slave_select_dly <= 1'b0;\n else slave_select_dly <= slave_select;\nend\n\nendmodule\n" }, { "path": "testbench/ahb_sif.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n// Copyright 2024 Antmicro \n// //\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n`ifdef RV_BUILD_AHB_LITE\n\nmodule ahb_sif #(\n parameter int MAX_DELAY = -1,\n parameter int MIN_DELAY = 0\n) (\n input logic [63:0] HWDATA,\n input logic HCLK,\n input logic HSEL,\n input logic [3:0] HPROT,\n input logic HWRITE,\n input logic [1:0] HTRANS,\n input logic [2:0] HSIZE,\n input logic HREADY,\n input logic HRESETn,\n input logic [31:0] HADDR,\n input logic [2:0] HBURST,\n\n output logic HREADYOUT,\n output logic HRESP,\n output logic [63:0] HRDATA\n);\n\n logic write;\n logic [31:0] laddr, addr;\n logic [7:0] strb_lat;\n logic [63:0] rdata;\n\n bit [7:0] mem[bit [31:0]];\n bit [7:0] wscnt;\n int dws = 0;\n int iws = 0;\n bit dws_rand;\n bit iws_rand;\n bit ok;\n\n // Wires\n wire [7:0] strb = HSIZE == 3'b000 ? 8'h1 << HADDR[2:0] :\n HSIZE == 3'b001 ? 8'h3 << {HADDR[2:1],1'b0} :\n HSIZE == 3'b010 ? 8'hf << {HADDR[2],2'b0} : 8'hff;\n\n\n initial begin\n if ($value$plusargs(\"iws=%d\", iws));\n if ($value$plusargs(\"dws=%d\", dws));\n dws_rand = dws < 0;\n iws_rand = iws < 0;\n end\n\n\n\n always @(negedge HCLK) begin\n if (HREADY) addr = HADDR;\n if (write & HREADY) begin\n if (strb_lat[7]) mem[{laddr[31:3], 3'd7}] = HWDATA[63:56];\n if (strb_lat[6]) mem[{laddr[31:3], 3'd6}] = HWDATA[55:48];\n if (strb_lat[5]) mem[{laddr[31:3], 3'd5}] = HWDATA[47:40];\n if (strb_lat[4]) mem[{laddr[31:3], 3'd4}] = HWDATA[39:32];\n if (strb_lat[3]) mem[{laddr[31:3], 3'd3}] = HWDATA[31:24];\n if (strb_lat[2]) mem[{laddr[31:3], 3'd2}] = HWDATA[23:16];\n if (strb_lat[1]) mem[{laddr[31:3], 3'd1}] = HWDATA[15:08];\n if (strb_lat[0]) mem[{laddr[31:3], 3'd0}] = HWDATA[07:00];\n end\n if (HREADY & HSEL & |HTRANS) begin\n if (MAX_DELAY < 0) begin\n`ifdef VERILATOR\n if (iws_rand & ~HPROT[0]) iws = $random & 15;\n if (dws_rand & HPROT[0]) dws = $random & 15;\n`else\n if (iws_rand & ~HPROT[0])\n ok = std::randomize(\n iws\n ) with {\n iws dist {\n 0 := 10,\n [1 : 3] :/ 2,\n [4 : 15] :/ 1\n };\n };\n if (dws_rand & HPROT[0])\n ok = std::randomize(\n dws\n ) with {\n dws dist {\n 0 := 10,\n [1 : 3] :/ 2,\n [4 : 15] :/ 1\n };\n };\n`endif\n end else begin\n if (~HPROT[0]) iws = MIN_DELAY + $random % (MAX_DELAY-MIN_DELAY+1);\n if (HPROT[0]) dws = MIN_DELAY + $random % (MAX_DELAY-MIN_DELAY+1);\n end\n end\n end\n\n\n assign HRDATA = HREADY ? rdata : ~rdata;\n assign HREADYOUT = wscnt == 0;\n assign HRESP = 0;\n\n always @(posedge HCLK or negedge HRESETn) begin\n if (~HRESETn) begin\n laddr <= 32'b0;\n write <= 1'b0;\n rdata <= '0;\n wscnt <= 0;\n end else begin\n if (HREADY & HSEL) begin\n laddr <= HADDR;\n write <= HWRITE & |HTRANS;\n if (|HTRANS & ~HWRITE)\n rdata <= {\n mem[{addr[31:3], 3'd7}] & {8{strb[7]}},\n mem[{addr[31:3], 3'd6}] & {8{strb[6]}},\n mem[{addr[31:3], 3'd5}] & {8{strb[5]}},\n mem[{addr[31:3], 3'd4}] & {8{strb[4]}},\n mem[{addr[31:3], 3'd3}] & {8{strb[3]}},\n mem[{addr[31:3], 3'd2}] & {8{strb[2]}},\n mem[{addr[31:3], 3'd1}] & {8{strb[1]}},\n mem[{addr[31:3], 3'd0}] & {8{strb[0]}}\n };\n strb_lat <= strb;\n end\n end\n if (HREADY & HSEL & |HTRANS) wscnt <= HPROT[0] ? dws[7:0] : iws[7:0];\n else if (wscnt != 0) wscnt <= wscnt - 1;\n end\n\n\nendmodule\n`endif\n\nmodule axi_slv #(\n TAGW = 1\n) (\n input aclk,\n input rst_l,\n input arvalid,\n output reg arready,\n input [ 31:0] araddr,\n input [TAGW-1:0] arid,\n input [ 7:0] arlen,\n input [ 1:0] arburst,\n input [ 2:0] arsize,\n\n output reg rvalid,\n input rready,\n output reg [ 63:0] rdata,\n output reg [ 1:0] rresp,\n output reg [TAGW-1:0] rid,\n output reg rlast,\n\n input awvalid,\n output reg awready,\n input [ 31:0] awaddr,\n input [TAGW-1:0] awid,\n input [ 7:0] awlen,\n input [ 1:0] awburst,\n input [ 2:0] awsize,\n\n input [63:0] wdata,\n input [ 7:0] wstrb,\n input wvalid,\n output reg wready,\n\n output reg bvalid,\n input bready,\n output reg [ 1:0] bresp,\n output reg [TAGW-1:0] bid\n);\n\n bit [7:0] mem[bit [31:0]];\n bit [31:0] write_address;\n bit [31:0] read_address;\n\n initial begin\n wready = 1;\n awready = 1;\n arready = 1'b1;\n rlast = 1'b0;\n rvalid = 0;\n bvalid = 0;\n end\n\n always @(posedge aclk) begin\n if (arvalid && arready) begin\n read_address = {araddr[31:3], 3'b000};\n rdata <= {\n mem[read_address+7],\n mem[read_address+6],\n mem[read_address+5],\n mem[read_address+4],\n mem[read_address+3],\n mem[read_address+2],\n mem[read_address+1],\n mem[read_address]\n };\n arready <= 0;\n rvalid <= 1;\n rid <= arid;\n rlast <= 1;\n rresp <= 0;\n end else if (rready) begin\n rvalid <= 0;\n arready <= 1;\n rlast <= 0;\n end\n\n if (awvalid) begin\n write_address = {awaddr[31:3], 3'b000};\n awready <= 0;\n end\n if (wvalid) begin\n bid <= awid;\n bvalid <= 1;\n wready <= 0;\n bresp <= 0;\n if (wstrb[7]) mem[write_address+7] = wdata[63:56];\n if (wstrb[6]) mem[write_address+6] = wdata[55:48];\n if (wstrb[5]) mem[write_address+5] = wdata[47:40];\n if (wstrb[4]) mem[write_address+4] = wdata[39:32];\n if (wstrb[3]) mem[write_address+3] = wdata[31:24];\n if (wstrb[2]) mem[write_address+2] = wdata[23:16];\n if (wstrb[1]) mem[write_address+1] = wdata[15:08];\n if (wstrb[0]) mem[write_address+0] = wdata[07:00];\n end if (bready && bvalid) begin\n bvalid <= 0;\n awready <= 1;\n wready <= 1;\n end\n end\nendmodule\n" }, { "path": "testbench/asm/bitmanip.s", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2024 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n\n#define STDOUT 0xd0580000\n#define RESULT_SUCCESS 0xff\n#define RESULT_FAILURE 0x1\n\n// 5-bit encodings of registers\n#define reg_map(x) reg_map__##x\n#define reg_map__t0 5\n#define reg_map__t1 6\n#define reg_map__t2 7\n\n#define INSTR_TWO_ARG(rd, rs1, rs2) (reg_map(rd) << 7 | reg_map(rs1) << 15 | reg_map(rs2) << 20)\n#define INSTR_ONE_ARG(rd, rs1) (reg_map(rd) << 7 | reg_map(rs1) << 15)\n\n// Implement instructions not implemented in the toolchain (Bitmanip Extenstion 0.94-draft, Jan 20, 2021)\n#define crc32_b(rd, rs1) .word (0b0110000 << 25 | (0b10000) << 20 | INSTR_ONE_ARG(rd, rs1) | 0b001 << 12 | 0b0010011)\n#define crc32_h(rd, rs1) .word (0b0110000 << 25 | (0b10001) << 20 | INSTR_ONE_ARG(rd, rs1) | 0b001 << 12 | 0b0010011)\n#define crc32_w(rd, rs1) .word (0b0110000 << 25 | (0b10010) << 20 | INSTR_ONE_ARG(rd, rs1) | 0b001 << 12 | 0b0010011)\n#define crc32_d(rd, rs1) .word (0b0110000 << 25 | (0b10011) << 20 | INSTR_ONE_ARG(rd, rs1) | 0b001 << 12 | 0b0010011)\n#define crc32c_b(rd, rs1) .word (0b0110000 << 25 | (0b11000) << 20 | INSTR_ONE_ARG(rd, rs1) | 0b001 << 12 | 0b0010011)\n#define crc32c_h(rd, rs1) .word (0b0110000 << 25 | (0b11001) << 20 | INSTR_ONE_ARG(rd, rs1) | 0b001 << 12 | 0b0010011)\n#define crc32c_w(rd, rs1) .word (0b0110000 << 25 | (0b11010) << 20 | INSTR_ONE_ARG(rd, rs1) | 0b001 << 12 | 0b0010011)\n#define crc32c_d(rd, rs1) .word (0b0110000 << 25 | (0b11011) << 20 | INSTR_ONE_ARG(rd, rs1) | 0b001 << 12 | 0b0010011)\n\n#define shfl(rd, rs1, rs2) .word (0b0000100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b001 << 12 | 0b0110011)\n#define unshfl(rd, rs1, rs2) .word (0b0000100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b101 << 12 | 0b0110011)\n#define bdecompress(rd, rs1, rs2) .word (0b0100100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b110 << 12 | 0b0110011)\n#define bcompress(rd, rs1, rs2) .word (0b0000100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b110 << 12 | 0b0110011)\n#define bfp(rd, rs1, rs2) .word (0b0100100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b111 << 12 | 0b0110011)\n#define grev(rd, rs1, rs2) .word (0b0110100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b101 << 12 | 0b0110011)\n#define gorc(rd, rs1, rs2) .word (0b0010100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b101 << 12 | 0b0110011)\n\n#define xperm_n(rd, rs1, rs2) .word (0b0010100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b010 << 12 | 0b0110011)\n#define xperm_b(rd, rs1, rs2) .word (0b0010100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b100 << 12 | 0b0110011)\n#define xperm_h(rd, rs1, rs2) .word (0b0010100 << 25 | INSTR_TWO_ARG(rd, rs1, rs2) | 0b110 << 12 | 0b0110011)\n\n#define EQUAL_OR_FAIL(reg, value) \\\n li t3, value; \\\n bne reg, t3, test_failed\n\n.global _start\n_start:\n li t0, 0xc0de // arg1\n li t1, 0xdec0de // arg2\n li t2, 0 // result\n\ntest_bcompress:\n bcompress(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0xff)\n\ntest_bdcompress:\n bdecompress(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0xc05c)\n\ntest_grev:\n grev(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0xb7030000)\n\ntest_gorc:\n gorc(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0xffffffff)\n\ntest_shfl:\n shfl(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0x30003132)\n\ntest_unshfl:\n unshfl(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0xcf0006)\n\ntest_crc32_b:\n crc32_b(t2, t1)\n EQUAL_OR_FAIL(t2, 0x616b2113)\n\ntest_crc32_h:\n crc32_h(t2, t1)\n EQUAL_OR_FAIL(t2, 0x84df2aff)\n\ntest_crc32_w:\n crc32_w(t2, t1)\n EQUAL_OR_FAIL(t2, 0x489fb07b)\n\ntest_crc32c_b:\n crc32c_b(t2, t1)\n EQUAL_OR_FAIL(t2, 0x7fab804c)\n\ntest_crc32c_h:\n crc32c_h(t2, t1)\n EQUAL_OR_FAIL(t2, 0xc4779ec)\n\ntest_crc32c_w:\n crc32c_w(t2, t1)\n EQUAL_OR_FAIL(t2, 0xa1ebfe1d)\n\ntest_xperm_n:\n xperm_n(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0xee000e00)\n\ntest_xperm_b:\n xperm_b(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0xde000000)\n\ntest_xperm_h:\n xperm_h(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0x0)\n\ntest_bfp:\n bfp(t2, t0, t1)\n EQUAL_OR_FAIL(t2, 0x8000c0de)\n\nsuccess:\n li a0, STDOUT\n li a1, RESULT_SUCCESS\n sw a1, 0(a0)\n\ndo_nothing:\n nop\n j do_nothing\n\ntest_failed:\n li a0, STDOUT\n li a1, RESULT_FAILURE\n sw a1, 0(a0)\n.long 0\n" }, { "path": "testbench/asm/cmark.c", "content": "#include \"defines.h\"\n\n#define ITERATIONS 1\n\n\n/*\nAuthor : Shay Gal-On, EEMBC\n\nThis file is part of EEMBC(R) and CoreMark(TM), which are Copyright (C) 2009\nAll rights reserved.\n\nEEMBC CoreMark Software is a product of EEMBC and is provided under the terms of the\nCoreMark License that is distributed with the official EEMBC COREMARK Software release.\nIf you received this EEMBC CoreMark Software without the accompanying CoreMark License,\nyou must discontinue use and download the official release from www.coremark.org.\n\nAlso, if you are publicly displaying scores generated from the EEMBC CoreMark software,\nmake sure that you are in compliance with Run and Reporting rules specified in the accompanying readme.txt file.\n\nEEMBC\n4354 Town Center Blvd. Suite 114-200\nEl Dorado Hills, CA, 95762\n*/\n\n//#include \"/wd/users/jrahmeh/coremark_v1.0/riscv/coremark.h\"\n\n/*\nAuthor : Shay Gal-On, EEMBC\n\nThis file is part of EEMBC(R) and CoreMark(TM), which are Copyright (C) 2009\nAll rights reserved.\n\nEEMBC CoreMark Software is a product of EEMBC and is provided under the terms of the\nCoreMark License that is distributed with the official EEMBC COREMARK Software release.\nIf you received this EEMBC CoreMark Software without the accompanying CoreMark License,\nyou must discontinue use and download the official release from www.coremark.org.\n\nAlso, if you are publicly displaying scores generated from the EEMBC CoreMark software,\nmake sure that you are in compliance with Run and Reporting rules specified in the accompanying readme.txt file.\n\nEEMBC\n4354 Town Center Blvd. Suite 114-200\nEl Dorado Hills, CA, 95762\n*/\n/* Topic: Description\n This file contains declarations of the various benchmark functions.\n*/\n\n/* Configuration: TOTAL_DATA_SIZE\n Define total size for data algorithms will operate on\n*/\n#ifndef TOTAL_DATA_SIZE\n#define TOTAL_DATA_SIZE 2*1000\n#endif\n\n#define SEED_ARG 0\n#define SEED_FUNC 1\n#define SEED_VOLATILE 2\n\n#define MEM_STATIC 0\n#define MEM_MALLOC 1\n#define MEM_STACK 2\n\n/* File : core_portme.h */\n\n/*\n Author : Shay Gal-On, EEMBC\n Legal : TODO!\n*/\n/* Topic : Description\n This file contains configuration constants required to execute on different platforms\n*/\n#ifndef CORE_PORTME_H\n#define CORE_PORTME_H\n/************************/\n/* Data types and settings */\n/************************/\n/* Configuration : HAS_FLOAT\n Define to 1 if the platform supports floating point.\n*/\n#ifndef HAS_FLOAT\n#define HAS_FLOAT 0\n#endif\n/* Configuration : HAS_TIME_H\n Define to 1 if platform has the time.h header file,\n and implementation of functions thereof.\n*/\n#ifndef HAS_TIME_H\n#define HAS_TIME_H 0\n#endif\n/* Configuration : USE_CLOCK\n Define to 1 if platform has the time.h header file,\n and implementation of functions thereof.\n*/\n#ifndef USE_CLOCK\n#define USE_CLOCK 0\n#endif\n/* Configuration : HAS_STDIO\n Define to 1 if the platform has stdio.h.\n*/\n#ifndef HAS_STDIO\n#define HAS_STDIO 0\n#endif\n/* Configuration : HAS_PRINTF\n Define to 1 if the platform has stdio.h and implements the printf function.\n*/\n#ifndef HAS_PRINTF\n#define HAS_PRINTF 1\nint whisperPrintf(const char* format, ...);\n#define ee_printf whisperPrintf\n#endif\n\n/* Configuration : CORE_TICKS\n Define type of return from the timing functions.\n */\n#include \ntypedef clock_t CORE_TICKS;\n\n/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION\n Initialize these strings per platform\n*/\n#ifndef COMPILER_VERSION\n #ifdef __GNUC__\n #define COMPILER_VERSION \"GCC\"__VERSION__\n #else\n #define COMPILER_VERSION \"Please put compiler version here (e.g. gcc 4.1)\"\n #endif\n#endif\n#ifndef COMPILER_FLAGS\n #define COMPILER_FLAGS \"-O2\"\n#endif\n\n#ifndef MEM_LOCATION\n// #define MEM_LOCATION \"STACK\"\n #define MEM_LOCATION \"STATIC\"\n#endif\n\n/* Data Types :\n To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in .\n\n *Imprtant* :\n ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!\n*/\ntypedef signed short ee_s16;\ntypedef unsigned short ee_u16;\ntypedef signed int ee_s32;\ntypedef double ee_f32;\ntypedef unsigned char ee_u8;\ntypedef unsigned int ee_u32;\ntypedef ee_u32 ee_ptr_int;\ntypedef size_t ee_size_t;\n/* align_mem :\n This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks.\n*/\n#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))\n\n/* Configuration : SEED_METHOD\n Defines method to get seed values that cannot be computed at compile time.\n\n Valid values :\n SEED_ARG - from command line.\n SEED_FUNC - from a system function.\n SEED_VOLATILE - from volatile variables.\n*/\n#ifndef SEED_METHOD\n#define SEED_METHOD SEED_VOLATILE\n#endif\n\n/* Configuration : MEM_METHOD\n Defines method to get a block of memry.\n\n Valid values :\n MEM_MALLOC - for platforms that implement malloc and have malloc.h.\n MEM_STATIC - to use a static memory array.\n MEM_STACK - to allocate the data block on the stack (NYI).\n*/\n#ifndef MEM_METHOD\n//#define MEM_METHOD MEM_STACK\n#define MEM_METHOD MEM_STATIC\n#endif\n\n/* Configuration : MULTITHREAD\n Define for parallel execution\n\n Valid values :\n 1 - only one context (default).\n N>1 - will execute N copies in parallel.\n\n Note :\n If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.\n\n Two sample implementations are provided. Use or to enable them.\n\n It is valid to have a different implementation of and in ,\n to fit a particular architecture.\n*/\n#ifndef MULTITHREAD\n#define MULTITHREAD 1\n#define USE_PTHREAD 0\n#define USE_FORK 0\n#define USE_SOCKET 0\n#endif\n\n/* Configuration : MAIN_HAS_NOARGC\n Needed if platform does not support getting arguments to main.\n\n Valid values :\n 0 - argc/argv to main is supported\n 1 - argc/argv to main is not supported\n\n Note :\n This flag only matters if MULTITHREAD has been defined to a value greater then 1.\n*/\n#ifndef MAIN_HAS_NOARGC\n#define MAIN_HAS_NOARGC 1\n#endif\n\n/* Configuration : MAIN_HAS_NORETURN\n Needed if platform does not support returning a value from main.\n\n Valid values :\n 0 - main returns an int, and return value will be 0.\n 1 - platform does not support returning a value from main\n*/\n#ifndef MAIN_HAS_NORETURN\n#define MAIN_HAS_NORETURN 0\n#endif\n\n/* Variable : default_num_contexts\n Not used for this simple port, must cintain the value 1.\n*/\nextern ee_u32 default_num_contexts;\n\ntypedef struct CORE_PORTABLE_S {\n ee_u8 portable_id;\n} core_portable;\n\n/* target specific init/fini */\nvoid portable_init(core_portable *p, int *argc, char *argv[]);\nvoid portable_fini(core_portable *p);\n\n#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN)\n#if (TOTAL_DATA_SIZE==1200)\n#define PROFILE_RUN 1\n#elif (TOTAL_DATA_SIZE==2000)\n#define PERFORMANCE_RUN 1\n#else\n#define VALIDATION_RUN 1\n#endif\n#endif\n\n#endif /* CORE_PORTME_H */\n\n\n#if HAS_STDIO\n#include \n#endif\n#if HAS_PRINTF\n#ifndef ee_printf\n#define ee_printf printf\n#endif\n#endif\n\n/* Actual benchmark execution in iterate */\nvoid *iterate(void *pres);\n\n/* Typedef: secs_ret\n For machines that have floating point support, get number of seconds as a double.\n Otherwise an unsigned int.\n*/\n#if HAS_FLOAT\ntypedef double secs_ret;\n#else\ntypedef ee_u32 secs_ret;\n#endif\n\n#if MAIN_HAS_NORETURN\n#define MAIN_RETURN_VAL\n#define MAIN_RETURN_TYPE void\n#else\n#define MAIN_RETURN_VAL 0\n#define MAIN_RETURN_TYPE int\n#endif\n\nvoid start_time(void);\nvoid stop_time(void);\nCORE_TICKS get_time(void);\nsecs_ret time_in_secs(CORE_TICKS ticks);\n\n/* Misc useful functions */\nee_u16 crcu8(ee_u8 data, ee_u16 crc);\nee_u16 crc16(ee_s16 newval, ee_u16 crc);\nee_u16 crcu16(ee_u16 newval, ee_u16 crc);\nee_u16 crcu32(ee_u32 newval, ee_u16 crc);\nee_u8 check_data_types();\nvoid *portable_malloc(ee_size_t size);\nvoid portable_free(void *p);\nee_s32 parseval(char *valstring);\n\n/* Algorithm IDS */\n#define ID_LIST (1<<0)\n#define ID_MATRIX (1<<1)\n#define ID_STATE (1<<2)\n#define ALL_ALGORITHMS_MASK (ID_LIST|ID_MATRIX|ID_STATE)\n#define NUM_ALGORITHMS 3\n\n/* list data structures */\ntypedef struct list_data_s {\n ee_s16 data16;\n ee_s16 idx;\n} list_data;\n\ntypedef struct list_head_s {\n struct list_head_s *next;\n struct list_data_s *info;\n} list_head;\n\n\n/*matrix benchmark related stuff */\n#define MATDAT_INT 1\n#if MATDAT_INT\ntypedef ee_s16 MATDAT;\ntypedef ee_s32 MATRES;\n#else\ntypedef ee_f16 MATDAT;\ntypedef ee_f32 MATRES;\n#endif\n\ntypedef struct MAT_PARAMS_S {\n int N;\n MATDAT *A;\n MATDAT *B;\n MATRES *C;\n} mat_params;\n\n/* state machine related stuff */\n/* List of all the possible states for the FSM */\ntypedef enum CORE_STATE {\n CORE_START=0,\n CORE_INVALID,\n CORE_S1,\n CORE_S2,\n CORE_INT,\n CORE_FLOAT,\n CORE_EXPONENT,\n CORE_SCIENTIFIC,\n NUM_CORE_STATES\n} core_state_e ;\n\n\n/* Helper structure to hold results */\ntypedef struct RESULTS_S {\n /* inputs */\n ee_s16 seed1; /* Initializing seed */\n ee_s16 seed2; /* Initializing seed */\n ee_s16 seed3; /* Initializing seed */\n void *memblock[4]; /* Pointer to safe memory location */\n ee_u32 size; /* Size of the data */\n ee_u32 iterations; /* Number of iterations to execute */\n ee_u32 execs; /* Bitmask of operations to execute */\n struct list_head_s *list;\n mat_params mat;\n /* outputs */\n ee_u16 crc;\n ee_u16 crclist;\n ee_u16 crcmatrix;\n ee_u16 crcstate;\n ee_s16 err;\n /* ultithread specific */\n core_portable port;\n} core_results;\n\n/* Multicore execution handling */\n#if (MULTITHREAD>1)\nee_u8 core_start_parallel(core_results *res);\nee_u8 core_stop_parallel(core_results *res);\n#endif\n\n/* list benchmark functions */\nlist_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed);\nee_u16 core_bench_list(core_results *res, ee_s16 finder_idx);\n\n/* state benchmark functions */\nvoid core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p);\nee_u16 core_bench_state(ee_u32 blksize, ee_u8 *memblock,\n ee_s16 seed1, ee_s16 seed2, ee_s16 step, ee_u16 crc);\n\n/* matrix benchmark functions */\nee_u32 core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p);\nee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc);\n\n\n\n\n\n/*\nTopic: Description\n Benchmark using a linked list.\n\n Linked list is a common data structure used in many applications.\n\n For our purposes, this will excercise the memory units of the processor.\n In particular, usage of the list pointers to find and alter data.\n\n We are not using Malloc since some platforms do not support this library.\n\n Instead, the memory block being passed in is used to create a list,\n and the benchmark takes care not to add more items then can be\n accomodated by the memory block. The porting layer will make sure\n that we have a valid memory block.\n\n All operations are done in place, without using any extra memory.\n\n The list itself contains list pointers and pointers to data items.\n Data items contain the following:\n\n idx - An index that captures the initial order of the list.\n data - Variable data initialized based on the input parameters. The 16b are divided as follows:\n o Upper 8b are backup of original data.\n o Bit 7 indicates if the lower 7 bits are to be used as is or calculated.\n o Bits 0-2 indicate type of operation to perform to get a 7b value.\n o Bits 3-6 provide input for the operation.\n\n*/\n\n/* local functions */\n\nlist_head *core_list_find(list_head *list,list_data *info);\nlist_head *core_list_reverse(list_head *list);\nlist_head *core_list_remove(list_head *item);\nlist_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified);\nlist_head *core_list_insert_new(list_head *insert_point\n , list_data *info, list_head **memblock, list_data **datablock\n , list_head *memblock_end, list_data *datablock_end);\ntypedef ee_s32(*list_cmp)(list_data *a, list_data *b, core_results *res);\nlist_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res);\n\nee_s16 calc_func(ee_s16 *pdata, core_results *res) {\n ee_s16 data=*pdata;\n ee_s16 retval;\n ee_u8 optype=(data>>7) & 1; /* bit 7 indicates if the function result has been cached */\n if (optype) /* if cached, use cache */\n return (data & 0x007f);\n else { /* otherwise calculate and cache the result */\n ee_s16 flag=data & 0x7; /* bits 0-2 is type of function to perform */\n ee_s16 dtype=((data>>3) & 0xf); /* bits 3-6 is specific data for the operation */\n dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */\n switch (flag) {\n case 0:\n if (dtype<0x22) /* set min period for bit corruption */\n dtype=0x22;\n retval=core_bench_state(res->size,res->memblock[3],res->seed1,res->seed2,dtype,res->crc);\n if (res->crcstate==0)\n res->crcstate=retval;\n break;\n case 1:\n retval=core_bench_matrix(&(res->mat),dtype,res->crc);\n if (res->crcmatrix==0)\n res->crcmatrix=retval;\n break;\n default:\n retval=data;\n break;\n }\n res->crc=crcu16(retval,res->crc);\n retval &= 0x007f;\n *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */\n return retval;\n }\n}\n/* Function: cmp_complex\n Compare the data item in a list cell.\n\n Can be used by mergesort.\n*/\nee_s32 cmp_complex(list_data *a, list_data *b, core_results *res) {\n ee_s16 val1=calc_func(&(a->data16),res);\n ee_s16 val2=calc_func(&(b->data16),res);\n return val1 - val2;\n}\n\n/* Function: cmp_idx\n Compare the idx item in a list cell, and regen the data.\n\n Can be used by mergesort.\n*/\nee_s32 cmp_idx(list_data *a, list_data *b, core_results *res) {\n if (res==NULL) {\n a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16>>8));\n b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16>>8));\n }\n return a->idx - b->idx;\n}\n\nvoid copy_info(list_data *to,list_data *from) {\n to->data16=from->data16;\n to->idx=from->idx;\n}\n\n/* Benchmark for linked list:\n - Try to find multiple data items.\n - List sort\n - Operate on data from list (crc)\n - Single remove/reinsert\n * At the end of this function, the list is back to original state\n*/\nee_u16 core_bench_list(core_results *res, ee_s16 finder_idx) {\n ee_u16 retval=0;\n ee_u16 found=0,missed=0;\n list_head *list=res->list;\n ee_s16 find_num=res->seed3;\n list_head *this_find;\n list_head *finder, *remover;\n list_data info;\n ee_s16 i;\n\n info.idx=finder_idx;\n /* find values in the list, and change the list each time (reverse and cache if value found) */\n for (i=0; inext->info->data16 >> 8) & 1;\n }\n else {\n found++;\n if (this_find->info->data16 & 0x1) /* use found value */\n retval+=(this_find->info->data16 >> 9) & 1;\n /* and cache next item at the head of the list (if any) */\n if (this_find->next != NULL) {\n finder = this_find->next;\n this_find->next = finder->next;\n finder->next=list->next;\n list->next=finder;\n }\n }\n if (info.idx>=0)\n info.idx++;\n#if CORE_DEBUG\n ee_printf(\"List find %d: [%d,%d,%d]\\n\",i,retval,missed,found);\n#endif\n }\n retval+=found*4-missed;\n /* sort the list by data content and remove one item*/\n if (finder_idx>0)\n list=core_list_mergesort(list,cmp_complex,res);\n remover=core_list_remove(list->next);\n /* CRC data content of list from location of index N forward, and then undo remove */\n finder=core_list_find(list,&info);\n if (!finder)\n finder=list->next;\n while (finder) {\n retval=crc16(list->info->data16,retval);\n finder=finder->next;\n }\n#if CORE_DEBUG\n ee_printf(\"List sort 1: %04x\\n\",retval);\n#endif\n remover=core_list_undo_remove(remover,list->next);\n /* sort the list by index, in effect returning the list to original state */\n list=core_list_mergesort(list,cmp_idx,NULL);\n /* CRC data content of list */\n finder=list->next;\n while (finder) {\n retval=crc16(list->info->data16,retval);\n finder=finder->next;\n }\n#if CORE_DEBUG\n ee_printf(\"List sort 2: %04x\\n\",retval);\n#endif\n return retval;\n}\n/* Function: core_list_init\n Initialize list with data.\n\n Parameters:\n blksize - Size of memory to be initialized.\n memblock - Pointer to memory block.\n seed - Actual values chosen depend on the seed parameter.\n The seed parameter MUST be supplied from a source that cannot be determined at compile time\n\n Returns:\n Pointer to the head of the list.\n\n*/\nlist_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed) {\n /* calculated pointers for the list */\n ee_u32 per_item=16+sizeof(struct list_data_s);\n ee_u32 size=(blksize/per_item)-2; /* to accomodate systems with 64b pointers, and make sure same code is executed, set max list elements */\n list_head *memblock_end=memblock+size;\n list_data *datablock=(list_data *)(memblock_end);\n list_data *datablock_end=datablock+size;\n /* some useful variables */\n ee_u32 i;\n list_head *finder,*list=memblock;\n list_data info;\n\n /* create a fake items for the list head and tail */\n list->next=NULL;\n list->info=datablock;\n list->info->idx=0x0000;\n list->info->data16=(ee_s16)0x8080;\n memblock++;\n datablock++;\n info.idx=0x7fff;\n info.data16=(ee_s16)0xffff;\n core_list_insert_new(list,&info,&memblock,&datablock,memblock_end,datablock_end);\n\n /* then insert size items */\n for (i=0; inext;\n i=1;\n while (finder->next!=NULL) {\n if (iinfo->idx=i++;\n else {\n ee_u16 pat=(ee_u16)(i++ ^ seed); /* get a pseudo random number */\n finder->info->idx=0x3fff & (((i & 0x07) << 8) | pat); /* make sure the mixed items end up after the ones in sequence */\n }\n finder=finder->next;\n }\n list = core_list_mergesort(list,cmp_idx,NULL);\n#if CORE_DEBUG\n ee_printf(\"Initialized list:\\n\");\n finder=list;\n while (finder) {\n ee_printf(\"[%04x,%04x]\",finder->info->idx,(ee_u16)finder->info->data16);\n finder=finder->next;\n }\n ee_printf(\"\\n\");\n#endif\n return list;\n}\n\n/* Function: core_list_insert\n Insert an item to the list\n\n Parameters:\n insert_point - where to insert the item.\n info - data for the cell.\n memblock - pointer for the list header\n datablock - pointer for the list data\n memblock_end - end of region for list headers\n datablock_end - end of region for list data\n\n Returns:\n Pointer to new item.\n*/\nlist_head *core_list_insert_new(list_head *insert_point, list_data *info, list_head **memblock, list_data **datablock\n , list_head *memblock_end, list_data *datablock_end) {\n list_head *newitem;\n\n if ((*memblock+1) >= memblock_end)\n return NULL;\n if ((*datablock+1) >= datablock_end)\n return NULL;\n\n newitem=*memblock;\n (*memblock)++;\n newitem->next=insert_point->next;\n insert_point->next=newitem;\n\n newitem->info=*datablock;\n (*datablock)++;\n copy_info(newitem->info,info);\n\n return newitem;\n}\n\n/* Function: core_list_remove\n Remove an item from the list.\n\n Operation:\n For a singly linked list, remove by copying the data from the next item\n over to the current cell, and unlinking the next item.\n\n Note:\n since there is always a fake item at the end of the list, no need to check for NULL.\n\n Returns:\n Removed item.\n*/\nlist_head *core_list_remove(list_head *item) {\n list_data *tmp;\n list_head *ret=item->next;\n /* swap data pointers */\n tmp=item->info;\n item->info=ret->info;\n ret->info=tmp;\n /* and eliminate item */\n item->next=item->next->next;\n ret->next=NULL;\n return ret;\n}\n\n/* Function: core_list_undo_remove\n Undo a remove operation.\n\n Operation:\n Since we want each iteration of the benchmark to be exactly the same,\n we need to be able to undo a remove.\n Link the removed item back into the list, and switch the info items.\n\n Parameters:\n item_removed - Return value from the \n item_modified - List item that was modified during \n\n Returns:\n The item that was linked back to the list.\n\n*/\nlist_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified) {\n list_data *tmp;\n /* swap data pointers */\n tmp=item_removed->info;\n item_removed->info=item_modified->info;\n item_modified->info=tmp;\n /* and insert item */\n item_removed->next=item_modified->next;\n item_modified->next=item_removed;\n return item_removed;\n}\n\n/* Function: core_list_find\n Find an item in the list\n\n Operation:\n Find an item by idx (if not 0) or specific data value\n\n Parameters:\n list - list head\n info - idx or data to find\n\n Returns:\n Found item, or NULL if not found.\n*/\nlist_head *core_list_find(list_head *list,list_data *info) {\n if (info->idx>=0) {\n while (list && (list->info->idx != info->idx))\n list=list->next;\n return list;\n } else {\n while (list && ((list->info->data16 & 0xff) != info->data16))\n list=list->next;\n return list;\n }\n}\n/* Function: core_list_reverse\n Reverse a list\n\n Operation:\n Rearrange the pointers so the list is reversed.\n\n Parameters:\n list - list head\n info - idx or data to find\n\n Returns:\n Found item, or NULL if not found.\n*/\n\nlist_head *core_list_reverse(list_head *list) {\n list_head *next=NULL, *tmp;\n while (list) {\n tmp=list->next;\n list->next=next;\n next=list;\n list=tmp;\n }\n return next;\n}\n/* Function: core_list_mergesort\n Sort the list in place without recursion.\n\n Description:\n Use mergesort, as for linked list this is a realistic solution.\n Also, since this is aimed at embedded, care was taken to use iterative rather then recursive algorithm.\n The sort can either return the list to original order (by idx) ,\n or use the data item to invoke other other algorithms and change the order of the list.\n\n Parameters:\n list - list to be sorted.\n cmp - cmp function to use\n\n Returns:\n New head of the list.\n\n Note:\n We have a special header for the list that will always be first,\n but the algorithm could theoretically modify where the list starts.\n\n */\nlist_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res) {\n list_head *p, *q, *e, *tail;\n ee_s32 insize, nmerges, psize, qsize, i;\n\n insize = 1;\n\n while (1) {\n p = list;\n list = NULL;\n tail = NULL;\n\n nmerges = 0; /* count number of merges we do in this pass */\n\n while (p) {\n nmerges++; /* there exists a merge to be done */\n /* step `insize' places along from p */\n q = p;\n psize = 0;\n for (i = 0; i < insize; i++) {\n psize++;\n q = q->next;\n if (!q) break;\n }\n\n /* if q hasn't fallen off end, we have two lists to merge */\n qsize = insize;\n\n /* now we have two lists; merge them */\n while (psize > 0 || (qsize > 0 && q)) {\n\n /* decide whether next element of merge comes from p or q */\n if (psize == 0) {\n /* p is empty; e must come from q. */\n e = q; q = q->next; qsize--;\n } else if (qsize == 0 || !q) {\n /* q is empty; e must come from p. */\n e = p; p = p->next; psize--;\n } else if (cmp(p->info,q->info,res) <= 0) {\n /* First element of p is lower (or same); e must come from p. */\n e = p; p = p->next; psize--;\n } else {\n /* First element of q is lower; e must come from q. */\n e = q; q = q->next; qsize--;\n }\n\n /* add the next element to the merged list */\n if (tail) {\n tail->next = e;\n } else {\n list = e;\n }\n tail = e;\n }\n\n /* now p has stepped `insize' places along, and q has too */\n p = q;\n }\n\n tail->next = NULL;\n\n /* If we have done only one merge, we're finished. */\n if (nmerges <= 1) /* allow for nmerges==0, the empty list case */\n return list;\n\n /* Otherwise repeat, merging lists twice the size */\n insize *= 2;\n }\n#if COMPILER_REQUIRES_SORT_RETURN\n return list;\n#endif\n}\n/*\nAuthor : Shay Gal-On, EEMBC\n\nThis file is part of EEMBC(R) and CoreMark(TM), which are Copyright (C) 2009\nAll rights reserved.\n\nEEMBC CoreMark Software is a product of EEMBC and is provided under the terms of the\nCoreMark License that is distributed with the official EEMBC COREMARK Software release.\nIf you received this EEMBC CoreMark Software without the accompanying CoreMark License,\nyou must discontinue use and download the official release from www.coremark.org.\n\nAlso, if you are publicly displaying scores generated from the EEMBC CoreMark software,\nmake sure that you are in compliance with Run and Reporting rules specified in the accompanying readme.txt file.\n\nEEMBC\n4354 Town Center Blvd. Suite 114-200\nEl Dorado Hills, CA, 95762\n*/\n/* File: core_main.c\n This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.\n*/\n//#include \"coremark.h\"\n\n/* Function: iterate\n Run the benchmark for a specified number of iterations.\n\n Operation:\n For each type of benchmarked algorithm:\n a - Initialize the data block for the algorithm.\n b - Execute the algorithm N times.\n\n Returns:\n NULL.\n*/\nstatic ee_u16 list_known_crc[] = {(ee_u16)0xd4b0,(ee_u16)0x3340,(ee_u16)0x6a79,(ee_u16)0xe714,(ee_u16)0xe3c1};\nstatic ee_u16 matrix_known_crc[] = {(ee_u16)0xbe52,(ee_u16)0x1199,(ee_u16)0x5608,(ee_u16)0x1fd7,(ee_u16)0x0747};\nstatic ee_u16 state_known_crc[] = {(ee_u16)0x5e47,(ee_u16)0x39bf,(ee_u16)0xe5a4,(ee_u16)0x8e3a,(ee_u16)0x8d84};\nvoid *iterate(void *pres) {\n ee_u32 i;\n ee_u16 crc;\n core_results *res=(core_results *)pres;\n ee_u32 iterations=res->iterations;\n res->crc=0;\n res->crclist=0;\n res->crcmatrix=0;\n res->crcstate=0;\n\n for (i=0; icrc=crcu16(crc,res->crc);\n crc=core_bench_list(res,-1);\n res->crc=crcu16(crc,res->crc);\n if (i==0) res->crclist=res->crc;\n }\n return NULL;\n}\n\n#if (SEED_METHOD==SEED_ARG)\nee_s32 get_seed_args(int i, int argc, char *argv[]);\n#define get_seed(x) (ee_s16)get_seed_args(x,argc,argv)\n#define get_seed_32(x) get_seed_args(x,argc,argv)\n#else /* via function or volatile */\nee_s32 get_seed_32(int i);\n#define get_seed(x) (ee_s16)get_seed_32(x)\n#endif\n\n#if (MEM_METHOD==MEM_STATIC)\nee_u8 static_memblk[TOTAL_DATA_SIZE];\n#endif\nchar *mem_name[3] = {\"Static\",\"Heap\",\"Stack\"};\n/* Function: main\n Main entry routine for the benchmark.\n This function is responsible for the following steps:\n\n 1 - Initialize input seeds from a source that cannot be determined at compile time.\n 2 - Initialize memory block for use.\n 3 - Run and time the benchmark.\n 4 - Report results, testing the validity of the output if the seeds are known.\n\n Arguments:\n 1 - first seed : Any value\n 2 - second seed : Must be identical to first for iterations to be identical\n 3 - third seed : Any value, should be at least an order of magnitude less then the input size, but bigger then 32.\n 4 - Iterations : Special, if set to 0, iterations will be automatically determined such that the benchmark will run between 10 to 100 secs\n\n*/\n\n#if MAIN_HAS_NOARGC\nMAIN_RETURN_TYPE main(void) {\n int argc=0;\n char *argv[1];\n#else\nMAIN_RETURN_TYPE main(int argc, char *argv[]) {\n#endif\n ee_u16 i,j=0,num_algorithms=0;\n ee_s16 known_id=-1,total_errors=0;\n ee_u16 seedcrc=0;\n CORE_TICKS total_time;\n core_results results[MULTITHREAD];\n#if (MEM_METHOD==MEM_STACK)\n ee_u8 stack_memblock[TOTAL_DATA_SIZE*MULTITHREAD];\n#endif\n /* first call any initializations needed */\n portable_init(&(results[0].port), &argc, argv);\n /* First some checks to make sure benchmark will run ok */\n if (sizeof(struct list_head_s)>128) {\n ee_printf(\"list_head structure too big for comparable data!\\n\");\n return MAIN_RETURN_VAL;\n }\n results[0].seed1=get_seed(1);\n results[0].seed2=get_seed(2);\n results[0].seed3=get_seed(3);\n results[0].iterations=get_seed_32(4);\n#if CORE_DEBUG\n results[0].iterations=1;\n#endif\n results[0].execs=get_seed_32(5);\n if (results[0].execs==0) { /* if not supplied, execute all algorithms */\n results[0].execs=ALL_ALGORITHMS_MASK;\n }\n /* put in some default values based on one seed only for easy testing */\n if ((results[0].seed1==0) && (results[0].seed2==0) && (results[0].seed3==0)) { /* validation run */\n results[0].seed1=0;\n results[0].seed2=0;\n results[0].seed3=0x66;\n }\n if ((results[0].seed1==1) && (results[0].seed2==0) && (results[0].seed3==0)) { /* perfromance run */\n results[0].seed1=0x3415;\n results[0].seed2=0x3415;\n results[0].seed3=0x66;\n }\n#if (MEM_METHOD==MEM_STATIC)\n results[0].memblock[0]=(void *)static_memblk;\n results[0].size=TOTAL_DATA_SIZE;\n results[0].err=0;\n #if (MULTITHREAD>1)\n #error \"Cannot use a static data area with multiple contexts!\"\n #endif\n#elif (MEM_METHOD==MEM_MALLOC)\n for (i=0 ; i1)\n if (default_num_contexts>MULTITHREAD) {\n default_num_contexts=MULTITHREAD;\n }\n for (i=0 ; i=0) {\n for (i=0 ; i 0)\n ee_printf(\"Iterations/Sec : %f\\n\",default_num_contexts*results[0].iterations/time_in_secs(total_time));\n#else\n ee_printf(\"Total time (secs): %d\\n\",time_in_secs(total_time));\n if (time_in_secs(total_time) > 0)\n// ee_printf(\"Iterations/Sec : %d\\n\",default_num_contexts*results[0].iterations/time_in_secs(total_time));\n ee_printf(\"Iterat/Sec/MHz : %d.%02d\\n\",1000*default_num_contexts*results[0].iterations/time_in_secs(total_time),\n 100000*default_num_contexts*results[0].iterations/time_in_secs(total_time) % 100);\n#endif\n if (time_in_secs(total_time) < 10) {\n ee_printf(\"ERROR! Must execute for at least 10 secs for a valid result!\\n\");\n total_errors++;\n }\n\n ee_printf(\"Iterations : %u\\n\",(ee_u32)default_num_contexts*results[0].iterations);\n ee_printf(\"Compiler version : %s\\n\",COMPILER_VERSION);\n ee_printf(\"Compiler flags : %s\\n\",COMPILER_FLAGS);\n#if (MULTITHREAD>1)\n ee_printf(\"Parallel %s : %d\\n\",PARALLEL_METHOD,default_num_contexts);\n#endif\n ee_printf(\"Memory location : %s\\n\",MEM_LOCATION);\n /* output for verification */\n ee_printf(\"seedcrc : 0x%04x\\n\",seedcrc);\n if (results[0].execs & ID_LIST)\n for (i=0 ; i1)\n ee_printf(\" / %d:%s\",default_num_contexts,PARALLEL_METHOD);\n#endif\n ee_printf(\"\\n\");\n }\n#endif\n }\n if (total_errors>0)\n ee_printf(\"Errors detected\\n\");\n if (total_errors<0)\n ee_printf(\"Cannot validate operation for these seed values, please compare with results on a known platform.\\n\");\n\n#if (MEM_METHOD==MEM_MALLOC)\n for (i=0 ; i>(from)) & (~(0xffffffff << (to))))\n\n#if CORE_DEBUG\nvoid printmat(MATDAT *A, ee_u32 N, char *name) {\n ee_u32 i,j;\n ee_printf(\"Matrix %s [%dx%d]:\\n\",name,N,N);\n for (i=0; i N times,\n changing the matrix values slightly by a constant amount each time.\n*/\nee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc) {\n ee_u32 N=p->N;\n MATRES *C=p->C;\n MATDAT *A=p->A;\n MATDAT *B=p->B;\n MATDAT val=(MATDAT)seed;\n\n crc=crc16(matrix_test(N,C,A,B,val),crc);\n\n return crc;\n}\n\n/* Function: matrix_test\n Perform matrix manipulation.\n\n Parameters:\n N - Dimensions of the matrix.\n C - memory for result matrix.\n A - input matrix\n B - operator matrix (not changed during operations)\n\n Returns:\n A CRC value that captures all results calculated in the function.\n In particular, crc of the value calculated on the result matrix\n after each step by .\n\n Operation:\n\n 1 - Add a constant value to all elements of a matrix.\n 2 - Multiply a matrix by a constant.\n 3 - Multiply a matrix by a vector.\n 4 - Multiply a matrix by a matrix.\n 5 - Add a constant value to all elements of a matrix.\n\n After the last step, matrix A is back to original contents.\n*/\nee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val) {\n ee_u16 crc=0;\n MATDAT clipval=matrix_big(val);\n\n matrix_add_const(N,A,val); /* make sure data changes */\n#if CORE_DEBUG\n printmat(A,N,\"matrix_add_const\");\n#endif\n matrix_mul_const(N,C,A,val);\n crc=crc16(matrix_sum(N,C,clipval),crc);\n#if CORE_DEBUG\n printmatC(C,N,\"matrix_mul_const\");\n#endif\n matrix_mul_vect(N,C,A,B);\n crc=crc16(matrix_sum(N,C,clipval),crc);\n#if CORE_DEBUG\n printmatC(C,N,\"matrix_mul_vect\");\n#endif\n matrix_mul_matrix(N,C,A,B);\n crc=crc16(matrix_sum(N,C,clipval),crc);\n#if CORE_DEBUG\n printmatC(C,N,\"matrix_mul_matrix\");\n#endif\n matrix_mul_matrix_bitextract(N,C,A,B);\n crc=crc16(matrix_sum(N,C,clipval),crc);\n#if CORE_DEBUG\n printmatC(C,N,\"matrix_mul_matrix_bitextract\");\n#endif\n\n matrix_add_const(N,A,-val); /* return matrix to initial value */\n return crc;\n}\n\n/* Function : matrix_init\n Initialize the memory block for matrix benchmarking.\n\n Parameters:\n blksize - Size of memory to be initialized.\n memblk - Pointer to memory block.\n seed - Actual values chosen depend on the seed parameter.\n p - pointers to containing initialized matrixes.\n\n Returns:\n Matrix dimensions.\n\n Note:\n The seed parameter MUST be supplied from a source that cannot be determined at compile time\n*/\nee_u32 core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p) {\n ee_u32 N=0;\n MATDAT *A;\n MATDAT *B;\n ee_s32 order=1;\n MATDAT val;\n ee_u32 i=0,j=0;\n if (seed==0)\n seed=1;\n while (jA=A;\n p->B=B;\n p->C=(MATRES *)align_mem(B+N*N);\n p->N=N;\n#if CORE_DEBUG\n printmat(A,N,\"A\");\n printmat(B,N,\"B\");\n#endif\n return N;\n}\n\n/* Function: matrix_sum\n Calculate a function that depends on the values of elements in the matrix.\n\n For each element, accumulate into a temporary variable.\n\n As long as this value is under the parameter clipval,\n add 1 to the result if the element is bigger then the previous.\n\n Otherwise, reset the accumulator and add 10 to the result.\n*/\nee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) {\n MATRES tmp=0,prev=0,cur=0;\n ee_s16 ret=0;\n ee_u32 i,j;\n for (i=0; iclipval) {\n ret+=10;\n tmp=0;\n } else {\n ret += (cur>prev) ? 1 : 0;\n }\n prev=cur;\n }\n }\n return ret;\n}\n\n/* Function: matrix_mul_const\n Multiply a matrix by a constant.\n This could be used as a scaler for instance.\n*/\nvoid matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) {\n ee_u32 i,j;\n for (i=0; i0) {\n for(i=0;i>3) & 0x3];\n next=4;\n break;\n case 3: /* float */\n case 4: /* float */\n buf=floatpat[(seed>>3) & 0x3];\n next=8;\n break;\n case 5: /* scientific */\n case 6: /* scientific */\n buf=scipat[(seed>>3) & 0x3];\n next=8;\n break;\n case 7: /* invalid */\n buf=errpat[(seed>>3) & 0x3];\n next=8;\n break;\n default: /* Never happen, just to make some compilers happy */\n break;\n }\n }\n size++;\n while (total='0') & (c<='9')) ? 1 : 0;\n return retval;\n}\n\n/* Function: core_state_transition\n Actual state machine.\n\n The state machine will continue scanning until either:\n 1 - an invalid input is detcted.\n 2 - a valid number has been detected.\n\n The input pointer is updated to point to the end of the token, and the end state is returned (either specific format determined or invalid).\n*/\n\nenum CORE_STATE core_state_transition( ee_u8 **instr , ee_u32 *transition_count) {\n ee_u8 *str=*instr;\n ee_u8 NEXT_SYMBOL;\n enum CORE_STATE state=CORE_START;\n for( ; *str && state != CORE_INVALID; str++ ) {\n NEXT_SYMBOL = *str;\n if (NEXT_SYMBOL==',') /* end of this input */ {\n str++;\n break;\n }\n switch(state) {\n case CORE_START:\n if(ee_isdigit(NEXT_SYMBOL)) {\n state = CORE_INT;\n }\n else if( NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-' ) {\n state = CORE_S1;\n }\n else if( NEXT_SYMBOL == '.' ) {\n state = CORE_FLOAT;\n }\n else {\n state = CORE_INVALID;\n transition_count[CORE_INVALID]++;\n }\n transition_count[CORE_START]++;\n break;\n case CORE_S1:\n if(ee_isdigit(NEXT_SYMBOL)) {\n state = CORE_INT;\n transition_count[CORE_S1]++;\n }\n else if( NEXT_SYMBOL == '.' ) {\n state = CORE_FLOAT;\n transition_count[CORE_S1]++;\n }\n else {\n state = CORE_INVALID;\n transition_count[CORE_S1]++;\n }\n break;\n case CORE_INT:\n if( NEXT_SYMBOL == '.' ) {\n state = CORE_FLOAT;\n transition_count[CORE_INT]++;\n }\n else if(!ee_isdigit(NEXT_SYMBOL)) {\n state = CORE_INVALID;\n transition_count[CORE_INT]++;\n }\n break;\n case CORE_FLOAT:\n if( NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e' ) {\n state = CORE_S2;\n transition_count[CORE_FLOAT]++;\n }\n else if(!ee_isdigit(NEXT_SYMBOL)) {\n state = CORE_INVALID;\n transition_count[CORE_FLOAT]++;\n }\n break;\n case CORE_S2:\n if( NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-' ) {\n state = CORE_EXPONENT;\n transition_count[CORE_S2]++;\n }\n else {\n state = CORE_INVALID;\n transition_count[CORE_S2]++;\n }\n break;\n case CORE_EXPONENT:\n if(ee_isdigit(NEXT_SYMBOL)) {\n state = CORE_SCIENTIFIC;\n transition_count[CORE_EXPONENT]++;\n }\n else {\n state = CORE_INVALID;\n transition_count[CORE_EXPONENT]++;\n }\n break;\n case CORE_SCIENTIFIC:\n if(!ee_isdigit(NEXT_SYMBOL)) {\n state = CORE_INVALID;\n transition_count[CORE_INVALID]++;\n }\n break;\n default:\n break;\n }\n }\n *instr=str;\n return state;\n}\n/*\nAuthor : Shay Gal-On, EEMBC\n\nThis file is part of EEMBC(R) and CoreMark(TM), which are Copyright (C) 2009\nAll rights reserved.\n\nEEMBC CoreMark Software is a product of EEMBC and is provided under the terms of the\nCoreMark License that is distributed with the official EEMBC COREMARK Software release.\nIf you received this EEMBC CoreMark Software without the accompanying CoreMark License,\nyou must discontinue use and download the official release from www.coremark.org.\n\nAlso, if you are publicly displaying scores generated from the EEMBC CoreMark software,\nmake sure that you are in compliance with Run and Reporting rules specified in the accompanying readme.txt file.\n\nEEMBC\n4354 Town Center Blvd. Suite 114-200\nEl Dorado Hills, CA, 95762\n*/\n//#include \"coremark.h\"\n/* Function: get_seed\n Get a values that cannot be determined at compile time.\n\n Since different embedded systems and compilers are used, 3 different methods are provided:\n 1 - Using a volatile variable. This method is only valid if the compiler is forced to generate code that\n reads the value of a volatile variable from memory at run time.\n Please note, if using this method, you would need to modify core_portme.c to generate training profile.\n 2 - Command line arguments. This is the preferred method if command line arguments are supported.\n 3 - System function. If none of the first 2 methods is available on the platform,\n a system function which is not a stub can be used.\n\n e.g. read the value on GPIO pins connected to switches, or invoke special simulator functions.\n*/\n#if (SEED_METHOD==SEED_VOLATILE)\n extern volatile ee_s32 seed1_volatile;\n extern volatile ee_s32 seed2_volatile;\n extern volatile ee_s32 seed3_volatile;\n extern volatile ee_s32 seed4_volatile;\n extern volatile ee_s32 seed5_volatile;\n ee_s32 get_seed_32(int i) {\n ee_s32 retval;\n switch (i) {\n case 1:\n retval=seed1_volatile;\n break;\n case 2:\n retval=seed2_volatile;\n break;\n case 3:\n retval=seed3_volatile;\n break;\n case 4:\n retval=seed4_volatile;\n break;\n case 5:\n retval=seed5_volatile;\n break;\n default:\n retval=0;\n break;\n }\n return retval;\n }\n#elif (SEED_METHOD==SEED_ARG)\nee_s32 parseval(char *valstring) {\n ee_s32 retval=0;\n ee_s32 neg=1;\n int hexmode=0;\n if (*valstring == '-') {\n neg=-1;\n valstring++;\n }\n if ((valstring[0] == '0') && (valstring[1] == 'x')) {\n hexmode=1;\n valstring+=2;\n }\n /* first look for digits */\n if (hexmode) {\n while (((*valstring >= '0') && (*valstring <= '9')) || ((*valstring >= 'a') && (*valstring <= 'f'))) {\n ee_s32 digit=*valstring-'0';\n if (digit>9)\n digit=10+*valstring-'a';\n retval*=16;\n retval+=digit;\n valstring++;\n }\n } else {\n while ((*valstring >= '0') && (*valstring <= '9')) {\n ee_s32 digit=*valstring-'0';\n retval*=10;\n retval+=digit;\n valstring++;\n }\n }\n /* now add qualifiers */\n if (*valstring=='K')\n retval*=1024;\n if (*valstring=='M')\n retval*=1024*1024;\n\n retval*=neg;\n return retval;\n}\n\nee_s32 get_seed_args(int i, int argc, char *argv[]) {\n if (argc>i)\n return parseval(argv[i]);\n return 0;\n}\n\n#elif (SEED_METHOD==SEED_FUNC)\n/* If using OS based function, you must define and implement the functions below in core_portme.h and core_portme.c ! */\nee_s32 get_seed_32(int i) {\n ee_s32 retval;\n switch (i) {\n case 1:\n retval=portme_sys1();\n break;\n case 2:\n retval=portme_sys2();\n break;\n case 3:\n retval=portme_sys3();\n break;\n case 4:\n retval=portme_sys4();\n break;\n case 5:\n retval=portme_sys5();\n break;\n default:\n retval=0;\n break;\n }\n return retval;\n}\n#endif\n\n/* Function: crc*\n Service functions to calculate 16b CRC code.\n\n*/\nee_u16 crcu8(ee_u8 data, ee_u16 crc )\n{\n ee_u8 i=0,x16=0,carry=0;\n\n for (i = 0; i < 8; i++)\n {\n x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1));\n data >>= 1;\n\n if (x16 == 1)\n {\n crc ^= 0x4002;\n carry = 1;\n }\n else\n carry = 0;\n crc >>= 1;\n if (carry)\n crc |= 0x8000;\n else\n crc &= 0x7fff;\n }\n return crc;\n}\nee_u16 crcu16(ee_u16 newval, ee_u16 crc) {\n crc=crcu8( (ee_u8) (newval) ,crc);\n crc=crcu8( (ee_u8) ((newval)>>8) ,crc);\n return crc;\n}\nee_u16 crcu32(ee_u32 newval, ee_u16 crc) {\n crc=crc16((ee_s16) newval ,crc);\n crc=crc16((ee_s16) (newval>>16) ,crc);\n return crc;\n}\nee_u16 crc16(ee_s16 newval, ee_u16 crc) {\n return crcu16((ee_u16)newval, crc);\n}\n\nee_u8 check_data_types() {\n ee_u8 retval=0;\n if (sizeof(ee_u8) != 1) {\n ee_printf(\"ERROR: ee_u8 is not an 8b datatype!\\n\");\n retval++;\n }\n if (sizeof(ee_u16) != 2) {\n ee_printf(\"ERROR: ee_u16 is not a 16b datatype!\\n\");\n retval++;\n }\n if (sizeof(ee_s16) != 2) {\n ee_printf(\"ERROR: ee_s16 is not a 16b datatype!\\n\");\n retval++;\n }\n if (sizeof(ee_s32) != 4) {\n ee_printf(\"ERROR: ee_s32 is not a 32b datatype!\\n\");\n retval++;\n }\n if (sizeof(ee_u32) != 4) {\n ee_printf(\"ERROR: ee_u32 is not a 32b datatype!\\n\");\n retval++;\n }\n if (sizeof(ee_ptr_int) != sizeof(int *)) {\n ee_printf(\"ERROR: ee_ptr_int is not a datatype that holds an int pointer!\\n\");\n retval++;\n }\n if (retval>0) {\n ee_printf(\"ERROR: Please modify the datatypes in core_portme.h!\\n\");\n }\n return retval;\n}\n/*\n File : core_portme.c\n*/\n/*\n Author : Shay Gal-On, EEMBC\n Legal : TODO!\n*/\n#include \n#include \n//#include \"coremark.h\"\n\n#if VALIDATION_RUN\n volatile ee_s32 seed1_volatile=0x3415;\n volatile ee_s32 seed2_volatile=0x3415;\n volatile ee_s32 seed3_volatile=0x66;\n#endif\n#if PERFORMANCE_RUN\n volatile ee_s32 seed1_volatile=0x0;\n volatile ee_s32 seed2_volatile=0x0;\n volatile ee_s32 seed3_volatile=0x66;\n#endif\n#if PROFILE_RUN\n volatile ee_s32 seed1_volatile=0x8;\n volatile ee_s32 seed2_volatile=0x8;\n volatile ee_s32 seed3_volatile=0x8;\n#endif\n volatile ee_s32 seed4_volatile=ITERATIONS;\n volatile ee_s32 seed5_volatile=0;\n/* Porting : Timing functions\n How to capture time and convert to seconds must be ported to whatever is supported by the platform.\n e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.\n Sample implementation for standard time.h and windows.h definitions included.\n*/\n/* Define : TIMER_RES_DIVIDER\n Divider to trade off timer resolution and total time that can be measured.\n\n Use lower values to increase resolution, but make sure that overflow does not occur.\n If there are issues with the return value overflowing, increase this value.\n */\n//#define NSECS_PER_SEC CLOCKS_PER_SEC\n#define NSECS_PER_SEC 1000000000\n#define CORETIMETYPE clock_t\n//#define GETMYTIME(_t) (*_t=clock())\n#define GETMYTIME(_t) (*_t=0)\n#define MYTIMEDIFF(fin,ini) ((fin)-(ini))\n#define TIMER_RES_DIVIDER 1\n#define SAMPLE_TIME_IMPLEMENTATION 1\n//#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER)\n\n#define EE_TICKS_PER_SEC 1000\n\n/** Define Host specific (POSIX), or target specific global time variables. */\nstatic CORETIMETYPE start_time_val, stop_time_val;\n\n/* Function : start_time\n This function will be called right before starting the timed portion of the benchmark.\n\n Implementation may be capturing a system timer (as implemented in the example code)\n or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.\n*/\nvoid start_time(void) {\nuint32_t mcyclel;\n asm volatile (\"csrr %0,mcycle\" : \"=r\" (mcyclel) );\n start_time_val = mcyclel;\n}\n/* Function : stop_time\n This function will be called right after ending the timed portion of the benchmark.\n\n Implementation may be capturing a system timer (as implemented in the example code)\n or other system parameters - e.g. reading the current value of cpu cycles counter.\n*/\nvoid stop_time(void) {\nuint32_t mcyclel;\n asm volatile (\"csrr %0,mcycle\" : \"=r\" (mcyclel) );\n stop_time_val = mcyclel;\n}\n/* Function : get_time\n Return an abstract \"ticks\" number that signifies time on the system.\n\n Actual value returned may be cpu cycles, milliseconds or any other value,\n as long as it can be converted to seconds by .\n This methodology is taken to accomodate any hardware or simulated platform.\n The sample implementation returns millisecs by default,\n and the resolution is controlled by \n*/\nCORE_TICKS get_time(void) {\n CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));\n return elapsed;\n}\n/* Function : time_in_secs\n Convert the value returned by get_time to seconds.\n\n The type is used to accomodate systems with no support for floating point.\n Default implementation implemented by the EE_TICKS_PER_SEC macro above.\n*/\nsecs_ret time_in_secs(CORE_TICKS ticks) {\n secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;\n return retval;\n}\n\nee_u32 default_num_contexts=1;\n\n/* Function : portable_init\n Target specific initialization code\n Test for some common mistakes.\n*/\nvoid portable_init(core_portable *p, int *argc, char *argv[])\n{\n if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {\n ee_printf(\"ERROR! Please define ee_ptr_int to a type that holds a pointer!\\n\");\n }\n if (sizeof(ee_u32) != 4) {\n ee_printf(\"ERROR! Please define ee_u32 to a 32b unsigned type!\\n\");\n }\n p->portable_id=1;\n}\n/* Function : portable_fini\n Target specific final code\n*/\nvoid portable_fini(core_portable *p)\n{\n p->portable_id=0;\n}\n\n\nvoid* memset(void* s, int c, size_t n)\n{\n asm(\"mv t0, a0\");\n asm(\"add a2, a2, a0\"); // end = s + n\n asm(\".memset_loop: bge a0, a2, .memset_end\");\n asm(\"sb a1, 0(a0)\");\n asm(\"addi a0, a0, 1\");\n asm(\"j .memset_loop\");\n asm(\".memset_end:\");\n asm(\"mv a0, t0\");\n asm(\"jr ra\");\n}\n" }, { "path": "testbench/asm/cmark.mki", "content": "TEST_CFLAGS = -finline-limit=400 -mbranch-cost=1 -Ofast -fno-code-hoisting -funroll-all-loops\nOFILES = crt0.o printf.o cmark.o\n" }, { "path": "testbench/asm/cmark_iccm.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000 ;\n .text : { crt0.o (.text*) }\n _end = .;\n . = 0xee000000 ;\n .text.init : { cmark.o (.text*) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n . = 0xf0040000;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xfffffff0;\n .iccm.ctl : { LONG(0xee000000); LONG(0xee008000) }\n . = 0xfffffff8;\n .data.ctl : { LONG(0xf0040000); LONG(STACK) }\n}\n" }, { "path": "testbench/asm/cmark_iccm.mki", "content": "TEST_CFLAGS = -g -O3 -funroll-all-loops\nOFILES = crt0.o printf.o cmark.o\n" }, { "path": "testbench/asm/common.s", "content": "#include \"defines.h\"\n#include \"tb.h\"\n\n.section .text\n.global _start\n_start:\n // Clear minstret\n csrw minstret, zero\n csrw minstreth, zero\n\n // Enable Caches in MRAC\n li x2, 0x5f555555\n csrw 0x7c0, x2\n\n // global interrupt enable\n csrr x2, mstatus\n ori x2, x2, 0x8\n csrw mstatus, x2\n\n // set up mtvec\n la x2, exc_int_handler\n csrw mtvec, x2\n\n // Set up NMI handler address\n li x3, STDOUT\n ori x2, x2, LOAD_NMI_ADDR\n sw x2, 0(x3)\n\n j main\n\n// Write 0xff to STDOUT for TB to terminate test.\n_finish:\n li x3, STDOUT\n addi x5, x0, 0xff\n sb x5, 0(x3)\n beq x0, x0, _finish\n.rept 100\n nop\n.endr\n\n// handler must be aligned to 256 bytes since it has to fit\n// in the upper 24 bits of nmi handler address set testbench command\n.balign 256\nexc_int_handler:\n // disable all interrupt sources\n csrw mie, zero\n // reenable signaling of NMIs for subsequent NMIs\n csrw 0xBC0, zero // mdeau\n // compare CSRs with expected values\n csrr x2, mcause\n bne x2, x4, fail\n csrr x2, 0x7FF // mscause\n bne x2, x5, fail\n // set mepc to return from the test once we leave the handler\n la x2, ok\n csrw mepc, x2\n mret\n\n// used for making sure we fail if we didn't jump to the exception/NMI handler\nfail_if_not_serviced:\n.rept 15\n nop\n.endr\n // fail if interrupt didn't get serviced\n j fail\n\nfail:\n // write 0x01 to STDOUT for TB to fail the test\n li x3, STDOUT\n addi x5, x0, 0x01\n sb x5, 0(x3)\n j fail\n\nok:\n ret" }, { "path": "testbench/asm/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n# Copyright 2020 Western Digital Corporation or its affiliates.\n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\n// startup code to support HLL programs\n\n#include \"defines.h\"\n\n.section .text.init\n.align 4\n.global _start\n_start:\n\n // Set trap handler\n la x1, _trap\n csrw mtvec, x1\n\n// enable caching, except region 0xd\n li t0, 0x59555555\n csrw 0x7c0, t0\n\n la sp, STACK\n\n call main\n\n # Map exit code of main() to command to be written to tohost\n snez a0, a0\n bnez a0, _finish\n li a0, 0xFF\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) // DemoTB test termination\n li a0, 1\n sw a0, 0(t0) // Whisper test termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.align 4\n_trap:\n li a0, 1 # failure\n j _finish\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/asm/dbus_nonblocking_load_error.s", "content": "#include \"common.s\"\n\ndbus_nonblocking_load_error:\n li x4, 0xF0000001\n li x5, 0x0\n // trigger bus fault at next load\n li x2, TRIGGER_DBUS_FAULT\n li x3, STDOUT\n sw x2, 0(x3)\n // bus fault is triggered on this instruction\n lw x2, 0(zero)\n j fail_if_not_serviced\n\nmain:\n call dbus_nonblocking_load_error\n j _finish" }, { "path": "testbench/asm/dbus_store_error.s", "content": "#include \"common.s\"\n\ndbus_store_error:\n li x4, 0xF0000000\n li x5, 0x0\n // address of some data that resides in memory (and not in iccm/dccm)\n lw x6, _start\n // trigger bus fault at next store\n li x2, TRIGGER_DBUS_FAULT\n li x3, STDOUT\n sw x2, 0(x3)\n // bus fault is triggered on this instruction\n sw x2, 0(x6)\n j fail_if_not_serviced\n\nmain:\n call dbus_store_error\n j _finish\n" }, { "path": "testbench/asm/dside_access_across_region_boundary.s", "content": "#include \"common.s\"\n\ndside_load_across_region_boundary:\n li x4, 0x4\n li x5, 0x2\n // load from across region boundary\n li x2, 0xe0000000-2\n lw x2, 0(x2)\n j fail_if_not_serviced\n\ndside_store_across_region_boundary:\n li x4, 0x6\n li x5, 0x2\n // store across region boundary\n li x2, 0xe0000000-2\n sw x2, 0(x2)\n j fail_if_not_serviced\n\nmain:\n call dside_load_across_region_boundary\n call dside_store_across_region_boundary\n j _finish" }, { "path": "testbench/asm/dside_access_region_prediction_error.s", "content": "#include \"common.s\"\n\ndside_load_region_prediction_error:\n li x4, 0x5\n li x5, 0x5\n // We take a large address that will overflow to another region\n // when offset is used in an 'lw' instruction: 0xFFFFFFFC + 0x4\n li x2, 0xFFFFFFFC\n lw x2, 0x4(x2)\n j fail_if_not_serviced\n\ndside_store_region_prediction_error:\n li x4, 0x7\n li x5, 0x5\n // same as in load region prediction error\n li x2, 0xFFFFFFFC\n sw x2, 0x4(x2)\n j fail_if_not_serviced\n\nmain:\n call dside_load_region_prediction_error\n call dside_store_region_prediction_error\n j _finish" }, { "path": "testbench/asm/dside_core_local_access_unmapped_address_error.s", "content": "#include \"common.s\"\n\ndside_core_local_load_unmapped_address_error:\n li x4, 0x5\n li x5, 0x2\n // load from DCCM upper boundary (this also triggers unmapped address error)\n li x2, RV_DCCM_EADR - 1\n lw x2, 0(x2)\n j fail_if_not_serviced\n\ndside_core_local_store_unmapped_address_error:\n li x4, 0x7\n li x5, 0x2\n // store to DCCM upper boundary (this also triggers unmapped address error)\n li x2, RV_DCCM_EADR - 1\n sw x2, 0(x2)\n j fail_if_not_serviced\n\nmain:\n call dside_core_local_load_unmapped_address_error\n call dside_core_local_store_unmapped_address_error\n j _finish" }, { "path": "testbench/asm/dside_pic_access_error.s", "content": "#include \"common.s\"\n\ndside_pic_load_access_error:\n li x4, 0x5\n li x5, 0x6\n // perform not word-sized load from PIC\n li x2, RV_PIC_BASE_ADDR\n lb x2, 0(x2)\n j fail_if_not_serviced\n\ndside_pic_store_access_error:\n li x4, 0x7\n li x5, 0x6\n // perform not word-sized store to PIC\n li x2, RV_PIC_BASE_ADDR\n sb x2, 0(x2)\n j fail_if_not_serviced\n\nmain:\n call dside_pic_load_access_error\n call dside_pic_store_access_error\n j _finish" }, { "path": "testbench/asm/dside_size_misaligned_access_to_non_idempotent_address.s", "content": "#include \"common.s\"\n\ndside_size_misaligned_load_to_non_idempotent_address:\n li x4, 0x4\n li x5, 0x1\n // load from across non-idempotent address (with side effects)\n // we take advantage of the fact that STDOUT is such an address\n li x2, STDOUT-2\n lw x2, 0(x2)\n j fail_if_not_serviced\n\ndside_size_misaligned_store_to_non_idempotent_address:\n li x4, 0x6\n li x5, 0x1\n // store to across non-idempotent address (with side effect)\n // we take advantage of the fact that STDOUT is such an address\n li x2, STDOUT-2\n sw x2, 0(x2)\n j fail_if_not_serviced\n\nmain:\n call dside_size_misaligned_load_to_non_idempotent_address\n call dside_size_misaligned_store_to_non_idempotent_address\n j _finish" }, { "path": "testbench/asm/ebreak_ecall.s", "content": "#include \"common.s\"\n\nbreakpoint_ebreak:\n li x4, 0x3\n li x5, 0x2\n ebreak\n j fail_if_not_serviced\n\nenvironment_call_from_m_mode:\n li x4, 0xB\n li x5, 0x0\n ecall\n j fail_if_not_serviced\n\nmain:\n call breakpoint_ebreak\n call environment_call_from_m_mode\n j _finish" }, { "path": "testbench/asm/hello_world.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text*) }\n _end = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n}\n" }, { "path": "testbench/asm/hello_world.s", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n\n// Assembly code for Hello World\n// Not using only ALU ops for creating the string\n\n\n#include \"defines.h\"\n\n#define STDOUT 0xd0580000\n\n\n// Code to execute\n.section .text\n.global _start\n_start:\n\n // Clear minstret\n csrw minstret, zero\n csrw minstreth, zero\n\n // Set trap handler\n la x1, _trap\n csrw mtvec, x1\n\n // Enable Caches in MRAC\n li x1, 0x5f555555\n csrw 0x7c0, x1\n\n // Load string from hw_data\n // and write to stdout address\n\n li x3, STDOUT\n la x4, hw_data\n\nloop:\n lb x5, 0(x4)\n sb x5, 0(x3)\n addi x4, x4, 1\n bnez x5, loop\n li a0, 0xff # success\n\n// Write return value (a0) from printf to STDOUT for TB to termiate test.\n_finish:\n li x3, STDOUT\n sb a0, 0(x3)\n beq x0, x0, _finish\n.rept 100\n nop\n.endr\n\n.align 4\n_trap:\n li a0, 1 # failure\n j _finish\n\n.data\nhw_data:\n.ascii \"-------------------------\\n\"\n.ascii \"Hello World from VeeR EL2\\n\"\n.ascii \"-------------------------\\n\"\n.byte 0\n" }, { "path": "testbench/asm/hello_world_dccm.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text*) }\n _end = .;\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n . = 0xf0040000;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xfffffff8;\n .data.ctl : { LONG(0xf0040000); LONG(STACK) }\n}\n" }, { "path": "testbench/asm/hello_world_iccm.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text*) }\n .data : { *(.*data) *(.rodata*)}\n . = ALIGN(4);\n printf_start = .;\n . = 0xee000000;\n .data_load : AT(printf_start) {*(.data_text)}\n printf_end = printf_start + SIZEOF(.data_load);\n}\n" }, { "path": "testbench/asm/hello_world_iccm.s", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n\n// Assembly code for Hello World\n// Not using only ALU ops for creating the string\n\n\n#include \"defines.h\"\n\n#define STDOUT 0xd0580000\n\n .set mfdc, 0x7f9\n.extern printf_start, printf_end\n// Code to execute\n.section .text\n.align 4\n.global _start\n_start:\n\n // Set trap handler\n la x1, _trap\n csrw mtvec, x1\n\n // Enable Caches in MRAC\n li x1, 0x5f555555\n csrw 0x7c0, x1\n li x3, 4\n csrw mfdc, x3 // disable store merging\n li x3, RV_ICCM_SADR\n la x4, printf_start\n la x5, printf_end\n\nload:\n lw x6, 0 (x4)\n sw x6, 0 (x3)\n addi x4,x4,4\n addi x3,x3,4\n bltu x4, x5, load\n\n fence.i\n call printf\n\n// Write return value (a0) from printf to STDOUT for TB to termiate test.\n_finish:\n li x3, STDOUT\n sb a0, 0(x3)\n beq x0, x0, _finish\n.rept 100\n nop\n.endr\n\n.align 4\n_trap:\n li a0, 1 # failure\n j _finish\n \n\n.data\nhw_data:\n.ascii \"------------------------------\\n\"\n.ascii \"Hello World from VeeR EL2 ICCM\\n\"\n.ascii \"------------------------------\\n\"\n.byte 0\n\n.section .data_text, \"ax\"\n // Load string from hw_data\n // and write to stdout address\n\nprintf:\n li x3, STDOUT\n la x4, hw_data\n\nloop:\n lb x5, 0(x4)\n sb x5, 0(x3)\n addi x4, x4, 1\n bnez x5, loop\n li a0, 0xff # success\n ret\n\n.long 0,1,2,3,4\n" }, { "path": "testbench/asm/icache.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n .text : { *(.text*) }\n . = 0x10000;\n .data : { *(.*data) *(.rodata*)}\n}\n" }, { "path": "testbench/asm/icache.s", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2024 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n\n#include \"defines.h\"\n\n#define STDOUT 0xd0580000\n\n .set mfdc, 0x7f9\n .set mrac, 0x7c0\n// Code to execute\n.section .text\n.global _start\n_start:\n // Enable Caches in MRAC\n li x1, 0x5f555555\n csrw mrac, x1\n li x3, 4\n csrw mfdc, x3 // disable store merging\n\n li t3, 0 // counter for the outer loop\n li t5, 100 // limit the outer loop to 100 iterations\nouter:\n beq t3, t5, report_success\n addi t3, t3, 1\n li t4, 123\ninner:\n addi t4, t4, -1\n bne t4, zero, inner\n jal x0, outer\nreport_success:\n // write 0xff to STDOUT to report success\n li x3, STDOUT\n li x2, 0xff\n sw x2, 0(x3)\nend:\n nop\n j end\n.long 0,1,2,3,4\n" }, { "path": "testbench/asm/illegal_instruction.s", "content": "#include \"common.s\"\n\nillegal_instruction:\n li x4, 0x2\n li x5, 0x0\n .word 0\n j fail_if_not_serviced\n\nmain:\n call illegal_instruction\n j _finish" }, { "path": "testbench/asm/infinite_loop.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n .text : { *(.text*) }\n . = 0x10000;\n .data : { *(.*data) *(.rodata*)}\n . = ALIGN(4);\n printf_start = .;\n . = 0xee000000;\n .data_load : AT(printf_start) {*(.data_text)}\n printf_end = printf_start + SIZEOF(.data_load);\n}\n" }, { "path": "testbench/asm/infinite_loop.s", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n// Copyright 2024 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n\n// Copied hello_world_iccm with an infinite loop inserted at the end\n\n#include \"defines.h\"\n\n#define STDOUT 0xd0580000\n\n .set mfdc, 0x7f9\n.extern printf_start, printf_end\n// Code to execute\n.section .text\n.global _start\n_start:\n\n\n\n // Enable Caches in MRAC\n li x1, 0x5f555555\n csrw 0x7c0, x1\n li x3, 4\n csrw mfdc, x3 // disable store merging\n\n // Simple infinite loop program with inner and outer loop\n li t3, 0\nouter:\n addi t3, t3, 1\n li t4, 123\ninner:\n addi t4, t4, -1\n bne t4, zero, inner\n jal x0, outer\n.long 0,1,2,3,4\n" }, { "path": "testbench/asm/internal_timer_ints.s", "content": "#include \"common.s\"\n\nmachine_internal_timer0_local_interrupt:\n li x4, 0x8000001d\n li x5, 0x0\n csrw 0x7D4, 0x0 // disable incrementing timer0\n csrw 0x7D2, 0x0 // reset timer0 count value\n csrw 0x7D3, 0x8 // set timer0 threshold to 8\n li x2, 0x20000000\n csrw mie, x2 // enable timer0 local interrupt\n csrw 0x7D4, 0x1 // reenable incrementing timer0\n j fail_if_not_serviced\n\nmachine_internal_timer1_local_interrupt:\n li x4, 0x8000001c\n li x5, 0x0\n csrw 0x7D7, 0x0 // disable incrementing timer0\n csrw 0x7D5, 0x0 // reset timer0 count value\n csrw 0x7D6, 0x8 // set timer0 threshold to 8\n li x2, 0x10000000\n csrw mie, x2 // enable timer0 local interrupt\n csrw 0x7D7, 0x1 // reenable incrementing timer0\n j fail_if_not_serviced\n\nmain:\n call machine_internal_timer0_local_interrupt\n call machine_internal_timer1_local_interrupt\n j _finish" }, { "path": "testbench/asm/iside_core_local_unmapped_address_error.s", "content": "#include \"common.s\"\n\niside_core_local_unmapped_address_error:\n li x4, 0x1\n li x5, 0x2\n // jump to address that's only halfway inside ICCM\n li x2, 0xee000000-2\n jalr x2, 0(x2)\n j fail_if_not_serviced\n\nmain:\n call iside_core_local_unmapped_address_error\n j _finish" }, { "path": "testbench/asm/iside_fetch_precise_bus_error.s", "content": "#include \"common.s\"\n\niside_fetch_precise_bus_error:\n li x4, 0x1\n li x5, 0x9\n li x2, TRIGGER_IBUS_FAULT\n li x3, STDOUT\n sw x2, 0(x3)\n // ibus fault is triggered on subsequent instruction - force refetch from memory\n // since testbench relies on bus transaction happening to trigger bus error\n fence.i\n j fail_if_not_serviced\n\nmain:\n call iside_fetch_precise_bus_error\n j _finish" }, { "path": "testbench/asm/lsu_trigger_hit.s", "content": "#include \"common.s\"\n\nlsu_trigger_hit:\n la x4, 0x3\n la x5, 0x1\n // set up address to trigger on\n li x2, 0xdeadbeef\n csrw tdata2, x2\n // enable trigger in M-mode, fire on address of a load\n li x3, 0x41\n csrw mcontrol, x3\n // load from that address\n lw x2, 0(x2)\n j fail_if_not_serviced\n\nmain:\n call lsu_trigger_hit\n j _finish" }, { "path": "testbench/asm/machine_external_ints.s", "content": "#include \"common.s\"\n\nmachine_software_interrupt:\n la x4, 0x80000003\n li x5, 0x0\n // enable software interrupt\n li x2, 0x8\n csrw mie, x2\n // trigger soft interrupt\n li x2, TRIGGER_SOFT_INT\n li x3, STDOUT\n sw x2, 0(x3)\n j fail_if_not_serviced\n\nmachine_timer_interrupt:\n la x4, 0x80000007\n li x5, 0x0\n // enable machine timer interrupt\n li x2, 0x80\n csrw mie, x2\n // trigger timer interrupt\n li x2, TRIGGER_TIMER_INT\n li x3, STDOUT\n sw x2, 0(x3)\n j fail_if_not_serviced\n\nmain:\n call machine_software_interrupt\n call machine_timer_interrupt\n j _finish" }, { "path": "testbench/asm/machine_external_vec_ints.s", "content": "#include \"common.s\"\n\nenable_ext_int1:\n // set up gateway configuration - level triggered active high\n li x2, 0x0\n li x3, (RV_PIC_BASE_ADDR + 0x4004) // meigwctrl1\n sw x2, 0(x3)\n // clear interrupt bit for gateway\n li x3, (RV_PIC_BASE_ADDR + 0x5004) // meigwclr1\n sw zero, 0(x3)\n // set up priority level\n li x3, (RV_PIC_BASE_ADDR + 0x4) // meipl1\n li x2, 0x1\n sw x2, 0(x3)\n\n // interrupt priority threshold and priority nesting are\n // already initialized at correct value and we're only\n // testing one interrupt so we don't bother setting them explicitly\n\n // enable external interrupt 1\n li x3, (RV_PIC_BASE_ADDR + 0x2004)\n li x2, 0x1\n sw x2, 0(x3)\n // enable external interrupts\n li x2, 0x800\n csrw mie, x2\n ret\n\nmachine_external_interrupt:\n la x4, 0x8000000b\n la x5, 0x0\n // Set up external interrupt vector table at the beginning of DCCM\n la x2, exc_int_handler\n li x3, RV_DCCM_SADR\n sw x2, 0(x3)\n // set up base interrupt vector table address\n csrw 0xBC8, x3 // meivt\n\n mv x6, x1 // save return address\n call enable_ext_int1\n mv x1, x6 // restore return address\n\n li x2, TRIGGER_EXT_INT1\n li x3, STDOUT\n sw x2, 0(x3)\n j fail_if_not_serviced\n\nfast_interrupt_dccm_region_access_error:\n la x4, 0xF0001001\n la x5, 0x0\n // set up base interrupt vector table address at some address\n // *not* in DCCM but in DCCM region\n // assume somewhat optimistically that DCCM isn't allocated\n // at the end of its region so RV_DCCM_EADR + 1 is still in DCCM region\n li x2, RV_DCCM_EADR + 1\n csrw 0xBC8, x2 // meivt\n\n mv x6, x1 // save return address\n call enable_ext_int1\n mv x1, x6 // restore return address\n\n // trigger external interrupt 1\n li x2, TRIGGER_EXT_INT1\n li x3, STDOUT\n sw x2, 0(x3)\n j fail_if_not_serviced\n\nfast_interrupt_non_dccm_region:\n la x4, 0xF0001002\n la x5, 0x0\n // set up interrupt vector table address at an address that's\n // not in DCCM region\n li x2, ((RV_DCCM_REGION + 1) % 0x10) << 28\n csrw 0xBC8, x2 // meivt\n\n mv x6, x1 // save return address\n call enable_ext_int1\n mv x1, x6 // restore return address\n\n // trigger external interrupt 1\n li x2, TRIGGER_EXT_INT1\n li x3, STDOUT\n sw x2, 0(x3)\n j fail_if_not_serviced\n\nmain:\n call machine_external_interrupt\n call fast_interrupt_dccm_region_access_error\n call fast_interrupt_non_dccm_region\n j _finish" }, { "path": "testbench/asm/nmi_pin_assertion.s", "content": "#include \"common.s\"\n\nnmi_pin_assertion:\n li x4, 0x0\n li x5, 0x0 \n // trigger NMI\n li x2, TRIGGER_NMI\n li x3, STDOUT\n sw x2, 0(x3)\n j fail_if_not_serviced\n\nmain:\n call nmi_pin_assertion\n j _finish" }, { "path": "testbench/asm/printf.c", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n\n#include \n#include \nextern volatile char tohost;\n\nstatic int\nwhisperPutc(char c)\n{\n tohost = c;\n return c;\n}\n\n\nstatic int\nwhisperPuts(const char* s)\n{\n while (*s)\n whisperPutc(*s++);\n whisperPutc('\\n');\n// whisperPutc(0xd);\n return 1;\n}\n\n\nstatic int\nwhisperPrintUnsigned(unsigned value, int width, char pad)\n{\n char buffer[20];\n int charCount = 0;\n\n do\n {\n char c = '0' + (value % 10);\n value = value / 10;\n buffer[charCount++] = c;\n }\n while (value);\n\n for (int i = charCount; i < width; ++i)\n whisperPutc(pad);\n\n char* p = buffer + charCount - 1;\n for (int i = 0; i < charCount; ++i)\n whisperPutc(*p--);\n\n return charCount;\n}\n\n\nstatic int\nwhisperPrintDecimal(int value, int width, char pad)\n{\n char buffer[20];\n int charCount = 0;\n\n unsigned neg = value < 0;\n if (neg)\n {\n value = -value;\n whisperPutc('-');\n width--;\n }\n\n do\n {\n char c = '0' + (value % 10);\n value = value / 10;\n buffer[charCount++] = c;\n }\n while (value);\n\n for (int i = charCount; i < width; ++i)\n whisperPutc(pad);\n\n char* p = buffer + charCount - 1;\n for (int i = 0; i < charCount; ++i)\n whisperPutc(*p--);\n\n if (neg)\n charCount++;\n\n return charCount;\n}\n\n\nstatic int\nwhisperPrintInt(int value, int width, int pad, int base)\n{\n if (base == 10)\n return whisperPrintDecimal(value, width, pad);\n\n char buffer[20];\n int charCount = 0;\n\n unsigned uu = value;\n\n if (base == 8)\n {\n do\n {\n char c = '0' + (uu & 7);\n buffer[charCount++] = c;\n uu >>= 3;\n }\n while (uu);\n }\n else if (base == 16)\n {\n do\n {\n int digit = uu & 0xf;\n char c = digit < 10 ? '0' + digit : 'a' + digit - 10;\n buffer[charCount++] = c;\n uu >>= 4;\n }\n while (uu);\n }\n else\n return -1;\n\n char* p = buffer + charCount - 1;\n for (unsigned i = 0; i < charCount; ++i)\n whisperPutc(*p--);\n\n return charCount;\n}\n\n/*\n// Print with g format\nstatic int\nwhisperPrintDoubleG(double value)\n{\n return 0;\n}\n\n\n// Print with f format\nstatic int\nwhisperPrintDoubleF(double value)\n{\n return 0;\n}\n*/\n\nint\nwhisperPrintfImpl(const char* format, va_list ap)\n{\n int count = 0; // Printed character count\n\n for (const char* fp = format; *fp; fp++)\n {\n char pad = ' ';\n int width = 0; // Field width\n\n if (*fp != '%')\n {\n whisperPutc(*fp);\n ++count;\n continue;\n }\n\n ++fp; // Skip %\n\n if (*fp == 0)\n break;\n\n if (*fp == '%')\n {\n whisperPutc('%');\n continue;\n }\n\n while (*fp == '0')\n {\n pad = '0';\n fp++; // Pad zero not yet implented.\n }\n\n if (*fp == '-')\n {\n fp++; // Pad right not yet implemented.\n }\n\n if (*fp == '*')\n {\n int outWidth = va_arg(ap, int);\n fp++; // Width not yet implemented.\n }\n else if (*fp >= '0' && *fp <= '9')\n { // Width not yet implemented.\n while (*fp >= '0' && *fp <= '9')\n width = width * 10 + (*fp++ - '0');\n }\n\n switch (*fp)\n {\n case 'd':\n count += whisperPrintDecimal(va_arg(ap, int), width, pad);\n break;\n\n case 'u':\n count += whisperPrintUnsigned((unsigned) va_arg(ap, unsigned), width, pad);\n break;\n\n case 'x':\n case 'X':\n count += whisperPrintInt(va_arg(ap, int), width, pad, 16);\n break;\n\n case 'o':\n count += whisperPrintInt(va_arg(ap, int), width, pad, 8);\n break;\n\n case 'c':\n whisperPutc(va_arg(ap, int));\n ++count;\n break;\n\n case 's':\n count += whisperPuts(va_arg(ap, char*));\n break;\n/*\n case 'g':\n count += whisperPrintDoubleG(va_arg(ap, double));\n break;\n\n case 'f':\n count += whisperPrintDoubleF(va_arg(ap, double));\n*/\n }\n }\n\n return count;\n}\n\n\nint\nwhisperPrintf(const char* format, ...)\n{\n va_list ap;\n\n va_start(ap, format);\n int code = whisperPrintfImpl(format, ap);\n va_end(ap);\n\n return code;\n}\n\nint\nputchar(int c)\n{\n return whisperPutc(c);\n}\n\nstruct FILE;\n\nint\nputc(int c, struct FILE* f)\n{\n return whisperPutc(c);\n}\n\n\nint\nputs(const char* s)\n{\n return whisperPuts(s);\n}\n\nint\nprintf(const char* format, ...)\n{\n va_list ap;\n\n va_start(ap, format);\n int code = whisperPrintfImpl(format, ap);\n va_end(ap);\n\n return code;\n}\n\n// function to read cpu mcycle csr for performance measurements\n// simplified version\nuint64_t get_mcycle(){\nunsigned int mcyclel;\nunsigned int mcycleh0 = 0, mcycleh1=1;\nuint64_t cycles;\n\nwhile(mcycleh0 != mcycleh1) {\n asm volatile (\"csrr %0,mcycleh\" : \"=r\" (mcycleh0) );\n asm volatile (\"csrr %0,mcycle\" : \"=r\" (mcyclel) );\n asm volatile (\"csrr %0,mcycleh\" : \"=r\" (mcycleh1) );\n}\ncycles = mcycleh1;\nreturn (cycles << 32) | mcyclel;\n\n}\n" }, { "path": "testbench/asm/read_after_read.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text*) }\n _end = .;\n . = 0xc0000000;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n}\n" }, { "path": "testbench/asm/read_after_read.mki", "content": "TEST_CFLAGS = -g -O3 -falign-functions=16\nOFILES = crt0.o read_after_read.o\n" }, { "path": "testbench/asm/read_after_read.s", "content": "#include \"defines.h\"\n\n.set mfdc, 0x7f9\n\n.section .text\n.align 4\n.global main\nmain:\n // Clear minstret\n csrw minstret, zero\n csrw minstreth, zero\n\n li t0, 0x5A555555\n csrw 0x7c0, t0\n\n li t0, 4\n fence.i\n csrw mfdc, t0 // disable store merging\n fence.i\n\n la a0, scratchpad\n la s6, scratchpad\n lw zero, 304(a0)\n lw a0, 24(s6) // 0x18\n lw a1, 20(s6) // 0x14\n sw a0, 28(sp)\n sw a1, 24(sp)\n lw a0, 16(s6) // 0x10\n lw a1, 12(s6) // 0x_C\n lw s3, 4(s6) // 0x_4\n lw s8, 8(s6) // 0x_8\n sw a0, 20(sp)\n sw a1, 16(sp)\n sw s3, 12(sp)\n sw s8, 8(sp)\n li a0, 1\n lw a1, 28(sp)\n li t0, 6\n bne a1, t0, failed\n lw a1, 24(sp)\n li t0, 5\n bne a1, t0, failed\n lw a1, 20(sp)\n li t0, 4\n bne a1, t0, failed\n lw a1, 16(sp)\n li t0, 3\n bne a1, t0, failed\n lw a1, 12(sp)\n li t0, 1\n bne a1, t0, failed\n lw a1, 8(sp)\n li t0, 2\n bne a1, t0, failed\n lw a1, 4(sp)\n li t0, 0\n bne a1, t0, failed\n li a0, 0\n.global failed\nfailed:\n ret\n\n.section .data\n.global scratchpad\nscratchpad:\n.4byte 0\n.4byte 1\n.4byte 2\n.4byte 3\n.4byte 4\n.4byte 5\n.4byte 6\n.4byte 7\n.4byte 8\n.4byte 9\n.4byte 10\n.4byte 11\n.4byte 12\n.4byte 13\n.4byte 14\n.4byte 15\n.4byte 16\n.4byte 17\n.4byte 18\n.4byte 19\n.4byte 20\n.4byte 21\n.4byte 22\n.4byte 23\n.4byte 24\n.4byte 25\n.4byte 26\n.4byte 27\n.4byte 28\n.4byte 29\n.4byte 30\n.4byte 31\n.4byte 32\n.4byte 33\n.4byte 34\n.4byte 35\n.4byte 36\n.4byte 37\n.4byte 38\n.4byte 39\n.4byte 40\n.4byte 41\n.4byte 42\n.4byte 43\n.4byte 44\n.4byte 45\n.4byte 46\n.4byte 47\n.4byte 48\n.4byte 49\n.4byte 50\n.4byte 51\n.4byte 52\n.4byte 53\n.4byte 54\n.4byte 55\n.4byte 56\n.4byte 57\n.4byte 58\n.4byte 59\n.4byte 60\n.4byte 61\n.4byte 62\n.4byte 63\n.4byte 64\n.4byte 65\n.4byte 66\n.4byte 67\n.4byte 68\n.4byte 69\n.4byte 70\n.4byte 71\n.4byte 72\n.4byte 73\n.4byte 74\n.4byte 75\n.4byte 76\n" }, { "path": "testbench/asm/tb.h", "content": "#define STDOUT 0xd0580000\n\n#define TRIGGER_NMI 0x80\n#define LOAD_NMI_ADDR 0x81\n#define TRIGGER_SOFT_INT 0x84\n#define TRIGGER_TIMER_INT 0x85\n#define TRIGGER_EXT_INT1 0x86\n#define TRIGGER_DBUS_FAULT 0x87\n#define TRIGGER_IBUS_FAULT 0x88\n" }, { "path": "testbench/axi4_mux/arbiter.v", "content": "/*\n\nCopyright (c) 2014-2021 Alex Forencich\nCopyright 2024 Antmicro \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n`default_nettype none\n\n/*\n * Arbiter module\n */\nmodule arbiter #\n(\n parameter PORTS = 4,\n // select round robin arbitration\n parameter ARB_TYPE_ROUND_ROBIN = 0,\n // blocking arbiter enable\n parameter ARB_BLOCK = 0,\n // block on acknowledge assert when nonzero, request deassert when 0\n parameter ARB_BLOCK_ACK = 1,\n // LSB priority selection\n parameter ARB_LSB_HIGH_PRIORITY = 0\n)\n(\n input wire clk,\n input wire rst,\n\n input wire [PORTS-1:0] request,\n input wire [PORTS-1:0] acknowledge,\n\n output wire [PORTS-1:0] grant,\n output wire grant_valid,\n output wire [$clog2(PORTS)-1:0] grant_encoded\n);\n\nreg [PORTS-1:0] grant_reg = 0, grant_next;\nreg grant_valid_reg = 0, grant_valid_next;\nreg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;\n\nassign grant_valid = grant_valid_reg;\nassign grant = grant_reg;\nassign grant_encoded = grant_encoded_reg;\n\nwire request_valid;\nwire [$clog2(PORTS)-1:0] request_index;\nwire [PORTS-1:0] request_mask;\n\npriority_encoder #(\n .WIDTH(PORTS),\n .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)\n)\npriority_encoder_inst (\n .input_unencoded(request),\n .output_valid(request_valid),\n .output_encoded(request_index),\n .output_unencoded(request_mask)\n);\n\nreg [PORTS-1:0] mask_reg = 0, mask_next;\n\nwire masked_request_valid;\nwire [$clog2(PORTS)-1:0] masked_request_index;\nwire [PORTS-1:0] masked_request_mask;\n\npriority_encoder #(\n .WIDTH(PORTS),\n .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)\n)\npriority_encoder_masked (\n .input_unencoded(request & mask_reg),\n .output_valid(masked_request_valid),\n .output_encoded(masked_request_index),\n .output_unencoded(masked_request_mask)\n);\n\nalways @* begin\n grant_next = 0;\n grant_valid_next = 0;\n grant_encoded_next = 0;\n mask_next = mask_reg;\n\n if (ARB_BLOCK && !ARB_BLOCK_ACK && grant_reg & request) begin\n // granted request still asserted; hold it\n grant_valid_next = grant_valid_reg;\n grant_next = grant_reg;\n grant_encoded_next = grant_encoded_reg;\n end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && !(grant_reg & acknowledge)) begin\n // granted request not yet acknowledged; hold it\n grant_valid_next = grant_valid_reg;\n grant_next = grant_reg;\n grant_encoded_next = grant_encoded_reg;\n end else if (request_valid) begin\n if (ARB_TYPE_ROUND_ROBIN) begin\n if (masked_request_valid) begin\n grant_valid_next = 1;\n grant_next = masked_request_mask;\n grant_encoded_next = masked_request_index;\n if (ARB_LSB_HIGH_PRIORITY) begin\n mask_next = {PORTS{1'b1}} << (masked_request_index + 1);\n end else begin\n mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);\n end\n end else begin\n grant_valid_next = 1;\n grant_next = request_mask;\n grant_encoded_next = request_index;\n if (ARB_LSB_HIGH_PRIORITY) begin\n mask_next = {PORTS{1'b1}} << (request_index + 1);\n end else begin\n mask_next = {PORTS{1'b1}} >> (PORTS - request_index);\n end\n end\n end else begin\n grant_valid_next = 1;\n grant_next = request_mask;\n grant_encoded_next = request_index;\n end\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n grant_reg <= 0;\n grant_valid_reg <= 0;\n grant_encoded_reg <= 0;\n mask_reg <= 0;\n end else begin\n grant_reg <= grant_next;\n grant_valid_reg <= grant_valid_next;\n grant_encoded_reg <= grant_encoded_next;\n mask_reg <= mask_next;\n end\nend\n\nendmodule\n\n`resetall\n" }, { "path": "testbench/axi4_mux/axi_crossbar.v", "content": "/*\n\nCopyright (c) 2018 Alex Forencich\nCopyright 2024 Antmicro \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n`default_nettype none\n\n/*\n * AXI4 crossbar\n */\nmodule axi_crossbar #\n(\n // Number of AXI inputs (slave interfaces)\n parameter S_COUNT = 4,\n // Number of AXI outputs (master interfaces)\n parameter M_COUNT = 4,\n // Width of data bus in bits\n parameter DATA_WIDTH = 32,\n // Width of address bus in bits\n parameter ADDR_WIDTH = 32,\n // Width of wstrb (width of data bus in words)\n parameter STRB_WIDTH = (DATA_WIDTH/8),\n // Input ID field width (from AXI masters)\n parameter S_ID_WIDTH = 8,\n // Output ID field width (towards AXI slaves)\n // Additional bits required for response routing\n parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),\n // Propagate awuser signal\n parameter AWUSER_ENABLE = 0,\n // Width of awuser signal\n parameter AWUSER_WIDTH = 1,\n // Propagate wuser signal\n parameter WUSER_ENABLE = 0,\n // Width of wuser signal\n parameter WUSER_WIDTH = 1,\n // Propagate buser signal\n parameter BUSER_ENABLE = 0,\n // Width of buser signal\n parameter BUSER_WIDTH = 1,\n // Propagate aruser signal\n parameter ARUSER_ENABLE = 0,\n // Width of aruser signal\n parameter ARUSER_WIDTH = 1,\n // Propagate ruser signal\n parameter RUSER_ENABLE = 0,\n // Width of ruser signal\n parameter RUSER_WIDTH = 1,\n // Number of concurrent unique IDs for each slave interface\n // S_COUNT concatenated fields of 32 bits\n parameter S_THREADS = {S_COUNT{32'd2}},\n // Number of concurrent operations for each slave interface\n // S_COUNT concatenated fields of 32 bits\n parameter S_ACCEPT = {S_COUNT{32'd16}},\n // Number of regions per master interface\n parameter M_REGIONS = 1,\n // Master interface base addresses\n // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits\n // set to zero for default addressing based on M_ADDR_WIDTH\n parameter M_BASE_ADDR = 0,\n // Master interface address widths\n // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits\n parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},\n // Read connections between interfaces\n // M_COUNT concatenated fields of S_COUNT bits\n parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}},\n // Write connections between interfaces\n // M_COUNT concatenated fields of S_COUNT bits\n parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}},\n // Number of concurrent operations for each master interface\n // M_COUNT concatenated fields of 32 bits\n parameter M_ISSUE = {M_COUNT{32'd4}},\n // Secure master (fail operations based on awprot/arprot)\n // M_COUNT bits\n parameter M_SECURE = {M_COUNT{1'b0}},\n // Slave interface AW channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},\n // Slave interface W channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_W_REG_TYPE = {S_COUNT{2'd0}},\n // Slave interface B channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_B_REG_TYPE = {S_COUNT{2'd1}},\n // Slave interface AR channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},\n // Slave interface R channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_R_REG_TYPE = {S_COUNT{2'd2}},\n // Master interface AW channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},\n // Master interface W channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_W_REG_TYPE = {M_COUNT{2'd2}},\n // Master interface B channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_B_REG_TYPE = {M_COUNT{2'd0}},\n // Master interface AR channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},\n // Master interface R channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_R_REG_TYPE = {M_COUNT{2'd0}}\n)\n(\n input wire clk,\n input wire rst,\n\n /*\n * AXI slave interfaces\n */\n input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_awid,\n input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr,\n input wire [S_COUNT*8-1:0] s_axi_awlen,\n input wire [S_COUNT*3-1:0] s_axi_awsize,\n input wire [S_COUNT*2-1:0] s_axi_awburst,\n input wire [S_COUNT-1:0] s_axi_awlock,\n input wire [S_COUNT*4-1:0] s_axi_awcache,\n input wire [S_COUNT*3-1:0] s_axi_awprot,\n input wire [S_COUNT*4-1:0] s_axi_awqos,\n input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser,\n input wire [S_COUNT-1:0] s_axi_awvalid,\n output wire [S_COUNT-1:0] s_axi_awready,\n input wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata,\n input wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb,\n input wire [S_COUNT-1:0] s_axi_wlast,\n input wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser,\n input wire [S_COUNT-1:0] s_axi_wvalid,\n output wire [S_COUNT-1:0] s_axi_wready,\n output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_bid,\n output wire [S_COUNT*2-1:0] s_axi_bresp,\n output wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser,\n output wire [S_COUNT-1:0] s_axi_bvalid,\n input wire [S_COUNT-1:0] s_axi_bready,\n input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid,\n input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr,\n input wire [S_COUNT*8-1:0] s_axi_arlen,\n input wire [S_COUNT*3-1:0] s_axi_arsize,\n input wire [S_COUNT*2-1:0] s_axi_arburst,\n input wire [S_COUNT-1:0] s_axi_arlock,\n input wire [S_COUNT*4-1:0] s_axi_arcache,\n input wire [S_COUNT*3-1:0] s_axi_arprot,\n input wire [S_COUNT*4-1:0] s_axi_arqos,\n input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser,\n input wire [S_COUNT-1:0] s_axi_arvalid,\n output wire [S_COUNT-1:0] s_axi_arready,\n output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid,\n output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata,\n output wire [S_COUNT*2-1:0] s_axi_rresp,\n output wire [S_COUNT-1:0] s_axi_rlast,\n output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser,\n output wire [S_COUNT-1:0] s_axi_rvalid,\n input wire [S_COUNT-1:0] s_axi_rready,\n\n /*\n * AXI master interfaces\n */\n output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_awid,\n output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr,\n output wire [M_COUNT*8-1:0] m_axi_awlen,\n output wire [M_COUNT*3-1:0] m_axi_awsize,\n output wire [M_COUNT*2-1:0] m_axi_awburst,\n output wire [M_COUNT-1:0] m_axi_awlock,\n output wire [M_COUNT*4-1:0] m_axi_awcache,\n output wire [M_COUNT*3-1:0] m_axi_awprot,\n output wire [M_COUNT*4-1:0] m_axi_awqos,\n output wire [M_COUNT*4-1:0] m_axi_awregion,\n output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser,\n output wire [M_COUNT-1:0] m_axi_awvalid,\n input wire [M_COUNT-1:0] m_axi_awready,\n output wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata,\n output wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb,\n output wire [M_COUNT-1:0] m_axi_wlast,\n output wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser,\n output wire [M_COUNT-1:0] m_axi_wvalid,\n input wire [M_COUNT-1:0] m_axi_wready,\n input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_bid,\n input wire [M_COUNT*2-1:0] m_axi_bresp,\n input wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser,\n input wire [M_COUNT-1:0] m_axi_bvalid,\n output wire [M_COUNT-1:0] m_axi_bready,\n output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_arid,\n output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr,\n output wire [M_COUNT*8-1:0] m_axi_arlen,\n output wire [M_COUNT*3-1:0] m_axi_arsize,\n output wire [M_COUNT*2-1:0] m_axi_arburst,\n output wire [M_COUNT-1:0] m_axi_arlock,\n output wire [M_COUNT*4-1:0] m_axi_arcache,\n output wire [M_COUNT*3-1:0] m_axi_arprot,\n output wire [M_COUNT*4-1:0] m_axi_arqos,\n output wire [M_COUNT*4-1:0] m_axi_arregion,\n output wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser,\n output wire [M_COUNT-1:0] m_axi_arvalid,\n input wire [M_COUNT-1:0] m_axi_arready,\n input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_rid,\n input wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata,\n input wire [M_COUNT*2-1:0] m_axi_rresp,\n input wire [M_COUNT-1:0] m_axi_rlast,\n input wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser,\n input wire [M_COUNT-1:0] m_axi_rvalid,\n output wire [M_COUNT-1:0] m_axi_rready\n);\n\naxi_crossbar_wr #(\n .S_COUNT(S_COUNT),\n .M_COUNT(M_COUNT),\n .DATA_WIDTH(DATA_WIDTH),\n .ADDR_WIDTH(ADDR_WIDTH),\n .STRB_WIDTH(STRB_WIDTH),\n .S_ID_WIDTH(S_ID_WIDTH),\n .M_ID_WIDTH(M_ID_WIDTH),\n .AWUSER_ENABLE(AWUSER_ENABLE),\n .AWUSER_WIDTH(AWUSER_WIDTH),\n .WUSER_ENABLE(WUSER_ENABLE),\n .WUSER_WIDTH(WUSER_WIDTH),\n .BUSER_ENABLE(BUSER_ENABLE),\n .BUSER_WIDTH(BUSER_WIDTH),\n .S_THREADS(S_THREADS),\n .S_ACCEPT(S_ACCEPT),\n .M_REGIONS(M_REGIONS),\n .M_BASE_ADDR(M_BASE_ADDR),\n .M_ADDR_WIDTH(M_ADDR_WIDTH),\n .M_CONNECT(M_CONNECT_WRITE),\n .M_ISSUE(M_ISSUE),\n .M_SECURE(M_SECURE),\n .S_AW_REG_TYPE(S_AW_REG_TYPE),\n .S_W_REG_TYPE (S_W_REG_TYPE),\n .S_B_REG_TYPE (S_B_REG_TYPE)\n)\naxi_crossbar_wr_inst (\n .clk(clk),\n .rst(rst),\n\n /*\n * AXI slave interfaces\n */\n .s_axi_awid(s_axi_awid),\n .s_axi_awaddr(s_axi_awaddr),\n .s_axi_awlen(s_axi_awlen),\n .s_axi_awsize(s_axi_awsize),\n .s_axi_awburst(s_axi_awburst),\n .s_axi_awlock(s_axi_awlock),\n .s_axi_awcache(s_axi_awcache),\n .s_axi_awprot(s_axi_awprot),\n .s_axi_awqos(s_axi_awqos),\n .s_axi_awuser(s_axi_awuser),\n .s_axi_awvalid(s_axi_awvalid),\n .s_axi_awready(s_axi_awready),\n .s_axi_wdata(s_axi_wdata),\n .s_axi_wstrb(s_axi_wstrb),\n .s_axi_wlast(s_axi_wlast),\n .s_axi_wuser(s_axi_wuser),\n .s_axi_wvalid(s_axi_wvalid),\n .s_axi_wready(s_axi_wready),\n .s_axi_bid(s_axi_bid),\n .s_axi_bresp(s_axi_bresp),\n .s_axi_buser(s_axi_buser),\n .s_axi_bvalid(s_axi_bvalid),\n .s_axi_bready(s_axi_bready),\n\n /*\n * AXI master interfaces\n */\n .m_axi_awid(m_axi_awid),\n .m_axi_awaddr(m_axi_awaddr),\n .m_axi_awlen(m_axi_awlen),\n .m_axi_awsize(m_axi_awsize),\n .m_axi_awburst(m_axi_awburst),\n .m_axi_awlock(m_axi_awlock),\n .m_axi_awcache(m_axi_awcache),\n .m_axi_awprot(m_axi_awprot),\n .m_axi_awqos(m_axi_awqos),\n .m_axi_awregion(m_axi_awregion),\n .m_axi_awuser(m_axi_awuser),\n .m_axi_awvalid(m_axi_awvalid),\n .m_axi_awready(m_axi_awready),\n .m_axi_wdata(m_axi_wdata),\n .m_axi_wstrb(m_axi_wstrb),\n .m_axi_wlast(m_axi_wlast),\n .m_axi_wuser(m_axi_wuser),\n .m_axi_wvalid(m_axi_wvalid),\n .m_axi_wready(m_axi_wready),\n .m_axi_bid(m_axi_bid),\n .m_axi_bresp(m_axi_bresp),\n .m_axi_buser(m_axi_buser),\n .m_axi_bvalid(m_axi_bvalid),\n .m_axi_bready(m_axi_bready)\n);\n\naxi_crossbar_rd #(\n .S_COUNT(S_COUNT),\n .M_COUNT(M_COUNT),\n .DATA_WIDTH(DATA_WIDTH),\n .ADDR_WIDTH(ADDR_WIDTH),\n .STRB_WIDTH(STRB_WIDTH),\n .S_ID_WIDTH(S_ID_WIDTH),\n .M_ID_WIDTH(M_ID_WIDTH),\n .ARUSER_ENABLE(ARUSER_ENABLE),\n .ARUSER_WIDTH(ARUSER_WIDTH),\n .RUSER_ENABLE(RUSER_ENABLE),\n .RUSER_WIDTH(RUSER_WIDTH),\n .S_THREADS(S_THREADS),\n .S_ACCEPT(S_ACCEPT),\n .M_REGIONS(M_REGIONS),\n .M_BASE_ADDR(M_BASE_ADDR),\n .M_ADDR_WIDTH(M_ADDR_WIDTH),\n .M_CONNECT(M_CONNECT_READ),\n .M_ISSUE(M_ISSUE),\n .M_SECURE(M_SECURE),\n .S_AR_REG_TYPE(S_AR_REG_TYPE),\n .S_R_REG_TYPE (S_R_REG_TYPE)\n)\naxi_crossbar_rd_inst (\n .clk(clk),\n .rst(rst),\n\n /*\n * AXI slave interfaces\n */\n .s_axi_arid(s_axi_arid),\n .s_axi_araddr(s_axi_araddr),\n .s_axi_arlen(s_axi_arlen),\n .s_axi_arsize(s_axi_arsize),\n .s_axi_arburst(s_axi_arburst),\n .s_axi_arlock(s_axi_arlock),\n .s_axi_arcache(s_axi_arcache),\n .s_axi_arprot(s_axi_arprot),\n .s_axi_arqos(s_axi_arqos),\n .s_axi_aruser(s_axi_aruser),\n .s_axi_arvalid(s_axi_arvalid),\n .s_axi_arready(s_axi_arready),\n .s_axi_rid(s_axi_rid),\n .s_axi_rdata(s_axi_rdata),\n .s_axi_rresp(s_axi_rresp),\n .s_axi_rlast(s_axi_rlast),\n .s_axi_ruser(s_axi_ruser),\n .s_axi_rvalid(s_axi_rvalid),\n .s_axi_rready(s_axi_rready),\n\n /*\n * AXI master interfaces\n */\n .m_axi_arid(m_axi_arid),\n .m_axi_araddr(m_axi_araddr),\n .m_axi_arlen(m_axi_arlen),\n .m_axi_arsize(m_axi_arsize),\n .m_axi_arburst(m_axi_arburst),\n .m_axi_arlock(m_axi_arlock),\n .m_axi_arcache(m_axi_arcache),\n .m_axi_arprot(m_axi_arprot),\n .m_axi_arqos(m_axi_arqos),\n .m_axi_arregion(m_axi_arregion),\n .m_axi_aruser(m_axi_aruser),\n .m_axi_arvalid(m_axi_arvalid),\n .m_axi_arready(m_axi_arready),\n .m_axi_rid(m_axi_rid),\n .m_axi_rdata(m_axi_rdata),\n .m_axi_rresp(m_axi_rresp),\n .m_axi_rlast(m_axi_rlast),\n .m_axi_ruser(m_axi_ruser),\n .m_axi_rvalid(m_axi_rvalid),\n .m_axi_rready(m_axi_rready)\n);\n\nendmodule\n\n`resetall\n" }, { "path": "testbench/axi4_mux/axi_crossbar_addr.v", "content": "/*\n\nCopyright (c) 2018 Alex Forencich\nCopyright 2024 Antmicro \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n`default_nettype none\n\n/*\n * AXI4 crossbar address decode and admission control\n */\nmodule axi_crossbar_addr #\n(\n // Slave interface index\n parameter S = 0,\n // Number of AXI inputs (slave interfaces)\n parameter S_COUNT = 4,\n // Number of AXI outputs (master interfaces)\n parameter M_COUNT = 4,\n // Width of address bus in bits\n parameter ADDR_WIDTH = 32,\n // ID field width\n parameter ID_WIDTH = 8,\n // Number of concurrent unique IDs\n parameter S_THREADS = 32'd2,\n // Number of concurrent operations\n parameter S_ACCEPT = 32'd16,\n // Number of regions per master interface\n parameter M_REGIONS = 1,\n // Master interface base addresses\n // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits\n // set to zero for default addressing based on M_ADDR_WIDTH\n parameter M_BASE_ADDR = 0,\n // Master interface address widths\n // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits\n parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},\n // Connections between interfaces\n // M_COUNT concatenated fields of S_COUNT bits\n parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},\n // Secure master (fail operations based on awprot/arprot)\n // M_COUNT bits\n parameter M_SECURE = {M_COUNT{1'b0}},\n // Enable write command output\n parameter WC_OUTPUT = 0\n)\n(\n input wire clk,\n input wire rst,\n\n /*\n * Address input\n */\n input wire [ID_WIDTH-1:0] s_axi_aid,\n input wire [ADDR_WIDTH-1:0] s_axi_aaddr,\n input wire [2:0] s_axi_aprot,\n input wire [3:0] s_axi_aqos,\n input wire s_axi_avalid,\n output wire s_axi_aready,\n\n /*\n * Address output\n */\n output wire [3:0] m_axi_aregion,\n output wire [$clog2(M_COUNT)-1:0] m_select,\n output wire m_axi_avalid,\n input wire m_axi_aready,\n\n /*\n * Write command output\n */\n output wire [$clog2(M_COUNT)-1:0] m_wc_select,\n output wire m_wc_decerr,\n output wire m_wc_valid,\n input wire m_wc_ready,\n\n /*\n * Reply command output\n */\n output wire m_rc_decerr,\n output wire m_rc_valid,\n input wire m_rc_ready,\n\n /*\n * Completion input\n */\n input wire [ID_WIDTH-1:0] s_cpl_id,\n input wire s_cpl_valid\n);\n\nparameter CL_S_COUNT = $clog2(S_COUNT);\nparameter CL_M_COUNT = $clog2(M_COUNT);\n\nparameter S_INT_THREADS = S_THREADS > S_ACCEPT ? S_ACCEPT : S_THREADS;\nparameter CL_S_INT_THREADS = $clog2(S_INT_THREADS);\nparameter CL_S_ACCEPT = $clog2(S_ACCEPT);\n\n// default address computation\nfunction [M_COUNT*M_REGIONS*ADDR_WIDTH-1:0] calcBaseAddrs(input [31:0] dummy);\n integer i;\n reg [ADDR_WIDTH-1:0] base;\n reg [ADDR_WIDTH-1:0] width;\n reg [ADDR_WIDTH-1:0] size;\n reg [ADDR_WIDTH-1:0] mask;\n begin\n calcBaseAddrs = {M_COUNT*M_REGIONS*ADDR_WIDTH{1'b0}};\n base = 0;\n for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin\n width = M_ADDR_WIDTH[i*32 +: 32];\n mask = {ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - width);\n size = mask + 1;\n if (width > 0) begin\n if ((base & mask) != 0) begin\n base = base + size - (base & mask); // align\n end\n calcBaseAddrs[i * ADDR_WIDTH +: ADDR_WIDTH] = base;\n base = base + size; // increment\n end\n end\n end\nendfunction\n\nparameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0);\n\ninteger i, j;\n\n// check configuration\ninitial begin\n if (S_ACCEPT < 1) begin\n $error(\"Error: need at least 1 accept (instance %m)\");\n $finish;\n end\n\n if (S_THREADS < 1) begin\n $error(\"Error: need at least 1 thread (instance %m)\");\n $finish;\n end\n\n if (S_THREADS > S_ACCEPT) begin\n $warning(\"Warning: requested thread count larger than accept count; limiting thread count to accept count (instance %m)\");\n end\n\n if (M_REGIONS < 1) begin\n $error(\"Error: need at least 1 region (instance %m)\");\n $finish;\n end\n\n for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin\n if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin\n $error(\"Error: address width out of range (instance %m)\");\n $finish;\n end\n end\n\n $display(\"Addressing configuration for axi_crossbar_addr instance %m\");\n for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin\n if (M_ADDR_WIDTH[i*32 +: 32]) begin\n $display(\"%2d (%2d): %x / %02d -- %x-%x\",\n i/M_REGIONS, i%M_REGIONS,\n M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],\n M_ADDR_WIDTH[i*32 +: 32],\n M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),\n M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))\n );\n end\n end\n\n for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin\n if ((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & (2**M_ADDR_WIDTH[i*32 +: 32]-1)) != 0) begin\n $display(\"Region not aligned:\");\n $display(\"%2d (%2d): %x / %2d -- %x-%x\",\n i/M_REGIONS, i%M_REGIONS,\n M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],\n M_ADDR_WIDTH[i*32 +: 32],\n M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),\n M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))\n );\n $error(\"Error: address range not aligned (instance %m)\");\n $finish;\n end\n end\n\n for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin\n for (j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin\n if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin\n if (((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32]))))\n && ((M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32])) <= (M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))))) begin\n $display(\"Overlapping regions:\");\n $display(\"%2d (%2d): %x / %2d -- %x-%x\",\n i/M_REGIONS, i%M_REGIONS,\n M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],\n M_ADDR_WIDTH[i*32 +: 32],\n M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),\n M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))\n );\n $display(\"%2d (%2d): %x / %2d -- %x-%x\",\n j/M_REGIONS, j%M_REGIONS,\n M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH],\n M_ADDR_WIDTH[j*32 +: 32],\n M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]),\n M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32]))\n );\n $error(\"Error: address ranges overlap (instance %m)\");\n $finish;\n end\n end\n end\n end\nend\n\nlocalparam [2:0]\n STATE_IDLE = 3'd0,\n STATE_DECODE = 3'd1;\n\nreg [2:0] state_reg = STATE_IDLE, state_next;\n\nreg s_axi_aready_reg = 0, s_axi_aready_next;\n\nreg [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next;\nreg [CL_M_COUNT-1:0] m_select_reg = 0, m_select_next;\nreg m_axi_avalid_reg = 1'b0, m_axi_avalid_next;\nreg m_decerr_reg = 1'b0, m_decerr_next;\nreg m_wc_valid_reg = 1'b0, m_wc_valid_next;\nreg m_rc_valid_reg = 1'b0, m_rc_valid_next;\n\nassign s_axi_aready = s_axi_aready_reg;\n\nassign m_axi_aregion = m_axi_aregion_reg;\nassign m_select = m_select_reg;\nassign m_axi_avalid = m_axi_avalid_reg;\n\nassign m_wc_select = m_select_reg;\nassign m_wc_decerr = m_decerr_reg;\nassign m_wc_valid = m_wc_valid_reg;\n\nassign m_rc_decerr = m_decerr_reg;\nassign m_rc_valid = m_rc_valid_reg;\n\nreg match;\nreg trans_start;\nreg trans_complete;\n\nreg [$clog2(S_ACCEPT+1)-1:0] trans_count_reg = 0;\nwire trans_limit = trans_count_reg >= S_ACCEPT && !trans_complete;\n\n// transfer ID thread tracking\nreg [ID_WIDTH-1:0] thread_id_reg[S_INT_THREADS-1:0];\nreg [CL_M_COUNT-1:0] thread_m_reg[S_INT_THREADS-1:0];\nreg [3:0] thread_region_reg[S_INT_THREADS-1:0];\nreg [$clog2(S_ACCEPT+1)-1:0] thread_count_reg[S_INT_THREADS-1:0];\n\nwire [S_INT_THREADS-1:0] thread_active;\nwire [S_INT_THREADS-1:0] thread_match;\nwire [S_INT_THREADS-1:0] thread_match_dest;\nwire [S_INT_THREADS-1:0] thread_cpl_match;\nwire [S_INT_THREADS-1:0] thread_trans_start;\nwire [S_INT_THREADS-1:0] thread_trans_complete;\n\ngenerate\n genvar n;\n\n for (n = 0; n < S_INT_THREADS; n = n + 1) begin\n initial begin\n thread_count_reg[n] <= 0;\n end\n\n assign thread_active[n] = thread_count_reg[n] != 0;\n assign thread_match[n] = thread_active[n] && thread_id_reg[n] == s_axi_aid;\n assign thread_match_dest[n] = thread_match[n] && thread_m_reg[n] == m_select_next && (M_REGIONS < 2 || thread_region_reg[n] == m_axi_aregion_next);\n assign thread_cpl_match[n] = thread_active[n] && thread_id_reg[n] == s_cpl_id;\n assign thread_trans_start[n] = (thread_match[n] || (!thread_active[n] && !thread_match && !(thread_trans_start & ({S_INT_THREADS{1'b1}} >> (S_INT_THREADS-n))))) && trans_start;\n assign thread_trans_complete[n] = thread_cpl_match[n] && trans_complete;\n\n always @(posedge clk) begin\n if (rst) begin\n thread_count_reg[n] <= 0;\n end else begin\n if (thread_trans_start[n] && !thread_trans_complete[n]) begin\n thread_count_reg[n] <= thread_count_reg[n] + 1;\n end else if (!thread_trans_start[n] && thread_trans_complete[n]) begin\n thread_count_reg[n] <= thread_count_reg[n] - 1;\n end\n end\n\n if (thread_trans_start[n]) begin\n thread_id_reg[n] <= s_axi_aid;\n thread_m_reg[n] <= m_select_next;\n thread_region_reg[n] <= m_axi_aregion_next;\n end\n end\n end\nendgenerate\n\nalways @* begin\n state_next = STATE_IDLE;\n\n match = 1'b0;\n trans_start = 1'b0;\n trans_complete = 1'b0;\n\n s_axi_aready_next = 1'b0;\n\n m_axi_aregion_next = m_axi_aregion_reg;\n m_select_next = m_select_reg;\n m_axi_avalid_next = m_axi_avalid_reg && !m_axi_aready;\n m_decerr_next = m_decerr_reg;\n m_wc_valid_next = m_wc_valid_reg && !m_wc_ready;\n m_rc_valid_next = m_rc_valid_reg && !m_rc_ready;\n\n case (state_reg)\n STATE_IDLE: begin\n // idle state, store values\n s_axi_aready_next = 1'b0;\n\n if (s_axi_avalid && !s_axi_aready) begin\n match = 1'b0;\n for (i = 0; i < M_COUNT; i = i + 1) begin\n for (j = 0; j < M_REGIONS; j = j + 1) begin\n if (M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] && (!M_SECURE[i] || !s_axi_aprot[1]) && (M_CONNECT & (1 << (S+i*S_COUNT))) && (s_axi_aaddr >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32]) == (M_BASE_ADDR_INT[(i*M_REGIONS+j)*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32])) begin\n m_select_next = i;\n m_axi_aregion_next = j;\n match = 1'b1;\n end\n end\n end\n\n if (match) begin\n // address decode successful\n if (!trans_limit && (thread_match_dest || (!(&thread_active) && !thread_match))) begin\n // transaction limit not reached\n m_axi_avalid_next = 1'b1;\n m_decerr_next = 1'b0;\n m_wc_valid_next = WC_OUTPUT;\n m_rc_valid_next = 1'b0;\n trans_start = 1'b1;\n state_next = STATE_DECODE;\n end else begin\n // transaction limit reached; block in idle\n state_next = STATE_IDLE;\n end\n end else begin\n // decode error\n m_axi_avalid_next = 1'b0;\n m_decerr_next = 1'b1;\n m_wc_valid_next = WC_OUTPUT;\n m_rc_valid_next = 1'b1;\n state_next = STATE_DECODE;\n end\n end else begin\n state_next = STATE_IDLE;\n end\n end\n STATE_DECODE: begin\n if (!m_axi_avalid_next && (!m_wc_valid_next || !WC_OUTPUT) && !m_rc_valid_next) begin\n s_axi_aready_next = 1'b1;\n state_next = STATE_IDLE;\n end else begin\n state_next = STATE_DECODE;\n end\n end\n endcase\n\n // manage completions\n trans_complete = s_cpl_valid;\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n state_reg <= STATE_IDLE;\n s_axi_aready_reg <= 1'b0;\n m_axi_avalid_reg <= 1'b0;\n m_wc_valid_reg <= 1'b0;\n m_rc_valid_reg <= 1'b0;\n\n trans_count_reg <= 0;\n end else begin\n state_reg <= state_next;\n s_axi_aready_reg <= s_axi_aready_next;\n m_axi_avalid_reg <= m_axi_avalid_next;\n m_wc_valid_reg <= m_wc_valid_next;\n m_rc_valid_reg <= m_rc_valid_next;\n\n if (trans_start && !trans_complete) begin\n trans_count_reg <= trans_count_reg + 1;\n end else if (!trans_start && trans_complete) begin\n trans_count_reg <= trans_count_reg - 1;\n end\n end\n\n m_axi_aregion_reg <= m_axi_aregion_next;\n m_select_reg <= m_select_next;\n m_decerr_reg <= m_decerr_next;\nend\n\nendmodule\n\n`resetall\n" }, { "path": "testbench/axi4_mux/axi_crossbar_rd.v", "content": "/*\n\nCopyright (c) 2018 Alex Forencich\nCopyright 2024 Antmicro \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n`default_nettype none\n\n/*\n * AXI4 crossbar (read)\n */\nmodule axi_crossbar_rd #\n(\n // Number of AXI inputs (slave interfaces)\n parameter S_COUNT = 4,\n // Number of AXI outputs (master interfaces)\n parameter M_COUNT = 4,\n // Width of data bus in bits\n parameter DATA_WIDTH = 32,\n // Width of address bus in bits\n parameter ADDR_WIDTH = 32,\n // Width of wstrb (width of data bus in words)\n parameter STRB_WIDTH = (DATA_WIDTH/8),\n // Input ID field width (from AXI masters)\n parameter S_ID_WIDTH = 8,\n // Output ID field width (towards AXI slaves)\n // Additional bits required for response routing\n parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),\n // Propagate aruser signal\n parameter ARUSER_ENABLE = 0,\n // Width of aruser signal\n parameter ARUSER_WIDTH = 1,\n // Propagate ruser signal\n parameter RUSER_ENABLE = 0,\n // Width of ruser signal\n parameter RUSER_WIDTH = 1,\n // Number of concurrent unique IDs for each slave interface\n // S_COUNT concatenated fields of 32 bits\n parameter S_THREADS = {S_COUNT{32'd2}},\n // Number of concurrent operations for each slave interface\n // S_COUNT concatenated fields of 32 bits\n parameter S_ACCEPT = {S_COUNT{32'd16}},\n // Number of regions per master interface\n parameter M_REGIONS = 1,\n // Master interface base addresses\n // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits\n // set to zero for default addressing based on M_ADDR_WIDTH\n parameter M_BASE_ADDR = 0,\n // Master interface address widths\n // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits\n parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},\n // Read connections between interfaces\n // M_COUNT concatenated fields of S_COUNT bits\n parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},\n // Number of concurrent operations for each master interface\n // M_COUNT concatenated fields of 32 bits\n parameter M_ISSUE = {M_COUNT{32'd4}},\n // Secure master (fail operations based on awprot/arprot)\n // M_COUNT bits\n parameter M_SECURE = {M_COUNT{1'b0}},\n // Slave interface AR channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},\n // Slave interface R channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_R_REG_TYPE = {S_COUNT{2'd2}},\n // Master interface AR channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},\n // Master interface R channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_R_REG_TYPE = {M_COUNT{2'd0}}\n)\n(\n input wire clk,\n input wire rst,\n\n /*\n * AXI slave interfaces\n */\n input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid,\n input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr,\n input wire [S_COUNT*8-1:0] s_axi_arlen,\n input wire [S_COUNT*3-1:0] s_axi_arsize,\n input wire [S_COUNT*2-1:0] s_axi_arburst,\n input wire [S_COUNT-1:0] s_axi_arlock,\n input wire [S_COUNT*4-1:0] s_axi_arcache,\n input wire [S_COUNT*3-1:0] s_axi_arprot,\n input wire [S_COUNT*4-1:0] s_axi_arqos,\n input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser,\n input wire [S_COUNT-1:0] s_axi_arvalid,\n output wire [S_COUNT-1:0] s_axi_arready,\n output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid,\n output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata,\n output wire [S_COUNT*2-1:0] s_axi_rresp,\n output wire [S_COUNT-1:0] s_axi_rlast,\n output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser,\n output wire [S_COUNT-1:0] s_axi_rvalid,\n input wire [S_COUNT-1:0] s_axi_rready,\n\n /*\n * AXI master interfaces\n */\n output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_arid,\n output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr,\n output wire [M_COUNT*8-1:0] m_axi_arlen,\n output wire [M_COUNT*3-1:0] m_axi_arsize,\n output wire [M_COUNT*2-1:0] m_axi_arburst,\n output wire [M_COUNT-1:0] m_axi_arlock,\n output wire [M_COUNT*4-1:0] m_axi_arcache,\n output wire [M_COUNT*3-1:0] m_axi_arprot,\n output wire [M_COUNT*4-1:0] m_axi_arqos,\n output wire [M_COUNT*4-1:0] m_axi_arregion,\n output wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser,\n output wire [M_COUNT-1:0] m_axi_arvalid,\n input wire [M_COUNT-1:0] m_axi_arready,\n input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_rid,\n input wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata,\n input wire [M_COUNT*2-1:0] m_axi_rresp,\n input wire [M_COUNT-1:0] m_axi_rlast,\n input wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser,\n input wire [M_COUNT-1:0] m_axi_rvalid,\n output wire [M_COUNT-1:0] m_axi_rready\n);\n\nparameter CL_S_COUNT = $clog2(S_COUNT);\nparameter CL_M_COUNT = $clog2(M_COUNT);\nparameter M_COUNT_P1 = M_COUNT+1;\nparameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);\n\ninteger i;\n\n// check configuration\ninitial begin\n if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin\n $error(\"Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)\");\n $finish;\n end\n\n for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin\n if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin\n $error(\"Error: value out of range (instance %m)\");\n $finish;\n end\n end\nend\n\nwire [S_COUNT*S_ID_WIDTH-1:0] int_s_axi_arid;\nwire [S_COUNT*ADDR_WIDTH-1:0] int_s_axi_araddr;\nwire [S_COUNT*8-1:0] int_s_axi_arlen;\nwire [S_COUNT*3-1:0] int_s_axi_arsize;\nwire [S_COUNT*2-1:0] int_s_axi_arburst;\nwire [S_COUNT-1:0] int_s_axi_arlock;\nwire [S_COUNT*4-1:0] int_s_axi_arcache;\nwire [S_COUNT*3-1:0] int_s_axi_arprot;\nwire [S_COUNT*4-1:0] int_s_axi_arqos;\nwire [S_COUNT*4-1:0] int_s_axi_arregion;\nwire [S_COUNT*ARUSER_WIDTH-1:0] int_s_axi_aruser;\nwire [S_COUNT-1:0] int_s_axi_arvalid;\nwire [S_COUNT-1:0] int_s_axi_arready;\n\nwire [S_COUNT*M_COUNT-1:0] int_axi_arvalid;\nwire [M_COUNT*S_COUNT-1:0] int_axi_arready;\n\nwire [M_COUNT*M_ID_WIDTH-1:0] int_m_axi_rid;\nwire [M_COUNT*DATA_WIDTH-1:0] int_m_axi_rdata;\nwire [M_COUNT*2-1:0] int_m_axi_rresp;\nwire [M_COUNT-1:0] int_m_axi_rlast;\nwire [M_COUNT*RUSER_WIDTH-1:0] int_m_axi_ruser;\nwire [M_COUNT-1:0] int_m_axi_rvalid;\nwire [M_COUNT-1:0] int_m_axi_rready;\n\nwire [M_COUNT*S_COUNT-1:0] int_axi_rvalid;\nwire [S_COUNT*M_COUNT-1:0] int_axi_rready;\n\ngenerate\n\n genvar m, n;\n\n for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces\n // address decode and admission control\n wire [CL_M_COUNT-1:0] a_select;\n\n wire m_axi_avalid;\n wire m_axi_aready;\n\n wire m_rc_decerr;\n wire m_rc_valid;\n wire m_rc_ready;\n\n wire [S_ID_WIDTH-1:0] s_cpl_id;\n wire s_cpl_valid;\n\n axi_crossbar_addr #(\n .S(m),\n .S_COUNT(S_COUNT),\n .M_COUNT(M_COUNT),\n .ADDR_WIDTH(ADDR_WIDTH),\n .ID_WIDTH(S_ID_WIDTH),\n .S_THREADS(S_THREADS[m*32 +: 32]),\n .S_ACCEPT(S_ACCEPT[m*32 +: 32]),\n .M_REGIONS(M_REGIONS),\n .M_BASE_ADDR(M_BASE_ADDR),\n .M_ADDR_WIDTH(M_ADDR_WIDTH),\n .M_CONNECT(M_CONNECT),\n .M_SECURE(M_SECURE),\n .WC_OUTPUT(0)\n )\n addr_inst (\n .clk(clk),\n .rst(rst),\n\n /*\n * Address input\n */\n .s_axi_aid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),\n .s_axi_aaddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),\n .s_axi_aprot(int_s_axi_arprot[m*3 +: 3]),\n .s_axi_aqos(int_s_axi_arqos[m*4 +: 4]),\n .s_axi_avalid(int_s_axi_arvalid[m]),\n .s_axi_aready(int_s_axi_arready[m]),\n\n /*\n * Address output\n */\n .m_axi_aregion(int_s_axi_arregion[m*4 +: 4]),\n .m_select(a_select),\n .m_axi_avalid(m_axi_avalid),\n .m_axi_aready(m_axi_aready),\n\n /*\n * Write command output\n */\n .m_wc_select(),\n .m_wc_decerr(),\n .m_wc_valid(),\n .m_wc_ready(1'b1),\n\n /*\n * Response command output\n */\n .m_rc_decerr(m_rc_decerr),\n .m_rc_valid(m_rc_valid),\n .m_rc_ready(m_rc_ready),\n\n /*\n * Completion input\n */\n .s_cpl_id(s_cpl_id),\n .s_cpl_valid(s_cpl_valid)\n );\n\n assign int_axi_arvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select;\n assign m_axi_aready = int_axi_arready[a_select*S_COUNT+m];\n\n // decode error handling\n reg [S_ID_WIDTH-1:0] decerr_m_axi_rid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_rid_next;\n reg decerr_m_axi_rlast_reg = 1'b0, decerr_m_axi_rlast_next;\n reg decerr_m_axi_rvalid_reg = 1'b0, decerr_m_axi_rvalid_next;\n wire decerr_m_axi_rready;\n\n reg [7:0] decerr_len_reg = 8'd0, decerr_len_next;\n\n assign m_rc_ready = !decerr_m_axi_rvalid_reg;\n\n always @* begin\n decerr_len_next = decerr_len_reg;\n decerr_m_axi_rid_next = decerr_m_axi_rid_reg;\n decerr_m_axi_rlast_next = decerr_m_axi_rlast_reg;\n decerr_m_axi_rvalid_next = decerr_m_axi_rvalid_reg;\n\n if (decerr_m_axi_rvalid_reg) begin\n if (decerr_m_axi_rready) begin\n if (decerr_len_reg > 0) begin\n decerr_len_next = decerr_len_reg-1;\n decerr_m_axi_rlast_next = (decerr_len_next == 0);\n decerr_m_axi_rvalid_next = 1'b1;\n end else begin\n decerr_m_axi_rvalid_next = 1'b0;\n end\n end\n end else if (m_rc_valid && m_rc_ready) begin\n decerr_len_next = int_s_axi_arlen[m*8 +: 8];\n decerr_m_axi_rid_next = int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH];\n decerr_m_axi_rlast_next = (decerr_len_next == 0);\n decerr_m_axi_rvalid_next = 1'b1;\n end\n end\n\n always @(posedge clk) begin\n if (rst) begin\n decerr_m_axi_rvalid_reg <= 1'b0;\n end else begin\n decerr_m_axi_rvalid_reg <= decerr_m_axi_rvalid_next;\n end\n\n decerr_m_axi_rid_reg <= decerr_m_axi_rid_next;\n decerr_m_axi_rlast_reg <= decerr_m_axi_rlast_next;\n decerr_len_reg <= decerr_len_next;\n end\n\n // read response arbitration\n wire [M_COUNT_P1-1:0] r_request;\n wire [M_COUNT_P1-1:0] r_acknowledge;\n wire [M_COUNT_P1-1:0] r_grant;\n wire r_grant_valid;\n wire [CL_M_COUNT_P1-1:0] r_grant_encoded;\n\n arbiter #(\n .PORTS(M_COUNT_P1),\n .ARB_TYPE_ROUND_ROBIN(1),\n .ARB_BLOCK(1),\n .ARB_BLOCK_ACK(1),\n .ARB_LSB_HIGH_PRIORITY(1)\n )\n r_arb_inst (\n .clk(clk),\n .rst(rst),\n .request(r_request),\n .acknowledge(r_acknowledge),\n .grant(r_grant),\n .grant_valid(r_grant_valid),\n .grant_encoded(r_grant_encoded)\n );\n\n // read response mux\n wire [S_ID_WIDTH-1:0] m_axi_rid_mux = {decerr_m_axi_rid_reg, int_m_axi_rid} >> r_grant_encoded*M_ID_WIDTH;\n wire [DATA_WIDTH-1:0] m_axi_rdata_mux = {{DATA_WIDTH{1'b0}}, int_m_axi_rdata} >> r_grant_encoded*DATA_WIDTH;\n wire [1:0] m_axi_rresp_mux = {2'b11, int_m_axi_rresp} >> r_grant_encoded*2;\n wire m_axi_rlast_mux = {decerr_m_axi_rlast_reg, int_m_axi_rlast} >> r_grant_encoded;\n wire [RUSER_WIDTH-1:0] m_axi_ruser_mux = {{RUSER_WIDTH{1'b0}}, int_m_axi_ruser} >> r_grant_encoded*RUSER_WIDTH;\n wire m_axi_rvalid_mux = ({decerr_m_axi_rvalid_reg, int_m_axi_rvalid} >> r_grant_encoded) & r_grant_valid;\n wire m_axi_rready_mux;\n\n assign int_axi_rready[m*M_COUNT +: M_COUNT] = (r_grant_valid && m_axi_rready_mux) << r_grant_encoded;\n assign decerr_m_axi_rready = (r_grant_valid && m_axi_rready_mux) && (r_grant_encoded == M_COUNT_P1-1);\n\n for (n = 0; n < M_COUNT; n = n + 1) begin\n assign r_request[n] = int_axi_rvalid[n*S_COUNT+m] && !r_grant[n];\n assign r_acknowledge[n] = r_grant[n] && int_axi_rvalid[n*S_COUNT+m] && m_axi_rlast_mux && m_axi_rready_mux;\n end\n\n assign r_request[M_COUNT_P1-1] = decerr_m_axi_rvalid_reg && !r_grant[M_COUNT_P1-1];\n assign r_acknowledge[M_COUNT_P1-1] = r_grant[M_COUNT_P1-1] && decerr_m_axi_rvalid_reg && decerr_m_axi_rlast_reg && m_axi_rready_mux;\n\n assign s_cpl_id = m_axi_rid_mux;\n assign s_cpl_valid = m_axi_rvalid_mux && m_axi_rready_mux && m_axi_rlast_mux;\n\n // S side register\n axi_register_rd #(\n .DATA_WIDTH(DATA_WIDTH),\n .ADDR_WIDTH(ADDR_WIDTH),\n .STRB_WIDTH(STRB_WIDTH),\n .ID_WIDTH(S_ID_WIDTH),\n .ARUSER_ENABLE(ARUSER_ENABLE),\n .ARUSER_WIDTH(ARUSER_WIDTH),\n .RUSER_ENABLE(RUSER_ENABLE),\n .RUSER_WIDTH(RUSER_WIDTH),\n .AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]),\n .R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2])\n )\n reg_inst (\n .clk(clk),\n .rst(rst),\n .s_axi_arid(s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),\n .s_axi_araddr(s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),\n .s_axi_arlen(s_axi_arlen[m*8 +: 8]),\n .s_axi_arsize(s_axi_arsize[m*3 +: 3]),\n .s_axi_arburst(s_axi_arburst[m*2 +: 2]),\n .s_axi_arlock(s_axi_arlock[m]),\n .s_axi_arcache(s_axi_arcache[m*4 +: 4]),\n .s_axi_arprot(s_axi_arprot[m*3 +: 3]),\n .s_axi_arqos(s_axi_arqos[m*4 +: 4]),\n .s_axi_arregion(4'd0),\n .s_axi_aruser(s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]),\n .s_axi_arvalid(s_axi_arvalid[m]),\n .s_axi_arready(s_axi_arready[m]),\n .s_axi_rid(s_axi_rid[m*S_ID_WIDTH +: S_ID_WIDTH]),\n .s_axi_rdata(s_axi_rdata[m*DATA_WIDTH +: DATA_WIDTH]),\n .s_axi_rresp(s_axi_rresp[m*2 +: 2]),\n .s_axi_rlast(s_axi_rlast[m]),\n .s_axi_ruser(s_axi_ruser[m*RUSER_WIDTH +: RUSER_WIDTH]),\n .s_axi_rvalid(s_axi_rvalid[m]),\n .s_axi_rready(s_axi_rready[m]),\n .m_axi_arid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),\n .m_axi_araddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),\n .m_axi_arlen(int_s_axi_arlen[m*8 +: 8]),\n .m_axi_arsize(int_s_axi_arsize[m*3 +: 3]),\n .m_axi_arburst(int_s_axi_arburst[m*2 +: 2]),\n .m_axi_arlock(int_s_axi_arlock[m]),\n .m_axi_arcache(int_s_axi_arcache[m*4 +: 4]),\n .m_axi_arprot(int_s_axi_arprot[m*3 +: 3]),\n .m_axi_arqos(int_s_axi_arqos[m*4 +: 4]),\n .m_axi_arregion(),\n .m_axi_aruser(int_s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]),\n .m_axi_arvalid(int_s_axi_arvalid[m]),\n .m_axi_arready(int_s_axi_arready[m]),\n .m_axi_rid(m_axi_rid_mux),\n .m_axi_rdata(m_axi_rdata_mux),\n .m_axi_rresp(m_axi_rresp_mux),\n .m_axi_rlast(m_axi_rlast_mux),\n .m_axi_ruser(m_axi_ruser_mux),\n .m_axi_rvalid(m_axi_rvalid_mux),\n .m_axi_rready(m_axi_rready_mux)\n );\n end // s_ifaces\n\n for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces\n // in-flight transaction count\n wire trans_start;\n wire trans_complete;\n reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;\n\n wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;\n\n always @(posedge clk) begin\n if (rst) begin\n trans_count_reg <= 0;\n end else begin\n if (trans_start && !trans_complete) begin\n trans_count_reg <= trans_count_reg + 1;\n end else if (!trans_start && trans_complete) begin\n trans_count_reg <= trans_count_reg - 1;\n end\n end\n end\n\n // address arbitration\n wire [S_COUNT-1:0] a_request;\n wire [S_COUNT-1:0] a_acknowledge;\n wire [S_COUNT-1:0] a_grant;\n wire a_grant_valid;\n wire [CL_S_COUNT-1:0] a_grant_encoded;\n\n arbiter #(\n .PORTS(S_COUNT),\n .ARB_TYPE_ROUND_ROBIN(1),\n .ARB_BLOCK(1),\n .ARB_BLOCK_ACK(1),\n .ARB_LSB_HIGH_PRIORITY(1)\n )\n a_arb_inst (\n .clk(clk),\n .rst(rst),\n .request(a_request),\n .acknowledge(a_acknowledge),\n .grant(a_grant),\n .grant_valid(a_grant_valid),\n .grant_encoded(a_grant_encoded)\n );\n\n // address mux\n wire [M_ID_WIDTH-1:0] s_axi_arid_mux = int_s_axi_arid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);\n wire [ADDR_WIDTH-1:0] s_axi_araddr_mux = int_s_axi_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];\n wire [7:0] s_axi_arlen_mux = int_s_axi_arlen[a_grant_encoded*8 +: 8];\n wire [2:0] s_axi_arsize_mux = int_s_axi_arsize[a_grant_encoded*3 +: 3];\n wire [1:0] s_axi_arburst_mux = int_s_axi_arburst[a_grant_encoded*2 +: 2];\n wire s_axi_arlock_mux = int_s_axi_arlock[a_grant_encoded];\n wire [3:0] s_axi_arcache_mux = int_s_axi_arcache[a_grant_encoded*4 +: 4];\n wire [2:0] s_axi_arprot_mux = int_s_axi_arprot[a_grant_encoded*3 +: 3];\n wire [3:0] s_axi_arqos_mux = int_s_axi_arqos[a_grant_encoded*4 +: 4];\n wire [3:0] s_axi_arregion_mux = int_s_axi_arregion[a_grant_encoded*4 +: 4];\n wire [ARUSER_WIDTH-1:0] s_axi_aruser_mux = int_s_axi_aruser[a_grant_encoded*ARUSER_WIDTH +: ARUSER_WIDTH];\n wire s_axi_arvalid_mux = int_axi_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;\n wire s_axi_arready_mux;\n\n assign int_axi_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_arready_mux) << a_grant_encoded;\n\n for (m = 0; m < S_COUNT; m = m + 1) begin\n assign a_request[m] = int_axi_arvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit;\n assign a_acknowledge[m] = a_grant[m] && int_axi_arvalid[m*M_COUNT+n] && s_axi_arready_mux;\n end\n\n assign trans_start = s_axi_arvalid_mux && s_axi_arready_mux && a_grant_valid;\n\n // read response forwarding\n wire [CL_S_COUNT-1:0] r_select = m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;\n\n assign int_axi_rvalid[n*S_COUNT +: S_COUNT] = int_m_axi_rvalid[n] << r_select;\n assign int_m_axi_rready[n] = int_axi_rready[r_select*M_COUNT+n];\n\n assign trans_complete = int_m_axi_rvalid[n] && int_m_axi_rready[n] && int_m_axi_rlast[n];\n\n // M side register\n axi_register_rd #(\n .DATA_WIDTH(DATA_WIDTH),\n .ADDR_WIDTH(ADDR_WIDTH),\n .STRB_WIDTH(STRB_WIDTH),\n .ID_WIDTH(M_ID_WIDTH),\n .ARUSER_ENABLE(ARUSER_ENABLE),\n .ARUSER_WIDTH(ARUSER_WIDTH),\n .RUSER_ENABLE(RUSER_ENABLE),\n .RUSER_WIDTH(RUSER_WIDTH),\n .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),\n .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])\n )\n reg_inst (\n .clk(clk),\n .rst(rst),\n .s_axi_arid(s_axi_arid_mux),\n .s_axi_araddr(s_axi_araddr_mux),\n .s_axi_arlen(s_axi_arlen_mux),\n .s_axi_arsize(s_axi_arsize_mux),\n .s_axi_arburst(s_axi_arburst_mux),\n .s_axi_arlock(s_axi_arlock_mux),\n .s_axi_arcache(s_axi_arcache_mux),\n .s_axi_arprot(s_axi_arprot_mux),\n .s_axi_arqos(s_axi_arqos_mux),\n .s_axi_arregion(s_axi_arregion_mux),\n .s_axi_aruser(s_axi_aruser_mux),\n .s_axi_arvalid(s_axi_arvalid_mux),\n .s_axi_arready(s_axi_arready_mux),\n .s_axi_rid(int_m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),\n .s_axi_rdata(int_m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),\n .s_axi_rresp(int_m_axi_rresp[n*2 +: 2]),\n .s_axi_rlast(int_m_axi_rlast[n]),\n .s_axi_ruser(int_m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),\n .s_axi_rvalid(int_m_axi_rvalid[n]),\n .s_axi_rready(int_m_axi_rready[n]),\n .m_axi_arid(m_axi_arid[n*M_ID_WIDTH +: M_ID_WIDTH]),\n .m_axi_araddr(m_axi_araddr[n*ADDR_WIDTH +: ADDR_WIDTH]),\n .m_axi_arlen(m_axi_arlen[n*8 +: 8]),\n .m_axi_arsize(m_axi_arsize[n*3 +: 3]),\n .m_axi_arburst(m_axi_arburst[n*2 +: 2]),\n .m_axi_arlock(m_axi_arlock[n]),\n .m_axi_arcache(m_axi_arcache[n*4 +: 4]),\n .m_axi_arprot(m_axi_arprot[n*3 +: 3]),\n .m_axi_arqos(m_axi_arqos[n*4 +: 4]),\n .m_axi_arregion(m_axi_arregion[n*4 +: 4]),\n .m_axi_aruser(m_axi_aruser[n*ARUSER_WIDTH +: ARUSER_WIDTH]),\n .m_axi_arvalid(m_axi_arvalid[n]),\n .m_axi_arready(m_axi_arready[n]),\n .m_axi_rid(m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),\n .m_axi_rdata(m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),\n .m_axi_rresp(m_axi_rresp[n*2 +: 2]),\n .m_axi_rlast(m_axi_rlast[n]),\n .m_axi_ruser(m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),\n .m_axi_rvalid(m_axi_rvalid[n]),\n .m_axi_rready(m_axi_rready[n])\n );\n end // m_ifaces\n\nendgenerate\n\nendmodule\n\n`resetall\n" }, { "path": "testbench/axi4_mux/axi_crossbar_wr.v", "content": "/*\n\nCopyright (c) 2018 Alex Forencich\nCopyright 2024 Antmicro \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n`default_nettype none\n\n/*\n * AXI4 crossbar (write)\n */\nmodule axi_crossbar_wr #\n(\n // Number of AXI inputs (slave interfaces)\n parameter S_COUNT = 4,\n // Number of AXI outputs (master interfaces)\n parameter M_COUNT = 4,\n // Width of data bus in bits\n parameter DATA_WIDTH = 32,\n // Width of address bus in bits\n parameter ADDR_WIDTH = 32,\n // Width of wstrb (width of data bus in words)\n parameter STRB_WIDTH = (DATA_WIDTH/8),\n // Input ID field width (from AXI masters)\n parameter S_ID_WIDTH = 8,\n // Output ID field width (towards AXI slaves)\n // Additional bits required for response routing\n parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),\n // Propagate awuser signal\n parameter AWUSER_ENABLE = 0,\n // Width of awuser signal\n parameter AWUSER_WIDTH = 1,\n // Propagate wuser signal\n parameter WUSER_ENABLE = 0,\n // Width of wuser signal\n parameter WUSER_WIDTH = 1,\n // Propagate buser signal\n parameter BUSER_ENABLE = 0,\n // Width of buser signal\n parameter BUSER_WIDTH = 1,\n // Number of concurrent unique IDs for each slave interface\n // S_COUNT concatenated fields of 32 bits\n parameter S_THREADS = {S_COUNT{32'd2}},\n // Number of concurrent operations for each slave interface\n // S_COUNT concatenated fields of 32 bits\n parameter S_ACCEPT = {S_COUNT{32'd16}},\n // Number of regions per master interface\n parameter M_REGIONS = 1,\n // Master interface base addresses\n // M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits\n // set to zero for default addressing based on M_ADDR_WIDTH\n parameter M_BASE_ADDR = 0,\n // Master interface address widths\n // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits\n parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},\n // Write connections between interfaces\n // M_COUNT concatenated fields of S_COUNT bits\n parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},\n // Number of concurrent operations for each master interface\n // M_COUNT concatenated fields of 32 bits\n parameter M_ISSUE = {M_COUNT{32'd4}},\n // Secure master (fail operations based on awprot/arprot)\n // M_COUNT bits\n parameter M_SECURE = {M_COUNT{1'b0}},\n // Slave interface AW channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_AW_REG_TYPE = {S_COUNT{2'd0}},\n // Slave interface W channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_W_REG_TYPE = {S_COUNT{2'd0}},\n // Slave interface B channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S_B_REG_TYPE = {S_COUNT{2'd1}},\n // Master interface AW channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},\n // Master interface W channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_W_REG_TYPE = {M_COUNT{2'd2}},\n // Master interface B channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M_B_REG_TYPE = {M_COUNT{2'd0}}\n)\n(\n input wire clk,\n input wire rst,\n\n /*\n * AXI slave interfaces\n */\n input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_awid,\n input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr,\n input wire [S_COUNT*8-1:0] s_axi_awlen,\n input wire [S_COUNT*3-1:0] s_axi_awsize,\n input wire [S_COUNT*2-1:0] s_axi_awburst,\n input wire [S_COUNT-1:0] s_axi_awlock,\n input wire [S_COUNT*4-1:0] s_axi_awcache,\n input wire [S_COUNT*3-1:0] s_axi_awprot,\n input wire [S_COUNT*4-1:0] s_axi_awqos,\n input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser,\n input wire [S_COUNT-1:0] s_axi_awvalid,\n output wire [S_COUNT-1:0] s_axi_awready,\n input wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata,\n input wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb,\n input wire [S_COUNT-1:0] s_axi_wlast,\n input wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser,\n input wire [S_COUNT-1:0] s_axi_wvalid,\n output wire [S_COUNT-1:0] s_axi_wready,\n output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_bid,\n output wire [S_COUNT*2-1:0] s_axi_bresp,\n output wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser,\n output wire [S_COUNT-1:0] s_axi_bvalid,\n input wire [S_COUNT-1:0] s_axi_bready,\n\n /*\n * AXI master interfaces\n */\n output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_awid,\n output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr,\n output wire [M_COUNT*8-1:0] m_axi_awlen,\n output wire [M_COUNT*3-1:0] m_axi_awsize,\n output wire [M_COUNT*2-1:0] m_axi_awburst,\n output wire [M_COUNT-1:0] m_axi_awlock,\n output wire [M_COUNT*4-1:0] m_axi_awcache,\n output wire [M_COUNT*3-1:0] m_axi_awprot,\n output wire [M_COUNT*4-1:0] m_axi_awqos,\n output wire [M_COUNT*4-1:0] m_axi_awregion,\n output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser,\n output wire [M_COUNT-1:0] m_axi_awvalid,\n input wire [M_COUNT-1:0] m_axi_awready,\n output wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata,\n output wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb,\n output wire [M_COUNT-1:0] m_axi_wlast,\n output wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser,\n output wire [M_COUNT-1:0] m_axi_wvalid,\n input wire [M_COUNT-1:0] m_axi_wready,\n input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_bid,\n input wire [M_COUNT*2-1:0] m_axi_bresp,\n input wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser,\n input wire [M_COUNT-1:0] m_axi_bvalid,\n output wire [M_COUNT-1:0] m_axi_bready\n);\n\nparameter CL_S_COUNT = $clog2(S_COUNT);\nparameter CL_M_COUNT = $clog2(M_COUNT);\nparameter M_COUNT_P1 = M_COUNT+1;\nparameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);\n\ninteger i;\n\n// check configuration\ninitial begin\n if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin\n $error(\"Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)\");\n $finish;\n end\n\n for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin\n if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin\n $error(\"Error: value out of range (instance %m)\");\n $finish;\n end\n end\nend\n\nwire [S_COUNT*S_ID_WIDTH-1:0] int_s_axi_awid;\nwire [S_COUNT*ADDR_WIDTH-1:0] int_s_axi_awaddr;\nwire [S_COUNT*8-1:0] int_s_axi_awlen;\nwire [S_COUNT*3-1:0] int_s_axi_awsize;\nwire [S_COUNT*2-1:0] int_s_axi_awburst;\nwire [S_COUNT-1:0] int_s_axi_awlock;\nwire [S_COUNT*4-1:0] int_s_axi_awcache;\nwire [S_COUNT*3-1:0] int_s_axi_awprot;\nwire [S_COUNT*4-1:0] int_s_axi_awqos;\nwire [S_COUNT*4-1:0] int_s_axi_awregion;\nwire [S_COUNT*AWUSER_WIDTH-1:0] int_s_axi_awuser;\nwire [S_COUNT-1:0] int_s_axi_awvalid;\nwire [S_COUNT-1:0] int_s_axi_awready;\n\nwire [S_COUNT*M_COUNT-1:0] int_axi_awvalid;\nwire [M_COUNT*S_COUNT-1:0] int_axi_awready;\n\nwire [S_COUNT*DATA_WIDTH-1:0] int_s_axi_wdata;\nwire [S_COUNT*STRB_WIDTH-1:0] int_s_axi_wstrb;\nwire [S_COUNT-1:0] int_s_axi_wlast;\nwire [S_COUNT*WUSER_WIDTH-1:0] int_s_axi_wuser;\nwire [S_COUNT-1:0] int_s_axi_wvalid;\nwire [S_COUNT-1:0] int_s_axi_wready;\n\nwire [S_COUNT*M_COUNT-1:0] int_axi_wvalid;\nwire [M_COUNT*S_COUNT-1:0] int_axi_wready;\n\nwire [M_COUNT*M_ID_WIDTH-1:0] int_m_axi_bid;\nwire [M_COUNT*2-1:0] int_m_axi_bresp;\nwire [M_COUNT*BUSER_WIDTH-1:0] int_m_axi_buser;\nwire [M_COUNT-1:0] int_m_axi_bvalid;\nwire [M_COUNT-1:0] int_m_axi_bready;\n\nwire [M_COUNT*S_COUNT-1:0] int_axi_bvalid;\nwire [S_COUNT*M_COUNT-1:0] int_axi_bready;\n\ngenerate\n\n genvar m, n;\n\n for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces\n // address decode and admission control\n wire [CL_M_COUNT-1:0] a_select;\n\n wire m_axi_avalid;\n wire m_axi_aready;\n\n wire [CL_M_COUNT-1:0] m_wc_select;\n wire m_wc_decerr;\n wire m_wc_valid;\n wire m_wc_ready;\n\n wire m_rc_decerr;\n wire m_rc_valid;\n wire m_rc_ready;\n\n wire [S_ID_WIDTH-1:0] s_cpl_id;\n wire s_cpl_valid;\n\n axi_crossbar_addr #(\n .S(m),\n .S_COUNT(S_COUNT),\n .M_COUNT(M_COUNT),\n .ADDR_WIDTH(ADDR_WIDTH),\n .ID_WIDTH(S_ID_WIDTH),\n .S_THREADS(S_THREADS[m*32 +: 32]),\n .S_ACCEPT(S_ACCEPT[m*32 +: 32]),\n .M_REGIONS(M_REGIONS),\n .M_BASE_ADDR(M_BASE_ADDR),\n .M_ADDR_WIDTH(M_ADDR_WIDTH),\n .M_CONNECT(M_CONNECT),\n .M_SECURE(M_SECURE),\n .WC_OUTPUT(1)\n )\n addr_inst (\n .clk(clk),\n .rst(rst),\n\n /*\n * Address input\n */\n .s_axi_aid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),\n .s_axi_aaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),\n .s_axi_aprot(int_s_axi_awprot[m*3 +: 3]),\n .s_axi_aqos(int_s_axi_awqos[m*4 +: 4]),\n .s_axi_avalid(int_s_axi_awvalid[m]),\n .s_axi_aready(int_s_axi_awready[m]),\n\n /*\n * Address output\n */\n .m_axi_aregion(int_s_axi_awregion[m*4 +: 4]),\n .m_select(a_select),\n .m_axi_avalid(m_axi_avalid),\n .m_axi_aready(m_axi_aready),\n\n /*\n * Write command output\n */\n .m_wc_select(m_wc_select),\n .m_wc_decerr(m_wc_decerr),\n .m_wc_valid(m_wc_valid),\n .m_wc_ready(m_wc_ready),\n\n /*\n * Response command output\n */\n .m_rc_decerr(m_rc_decerr),\n .m_rc_valid(m_rc_valid),\n .m_rc_ready(m_rc_ready),\n\n /*\n * Completion input\n */\n .s_cpl_id(s_cpl_id),\n .s_cpl_valid(s_cpl_valid)\n );\n\n assign int_axi_awvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select;\n assign m_axi_aready = int_axi_awready[a_select*S_COUNT+m];\n\n // write command handling\n reg [CL_M_COUNT-1:0] w_select_reg = 0, w_select_next;\n reg w_drop_reg = 1'b0, w_drop_next;\n reg w_select_valid_reg = 1'b0, w_select_valid_next;\n\n assign m_wc_ready = !w_select_valid_reg;\n\n always @* begin\n w_select_next = w_select_reg;\n w_drop_next = w_drop_reg && !(int_s_axi_wvalid[m] && int_s_axi_wready[m] && int_s_axi_wlast[m]);\n w_select_valid_next = w_select_valid_reg && !(int_s_axi_wvalid[m] && int_s_axi_wready[m] && int_s_axi_wlast[m]);\n\n if (m_wc_valid && !w_select_valid_reg) begin\n w_select_next = m_wc_select;\n w_drop_next = m_wc_decerr;\n w_select_valid_next = m_wc_valid;\n end\n end\n\n always @(posedge clk) begin\n if (rst) begin\n w_select_valid_reg <= 1'b0;\n end else begin\n w_select_valid_reg <= w_select_valid_next;\n end\n\n w_select_reg <= w_select_next;\n w_drop_reg <= w_drop_next;\n end\n\n // write data forwarding\n assign int_axi_wvalid[m*M_COUNT +: M_COUNT] = (int_s_axi_wvalid[m] && w_select_valid_reg && !w_drop_reg) << w_select_reg;\n assign int_s_axi_wready[m] = int_axi_wready[w_select_reg*S_COUNT+m] || w_drop_reg;\n\n // decode error handling\n reg [S_ID_WIDTH-1:0] decerr_m_axi_bid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_bid_next;\n reg decerr_m_axi_bvalid_reg = 1'b0, decerr_m_axi_bvalid_next;\n wire decerr_m_axi_bready;\n\n assign m_rc_ready = !decerr_m_axi_bvalid_reg;\n\n always @* begin\n decerr_m_axi_bid_next = decerr_m_axi_bid_reg;\n decerr_m_axi_bvalid_next = decerr_m_axi_bvalid_reg;\n\n if (decerr_m_axi_bvalid_reg) begin\n if (decerr_m_axi_bready) begin\n decerr_m_axi_bvalid_next = 1'b0;\n end\n end else if (m_rc_valid && m_rc_ready) begin\n decerr_m_axi_bid_next = int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH];\n decerr_m_axi_bvalid_next = 1'b1;\n end\n end\n\n always @(posedge clk) begin\n if (rst) begin\n decerr_m_axi_bvalid_reg <= 1'b0;\n end else begin\n decerr_m_axi_bvalid_reg <= decerr_m_axi_bvalid_next;\n end\n\n decerr_m_axi_bid_reg <= decerr_m_axi_bid_next;\n end\n\n // write response arbitration\n wire [M_COUNT_P1-1:0] b_request;\n wire [M_COUNT_P1-1:0] b_acknowledge;\n wire [M_COUNT_P1-1:0] b_grant;\n wire b_grant_valid;\n wire [CL_M_COUNT_P1-1:0] b_grant_encoded;\n\n arbiter #(\n .PORTS(M_COUNT_P1),\n .ARB_TYPE_ROUND_ROBIN(1),\n .ARB_BLOCK(1),\n .ARB_BLOCK_ACK(1),\n .ARB_LSB_HIGH_PRIORITY(1)\n )\n b_arb_inst (\n .clk(clk),\n .rst(rst),\n .request(b_request),\n .acknowledge(b_acknowledge),\n .grant(b_grant),\n .grant_valid(b_grant_valid),\n .grant_encoded(b_grant_encoded)\n );\n\n // write response mux\n wire [S_ID_WIDTH-1:0] m_axi_bid_mux = {decerr_m_axi_bid_reg, int_m_axi_bid} >> b_grant_encoded*M_ID_WIDTH;\n wire [1:0] m_axi_bresp_mux = {2'b11, int_m_axi_bresp} >> b_grant_encoded*2;\n wire [BUSER_WIDTH-1:0] m_axi_buser_mux = {{BUSER_WIDTH{1'b0}}, int_m_axi_buser} >> b_grant_encoded*BUSER_WIDTH;\n wire m_axi_bvalid_mux = ({decerr_m_axi_bvalid_reg, int_m_axi_bvalid} >> b_grant_encoded) & b_grant_valid;\n wire m_axi_bready_mux;\n\n assign int_axi_bready[m*M_COUNT +: M_COUNT] = (b_grant_valid && m_axi_bready_mux) << b_grant_encoded;\n assign decerr_m_axi_bready = (b_grant_valid && m_axi_bready_mux) && (b_grant_encoded == M_COUNT_P1-1);\n\n for (n = 0; n < M_COUNT; n = n + 1) begin\n assign b_request[n] = int_axi_bvalid[n*S_COUNT+m] && !b_grant[n];\n assign b_acknowledge[n] = b_grant[n] && int_axi_bvalid[n*S_COUNT+m] && m_axi_bready_mux;\n end\n\n assign b_request[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1];\n assign b_acknowledge[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && m_axi_bready_mux;\n\n assign s_cpl_id = m_axi_bid_mux;\n assign s_cpl_valid = m_axi_bvalid_mux && m_axi_bready_mux;\n\n // S side register\n axi_register_wr #(\n .DATA_WIDTH(DATA_WIDTH),\n .ADDR_WIDTH(ADDR_WIDTH),\n .STRB_WIDTH(STRB_WIDTH),\n .ID_WIDTH(S_ID_WIDTH),\n .AWUSER_ENABLE(AWUSER_ENABLE),\n .AWUSER_WIDTH(AWUSER_WIDTH),\n .WUSER_ENABLE(WUSER_ENABLE),\n .WUSER_WIDTH(WUSER_WIDTH),\n .BUSER_ENABLE(BUSER_ENABLE),\n .BUSER_WIDTH(BUSER_WIDTH),\n .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]),\n .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]),\n .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2])\n )\n reg_inst (\n .clk(clk),\n .rst(rst),\n .s_axi_awid(s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),\n .s_axi_awaddr(s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),\n .s_axi_awlen(s_axi_awlen[m*8 +: 8]),\n .s_axi_awsize(s_axi_awsize[m*3 +: 3]),\n .s_axi_awburst(s_axi_awburst[m*2 +: 2]),\n .s_axi_awlock(s_axi_awlock[m]),\n .s_axi_awcache(s_axi_awcache[m*4 +: 4]),\n .s_axi_awprot(s_axi_awprot[m*3 +: 3]),\n .s_axi_awqos(s_axi_awqos[m*4 +: 4]),\n .s_axi_awregion(4'd0),\n .s_axi_awuser(s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]),\n .s_axi_awvalid(s_axi_awvalid[m]),\n .s_axi_awready(s_axi_awready[m]),\n .s_axi_wdata(s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]),\n .s_axi_wstrb(s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]),\n .s_axi_wlast(s_axi_wlast[m]),\n .s_axi_wuser(s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]),\n .s_axi_wvalid(s_axi_wvalid[m]),\n .s_axi_wready(s_axi_wready[m]),\n .s_axi_bid(s_axi_bid[m*S_ID_WIDTH +: S_ID_WIDTH]),\n .s_axi_bresp(s_axi_bresp[m*2 +: 2]),\n .s_axi_buser(s_axi_buser[m*BUSER_WIDTH +: BUSER_WIDTH]),\n .s_axi_bvalid(s_axi_bvalid[m]),\n .s_axi_bready(s_axi_bready[m]),\n .m_axi_awid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),\n .m_axi_awaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),\n .m_axi_awlen(int_s_axi_awlen[m*8 +: 8]),\n .m_axi_awsize(int_s_axi_awsize[m*3 +: 3]),\n .m_axi_awburst(int_s_axi_awburst[m*2 +: 2]),\n .m_axi_awlock(int_s_axi_awlock[m]),\n .m_axi_awcache(int_s_axi_awcache[m*4 +: 4]),\n .m_axi_awprot(int_s_axi_awprot[m*3 +: 3]),\n .m_axi_awqos(int_s_axi_awqos[m*4 +: 4]),\n .m_axi_awregion(),\n .m_axi_awuser(int_s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]),\n .m_axi_awvalid(int_s_axi_awvalid[m]),\n .m_axi_awready(int_s_axi_awready[m]),\n .m_axi_wdata(int_s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]),\n .m_axi_wstrb(int_s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]),\n .m_axi_wlast(int_s_axi_wlast[m]),\n .m_axi_wuser(int_s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]),\n .m_axi_wvalid(int_s_axi_wvalid[m]),\n .m_axi_wready(int_s_axi_wready[m]),\n .m_axi_bid(m_axi_bid_mux),\n .m_axi_bresp(m_axi_bresp_mux),\n .m_axi_buser(m_axi_buser_mux),\n .m_axi_bvalid(m_axi_bvalid_mux),\n .m_axi_bready(m_axi_bready_mux)\n );\n end // s_ifaces\n\n for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces\n // in-flight transaction count\n wire trans_start;\n wire trans_complete;\n reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;\n\n wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;\n\n always @(posedge clk) begin\n if (rst) begin\n trans_count_reg <= 0;\n end else begin\n if (trans_start && !trans_complete) begin\n trans_count_reg <= trans_count_reg + 1;\n end else if (!trans_start && trans_complete) begin\n trans_count_reg <= trans_count_reg - 1;\n end\n end\n end\n\n // address arbitration\n reg [CL_S_COUNT-1:0] w_select_reg = 0, w_select_next;\n reg w_select_valid_reg = 1'b0, w_select_valid_next;\n reg w_select_new_reg = 1'b0, w_select_new_next;\n\n wire [S_COUNT-1:0] a_request;\n wire [S_COUNT-1:0] a_acknowledge;\n wire [S_COUNT-1:0] a_grant;\n wire a_grant_valid;\n wire [CL_S_COUNT-1:0] a_grant_encoded;\n\n arbiter #(\n .PORTS(S_COUNT),\n .ARB_TYPE_ROUND_ROBIN(1),\n .ARB_BLOCK(1),\n .ARB_BLOCK_ACK(1),\n .ARB_LSB_HIGH_PRIORITY(1)\n )\n a_arb_inst (\n .clk(clk),\n .rst(rst),\n .request(a_request),\n .acknowledge(a_acknowledge),\n .grant(a_grant),\n .grant_valid(a_grant_valid),\n .grant_encoded(a_grant_encoded)\n );\n\n // address mux\n wire [M_ID_WIDTH-1:0] s_axi_awid_mux = int_s_axi_awid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);\n wire [ADDR_WIDTH-1:0] s_axi_awaddr_mux = int_s_axi_awaddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];\n wire [7:0] s_axi_awlen_mux = int_s_axi_awlen[a_grant_encoded*8 +: 8];\n wire [2:0] s_axi_awsize_mux = int_s_axi_awsize[a_grant_encoded*3 +: 3];\n wire [1:0] s_axi_awburst_mux = int_s_axi_awburst[a_grant_encoded*2 +: 2];\n wire s_axi_awlock_mux = int_s_axi_awlock[a_grant_encoded];\n wire [3:0] s_axi_awcache_mux = int_s_axi_awcache[a_grant_encoded*4 +: 4];\n wire [2:0] s_axi_awprot_mux = int_s_axi_awprot[a_grant_encoded*3 +: 3];\n wire [3:0] s_axi_awqos_mux = int_s_axi_awqos[a_grant_encoded*4 +: 4];\n wire [3:0] s_axi_awregion_mux = int_s_axi_awregion[a_grant_encoded*4 +: 4];\n wire [AWUSER_WIDTH-1:0] s_axi_awuser_mux = int_s_axi_awuser[a_grant_encoded*AWUSER_WIDTH +: AWUSER_WIDTH];\n wire s_axi_awvalid_mux = int_axi_awvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;\n wire s_axi_awready_mux;\n\n assign int_axi_awready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_awready_mux) << a_grant_encoded;\n\n for (m = 0; m < S_COUNT; m = m + 1) begin\n assign a_request[m] = int_axi_awvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit && !w_select_valid_next;\n assign a_acknowledge[m] = a_grant[m] && int_axi_awvalid[m*M_COUNT+n] && s_axi_awready_mux;\n end\n\n assign trans_start = s_axi_awvalid_mux && s_axi_awready_mux && a_grant_valid;\n\n // write data mux\n wire [DATA_WIDTH-1:0] s_axi_wdata_mux = int_s_axi_wdata[w_select_reg*DATA_WIDTH +: DATA_WIDTH];\n wire [STRB_WIDTH-1:0] s_axi_wstrb_mux = int_s_axi_wstrb[w_select_reg*STRB_WIDTH +: STRB_WIDTH];\n wire s_axi_wlast_mux = int_s_axi_wlast[w_select_reg];\n wire [WUSER_WIDTH-1:0] s_axi_wuser_mux = int_s_axi_wuser[w_select_reg*WUSER_WIDTH +: WUSER_WIDTH];\n wire s_axi_wvalid_mux = int_axi_wvalid[w_select_reg*M_COUNT+n] && w_select_valid_reg;\n wire s_axi_wready_mux;\n\n assign int_axi_wready[n*S_COUNT +: S_COUNT] = (w_select_valid_reg && s_axi_wready_mux) << w_select_reg;\n\n // write data routing\n always @* begin\n w_select_next = w_select_reg;\n w_select_valid_next = w_select_valid_reg && !(s_axi_wvalid_mux && s_axi_wready_mux && s_axi_wlast_mux);\n w_select_new_next = w_select_new_reg || !a_grant_valid || a_acknowledge;\n\n if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin\n w_select_next = a_grant_encoded;\n w_select_valid_next = a_grant_valid;\n w_select_new_next = 1'b0;\n end\n end\n\n always @(posedge clk) begin\n if (rst) begin\n w_select_valid_reg <= 1'b0;\n w_select_new_reg <= 1'b1;\n end else begin\n w_select_valid_reg <= w_select_valid_next;\n w_select_new_reg <= w_select_new_next;\n end\n\n w_select_reg <= w_select_next;\n end\n\n // write response forwarding\n wire [CL_S_COUNT-1:0] b_select = m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;\n\n assign int_axi_bvalid[n*S_COUNT +: S_COUNT] = int_m_axi_bvalid[n] << b_select;\n assign int_m_axi_bready[n] = int_axi_bready[b_select*M_COUNT+n];\n\n assign trans_complete = int_m_axi_bvalid[n] && int_m_axi_bready[n];\n\n // M side register\n axi_register_wr #(\n .DATA_WIDTH(DATA_WIDTH),\n .ADDR_WIDTH(ADDR_WIDTH),\n .STRB_WIDTH(STRB_WIDTH),\n .ID_WIDTH(M_ID_WIDTH),\n .AWUSER_ENABLE(AWUSER_ENABLE),\n .AWUSER_WIDTH(AWUSER_WIDTH),\n .WUSER_ENABLE(WUSER_ENABLE),\n .WUSER_WIDTH(WUSER_WIDTH),\n .BUSER_ENABLE(BUSER_ENABLE),\n .BUSER_WIDTH(BUSER_WIDTH),\n .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]),\n .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]),\n .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2])\n )\n reg_inst (\n .clk(clk),\n .rst(rst),\n .s_axi_awid(s_axi_awid_mux),\n .s_axi_awaddr(s_axi_awaddr_mux),\n .s_axi_awlen(s_axi_awlen_mux),\n .s_axi_awsize(s_axi_awsize_mux),\n .s_axi_awburst(s_axi_awburst_mux),\n .s_axi_awlock(s_axi_awlock_mux),\n .s_axi_awcache(s_axi_awcache_mux),\n .s_axi_awprot(s_axi_awprot_mux),\n .s_axi_awqos(s_axi_awqos_mux),\n .s_axi_awregion(s_axi_awregion_mux),\n .s_axi_awuser(s_axi_awuser_mux),\n .s_axi_awvalid(s_axi_awvalid_mux),\n .s_axi_awready(s_axi_awready_mux),\n .s_axi_wdata(s_axi_wdata_mux),\n .s_axi_wstrb(s_axi_wstrb_mux),\n .s_axi_wlast(s_axi_wlast_mux),\n .s_axi_wuser(s_axi_wuser_mux),\n .s_axi_wvalid(s_axi_wvalid_mux),\n .s_axi_wready(s_axi_wready_mux),\n .s_axi_bid(int_m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]),\n .s_axi_bresp(int_m_axi_bresp[n*2 +: 2]),\n .s_axi_buser(int_m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]),\n .s_axi_bvalid(int_m_axi_bvalid[n]),\n .s_axi_bready(int_m_axi_bready[n]),\n .m_axi_awid(m_axi_awid[n*M_ID_WIDTH +: M_ID_WIDTH]),\n .m_axi_awaddr(m_axi_awaddr[n*ADDR_WIDTH +: ADDR_WIDTH]),\n .m_axi_awlen(m_axi_awlen[n*8 +: 8]),\n .m_axi_awsize(m_axi_awsize[n*3 +: 3]),\n .m_axi_awburst(m_axi_awburst[n*2 +: 2]),\n .m_axi_awlock(m_axi_awlock[n]),\n .m_axi_awcache(m_axi_awcache[n*4 +: 4]),\n .m_axi_awprot(m_axi_awprot[n*3 +: 3]),\n .m_axi_awqos(m_axi_awqos[n*4 +: 4]),\n .m_axi_awregion(m_axi_awregion[n*4 +: 4]),\n .m_axi_awuser(m_axi_awuser[n*AWUSER_WIDTH +: AWUSER_WIDTH]),\n .m_axi_awvalid(m_axi_awvalid[n]),\n .m_axi_awready(m_axi_awready[n]),\n .m_axi_wdata(m_axi_wdata[n*DATA_WIDTH +: DATA_WIDTH]),\n .m_axi_wstrb(m_axi_wstrb[n*STRB_WIDTH +: STRB_WIDTH]),\n .m_axi_wlast(m_axi_wlast[n]),\n .m_axi_wuser(m_axi_wuser[n*WUSER_WIDTH +: WUSER_WIDTH]),\n .m_axi_wvalid(m_axi_wvalid[n]),\n .m_axi_wready(m_axi_wready[n]),\n .m_axi_bid(m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]),\n .m_axi_bresp(m_axi_bresp[n*2 +: 2]),\n .m_axi_buser(m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]),\n .m_axi_bvalid(m_axi_bvalid[n]),\n .m_axi_bready(m_axi_bready[n])\n );\n end // m_ifaces\n\nendgenerate\n\nendmodule\n\n`resetall\n" }, { "path": "testbench/axi4_mux/axi_crossbar_wrap_2x1.v", "content": "/*\n\nCopyright (c) 2020 Alex Forencich\nCopyright 2024 Antmicro \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n`default_nettype none\n\n/*\n * AXI4 2x1 crossbar (wrapper)\n */\nmodule axi_crossbar_wrap_2x1 #\n(\n parameter S_COUNT = 2,\n parameter M_COUNT = 1,\n // Width of data bus in bits\n parameter DATA_WIDTH = 32,\n // Width of address bus in bits\n parameter ADDR_WIDTH = 32,\n // Width of wstrb (width of data bus in words)\n parameter STRB_WIDTH = (DATA_WIDTH/8),\n // Input ID field width (from AXI masters)\n parameter S_ID_WIDTH = 8,\n // Output ID field width (towards AXI slaves)\n // Additional bits required for response routing\n parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),\n // Propagate awuser signal\n parameter AWUSER_ENABLE = 0,\n // Width of awuser signal\n parameter AWUSER_WIDTH = 1,\n // Propagate wuser signal\n parameter WUSER_ENABLE = 0,\n // Width of wuser signal\n parameter WUSER_WIDTH = 1,\n // Propagate buser signal\n parameter BUSER_ENABLE = 0,\n // Width of buser signal\n parameter BUSER_WIDTH = 1,\n // Propagate aruser signal\n parameter ARUSER_ENABLE = 0,\n // Width of aruser signal\n parameter ARUSER_WIDTH = 1,\n // Propagate ruser signal\n parameter RUSER_ENABLE = 0,\n // Width of ruser signal\n parameter RUSER_WIDTH = 1,\n // Number of concurrent unique IDs\n parameter S00_THREADS = 2,\n // Number of concurrent operations\n parameter S00_ACCEPT = 16,\n // Number of concurrent unique IDs\n parameter S01_THREADS = 2,\n // Number of concurrent operations\n parameter S01_ACCEPT = 16,\n // Number of regions per master interface\n parameter M_REGIONS = 1,\n // Master interface base addresses\n // M_REGIONS concatenated fields of ADDR_WIDTH bits\n parameter M00_BASE_ADDR = 0,\n // Master interface address widths\n // M_REGIONS concatenated fields of 32 bits\n parameter M00_ADDR_WIDTH = {M_REGIONS{32'd24}},\n // Read connections between interfaces\n // S_COUNT bits\n parameter M00_CONNECT_READ = 2'b11,\n // Write connections between interfaces\n // S_COUNT bits\n parameter M00_CONNECT_WRITE = 2'b11,\n // Number of concurrent operations for each master interface\n parameter M00_ISSUE = 4,\n // Secure master (fail operations based on awprot/arprot)\n parameter M00_SECURE = 0,\n // Slave interface AW channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S00_AW_REG_TYPE = 0,\n // Slave interface W channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S00_W_REG_TYPE = 0,\n // Slave interface B channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S00_B_REG_TYPE = 1,\n // Slave interface AR channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S00_AR_REG_TYPE = 0,\n // Slave interface R channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S00_R_REG_TYPE = 2,\n // Slave interface AW channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S01_AW_REG_TYPE = 0,\n // Slave interface W channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S01_W_REG_TYPE = 0,\n // Slave interface B channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S01_B_REG_TYPE = 1,\n // Slave interface AR channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S01_AR_REG_TYPE = 0,\n // Slave interface R channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter S01_R_REG_TYPE = 2,\n // Master interface AW channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M00_AW_REG_TYPE = 1,\n // Master interface W channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M00_W_REG_TYPE = 2,\n // Master interface B channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M00_B_REG_TYPE = 0,\n // Master interface AR channel register type (output)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M00_AR_REG_TYPE = 1,\n // Master interface R channel register type (input)\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter M00_R_REG_TYPE = 0\n)\n(\n input wire clk,\n input wire rst,\n\n /*\n * AXI slave interface\n */\n input wire [S_ID_WIDTH-1:0] s00_axi_awid,\n input wire [ADDR_WIDTH-1:0] s00_axi_awaddr,\n input wire [7:0] s00_axi_awlen,\n input wire [2:0] s00_axi_awsize,\n input wire [1:0] s00_axi_awburst,\n input wire s00_axi_awlock,\n input wire [3:0] s00_axi_awcache,\n input wire [2:0] s00_axi_awprot,\n input wire [3:0] s00_axi_awqos,\n input wire [AWUSER_WIDTH-1:0] s00_axi_awuser,\n input wire s00_axi_awvalid,\n output wire s00_axi_awready,\n input wire [DATA_WIDTH-1:0] s00_axi_wdata,\n input wire [STRB_WIDTH-1:0] s00_axi_wstrb,\n input wire s00_axi_wlast,\n input wire [WUSER_WIDTH-1:0] s00_axi_wuser,\n input wire s00_axi_wvalid,\n output wire s00_axi_wready,\n output wire [S_ID_WIDTH-1:0] s00_axi_bid,\n output wire [1:0] s00_axi_bresp,\n output wire [BUSER_WIDTH-1:0] s00_axi_buser,\n output wire s00_axi_bvalid,\n input wire s00_axi_bready,\n input wire [S_ID_WIDTH-1:0] s00_axi_arid,\n input wire [ADDR_WIDTH-1:0] s00_axi_araddr,\n input wire [7:0] s00_axi_arlen,\n input wire [2:0] s00_axi_arsize,\n input wire [1:0] s00_axi_arburst,\n input wire s00_axi_arlock,\n input wire [3:0] s00_axi_arcache,\n input wire [2:0] s00_axi_arprot,\n input wire [3:0] s00_axi_arqos,\n input wire [ARUSER_WIDTH-1:0] s00_axi_aruser,\n input wire s00_axi_arvalid,\n output wire s00_axi_arready,\n output wire [S_ID_WIDTH-1:0] s00_axi_rid,\n output wire [DATA_WIDTH-1:0] s00_axi_rdata,\n output wire [1:0] s00_axi_rresp,\n output wire s00_axi_rlast,\n output wire [RUSER_WIDTH-1:0] s00_axi_ruser,\n output wire s00_axi_rvalid,\n input wire s00_axi_rready,\n\n input wire [S_ID_WIDTH-1:0] s01_axi_awid,\n input wire [ADDR_WIDTH-1:0] s01_axi_awaddr,\n input wire [7:0] s01_axi_awlen,\n input wire [2:0] s01_axi_awsize,\n input wire [1:0] s01_axi_awburst,\n input wire s01_axi_awlock,\n input wire [3:0] s01_axi_awcache,\n input wire [2:0] s01_axi_awprot,\n input wire [3:0] s01_axi_awqos,\n input wire [AWUSER_WIDTH-1:0] s01_axi_awuser,\n input wire s01_axi_awvalid,\n output wire s01_axi_awready,\n input wire [DATA_WIDTH-1:0] s01_axi_wdata,\n input wire [STRB_WIDTH-1:0] s01_axi_wstrb,\n input wire s01_axi_wlast,\n input wire [WUSER_WIDTH-1:0] s01_axi_wuser,\n input wire s01_axi_wvalid,\n output wire s01_axi_wready,\n output wire [S_ID_WIDTH-1:0] s01_axi_bid,\n output wire [1:0] s01_axi_bresp,\n output wire [BUSER_WIDTH-1:0] s01_axi_buser,\n output wire s01_axi_bvalid,\n input wire s01_axi_bready,\n input wire [S_ID_WIDTH-1:0] s01_axi_arid,\n input wire [ADDR_WIDTH-1:0] s01_axi_araddr,\n input wire [7:0] s01_axi_arlen,\n input wire [2:0] s01_axi_arsize,\n input wire [1:0] s01_axi_arburst,\n input wire s01_axi_arlock,\n input wire [3:0] s01_axi_arcache,\n input wire [2:0] s01_axi_arprot,\n input wire [3:0] s01_axi_arqos,\n input wire [ARUSER_WIDTH-1:0] s01_axi_aruser,\n input wire s01_axi_arvalid,\n output wire s01_axi_arready,\n output wire [S_ID_WIDTH-1:0] s01_axi_rid,\n output wire [DATA_WIDTH-1:0] s01_axi_rdata,\n output wire [1:0] s01_axi_rresp,\n output wire s01_axi_rlast,\n output wire [RUSER_WIDTH-1:0] s01_axi_ruser,\n output wire s01_axi_rvalid,\n input wire s01_axi_rready,\n\n /*\n * AXI master interface\n */\n output wire [M_ID_WIDTH-1:0] m00_axi_awid,\n output wire [ADDR_WIDTH-1:0] m00_axi_awaddr,\n output wire [7:0] m00_axi_awlen,\n output wire [2:0] m00_axi_awsize,\n output wire [1:0] m00_axi_awburst,\n output wire m00_axi_awlock,\n output wire [3:0] m00_axi_awcache,\n output wire [2:0] m00_axi_awprot,\n output wire [3:0] m00_axi_awqos,\n output wire [3:0] m00_axi_awregion,\n output wire [AWUSER_WIDTH-1:0] m00_axi_awuser,\n output wire m00_axi_awvalid,\n input wire m00_axi_awready,\n output wire [DATA_WIDTH-1:0] m00_axi_wdata,\n output wire [STRB_WIDTH-1:0] m00_axi_wstrb,\n output wire m00_axi_wlast,\n output wire [WUSER_WIDTH-1:0] m00_axi_wuser,\n output wire m00_axi_wvalid,\n input wire m00_axi_wready,\n input wire [M_ID_WIDTH-1:0] m00_axi_bid,\n input wire [1:0] m00_axi_bresp,\n input wire [BUSER_WIDTH-1:0] m00_axi_buser,\n input wire m00_axi_bvalid,\n output wire m00_axi_bready,\n output wire [M_ID_WIDTH-1:0] m00_axi_arid,\n output wire [ADDR_WIDTH-1:0] m00_axi_araddr,\n output wire [7:0] m00_axi_arlen,\n output wire [2:0] m00_axi_arsize,\n output wire [1:0] m00_axi_arburst,\n output wire m00_axi_arlock,\n output wire [3:0] m00_axi_arcache,\n output wire [2:0] m00_axi_arprot,\n output wire [3:0] m00_axi_arqos,\n output wire [3:0] m00_axi_arregion,\n output wire [ARUSER_WIDTH-1:0] m00_axi_aruser,\n output wire m00_axi_arvalid,\n input wire m00_axi_arready,\n input wire [M_ID_WIDTH-1:0] m00_axi_rid,\n input wire [DATA_WIDTH-1:0] m00_axi_rdata,\n input wire [1:0] m00_axi_rresp,\n input wire m00_axi_rlast,\n input wire [RUSER_WIDTH-1:0] m00_axi_ruser,\n input wire m00_axi_rvalid,\n output wire m00_axi_rready\n);\n\n// parameter sizing helpers\nfunction [ADDR_WIDTH*M_REGIONS-1:0] w_a_r(input [ADDR_WIDTH*M_REGIONS-1:0] val);\n w_a_r = val;\nendfunction\n\nfunction [32*M_REGIONS-1:0] w_32_r(input [32*M_REGIONS-1:0] val);\n w_32_r = val;\nendfunction\n\nfunction [S_COUNT-1:0] w_s(input [S_COUNT-1:0] val);\n w_s = val;\nendfunction\n\nfunction [31:0] w_32(input [31:0] val);\n w_32 = val;\nendfunction\n\nfunction [1:0] w_2(input [1:0] val);\n w_2 = val;\nendfunction\n\nfunction w_1(input val);\n w_1 = val;\nendfunction\n\naxi_crossbar #(\n .S_COUNT(S_COUNT),\n .M_COUNT(M_COUNT),\n .DATA_WIDTH(DATA_WIDTH),\n .ADDR_WIDTH(ADDR_WIDTH),\n .STRB_WIDTH(STRB_WIDTH),\n .S_ID_WIDTH(S_ID_WIDTH),\n .M_ID_WIDTH(M_ID_WIDTH),\n .AWUSER_ENABLE(AWUSER_ENABLE),\n .AWUSER_WIDTH(AWUSER_WIDTH),\n .WUSER_ENABLE(WUSER_ENABLE),\n .WUSER_WIDTH(WUSER_WIDTH),\n .BUSER_ENABLE(BUSER_ENABLE),\n .BUSER_WIDTH(BUSER_WIDTH),\n .ARUSER_ENABLE(ARUSER_ENABLE),\n .ARUSER_WIDTH(ARUSER_WIDTH),\n .RUSER_ENABLE(RUSER_ENABLE),\n .RUSER_WIDTH(RUSER_WIDTH),\n .S_THREADS({ w_32(S01_THREADS), w_32(S00_THREADS) }),\n .S_ACCEPT({ w_32(S01_ACCEPT), w_32(S00_ACCEPT) }),\n .M_REGIONS(M_REGIONS),\n .M_BASE_ADDR({ w_a_r(M00_BASE_ADDR) }),\n .M_ADDR_WIDTH({ w_32_r(M00_ADDR_WIDTH) }),\n .M_CONNECT_READ({ w_s(M00_CONNECT_READ) }),\n .M_CONNECT_WRITE({ w_s(M00_CONNECT_WRITE) }),\n .M_ISSUE({ w_32(M00_ISSUE) }),\n .M_SECURE({ w_1(M00_SECURE) }),\n .S_AR_REG_TYPE({ w_2(S01_AR_REG_TYPE), w_2(S00_AR_REG_TYPE) }),\n .S_R_REG_TYPE({ w_2(S01_R_REG_TYPE), w_2(S00_R_REG_TYPE) }),\n .S_AW_REG_TYPE({ w_2(S01_AW_REG_TYPE), w_2(S00_AW_REG_TYPE) }),\n .S_W_REG_TYPE({ w_2(S01_W_REG_TYPE), w_2(S00_W_REG_TYPE) }),\n .S_B_REG_TYPE({ w_2(S01_B_REG_TYPE), w_2(S00_B_REG_TYPE) }),\n .M_AR_REG_TYPE({ w_2(M00_AR_REG_TYPE) }),\n .M_R_REG_TYPE({ w_2(M00_R_REG_TYPE) }),\n .M_AW_REG_TYPE({ w_2(M00_AW_REG_TYPE) }),\n .M_W_REG_TYPE({ w_2(M00_W_REG_TYPE) }),\n .M_B_REG_TYPE({ w_2(M00_B_REG_TYPE) })\n)\naxi_crossbar_inst (\n .clk(clk),\n .rst(rst),\n .s_axi_awid({ s01_axi_awid, s00_axi_awid }),\n .s_axi_awaddr({ s01_axi_awaddr, s00_axi_awaddr }),\n .s_axi_awlen({ s01_axi_awlen, s00_axi_awlen }),\n .s_axi_awsize({ s01_axi_awsize, s00_axi_awsize }),\n .s_axi_awburst({ s01_axi_awburst, s00_axi_awburst }),\n .s_axi_awlock({ s01_axi_awlock, s00_axi_awlock }),\n .s_axi_awcache({ s01_axi_awcache, s00_axi_awcache }),\n .s_axi_awprot({ s01_axi_awprot, s00_axi_awprot }),\n .s_axi_awqos({ s01_axi_awqos, s00_axi_awqos }),\n .s_axi_awuser({ s01_axi_awuser, s00_axi_awuser }),\n .s_axi_awvalid({ s01_axi_awvalid, s00_axi_awvalid }),\n .s_axi_awready({ s01_axi_awready, s00_axi_awready }),\n .s_axi_wdata({ s01_axi_wdata, s00_axi_wdata }),\n .s_axi_wstrb({ s01_axi_wstrb, s00_axi_wstrb }),\n .s_axi_wlast({ s01_axi_wlast, s00_axi_wlast }),\n .s_axi_wuser({ s01_axi_wuser, s00_axi_wuser }),\n .s_axi_wvalid({ s01_axi_wvalid, s00_axi_wvalid }),\n .s_axi_wready({ s01_axi_wready, s00_axi_wready }),\n .s_axi_bid({ s01_axi_bid, s00_axi_bid }),\n .s_axi_bresp({ s01_axi_bresp, s00_axi_bresp }),\n .s_axi_buser({ s01_axi_buser, s00_axi_buser }),\n .s_axi_bvalid({ s01_axi_bvalid, s00_axi_bvalid }),\n .s_axi_bready({ s01_axi_bready, s00_axi_bready }),\n .s_axi_arid({ s01_axi_arid, s00_axi_arid }),\n .s_axi_araddr({ s01_axi_araddr, s00_axi_araddr }),\n .s_axi_arlen({ s01_axi_arlen, s00_axi_arlen }),\n .s_axi_arsize({ s01_axi_arsize, s00_axi_arsize }),\n .s_axi_arburst({ s01_axi_arburst, s00_axi_arburst }),\n .s_axi_arlock({ s01_axi_arlock, s00_axi_arlock }),\n .s_axi_arcache({ s01_axi_arcache, s00_axi_arcache }),\n .s_axi_arprot({ s01_axi_arprot, s00_axi_arprot }),\n .s_axi_arqos({ s01_axi_arqos, s00_axi_arqos }),\n .s_axi_aruser({ s01_axi_aruser, s00_axi_aruser }),\n .s_axi_arvalid({ s01_axi_arvalid, s00_axi_arvalid }),\n .s_axi_arready({ s01_axi_arready, s00_axi_arready }),\n .s_axi_rid({ s01_axi_rid, s00_axi_rid }),\n .s_axi_rdata({ s01_axi_rdata, s00_axi_rdata }),\n .s_axi_rresp({ s01_axi_rresp, s00_axi_rresp }),\n .s_axi_rlast({ s01_axi_rlast, s00_axi_rlast }),\n .s_axi_ruser({ s01_axi_ruser, s00_axi_ruser }),\n .s_axi_rvalid({ s01_axi_rvalid, s00_axi_rvalid }),\n .s_axi_rready({ s01_axi_rready, s00_axi_rready }),\n .m_axi_awid({ m00_axi_awid }),\n .m_axi_awaddr({ m00_axi_awaddr }),\n .m_axi_awlen({ m00_axi_awlen }),\n .m_axi_awsize({ m00_axi_awsize }),\n .m_axi_awburst({ m00_axi_awburst }),\n .m_axi_awlock({ m00_axi_awlock }),\n .m_axi_awcache({ m00_axi_awcache }),\n .m_axi_awprot({ m00_axi_awprot }),\n .m_axi_awqos({ m00_axi_awqos }),\n .m_axi_awregion({ m00_axi_awregion }),\n .m_axi_awuser({ m00_axi_awuser }),\n .m_axi_awvalid({ m00_axi_awvalid }),\n .m_axi_awready({ m00_axi_awready }),\n .m_axi_wdata({ m00_axi_wdata }),\n .m_axi_wstrb({ m00_axi_wstrb }),\n .m_axi_wlast({ m00_axi_wlast }),\n .m_axi_wuser({ m00_axi_wuser }),\n .m_axi_wvalid({ m00_axi_wvalid }),\n .m_axi_wready({ m00_axi_wready }),\n .m_axi_bid({ m00_axi_bid }),\n .m_axi_bresp({ m00_axi_bresp }),\n .m_axi_buser({ m00_axi_buser }),\n .m_axi_bvalid({ m00_axi_bvalid }),\n .m_axi_bready({ m00_axi_bready }),\n .m_axi_arid({ m00_axi_arid }),\n .m_axi_araddr({ m00_axi_araddr }),\n .m_axi_arlen({ m00_axi_arlen }),\n .m_axi_arsize({ m00_axi_arsize }),\n .m_axi_arburst({ m00_axi_arburst }),\n .m_axi_arlock({ m00_axi_arlock }),\n .m_axi_arcache({ m00_axi_arcache }),\n .m_axi_arprot({ m00_axi_arprot }),\n .m_axi_arqos({ m00_axi_arqos }),\n .m_axi_arregion({ m00_axi_arregion }),\n .m_axi_aruser({ m00_axi_aruser }),\n .m_axi_arvalid({ m00_axi_arvalid }),\n .m_axi_arready({ m00_axi_arready }),\n .m_axi_rid({ m00_axi_rid }),\n .m_axi_rdata({ m00_axi_rdata }),\n .m_axi_rresp({ m00_axi_rresp }),\n .m_axi_rlast({ m00_axi_rlast }),\n .m_axi_ruser({ m00_axi_ruser }),\n .m_axi_rvalid({ m00_axi_rvalid }),\n .m_axi_rready({ m00_axi_rready })\n);\n\nendmodule\n\n`resetall\n" }, { "path": "testbench/axi4_mux/axi_register_rd.v", "content": "/*\n\nCopyright (c) 2018 Alex Forencich\nCopyright 2024 Antmicro \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n`default_nettype none\n\n/*\n * AXI4 register (read)\n */\nmodule axi_register_rd #\n(\n // Width of data bus in bits\n parameter DATA_WIDTH = 32,\n // Width of address bus in bits\n parameter ADDR_WIDTH = 32,\n // Width of wstrb (width of data bus in words)\n parameter STRB_WIDTH = (DATA_WIDTH/8),\n // Width of ID signal\n parameter ID_WIDTH = 8,\n // Propagate aruser signal\n parameter ARUSER_ENABLE = 0,\n // Width of aruser signal\n parameter ARUSER_WIDTH = 1,\n // Propagate ruser signal\n parameter RUSER_ENABLE = 0,\n // Width of ruser signal\n parameter RUSER_WIDTH = 1,\n // AR channel register type\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter AR_REG_TYPE = 1,\n // R channel register type\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter R_REG_TYPE = 2\n)\n(\n input wire clk,\n input wire rst,\n\n /*\n * AXI slave interface\n */\n input wire [ID_WIDTH-1:0] s_axi_arid,\n input wire [ADDR_WIDTH-1:0] s_axi_araddr,\n input wire [7:0] s_axi_arlen,\n input wire [2:0] s_axi_arsize,\n input wire [1:0] s_axi_arburst,\n input wire s_axi_arlock,\n input wire [3:0] s_axi_arcache,\n input wire [2:0] s_axi_arprot,\n input wire [3:0] s_axi_arqos,\n input wire [3:0] s_axi_arregion,\n input wire [ARUSER_WIDTH-1:0] s_axi_aruser,\n input wire s_axi_arvalid,\n output wire s_axi_arready,\n output wire [ID_WIDTH-1:0] s_axi_rid,\n output wire [DATA_WIDTH-1:0] s_axi_rdata,\n output wire [1:0] s_axi_rresp,\n output wire s_axi_rlast,\n output wire [RUSER_WIDTH-1:0] s_axi_ruser,\n output wire s_axi_rvalid,\n input wire s_axi_rready,\n\n /*\n * AXI master interface\n */\n output wire [ID_WIDTH-1:0] m_axi_arid,\n output wire [ADDR_WIDTH-1:0] m_axi_araddr,\n output wire [7:0] m_axi_arlen,\n output wire [2:0] m_axi_arsize,\n output wire [1:0] m_axi_arburst,\n output wire m_axi_arlock,\n output wire [3:0] m_axi_arcache,\n output wire [2:0] m_axi_arprot,\n output wire [3:0] m_axi_arqos,\n output wire [3:0] m_axi_arregion,\n output wire [ARUSER_WIDTH-1:0] m_axi_aruser,\n output wire m_axi_arvalid,\n input wire m_axi_arready,\n input wire [ID_WIDTH-1:0] m_axi_rid,\n input wire [DATA_WIDTH-1:0] m_axi_rdata,\n input wire [1:0] m_axi_rresp,\n input wire m_axi_rlast,\n input wire [RUSER_WIDTH-1:0] m_axi_ruser,\n input wire m_axi_rvalid,\n output wire m_axi_rready\n);\n\ngenerate\n\n// AR channel\n\nif (AR_REG_TYPE > 1) begin\n// skid buffer, no bubble cycles\n\n// datapath registers\nreg s_axi_arready_reg = 1'b0;\n\nreg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}};\nreg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}};\nreg [7:0] m_axi_arlen_reg = 8'd0;\nreg [2:0] m_axi_arsize_reg = 3'd0;\nreg [1:0] m_axi_arburst_reg = 2'd0;\nreg m_axi_arlock_reg = 1'b0;\nreg [3:0] m_axi_arcache_reg = 4'd0;\nreg [2:0] m_axi_arprot_reg = 3'd0;\nreg [3:0] m_axi_arqos_reg = 4'd0;\nreg [3:0] m_axi_arregion_reg = 4'd0;\nreg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}};\nreg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;\n\nreg [ID_WIDTH-1:0] temp_m_axi_arid_reg = {ID_WIDTH{1'b0}};\nreg [ADDR_WIDTH-1:0] temp_m_axi_araddr_reg = {ADDR_WIDTH{1'b0}};\nreg [7:0] temp_m_axi_arlen_reg = 8'd0;\nreg [2:0] temp_m_axi_arsize_reg = 3'd0;\nreg [1:0] temp_m_axi_arburst_reg = 2'd0;\nreg temp_m_axi_arlock_reg = 1'b0;\nreg [3:0] temp_m_axi_arcache_reg = 4'd0;\nreg [2:0] temp_m_axi_arprot_reg = 3'd0;\nreg [3:0] temp_m_axi_arqos_reg = 4'd0;\nreg [3:0] temp_m_axi_arregion_reg = 4'd0;\nreg [ARUSER_WIDTH-1:0] temp_m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}};\nreg temp_m_axi_arvalid_reg = 1'b0, temp_m_axi_arvalid_next;\n\n// datapath control\nreg store_axi_ar_input_to_output;\nreg store_axi_ar_input_to_temp;\nreg store_axi_ar_temp_to_output;\n\nassign s_axi_arready = s_axi_arready_reg;\n\nassign m_axi_arid = m_axi_arid_reg;\nassign m_axi_araddr = m_axi_araddr_reg;\nassign m_axi_arlen = m_axi_arlen_reg;\nassign m_axi_arsize = m_axi_arsize_reg;\nassign m_axi_arburst = m_axi_arburst_reg;\nassign m_axi_arlock = m_axi_arlock_reg;\nassign m_axi_arcache = m_axi_arcache_reg;\nassign m_axi_arprot = m_axi_arprot_reg;\nassign m_axi_arqos = m_axi_arqos_reg;\nassign m_axi_arregion = m_axi_arregion_reg;\nassign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};\nassign m_axi_arvalid = m_axi_arvalid_reg;\n\n// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)\nwire s_axi_arready_early = m_axi_arready | (~temp_m_axi_arvalid_reg & (~m_axi_arvalid_reg | ~s_axi_arvalid));\n\nalways @* begin\n // transfer sink ready state to source\n m_axi_arvalid_next = m_axi_arvalid_reg;\n temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg;\n\n store_axi_ar_input_to_output = 1'b0;\n store_axi_ar_input_to_temp = 1'b0;\n store_axi_ar_temp_to_output = 1'b0;\n\n if (s_axi_arready_reg) begin\n // input is ready\n if (m_axi_arready | ~m_axi_arvalid_reg) begin\n // output is ready or currently not valid, transfer data to output\n m_axi_arvalid_next = s_axi_arvalid;\n store_axi_ar_input_to_output = 1'b1;\n end else begin\n // output is not ready, store input in temp\n temp_m_axi_arvalid_next = s_axi_arvalid;\n store_axi_ar_input_to_temp = 1'b1;\n end\n end else if (m_axi_arready) begin\n // input is not ready, but output is ready\n m_axi_arvalid_next = temp_m_axi_arvalid_reg;\n temp_m_axi_arvalid_next = 1'b0;\n store_axi_ar_temp_to_output = 1'b1;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n s_axi_arready_reg <= 1'b0;\n m_axi_arvalid_reg <= 1'b0;\n temp_m_axi_arvalid_reg <= 1'b0;\n end else begin\n s_axi_arready_reg <= s_axi_arready_early;\n m_axi_arvalid_reg <= m_axi_arvalid_next;\n temp_m_axi_arvalid_reg <= temp_m_axi_arvalid_next;\n end\n\n // datapath\n if (store_axi_ar_input_to_output) begin\n m_axi_arid_reg <= s_axi_arid;\n m_axi_araddr_reg <= s_axi_araddr;\n m_axi_arlen_reg <= s_axi_arlen;\n m_axi_arsize_reg <= s_axi_arsize;\n m_axi_arburst_reg <= s_axi_arburst;\n m_axi_arlock_reg <= s_axi_arlock;\n m_axi_arcache_reg <= s_axi_arcache;\n m_axi_arprot_reg <= s_axi_arprot;\n m_axi_arqos_reg <= s_axi_arqos;\n m_axi_arregion_reg <= s_axi_arregion;\n m_axi_aruser_reg <= s_axi_aruser;\n end else if (store_axi_ar_temp_to_output) begin\n m_axi_arid_reg <= temp_m_axi_arid_reg;\n m_axi_araddr_reg <= temp_m_axi_araddr_reg;\n m_axi_arlen_reg <= temp_m_axi_arlen_reg;\n m_axi_arsize_reg <= temp_m_axi_arsize_reg;\n m_axi_arburst_reg <= temp_m_axi_arburst_reg;\n m_axi_arlock_reg <= temp_m_axi_arlock_reg;\n m_axi_arcache_reg <= temp_m_axi_arcache_reg;\n m_axi_arprot_reg <= temp_m_axi_arprot_reg;\n m_axi_arqos_reg <= temp_m_axi_arqos_reg;\n m_axi_arregion_reg <= temp_m_axi_arregion_reg;\n m_axi_aruser_reg <= temp_m_axi_aruser_reg;\n end\n\n if (store_axi_ar_input_to_temp) begin\n temp_m_axi_arid_reg <= s_axi_arid;\n temp_m_axi_araddr_reg <= s_axi_araddr;\n temp_m_axi_arlen_reg <= s_axi_arlen;\n temp_m_axi_arsize_reg <= s_axi_arsize;\n temp_m_axi_arburst_reg <= s_axi_arburst;\n temp_m_axi_arlock_reg <= s_axi_arlock;\n temp_m_axi_arcache_reg <= s_axi_arcache;\n temp_m_axi_arprot_reg <= s_axi_arprot;\n temp_m_axi_arqos_reg <= s_axi_arqos;\n temp_m_axi_arregion_reg <= s_axi_arregion;\n temp_m_axi_aruser_reg <= s_axi_aruser;\n end\nend\n\nend else if (AR_REG_TYPE == 1) begin\n// simple register, inserts bubble cycles\n\n// datapath registers\nreg s_axi_arready_reg = 1'b0;\n\nreg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}};\nreg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}};\nreg [7:0] m_axi_arlen_reg = 8'd0;\nreg [2:0] m_axi_arsize_reg = 3'd0;\nreg [1:0] m_axi_arburst_reg = 2'd0;\nreg m_axi_arlock_reg = 1'b0;\nreg [3:0] m_axi_arcache_reg = 4'd0;\nreg [2:0] m_axi_arprot_reg = 3'd0;\nreg [3:0] m_axi_arqos_reg = 4'd0;\nreg [3:0] m_axi_arregion_reg = 4'd0;\nreg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}};\nreg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;\n\n// datapath control\nreg store_axi_ar_input_to_output;\n\nassign s_axi_arready = s_axi_arready_reg;\n\nassign m_axi_arid = m_axi_arid_reg;\nassign m_axi_araddr = m_axi_araddr_reg;\nassign m_axi_arlen = m_axi_arlen_reg;\nassign m_axi_arsize = m_axi_arsize_reg;\nassign m_axi_arburst = m_axi_arburst_reg;\nassign m_axi_arlock = m_axi_arlock_reg;\nassign m_axi_arcache = m_axi_arcache_reg;\nassign m_axi_arprot = m_axi_arprot_reg;\nassign m_axi_arqos = m_axi_arqos_reg;\nassign m_axi_arregion = m_axi_arregion_reg;\nassign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};\nassign m_axi_arvalid = m_axi_arvalid_reg;\n\n// enable ready input next cycle if output buffer will be empty\nwire s_axi_arready_early = !m_axi_arvalid_next;\n\nalways @* begin\n // transfer sink ready state to source\n m_axi_arvalid_next = m_axi_arvalid_reg;\n\n store_axi_ar_input_to_output = 1'b0;\n\n if (s_axi_arready_reg) begin\n m_axi_arvalid_next = s_axi_arvalid;\n store_axi_ar_input_to_output = 1'b1;\n end else if (m_axi_arready) begin\n m_axi_arvalid_next = 1'b0;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n s_axi_arready_reg <= 1'b0;\n m_axi_arvalid_reg <= 1'b0;\n end else begin\n s_axi_arready_reg <= s_axi_arready_early;\n m_axi_arvalid_reg <= m_axi_arvalid_next;\n end\n\n // datapath\n if (store_axi_ar_input_to_output) begin\n m_axi_arid_reg <= s_axi_arid;\n m_axi_araddr_reg <= s_axi_araddr;\n m_axi_arlen_reg <= s_axi_arlen;\n m_axi_arsize_reg <= s_axi_arsize;\n m_axi_arburst_reg <= s_axi_arburst;\n m_axi_arlock_reg <= s_axi_arlock;\n m_axi_arcache_reg <= s_axi_arcache;\n m_axi_arprot_reg <= s_axi_arprot;\n m_axi_arqos_reg <= s_axi_arqos;\n m_axi_arregion_reg <= s_axi_arregion;\n m_axi_aruser_reg <= s_axi_aruser;\n end\nend\n\nend else begin\n\n // bypass AR channel\n assign m_axi_arid = s_axi_arid;\n assign m_axi_araddr = s_axi_araddr;\n assign m_axi_arlen = s_axi_arlen;\n assign m_axi_arsize = s_axi_arsize;\n assign m_axi_arburst = s_axi_arburst;\n assign m_axi_arlock = s_axi_arlock;\n assign m_axi_arcache = s_axi_arcache;\n assign m_axi_arprot = s_axi_arprot;\n assign m_axi_arqos = s_axi_arqos;\n assign m_axi_arregion = s_axi_arregion;\n assign m_axi_aruser = ARUSER_ENABLE ? s_axi_aruser : {ARUSER_WIDTH{1'b0}};\n assign m_axi_arvalid = s_axi_arvalid;\n assign s_axi_arready = m_axi_arready;\n\nend\n\n// R channel\n\nif (R_REG_TYPE > 1) begin\n// skid buffer, no bubble cycles\n\n// datapath registers\nreg m_axi_rready_reg = 1'b0;\n\nreg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}};\nreg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}};\nreg [1:0] s_axi_rresp_reg = 2'b0;\nreg s_axi_rlast_reg = 1'b0;\nreg [RUSER_WIDTH-1:0] s_axi_ruser_reg = {RUSER_WIDTH{1'b0}};\nreg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;\n\nreg [ID_WIDTH-1:0] temp_s_axi_rid_reg = {ID_WIDTH{1'b0}};\nreg [DATA_WIDTH-1:0] temp_s_axi_rdata_reg = {DATA_WIDTH{1'b0}};\nreg [1:0] temp_s_axi_rresp_reg = 2'b0;\nreg temp_s_axi_rlast_reg = 1'b0;\nreg [RUSER_WIDTH-1:0] temp_s_axi_ruser_reg = {RUSER_WIDTH{1'b0}};\nreg temp_s_axi_rvalid_reg = 1'b0, temp_s_axi_rvalid_next;\n\n// datapath control\nreg store_axi_r_input_to_output;\nreg store_axi_r_input_to_temp;\nreg store_axi_r_temp_to_output;\n\nassign m_axi_rready = m_axi_rready_reg;\n\nassign s_axi_rid = s_axi_rid_reg;\nassign s_axi_rdata = s_axi_rdata_reg;\nassign s_axi_rresp = s_axi_rresp_reg;\nassign s_axi_rlast = s_axi_rlast_reg;\nassign s_axi_ruser = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}};\nassign s_axi_rvalid = s_axi_rvalid_reg;\n\n// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)\nwire m_axi_rready_early = s_axi_rready | (~temp_s_axi_rvalid_reg & (~s_axi_rvalid_reg | ~m_axi_rvalid));\n\nalways @* begin\n // transfer sink ready state to source\n s_axi_rvalid_next = s_axi_rvalid_reg;\n temp_s_axi_rvalid_next = temp_s_axi_rvalid_reg;\n\n store_axi_r_input_to_output = 1'b0;\n store_axi_r_input_to_temp = 1'b0;\n store_axi_r_temp_to_output = 1'b0;\n\n if (m_axi_rready_reg) begin\n // input is ready\n if (s_axi_rready | ~s_axi_rvalid_reg) begin\n // output is ready or currently not valid, transfer data to output\n s_axi_rvalid_next = m_axi_rvalid;\n store_axi_r_input_to_output = 1'b1;\n end else begin\n // output is not ready, store input in temp\n temp_s_axi_rvalid_next = m_axi_rvalid;\n store_axi_r_input_to_temp = 1'b1;\n end\n end else if (s_axi_rready) begin\n // input is not ready, but output is ready\n s_axi_rvalid_next = temp_s_axi_rvalid_reg;\n temp_s_axi_rvalid_next = 1'b0;\n store_axi_r_temp_to_output = 1'b1;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n m_axi_rready_reg <= 1'b0;\n s_axi_rvalid_reg <= 1'b0;\n temp_s_axi_rvalid_reg <= 1'b0;\n end else begin\n m_axi_rready_reg <= m_axi_rready_early;\n s_axi_rvalid_reg <= s_axi_rvalid_next;\n temp_s_axi_rvalid_reg <= temp_s_axi_rvalid_next;\n end\n\n // datapath\n if (store_axi_r_input_to_output) begin\n s_axi_rid_reg <= m_axi_rid;\n s_axi_rdata_reg <= m_axi_rdata;\n s_axi_rresp_reg <= m_axi_rresp;\n s_axi_rlast_reg <= m_axi_rlast;\n s_axi_ruser_reg <= m_axi_ruser;\n end else if (store_axi_r_temp_to_output) begin\n s_axi_rid_reg <= temp_s_axi_rid_reg;\n s_axi_rdata_reg <= temp_s_axi_rdata_reg;\n s_axi_rresp_reg <= temp_s_axi_rresp_reg;\n s_axi_rlast_reg <= temp_s_axi_rlast_reg;\n s_axi_ruser_reg <= temp_s_axi_ruser_reg;\n end\n\n if (store_axi_r_input_to_temp) begin\n temp_s_axi_rid_reg <= m_axi_rid;\n temp_s_axi_rdata_reg <= m_axi_rdata;\n temp_s_axi_rresp_reg <= m_axi_rresp;\n temp_s_axi_rlast_reg <= m_axi_rlast;\n temp_s_axi_ruser_reg <= m_axi_ruser;\n end\nend\n\nend else if (R_REG_TYPE == 1) begin\n// simple register, inserts bubble cycles\n\n// datapath registers\nreg m_axi_rready_reg = 1'b0;\n\nreg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}};\nreg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}};\nreg [1:0] s_axi_rresp_reg = 2'b0;\nreg s_axi_rlast_reg = 1'b0;\nreg [RUSER_WIDTH-1:0] s_axi_ruser_reg = {RUSER_WIDTH{1'b0}};\nreg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;\n\n// datapath control\nreg store_axi_r_input_to_output;\n\nassign m_axi_rready = m_axi_rready_reg;\n\nassign s_axi_rid = s_axi_rid_reg;\nassign s_axi_rdata = s_axi_rdata_reg;\nassign s_axi_rresp = s_axi_rresp_reg;\nassign s_axi_rlast = s_axi_rlast_reg;\nassign s_axi_ruser = RUSER_ENABLE ? s_axi_ruser_reg : {RUSER_WIDTH{1'b0}};\nassign s_axi_rvalid = s_axi_rvalid_reg;\n\n// enable ready input next cycle if output buffer will be empty\nwire m_axi_rready_early = !s_axi_rvalid_next;\n\nalways @* begin\n // transfer sink ready state to source\n s_axi_rvalid_next = s_axi_rvalid_reg;\n\n store_axi_r_input_to_output = 1'b0;\n\n if (m_axi_rready_reg) begin\n s_axi_rvalid_next = m_axi_rvalid;\n store_axi_r_input_to_output = 1'b1;\n end else if (s_axi_rready) begin\n s_axi_rvalid_next = 1'b0;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n m_axi_rready_reg <= 1'b0;\n s_axi_rvalid_reg <= 1'b0;\n end else begin\n m_axi_rready_reg <= m_axi_rready_early;\n s_axi_rvalid_reg <= s_axi_rvalid_next;\n end\n\n // datapath\n if (store_axi_r_input_to_output) begin\n s_axi_rid_reg <= m_axi_rid;\n s_axi_rdata_reg <= m_axi_rdata;\n s_axi_rresp_reg <= m_axi_rresp;\n s_axi_rlast_reg <= m_axi_rlast;\n s_axi_ruser_reg <= m_axi_ruser;\n end\nend\n\nend else begin\n\n // bypass R channel\n assign s_axi_rid = m_axi_rid;\n assign s_axi_rdata = m_axi_rdata;\n assign s_axi_rresp = m_axi_rresp;\n assign s_axi_rlast = m_axi_rlast;\n assign s_axi_ruser = RUSER_ENABLE ? m_axi_ruser : {RUSER_WIDTH{1'b0}};\n assign s_axi_rvalid = m_axi_rvalid;\n assign m_axi_rready = s_axi_rready;\n\nend\n\nendgenerate\n\nendmodule\n\n`resetall\n" }, { "path": "testbench/axi4_mux/axi_register_wr.v", "content": "/*\n\nCopyright (c) 2018 Alex Forencich\nCopyright 2024 Antmicro \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n`default_nettype none\n\n/*\n * AXI4 register (write)\n */\nmodule axi_register_wr #\n(\n // Width of data bus in bits\n parameter DATA_WIDTH = 32,\n // Width of address bus in bits\n parameter ADDR_WIDTH = 32,\n // Width of wstrb (width of data bus in words)\n parameter STRB_WIDTH = (DATA_WIDTH/8),\n // Width of ID signal\n parameter ID_WIDTH = 8,\n // Propagate awuser signal\n parameter AWUSER_ENABLE = 0,\n // Width of awuser signal\n parameter AWUSER_WIDTH = 1,\n // Propagate wuser signal\n parameter WUSER_ENABLE = 0,\n // Width of wuser signal\n parameter WUSER_WIDTH = 1,\n // Propagate buser signal\n parameter BUSER_ENABLE = 0,\n // Width of buser signal\n parameter BUSER_WIDTH = 1,\n // AW channel register type\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter AW_REG_TYPE = 1,\n // W channel register type\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter W_REG_TYPE = 2,\n // B channel register type\n // 0 to bypass, 1 for simple buffer, 2 for skid buffer\n parameter B_REG_TYPE = 1\n)\n(\n input wire clk,\n input wire rst,\n\n /*\n * AXI slave interface\n */\n input wire [ID_WIDTH-1:0] s_axi_awid,\n input wire [ADDR_WIDTH-1:0] s_axi_awaddr,\n input wire [7:0] s_axi_awlen,\n input wire [2:0] s_axi_awsize,\n input wire [1:0] s_axi_awburst,\n input wire s_axi_awlock,\n input wire [3:0] s_axi_awcache,\n input wire [2:0] s_axi_awprot,\n input wire [3:0] s_axi_awqos,\n input wire [3:0] s_axi_awregion,\n input wire [AWUSER_WIDTH-1:0] s_axi_awuser,\n input wire s_axi_awvalid,\n output wire s_axi_awready,\n input wire [DATA_WIDTH-1:0] s_axi_wdata,\n input wire [STRB_WIDTH-1:0] s_axi_wstrb,\n input wire s_axi_wlast,\n input wire [WUSER_WIDTH-1:0] s_axi_wuser,\n input wire s_axi_wvalid,\n output wire s_axi_wready,\n output wire [ID_WIDTH-1:0] s_axi_bid,\n output wire [1:0] s_axi_bresp,\n output wire [BUSER_WIDTH-1:0] s_axi_buser,\n output wire s_axi_bvalid,\n input wire s_axi_bready,\n\n /*\n * AXI master interface\n */\n output wire [ID_WIDTH-1:0] m_axi_awid,\n output wire [ADDR_WIDTH-1:0] m_axi_awaddr,\n output wire [7:0] m_axi_awlen,\n output wire [2:0] m_axi_awsize,\n output wire [1:0] m_axi_awburst,\n output wire m_axi_awlock,\n output wire [3:0] m_axi_awcache,\n output wire [2:0] m_axi_awprot,\n output wire [3:0] m_axi_awqos,\n output wire [3:0] m_axi_awregion,\n output wire [AWUSER_WIDTH-1:0] m_axi_awuser,\n output wire m_axi_awvalid,\n input wire m_axi_awready,\n output wire [DATA_WIDTH-1:0] m_axi_wdata,\n output wire [STRB_WIDTH-1:0] m_axi_wstrb,\n output wire m_axi_wlast,\n output wire [WUSER_WIDTH-1:0] m_axi_wuser,\n output wire m_axi_wvalid,\n input wire m_axi_wready,\n input wire [ID_WIDTH-1:0] m_axi_bid,\n input wire [1:0] m_axi_bresp,\n input wire [BUSER_WIDTH-1:0] m_axi_buser,\n input wire m_axi_bvalid,\n output wire m_axi_bready\n);\n\ngenerate\n\n// AW channel\n\nif (AW_REG_TYPE > 1) begin\n// skid buffer, no bubble cycles\n\n// datapath registers\nreg s_axi_awready_reg = 1'b0;\n\nreg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}};\nreg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}};\nreg [7:0] m_axi_awlen_reg = 8'd0;\nreg [2:0] m_axi_awsize_reg = 3'd0;\nreg [1:0] m_axi_awburst_reg = 2'd0;\nreg m_axi_awlock_reg = 1'b0;\nreg [3:0] m_axi_awcache_reg = 4'd0;\nreg [2:0] m_axi_awprot_reg = 3'd0;\nreg [3:0] m_axi_awqos_reg = 4'd0;\nreg [3:0] m_axi_awregion_reg = 4'd0;\nreg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}};\nreg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;\n\nreg [ID_WIDTH-1:0] temp_m_axi_awid_reg = {ID_WIDTH{1'b0}};\nreg [ADDR_WIDTH-1:0] temp_m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}};\nreg [7:0] temp_m_axi_awlen_reg = 8'd0;\nreg [2:0] temp_m_axi_awsize_reg = 3'd0;\nreg [1:0] temp_m_axi_awburst_reg = 2'd0;\nreg temp_m_axi_awlock_reg = 1'b0;\nreg [3:0] temp_m_axi_awcache_reg = 4'd0;\nreg [2:0] temp_m_axi_awprot_reg = 3'd0;\nreg [3:0] temp_m_axi_awqos_reg = 4'd0;\nreg [3:0] temp_m_axi_awregion_reg = 4'd0;\nreg [AWUSER_WIDTH-1:0] temp_m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}};\nreg temp_m_axi_awvalid_reg = 1'b0, temp_m_axi_awvalid_next;\n\n// datapath control\nreg store_axi_aw_input_to_output;\nreg store_axi_aw_input_to_temp;\nreg store_axi_aw_temp_to_output;\n\nassign s_axi_awready = s_axi_awready_reg;\n\nassign m_axi_awid = m_axi_awid_reg;\nassign m_axi_awaddr = m_axi_awaddr_reg;\nassign m_axi_awlen = m_axi_awlen_reg;\nassign m_axi_awsize = m_axi_awsize_reg;\nassign m_axi_awburst = m_axi_awburst_reg;\nassign m_axi_awlock = m_axi_awlock_reg;\nassign m_axi_awcache = m_axi_awcache_reg;\nassign m_axi_awprot = m_axi_awprot_reg;\nassign m_axi_awqos = m_axi_awqos_reg;\nassign m_axi_awregion = m_axi_awregion_reg;\nassign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};\nassign m_axi_awvalid = m_axi_awvalid_reg;\n\n// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)\nwire s_axi_awready_early = m_axi_awready | (~temp_m_axi_awvalid_reg & (~m_axi_awvalid_reg | ~s_axi_awvalid));\n\nalways @* begin\n // transfer sink ready state to source\n m_axi_awvalid_next = m_axi_awvalid_reg;\n temp_m_axi_awvalid_next = temp_m_axi_awvalid_reg;\n\n store_axi_aw_input_to_output = 1'b0;\n store_axi_aw_input_to_temp = 1'b0;\n store_axi_aw_temp_to_output = 1'b0;\n\n if (s_axi_awready_reg) begin\n // input is ready\n if (m_axi_awready | ~m_axi_awvalid_reg) begin\n // output is ready or currently not valid, transfer data to output\n m_axi_awvalid_next = s_axi_awvalid;\n store_axi_aw_input_to_output = 1'b1;\n end else begin\n // output is not ready, store input in temp\n temp_m_axi_awvalid_next = s_axi_awvalid;\n store_axi_aw_input_to_temp = 1'b1;\n end\n end else if (m_axi_awready) begin\n // input is not ready, but output is ready\n m_axi_awvalid_next = temp_m_axi_awvalid_reg;\n temp_m_axi_awvalid_next = 1'b0;\n store_axi_aw_temp_to_output = 1'b1;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n s_axi_awready_reg <= 1'b0;\n m_axi_awvalid_reg <= 1'b0;\n temp_m_axi_awvalid_reg <= 1'b0;\n end else begin\n s_axi_awready_reg <= s_axi_awready_early;\n m_axi_awvalid_reg <= m_axi_awvalid_next;\n temp_m_axi_awvalid_reg <= temp_m_axi_awvalid_next;\n end\n\n // datapath\n if (store_axi_aw_input_to_output) begin\n m_axi_awid_reg <= s_axi_awid;\n m_axi_awaddr_reg <= s_axi_awaddr;\n m_axi_awlen_reg <= s_axi_awlen;\n m_axi_awsize_reg <= s_axi_awsize;\n m_axi_awburst_reg <= s_axi_awburst;\n m_axi_awlock_reg <= s_axi_awlock;\n m_axi_awcache_reg <= s_axi_awcache;\n m_axi_awprot_reg <= s_axi_awprot;\n m_axi_awqos_reg <= s_axi_awqos;\n m_axi_awregion_reg <= s_axi_awregion;\n m_axi_awuser_reg <= s_axi_awuser;\n end else if (store_axi_aw_temp_to_output) begin\n m_axi_awid_reg <= temp_m_axi_awid_reg;\n m_axi_awaddr_reg <= temp_m_axi_awaddr_reg;\n m_axi_awlen_reg <= temp_m_axi_awlen_reg;\n m_axi_awsize_reg <= temp_m_axi_awsize_reg;\n m_axi_awburst_reg <= temp_m_axi_awburst_reg;\n m_axi_awlock_reg <= temp_m_axi_awlock_reg;\n m_axi_awcache_reg <= temp_m_axi_awcache_reg;\n m_axi_awprot_reg <= temp_m_axi_awprot_reg;\n m_axi_awqos_reg <= temp_m_axi_awqos_reg;\n m_axi_awregion_reg <= temp_m_axi_awregion_reg;\n m_axi_awuser_reg <= temp_m_axi_awuser_reg;\n end\n\n if (store_axi_aw_input_to_temp) begin\n temp_m_axi_awid_reg <= s_axi_awid;\n temp_m_axi_awaddr_reg <= s_axi_awaddr;\n temp_m_axi_awlen_reg <= s_axi_awlen;\n temp_m_axi_awsize_reg <= s_axi_awsize;\n temp_m_axi_awburst_reg <= s_axi_awburst;\n temp_m_axi_awlock_reg <= s_axi_awlock;\n temp_m_axi_awcache_reg <= s_axi_awcache;\n temp_m_axi_awprot_reg <= s_axi_awprot;\n temp_m_axi_awqos_reg <= s_axi_awqos;\n temp_m_axi_awregion_reg <= s_axi_awregion;\n temp_m_axi_awuser_reg <= s_axi_awuser;\n end\nend\n\nend else if (AW_REG_TYPE == 1) begin\n// simple register, inserts bubble cycles\n\n// datapath registers\nreg s_axi_awready_reg = 1'b0;\n\nreg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}};\nreg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}};\nreg [7:0] m_axi_awlen_reg = 8'd0;\nreg [2:0] m_axi_awsize_reg = 3'd0;\nreg [1:0] m_axi_awburst_reg = 2'd0;\nreg m_axi_awlock_reg = 1'b0;\nreg [3:0] m_axi_awcache_reg = 4'd0;\nreg [2:0] m_axi_awprot_reg = 3'd0;\nreg [3:0] m_axi_awqos_reg = 4'd0;\nreg [3:0] m_axi_awregion_reg = 4'd0;\nreg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}};\nreg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;\n\n// datapath control\nreg store_axi_aw_input_to_output;\n\nassign s_axi_awready = s_axi_awready_reg;\n\nassign m_axi_awid = m_axi_awid_reg;\nassign m_axi_awaddr = m_axi_awaddr_reg;\nassign m_axi_awlen = m_axi_awlen_reg;\nassign m_axi_awsize = m_axi_awsize_reg;\nassign m_axi_awburst = m_axi_awburst_reg;\nassign m_axi_awlock = m_axi_awlock_reg;\nassign m_axi_awcache = m_axi_awcache_reg;\nassign m_axi_awprot = m_axi_awprot_reg;\nassign m_axi_awqos = m_axi_awqos_reg;\nassign m_axi_awregion = m_axi_awregion_reg;\nassign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};\nassign m_axi_awvalid = m_axi_awvalid_reg;\n\n// enable ready input next cycle if output buffer will be empty\nwire s_axi_awready_eawly = !m_axi_awvalid_next;\n\nalways @* begin\n // transfer sink ready state to source\n m_axi_awvalid_next = m_axi_awvalid_reg;\n\n store_axi_aw_input_to_output = 1'b0;\n\n if (s_axi_awready_reg) begin\n m_axi_awvalid_next = s_axi_awvalid;\n store_axi_aw_input_to_output = 1'b1;\n end else if (m_axi_awready) begin\n m_axi_awvalid_next = 1'b0;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n s_axi_awready_reg <= 1'b0;\n m_axi_awvalid_reg <= 1'b0;\n end else begin\n s_axi_awready_reg <= s_axi_awready_eawly;\n m_axi_awvalid_reg <= m_axi_awvalid_next;\n end\n\n // datapath\n if (store_axi_aw_input_to_output) begin\n m_axi_awid_reg <= s_axi_awid;\n m_axi_awaddr_reg <= s_axi_awaddr;\n m_axi_awlen_reg <= s_axi_awlen;\n m_axi_awsize_reg <= s_axi_awsize;\n m_axi_awburst_reg <= s_axi_awburst;\n m_axi_awlock_reg <= s_axi_awlock;\n m_axi_awcache_reg <= s_axi_awcache;\n m_axi_awprot_reg <= s_axi_awprot;\n m_axi_awqos_reg <= s_axi_awqos;\n m_axi_awregion_reg <= s_axi_awregion;\n m_axi_awuser_reg <= s_axi_awuser;\n end\nend\n\nend else begin\n\n // bypass AW channel\n assign m_axi_awid = s_axi_awid;\n assign m_axi_awaddr = s_axi_awaddr;\n assign m_axi_awlen = s_axi_awlen;\n assign m_axi_awsize = s_axi_awsize;\n assign m_axi_awburst = s_axi_awburst;\n assign m_axi_awlock = s_axi_awlock;\n assign m_axi_awcache = s_axi_awcache;\n assign m_axi_awprot = s_axi_awprot;\n assign m_axi_awqos = s_axi_awqos;\n assign m_axi_awregion = s_axi_awregion;\n assign m_axi_awuser = AWUSER_ENABLE ? s_axi_awuser : {AWUSER_WIDTH{1'b0}};\n assign m_axi_awvalid = s_axi_awvalid;\n assign s_axi_awready = m_axi_awready;\n\nend\n\n// W channel\n\nif (W_REG_TYPE > 1) begin\n// skid buffer, no bubble cycles\n\n// datapath registers\nreg s_axi_wready_reg = 1'b0;\n\nreg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}};\nreg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};\nreg m_axi_wlast_reg = 1'b0;\nreg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}};\nreg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;\n\nreg [DATA_WIDTH-1:0] temp_m_axi_wdata_reg = {DATA_WIDTH{1'b0}};\nreg [STRB_WIDTH-1:0] temp_m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};\nreg temp_m_axi_wlast_reg = 1'b0;\nreg [WUSER_WIDTH-1:0] temp_m_axi_wuser_reg = {WUSER_WIDTH{1'b0}};\nreg temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;\n\n// datapath control\nreg store_axi_w_input_to_output;\nreg store_axi_w_input_to_temp;\nreg store_axi_w_temp_to_output;\n\nassign s_axi_wready = s_axi_wready_reg;\n\nassign m_axi_wdata = m_axi_wdata_reg;\nassign m_axi_wstrb = m_axi_wstrb_reg;\nassign m_axi_wlast = m_axi_wlast_reg;\nassign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};\nassign m_axi_wvalid = m_axi_wvalid_reg;\n\n// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)\nwire s_axi_wready_early = m_axi_wready | (~temp_m_axi_wvalid_reg & (~m_axi_wvalid_reg | ~s_axi_wvalid));\n\nalways @* begin\n // transfer sink ready state to source\n m_axi_wvalid_next = m_axi_wvalid_reg;\n temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;\n\n store_axi_w_input_to_output = 1'b0;\n store_axi_w_input_to_temp = 1'b0;\n store_axi_w_temp_to_output = 1'b0;\n\n if (s_axi_wready_reg) begin\n // input is ready\n if (m_axi_wready | ~m_axi_wvalid_reg) begin\n // output is ready or currently not valid, transfer data to output\n m_axi_wvalid_next = s_axi_wvalid;\n store_axi_w_input_to_output = 1'b1;\n end else begin\n // output is not ready, store input in temp\n temp_m_axi_wvalid_next = s_axi_wvalid;\n store_axi_w_input_to_temp = 1'b1;\n end\n end else if (m_axi_wready) begin\n // input is not ready, but output is ready\n m_axi_wvalid_next = temp_m_axi_wvalid_reg;\n temp_m_axi_wvalid_next = 1'b0;\n store_axi_w_temp_to_output = 1'b1;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n s_axi_wready_reg <= 1'b0;\n m_axi_wvalid_reg <= 1'b0;\n temp_m_axi_wvalid_reg <= 1'b0;\n end else begin\n s_axi_wready_reg <= s_axi_wready_early;\n m_axi_wvalid_reg <= m_axi_wvalid_next;\n temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;\n end\n\n // datapath\n if (store_axi_w_input_to_output) begin\n m_axi_wdata_reg <= s_axi_wdata;\n m_axi_wstrb_reg <= s_axi_wstrb;\n m_axi_wlast_reg <= s_axi_wlast;\n m_axi_wuser_reg <= s_axi_wuser;\n end else if (store_axi_w_temp_to_output) begin\n m_axi_wdata_reg <= temp_m_axi_wdata_reg;\n m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;\n m_axi_wlast_reg <= temp_m_axi_wlast_reg;\n m_axi_wuser_reg <= temp_m_axi_wuser_reg;\n end\n\n if (store_axi_w_input_to_temp) begin\n temp_m_axi_wdata_reg <= s_axi_wdata;\n temp_m_axi_wstrb_reg <= s_axi_wstrb;\n temp_m_axi_wlast_reg <= s_axi_wlast;\n temp_m_axi_wuser_reg <= s_axi_wuser;\n end\nend\n\nend else if (W_REG_TYPE == 1) begin\n// simple register, inserts bubble cycles\n\n// datapath registers\nreg s_axi_wready_reg = 1'b0;\n\nreg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}};\nreg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};\nreg m_axi_wlast_reg = 1'b0;\nreg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}};\nreg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;\n\n// datapath control\nreg store_axi_w_input_to_output;\n\nassign s_axi_wready = s_axi_wready_reg;\n\nassign m_axi_wdata = m_axi_wdata_reg;\nassign m_axi_wstrb = m_axi_wstrb_reg;\nassign m_axi_wlast = m_axi_wlast_reg;\nassign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};\nassign m_axi_wvalid = m_axi_wvalid_reg;\n\n// enable ready input next cycle if output buffer will be empty\nwire s_axi_wready_ewly = !m_axi_wvalid_next;\n\nalways @* begin\n // transfer sink ready state to source\n m_axi_wvalid_next = m_axi_wvalid_reg;\n\n store_axi_w_input_to_output = 1'b0;\n\n if (s_axi_wready_reg) begin\n m_axi_wvalid_next = s_axi_wvalid;\n store_axi_w_input_to_output = 1'b1;\n end else if (m_axi_wready) begin\n m_axi_wvalid_next = 1'b0;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n s_axi_wready_reg <= 1'b0;\n m_axi_wvalid_reg <= 1'b0;\n end else begin\n s_axi_wready_reg <= s_axi_wready_ewly;\n m_axi_wvalid_reg <= m_axi_wvalid_next;\n end\n\n // datapath\n if (store_axi_w_input_to_output) begin\n m_axi_wdata_reg <= s_axi_wdata;\n m_axi_wstrb_reg <= s_axi_wstrb;\n m_axi_wlast_reg <= s_axi_wlast;\n m_axi_wuser_reg <= s_axi_wuser;\n end\nend\n\nend else begin\n\n // bypass W channel\n assign m_axi_wdata = s_axi_wdata;\n assign m_axi_wstrb = s_axi_wstrb;\n assign m_axi_wlast = s_axi_wlast;\n assign m_axi_wuser = WUSER_ENABLE ? s_axi_wuser : {WUSER_WIDTH{1'b0}};\n assign m_axi_wvalid = s_axi_wvalid;\n assign s_axi_wready = m_axi_wready;\n\nend\n\n// B channel\n\nif (B_REG_TYPE > 1) begin\n// skid buffer, no bubble cycles\n\n// datapath registers\nreg m_axi_bready_reg = 1'b0;\n\nreg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}};\nreg [1:0] s_axi_bresp_reg = 2'b0;\nreg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}};\nreg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;\n\nreg [ID_WIDTH-1:0] temp_s_axi_bid_reg = {ID_WIDTH{1'b0}};\nreg [1:0] temp_s_axi_bresp_reg = 2'b0;\nreg [BUSER_WIDTH-1:0] temp_s_axi_buser_reg = {BUSER_WIDTH{1'b0}};\nreg temp_s_axi_bvalid_reg = 1'b0, temp_s_axi_bvalid_next;\n\n// datapath control\nreg store_axi_b_input_to_output;\nreg store_axi_b_input_to_temp;\nreg store_axi_b_temp_to_output;\n\nassign m_axi_bready = m_axi_bready_reg;\n\nassign s_axi_bid = s_axi_bid_reg;\nassign s_axi_bresp = s_axi_bresp_reg;\nassign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};\nassign s_axi_bvalid = s_axi_bvalid_reg;\n\n// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)\nwire m_axi_bready_early = s_axi_bready | (~temp_s_axi_bvalid_reg & (~s_axi_bvalid_reg | ~m_axi_bvalid));\n\nalways @* begin\n // transfer sink ready state to source\n s_axi_bvalid_next = s_axi_bvalid_reg;\n temp_s_axi_bvalid_next = temp_s_axi_bvalid_reg;\n\n store_axi_b_input_to_output = 1'b0;\n store_axi_b_input_to_temp = 1'b0;\n store_axi_b_temp_to_output = 1'b0;\n\n if (m_axi_bready_reg) begin\n // input is ready\n if (s_axi_bready | ~s_axi_bvalid_reg) begin\n // output is ready or currently not valid, transfer data to output\n s_axi_bvalid_next = m_axi_bvalid;\n store_axi_b_input_to_output = 1'b1;\n end else begin\n // output is not ready, store input in temp\n temp_s_axi_bvalid_next = m_axi_bvalid;\n store_axi_b_input_to_temp = 1'b1;\n end\n end else if (s_axi_bready) begin\n // input is not ready, but output is ready\n s_axi_bvalid_next = temp_s_axi_bvalid_reg;\n temp_s_axi_bvalid_next = 1'b0;\n store_axi_b_temp_to_output = 1'b1;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n m_axi_bready_reg <= 1'b0;\n s_axi_bvalid_reg <= 1'b0;\n temp_s_axi_bvalid_reg <= 1'b0;\n end else begin\n m_axi_bready_reg <= m_axi_bready_early;\n s_axi_bvalid_reg <= s_axi_bvalid_next;\n temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next;\n end\n\n // datapath\n if (store_axi_b_input_to_output) begin\n s_axi_bid_reg <= m_axi_bid;\n s_axi_bresp_reg <= m_axi_bresp;\n s_axi_buser_reg <= m_axi_buser;\n end else if (store_axi_b_temp_to_output) begin\n s_axi_bid_reg <= temp_s_axi_bid_reg;\n s_axi_bresp_reg <= temp_s_axi_bresp_reg;\n s_axi_buser_reg <= temp_s_axi_buser_reg;\n end\n\n if (store_axi_b_input_to_temp) begin\n temp_s_axi_bid_reg <= m_axi_bid;\n temp_s_axi_bresp_reg <= m_axi_bresp;\n temp_s_axi_buser_reg <= m_axi_buser;\n end\nend\n\nend else if (B_REG_TYPE == 1) begin\n// simple register, inserts bubble cycles\n\n// datapath registers\nreg m_axi_bready_reg = 1'b0;\n\nreg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}};\nreg [1:0] s_axi_bresp_reg = 2'b0;\nreg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}};\nreg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;\n\n// datapath control\nreg store_axi_b_input_to_output;\n\nassign m_axi_bready = m_axi_bready_reg;\n\nassign s_axi_bid = s_axi_bid_reg;\nassign s_axi_bresp = s_axi_bresp_reg;\nassign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};\nassign s_axi_bvalid = s_axi_bvalid_reg;\n\n// enable ready input next cycle if output buffer will be empty\nwire m_axi_bready_early = !s_axi_bvalid_next;\n\nalways @* begin\n // transfer sink ready state to source\n s_axi_bvalid_next = s_axi_bvalid_reg;\n\n store_axi_b_input_to_output = 1'b0;\n\n if (m_axi_bready_reg) begin\n s_axi_bvalid_next = m_axi_bvalid;\n store_axi_b_input_to_output = 1'b1;\n end else if (s_axi_bready) begin\n s_axi_bvalid_next = 1'b0;\n end\nend\n\nalways @(posedge clk) begin\n if (rst) begin\n m_axi_bready_reg <= 1'b0;\n s_axi_bvalid_reg <= 1'b0;\n end else begin\n m_axi_bready_reg <= m_axi_bready_early;\n s_axi_bvalid_reg <= s_axi_bvalid_next;\n end\n\n // datapath\n if (store_axi_b_input_to_output) begin\n s_axi_bid_reg <= m_axi_bid;\n s_axi_bresp_reg <= m_axi_bresp;\n s_axi_buser_reg <= m_axi_buser;\n end\nend\n\nend else begin\n\n // bypass B channel\n assign s_axi_bid = m_axi_bid;\n assign s_axi_bresp = m_axi_bresp;\n assign s_axi_buser = BUSER_ENABLE ? m_axi_buser : {BUSER_WIDTH{1'b0}};\n assign s_axi_bvalid = m_axi_bvalid;\n assign m_axi_bready = s_axi_bready;\n\nend\n\nendgenerate\n\nendmodule\n\n`resetall\n" }, { "path": "testbench/axi4_mux/priority_encoder.v", "content": "/*\n\nCopyright (c) 2014-2021 Alex Forencich\nCopyright 2024 Antmicro \n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n`default_nettype none\n\n/*\n * Priority encoder module\n */\nmodule priority_encoder #\n(\n parameter WIDTH = 4,\n // LSB priority selection\n parameter LSB_HIGH_PRIORITY = 0\n)\n(\n input wire [WIDTH-1:0] input_unencoded,\n output wire output_valid,\n output wire [$clog2(WIDTH)-1:0] output_encoded,\n output wire [WIDTH-1:0] output_unencoded\n);\n\nparameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1;\nparameter W = 2**LEVELS;\n\n// pad input to even power of two\nwire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded};\n\nwire [W/2-1:0] stage_valid[LEVELS-1:0];\nwire [W/2-1:0] stage_enc[LEVELS-1:0];\n\ngenerate\n genvar l, n;\n\n // process input bits; generate valid bit and encoded bit for each pair\n for (n = 0; n < W/2; n = n + 1) begin : loop_in\n assign stage_valid[0][n] = |input_padded[n*2+1:n*2];\n if (LSB_HIGH_PRIORITY) begin\n // bit 0 is highest priority\n assign stage_enc[0][n] = !input_padded[n*2+0];\n end else begin\n // bit 0 is lowest priority\n assign stage_enc[0][n] = input_padded[n*2+1];\n end\n end\n\n // compress down to single valid bit and encoded bus\n for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels\n for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress\n assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];\n if (LSB_HIGH_PRIORITY) begin\n // bit 0 is highest priority\n assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};\n end else begin\n // bit 0 is lowest priority\n assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};\n end\n end\n end\nendgenerate\n\nassign output_valid = stage_valid[LEVELS-1];\nassign output_encoded = stage_enc[LEVELS-1];\nassign output_unencoded = 1 << output_encoded;\n\nendmodule\n\n`resetall\n" }, { "path": "testbench/axi_lsu_dma_bridge.sv", "content": "\n// connects LSI master to external AXI slave and DMA slave\nmodule axi_lsu_dma_bridge\n#(\nparameter M_ID_WIDTH = 8,\nparameter S0_ID_WIDTH = 8\n)\n(\ninput clk,\ninput reset_l,\n\n// master read bus\ninput m_arvalid,\ninput [M_ID_WIDTH-1:0] m_arid,\ninput[31:0] m_araddr,\noutput m_arready,\n\noutput m_rvalid,\ninput m_rready,\noutput [63:0] m_rdata,\noutput [M_ID_WIDTH-1:0] m_rid,\noutput [1:0] m_rresp,\noutput m_rlast,\n\n// master write bus\ninput m_awvalid,\ninput [M_ID_WIDTH-1:0] m_awid,\ninput[31:0] m_awaddr,\noutput m_awready,\n\ninput m_wvalid,\noutput m_wready,\n\noutput[1:0] m_bresp,\noutput m_bvalid,\noutput[M_ID_WIDTH-1:0] m_bid,\ninput m_bready,\n\n// slave 0 if general ext memory\noutput s0_arvalid,\ninput s0_arready,\n\ninput s0_rvalid,\ninput[S0_ID_WIDTH-1:0] s0_rid,\ninput[1:0] s0_rresp,\ninput[63:0] s0_rdata,\ninput s0_rlast,\noutput s0_rready,\n\noutput s0_awvalid,\ninput s0_awready,\n\noutput s0_wvalid,\ninput s0_wready,\n\ninput[1:0] s0_bresp,\ninput s0_bvalid,\ninput[S0_ID_WIDTH-1:0] s0_bid,\noutput s0_bready,\n\n// slave 1 if DMA port\noutput s1_arvalid,\ninput s1_arready,\n\ninput s1_rvalid,\ninput[1:0] s1_rresp,\ninput[63:0] s1_rdata,\ninput s1_rlast,\noutput s1_rready,\n\noutput s1_awvalid,\ninput s1_awready,\n\noutput s1_wvalid,\ninput s1_wready,\n\ninput[1:0] s1_bresp,\ninput s1_bvalid,\noutput s1_bready\n);\n\nparameter ICCM_BASE = `RV_ICCM_BITS; // in LSBs\nlocalparam IDFIFOSZ = $clog2(`RV_DMA_BUF_DEPTH);\nbit[31:0] iccm_real_base_addr = `RV_ICCM_SADR ;\n\nwire ar_slave_select;\nwire aw_slave_select;\nwire w_slave_select;\n\nwire rresp_select;\nwire bresp_select;\nwire ar_iccm_select;\nwire aw_iccm_select;\n\nreg [1:0] wsel_iptr, wsel_optr;\nreg [2:0] wsel_count;\nreg [3:0] wsel;\n\n\nreg [M_ID_WIDTH-1:0] arid [1<\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n\n#include \"jtagdpi.h\"\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"tcp_server.h\"\n\n// Uncomment to enable JTAG DPI debugging. The code will print vertically\n// oriented waveform for all JTAG signals.\n//#define JTAGDPI_DEBUG\n\nstruct jtagdpi_signals {\n uint8_t tck;\n uint8_t tms;\n uint8_t tdi;\n uint8_t tdo;\n uint8_t trst_n;\n uint8_t srst_n;\n};\n\nstruct jtagdpi_ctx {\n // Server context\n struct tcp_server_ctx *sock;\n // Signals\n struct jtagdpi_signals curr;\n#ifdef JTAGDPI_DEBUG\n struct jtagdpi_signals prev;\n uint8_t init;\n#endif\n};\n\n/**\n * Reset the JTAG signals to a \"dongle unplugged\" state\n */\nstatic void reset_jtag_signals(struct jtagdpi_ctx *ctx) {\n assert(ctx);\n\n // Set all to zero\n memset(&ctx->curr, 0, sizeof(struct jtagdpi_signals));\n#ifdef JTAGDPI_DEBUG\n memset(&ctx->prev, 0, sizeof(struct jtagdpi_signals));\n#endif\n\n // trst_n is pulled down (reset active) by default\n // srst_n is pulled up (reset not active) by default\n ctx->curr.srst_n = 1;\n#ifdef JTAGDPI_DEBUG\n ctx->prev.srst_n = 1;\n#endif\n}\n\n/**\n * Update the JTAG signals in the context structure\n */\nstatic void update_jtag_signals(struct jtagdpi_ctx *ctx) {\n assert(ctx);\n\n /*\n * Documentation pointer:\n * The remote_bitbang protocol implemented below is documented in the OpenOCD\n * source tree at doc/manual/jtag/drivers/remote_bitbang.txt, or online at\n * https://repo.or.cz/openocd.git/blob/HEAD:/doc/manual/jtag/drivers/remote_bitbang.txt\n */\n\n // read a command byte\n char cmd;\n if (!tcp_server_read(ctx->sock, &cmd)) {\n return;\n }\n\n bool act_send_resp = false;\n bool act_quit = false;\n\n // parse received command byte\n if (cmd >= '0' && cmd <= '7') {\n // JTAG write\n char cmd_bit = cmd - '0';\n ctx->curr.tdi = (cmd_bit >> 0) & 0x1;\n ctx->curr.tms = (cmd_bit >> 1) & 0x1;\n ctx->curr.tck = (cmd_bit >> 2) & 0x1;\n } else if (cmd >= 'r' && cmd <= 'u') {\n // JTAG reset (active high from OpenOCD)\n char cmd_bit = cmd - 'r';\n ctx->curr.srst_n = !((cmd_bit >> 0) & 0x1);\n ctx->curr.trst_n = !((cmd_bit >> 1) & 0x1);\n } else if (cmd == 'R') {\n // JTAG read\n act_send_resp = true;\n } else if (cmd == 'B') {\n // printf(\"%s: BLINK ON!\\n\", ctx->display_name);\n } else if (cmd == 'b') {\n // printf(\"%s: BLINK OFF!\\n\", ctx->display_name);\n } else if (cmd == 'Q') {\n // quit (client disconnect)\n act_quit = true;\n } else {\n fprintf(stderr,\n \"JTAG DPI Protocol violation detected: unsupported command %c\\n\",\n cmd);\n exit(1);\n }\n\n // send tdo as response\n if (act_send_resp) {\n char tdo_ascii = ctx->curr.tdo + '0';\n tcp_server_write(ctx->sock, tdo_ascii);\n }\n\n if (act_quit) {\n printf(\"JTAG DPI: Remote disconnected.\\n\");\n tcp_server_client_close(ctx->sock);\n }\n}\n\nvoid *jtagdpi_create(const char *display_name, int listen_port) {\n struct jtagdpi_ctx *ctx =\n (struct jtagdpi_ctx *)calloc(1, sizeof(struct jtagdpi_ctx));\n assert(ctx);\n\n // Create socket\n ctx->sock = tcp_server_create(display_name, listen_port);\n#ifdef JTAGDPI_DEBUG\n ctx->init = 1;\n#endif\n\n reset_jtag_signals(ctx);\n\n printf(\n \"\\n\"\n \"JTAG: Virtual JTAG interface %s is listening on port %d. Use\\n\"\n \"OpenOCD and the following configuration to connect:\\n\"\n \" interface remote_bitbang\\n\"\n \" remote_bitbang_host localhost\\n\"\n \" remote_bitbang_port %d\\n\",\n display_name, listen_port, listen_port);\n\n return (void *)ctx;\n}\n\nvoid jtagdpi_close(void *ctx_void) {\n struct jtagdpi_ctx *ctx = (struct jtagdpi_ctx *)ctx_void;\n if (!ctx) {\n return;\n }\n tcp_server_close(ctx->sock);\n free(ctx);\n}\n\n#ifdef JTAGDPI_DEBUG\nstatic void jtagdpi_dbg(struct jtagdpi_ctx *ctx) {\n\n uint8_t* curr = (uint8_t*)&ctx->curr;\n uint8_t* prev = (uint8_t*)&ctx->prev;\n\n if (ctx->init) {\n fprintf(stderr, \"tck tms tdi tdo trst srst\\n\");\n ctx->init = 0;\n }\n\n for (int i=0; i<6; ++i) {\n if (!prev[i] && curr[i]) {\n fprintf(stderr, \"\\\\ \");\n }\n if ( prev[i] && curr[i]) {\n fprintf(stderr, \" | \");\n }\n if ( prev[i] && !curr[i]) {\n fprintf(stderr, \"/ \");\n }\n if (!prev[i] && !curr[i]) {\n fprintf(stderr, \"| \");\n }\n }\n fprintf(stderr, \"\\n\");\n}\n#endif\n\nvoid jtagdpi_tick(void *ctx_void, svBit *tck, svBit *tms, svBit *tdi,\n svBit *trst_n, svBit *srst_n, const svBit tdo) {\n struct jtagdpi_ctx *ctx = (struct jtagdpi_ctx *)ctx_void;\n\n // Get TDO\n ctx->curr.tdo = tdo;\n\n // TODO: Evaluate moving this functionality into a separate thread\n if (ctx) {\n update_jtag_signals(ctx);\n }\n\n#ifdef JTAGDPI_DEBUG\n if (memcmp(&ctx->curr, &ctx->prev, sizeof(struct jtagdpi_signals))) {\n jtagdpi_dbg(ctx);\n memcpy(&ctx->prev, &ctx->curr, sizeof(struct jtagdpi_signals));\n }\n#endif\n\n *tdi = ctx->curr.tdi;\n *tms = ctx->curr.tms;\n *tck = ctx->curr.tck;\n *srst_n = ctx->curr.srst_n;\n *trst_n = ctx->curr.trst_n;\n}\n" }, { "path": "testbench/jtagdpi/jtagdpi.h", "content": "// Copyright lowRISC contributors.\n// Copyright 2024 Antmicro \n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n\n#ifndef OPENTITAN_HW_DV_DPI_JTAGDPI_JTAGDPI_H_\n#define OPENTITAN_HW_DV_DPI_JTAGDPI_JTAGDPI_H_\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct jtagdpi_ctx;\n\n/**\n * Constructor: Create and initialize jtagdpi context object\n *\n * Call from a initial block.\n *\n * @param display_name Name of the JTAG interface (for display purposes only)\n * @param listen_port Port to listen on\n * @return an initialized struct jtagdpi_ctx context object\n */\nvoid *jtagdpi_create(const char *display_name, int listen_port);\n\n/**\n * Destructor: Close all connections and free all resources\n *\n * Call from a finish block.\n *\n * @param ctx_void a struct jtagdpi_ctx context object\n */\nvoid jtagdpi_close(void *ctx_void);\n\n/**\n * Drive JTAG signals\n *\n * Call this function from the simulation at every clock tick to read/write\n * from/to the JTAG signals.\n *\n * @param ctx_void a struct jtagdpi_ctx context object\n * @param tck JTAG test clock signal\n * @param tms JTAG test mode select signal\n * @param tdi JTAG test data input signal\n * @param trst_n JTAG test reset signal (active low)\n * @param srst_n JTAG system reset signal (active low)\n * @param tdo JTAG test data out\n */\nvoid jtagdpi_tick(void *ctx_void, svBit *tck, svBit *tms, svBit *tdi,\n svBit *trst_n, svBit *srst_n, const svBit tdo);\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n#endif // OPENTITAN_HW_DV_DPI_JTAGDPI_JTAGDPI_H_\n" }, { "path": "testbench/jtagdpi/jtagdpi.sv", "content": "// Copyright lowRISC contributors.\n// Copyright 2024 Antmicro \n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n\nmodule jtagdpi #(\n parameter string Name = \"jtag0\", // name of the JTAG interface (display only)\n parameter int ListenPort = 44853 // TCP port to listen on\n)(\n input logic clk_i,\n input logic rst_ni,\n\n output logic jtag_tck,\n output logic jtag_tms,\n output logic jtag_tdi,\n input logic jtag_tdo,\n output logic jtag_trst_n,\n output logic jtag_srst_n\n);\n\n import \"DPI-C\"\n function chandle jtagdpi_create(input string name, input int listen_port);\n\n import \"DPI-C\"\n function void jtagdpi_tick(input chandle ctx, output bit tck, output bit tms,\n output bit tdi, output bit trst_n,\n output bit srst_n, input bit tdo);\n\n import \"DPI-C\"\n function void jtagdpi_close(input chandle ctx);\n\n chandle ctx;\n\n initial begin\n ctx = jtagdpi_create(Name, ListenPort);\n end\n\n final begin\n jtagdpi_close(ctx);\n ctx = null;\n end\n\n always_ff @(posedge clk_i, negedge rst_ni) begin\n jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,\n jtag_tdo);\n end\n\nendmodule\n" }, { "path": "testbench/link.ld", "content": "\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS\n{\n . = 0;\n .text : { *(.text*) }\n _end = .;\n . = 0x10000;\n .data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }\n}\n" }, { "path": "testbench/openocd_scripts/common.tcl", "content": "# SPDX-License-Identifier: Apache-2.0\n# Copyright 2024 Antmicro \n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\nproc compare {x y} {\n puts \"'$x' vs. '$y'\"\n\n if {[llength $y] != [llength $y]} {\n puts \"length mismatch!\"\n return -1\n }\n\n for {set i 0} {$i < [llength $x]} {incr i} {\n if {[lindex $x $i] != [lindex $y $i]} {\n puts \"item $i mismatch!\"\n return -1\n }\n }\n\n return 0\n}\n\nset STDOUT 0x300300cc\nset dmstatus_addr 0x11\n\n" }, { "path": "testbench/openocd_scripts/jtag_cg.tcl", "content": "# SPDX-License-Identifier: Apache-2.0\n# Copyright 2024 Antmicro \n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\n\nproc dmi_dump {} {\n # Dumps all DMI registers defined by the spec\n\n # DMI regs per \"RISC-V External Debug Support Version 0.13.2\"\n set dmi_regs {\n {0x04 \"data0\"}\n {0x0f \"data1\"}\n {0x10 \"dmcontrol\"}\n {0x11 \"dmstatus\"}\n {0x12 \"hartinfo\"}\n {0x13 \"haltsum1\"}\n {0x14 \"hawindowsel\"}\n {0x15 \"hawindow\"}\n {0x16 \"abstractcs\"}\n {0x17 \"command\"}\n {0x18 \"abstractauto\"}\n {0x19 \"configstrptr0\"}\n {0x1a \"configstrptr1\"}\n {0x1b \"configstrptr2\"}\n {0x1c \"configstrptr3\"}\n {0x1d \"nextdm\"}\n {0x20 \"progbuf0\"}\n {0x2f \"progbuf15\"}\n {0x30 \"authdata\"}\n {0x34 \"haltsum2\"}\n {0x35 \"haltsum3\"}\n {0x37 \"sbaddress3\"}\n {0x38 \"sbcs\"}\n {0x39 \"sbaddress0\"}\n {0x3a \"sbaddress1\"}\n {0x3b \"sbaddress2\"}\n {0x3c \"sbdata0\"}\n {0x3d \"sbdata1\"}\n {0x3e \"sbdata2\"}\n {0x3f \"sbdata3\"}\n {0x40 \"haltsum\"}\n }\n\n puts \"Dumping DMI registers\"\n foreach it $dmi_regs {\n set addr [lindex $it 0]\n set name [lindex $it 1]\n set val [riscv dmi_read $addr]\n\n puts \" $addr $name $val\"\n }\n}\n\nproc test_single_access { addr size data1 data2 } {\n # Tests memory access to a single address. Writes data1, then overwrites\n # it with data2, performs readback and compares the read value.\n\n set astr [format %08X $addr]\n puts \" $size-bit access to 0x$astr\"\n\n # Write 1\n if {[catch { write_memory $addr $size $data1 phys }]} {\n return -1\n }\n # Write 2\n if {[catch { write_memory $addr $size $data2 phys }]} {\n return -1\n }\n\n # Read\n if {[catch { set readback [read_memory $addr $size 1 phys] }]} {\n return -1\n }\n # Compare\n if {[compare $readback $data2] != 0} {\n return -1\n }\n\n return 0\n}\n\nproc test_memory_access { access_mode base_address widths uwidths } {\n # Test various types of memory access to the given address\n # \"widths\" is a list of aligned access sizes to execute and \"uwidths\"\n # is a list of unaligned accesses to perform.\n\n puts \"Testing memory access at $base_address using $access_mode mode\"\n riscv set_mem_access $access_mode\n\n set addr0 $base_address\n set addr1 [ expr {$base_address + 1} ]\n set addr2 [ expr {$base_address + 2} ]\n set addr3 [ expr {$base_address + 3} ]\n\n set data32_1 0xCAFEBACA\n set data32_2 0xDEADBEEF\n\n set data16_1 0xFACE\n set data16_2 0x5A5A\n\n set data8_1 0x55\n set data8_2 0xAA\n\n # Aligned accesses\n puts \" testing aligned access\"\n\n if {[lsearch -exact $widths 32] >= 0} {\n test_single_access $addr0 32 $data32_1 $data32_2\n }\n\n if {[lsearch -exact $widths 16] >= 0} {\n test_single_access $addr0 16 $data16_1 $data16_2\n test_single_access $addr2 16 $data16_2 $data16_1\n }\n\n if {[lsearch -exact $widths 8] >= 0} {\n test_single_access $addr0 8 $data8_1 $data8_2\n test_single_access $addr1 8 $data8_2 $data8_1\n test_single_access $addr2 8 $data8_1 $data8_2\n test_single_access $addr3 8 $data8_2 $data8_1\n }\n\n # Unaligned accesses\n puts \" testing unaligned access\"\n\n if {[lsearch -exact $uwidths 32] >= 0} {\n test_single_access $addr1 32 $data32_2 $data32_1\n test_single_access $addr2 32 $data32_1 $data32_2\n test_single_access $addr3 32 $data32_2 $data32_1\n }\n\n if {[lsearch -exact $uwidths 16] >= 0} {\n test_single_access $addr1 16 $data16_2 $data16_1\n test_single_access $addr3 16 $data16_2 $data16_1\n }\n}\n\n# Memory region base addesses for \"default\" VeeR configuration\nset ram_begin 0x00000000\nset dccm_begin 0xF0040000\nset iccm_begin 0xEE000000\nset pic_begin 0xF00C0000\n\ninit\n\nset script_dir [file dirname [info script]]\nsource [file join $script_dir common.tcl]\n\nputs \"Read Debug Module Status Register...\"\nset val [riscv dmi_read $dmstatus_addr]\nputs \" dmstatus: $val\"\nif {($val & 0x00000c00) == 0} {\n echo \"The hart is halted!\"\n shutdown error\n}\nputs \"\"\n\n# Dump all DMI registers\ndmi_dump\n\n# Access abstractauto (0x18) DMI register\nputs \"Exercising abstractauto (0x18) DMI register\"\nfor {set i 0} {$i < 10} {incr i} {\n riscv dmi_write 0x18 [expr {int(rand()*0xFFFFFFFF)}]\n riscv dmi_read 0x18\n riscv dmi_write 0x18 0\n}\n\n# Access sbdata1 (0x3D)\nfor {set i 0} {$i < 10} {incr i} {\n riscv dmi_write 0x3D [expr {int(rand()*0xFFFFFFFF)}]\n riscv dmi_read 0x3D\n riscv dmi_write 0x3D 0\n}\n\n# Test access in sysbus mode\nfor {set i 0} {$i < 5} {incr i} {\n test_memory_access \"sysbus\" $dccm_begin {32 16 8} {32 16}\n test_memory_access \"sysbus\" $ram_begin {32 16 8} {32 16}\n test_memory_access \"sysbus\" $iccm_begin {32} {32 16}\n test_memory_access \"sysbus\" $pic_begin {32 16 8} {32 16}\n}\n\n# Halt the core\nputs \"Halting the core\"\nhalt\nset val [riscv dmi_read $dmstatus_addr]\nputs \" dmstatus: $val\"\n\n# Manually attempt 64-bit sysbus transaction to trigger internal illegal size\n# error in the debug core\nputs \"Attempting 64-bit memory access in abstract mode\"\nfor {set i 0} {$i < 5} {incr i} {\n riscv dmi_write 0x38 0x000E0000\n riscv dmi_write 0x39 $ram_begin\n riscv dmi_write 0x3C [expr {int(rand()*0xFFFFFFFF)}]\n # Clear errors\n riscv dmi_write 0x38 0x00407000\n}\n\nputs \"Testing automatic bus read (sbreadonaddr=1)\"\nfor {set i 0} {$i < 5} {incr i} {\n riscv dmi_write 0x38 0x00140000\n for {set j 0} {$j < 5} {incr j} {\n riscv dmi_write 0x39 [expr {$ram_begin + 4 * $j}]\n set val [riscv dmi_read 0x3C]\n puts \" sbdata0: $val\"\n }\n}\n\nputs \"Testing automatic bus read and address increment (sbreadondata=1, sbautoincrement=1)\"\nfor {set i 0} {$i < 5} {incr i} {\n riscv dmi_write 0x38 0x00058000\n riscv dmi_write 0x39 $ram_begin\n for {set j 0} {$j < 5} {incr j} {\n set val [riscv dmi_read 0x3C]\n puts \" sbdata0: $val\"\n }\n}\n\n# Test access in abstract mode\nfor {set i 0} {$i < 5} {incr i} {\n test_memory_access \"abstract\" $dccm_begin {32 16 8} {32 16}\n test_memory_access \"abstract\" $ram_begin {32 16 8} {32 16}\n test_memory_access \"abstract\" $iccm_begin {32} {32 16}\n # No abstract access to PIC\n #test_memory_access \"abstract\" $pic_begin {32} {}\n}\n\n# Send signal to call $finish\nriscv set_mem_access sysbus\nwrite_memory 0xd0580000 8 0xFF phys\n\nshutdown\n" }, { "path": "testbench/openocd_scripts/sim-jtagdpi.cfg", "content": "# Copyright lowRISC contributors.\n# Copyright 2024 Antmicro \n# Licensed under the Apache License, Version 2.0, see LICENSE for details.\n# SPDX-License-Identifier: Apache-2.0\n\n# \"JTAG adapter\" for simulation, exposed to OpenOCD through a TCP socket\n# speaking the remote_bitbang protocol. The adapter is implemented as\n# SystemVerilog DPI module.\n\nadapter driver remote_bitbang\nremote_bitbang port 5000\nremote_bitbang host localhost\n" }, { "path": "testbench/openocd_scripts/veer-el2-rst.cfg", "content": "set _CHIPNAME riscv\n\njtag newtap $_CHIPNAME tap -irlen 5\nset _TARGETNAME $_CHIPNAME.tap\ntarget create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread\n\n# Mem access mode\nriscv set_mem_access sysbus\n\n# The following commands disable target examination and set explicitly the\n# core parameters read from CSRs. These required a modified version of\n# OpenOCD from https://github.com/antmicro/openocd/tree/riscv-nohalt\nriscv set_nohalt on\nriscv set_xlen 32\nriscv set_misa 0x40001104\n" }, { "path": "testbench/openocd_scripts/verilator-rst.cfg", "content": "source [find sim-jtagdpi.cfg]\nsource [find veer-el2-rst.cfg]\n" }, { "path": "testbench/tb_top.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n// Copyright (c) 2024 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n\n`ifndef VERILATOR\nmodule tb_top\n import tb_top_pkg::*;\n#(\n parameter int MAX_CYCLES = 2_000_000,\n `include \"el2_param.vh\"\n);\n\n logic i_cpu_halt_req, o_cpu_halt_ack, o_cpu_halt_status;\n logic i_cpu_run_req, o_cpu_run_ack;\n logic mpc_debug_halt_req, mpc_debug_halt_ack;\n logic mpc_debug_run_req, mpc_debug_run_ack;\n logic o_debug_mode_status;\n logic lsu_bus_clk_en;\n\n assign lsu_bus_clk_en = 1'b1;\n`else\nmodule tb_top\n import tb_top_pkg::*;\n#(\n parameter int MAX_CYCLES = 2_000_000,\n `include \"el2_param.vh\"\n) (\n input bit core_clk,\n input bit rst_l,\n input bit [31:0] mem_signature_begin,\n input bit [31:0] mem_signature_end,\n input bit [31:0] mem_mailbox,\n input bit i_cpu_halt_req, // Async halt req to CPU\n output bit o_cpu_halt_ack, // core response to halt\n output bit o_cpu_halt_status, // 1'b1 indicates core is halted\n input bit i_cpu_run_req, // Async restart req to CPU\n output bit o_cpu_run_ack, // Core response to run req\n input bit mpc_debug_halt_req,\n output bit mpc_debug_halt_ack,\n input bit mpc_debug_run_req,\n output bit mpc_debug_run_ack,\n output bit o_debug_mode_status,\n input bit lsu_bus_clk_en\n);\n`endif\n\n`ifdef RV_BUILD_AHB_LITE\n logic lmem_hsel;\n logic [31:0] lmem_haddr;\n logic [2:0] lmem_hburst;\n logic lmem_hmastlock;\n logic [3:0] lmem_hprot;\n logic [2:0] lmem_hsize;\n logic [1:0] lmem_htrans;\n logic lmem_hwrite;\n logic lmem_hreadyout;\n logic lmem_hreadyin;\n\n logic dma_hsel;\n logic [31:0] dma_haddr;\n logic [2:0] dma_hburst;\n logic dma_hmastlock;\n logic [3:0] dma_hprot;\n logic [2:0] dma_hsize;\n logic [1:0] dma_htrans;\n logic dma_hwrite;\n logic dma_hreadyout;\n logic dma_hreadyin;\n`endif // RV_BUILD_AHB_LITE\n\n`ifndef VERILATOR\n bit core_clk;\n bit [31:0] mem_signature_begin = 32'd0; // TODO:\n bit [31:0] mem_signature_end = 32'd0;\n bit [31:0] mem_mailbox = 32'hD0580000;\n logic rst_l;\n`endif\n logic porst_l;\n logic [pt.PIC_TOTAL_INT:1] extintsrc_req;\n logic nmi_int;\n logic timer_int;\n logic soft_int;\n\n logic [31:0] reset_vector;\n logic [31:0] nmi_vector;\n logic [31:1] jtag_id;\n\n logic [31:0] ic_haddr ;\n logic [2:0] ic_hburst ;\n logic ic_hmastlock ;\n logic [3:0] ic_hprot ;\n logic [2:0] ic_hsize ;\n logic [1:0] ic_htrans ;\n logic ic_hwrite ;\n logic [63:0] ic_hrdata ;\n logic ic_hready ;\n logic ic_hresp ;\n\n logic [31:0] lsu_haddr ;\n logic [2:0] lsu_hburst ;\n logic lsu_hmastlock ;\n logic [3:0] lsu_hprot ;\n logic [2:0] lsu_hsize ;\n logic [1:0] lsu_htrans ;\n logic lsu_hwrite ;\n logic [63:0] lsu_hrdata ;\n logic [63:0] lsu_hwdata ;\n logic lsu_hready ;\n logic lsu_hresp ;\n\n logic [31:0] mux_haddr ;\n logic [2:0] mux_hburst ;\n logic mux_hmastlock ;\n logic [3:0] mux_hprot ;\n logic [2:0] mux_hsize ;\n logic [1:0] mux_htrans ;\n logic mux_hwrite ;\n logic mux_hsel ;\n logic [63:0] mux_hrdata ;\n logic [63:0] mux_hwdata ;\n logic mux_hready ;\n logic mux_hresp ;\n logic mux_hreadyout ;\n\n logic [31:0] sb_haddr ;\n logic [2:0] sb_hburst ;\n logic sb_hmastlock ;\n logic [3:0] sb_hprot ;\n logic [2:0] sb_hsize ;\n logic [1:0] sb_htrans ;\n logic sb_hwrite ;\n\n logic [63:0] sb_hrdata ;\n logic [63:0] sb_hwdata ;\n logic sb_hready ;\n logic sb_hresp ;\n\n logic [31:0] trace_rv_i_insn_ip;\n logic [31:0] trace_rv_i_address_ip;\n logic trace_rv_i_valid_ip;\n logic trace_rv_i_exception_ip;\n logic [4:0] trace_rv_i_ecause_ip;\n logic trace_rv_i_interrupt_ip;\n logic [31:0] trace_rv_i_tval_ip;\n\n\n\n logic jtag_tdo;\n logic jtag_tck;\n logic jtag_tms;\n logic jtag_tdi;\n logic jtag_trst_n;\n\n logic mailbox_write;\n logic [63:0] mailbox_data;\n\n logic [63:0] lmem_hrdata ;\n logic [63:0] lmem_hwdata ;\n logic lmem_hready ;\n logic lmem_hresp ;\n\n logic [63:0] dma_hrdata ;\n logic [63:0] dma_hwdata ;\n logic dma_hready ;\n logic dma_hresp ;\n\n logic mpc_reset_run_req;\n logic debug_brkpt_status;\n\n int cycleCnt;\n logic mailbox_data_val;\n\n wire lmem_hready_out;\n wire dma_hready_out;\n int commit_count;\n\n logic [3:0] nmi_assert_int;\n\n logic wb_valid;\n logic [4:0] wb_dest;\n logic [31:0] wb_data;\n\n logic wb_csr_valid;\n logic [11:0] wb_csr_dest;\n logic [31:0] wb_csr_data;\n\n logic dmi_core_enable;\n\n always_comb dmi_core_enable = ~(o_cpu_halt_status);\n\n `ifdef RV_OPENOCD_TEST\n // SB and LSU AHB master mux\n ahb_lite_2to1_mux #(\n .AHB_LITE_ADDR_WIDTH (32),\n .AHB_LITE_DATA_WIDTH (64),\n .AHB_NO_OPT(1) //Prevent address and data phase overlap between initiators\n ) u_sb_lsu_ahb_mux (\n .hclk (core_clk),\n .hreset_n (rst_l),\n .force_bus_idle (),\n // Initiator 0\n .hsel_i_0 (1'b1 ),\n .haddr_i_0 (lsu_haddr ),\n .hwdata_i_0 (lsu_hwdata),\n .hwrite_i_0 (lsu_hwrite),\n .htrans_i_0 (lsu_htrans),\n .hsize_i_0 (lsu_hsize ),\n .hready_i_0 (lsu_hready),\n .hresp_o_0 (lsu_hresp ),\n .hready_o_0 (lsu_hready),\n .hrdata_o_0 (lsu_hrdata),\n\n // Initiator 1\n .hsel_i_1 (1'b1 ),\n .haddr_i_1 (sb_haddr ),\n .hwdata_i_1 (sb_hwdata ),\n .hwrite_i_1 (sb_hwrite ),\n .htrans_i_1 (sb_htrans ),\n .hsize_i_1 (sb_hsize ),\n .hready_i_1 (sb_hready ),\n .hresp_o_1 (sb_hresp ),\n .hready_o_1 (sb_hready ),\n .hrdata_o_1 (sb_hrdata ),\n\n // Responder\n .hsel_o (mux_hsel),\n .haddr_o (mux_haddr ),\n .hwdata_o (mux_hwdata),\n .hwrite_o (mux_hwrite),\n .htrans_o (mux_htrans),\n .hsize_o (mux_hsize ),\n .hready_o (mux_hready),\n .hresp_i (mux_hresp ),\n .hreadyout_i (mux_hreadyout),\n .hrdata_i (mux_hrdata)\n );\n `else\n assign mux_hsel = 1'b1;\n assign mux_haddr = lsu_haddr;\n assign mux_hwdata = lsu_hwdata;\n assign mux_hwrite = lsu_hwrite;\n assign mux_htrans = lsu_htrans;\n assign mux_hsize = lsu_hsize;\n\n assign lsu_hresp = mux_hresp;\n assign lsu_hrdata = mux_hrdata;\n assign lsu_hready = mux_hreadyout;\n `endif\n\n`ifdef RV_BUILD_AXI4\n //-------------------------- LSU AXI signals--------------------------\n // AXI Write Channels\n parameter int RV_MUX_BUS_TAG = (`RV_LSU_BUS_TAG > `RV_SB_BUS_TAG ? `RV_LSU_BUS_TAG : `RV_SB_BUS_TAG) + 1;\n wire lsu_axi_awvalid;\n wire lsu_axi_awready;\n wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid;\n wire [31:0] lsu_axi_awaddr;\n wire [3:0] lsu_axi_awregion;\n wire [7:0] lsu_axi_awlen;\n wire [2:0] lsu_axi_awsize;\n wire [1:0] lsu_axi_awburst;\n wire lsu_axi_awlock;\n wire [3:0] lsu_axi_awcache;\n wire [2:0] lsu_axi_awprot;\n wire [3:0] lsu_axi_awqos;\n\n wire lsu_axi_wvalid;\n wire lsu_axi_wready;\n wire [63:0] lsu_axi_wdata;\n wire [7:0] lsu_axi_wstrb;\n wire lsu_axi_wlast;\n\n wire lsu_axi_bvalid;\n wire lsu_axi_bready;\n wire [1:0] lsu_axi_bresp;\n wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid;\n\n // AXI Read Channels\n wire lsu_axi_arvalid;\n wire lsu_axi_arready;\n wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid;\n wire [31:0] lsu_axi_araddr;\n wire [3:0] lsu_axi_arregion;\n wire [7:0] lsu_axi_arlen;\n wire [2:0] lsu_axi_arsize;\n wire [1:0] lsu_axi_arburst;\n wire lsu_axi_arlock;\n wire [3:0] lsu_axi_arcache;\n wire [2:0] lsu_axi_arprot;\n wire [3:0] lsu_axi_arqos;\n\n wire lsu_axi_rvalid;\n wire lsu_axi_rready;\n wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid;\n wire [63:0] lsu_axi_rdata;\n wire [1:0] lsu_axi_rresp;\n wire lsu_axi_rlast;\n wire lsu_axi_awuser;\n wire lsu_axi_wuser;\n wire lsu_axi_buser;\n wire lsu_axi_aruser;\n wire lsu_axi_ruser;\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n wire ifu_axi_awvalid;\n wire ifu_axi_awready;\n wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid;\n wire [31:0] ifu_axi_awaddr;\n wire [3:0] ifu_axi_awregion;\n wire [7:0] ifu_axi_awlen;\n wire [2:0] ifu_axi_awsize;\n wire [1:0] ifu_axi_awburst;\n wire ifu_axi_awlock;\n wire [3:0] ifu_axi_awcache;\n wire [2:0] ifu_axi_awprot;\n wire [3:0] ifu_axi_awqos;\n\n wire ifu_axi_wvalid;\n wire ifu_axi_wready;\n wire [63:0] ifu_axi_wdata;\n wire [7:0] ifu_axi_wstrb;\n wire ifu_axi_wlast;\n\n wire ifu_axi_bvalid;\n wire ifu_axi_bready;\n wire [1:0] ifu_axi_bresp;\n wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid;\n\n // AXI Read Channels\n wire ifu_axi_arvalid;\n wire ifu_axi_arready;\n wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid;\n wire [31:0] ifu_axi_araddr;\n wire [3:0] ifu_axi_arregion;\n wire [7:0] ifu_axi_arlen;\n wire [2:0] ifu_axi_arsize;\n wire [1:0] ifu_axi_arburst;\n wire ifu_axi_arlock;\n wire [3:0] ifu_axi_arcache;\n wire [2:0] ifu_axi_arprot;\n wire [3:0] ifu_axi_arqos;\n\n wire ifu_axi_rvalid;\n wire ifu_axi_rready;\n wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid;\n wire [63:0] ifu_axi_rdata;\n wire [1:0] ifu_axi_rresp;\n wire ifu_axi_rlast;\n\n //-------------------------- SB AXI signals--------------------------\n // AXI Write Channels\n wire sb_axi_awvalid;\n wire sb_axi_awready;\n wire [`RV_SB_BUS_TAG-1:0] sb_axi_awid;\n wire [31:0] sb_axi_awaddr;\n wire [3:0] sb_axi_awregion;\n wire [7:0] sb_axi_awlen;\n wire [2:0] sb_axi_awsize;\n wire [1:0] sb_axi_awburst;\n wire sb_axi_awlock;\n wire [3:0] sb_axi_awcache;\n wire [2:0] sb_axi_awprot;\n wire [3:0] sb_axi_awqos;\n\n wire sb_axi_wvalid;\n wire sb_axi_wready;\n wire [63:0] sb_axi_wdata;\n wire [7:0] sb_axi_wstrb;\n wire sb_axi_wlast;\n\n wire sb_axi_bvalid;\n wire sb_axi_bready;\n wire [1:0] sb_axi_bresp;\n wire [`RV_SB_BUS_TAG-1:0] sb_axi_bid;\n\n // AXI Read Channels\n wire sb_axi_arvalid;\n wire sb_axi_arready;\n wire [`RV_SB_BUS_TAG-1:0] sb_axi_arid;\n wire [31:0] sb_axi_araddr;\n wire [3:0] sb_axi_arregion;\n wire [7:0] sb_axi_arlen;\n wire [2:0] sb_axi_arsize;\n wire [1:0] sb_axi_arburst;\n wire sb_axi_arlock;\n wire [3:0] sb_axi_arcache;\n wire [2:0] sb_axi_arprot;\n wire [3:0] sb_axi_arqos;\n\n wire sb_axi_rvalid;\n wire sb_axi_rready;\n wire [`RV_SB_BUS_TAG-1:0] sb_axi_rid;\n wire [63:0] sb_axi_rdata;\n wire [1:0] sb_axi_rresp;\n wire sb_axi_rlast;\n wire sb_axi_awuser;\n wire sb_axi_wuser;\n wire sb_axi_buser;\n wire sb_axi_aruser;\n wire sb_axi_ruser;\n\n //-------------------------- DMA AXI signals--------------------------\n // AXI Write Channels\n wire dma_axi_awvalid;\n wire dma_axi_awready;\n wire [`RV_DMA_BUS_TAG-1:0] dma_axi_awid;\n wire [31:0] dma_axi_awaddr;\n wire [2:0] dma_axi_awsize;\n wire [2:0] dma_axi_awprot;\n wire [7:0] dma_axi_awlen;\n wire [1:0] dma_axi_awburst;\n\n\n wire dma_axi_wvalid;\n wire dma_axi_wready;\n wire [63:0] dma_axi_wdata;\n wire [7:0] dma_axi_wstrb;\n wire dma_axi_wlast;\n\n wire dma_axi_bvalid;\n wire dma_axi_bready;\n wire [1:0] dma_axi_bresp;\n wire [`RV_DMA_BUS_TAG-1:0] dma_axi_bid;\n\n // AXI Read Channels\n wire dma_axi_arvalid;\n wire dma_axi_arready;\n wire [`RV_DMA_BUS_TAG-1:0] dma_axi_arid;\n wire [31:0] dma_axi_araddr;\n wire [2:0] dma_axi_arsize;\n wire [2:0] dma_axi_arprot;\n wire [7:0] dma_axi_arlen;\n wire [1:0] dma_axi_arburst;\n\n wire dma_axi_rvalid;\n wire dma_axi_rready;\n wire [`RV_DMA_BUS_TAG-1:0] dma_axi_rid;\n wire [63:0] dma_axi_rdata;\n wire [1:0] dma_axi_rresp;\n wire dma_axi_rlast;\n\n wire lmem_axi_arvalid;\n wire lmem_axi_arready;\n\n wire lmem_axi_rvalid;\n wire [RV_MUX_BUS_TAG-1:0] lmem_axi_rid;\n wire [1:0] lmem_axi_rresp;\n wire [63:0] lmem_axi_rdata;\n wire lmem_axi_rlast;\n wire lmem_axi_rready;\n\n wire lmem_axi_awvalid;\n wire lmem_axi_awready;\n\n wire lmem_axi_wvalid;\n wire lmem_axi_wready;\n\n wire [1:0] lmem_axi_bresp;\n wire lmem_axi_bvalid;\n wire [RV_MUX_BUS_TAG-1:0] lmem_axi_bid;\n wire lmem_axi_bready;\n\n wire mux_axi_awvalid;\n wire mux_axi_awready;\n wire [RV_MUX_BUS_TAG-1:0] mux_axi_awid;\n wire [31:0] mux_axi_awaddr;\n wire [3:0] mux_axi_awregion;\n wire [7:0] mux_axi_awlen;\n wire [2:0] mux_axi_awsize;\n wire [1:0] mux_axi_awburst;\n wire mux_axi_awlock;\n wire [3:0] mux_axi_awcache;\n wire [2:0] mux_axi_awprot;\n wire [3:0] mux_axi_awqos;\n\n wire mux_axi_wvalid;\n wire mux_axi_wready;\n wire [63:0] mux_axi_wdata;\n wire [7:0] mux_axi_wstrb;\n wire mux_axi_wlast;\n\n wire mux_axi_bvalid;\n wire mux_axi_bready;\n wire [1:0] mux_axi_bresp;\n wire [RV_MUX_BUS_TAG-1:0] mux_axi_bid;\n\n // AXI Read Channels\n wire mux_axi_arvalid;\n wire mux_axi_arready;\n wire [RV_MUX_BUS_TAG-1:0] mux_axi_arid;\n wire [31:0] mux_axi_araddr;\n wire [3:0] mux_axi_arregion;\n wire [7:0] mux_axi_arlen;\n wire [2:0] mux_axi_arsize;\n wire [1:0] mux_axi_arburst;\n wire mux_axi_arlock;\n wire [3:0] mux_axi_arcache;\n wire [2:0] mux_axi_arprot;\n wire [3:0] mux_axi_arqos;\n\n wire mux_axi_rvalid;\n wire mux_axi_rready;\n wire [RV_MUX_BUS_TAG-1:0] mux_axi_rid;\n wire [63:0] mux_axi_rdata;\n wire [1:0] mux_axi_rresp;\n wire mux_axi_rlast;\n wire mux_axi_awuser;\n wire mux_axi_wuser;\n wire mux_axi_buser;\n wire mux_axi_aruser;\n wire mux_axi_ruser;\n\n`ifdef RV_OPENOCD_TEST\n axi_crossbar_wrap_2x1 #(\n .ADDR_WIDTH (32),\n .DATA_WIDTH (64),\n .S_ID_WIDTH(RV_MUX_BUS_TAG - 1),\n .M00_ADDR_WIDTH(32)\n ) u_axi_crossbar (\n .clk(core_clk),\n .rst(!rst_l),\n\n // LSU\n .s00_axi_arvalid(lsu_axi_arvalid),\n .s00_axi_arready(lsu_axi_arready),\n .s00_axi_araddr(lsu_axi_araddr),\n .s00_axi_arid(lsu_axi_arid),\n .s00_axi_arlen(lsu_axi_arlen),\n .s00_axi_arburst(lsu_axi_arburst),\n .s00_axi_arsize(lsu_axi_arsize),\n\n .s00_axi_rvalid(lsu_axi_rvalid),\n .s00_axi_rready(lsu_axi_rready),\n .s00_axi_rdata(lsu_axi_rdata),\n .s00_axi_rresp(lsu_axi_rresp),\n .s00_axi_rid(lsu_axi_rid),\n .s00_axi_rlast(lsu_axi_rlast),\n\n .s00_axi_awvalid(lsu_axi_awvalid),\n .s00_axi_awready(lsu_axi_awready),\n .s00_axi_awaddr(lsu_axi_awaddr),\n .s00_axi_awid(lsu_axi_awid),\n .s00_axi_awlen(lsu_axi_awlen),\n .s00_axi_awburst(lsu_axi_awburst),\n .s00_axi_awlock(lsu_axi_awlock),\n .s00_axi_awcache(lsu_axi_awcache),\n .s00_axi_awprot(lsu_axi_awprot),\n .s00_axi_awqos(lsu_axi_awqos),\n .s00_axi_awuser(lsu_axi_awuser),\n .s00_axi_wlast(lsu_axi_wlast),\n .s00_axi_wuser(lsu_axi_wuser),\n .s00_axi_buser(lsu_axi_buser),\n .s00_axi_arlock(lsu_axi_arlock),\n .s00_axi_arcache(lsu_axi_arcache),\n .s00_axi_arprot(lsu_axi_arprot),\n .s00_axi_arqos(lsu_axi_arqos),\n .s00_axi_aruser(lsu_axi_aruser),\n .s00_axi_ruser(lsu_axi_ruser),\n .s00_axi_awsize(lsu_axi_awsize),\n\n .s00_axi_wdata(lsu_axi_wdata),\n .s00_axi_wstrb(lsu_axi_wstrb),\n .s00_axi_wvalid(lsu_axi_wvalid),\n .s00_axi_wready(lsu_axi_wready),\n\n .s00_axi_bvalid(lsu_axi_bvalid),\n .s00_axi_bready(lsu_axi_bready),\n .s00_axi_bresp(lsu_axi_bresp),\n .s00_axi_bid(lsu_axi_bid),\n\n // SB\n .s01_axi_arvalid(sb_axi_arvalid),\n .s01_axi_arready(sb_axi_arready),\n .s01_axi_araddr(sb_axi_araddr),\n .s01_axi_arid(sb_axi_arid),\n .s01_axi_arlen(sb_axi_arlen),\n .s01_axi_arburst(sb_axi_arburst),\n .s01_axi_arsize(sb_axi_arsize),\n\n .s01_axi_rvalid(sb_axi_rvalid),\n .s01_axi_rready(sb_axi_rready),\n .s01_axi_rdata(sb_axi_rdata),\n .s01_axi_rresp(sb_axi_rresp),\n .s01_axi_rid(sb_axi_rid),\n .s01_axi_rlast(sb_axi_rlast),\n\n .s01_axi_awvalid(sb_axi_awvalid),\n .s01_axi_awready(sb_axi_awready),\n .s01_axi_awaddr(sb_axi_awaddr),\n .s01_axi_awid(sb_axi_awid),\n .s01_axi_awlen(sb_axi_awlen),\n .s01_axi_awburst(sb_axi_awburst),\n .s01_axi_awlock(sb_axi_awlock),\n .s01_axi_awcache(sb_axi_awcache),\n .s01_axi_awprot(sb_axi_awprot),\n .s01_axi_awqos(sb_axi_awqos),\n .s01_axi_awuser(sb_axi_awuser),\n .s01_axi_wlast(sb_axi_wlast),\n .s01_axi_wuser(sb_axi_wuser),\n .s01_axi_buser(sb_axi_buser),\n .s01_axi_arlock(sb_axi_arlock),\n .s01_axi_arcache(sb_axi_arcache),\n .s01_axi_arprot(sb_axi_arprot),\n .s01_axi_arqos(sb_axi_arqos),\n .s01_axi_aruser(sb_axi_aruser),\n .s01_axi_ruser(sb_axi_ruser),\n .s01_axi_awsize(sb_axi_awsize),\n\n .s01_axi_wdata(sb_axi_wdata),\n .s01_axi_wstrb(sb_axi_wstrb),\n .s01_axi_wvalid(sb_axi_wvalid),\n .s01_axi_wready(sb_axi_wready),\n\n .s01_axi_bvalid(sb_axi_bvalid),\n .s01_axi_bready(sb_axi_bready),\n .s01_axi_bresp(sb_axi_bresp),\n .s01_axi_bid(sb_axi_bid),\n\n // Output\n .m00_axi_arvalid(mux_axi_arvalid),\n .m00_axi_arready(mux_axi_arready),\n .m00_axi_araddr(mux_axi_araddr),\n .m00_axi_arid(mux_axi_arid),\n .m00_axi_arlen(mux_axi_arlen),\n .m00_axi_arburst(mux_axi_arburst),\n .m00_axi_arsize(mux_axi_arsize),\n\n .m00_axi_rvalid(mux_axi_rvalid),\n .m00_axi_rready(mux_axi_rready),\n .m00_axi_rdata(mux_axi_rdata),\n .m00_axi_rresp(mux_axi_rresp),\n .m00_axi_rid(mux_axi_rid),\n .m00_axi_rlast(mux_axi_rlast),\n\n .m00_axi_awvalid(mux_axi_awvalid),\n .m00_axi_awready(mux_axi_awready),\n .m00_axi_awaddr(mux_axi_awaddr),\n .m00_axi_awid(mux_axi_awid),\n .m00_axi_awlen(mux_axi_awlen),\n .m00_axi_awburst(mux_axi_awburst),\n .m00_axi_awlock(mux_axi_awlock),\n .m00_axi_awcache(mux_axi_awcache),\n .m00_axi_awprot(mux_axi_awprot),\n .m00_axi_awqos(mux_axi_awqos),\n .m00_axi_awuser(mux_axi_awuser),\n .m00_axi_wlast(mux_axi_wlast),\n .m00_axi_wuser(mux_axi_wuser),\n .m00_axi_buser(mux_axi_buser),\n .m00_axi_arlock(mux_axi_arlock),\n .m00_axi_arcache(mux_axi_arcache),\n .m00_axi_arprot(mux_axi_arprot),\n .m00_axi_arqos(mux_axi_arqos),\n .m00_axi_aruser(mux_axi_aruser),\n .m00_axi_ruser(mux_axi_ruser),\n .m00_axi_awsize(mux_axi_awsize),\n\n .m00_axi_wdata(mux_axi_wdata),\n .m00_axi_wstrb(mux_axi_wstrb),\n .m00_axi_wvalid(mux_axi_wvalid),\n .m00_axi_wready(mux_axi_wready),\n\n .m00_axi_bvalid(mux_axi_bvalid),\n .m00_axi_bready(mux_axi_bready),\n .m00_axi_bresp(mux_axi_bresp),\n .m00_axi_bid(mux_axi_bid),\n .m00_axi_awregion(mux_axi_awregion),\n .m00_axi_arregion(mux_axi_arregion)\n );\n`else\n assign mux_axi_arvalid = lsu_axi_arvalid;\n assign lsu_axi_arready = mux_axi_arready;\n assign mux_axi_araddr = lsu_axi_araddr;\n assign mux_axi_arid = lsu_axi_arid;\n assign mux_axi_arlen = lsu_axi_arlen;\n assign mux_axi_arburst = lsu_axi_arburst;\n assign mux_axi_arsize = lsu_axi_arsize;\n assign lsu_axi_rvalid = mux_axi_rvalid;\n assign mux_axi_rready = lsu_axi_rready;\n assign lsu_axi_rdata = mux_axi_rdata;\n assign lsu_axi_rresp = mux_axi_rresp;\n assign lsu_axi_rid = mux_axi_rid;\n assign lsu_axi_rlast = mux_axi_rlast;\n assign mux_axi_awvalid = lsu_axi_awvalid;\n assign lsu_axi_awready = mux_axi_awready;\n assign mux_axi_awaddr = lsu_axi_awaddr;\n assign mux_axi_awid = lsu_axi_awid;\n assign mux_axi_awlen = lsu_axi_awlen;\n assign mux_axi_awburst = lsu_axi_awburst;\n assign mux_axi_awlock = lsu_axi_awlock;\n assign mux_axi_awcache = lsu_axi_awcache;\n assign mux_axi_awprot = lsu_axi_awprot;\n assign mux_axi_awqos = lsu_axi_awqos;\n assign mux_axi_awuser = lsu_axi_awuser;\n assign mux_axi_wlast = lsu_axi_wlast;\n assign mux_axi_wuser = lsu_axi_wuser;\n assign lsu_axi_buser = mux_axi_buser;\n assign mux_axi_arlock = lsu_axi_arlock;\n assign mux_axi_arcache = lsu_axi_arcache;\n assign mux_axi_arprot = lsu_axi_arprot;\n assign mux_axi_arqos = lsu_axi_arqos;\n assign mux_axi_aruser = lsu_axi_aruser;\n assign lsu_axi_ruser = mux_axi_ruser;\n assign mux_axi_awsize = lsu_axi_awsize;\n assign mux_axi_wdata = lsu_axi_wdata;\n assign mux_axi_wstrb = lsu_axi_wstrb;\n assign mux_axi_wvalid = lsu_axi_wvalid;\n assign lsu_axi_wready = mux_axi_wready;\n assign lsu_axi_bvalid = mux_axi_bvalid;\n assign mux_axi_bready = lsu_axi_bready;\n assign lsu_axi_bresp = mux_axi_bresp;\n assign lsu_axi_bid = mux_axi_bid;\n assign mux_axi_awregion = lsu_axi_awregion;\n assign mux_axi_arregion = lsu_axi_arregion;\n`endif\n\n`endif\n string abi_reg[32]; // ABI register names\n el2_mem_if el2_mem_export ();\n\n logic [pt.ICCM_NUM_BANKS-1:0][ 38:0] iccm_bank_wr_fdata;\n logic [pt.ICCM_NUM_BANKS-1:0][ 38:0] iccm_bank_fdout;\n logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_fdata_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-1:0] dccm_bank_fdout;\n\n tb_top_pkg::veer_sram_error_injection_mode_t error_injection_mode;\n\n`define DEC rvtop_wrapper.rvtop.veer.dec\n\n`ifdef RV_BUILD_AHB_LITE\n always_ff @(posedge core_clk)\n mailbox_write <= lmem.HSEL && lmem.HREADY && lmem.HADDR == mem_mailbox && rst_l;\n assign mailbox_data = lmem.HWDATA;\n`endif\n\n`ifdef RV_BUILD_AXI4\n assign mailbox_write = lmem.awvalid && lmem.awaddr == mem_mailbox && rst_l;\n assign mailbox_data = lmem.wdata;\n`endif\n\n assign mailbox_data_val = mailbox_data[7:0] > 8'h5 && mailbox_data[7:0] < 8'h7f;\n\n integer fd, tp, el;\n logic next_dbus_error;\n logic next_ibus_error;\n\n always @(negedge core_clk or negedge rst_l) begin\n if (rst_l == 0) begin\n error_injection_mode <= '0;\n next_dbus_error <= '0;\n next_ibus_error <= '0;\n end else begin\n nmi_assert_int <= nmi_assert_int >> 1;\n soft_int <= 0;\n timer_int <= 0;\n extintsrc_req[1] <= 0;\n cycleCnt <= cycleCnt+1;\n // timeout monitor\n if(cycleCnt == MAX_CYCLES) begin\n $display (\"Hit max cycle count (%0d) .. stopping\", cycleCnt);\n $display(\"TEST_FAILED\");\n `ifdef TB_SILENT_FAIL\n $finish;\n `else\n $fatal;\n `endif // TB_SILENT_FAIL\n end\n // console Monitor\n if( mailbox_data_val & mailbox_write) begin\n $fwrite(fd,\"%c\", mailbox_data[7:0]);\n $write(\"%c\", mailbox_data[7:0]);\n end\n // Interrupt signals control\n // data[7:0] == 0x80 - clear ext irq line index given by data[15:8]\n // data[7:0] == 0x81 - set ext irq line index given by data[15:8]\n // data[7:0] == 0x82 - clean NMI, timer and soft irq lines to bits data[8:10]\n // data[7:0] == 0x83 - set NMI, timer and soft irq lines to bits data[8:10]\n // data[7:0] == 0x86 - Trigger external interrupt\n // data[7:0] == 0x87 - (AXI4) Trigger data bus error on the next load/store\n // data[7:0] == 0x88 - (AXI4) Trigger instruction bus error on the next load/store\n // data[7:0] == 0x90 - clear all interrupt request signals\n if(mailbox_write && (mailbox_data[7:0] >= 8'h80 && mailbox_data[7:0] < 8'h87)) begin\n if (mailbox_data[7:0] == 8'h80) begin\n if (mailbox_data[15:8] > 0 && mailbox_data[15:8] < pt.PIC_TOTAL_INT && nmi_assert_int == 4'b0000)\n extintsrc_req[mailbox_data[15:8]] <= 1'b0;\n nmi_assert_int <= 4'b1111;\n end\n if (mailbox_data[7:0] == 8'h81) begin\n if (mailbox_data[15:8] > 0 && mailbox_data[15:8] < pt.PIC_TOTAL_INT)\n extintsrc_req[mailbox_data[15:8]] <= 1'b1;\n nmi_vector[31:1] <= {mailbox_data[31:8], 7'h00};\n end\n if (mailbox_data[7:0] == 8'h82 && nmi_assert_int == 4'b0000) begin\n nmi_assert_int <= {4{nmi_int & ~mailbox_data[8]}};\n timer_int <= timer_int & ~mailbox_data[9];\n soft_int <= soft_int & ~mailbox_data[10];\n end\n if (mailbox_data[7:0] == 8'h83 && nmi_assert_int == 4'b0000) begin\n nmi_assert_int <= {4{nmi_int | mailbox_data[8]}};\n timer_int <= timer_int | mailbox_data[9];\n soft_int <= soft_int | mailbox_data[10];\n end\n if (mailbox_data[7:0] == 8'h84) begin\n soft_int <= 1;\n end\n if (mailbox_data[7:0] == 8'h85) begin\n timer_int <= 1;\n end\n if (mailbox_data[7:0] == 8'h86) begin\n extintsrc_req[1] <= 1;\n end\n end\n if(mailbox_write && (mailbox_data[7:0] == 8'h90)) begin\n extintsrc_req <= {pt.PIC_TOTAL_INT-1{1'b0}};\n nmi_assert_int <= 4'b0000;\n timer_int <= 1'b0;\n soft_int <= 1'b0;\n end\n // end\n // ECC error injection\n if(mailbox_write && (mailbox_data[7:0] == 8'he0)) begin\n $display(\"Injecting single bit ICCM error\");\n error_injection_mode.iccm_single_bit_error <= 1'b1;\n end\n else if(mailbox_write && (mailbox_data[7:0] == 8'he1)) begin\n $display(\"Injecting double bit ICCM error\");\n error_injection_mode.iccm_double_bit_error <= 1'b1;\n end\n else if(mailbox_write && (mailbox_data[7:0] == 8'he2)) begin\n $display(\"Injecting single bit DCCM error\");\n error_injection_mode.dccm_single_bit_error <= 1'b1;\n end\n else if(mailbox_write && (mailbox_data[7:0] == 8'he3)) begin\n $display(\"Injecting double bit DCCM error\");\n error_injection_mode.dccm_double_bit_error <= 1'b1;\n end\n else if(mailbox_write && (mailbox_data[7:0] == 8'he4)) begin\n $display(\"Disable ECC error injection\");\n error_injection_mode <= '0;\n end\n // Memory signature dump\n if(mailbox_write && (mailbox_data[7:0] == 8'hFF || mailbox_data[7:0] == 8'h01)) begin\n if (mem_signature_begin < mem_signature_end) begin\n dump_signature();\n end\n end\n // End Of test monitor\n if(mailbox_write && mailbox_data[7:0] == 8'hff) begin\n $display(\"TEST_PASSED\");\n $display(\"\\nFinished : minstret = %0d, mcycle = %0d\", `DEC.tlu.minstretl[31:0],`DEC.tlu.mcyclel[31:0]);\n $display(\"See \\\"exec.log\\\" for execution trace with register updates..\\n\");\n // OpenOCD test breaks if simulation closes the TCP connection first.\n // This delay allows OpenOCD to close the connection before the #finish.\n #15000;\n $finish;\n end\n else if(mailbox_write && mailbox_data[7:0] == 8'h1) begin\n $display(\"TEST_FAILED\");\n `ifdef TB_SILENT_FAIL\n $finish;\n `else\n $fatal;\n `endif // TB_SILENT_FAIL\n end\n end\n end\n\n `ifdef RV_BUILD_AXI4\n // this needs to be a separate block due to sensitivity to other signals\n always @(negedge core_clk or lsu_axi_bvalid or lsu_axi_rvalid or ifu_axi_rvalid or ifu_axi_rid) begin\n if (mailbox_write && mailbox_data[7:0] == 8'h87)\n // wait for current transaction that to complete to not trigger error on it\n @(negedge lsu_axi_bvalid) next_dbus_error <= 1;\n if (mailbox_write && mailbox_data[7:0] == 8'h88)\n @(negedge ifu_axi_rvalid or ifu_axi_rid) next_ibus_error <= 1;\n // turn off forcing dbus error after a transaction\n if (next_dbus_error)\n @(negedge lsu_axi_bvalid or negedge lsu_axi_rvalid) next_dbus_error <= 0;\n if (next_ibus_error)\n @(negedge ifu_axi_rvalid or ifu_axi_rid) next_ibus_error <= 0;\n end\n\n logic [1:0] lsu_axi_rresp_override;\n logic [1:0] lsu_axi_bresp_override;\n logic [1:0] ifu_axi_rresp_override;\n always_comb begin\n lsu_axi_rresp_override = lsu_axi_rresp;\n lsu_axi_bresp_override = lsu_axi_bresp;\n ifu_axi_rresp_override = ifu_axi_rresp;\n if (next_dbus_error) begin\n // force slave bus error\n if (lsu_axi_rvalid)\n lsu_axi_rresp_override = 2'b10;\n if (lsu_axi_bvalid)\n lsu_axi_bresp_override = 2'b10;\n end\n if (next_ibus_error) begin\n if (ifu_axi_rvalid)\n ifu_axi_rresp_override = 2'b10;\n end\n end\n `endif\n\n // nmi_int must be asserted for at least two clock cycles and then deasserted for\n // at least two clock cycles - see RISC-V VeeR EL2 Programmer's Reference Manual section 2.16\n assign nmi_int = |{nmi_assert_int[3:2]};\n\n // trace monitor\n always @(posedge core_clk) begin\n wb_valid <= `DEC.dec_i0_wen_r;\n wb_dest <= `DEC.dec_i0_waddr_r;\n wb_data <= `DEC.dec_i0_wdata_r;\n wb_csr_valid <= `DEC.dec_csr_wen_r;\n wb_csr_dest <= `DEC.dec_csr_wraddr_r;\n wb_csr_data <= `DEC.dec_csr_wrdata_r;\n if (trace_rv_i_valid_ip) begin\n $fwrite(tp,\"%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\\n\", trace_rv_i_valid_ip, 0, trace_rv_i_address_ip,\n 0, trace_rv_i_insn_ip,trace_rv_i_exception_ip,trace_rv_i_ecause_ip,\n trace_rv_i_tval_ip,trace_rv_i_interrupt_ip);\n // Basic trace - no exception register updates\n // #1 0 ee000000 b0201073 c 0b02 00000000\n commit_count++;\n $fwrite (el, \"%10d : %8s 0 %h %h%13s %14s ; %s\\n\", cycleCnt, $sformatf(\"#%0d\",commit_count),\n trace_rv_i_address_ip, trace_rv_i_insn_ip,\n (wb_dest !=0 && wb_valid)? $sformatf(\"%s=%h\", abi_reg[wb_dest], wb_data) : \" \",\n (wb_csr_valid)? $sformatf(\"c%h=%h\", wb_csr_dest, wb_csr_data) : \" \",\n dasm(trace_rv_i_insn_ip, trace_rv_i_address_ip, wb_dest & {5{wb_valid}}, wb_data)\n );\n end\n if(`DEC.dec_nonblock_load_wen) begin\n $fwrite (el, \"%10d : %32s=%h ; nbL\\n\", cycleCnt, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);\n tb_top.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data;\n end\n if(`DEC.exu_div_wren) begin\n $fwrite (el, \"%10d : %32s=%h ; nbD\\n\", cycleCnt, abi_reg[`DEC.div_waddr_wb], `DEC.exu_div_result);\n tb_top.gpr[0][`DEC.div_waddr_wb] = `DEC.exu_div_result;\n end\n end\n\n\n initial begin\n abi_reg[0] = \"zero\";\n abi_reg[1] = \"ra\";\n abi_reg[2] = \"sp\";\n abi_reg[3] = \"gp\";\n abi_reg[4] = \"tp\";\n abi_reg[5] = \"t0\";\n abi_reg[6] = \"t1\";\n abi_reg[7] = \"t2\";\n abi_reg[8] = \"s0\";\n abi_reg[9] = \"s1\";\n abi_reg[10] = \"a0\";\n abi_reg[11] = \"a1\";\n abi_reg[12] = \"a2\";\n abi_reg[13] = \"a3\";\n abi_reg[14] = \"a4\";\n abi_reg[15] = \"a5\";\n abi_reg[16] = \"a6\";\n abi_reg[17] = \"a7\";\n abi_reg[18] = \"s2\";\n abi_reg[19] = \"s3\";\n abi_reg[20] = \"s4\";\n abi_reg[21] = \"s5\";\n abi_reg[22] = \"s6\";\n abi_reg[23] = \"s7\";\n abi_reg[24] = \"s8\";\n abi_reg[25] = \"s9\";\n abi_reg[26] = \"s10\";\n abi_reg[27] = \"s11\";\n abi_reg[28] = \"t3\";\n abi_reg[29] = \"t4\";\n abi_reg[30] = \"t5\";\n abi_reg[31] = \"t6\";\n\n extintsrc_req = {pt.PIC_TOTAL_INT-1{1'b0}};\n timer_int = 0;\n soft_int = 0;\n\n // tie offs\n jtag_id[31:28] = 4'b1;\n jtag_id[27:12] = '0;\n jtag_id[11:1] = 11'h45;\n reset_vector = `RV_RESET_VEC;\n nmi_assert_int = 0;\n nmi_vector = 32'hee000000;\n\n $readmemh(\"program.hex\", lmem.mem);\n $readmemh(\"program.hex\", imem.mem);\n tp = $fopen(\"trace_port.csv\",\"w\");\n el = $fopen(\"exec.log\",\"w\");\n $fwrite (el, \"// Cycle : #inst 0 pc opcode reg=value csr=value ; mnemonic\\n\");\n fd = $fopen(\"console.log\",\"w\");\n commit_count = 0;\n preload_dccm();\n preload_iccm();\n\n`ifndef VERILATOR\n $dumpfile(\"dump.vcd\");\n $dumpvars(0, tb_top);\n rst_l = 1'b1;\n rst_l = #5 1'b0;\n rst_l = #25 1'b1;\n // halt and start the core\n i_cpu_halt_req = 1'b0;\n i_cpu_run_req = 1'b0;\n mpc_debug_halt_req = 1'b0;\n mpc_debug_run_req = 1'b0;\n\n $display(\"halting CPU and waiting for ack\");\n i_cpu_halt_req = #5 1'b1;\n wait(o_cpu_halt_ack == 1);\n $display(\"waiting for halt\");\n i_cpu_halt_req = 1'b0;\n wait(o_cpu_halt_status == 1'b1);\n $display(\"requesting start and waiting for ack\");\n i_cpu_run_req = 1'b1;\n wait(o_cpu_run_ack == 1'b1);\n $display(\"waiting for run\");\n i_cpu_run_req = 1'b0;\n wait(o_cpu_halt_status == 1'b0);\n $display(\"done\");\n\n $display(\"requesting mpc halt and wating for ack\");\n mpc_debug_halt_req = 1'b1;\n wait(mpc_debug_halt_ack == 1'b1);\n $display(\"waiting for debug halt\");\n mpc_debug_halt_req = 1'b0;\n wait(o_debug_mode_status == 1'b1);\n $display(\"requesting start and waiting for ack\");\n mpc_debug_run_req = 1'b1;\n wait(mpc_debug_run_ack == 1'b1);\n $display(\"waiting for cpu to start\");\n mpc_debug_run_req = 1'b0;\n wait(o_debug_mode_status == 1'b0);\n $display(\"done\");\n`endif\n end\n`ifndef VERILATOR\n initial begin\n forever core_clk = #5 ~core_clk;\n end\n initial begin\n porst_l = 1'b1;\n porst_l = #1 1'b0;\n porst_l = #10 1'b1;\n end\n`else\n assign porst_l = cycleCnt > 2;\n`endif\n //=========================================================================-\n // RTL instance\n //=========================================================================-\nveer_wrapper rvtop_wrapper (\n .rst_l ( rst_l ),\n .dbg_rst_l ( porst_l ),\n .clk ( core_clk ),\n .rst_vec ( reset_vector[31:1]),\n .nmi_int ( nmi_int ),\n .nmi_vec ( nmi_vector[31:1]),\n .jtag_id ( jtag_id[31:1]),\n\n`ifdef RV_BUILD_AHB_LITE\n .haddr ( ic_haddr ),\n .hburst ( ic_hburst ),\n .hmastlock ( ic_hmastlock ),\n .hprot ( ic_hprot ),\n .hsize ( ic_hsize ),\n .htrans ( ic_htrans ),\n .hwrite ( ic_hwrite ),\n\n .hrdata ( ic_hrdata[63:0]),\n .hready ( ic_hready ),\n .hresp ( ic_hresp ),\n\n //---------------------------------------------------------------\n // Debug AHB Master\n //---------------------------------------------------------------\n .sb_haddr ( sb_haddr ),\n .sb_hburst ( sb_hburst ),\n .sb_hmastlock ( sb_hmastlock ),\n .sb_hprot ( sb_hprot ),\n .sb_hsize ( sb_hsize ),\n .sb_htrans ( sb_htrans ),\n .sb_hwrite ( sb_hwrite ),\n .sb_hwdata ( sb_hwdata ),\n\n .sb_hrdata ( sb_hrdata ),\n .sb_hready ( sb_hready ),\n .sb_hresp ( sb_hresp ),\n\n //---------------------------------------------------------------\n // LSU AHB Master\n //---------------------------------------------------------------\n .lsu_haddr ( lsu_haddr ),\n .lsu_hburst ( lsu_hburst ),\n .lsu_hmastlock ( lsu_hmastlock ),\n .lsu_hprot ( lsu_hprot ),\n .lsu_hsize ( lsu_hsize ),\n .lsu_htrans ( lsu_htrans ),\n .lsu_hwrite ( lsu_hwrite ),\n .lsu_hwdata ( lsu_hwdata ),\n\n .lsu_hrdata ( lsu_hrdata[63:0]),\n .lsu_hready ( lsu_hready ),\n .lsu_hresp ( lsu_hresp ),\n\n //---------------------------------------------------------------\n // DMA Slave\n //---------------------------------------------------------------\n .dma_haddr (dma_haddr),\n .dma_hburst (dma_hburst),\n .dma_hmastlock (dma_hmastlock),\n .dma_hprot (dma_hprot),\n .dma_hsize (dma_hsize),\n .dma_htrans (dma_htrans),\n .dma_hwrite (dma_hwrite),\n .dma_hwdata (dma_hwdata),\n\n .dma_hrdata ( dma_hrdata ),\n .dma_hresp ( dma_hresp ),\n .dma_hsel ( dma_hsel ),\n .dma_hreadyin ( dma_hready_out ),\n .dma_hreadyout ( dma_hready_out ),\n`endif // RV_BUILD_AHB_LITE\n`ifdef RV_BUILD_AXI4\n //-------------------------- LSU AXI signals--------------------------\n // AXI Write Channels\n .lsu_axi_awvalid (lsu_axi_awvalid),\n .lsu_axi_awready (lsu_axi_awready),\n .lsu_axi_awid (lsu_axi_awid),\n .lsu_axi_awaddr (lsu_axi_awaddr),\n .lsu_axi_awregion (lsu_axi_awregion),\n .lsu_axi_awlen (lsu_axi_awlen),\n .lsu_axi_awsize (lsu_axi_awsize),\n .lsu_axi_awburst (lsu_axi_awburst),\n .lsu_axi_awlock (lsu_axi_awlock),\n .lsu_axi_awcache (lsu_axi_awcache),\n .lsu_axi_awprot (lsu_axi_awprot),\n .lsu_axi_awqos (lsu_axi_awqos),\n\n .lsu_axi_wvalid (lsu_axi_wvalid),\n .lsu_axi_wready (lsu_axi_wready),\n .lsu_axi_wdata (lsu_axi_wdata),\n .lsu_axi_wstrb (lsu_axi_wstrb),\n .lsu_axi_wlast (lsu_axi_wlast),\n\n .lsu_axi_bvalid (lsu_axi_bvalid),\n .lsu_axi_bready (lsu_axi_bready),\n .lsu_axi_bresp (lsu_axi_bresp_override),\n .lsu_axi_bid (lsu_axi_bid),\n\n\n .lsu_axi_arvalid (lsu_axi_arvalid),\n .lsu_axi_arready (lsu_axi_arready),\n .lsu_axi_arid (lsu_axi_arid),\n .lsu_axi_araddr (lsu_axi_araddr),\n .lsu_axi_arregion (lsu_axi_arregion),\n .lsu_axi_arlen (lsu_axi_arlen),\n .lsu_axi_arsize (lsu_axi_arsize),\n .lsu_axi_arburst (lsu_axi_arburst),\n .lsu_axi_arlock (lsu_axi_arlock),\n .lsu_axi_arcache (lsu_axi_arcache),\n .lsu_axi_arprot (lsu_axi_arprot),\n .lsu_axi_arqos (lsu_axi_arqos),\n\n .lsu_axi_rvalid (lsu_axi_rvalid),\n .lsu_axi_rready (lsu_axi_rready),\n .lsu_axi_rid (lsu_axi_rid),\n .lsu_axi_rdata (lsu_axi_rdata),\n .lsu_axi_rresp (lsu_axi_rresp_override),\n .lsu_axi_rlast (lsu_axi_rlast),\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n .ifu_axi_awvalid (ifu_axi_awvalid),\n .ifu_axi_awready (ifu_axi_awready),\n .ifu_axi_awid (ifu_axi_awid),\n .ifu_axi_awaddr (ifu_axi_awaddr),\n .ifu_axi_awregion (ifu_axi_awregion),\n .ifu_axi_awlen (ifu_axi_awlen),\n .ifu_axi_awsize (ifu_axi_awsize),\n .ifu_axi_awburst (ifu_axi_awburst),\n .ifu_axi_awlock (ifu_axi_awlock),\n .ifu_axi_awcache (ifu_axi_awcache),\n .ifu_axi_awprot (ifu_axi_awprot),\n .ifu_axi_awqos (ifu_axi_awqos),\n\n .ifu_axi_wvalid (ifu_axi_wvalid),\n .ifu_axi_wready (ifu_axi_wready),\n .ifu_axi_wdata (ifu_axi_wdata),\n .ifu_axi_wstrb (ifu_axi_wstrb),\n .ifu_axi_wlast (ifu_axi_wlast),\n\n .ifu_axi_bvalid (ifu_axi_bvalid),\n .ifu_axi_bready (ifu_axi_bready),\n .ifu_axi_bresp (ifu_axi_bresp),\n .ifu_axi_bid (ifu_axi_bid),\n\n .ifu_axi_arvalid (ifu_axi_arvalid),\n .ifu_axi_arready (ifu_axi_arready),\n .ifu_axi_arid (ifu_axi_arid),\n .ifu_axi_araddr (ifu_axi_araddr),\n .ifu_axi_arregion (ifu_axi_arregion),\n .ifu_axi_arlen (ifu_axi_arlen),\n .ifu_axi_arsize (ifu_axi_arsize),\n .ifu_axi_arburst (ifu_axi_arburst),\n .ifu_axi_arlock (ifu_axi_arlock),\n .ifu_axi_arcache (ifu_axi_arcache),\n .ifu_axi_arprot (ifu_axi_arprot),\n .ifu_axi_arqos (ifu_axi_arqos),\n\n .ifu_axi_rvalid (ifu_axi_rvalid),\n .ifu_axi_rready (ifu_axi_rready),\n .ifu_axi_rid (ifu_axi_rid),\n .ifu_axi_rdata (ifu_axi_rdata),\n .ifu_axi_rresp (ifu_axi_rresp_override),\n .ifu_axi_rlast (ifu_axi_rlast),\n\n //-------------------------- SB AXI signals--------------------------\n // AXI Write Channels\n .sb_axi_awvalid (sb_axi_awvalid),\n .sb_axi_awready (sb_axi_awready),\n .sb_axi_awid (sb_axi_awid),\n .sb_axi_awaddr (sb_axi_awaddr),\n .sb_axi_awregion (sb_axi_awregion),\n .sb_axi_awlen (sb_axi_awlen),\n .sb_axi_awsize (sb_axi_awsize),\n .sb_axi_awburst (sb_axi_awburst),\n .sb_axi_awlock (sb_axi_awlock),\n .sb_axi_awcache (sb_axi_awcache),\n .sb_axi_awprot (sb_axi_awprot),\n .sb_axi_awqos (sb_axi_awqos),\n\n .sb_axi_wvalid (sb_axi_wvalid),\n .sb_axi_wready (sb_axi_wready),\n .sb_axi_wdata (sb_axi_wdata),\n .sb_axi_wstrb (sb_axi_wstrb),\n .sb_axi_wlast (sb_axi_wlast),\n\n .sb_axi_bvalid (sb_axi_bvalid),\n .sb_axi_bready (sb_axi_bready),\n .sb_axi_bresp (sb_axi_bresp),\n .sb_axi_bid (sb_axi_bid),\n\n\n .sb_axi_arvalid (sb_axi_arvalid),\n .sb_axi_arready (sb_axi_arready),\n .sb_axi_arid (sb_axi_arid),\n .sb_axi_araddr (sb_axi_araddr),\n .sb_axi_arregion (sb_axi_arregion),\n .sb_axi_arlen (sb_axi_arlen),\n .sb_axi_arsize (sb_axi_arsize),\n .sb_axi_arburst (sb_axi_arburst),\n .sb_axi_arlock (sb_axi_arlock),\n .sb_axi_arcache (sb_axi_arcache),\n .sb_axi_arprot (sb_axi_arprot),\n .sb_axi_arqos (sb_axi_arqos),\n\n .sb_axi_rvalid (sb_axi_rvalid),\n .sb_axi_rready (sb_axi_rready),\n .sb_axi_rid (sb_axi_rid),\n .sb_axi_rdata (sb_axi_rdata),\n .sb_axi_rresp (sb_axi_rresp),\n .sb_axi_rlast (sb_axi_rlast),\n\n //-------------------------- DMA AXI signals--------------------------\n // AXI Write Channels\n .dma_axi_awvalid (dma_axi_awvalid),\n .dma_axi_awready (dma_axi_awready),\n .dma_axi_awid ('0),\n .dma_axi_awaddr (lsu_axi_awaddr),\n .dma_axi_awsize (lsu_axi_awsize),\n .dma_axi_awprot (lsu_axi_awprot),\n .dma_axi_awlen (lsu_axi_awlen),\n .dma_axi_awburst (lsu_axi_awburst),\n\n\n .dma_axi_wvalid (dma_axi_wvalid),\n .dma_axi_wready (dma_axi_wready),\n .dma_axi_wdata (lsu_axi_wdata),\n .dma_axi_wstrb (lsu_axi_wstrb),\n .dma_axi_wlast (lsu_axi_wlast),\n\n .dma_axi_bvalid (dma_axi_bvalid),\n .dma_axi_bready (dma_axi_bready),\n .dma_axi_bresp (dma_axi_bresp),\n .dma_axi_bid (),\n\n\n .dma_axi_arvalid (dma_axi_arvalid),\n .dma_axi_arready (dma_axi_arready),\n .dma_axi_arid ('0),\n .dma_axi_araddr (lsu_axi_araddr),\n .dma_axi_arsize (lsu_axi_arsize),\n .dma_axi_arprot (lsu_axi_arprot),\n .dma_axi_arlen (lsu_axi_arlen),\n .dma_axi_arburst (lsu_axi_arburst),\n\n .dma_axi_rvalid (dma_axi_rvalid),\n .dma_axi_rready (dma_axi_rready),\n .dma_axi_rid (),\n .dma_axi_rdata (dma_axi_rdata),\n .dma_axi_rresp (dma_axi_rresp),\n .dma_axi_rlast (dma_axi_rlast),\n`endif\n .timer_int ( timer_int ),\n .extintsrc_req ( extintsrc_req ),\n\n .lsu_bus_clk_en (lsu_bus_clk_en),// Clock ratio b/w cpu core clk & AHB master interface\n .ifu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface\n .dbg_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB Debug master interface\n .dma_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB slave interface\n\n .trace_rv_i_insn_ip (trace_rv_i_insn_ip),\n .trace_rv_i_address_ip (trace_rv_i_address_ip),\n .trace_rv_i_valid_ip (trace_rv_i_valid_ip),\n .trace_rv_i_exception_ip(trace_rv_i_exception_ip),\n .trace_rv_i_ecause_ip (trace_rv_i_ecause_ip),\n .trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),\n .trace_rv_i_tval_ip (trace_rv_i_tval_ip),\n\n .jtag_tck (jtag_tck),\n .jtag_tms (jtag_tms),\n .jtag_tdi (jtag_tdi),\n .jtag_trst_n (jtag_trst_n),\n .jtag_tdo (jtag_tdo),\n .jtag_tdoEn (),\n\n .mpc_debug_halt_ack ( mpc_debug_halt_ack),\n .mpc_debug_halt_req ( mpc_debug_halt_req),\n .mpc_debug_run_ack ( mpc_debug_run_ack),\n .mpc_debug_run_req ( mpc_debug_run_req),\n .mpc_reset_run_req ( 1'b1), // Start running after reset\n .debug_brkpt_status (debug_brkpt_status),\n\n .i_cpu_halt_req ( i_cpu_halt_req ), // Async halt req to CPU\n .o_cpu_halt_ack ( o_cpu_halt_ack ), // core response to halt\n .o_cpu_halt_status ( o_cpu_halt_status ), // 1'b1 indicates core is halted\n .i_cpu_run_req ( i_cpu_run_req ), // Async restart req to CPU\n .o_debug_mode_status ( o_debug_mode_status),\n .o_cpu_run_ack ( o_cpu_run_ack ), // Core response to run req\n\n .dec_tlu_perfcnt0 (),\n .dec_tlu_perfcnt1 (),\n .dec_tlu_perfcnt2 (),\n .dec_tlu_perfcnt3 (),\n\n .mem_clk (el2_mem_export.clk),\n\n .iccm_clken (el2_mem_export.iccm_clken),\n .iccm_wren_bank (el2_mem_export.iccm_wren_bank),\n .iccm_addr_bank (el2_mem_export.iccm_addr_bank),\n .iccm_bank_wr_data (el2_mem_export.iccm_bank_wr_data),\n .iccm_bank_wr_ecc (el2_mem_export.iccm_bank_wr_ecc),\n .iccm_bank_dout (el2_mem_export.iccm_bank_dout),\n .iccm_bank_ecc (el2_mem_export.iccm_bank_ecc),\n\n .dccm_clken (el2_mem_export.dccm_clken),\n .dccm_wren_bank (el2_mem_export.dccm_wren_bank),\n .dccm_addr_bank (el2_mem_export.dccm_addr_bank),\n .dccm_wr_data_bank (el2_mem_export.dccm_wr_data_bank),\n .dccm_wr_ecc_bank (el2_mem_export.dccm_wr_ecc_bank),\n .dccm_bank_dout (el2_mem_export.dccm_bank_dout),\n .dccm_bank_ecc (el2_mem_export.dccm_bank_ecc),\n\n .ic_tag_clken_final (el2_mem_export.ic_tag_clken_final),\n .ic_tag_wren_q (el2_mem_export.ic_tag_wren_q),\n .ic_tag_wren_biten_vec (el2_mem_export.ic_tag_wren_biten_vec),\n .ic_tag_wr_data (el2_mem_export.ic_tag_wr_data),\n .ic_rw_addr_q (el2_mem_export.ic_rw_addr_q),\n .ic_tag_data_raw_packed_pre (el2_mem_export.ic_tag_data_raw_packed_pre),\n .ic_tag_data_raw_pre (el2_mem_export.ic_tag_data_raw_pre),\n .ic_b_sb_wren (el2_mem_export.ic_b_sb_wren),\n .ic_b_sb_bit_en_vec (el2_mem_export.ic_b_sb_bit_en_vec),\n .ic_sb_wr_data (el2_mem_export.ic_sb_wr_data),\n .ic_rw_addr_bank_q (el2_mem_export.ic_rw_addr_bank_q),\n .wb_packeddout_pre (el2_mem_export.wb_packeddout_pre),\n .ic_bank_way_clken_final (el2_mem_export.ic_bank_way_clken_final),\n .ic_bank_way_clken_final_up (el2_mem_export.ic_bank_way_clken_final_up),\n .wb_dout_pre_up (el2_mem_export.wb_dout_pre_up),\n\n .iccm_ecc_single_error (),\n .iccm_ecc_double_error (),\n .dccm_ecc_single_error (),\n .dccm_ecc_double_error (),\n\n`ifdef RV_LOCKSTEP_ENABLE\n .disable_corruption_detection_i ('0),\n .lockstep_err_injection_en_i ('0),\n .corruption_detected_o (),\n`endif\n\n .soft_int (soft_int),\n .core_id ('0),\n .scan_mode ( 1'b0 ), // To enable scan mode\n .mbist_mode ( 1'b0 ), // to enable mbist\n\n .dmi_core_enable (dmi_core_enable),\n .dmi_uncore_enable (),\n .dmi_uncore_en (),\n .dmi_uncore_wr_en (),\n .dmi_uncore_addr (),\n .dmi_uncore_wdata (),\n .dmi_uncore_rdata (),\n .dmi_active ()\n\n);\n\n\n //=========================================================================-\n // AHB I$ instance\n //=========================================================================-\n`ifdef RV_BUILD_AHB_LITE\n\nahb_sif imem (\n // Inputs\n .HWDATA(64'h0),\n .HCLK(core_clk),\n .HSEL(1'b1),\n .HPROT(ic_hprot),\n .HWRITE(ic_hwrite),\n .HTRANS(ic_htrans),\n .HSIZE(ic_hsize),\n .HREADY(ic_hready),\n .HRESETn(rst_l),\n .HADDR(ic_haddr),\n .HBURST(ic_hburst),\n\n // Outputs\n .HREADYOUT(ic_hready),\n .HRESP(ic_hresp),\n .HRDATA(ic_hrdata[63:0])\n);\n\nahb_sif #(\n .MAX_DELAY(1),\n .MIN_DELAY(1)\n)lmem(\n // Inputs\n .HCLK(core_clk),\n .HRESETn(rst_l),\n\n .HSEL(lmem_hsel),\n .HADDR(lmem_haddr),\n .HBURST(lmem_hburst),\n .HPROT(lmem_hprot),\n .HWRITE(lmem_hwrite),\n .HWDATA(lmem_hwdata),\n .HTRANS(lmem_htrans),\n .HSIZE(lmem_hsize),\n .HREADY(lmem_hready_out),\n\n // Outputs\n .HREADYOUT(lmem_hready_out),\n .HRESP(lmem_hresp),\n .HRDATA(lmem_hrdata)\n);\n\nahb_lsu_dma_bridge #(.pt(pt)) bridge (\n .clk(core_clk),\n .reset_l(rst_l),\n\n .m_ahb_haddr(mux_haddr[31:0]),\n .m_ahb_hburst(mux_hburst),\n .m_ahb_hmastlock(mux_hmastlock),\n .m_ahb_hprot(mux_hprot[3:0]),\n .m_ahb_hsize(mux_hsize[2:0]),\n .m_ahb_htrans(mux_htrans[1:0]),\n .m_ahb_hwrite(mux_hwrite),\n .m_ahb_hwdata(mux_hwdata[63:0]),\n .m_ahb_hsel(mux_hsel),\n .m_ahb_hreadyin(mux_hready),\n .m_ahb_hrdata(mux_hrdata[63:0]),\n .m_ahb_hreadyout(mux_hreadyout),\n .m_ahb_hresp(mux_hresp),\n\n .s0_ahb_hsel(lmem_hsel),\n .s0_ahb_haddr(lmem_haddr),\n .s0_ahb_hburst(lmem_hburst),\n .s0_ahb_hmastlock(lmem_hmastlock),\n .s0_ahb_hprot(lmem_hprot),\n .s0_ahb_hsize(lmem_hsize),\n .s0_ahb_htrans(lmem_htrans),\n .s0_ahb_hwrite(lmem_hwrite),\n .s0_ahb_hwdata(lmem_hwdata),\n .s0_ahb_hrdata(lmem_hrdata),\n .s0_ahb_hready(lmem_hready_out),\n .s0_ahb_hresp(lmem_hresp),\n\n .s1_ahb_hsel(dma_hsel),\n .s1_ahb_haddr(dma_haddr),\n .s1_ahb_hburst(dma_hburst),\n .s1_ahb_hmastlock(dma_hmastlock),\n .s1_ahb_hprot(dma_hprot),\n .s1_ahb_hsize(dma_hsize),\n .s1_ahb_htrans(dma_htrans),\n .s1_ahb_hwrite(dma_hwrite),\n .s1_ahb_hwdata(dma_hwdata),\n .s1_ahb_hrdata(dma_hrdata),\n .s1_ahb_hready(dma_hready_out),\n .s1_ahb_hresp(dma_hresp)\n);\n`endif // RV_BUILD_AHB_LITE\n\n`ifdef RV_BUILD_AXI4\naxi_slv #(.TAGW(`RV_IFU_BUS_TAG)) imem(\n .aclk(core_clk),\n .rst_l(rst_l),\n .arvalid(ifu_axi_arvalid),\n .arready(ifu_axi_arready),\n .araddr(ifu_axi_araddr),\n .arid(ifu_axi_arid),\n .arlen(ifu_axi_arlen),\n .arburst(ifu_axi_arburst),\n .arsize(ifu_axi_arsize),\n\n .rvalid(ifu_axi_rvalid),\n .rready(ifu_axi_rready),\n .rdata(ifu_axi_rdata),\n .rresp(ifu_axi_rresp),\n .rid(ifu_axi_rid),\n .rlast(ifu_axi_rlast),\n\n .awvalid(1'b0),\n .awready(),\n .awaddr('0),\n .awid('0),\n .awlen('0),\n .awburst('0),\n .awsize('0),\n\n .wdata('0),\n .wstrb('0),\n .wvalid(1'b0),\n .wready(),\n\n .bvalid(),\n .bready(1'b0),\n .bresp(),\n .bid()\n);\n\ndefparam lmem.TAGW = RV_MUX_BUS_TAG;\n\n//axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem(\naxi_slv lmem(\n .aclk(core_clk),\n .rst_l(rst_l),\n .arvalid(lmem_axi_arvalid),\n .arready(lmem_axi_arready),\n .araddr(mux_axi_araddr),\n .arid(mux_axi_arid),\n .arlen(mux_axi_arlen),\n .arburst(mux_axi_arburst),\n .arsize(mux_axi_arsize),\n\n .rvalid(lmem_axi_rvalid),\n .rready(lmem_axi_rready),\n .rdata(lmem_axi_rdata),\n .rresp(lmem_axi_rresp),\n .rid(lmem_axi_rid),\n .rlast(lmem_axi_rlast),\n\n .awvalid(lmem_axi_awvalid),\n .awready(lmem_axi_awready),\n .awaddr(mux_axi_awaddr),\n .awid(mux_axi_awid),\n .awlen(mux_axi_awlen),\n .awburst(mux_axi_awburst),\n .awsize(mux_axi_awsize),\n\n .wdata(mux_axi_wdata),\n .wstrb(mux_axi_wstrb),\n .wvalid(lmem_axi_wvalid),\n .wready(lmem_axi_wready),\n\n .bvalid(lmem_axi_bvalid),\n .bready(lmem_axi_bready),\n .bresp(lmem_axi_bresp),\n .bid(lmem_axi_bid)\n);\n\naxi_lsu_dma_bridge # (RV_MUX_BUS_TAG, RV_MUX_BUS_TAG) bridge(\n .clk(core_clk),\n .reset_l(rst_l),\n\n .m_arvalid(mux_axi_arvalid),\n .m_arid(mux_axi_arid),\n .m_araddr(mux_axi_araddr),\n .m_arready(mux_axi_arready),\n\n .m_rvalid(mux_axi_rvalid),\n .m_rready(mux_axi_rready),\n .m_rdata(mux_axi_rdata),\n .m_rid(mux_axi_rid),\n .m_rresp(mux_axi_rresp),\n .m_rlast(mux_axi_rlast),\n\n .m_awvalid(mux_axi_awvalid),\n .m_awid(mux_axi_awid),\n .m_awaddr(mux_axi_awaddr),\n .m_awready(mux_axi_awready),\n\n .m_wvalid(mux_axi_wvalid),\n .m_wready(mux_axi_wready),\n\n .m_bresp(mux_axi_bresp),\n .m_bvalid(mux_axi_bvalid),\n .m_bid(mux_axi_bid),\n .m_bready(mux_axi_bready),\n\n .s0_arvalid(lmem_axi_arvalid),\n .s0_arready(lmem_axi_arready),\n\n .s0_rvalid(lmem_axi_rvalid),\n .s0_rid(lmem_axi_rid),\n .s0_rresp(lmem_axi_rresp),\n .s0_rdata(lmem_axi_rdata),\n .s0_rlast(lmem_axi_rlast),\n .s0_rready(lmem_axi_rready),\n\n .s0_awvalid(lmem_axi_awvalid),\n .s0_awready(lmem_axi_awready),\n\n .s0_wvalid(lmem_axi_wvalid),\n .s0_wready(lmem_axi_wready),\n\n .s0_bresp(lmem_axi_bresp),\n .s0_bvalid(lmem_axi_bvalid),\n .s0_bid(lmem_axi_bid),\n .s0_bready(lmem_axi_bready),\n\n\n .s1_arvalid(dma_axi_arvalid),\n .s1_arready(dma_axi_arready),\n\n .s1_rvalid(dma_axi_rvalid),\n .s1_rresp(dma_axi_rresp),\n .s1_rdata(dma_axi_rdata),\n .s1_rlast(dma_axi_rlast),\n .s1_rready(dma_axi_rready),\n\n .s1_awvalid(dma_axi_awvalid),\n .s1_awready(dma_axi_awready),\n\n .s1_wvalid(dma_axi_wvalid),\n .s1_wready(dma_axi_wready),\n\n .s1_bresp(dma_axi_bresp),\n .s1_bvalid(dma_axi_bvalid),\n .s1_bready(dma_axi_bready)\n);\n\n\n`endif\n\ntask preload_iccm;\nbit[31:0] data;\nbit[31:0] addr, eaddr, saddr;\n\n/*\naddresses:\n 0xfffffff0 - ICCM start address to load\n 0xfffffff4 - ICCM end address to load\n*/\n`ifndef VERILATOR\ninit_iccm();\n`endif\naddr = 'hffff_fff0;\nsaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};\nif ( (saddr < `RV_ICCM_SADR) || (saddr > `RV_ICCM_EADR)) return;\n`ifndef RV_ICCM_ENABLE\n $display(\"********************************************************\");\n $display(\"ICCM preload: there is no ICCM in VeeR, terminating !!!\");\n $display(\"********************************************************\");\n $finish;\n`endif\naddr += 4;\neaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};\n$display(\"ICCM pre-load from %h to %h\", saddr, eaddr);\n\nfor(addr= saddr; addr <= eaddr; addr+=4) begin\n data = {imem.mem[addr+3],imem.mem[addr+2],imem.mem[addr+1],imem.mem[addr]};\n slam_iccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data});\nend\n\nendtask\n\n\ntask preload_dccm;\nbit[31:0] data;\nbit[31:0] addr, saddr, eaddr;\n\n/*\naddresses:\n 0xffff_fff8 - DCCM start address to load\n 0xffff_fffc - DCCM end address to load\n*/\n\naddr = 'hffff_fff8;\nsaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};\nif (saddr < `RV_DCCM_SADR || saddr > `RV_DCCM_EADR) return;\n`ifndef RV_DCCM_ENABLE\n $display(\"********************************************************\");\n $display(\"DCCM preload: there is no DCCM in VeeR, terminating !!!\");\n $display(\"********************************************************\");\n $finish;\n`endif\naddr += 4;\neaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};\n$display(\"DCCM pre-load from %h to %h\", saddr, eaddr);\n\nfor(addr=saddr; addr <= eaddr; addr+=4) begin\n data = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};\n slam_dccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data});\nend\n\nendtask\n\n\n\n`define DRAM(bk) Gen_dccm_enable.dccm_loop[bk].dccm.dccm_bank.ram_core\n`define IRAM(bk) Gen_iccm_enable.iccm_loop[bk].iccm.iccm_bank.ram_core\n\n\ntask slam_dccm_ram(input [31:0] addr, input[38:0] data);\nint bank, indx;\nbank = get_dccm_bank(addr, indx);\n`ifdef RV_DCCM_ENABLE\ncase(bank)\n0: `DRAM(0)[indx] = data;\n1: `DRAM(1)[indx] = data;\n`ifdef RV_DCCM_NUM_BANKS_4\n2: `DRAM(2)[indx] = data;\n3: `DRAM(3)[indx] = data;\n`endif\n`ifdef RV_DCCM_NUM_BANKS_8\n2: `DRAM(2)[indx] = data;\n3: `DRAM(3)[indx] = data;\n4: `DRAM(4)[indx] = data;\n5: `DRAM(5)[indx] = data;\n6: `DRAM(6)[indx] = data;\n7: `DRAM(7)[indx] = data;\n`endif\nendcase\n`endif\n//$display(\"Writing bank %0d indx=%0d A=%h, D=%h\",bank, indx, addr, data);\nendtask\n\n\ntask slam_iccm_ram( input[31:0] addr, input[38:0] data);\nint bank, idx;\n\nbank = get_iccm_bank(addr, idx);\n`ifdef RV_ICCM_ENABLE\ncase(bank) // {\n 0: `IRAM(0)[idx] = data;\n 1: `IRAM(1)[idx] = data;\n `ifdef RV_ICCM_NUM_BANKS_4\n 2: `IRAM(2)[idx] = data;\n 3: `IRAM(3)[idx] = data;\n `endif\n `ifdef RV_ICCM_NUM_BANKS_8\n 2: `IRAM(2)[idx] = data;\n 3: `IRAM(3)[idx] = data;\n 4: `IRAM(4)[idx] = data;\n 5: `IRAM(5)[idx] = data;\n 6: `IRAM(6)[idx] = data;\n 7: `IRAM(7)[idx] = data;\n `endif\n\n `ifdef RV_ICCM_NUM_BANKS_16\n 2: `IRAM(2)[idx] = data;\n 3: `IRAM(3)[idx] = data;\n 4: `IRAM(4)[idx] = data;\n 5: `IRAM(5)[idx] = data;\n 6: `IRAM(6)[idx] = data;\n 7: `IRAM(7)[idx] = data;\n 8: `IRAM(8)[idx] = data;\n 9: `IRAM(9)[idx] = data;\n 10: `IRAM(10)[idx] = data;\n 11: `IRAM(11)[idx] = data;\n 12: `IRAM(12)[idx] = data;\n 13: `IRAM(13)[idx] = data;\n 14: `IRAM(14)[idx] = data;\n 15: `IRAM(15)[idx] = data;\n `endif\nendcase // }\n`endif\nendtask\n\ntask init_iccm;\n`ifdef RV_ICCM_ENABLE\n `IRAM(0) = '{default:39'h0};\n `IRAM(1) = '{default:39'h0};\n`ifdef RV_ICCM_NUM_BANKS_4\n `IRAM(2) = '{default:39'h0};\n `IRAM(3) = '{default:39'h0};\n`endif\n`ifdef RV_ICCM_NUM_BANKS_8\n `IRAM(4) = '{default:39'h0};\n `IRAM(5) = '{default:39'h0};\n `IRAM(6) = '{default:39'h0};\n `IRAM(7) = '{default:39'h0};\n`endif\n\n`ifdef RV_ICCM_NUM_BANKS_16\n `IRAM(4) = '{default:39'h0};\n `IRAM(5) = '{default:39'h0};\n `IRAM(6) = '{default:39'h0};\n `IRAM(7) = '{default:39'h0};\n `IRAM(8) = '{default:39'h0};\n `IRAM(9) = '{default:39'h0};\n `IRAM(10) = '{default:39'h0};\n `IRAM(11) = '{default:39'h0};\n `IRAM(12) = '{default:39'h0};\n `IRAM(13) = '{default:39'h0};\n `IRAM(14) = '{default:39'h0};\n `IRAM(15) = '{default:39'h0};\n `endif\n`endif\nendtask\n\n\nfunction[6:0] riscv_ecc32(input[31:0] data);\nreg[6:0] synd;\nsynd[0] = ^(data & 32'h56aa_ad5b);\nsynd[1] = ^(data & 32'h9b33_366d);\nsynd[2] = ^(data & 32'he3c3_c78e);\nsynd[3] = ^(data & 32'h03fc_07f0);\nsynd[4] = ^(data & 32'h03ff_f800);\nsynd[5] = ^(data & 32'hfc00_0000);\nsynd[6] = ^{data, synd[5:0]};\nreturn synd;\nendfunction\n\nfunction int get_dccm_bank(input[31:0] addr, output int bank_idx);\n`ifdef RV_DCCM_NUM_BANKS_2\n bank_idx = int'(addr[`RV_DCCM_BITS-1:3]);\n return int'( addr[2]);\n`elsif RV_DCCM_NUM_BANKS_4\n bank_idx = int'(addr[`RV_DCCM_BITS-1:4]);\n return int'(addr[3:2]);\n`elsif RV_DCCM_NUM_BANKS_8\n bank_idx = int'(addr[`RV_DCCM_BITS-1:5]);\n return int'( addr[4:2]);\n`endif\nendfunction\n\nfunction int get_iccm_bank(input[31:0] addr, output int bank_idx);\n`ifdef RV_DCCM_NUM_BANKS_2\n bank_idx = int'(addr[`RV_DCCM_BITS-1:3]);\n return int'( addr[2]);\n`elsif RV_ICCM_NUM_BANKS_4\n bank_idx = int'(addr[`RV_ICCM_BITS-1:4]);\n return int'(addr[3:2]);\n`elsif RV_ICCM_NUM_BANKS_8\n bank_idx = int'(addr[`RV_ICCM_BITS-1:5]);\n return int'( addr[4:2]);\n`elsif RV_ICCM_NUM_BANKS_16\n bank_idx = int'(addr[`RV_ICCM_BITS-1:6]);\n return int'( addr[5:2]);\n`endif\nendfunction\n\ntask dump_signature ();\n integer fp, i;\n\n $display(\"Dumping memory signature (0x%08X - 0x%08X)...\",\n mem_signature_begin,\n mem_signature_end\n );\n\n fp = $fopen(\"veer.signature\", \"w\");\n for (i=mem_signature_begin; i= `RV_DCCM_SADR && i < `RV_DCCM_EADR) begin\n bit[38:0] data;\n int bank, indx;\n bank = get_dccm_bank(i, indx);\n\n case (bank)\n 0: data = `DRAM(0)[indx];\n 1: data = `DRAM(1)[indx];\n `ifdef RV_DCCM_NUM_BANKS_4\n 2: data = `DRAM(2)[indx];\n 3: data = `DRAM(3)[indx];\n `endif\n `ifdef RV_DCCM_NUM_BANKS_8\n 2: data = `DRAM(2)[indx];\n 3: data = `DRAM(3)[indx];\n 4: data = `DRAM(4)[indx];\n 5: data = `DRAM(5)[indx];\n 6: data = `DRAM(6)[indx];\n 7: data = `DRAM(7)[indx];\n `endif\n endcase\n\n $fwrite(fp, \"%08X\\n\", data[31:0]);\n end else\n`endif\n // From RAM\n begin\n $fwrite(fp, \"%02X%02X%02X%02X\\n\",\n lmem.mem[i+3],\n lmem.mem[i+2],\n lmem.mem[i+1],\n lmem.mem[i+0]\n );\n end\n end\n\n $fclose(fp);\nendtask\n\n//////////////////////////////////////////////////////\n// DCCM\n//\nif (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable\n `define EL2_LOCAL_DCCM_RAM_TEST_PORTS .TEST1 (1'b0 ), \\\n .RME (1'b0 ), \\\n .RM (4'b0000), \\\n .LS (1'b0 ), \\\n .DS (1'b0 ), \\\n .SD (1'b0 ), \\\n .TEST_RNM(1'b0 ), \\\n .BC1 (1'b0 ), \\\n .BC2 (1'b0 ), \\\n\n logic [pt.DCCM_NUM_BANKS-1:0] [pt.DCCM_FDATA_WIDTH-1:0] dccm_wdata_bitflip;\n int ii;\n localparam DCCM_INDEX_DEPTH = ((pt.DCCM_SIZE)*1024)/((pt.DCCM_BYTE_WIDTH)*(pt.DCCM_NUM_BANKS)); // Depth of memory bank\n // 8 Banks, 16KB each (2048 x 72)\n always_ff @(el2_mem_export.clk) begin : inject_dccm_ecc_error\n if (~error_injection_mode.dccm_single_bit_error && ~error_injection_mode.dccm_double_bit_error) begin\n dccm_wdata_bitflip <= '{default:0};\n end else if (el2_mem_export.dccm_clken & el2_mem_export.dccm_wren_bank) begin\n for (ii=0; ii\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n\n#include \"tcp_server.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/**\n * Simple buffer for passing data between TCP sockets and DPI modules\n */\n#define BUFSIZE_BYTE 1024 // FIXME: This must be larger than the remote_bitbang\n // buffer in OpenOCD. Otherwise deadlock occurs.\n\nstruct tcp_buf {\n unsigned int rptr;\n unsigned int wptr;\n char buf[BUFSIZE_BYTE];\n};\n\n/**\n * TCP Server thread context structure\n */\nstruct tcp_server_ctx {\n // Writeable by the host thread\n char *display_name;\n uint16_t listen_port;\n volatile bool socket_run;\n // Writeable by the server thread\n struct tcp_buf *buf_in;\n struct tcp_buf *buf_out;\n int sfd; // socket fd\n int cfd; // client fd\n pthread_t sock_thread;\n};\n\nstatic bool tcp_buffer_is_full(struct tcp_buf *buf) {\n if (buf->wptr >= buf->rptr) {\n return (buf->wptr - buf->rptr) == (BUFSIZE_BYTE - 1);\n } else {\n return (buf->rptr - buf->wptr) == 1;\n }\n}\n\nstatic bool tcp_buffer_is_empty(struct tcp_buf *buf) {\n return (buf->wptr == buf->rptr);\n}\n\nstatic void tcp_buffer_put_byte(struct tcp_buf *buf, char dat) {\n bool done = false;\n while (!done) {\n if (!tcp_buffer_is_full(buf)) {\n buf->buf[buf->wptr++] = dat;\n buf->wptr %= BUFSIZE_BYTE;\n done = true;\n }\n }\n}\n\nstatic bool tcp_buffer_get_byte(struct tcp_buf *buf, char *dat) {\n if (tcp_buffer_is_empty(buf)) {\n return false;\n }\n *dat = buf->buf[buf->rptr++];\n buf->rptr %= BUFSIZE_BYTE;\n return true;\n}\n\nstatic struct tcp_buf *tcp_buffer_new(void) {\n struct tcp_buf *buf_new;\n buf_new = (struct tcp_buf *)malloc(sizeof(struct tcp_buf));\n buf_new->rptr = 0;\n buf_new->wptr = 0;\n return buf_new;\n}\n\nstatic void tcp_buffer_free(struct tcp_buf **buf) {\n free(*buf);\n *buf = NULL;\n}\n\n/**\n * Start a TCP server\n *\n * This function creates attempts to create a new TCP socket instance. The\n * socket is a non-blocking stream socket, with buffering disabled.\n *\n * @param ctx context object\n * @return 0 on success, -1 in case of an error\n */\nstatic int start(struct tcp_server_ctx *ctx) {\n int rv;\n\n assert(ctx->sfd == 0 && \"Server already started.\");\n\n // create socket\n int sfd = socket(AF_INET, SOCK_STREAM, 0);\n if (sfd == -1) {\n fprintf(stderr, \"%s: Unable to create socket: %s (%d)\\n\", ctx->display_name,\n strerror(errno), errno);\n return -1;\n }\n\n rv = fcntl(sfd, F_SETFL, O_NONBLOCK);\n if (rv != 0) {\n fprintf(stderr, \"%s: Unable to make socket non-blocking: %s (%d)\\n\",\n ctx->display_name, strerror(errno), errno);\n return -1;\n }\n\n // reuse existing socket (if existing)\n int reuse_socket = 1;\n rv = setsockopt(sfd, SOL_SOCKET, SO_REUSEADDR, &reuse_socket, sizeof(int));\n if (rv != 0) {\n fprintf(stderr, \"%s: Unable to set socket options: %s (%d)\\n\",\n ctx->display_name, strerror(errno), errno);\n return -1;\n }\n\n // stop tcp socket from buffering (buffering prevents timely responses to\n // OpenOCD which severly limits debugging performance)\n int tcp_nodelay = 1;\n rv = setsockopt(sfd, IPPROTO_TCP, TCP_NODELAY, &tcp_nodelay, sizeof(int));\n if (rv != 0) {\n fprintf(stderr, \"%s: Unable to set socket nodelay: %s (%d)\\n\",\n ctx->display_name, strerror(errno), errno);\n return -1;\n }\n\n // bind server\n struct sockaddr_in addr;\n memset(&addr, 0, sizeof(addr));\n addr.sin_family = AF_INET;\n addr.sin_addr.s_addr = htonl(INADDR_ANY);\n addr.sin_port = htons(ctx->listen_port);\n\n rv = bind(sfd, (struct sockaddr *)&addr, sizeof(addr));\n if (rv != 0) {\n fprintf(stderr, \"%s: Failed to bind socket: %s (%d)\\n\", ctx->display_name,\n strerror(errno), errno);\n return -1;\n }\n\n // listen for incoming connections\n rv = listen(sfd, 1);\n if (rv != 0) {\n fprintf(stderr, \"%s: Failed to listen on socket: %s (%d)\\n\",\n ctx->display_name, strerror(errno), errno);\n return -1;\n }\n\n ctx->sfd = sfd;\n assert(ctx->sfd > 0);\n\n return 0;\n}\n\n/**\n * Accept an incoming connection from a client (nonblocking)\n *\n * The resulting client fd is made non-blocking.\n *\n * @param ctx context object\n * @return 0 on success, any other value indicates an error\n */\nstatic int client_tryaccept(struct tcp_server_ctx *ctx) {\n int rv;\n\n assert(ctx->sfd > 0);\n assert(ctx->cfd == 0);\n\n int cfd = accept(ctx->sfd, NULL, NULL);\n\n if (cfd == -1 && errno == EAGAIN) {\n return -EAGAIN;\n }\n\n if (cfd == -1) {\n fprintf(stderr, \"%s: Unable to accept incoming connection: %s (%d)\\n\",\n ctx->display_name, strerror(errno), errno);\n return -1;\n }\n\n rv = fcntl(cfd, F_SETFL, O_NONBLOCK);\n if (rv != 0) {\n fprintf(stderr, \"%s: Unable to make client socket non-blocking: %s (%d)\\n\",\n ctx->display_name, strerror(errno), errno);\n return -1;\n }\n\n ctx->cfd = cfd;\n assert(ctx->cfd > 0);\n\n printf(\"%s: Accepted client connection\\n\", ctx->display_name);\n\n return 0;\n}\n\n/**\n * Stop the TCP server\n *\n * @param ctx context object\n */\nstatic void stop(struct tcp_server_ctx *ctx) {\n assert(ctx);\n if (!ctx->sfd) {\n return;\n }\n close(ctx->sfd);\n ctx->sfd = 0;\n}\n\n/**\n * Receive a byte from a connected client\n *\n * @param ctx context object\n * @param cmd byte received\n * @return true if a byte was read\n */\nstatic bool get_byte(struct tcp_server_ctx *ctx, char *cmd) {\n assert(ctx);\n\n ssize_t num_read = read(ctx->cfd, cmd, 1);\n\n if (num_read == 0) {\n return false;\n }\n if (num_read == -1) {\n if (errno == EAGAIN || errno == EWOULDBLOCK) {\n return false;\n } else if (errno == EBADF) {\n // Possibly client went away? Accept a new connection.\n fprintf(stderr, \"%s: Client disappeared.\\n\", ctx->display_name);\n tcp_server_client_close(ctx);\n return false;\n } else {\n fprintf(stderr, \"%s: Error while reading from client: %s (%d)\\n\",\n ctx->display_name, strerror(errno), errno);\n assert(0 && \"Error reading from client\");\n }\n }\n assert(num_read == 1);\n return true;\n}\n\n/**\n * Send a byte to a connected client\n *\n * @param ctx context object\n * @param cmd byte to send\n */\nstatic void put_byte(struct tcp_server_ctx *ctx, char cmd) {\n while (1) {\n ssize_t num_written = send(ctx->cfd, &cmd, sizeof(cmd), MSG_NOSIGNAL);\n if (num_written == -1) {\n if (errno == EAGAIN || errno == EWOULDBLOCK) {\n continue;\n } else if (errno == EPIPE) {\n printf(\"%s: Remote disconnected.\\n\", ctx->display_name);\n tcp_server_client_close(ctx);\n break;\n } else {\n fprintf(stderr, \"%s: Error while writing to client: %s (%d)\\n\",\n ctx->display_name, strerror(errno), errno);\n assert(0 && \"Error writing to client.\");\n }\n }\n if (num_written >= 1) {\n break;\n }\n }\n}\n\n/**\n * Cleanup server context\n *\n * @param ctx context object\n */\nstatic void ctx_free(struct tcp_server_ctx *ctx) {\n // Free the buffers\n tcp_buffer_free(&ctx->buf_in);\n tcp_buffer_free(&ctx->buf_out);\n // Free the display name\n free(ctx->display_name);\n // Free the ctx\n free(ctx);\n ctx = NULL;\n}\n\n/**\n * Thread function to create a new server instance\n *\n * @param ctx_void context object\n * @return Always returns NULL\n */\nstatic void *server_create(void *ctx_void) {\n // Cast to a server struct\n struct tcp_server_ctx *ctx = (struct tcp_server_ctx *)ctx_void;\n struct timeval timeout;\n\n // Start the server\n int rv = start(ctx);\n if (rv != 0) {\n fprintf(stderr, \"%s: Unable to create TCP server on port %d\\n\",\n ctx->display_name, ctx->listen_port);\n goto err_cleanup_return;\n }\n\n // Initialise timeout\n timeout.tv_sec = 0;\n\n // Initialise fd_set\n\n // Start waiting for connection / data\n char xfer_data;\n while (ctx->socket_run) {\n // Initialise structure of fds\n fd_set read_fds;\n FD_ZERO(&read_fds);\n if (ctx->sfd) {\n FD_SET(ctx->sfd, &read_fds);\n }\n if (ctx->cfd) {\n FD_SET(ctx->cfd, &read_fds);\n }\n // max fd num\n int mfd = (ctx->cfd > ctx->sfd) ? ctx->cfd : ctx->sfd;\n\n // Set timeout - 50us gives good performance\n timeout.tv_usec = 50;\n\n // Wait for socket activity or timeout\n rv = select(mfd + 1, &read_fds, NULL, NULL, &timeout);\n\n if (rv < 0) {\n printf(\"%s: Socket read failed, port: %d\\n\", ctx->display_name,\n ctx->listen_port);\n tcp_server_client_close(ctx);\n }\n\n // New connection\n if (FD_ISSET(ctx->sfd, &read_fds)) {\n client_tryaccept(ctx);\n }\n\n // New client data\n if (FD_ISSET(ctx->cfd, &read_fds)) {\n while (get_byte(ctx, &xfer_data)) {\n tcp_buffer_put_byte(ctx->buf_in, xfer_data);\n }\n }\n\n if (ctx->cfd != 0) {\n while (tcp_buffer_get_byte(ctx->buf_out, &xfer_data)) {\n put_byte(ctx, xfer_data);\n }\n }\n }\n\nerr_cleanup_return:\n\n // Simulation done - clean up\n tcp_server_client_close(ctx);\n stop(ctx);\n\n return NULL;\n}\n\n// Abstract interface functions\nstruct tcp_server_ctx *tcp_server_create(const char *display_name,\n int listen_port) {\n struct tcp_server_ctx *ctx =\n (struct tcp_server_ctx *)calloc(1, sizeof(struct tcp_server_ctx));\n assert(ctx);\n\n // Create the buffers\n struct tcp_buf *buf_in = tcp_buffer_new();\n struct tcp_buf *buf_out = tcp_buffer_new();\n assert(buf_in);\n assert(buf_out);\n\n // Populate the struct with buffer pointers\n ctx->buf_in = buf_in;\n ctx->buf_out = buf_out;\n\n // Set up socket details\n ctx->socket_run = true;\n ctx->listen_port = listen_port;\n ctx->display_name = strdup(display_name);\n assert(ctx->display_name);\n\n if (pthread_create(&ctx->sock_thread, NULL, server_create, (void *)ctx) !=\n 0) {\n fprintf(stderr, \"%s: Unable to create TCP socket thread\\n\",\n ctx->display_name);\n ctx_free(ctx);\n free(ctx);\n return NULL;\n }\n return ctx;\n}\n\nbool tcp_server_read(struct tcp_server_ctx *ctx, char *dat) {\n return tcp_buffer_get_byte(ctx->buf_in, dat);\n}\n\nvoid tcp_server_write(struct tcp_server_ctx *ctx, char dat) {\n tcp_buffer_put_byte(ctx->buf_out, dat);\n}\n\nvoid tcp_server_close(struct tcp_server_ctx *ctx) {\n // Shut down the socket thread\n ctx->socket_run = false;\n pthread_join(ctx->sock_thread, NULL);\n ctx_free(ctx);\n}\n\nvoid tcp_server_client_close(struct tcp_server_ctx *ctx) {\n assert(ctx);\n\n if (!ctx->cfd) {\n return;\n }\n\n close(ctx->cfd);\n ctx->cfd = 0;\n}\n" }, { "path": "testbench/tcp_server/tcp_server.h", "content": "// Copyright lowRISC contributors.\n// Copyright 2024 Antmicro \n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n\n#ifndef OPENTITAN_HW_DV_DPI_COMMON_TCP_SERVER_TCP_SERVER_H_\n#define OPENTITAN_HW_DV_DPI_COMMON_TCP_SERVER_TCP_SERVER_H_\n\n/**\n * Functions to create and interact with a threaded TCP server\n *\n * This is intended to be used by simulation add-on DPI modules to provide\n * basic TCP socket communication between a host and simulated peripherals.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n\nstruct tcp_server_ctx;\n\n/**\n * Non-blocking read of a byte from a connected client\n *\n * @param ctx tcp server context object\n * @param dat byte received\n * @return true if a byte was read\n */\nbool tcp_server_read(struct tcp_server_ctx *ctx, char *dat);\n\n/**\n * Write a byte to a connected client\n *\n * The write is internally buffered and so does not block if the client is not\n * ready to accept data, but does block if the buffer is full.\n *\n * @param ctx tcp server context object\n * @param dat byte to send\n */\nvoid tcp_server_write(struct tcp_server_ctx *ctx, char dat);\n\n/**\n * Create a new TCP server instance\n *\n * @param display_name C string description of server\n * @param listen_port On which port the server should listen\n * @return A pointer to the created context struct\n */\nstruct tcp_server_ctx *tcp_server_create(const char *display_name,\n int listen_port);\n\n/**\n * Shut down the server and free all reserved memory\n *\n * @param ctx tcp server context object\n */\nvoid tcp_server_close(struct tcp_server_ctx *ctx);\n\n/**\n * Instruct the server to disconnect a client\n *\n * @param ctx tcp server context object\n */\nvoid tcp_server_client_close(struct tcp_server_ctx *ctx);\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n#endif // OPENTITAN_HW_DV_DPI_COMMON_TCP_SERVER_TCP_SERVER_H_\n" }, { "path": "testbench/test_tb_top.cpp", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n#include \n#include \n#include \n#include \n#include \n#include \n#include \"Vtb_top.h\"\n#include \"verilated.h\"\n#include \"verilated_vcd_c.h\"\n\n\nvluint64_t main_time = 0;\n\ndouble sc_time_stamp () {\n return main_time;\n}\n\nstd::map load_symbols (const std::string& fileName) {\n\n // Open the symbol list file\n std::ifstream fp(fileName);\n if (!fp.good()) {\n std::cerr << \"Error loading symbols from '\" << fileName << \"'\" << std::endl;\n exit(EXIT_FAILURE);\n }\n\n // Parse lines\n std::map symbols;\n for (std::string line; std::getline(fp, line); ) {\n\n // Remove any trailing whitespaces\n auto pos = line.find_last_not_of(\" \\r\\n\\t\");\n line = line.substr(0, pos + 1);\n\n // Get address\n auto apos = line.find_first_of(\" \\r\\n\\t\");\n const auto astr = line.substr(0, apos);\n\n // Get name\n auto npos = line.find_last_of(\" \\r\\n\\t\");\n const auto nstr = line.substr(npos + 1);\n\n symbols[nstr] = strtol(astr.c_str(), nullptr, 16);\n }\n\n return symbols;\n}\n\nint main(int argc, char** argv) {\n std::cout << \"\\nVerilatorTB: Start of sim\\n\" << std::endl;\n\n Verilated::commandArgs(argc, argv);\n\n Vtb_top* tb = new Vtb_top;\n bool test_halt = false;\n bool test_lsu_clk_ratio = false;\n\n tb->mem_signature_begin = 0x00000000;\n tb->mem_signature_end = 0x00000000;\n tb->mem_mailbox = 0xD0580000;\n\n std::map symbols;\n\n // Setup memory signature range by looking up symbol names in the provided\n // symbol dump file\n for (int i=1; imem_signature_begin = beg->second;\n tb->mem_signature_end = end->second;\n }\n }\n }\n\n // Setup memory signature range if provided. Look for the commandline option\n // \"--mem-signature \". Addresses need to be hexadecimal\n for (int i=1; imem_signature_begin = strtol(argv[i+1], nullptr, 16);\n tb->mem_signature_end = strtol(argv[i+2], nullptr, 16);\n }\n }\n\n // Set mailbox address if provided. The commandline option is:\n // \"--mailbox-addr
\"\n for (int i=1; imem_mailbox = strtol(argv[i+1], nullptr, 16);\n }\n }\n\n // Set mailbox address to the address of the given symbol name via:\n // \"--mailbox-sym \"\n for (int i=1; imem_mailbox = it->second;\n }\n }\n }\n\n // run halt start procedure if requested with\n // \"--test-halt\"\n for (int i=1; imem_signature_begin << std::endl;\n std::cout << \"mem_signature_end = \" << std::hex << std::setw(8) <<\n std::uppercase << tb->mem_signature_end << std::endl;\n std::cout << \"mem_mailbox = \" << std::hex << std::setw(8) <<\n std::uppercase << tb->mem_mailbox << std::endl;\n std::cout << std::flush;\n\n // init trace dump\n VerilatedVcdC* tfp = NULL;\n\n#if VM_TRACE\n Verilated::traceEverOn(true);\n tfp = new VerilatedVcdC;\n tb->trace (tfp, 24);\n tfp->open (\"sim.vcd\");\n#endif\n tb->lsu_bus_clk_en = 1;\n // reset\n tb->rst_l = 0;\n for (int i=0;i<6;i++) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n tb->rst_l = 1;\n // Simulate\n if(test_halt) {\n // Test halt/start first (if requested)\n tb->i_cpu_halt_req = 1;\n // wait for ack\n std::cout<<\"Waiting for halt\"<o_cpu_halt_ack) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n tb->i_cpu_halt_req = 0;\n // wait for halt signal\n while(!tb->o_cpu_halt_status) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n // restart the CPU\n tb->i_cpu_run_req = 1;\n // wait for ack\n while(!tb->o_cpu_run_ack) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n tb->i_cpu_run_req = 0;\n // wait for run signal\n std::cout<<\"Waiting for restart\"<o_cpu_halt_status) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n // test mpc halt\n tb->mpc_debug_halt_req = 1;\n // wait for ack\n std::cout<<\"Waiting for mpc halt\"<mpc_debug_halt_ack) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n tb->mpc_debug_halt_req = 0;\n // wait for halt signal\n while(!tb->o_debug_mode_status) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n // restart the CPU\n tb->mpc_debug_run_req = 1;\n // wait for ack\n while(!tb->mpc_debug_run_ack) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n tb->mpc_debug_run_req = 0;\n // wait for run signal\n std::cout<<\"Waiting for mpc restart\"<o_debug_mode_status) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n } else {\n tb->i_cpu_halt_req = 0;\n tb->i_cpu_run_req = 0;\n tb->mpc_debug_halt_req = 0;\n tb->mpc_debug_run_req = 0;\n }\n\n if (test_lsu_clk_ratio) {\n std::cout<<\"Test lower clock ratio between bus master interface and core\" << std::endl;\n tb->lsu_bus_clk_en = 0;\n for(int i=0;i<30;i++) {\n for(int j=0;j<10;j++) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n tb->lsu_bus_clk_en = !tb->lsu_bus_clk_en;\n }\n tb->lsu_bus_clk_en = 1;\n\n std::cout<<\"Pre-start checks complete. Restarting again for normal operation.\" << std::endl;\n // reset\n tb->rst_l = 0;\n for (int i=0;i<30;i++) {\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n tb->rst_l = 1;\n }\n\n while(!Verilated::gotFinish()){\n#if VM_TRACE\n tfp->dump (main_time);\n#endif\n main_time += 5;\n tb->core_clk = !tb->core_clk;\n tb->eval();\n }\n tb->final();\n\n#if VM_TRACE\n tfp->close();\n#endif\n\n // Write coverage data\n#if VM_COVERAGE\n Verilated::threadContextp()->coveragep()->write(\"coverage.dat\");\n#endif\n\n std::cout << \"\\nVerilatorTB: End of sim\" << std::endl;\n exit(EXIT_SUCCESS);\n\n}\n" }, { "path": "testbench/tests/clk_override/clk_override.c", "content": "#include \n#include \n\nint main () {\n\n uint32_t value = 0;\n __asm__ volatile (\n \"csrw 0x7f8, %0\" // Write the value of foo to MCGC CSR\n : // No output operands\n : \"r\"(value) // Input operand (value) as register\n );\n\n for (int bit = 0; bit <= 9; bit++) {\n value = 1 << bit;\n __asm__ volatile (\n \"csrw 0x7f8, %0\"\n :\n : \"r\"(value)\n );\n }\n return 0;\n}\n" }, { "path": "testbench/tests/clk_override/clk_override.ld", "content": "/* SPDX-License-Identifier: Apache-2.0 */\n\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text.init*) *(.text*) }\n _end = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n}\n" }, { "path": "testbench/tests/clk_override/clk_override.mki", "content": "# SPDX-License-Identifier: Apache-2.0\n\nOFILES = crt0.o clk_override.o printf.o\nTEST_CFLAGS = -g -O3 -falign-functions=16\n" }, { "path": "testbench/tests/clk_override/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.section .text.init\n.global _start\n_start:\n\n # Setup stack\n la sp, STACK\n\n # Call main()\n call main\n\n # Map exit code: == 0 - success, != 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/tests/core_pause/core_pause.c", "content": "#include \n#include \n\nint main () {\n /* pause the core for 0xfff cycles */\n uint32_t value = 0xfff;\n __asm__ volatile (\n \"csrw 0x7c2, %0\" // Write the value of foo to MCPC CSR\n : // No output operands\n : \"r\"(value) // Input operand (value) as register\n );\n return 0;\n}\n" }, { "path": "testbench/tests/core_pause/core_pause.ld", "content": "/* SPDX-License-Identifier: Apache-2.0 */\n\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text.init*) *(.text*) }\n _end = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n}\n" }, { "path": "testbench/tests/core_pause/core_pause.mki", "content": "# SPDX-License-Identifier: Apache-2.0\n\nOFILES = crt0.o core_pause.o printf.o\nTEST_CFLAGS = -g -O3 -falign-functions=16\n" }, { "path": "testbench/tests/core_pause/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.section .text.init\n.global _start\n_start:\n\n # Setup stack\n la sp, STACK\n\n # Call main()\n call main\n\n # Map exit code: == 0 - success, != 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/tests/csr_access/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.section .text.init\n.global _start\n_start:\n\n # Setup stack\n la sp, STACK\n\n # Setup trap handler\n la t0, _trap\n csrw mtvec, t0\n\n # Setup PMP\n # Region 0 TOR 0x00000000-0xFFFFFFFF RWX\n li t0, 0xFFFFFFFF\n csrw pmpaddr0, t0\n li t0, 0x0000000F\n csrw pmpcfg0, t0\n\n # Call main()\n call main\n\n # Map exit code: == 0 - success, != 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n_trap:\n\n # Push stuff\n addi sp, sp, -17*4\n \n sw ra, 0*4(sp)\n sw a0, 1*4(sp)\n sw a1, 2*4(sp)\n sw a2, 3*4(sp)\n sw a3, 4*4(sp)\n sw a4, 5*4(sp)\n sw a5, 6*4(sp)\n sw a6, 7*4(sp)\n sw a7, 8*4(sp)\n sw t0, 9*4(sp)\n sw t1, 10*4(sp)\n sw t2, 11*4(sp)\n sw t3, 12*4(sp)\n sw t4, 13*4(sp)\n sw t5, 14*4(sp)\n sw t6, 15*4(sp)\n\n call trap_handler\n\n # Advance mepc if the cause is not an external interrupt\n csrr t0, mcause\n li t1, 0x80000000\n and t0, t0, t1\n bne t0, x0, _is_irq\n\n csrr t0, mepc\n addi t0, t0, 4\n csrw mepc, t0\n\n_is_irq:\n\n # Pop stuff\n lw ra, 0*4(sp)\n lw a0, 1*4(sp)\n lw a1, 2*4(sp)\n lw a2, 3*4(sp)\n lw a3, 4*4(sp)\n lw a4, 5*4(sp)\n lw a5, 6*4(sp)\n lw a6, 7*4(sp)\n lw a7, 8*4(sp)\n lw t0, 9*4(sp)\n lw t1, 10*4(sp)\n lw t2, 11*4(sp)\n lw t3, 12*4(sp)\n lw t4, 13*4(sp)\n lw t5, 14*4(sp)\n lw t6, 15*4(sp)\n\n addi sp, sp, 17*4\n\n mret\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/tests/csr_access/csr_access.c", "content": "#include \n#include \n#include \n\n#define _read_csr(csr) ({ \\\n unsigned long res; \\\n asm volatile (\"csrr %0, \" #csr : \"=r\"(res)); \\\n res; \\\n})\n\n#define _write_csr(csr, val) { \\\n asm volatile (\"csrw \" #csr \", %0\" : : \"r\"(val)); \\\n}\n\n#define MISA_U (1 << 20)\n\n#define MAGIC 0xDEADBEEF\n\nstruct csr_t {\n uint32_t addr;\n const char* name;\n};\n\nstatic const struct csr_t g_read_csrs[] = {\n\n {0xF11, \"mvendorid\"},\n {0xF12, \"marchid\"},\n {0xF13, \"mimpid\"},\n {0xF14, \"mhartid\"},\n\n {0x300, \"mstatus\"},\n {0x301, \"misa\"},\n {0x304, \"mie\"},\n {0x305, \"mtvec\"},\n\n {0x306, \"mcounteren\"},\n {0x320, \"mcountinhibit\"},\n\n {0x340, \"mscratch\"},\n {0x341, \"mepc\"},\n {0x342, \"mcause\"},\n {0x343, \"mtval\"},\n {0x344, \"mip\"},\n\n {0xB00, \"mcycle\"},\n {0xB02, \"minstret\"},\n {0xB80, \"mcycleh\"},\n {0xB82, \"minstreth\"},\n\n {0x30A, \"menvcfg\"},\n {0x31A, \"menvcfgh\"},\n\n {0x747, \"mseccfg\"},\n {0x757, \"mseccfgh\"},\n\n // PMP\n {0x3A0, \"pmpcfg0\"},\n {0x3B0, \"pmpaddr0\"},\n {0x3C0, \"pmpaddr16\"},\n {0x3D0, \"pmpaddr32\"},\n {0x3E0, \"pmpaddr48\"},\n\n {0xC00, \"cycle\"},\n {0xC80, \"cycleh\"},\n {0xC02, \"instret\"},\n {0xC82, \"instreth\"},\n\n // VeeR specific CSRs\n {0x7FF, \"mscause\"},\n {0xBC0, \"mdeau\"},\n {0xFC0, \"mdseac\"},\n {0xBC8, \"meivt\"},\n {0xFC8, \"meihap\"},\n {0xBC9, \"meipt\"},\n// {0xBCA, \"meicpct\"}, // This one seems to be readable only when an interrupt is pending\n {0xBCC, \"meicurpl\"},\n {0xBCB, \"meicidpl\"},\n// {0x7B0, \"dcsr\"}, // These are accessible only when the core is halted\n// {0x7B1, \"dpc\"},\n// {0x7C4, \"dmst\"},\n// {0x7C8, \"dicawics\"},\n// {0x7CC, \"dicad0h\"},\n// {0x7C9, \"dicad0\"},\n// {0x7CA, \"dicad1\"},\n// {0x7CB, \"dicago\"},\n {0x7A0, \"mtsel\"},\n {0x7A1, \"mtdata1\"},\n {0x7A2, \"mtdata2\"},\n {0x7C0, \"mrac\"},\n {0xB03, \"mhpmc3\"},\n {0xB04, \"mhpmc4\"},\n {0xB05, \"mhpmc5\"},\n {0xB06, \"mhpmc6\"},\n {0xB83, \"mhpmc3h\"},\n {0xB84, \"mhpmc4h\"},\n {0xB85, \"mhpmc5h\"},\n {0xB86, \"mhpmc6h\"},\n {0x323, \"mhpme3\"},\n {0x324, \"mhpme4\"},\n {0x325, \"mhpme5\"},\n {0x326, \"mhpme6\"},\n {0x7F0, \"micect\"},\n {0x7F1, \"miccmect\"},\n {0x7F2, \"mdccmect\"},\n {0x7C6, \"mpmc\"},\n {0x7F8, \"mcgc\"},\n {0x7C2, \"mcpc\"},\n {0x7F9, \"mfdc\"},\n {0x7D4, \"mitctl0\"},\n {0x7D7, \"mitctl1\"},\n {0x7D3, \"mitb0\"},\n {0x7D6, \"mitb1\"},\n {0x7D2, \"mitcnt0\"},\n {0x7D5, \"mitcnt1\"},\n {0xB07, \"perfva\"},\n {0xB08, \"perfvb\"},\n {0xB10, \"perfvc\"},\n {0xB87, \"perfvd\"},\n {0xB88, \"perfve\"},\n {0xB90, \"perfvf\"},\n {0x327, \"perfvg\"},\n {0x328, \"perfvh\"},\n {0x330, \"perfvi\"},\n {0x7CE, \"mfdht\"},\n {0x7CF, \"mfdhs\"}\n};\n\nstatic const struct csr_t g_write_csrs[] = {\n\n // Test write only for a few CSRs not to cause unwanted effects\n {0x304, \"mie\"},\n {0x340, \"mscratch\"},\n {0x30A, \"menvcfg\"},\n {0x31A, \"menvcfgh\"},\n};\n\nunsigned long read_csr (uint32_t addr) {\n\n // Define the result to be explicitly in register a0 - the return value\n // by the calling convention. Preset it to a magic value so that when\n // a CSR access fails the value stays there.\n volatile register uint32_t val asm(\"a0\") = MAGIC;\n\n // Since RISC-V does not allow indirect CSR addressing there's a big\n // 'switch' to handle that.\n switch (addr) {\n\n case 0xF11: val = _read_csr(0xF11); break;\n case 0xF12: val = _read_csr(0xF12); break;\n case 0xF13: val = _read_csr(0xF13); break;\n case 0xF14: val = _read_csr(0xF14); break;\n\n case 0x300: val = _read_csr(0x300); break;\n case 0x301: val = _read_csr(0x301); break;\n case 0x304: val = _read_csr(0x304); break;\n case 0x305: val = _read_csr(0x305); break;\n case 0x306: val = _read_csr(0x306); break;\n\n case 0x30A: val = _read_csr(0x30A); break;\n case 0x31A: val = _read_csr(0x31A); break;\n\n case 0x320: val = _read_csr(0x320); break;\n\n case 0x340: val = _read_csr(0x340); break;\n case 0x341: val = _read_csr(0x341); break;\n case 0x342: val = _read_csr(0x342); break;\n case 0x343: val = _read_csr(0x343); break;\n case 0x344: val = _read_csr(0x344); break;\n\n case 0xB00: val = _read_csr(0xB00); break;\n case 0xB02: val = _read_csr(0xB02); break;\n case 0xB80: val = _read_csr(0xB80); break;\n case 0xB82: val = _read_csr(0xB82); break;\n\n case 0xC00: val = _read_csr(0xC00); break;\n case 0xC80: val = _read_csr(0xC80); break;\n case 0xC02: val = _read_csr(0xC02); break;\n case 0xC82: val = _read_csr(0xC82); break;\n\n case 0x3A0: val = _read_csr(0x3A0); break;\n case 0x3B0: val = _read_csr(0x3B0); break;\n case 0x3C0: val = _read_csr(0x3C0); break;\n case 0x3D0: val = _read_csr(0x3D0); break;\n case 0x3E0: val = _read_csr(0x3E0); break;\n\n case 0x747: val = _read_csr(0x747); break;\n case 0x757: val = _read_csr(0x757); break;\n\n case 0x7FF: val = _read_csr(0x7FF); break;\n case 0x7C0: val = _read_csr(0x7C0); break;\n case 0x7C4: val = _read_csr(0x7C4); break;\n case 0xBC0: val = _read_csr(0xBC0); break;\n case 0xFC0: val = _read_csr(0xFC0); break;\n case 0xBC8: val = _read_csr(0xBC8); break;\n case 0xFC8: val = _read_csr(0xFC8); break;\n case 0xBC9: val = _read_csr(0xBC9); break;\n case 0xBCA: val = _read_csr(0xBCA); break;\n case 0xBCC: val = _read_csr(0xBCC); break;\n case 0xBCB: val = _read_csr(0xBCB); break;\n case 0x7B0: val = _read_csr(0x7B0); break;\n case 0x7B1: val = _read_csr(0x7B1); break;\n case 0x7C8: val = _read_csr(0x7C8); break;\n case 0x7CC: val = _read_csr(0x7CC); break;\n case 0x7C9: val = _read_csr(0x7C9); break;\n case 0x7CA: val = _read_csr(0x7CA); break;\n case 0x7CB: val = _read_csr(0x7CB); break;\n case 0x7A0: val = _read_csr(0x7A0); break;\n case 0x7A1: val = _read_csr(0x7A1); break;\n case 0x7A2: val = _read_csr(0x7A2); break;\n case 0xB03: val = _read_csr(0xB03); break;\n case 0xB04: val = _read_csr(0xB04); break;\n case 0xB05: val = _read_csr(0xB05); break;\n case 0xB06: val = _read_csr(0xB06); break;\n case 0xB83: val = _read_csr(0xB83); break;\n case 0xB84: val = _read_csr(0xB84); break;\n case 0xB85: val = _read_csr(0xB85); break;\n case 0xB86: val = _read_csr(0xB86); break;\n case 0x323: val = _read_csr(0x323); break;\n case 0x324: val = _read_csr(0x324); break;\n case 0x325: val = _read_csr(0x325); break;\n case 0x326: val = _read_csr(0x326); break;\n case 0x7F0: val = _read_csr(0x7F0); break;\n case 0x7F1: val = _read_csr(0x7F1); break;\n case 0x7F2: val = _read_csr(0x7F2); break;\n case 0x7C6: val = _read_csr(0x7C6); break;\n case 0x7F8: val = _read_csr(0x7F8); break;\n case 0x7C2: val = _read_csr(0x7C2); break;\n case 0x7F9: val = _read_csr(0x7F9); break;\n case 0x7D4: val = _read_csr(0x7D4); break;\n case 0x7D7: val = _read_csr(0x7D7); break;\n case 0x7D3: val = _read_csr(0x7D3); break;\n case 0x7D6: val = _read_csr(0x7D6); break;\n case 0x7D2: val = _read_csr(0x7D2); break;\n case 0x7D5: val = _read_csr(0x7D5); break;\n case 0xB07: val = _read_csr(0xB07); break;\n case 0xB08: val = _read_csr(0xB08); break;\n case 0xB10: val = _read_csr(0xB10); break;\n case 0xB87: val = _read_csr(0xB87); break;\n case 0xB88: val = _read_csr(0xB88); break;\n case 0xB90: val = _read_csr(0xB90); break;\n case 0x327: val = _read_csr(0x327); break;\n case 0x328: val = _read_csr(0x328); break;\n case 0x330: val = _read_csr(0x330); break;\n case 0x7CE: val = _read_csr(0x7CE); break;\n case 0x7CF: val = _read_csr(0x7CF); break;\n }\n\n return val;\n}\n\nvoid write_csr (uint32_t addr, uint32_t val) {\n\n // Since RISC-V does not allow indirect CSR addressing there's a big\n // 'switch' to handle that.\n\n switch (addr) {\n case 0x304: _write_csr(0x304, val); return;\n case 0x306: _write_csr(0x306, val); return;\n\n case 0x30A: _write_csr(0x30A, val); return;\n case 0x31A: _write_csr(0x31A, val); return;\n\n case 0x340: _write_csr(0x340, val); return;\n\n // The test verifies writes to just a handful of CSRs so not all of\n // them are mentioned here\n }\n\n // Unknown address\n _write_csr(0xFFF, 0);\n}\n\nvolatile unsigned long last_trap = 0xFFFFFFFF;\nvolatile unsigned long fail_count = 0;\n\nvoid test_csr_read_access (uint8_t user_mode) {\n\n int ok;\n\n // Loop over all implemented CSRs and try reading them.\n for (size_t i=0; i < sizeof(g_read_csrs) / sizeof(g_read_csrs[0]); ++i) {\n const struct csr_t* csr = &g_read_csrs[i];\n\n // Attempt CSR read\n last_trap = 0xFFFFFFFF;\n volatile unsigned long val = read_csr(csr->addr);\n\n // In user mode only unprivileged / user CSRs should be readable.\n // Accessing others should yield in illegal instruction exception\n if (user_mode) {\n if ((csr->addr & 0x300) == 0) { // Unprivileged / user\n ok = (last_trap == 0xFFFFFFFF);\n } else {\n ok = (last_trap == 0x2);\n\n // If the access failed check if the read was actually terminated\n if (ok && val != MAGIC) {\n printf(\"0x%08X\\n\", val);\n ok = 0;\n }\n }\n }\n // In machine mode all CSRs should be readable\n else {\n ok = (last_trap == 0xFFFFFFFF);\n }\n\n // Count fails\n fail_count += !ok;\n printf(\"%s 0x%03X '%s'\\n\", ok ? \"[ OK ]\" : \"[ FAIL ]\", csr->addr, csr->name);\n }\n\n}\n\nvoid test_csr_write_access (uint8_t user_mode) {\n\n int ok = 1;\n\n // Loop over all implemented CSRs and try writing them.\n for (size_t i=0; i < sizeof(g_write_csrs) / sizeof(g_write_csrs[0]); ++i) {\n const struct csr_t* csr = &g_write_csrs[i];\n\n // Attempt CSR write\n last_trap = 0xFFFFFFFF;\n write_csr(csr->addr, 0);\n\n // In user mode only unprivileged / user CSRs should be writable.\n // Accessing others should yield in illegal instruction exception\n if (user_mode) {\n if ((csr->addr & 0x300) == 0) { // Unprivileged / user\n ok = (last_trap == 0xFFFFFFFF);\n } else {\n ok = (last_trap == 0x2);\n }\n }\n // In machine mode all CSRs should be readable\n else {\n ok = (last_trap == 0xFFFFFFFF);\n }\n\n // Count fails\n fail_count += !ok;\n printf(\"%s 0x%03X '%s'\\n\", ok ? \"[ OK ]\" : \"[ FAIL ]\", csr->addr, csr->name);\n }\n}\n\nvoid user_main ();\nvoid machine_main ();\n\nvoid trap_handler () {\n\n unsigned long mstatus = _read_csr(mstatus);\n unsigned long mcause = _read_csr(mcause);\n printf(\"trap! mstatus=0x%08X, mcause=0x%08X\\n\", mstatus, mcause);\n\n // Store trap cause\n last_trap = mcause;\n\n // If the trap cause is ECALL.U return to machine_main()\n if (mcause == 0x08) {\n void* ptr = (void*)machine_main;\n _write_csr(mepc, (unsigned long)ptr - 4); // -4 as the trap handler advances mepc\n _write_csr(mstatus, mstatus | (3 << 11)); // MPP=11 (M-mode)\n }\n}\n\nint main () {\n printf(\"\\nHello VeeR\\n\");\n\n // The test requires user mode support\n if ((_read_csr(misa) & MISA_U) == 0) {\n printf(\"ERROR: The test requires user mode support. Aborting.\\n\");\n return -1;\n }\n \n // Test CSR access assuming machine mode\n printf(\"Testing CSR read...\\n\");\n test_csr_read_access(0);\n printf(\"Testing CSR write...\\n\");\n test_csr_write_access(0);\n\n // Write mcounteren.CY and mcounteren.IR to allow access cycle and instret\n // from user mode\n _write_csr(0x306, 0x5);\n\n // Clear mscratch\n _write_csr(mscratch, 0);\n\n // Go to user mode\n unsigned long mstatus = _read_csr(mstatus);\n mstatus &= ~(3 << 11); // MPP = 00 (user)\n mstatus &= ~(1 << 17); // MPRV = 0\n _write_csr(mstatus, mstatus);\n\n void* ptr = (void*)user_main;\n _write_csr(mepc, (unsigned long)ptr);\n asm volatile (\"mret\");\n\n return 0;\n}\n\n__attribute__((noreturn)) void user_main () {\n printf(\"\\nHello from user_main()\\n\");\n\n // Test CSR access assuming user mode\n printf(\"Testing CSR read...\\n\");\n test_csr_read_access(1);\n printf(\"Testing CSR write...\\n\");\n test_csr_write_access(1);\n\n // Try writing something to mscratch. Ignore exception, later the CSR is\n // to be read back from machine mode\n printf(\"Attempting to write mscratch...\\n\");\n _write_csr(mscratch, MAGIC);\n\n // Trigger an ECALL to go to machine mode again\n asm volatile (\"ecall\");\n\n while (1); // Make compiler not complain\n}\n\n__attribute__((noreturn)) void machine_main () {\n printf(\"\\nHello from machine_main()\\n\");\n\n // Check mscratch. It should not contain the pattern written from user mode\n printf(\"Reading mscratch...\\n\");\n unsigned long mscratch = _read_csr(mscratch);\n if (mscratch == MAGIC) {\n fail_count++;\n printf(\"[ FAIL ] previous write succeeded while it shouldn't\\n\");\n } else {\n printf(\"[ OK ]\\n\");\n }\n printf(\"\\n\");\n\n // Terminate the simulation\n // set the exit code to 0xFF / 0x01 and jump to _finish.\n unsigned long res = (fail_count == 0) ? 0xFF : 0x01;\n asm volatile (\n \"mv a0, %0\\n\"\n \"j _finish\\n\"\n : : \"r\"(res)\n );\n\n while (1); // Make compiler not complain\n}\n" }, { "path": "testbench/tests/csr_access/csr_access.ld", "content": "/* SPDX-License-Identifier: Apache-2.0 */\n\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text.init*) *(.text*) }\n _end = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n}\n" }, { "path": "testbench/tests/csr_access/csr_access.mki", "content": "# SPDX-License-Identifier: Apache-2.0\n\nOFILES = crt0.o csr_access.o veer.o\nTEST_CFLAGS = -g -O3 -falign-functions=16\n" }, { "path": "testbench/tests/csr_access/veer.c", "content": "/* SPDX-License-Identifier: Apache-2.0\n * Copyright 2023 Antmicro, Ltd. \n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \n#include \n\nextern volatile char tohost;\n\n\n__attribute__((__noreturn__)) void _exit (int status)\n{\n if (!status) tohost = 0xff;\n else tohost = 0x01;\n while (1) {};\n}\n\nint veer_tb_putc(char c, FILE *stream)\n{\n (void) stream;\n tohost = c;\n return c;\n}\n\nstatic FILE __stdio = FDEV_SETUP_STREAM(veer_tb_putc, NULL, NULL, _FDEV_SETUP_WRITE);\nFILE *const stdin = &__stdio;\n__strong_reference(stdin, stdout);\n__strong_reference(stdin, stderr);\n" }, { "path": "testbench/tests/csr_misa/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.section .text.init\n.global _start\n_start:\n\n # Setup stack\n la sp, STACK\n\n # Call main()\n call main\n\n # Map exit code: == 0 - success, != 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/tests/csr_misa/csr_misa.c", "content": "#include \n#include \n\n#define read_csr(csr) ({ \\\n unsigned long res; \\\n asm volatile (\"csrr %0, \" #csr : \"=r\"(res)); \\\n res; \\\n})\n\nint main () {\n #ifdef RV_USER_MODE\n const unsigned int user_mode = 1;\n #else\n const unsigned int user_mode = 0;\n #endif\n const unsigned int compressed_ext = 1;\n const unsigned int rv32i_base_isa = 1;\n const unsigned int int_mult_ext = 1;\n const unsigned int base = 1;\n const unsigned long golden = base << 30 | user_mode << 20 | int_mult_ext << 12 | \\\n rv32i_base_isa << 8 | compressed_ext << 2;\n\n // Read and print misa\n unsigned long misa = read_csr(misa);\n printf(\"misa = 0x%08X vs. 0x%08X\\n\", misa, golden);\n\n // Check\n return (misa == golden) ? 0 : -1;\n}\n" }, { "path": "testbench/tests/csr_misa/csr_misa.ld", "content": "/* SPDX-License-Identifier: Apache-2.0 */\n\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text.init*) *(.text*) }\n _end = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n}\n" }, { "path": "testbench/tests/csr_misa/csr_misa.mki", "content": "# SPDX-License-Identifier: Apache-2.0\n\nOFILES = crt0.o csr_misa.o printf.o\nTEST_CFLAGS = -g -O3 -falign-functions=16\n" }, { "path": "testbench/tests/csr_mseccfg/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.option norvc\n.option nopic\n\n.section .text.init\n.align 4\n.global _start\n_start:\n\n # Setup stack\n la sp, STACK\n\n # Setup trap handler\n la t0, _trap_entry\n csrw mtvec, t0\n\n # Call main()\n call main\n\n # Map exit code: == 0 - success, != 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.align 8\n_trap_entry:\n # In this test no trap should happen. Trigger test failure if it does.\n la a0, 1\n j _finish\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/tests/csr_mseccfg/csr_mseccfg.c", "content": "#include \n#include \n\n// Check if VeeR is configured for Smepmp\n#if !RV_SMEPMP\n#error \"The mseccfg CSR test requires Smepmp to be enabled\" \n#endif\n\n\n// ============================================================================\n\n#define read_csr(csr) ({ \\\n unsigned long res; \\\n asm volatile (\"csrr %0, %1\" : \"=r\"(res) : \"i\"(csr)); \\\n res; \\\n})\n\n#define write_csr(csr, val) { \\\n asm volatile (\"csrw %0, %1\" : : \"i\"(csr), \"r\"(val)); \\\n}\n\n// ============================================================================\n\n#define CSR_MSECCFG 0x747\n\n#define CSR_PMPCFG0 0x3A0\n#define CSR_PMPADDR0 0x3B0\n#define CSR_PMPADDR1 0x3B1\n#define CSR_PMPADDR2 0x3B2\n#define CSR_PMPADDR3 0x3B3\n\n#define MSECCFG_MML (1 << 0)\n#define MSECCFG_MMWP (1 << 1)\n#define MSECCFG_RLB (1 << 2)\n\n#define PMPCFG_R (1 << 0)\n#define PMPCFG_W (1 << 1)\n#define PMPCFG_X (1 << 2)\n#define PMPCFG_TOR (1 << 3)\n#define PMPCFG_L (1 << 7)\n\n// ============================================================================\n\nextern uint32_t _code_begin;\nextern uint32_t _code_end;\nextern uint32_t _data_begin;\nextern uint32_t _data_end;\n\n// Takes an address of a symbol\n#define A(x) ((uint32_t)(&(x)))\n// Converts an address for PMP by shifting it 2 bits to the right\n#define PMPADDR(x) ((x) >> 2)\n// Shifts PMP region config bits to appropriate position give the region index\n#define PMPREGION(cfg,idx) ((cfg) << (8 * ((idx) % 4)))\n\n// ============================================================================\n\nint main () {\n\n volatile uint32_t reg;\n\n // Check that mseccfg is zeroed\n printf(\"Checking that mseccfg is all-zero...\\n\");\n reg = read_csr(CSR_MSECCFG);\n if (reg != 0) {\n printf(\"ERROR: mseccfg=0x%08X\\n\", reg);\n return -1;\n }\n printf(\"ok.\\n\");\n\n // Verify that mseccfg.RLB can be set and cleared\n printf(\"Checking if mseccfg.RLB is writeable...\\n\");\n reg = read_csr(CSR_MSECCFG);\n write_csr(CSR_MSECCFG, reg | MSECCFG_RLB);\n\n reg = read_csr(CSR_MSECCFG);\n if (!(reg & MSECCFG_RLB)) {\n printf(\"ERROR: mseccfg.MML cannot be set\\n\");\n return -1;\n }\n\n reg = read_csr(CSR_MSECCFG);\n write_csr(CSR_MSECCFG, reg & ~MSECCFG_RLB);\n\n reg = read_csr(CSR_MSECCFG);\n if (reg & MSECCFG_RLB) {\n printf(\"ERROR: mseccfg.RLB cannot be cleared\\n\");\n return -1;\n }\n printf(\"ok.\\n\");\n\n // Configure PMP\n // region 1: _code_begin - _code_end, --X\n // region 3: _data_begin - _data_end, RW-\n write_csr(CSR_PMPADDR0, PMPADDR(A(_code_begin))); // PMPADDRx stores address bits 33:2\n write_csr(CSR_PMPADDR1, PMPADDR(A(_code_end)));\n write_csr(CSR_PMPADDR2, PMPADDR(A(_data_begin)));\n write_csr(CSR_PMPADDR3, PMPADDR(A(_data_end)));\n\n uint32_t pmpcfg;\n pmpcfg = PMPREGION((PMPCFG_TOR | PMPCFG_W | PMPCFG_X), 1) |\n PMPREGION((PMPCFG_TOR | PMPCFG_W), 2) |\n PMPREGION((PMPCFG_TOR | PMPCFG_R | PMPCFG_W), 3);\n\n write_csr(CSR_PMPCFG0, pmpcfg);\n\n // Set mseccfg.RLB and check if the region can be locked and unlocked\n printf(\"Checking if mseccfg.RLB=1 allows PMP regions to be unlocked...\\n\");\n\n reg = read_csr(CSR_MSECCFG);\n write_csr(CSR_MSECCFG, reg | MSECCFG_RLB);\n\n // Lock region 1 and check\n write_csr(CSR_PMPCFG0, pmpcfg | PMPREGION(PMPCFG_L, 1));\n reg = read_csr(CSR_PMPCFG0);\n if (!(reg & PMPREGION(PMPCFG_L, 1))) {\n printf(\"ERROR: cannot lock PMP region 0\\n\");\n return -1;\n }\n\n // Unlock region 1 and check\n write_csr(CSR_PMPCFG0, pmpcfg);\n reg = read_csr(CSR_PMPCFG0);\n if (reg & PMPREGION(PMPCFG_L, 1)) {\n printf(\"ERROR: cannot unlock PMP region 0\\n\");\n return -1;\n }\n printf(\"ok.\\n\");\n\n // Verify that when at least one PMP region is locked mseccfg.RLB cannot be\n // set.\n printf(\"Checking if mseccfg.RLB cannot be set if any PMP region is locked...\\n\");\n\n // Clear RLB\n reg = read_csr(CSR_MSECCFG);\n write_csr(CSR_MSECCFG, reg & ~MSECCFG_RLB);\n\n // Lock region 1\n write_csr(CSR_PMPCFG0, pmpcfg | PMPREGION(PMPCFG_L, 1));\n\n // Try setting RLB and check\n reg = read_csr(CSR_MSECCFG);\n write_csr(CSR_MSECCFG, reg | MSECCFG_RLB);\n\n reg = read_csr(CSR_MSECCFG);\n if (reg & MSECCFG_RLB) {\n printf(\"ERROR: mseccfg.RLB can still be set\\n\");\n return -1;\n }\n printf(\"ok.\\n\");\n\n // Verify that mseccfg.MML cannot be cleared once set\n printf(\"Checking if mseccfg.MML cannot be cleared...\\n\");\n\n // Lock region 3. Region 1 is already locked. This is necessary for the\n // test as when MML=1 non-locked regions always deny access in M mode\n write_csr(CSR_PMPCFG0, pmpcfg | PMPREGION(PMPCFG_L, 3));\n\n reg = read_csr(CSR_MSECCFG);\n write_csr(CSR_MSECCFG, reg | MSECCFG_MML);\n reg = read_csr(CSR_MSECCFG);\n write_csr(CSR_MSECCFG, reg & ~MSECCFG_MML);\n\n reg = read_csr(CSR_MSECCFG);\n if (!(reg & MSECCFG_MML)) {\n printf(\"ERROR: mseccfg.MML can be cleared\\n\");\n return -1;\n }\n printf(\"ok.\\n\");\n\n // Verify that mseccfg.MMWP cannot be cleared once set\n printf(\"Checking if mseccfg.MMWP cannot be cleared...\\n\");\n reg = read_csr(CSR_MSECCFG);\n write_csr(CSR_MSECCFG, reg | MSECCFG_MMWP);\n reg = read_csr(CSR_MSECCFG);\n write_csr(CSR_MSECCFG, reg & ~MSECCFG_MMWP);\n\n reg = read_csr(CSR_MSECCFG);\n if (!(reg & MSECCFG_MMWP)) {\n printf(\"ERROR: mseccfg.MMWP can be cleared\\n\");\n return -1;\n }\n printf(\"ok.\\n\");\n\n return 0;\n}\n" }, { "path": "testbench/tests/csr_mseccfg/csr_mseccfg.ld", "content": "/* SPDX-License-Identifier: Apache-2.0 */\n\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n _code_begin = .;\n .text : { *(.text.init*) *(.text*) }\n _code_end = .;\n _data_begin = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n _data_end = .;\n}\n" }, { "path": "testbench/tests/csr_mseccfg/csr_mseccfg.mki", "content": "# SPDX-License-Identifier: Apache-2.0\n\nOFILES = crt0.o csr_mseccfg.o printf.o\nTEST_CFLAGS = -g -O0 -falign-functions=16\n" }, { "path": "testbench/tests/csr_mstatus/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.section .text.init\n.global _start\n_start:\n\n # Setup stack\n la sp, STACK\n\n # Setup PMP\n # Region 0 TOR 0x00000000-0xFFFFFFFF RWX\n li t0, 0xFFFFFFFF\n csrw pmpaddr0, t0\n li t0, 0x0000000F\n csrw pmpcfg0, t0\n\n # Call main()\n call main\n\n # Map exit code: == 0 - success, != 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/tests/csr_mstatus/csr_mstatus.c", "content": "#include \n\n#define read_csr(csr) ({ \\\n unsigned long res; \\\n asm volatile (\"csrr %0, \" #csr : \"=r\"(res)); \\\n res; \\\n})\n\n#define write_csr(csr, val) { \\\n asm volatile (\"csrw \" #csr \", %0\" : : \"r\"(val)); \\\n}\n\n#define MISA_U (1 << 20)\n\nint main () {\n\n // The test requires user mode support\n if ((read_csr(misa) & MISA_U) == 0) {\n printf(\"ERROR: The test requires user mode support. Aborting.\\n\");\n return -1;\n }\n\n unsigned long prv, cur;\n int res = 0;\n\n // Test privilete mode availablilty by writing to mstatus.MPP and reading\n // it back. The value should match.\n\n // M-mode\n printf(\"M mode:\\n\");\n prv = read_csr(mstatus);\n prv &= ~(3 << 11);\n prv |= (3 << 11); // MPP = 11\n printf(\" 0x%08X\\n\", prv);\n write_csr(mstatus, prv);\n cur = read_csr(mstatus);\n printf(\" 0x%08X\\n\", cur);\n if (((prv ^ cur) & (3 << 11)) == 0) {\n printf(\" ok.\\n\");\n } else {\n printf(\" not supported.\\n\");\n res = -1; // error\n }\n\n // S-mode\n printf(\"S mode:\\n\");\n prv = read_csr(mstatus);\n prv &= ~(3 << 11);\n prv |= (1 << 11); // MPP = 01\n printf(\" 0x%08X\\n\", prv);\n write_csr(mstatus, prv);\n cur = read_csr(mstatus);\n printf(\" 0x%08X\\n\", cur);\n if (((prv ^ cur) & (3 << 11)) == 0) {\n printf(\" ok.\\n\");\n res = -1; // error\n } else {\n printf(\" not supported.\\n\");\n }\n\n // U-mode\n printf(\"U mode:\\n\");\n prv = read_csr(mstatus);\n prv &= ~(3 << 11); // MPP = 00\n printf(\" 0x%08X\\n\", prv);\n write_csr(mstatus, prv);\n cur = read_csr(mstatus);\n printf(\" 0x%08X\\n\", cur);\n if (((prv ^ cur) & (3 << 11)) == 0) {\n printf(\" ok.\\n\");\n } else {\n printf(\" not supported.\\n\");\n res = -1; // error\n }\n\n // Test the MPRV bit\n\n printf(\"MPRV\\n\");\n\n prv = read_csr(mstatus);\n prv |= (1 << 17); // MPRV=1\n printf(\" 0x%08X\\n\", prv);\n write_csr(mstatus, prv);\n cur = read_csr(mstatus);\n printf(\" 0x%08X\\n\", cur);\n if (((prv ^ cur) & (3 << 17)) != 0) {\n printf(\" cannot set!\\n\");\n res = -1;\n } else {\n printf(\" ok.\\n\");\n }\n\n prv = read_csr(mstatus);\n prv &= ~(1 << 17); // MPRV=0\n printf(\" 0x%08X\\n\", prv);\n write_csr(mstatus, prv);\n cur = read_csr(mstatus);\n printf(\" 0x%08X\\n\", cur);\n if (((prv ^ cur) & (3 << 17)) != 0) {\n printf(\" cannot clear!\\n\");\n res = -1;\n } else {\n printf(\" ok.\\n\");\n }\n\n return res;\n}\n" }, { "path": "testbench/tests/csr_mstatus/csr_mstatus.ld", "content": "/* SPDX-License-Identifier: Apache-2.0 */\n\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text.init*) *(.text*) }\n _end = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n}\n" }, { "path": "testbench/tests/csr_mstatus/csr_mstatus.mki", "content": "# SPDX-License-Identifier: Apache-2.0\n\nOFILES = crt0.o csr_mstatus.o printf.o\nTEST_CFLAGS = -g -O3 -falign-functions=16\n" }, { "path": "testbench/tests/dhry/dhry.h", "content": "#pragma once\n\n/*\n ****************************************************************************\n *\n * \"DHRYSTONE\" Benchmark Program\n * -----------------------------\n *\n * Version: C, Version 2.1\n *\n * File: dhry.h (part 1 of 3)\n *\n * Date: May 25, 1988\n *\n * Author: Reinhold P. Weicker\n * Siemens AG, E STE 35\n * Postfach 3240\n * 8520 Erlangen\n * Germany (West)\n * Phone: [xxx-49]-9131-7-20330\n * (8-17 Central European Time)\n * Usenet: ..!mcvax!unido!estevax!weicker\n *\n * Original Version (in Ada) published in\n * \"Communications of the ACM\" vol. 27., no. 10 (Oct. 1984),\n * pp. 1013 - 1030, together with the statistics\n * on which the distribution of statements etc. is based.\n *\n * In this C version, the following C library functions are used:\n * - strcpy, strcmp (inside the measurement loop)\n * - printf, scanf (outside the measurement loop)\n * In addition, Berkeley UNIX system calls \"times ()\" or \"time ()\"\n * are used for execution time measurement. For measurements\n * on other systems, these calls have to be changed.\n *\n * Collection of Results:\n * Reinhold Weicker (address see above) and\n *\n * Rick Richardson\n * PC Research. Inc.\n * 94 Apple Orchard Drive\n * Tinton Falls, NJ 07724\n * Phone: (201) 389-8963 (9-17 EST)\n * Usenet: ...!uunet!pcrat!rick\n *\n * Please send results to Rick Richardson and/or Reinhold Weicker.\n * Complete information should be given on hardware and software used.\n * Hardware information includes: Machine type, CPU, type and size\n * of caches; for microprocessors: clock frequency, memory speed\n * (number of wait states).\n * Software information includes: Compiler (and runtime library)\n * manufacturer and version, compilation switches, OS version.\n * The Operating System version may give an indication about the\n * compiler; Dhrystone itself performs no OS calls in the measurement loop.\n *\n * The complete output generated by the program should be mailed\n * such that at least some checks for correctness can be made.\n *\n ***************************************************************************\n *\n * History: This version C/2.1 has been made for two reasons:\n *\n * 1) There is an obvious need for a common C version of\n * Dhrystone, since C is at present the most popular system\n * programming language for the class of processors\n * (microcomputers, minicomputers) where Dhrystone is used most.\n * There should be, as far as possible, only one C version of\n * Dhrystone such that results can be compared without\n * restrictions. In the past, the C versions distributed\n * by Rick Richardson (Version 1.1) and by Reinhold Weicker\n * had small (though not significant) differences.\n *\n * 2) As far as it is possible without changes to the Dhrystone\n * statistics, optimizing compilers should be prevented from\n * removing significant statements.\n *\n * This C version has been developed in cooperation with\n * Rick Richardson (Tinton Falls, NJ), it incorporates many\n * ideas from the \"Version 1.1\" distributed previously by\n * him over the UNIX network Usenet.\n * I also thank Chaim Benedelac (National Semiconductor),\n * David Ditzel (SUN), Earl Killian and John Mashey (MIPS),\n * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)\n * for their help with comments on earlier versions of the\n * benchmark.\n *\n * Changes: In the initialization part, this version follows mostly\n * Rick Richardson's version distributed via Usenet, not the\n * version distributed earlier via floppy disk by Reinhold Weicker.\n * As a concession to older compilers, names have been made\n * unique within the first 8 characters.\n * Inside the measurement loop, this version follows the\n * version previously distributed by Reinhold Weicker.\n *\n * At several places in the benchmark, code has been added,\n * but within the measurement loop only in branches that\n * are not executed. The intention is that optimizing compilers\n * should be prevented from moving code out of the measurement\n * loop, or from removing code altogether. Since the statements\n * that are executed within the measurement loop have NOT been\n * changed, the numbers defining the \"Dhrystone distribution\"\n * (distribution of statements, operand types and locality)\n * still hold. Except for sophisticated optimizing compilers,\n * execution times for this version should be the same as\n * for previous versions.\n *\n * Since it has proven difficult to subtract the time for the\n * measurement loop overhead in a correct way, the loop check\n * has been made a part of the benchmark. This does have\n * an impact - though a very minor one - on the distribution\n * statistics which have been updated for this version.\n *\n * All changes within the measurement loop are described\n * and discussed in the companion paper \"Rationale for\n * Dhrystone version 2\".\n *\n * Because of the self-imposed limitation that the order and\n * distribution of the executed statements should not be\n * changed, there are still cases where optimizing compilers\n * may not generate code for some statements. To a certain\n * degree, this is unavoidable for small synthetic benchmarks.\n * Users of the benchmark are advised to check code listings\n * whether code is generated for all statements of Dhrystone.\n *\n * Version 2.1 is identical to version 2.0 distributed via\n * the UNIX network Usenet in March 1988 except that it corrects\n * some minor deficiencies that were found by users of version 2.0.\n * The only change within the measurement loop is that a\n * non-executed \"else\" part was added to the \"if\" statement in\n * Func_3, and a non-executed \"else\" part removed from Proc_3.\n *\n ***************************************************************************\n *\n * Defines: The following \"Defines\" are possible:\n * -DREG=register (default: Not defined)\n * As an approximation to what an average C programmer\n * might do, the \"register\" storage class is applied\n * (if enabled by -DREG=register)\n * - for local variables, if they are used (dynamically)\n * five or more times\n * - for parameters if they are used (dynamically)\n * six or more times\n * Note that an optimal \"register\" strategy is\n * compiler-dependent, and that \"register\" declarations\n * do not necessarily lead to faster execution.\n * -DNOSTRUCTASSIGN (default: Not defined)\n * Define if the C compiler does not support\n * assignment of structures.\n * -DNOENUMS (default: Not defined)\n * Define if the C compiler does not support\n * enumeration types.\n * -DTIMES (default)\n * -DTIME\n * The \"times\" function of UNIX (returning process times)\n * or the \"time\" function (returning wallclock time)\n * is used for measurement.\n * For single user machines, \"time ()\" is adequate. For\n * multi-user machines where you cannot get single-user\n * access, use the \"times ()\" function. If you have\n * neither, use a stopwatch in the dead of night.\n * \"printf\"s are provided marking the points \"Start Timer\"\n * and \"Stop Timer\". DO NOT use the UNIX \"time(1)\"\n * command, as this will measure the total time to\n * run this program, which will (erroneously) include\n * the time to allocate storage (malloc) and to perform\n * the initialization.\n * -DHZ=nnn\n * In Berkeley UNIX, the function \"times\" returns process\n * time in 1/HZ seconds, with HZ = 60 for most systems.\n * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY\n * A VALUE.\n *\n ***************************************************************************\n *\n * Compilation model and measurement (IMPORTANT):\n *\n * This C version of Dhrystone consists of three files:\n * - dhry.h (this file, containing global definitions and comments)\n * - dhry_1.c (containing the code corresponding to Ada package Pack_1)\n * - dhry_2.c (containing the code corresponding to Ada package Pack_2)\n *\n * The following \"ground rules\" apply for measurements:\n * - Separate compilation\n * - No procedure merging\n * - Otherwise, compiler optimizations are allowed but should be indicated\n * - Default results are those without register declarations\n * See the companion paper \"Rationale for Dhrystone Version 2\" for a more\n * detailed discussion of these ground rules.\n *\n * For 16-Bit processors (e.g. 80186, 80286), times for all compilation\n * models (\"small\", \"medium\", \"large\" etc.) should be given if possible,\n * together with a definition of these models for the compiler system used.\n *\n **************************************************************************\n *\n * Dhrystone (C version) statistics:\n *\n * [Comment from the first distribution, updated for version 2.\n * Note that because of language differences, the numbers are slightly\n * different from the Ada version.]\n *\n * The following program contains statements of a high level programming\n * language (here: C) in a distribution considered representative:\n *\n * assignments 52 (51.0 %)\n * control statements 33 (32.4 %)\n * procedure, function calls 17 (16.7 %)\n *\n * 103 statements are dynamically executed. The program is balanced with\n * respect to the three aspects:\n *\n * - statement type\n * - operand type\n * - operand locality\n * operand global, local, parameter, or constant.\n *\n * The combination of these three aspects is balanced only approximately.\n *\n * 1. Statement Type:\n * ----------------- number\n *\n * V1 = V2 9\n * (incl. V1 = F(..)\n * V = Constant 12\n * Assignment, 7\n * with array element\n * Assignment, 6\n * with record component\n * --\n * 34 34\n *\n * X = Y +|-|\"&&\"|\"|\" Z 5\n * X = Y +|-|\"==\" Constant 6\n * X = X +|- 1 3\n * X = Y *|/ Z 2\n * X = Expression, 1\n * two operators\n * X = Expression, 1\n * three operators\n * --\n * 18 18\n *\n * if .... 14\n * with \"else\" 7\n * without \"else\" 7\n * executed 3\n * not executed 4\n * for ... 7 | counted every time\n * while ... 4 | the loop condition\n * do ... while 1 | is evaluated\n * switch ... 1\n * break 1\n * declaration with 1\n * initialization\n * --\n * 34 34\n *\n * P (...) procedure call 11\n * user procedure 10\n * library procedure 1\n * X = F (...)\n * function call 6\n * user function 5\n * library function 1\n * --\n * 17 17\n * ---\n * 103\n *\n * The average number of parameters in procedure or function calls\n * is 1.82 (not counting the function values aX *\n *\n * 2. Operators\n * ------------\n * number approximate\n * percentage\n *\n * Arithmetic 32 50.8\n *\n * + 21 33.3\n * - 7 11.1\n * * 3 4.8\n * / (int div) 1 1.6\n *\n * Comparison 27 42.8\n *\n * == 9 14.3\n * /= 4 6.3\n * > 1 1.6\n * < 3 4.8\n * >= 1 1.6\n * <= 9 14.3\n *\n * Logic 4 6.3\n *\n * && (AND-THEN) 1 1.6\n * | (OR) 1 1.6\n * ! (NOT) 2 3.2\n *\n * -- -----\n * 63 100.1\n *\n *\n * 3. Operand Type (counted once per operand reference):\n * ---------------\n * number approximate\n * percentage\n *\n * Integer 175 72.3 %\n * Character 45 18.6 %\n * Pointer 12 5.0 %\n * String30 6 2.5 %\n * Array 2 0.8 %\n * Record 2 0.8 %\n * --- -------\n * 242 100.0 %\n *\n * When there is an access path leading to the final operand (e.g. a record\n * component), only the final data type on the access path is counted.\n *\n *\n * 4. Operand Locality:\n * -------------------\n * number approximate\n * percentage\n *\n * local variable 114 47.1 %\n * global variable 22 9.1 %\n * parameter 45 18.6 %\n * value 23 9.5 %\n * reference 22 9.1 %\n * function result 6 2.5 %\n * constant 55 22.7 %\n * --- -------\n * 242 100.0 %\n *\n *\n * The program does not compute anything meaningful, but it is syntactically\n * and semantically correct. All variables have a value assigned to them\n * before they are used as a source operand.\n *\n * There has been no explicit effort to account for the effects of a\n * cache, or to balance the use of long or short displacements for code or\n * data.\n *\n ***************************************************************************\n */\n\n/* Compiler and system dependent definitions: */\n\n#ifndef TIME\n#undef TIMES\n#define TIMES\n#endif\n /* Use times(2) time function unless */\n /* explicitly defined otherwise */\n\n#ifdef MSC_CLOCK\n#undef HZ\n#undef TIMES\n#include \n#define HZ CLK_TCK\n#endif\n /* Use Microsoft C hi-res clock */\n\n#ifdef TIMES\n#include \n#include \n\n#ifndef HZ\n#define HZ 100\n#endif\n /* for \"times\" */\n#endif\n\n#define Mic_secs_Per_Second 1000000.0\n /* Berkeley UNIX C returns process times in seconds/HZ */\n\n#ifdef NOSTRUCTASSIGN\n#define structassign(d, s) memcpy(&(d), &(s), sizeof(d))\n#else\n#define structassign(d, s) d = s\n#endif\n\n#ifdef NOENUM\n#define Ident_1 0\n#define Ident_2 1\n#define Ident_3 2\n#define Ident_4 3\n#define Ident_5 4\n typedef int Enumeration;\n#else\n typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}\n Enumeration;\n#endif\n /* for boolean and enumeration types in Ada, Pascal */\n\n/* General definitions: */\n\n//#include \n /* for strcpy, strcmp */\n\n#define Null 0\n /* Value of a Null pointer */\n#define true 1\n#define false 0\n\ntypedef int One_Thirty;\ntypedef int One_Fifty;\ntypedef char Capital_Letter;\ntypedef int Boolean;\ntypedef char Str_30 [31];\ntypedef int Arr_1_Dim [50];\ntypedef int Arr_2_Dim [50] [50];\n\ntypedef struct record\n {\n struct record *Ptr_Comp;\n Enumeration Discr;\n union {\n struct {\n Enumeration Enum_Comp;\n int Int_Comp;\n char Str_Comp [31];\n } var_1;\n struct {\n Enumeration E_Comp_2;\n char Str_2_Comp [31];\n } var_2;\n struct {\n char Ch_1_Comp;\n char Ch_2_Comp;\n } var_3;\n } variant;\n } Rec_Type, *Rec_Pointer;\n\n\n" }, { "path": "testbench/tests/dhry/dhry.mki", "content": "OFILES = crt0.o dhry_1.o dhry_2.o printf.o\nTEST_CFLAGS = -g -O3\n" }, { "path": "testbench/tests/dhry/dhry_1.c", "content": "#define VEER\n/*\n ****************************************************************************\n *\n * \"DHRYSTONE\" Benchmark Program\n * -----------------------------\n *\n * Version: C, Version 2.1\n *\n * File: dhry_1.c (part 2 of 3)\n *\n * Date: May 25, 1988\n *\n * Author: Reinhold P. Weicker\n *\n ****************************************************************************\n */\n\n#ifdef VEER\n#include \n#include \nextern uint64_t get_mcycle();\n#endif\n\n#include \"dhry.h\"\n\n/* Global Variables: */\n\nRec_Pointer Ptr_Glob,\n Next_Ptr_Glob;\nint Int_Glob;\nBoolean Bool_Glob;\nchar Ch_1_Glob,\n Ch_2_Glob;\nint Arr_1_Glob [50];\nint Arr_2_Glob [50] [50];\n\nEnumeration Func_1 ();\n /* forward declaration necessary since Enumeration may not simply be int */\n\n#ifndef REG\n Boolean Reg = false;\n#define REG\n /* REG becomes defined as empty */\n /* i.e. no register variables */\n#else\n Boolean Reg = true;\n#endif\n\n/* variables for time measurement: */\n\n#ifdef TIMES\nstruct tms time_info;\n#define Too_Small_Time (2*HZ)\n /* Measurements should last at least about 2 seconds */\n#endif\n#ifdef TIME\nextern long time();\n /* see library function \"time\" */\n#define Too_Small_Time 2\n /* Measurements should last at least 2 seconds */\n#endif\n#ifdef MSC_CLOCK\nextern clock_t clock();\n#define Too_Small_Time (2*HZ)\n#endif\n\nlong\n Begin_Time,\n End_Time,\n User_Time;\n\nfloat Microseconds,\n Dhrystones_Per_Second;\n\n/* end of variables for time measurement */\n\n\nextern char* strcpy(char*, const char*);\n\nextern Boolean Func_2 (Str_30, Str_30);\nextern void Proc_7 (One_Fifty Int_1_Par_Val, One_Fifty Int_2_Par_Val,\n One_Fifty *Int_Par_Ref);\n\nextern void Proc_8 (Arr_1_Dim Arr_1_Par_Ref, Arr_2_Dim Arr_2_Par_Ref,\n int Int_1_Par_Val, int Int_2_Par_Val);\n\nextern void Proc_6 (Enumeration Enum_Val_Par,\n Enumeration *Enum_Ref_Par);\n\nvoid Proc_5();\nvoid Proc_4();\n\nvoid Proc_1(Rec_Pointer Ptr_Val_Par);\nvoid Proc_2(One_Fifty *Int_Par_Ref);\nvoid Proc_3(Rec_Pointer *Ptr_Ref_Par);\n\n\nint\nmain ()\n/*****/\n\n /* main program, corresponds to procedures */\n /* Main and Proc_0 in the Ada version */\n{\n One_Fifty Int_1_Loc;\n REG One_Fifty Int_2_Loc;\n One_Fifty Int_3_Loc;\n REG char Ch_Index;\n Enumeration Enum_Loc;\n Str_30 Str_1_Loc;\n Str_30 Str_2_Loc;\n REG int Run_Index;\n REG int Number_Of_Runs;\n\n /* Initializations */\n\n Rec_Type rec0;\n Rec_Type rec1;\n\n Next_Ptr_Glob = &rec0;\n Ptr_Glob = &rec1;\n\n Ptr_Glob->Ptr_Comp = Next_Ptr_Glob;\n Ptr_Glob->Discr = Ident_1;\n Ptr_Glob->variant.var_1.Enum_Comp = Ident_3;\n Ptr_Glob->variant.var_1.Int_Comp = 40;\n strcpy (Ptr_Glob->variant.var_1.Str_Comp,\n \"DHRYSTONE PROGRAM, SOME STRING\");\n strcpy (Str_1_Loc, \"DHRYSTONE PROGRAM, 1'ST STRING\");\n\n Arr_2_Glob [8][7] = 10;\n /* Was missing in published program. Without this statement, */\n /* Arr_2_Glob [8][7] would have an undefined value. */\n /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */\n /* overflow may occur for this array element. */\n\n printf (\"Dhrystone Benchmark, Version 2.1 (Language: C)\\n\");\n if (Reg)\n {\n printf (\"Program compiled with 'register' attribute\\n\");\n }\n else\n {\n printf (\"Program compiled without 'register' attribute\\n\");\n }\n\n #ifndef VEER\n printf (\"Please give the number of runs through the benchmark: \");\n {\n int n = 1000;\n scanf (\"%d\", &n);\n Number_Of_Runs = n;\n }\n printf (\"\\n\");\n #else\n // We do not have scanf. Hardwire number of runs.\n Number_Of_Runs = 1000;\n #endif\n\n printf (\"Execution starts, %d runs through Dhrystone\\n\", Number_Of_Runs);\n\n /***************/\n /* Start timer */\n /***************/\n\n#ifdef VEER\n Begin_Time = get_mcycle();\n#else\n\n#ifdef TIMES\n times (&time_info);\n Begin_Time = (long) time_info.tms_utime;\n#endif\n#ifdef TIME\n Begin_Time = time ( (long *) 0);\n#endif\n#ifdef MSC_CLOCK\n Begin_Time = clock();\n#endif\n\n#endif\n\n __asm(\"__perf_start:\");\n\n for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)\n {\n __asm(\"__loop_start:\");\n\n Proc_5();\n Proc_4();\n /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */\n Int_1_Loc = 2;\n Int_2_Loc = 3;\n strcpy (Str_2_Loc, \"DHRYSTONE PROGRAM, 2'ND STRING\");\n Enum_Loc = Ident_2;\n Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);\n /* Bool_Glob == 1 */\n while (Int_1_Loc < Int_2_Loc) /* loop body executed once */\n {\n Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;\n /* Int_3_Loc == 7 */\n Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);\n /* Int_3_Loc == 7 */\n Int_1_Loc += 1;\n } /* while */\n /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */\n Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);\n /* Int_Glob == 5 */\n Proc_1 (Ptr_Glob);\n for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)\n /* loop body executed twice */\n {\n if (Enum_Loc == Func_1 (Ch_Index, 'C'))\n /* then, not executed */\n {\n Proc_6 (Ident_1, &Enum_Loc);\n strcpy (Str_2_Loc, \"DHRYSTONE PROGRAM, 3'RD STRING\");\n Int_2_Loc = Run_Index;\n Int_Glob = Run_Index;\n }\n }\n /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */\n Int_2_Loc = Int_2_Loc * Int_1_Loc;\n Int_1_Loc = Int_2_Loc / Int_3_Loc;\n Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;\n /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */\n Proc_2 (&Int_1_Loc);\n /* Int_1_Loc == 5 */\n\n } /* loop \"for Run_Index\" */\n\n __asm(\"__perf_end:\");\n\n /**************/\n /* Stop timer */\n /**************/\n\n#ifdef VEER\n End_Time = get_mcycle();\n printf(\"End_time=%d\\n\", (int) End_Time);\n#else\n#ifdef TIMES\n times (&time_info);\n End_Time = (long) time_info.tms_utime;\n#endif\n#ifdef TIME\n End_Time = time ( (long *) 0);\n#endif\n#ifdef MSC_CLOCK\n End_Time = clock();\n#endif\n\n#endif\n\n printf (\"Final values of the variables used in the benchmark:\\n\\n\");\n printf (\"Int_Glob: %d\\n\", Int_Glob);\n printf (\" should be: %d\\n\", 5);\n printf (\"Bool_Glob: %d\\n\", Bool_Glob);\n printf (\" should be: %d\\n\", 1);\n printf (\"Ch_1_Glob: %c\\n\", Ch_1_Glob);\n printf (\" should be: %c\\n\", 'A');\n printf (\"Ch_2_Glob: %c\\n\", Ch_2_Glob);\n printf (\" should be: %c\\n\", 'B');\n printf (\"Arr_1_Glob[8]: %d\\n\", Arr_1_Glob[8]);\n printf (\" should be: %d\\n\", 7);\n printf (\"Arr_2_Glob[8][7]: %d\\n\", Arr_2_Glob[8][7]);\n printf (\" should be: Number_Of_Runs + 10\\n\");\n printf (\"Ptr_Glob->Ptr_Comp: %x\\n\", (int) Ptr_Glob->Ptr_Comp);\n printf (\" should be: (implementation-dependent)\\n\");\n printf (\" Discr: %d\\n\", Ptr_Glob->Discr);\n printf (\" should be: %d\\n\", 0);\n printf (\" Enum_Comp: %d\\n\", Ptr_Glob->variant.var_1.Enum_Comp);\n printf (\" should be: %d\\n\", 2);\n printf (\" Int_Comp: %d\\n\", Ptr_Glob->variant.var_1.Int_Comp);\n printf (\" should be: %d\\n\", 17);\n printf (\" Str_Comp: %s\", Ptr_Glob->variant.var_1.Str_Comp);\n printf (\" should be: DHRYSTONE PROGRAM, SOME STRING\\n\");\n printf (\"Next_Ptr_Glob->Ptr_Comp:%x\\n\", (int) Next_Ptr_Glob->Ptr_Comp);\n printf (\" should be: (implementation-dependent), same as above\\n\");\n printf (\" Discr: %d\\n\", Next_Ptr_Glob->Discr);\n printf (\" should be: %d\\n\", 0);\n printf (\" Enum_Comp: %d\\n\", Next_Ptr_Glob->variant.var_1.Enum_Comp);\n printf (\" should be: %d\\n\", 1);\n printf (\" Int_Comp: %d\\n\", Next_Ptr_Glob->variant.var_1.Int_Comp);\n printf (\" should be: %d\\n\", 18);\n printf (\" Str_Comp: %s\", Next_Ptr_Glob->variant.var_1.Str_Comp);\n printf (\" should be: DHRYSTONE PROGRAM, SOME STRING\\n\");\n printf (\"Int_1_Loc: %d\\n\", Int_1_Loc);\n printf (\" should be: %d\\n\", 5);\n printf (\"Int_2_Loc: %d\\n\", Int_2_Loc);\n printf (\" should be: %d\\n\", 13);\n printf (\"Int_3_Loc: %d\\n\", Int_3_Loc);\n printf (\" should be: %d\\n\", 7);\n printf (\"Enum_Loc: %d\\n\", Enum_Loc);\n printf (\" should be: %d\\n\", 1);\n printf (\"Str_1_Loc: %s\", Str_1_Loc);\n printf (\" should be: DHRYSTONE PROGRAM, 1'ST STRING\\n\");\n printf (\"Str_2_Loc: %s\", Str_2_Loc);\n printf (\" should be: DHRYSTONE PROGRAM, 2'ND STRING\\n\");\n printf (\"\\n\");\n\n User_Time = End_Time - Begin_Time;\n\n if (User_Time < Too_Small_Time)\n {\n printf (\"User time %d\\n\", User_Time);\n printf (\"Measured time too small to obtain meaningful results\\n\");\n printf (\"Please increase number of runs\\n\");\n printf (\"\\n\");\n }\n else\n {\n#ifdef VEER\n printf (\"Run time = %d clocks for %d Dhrystones\\n\", User_Time, Number_Of_Runs );\n printf (\"Dhrystones per Second per MHz: \");\n printf (\"%d.%02d\", 1000000*Number_Of_Runs/User_Time,(100000000*Number_Of_Runs/User_Time) % 100);\n#else\n#ifdef TIME\n Microseconds = (float) User_Time * Mic_secs_Per_Second\n / (float) Number_Of_Runs;\n Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time;\n#else\n Microseconds = (float) User_Time * Mic_secs_Per_Second\n / ((float) HZ * ((float) Number_Of_Runs));\n Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)\n / (float) User_Time;\n#endif\n printf (\"Microseconds for one run through Dhrystone: \");\n printf (\"%6.1f \\n\", Microseconds);\n printf (\"Dhrystones per Second: \");\n printf (\"%6.1f \\n\", Dhrystones_Per_Second);\n\n#endif\n\n printf (\"\\n\");\n }\n\n return 0;\n}\n\n\nvoid\nProc_1 (Ptr_Val_Par)\n/******************/\n\nREG Rec_Pointer Ptr_Val_Par;\n /* executed once */\n{\n REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;\n /* == Ptr_Glob_Next */\n /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */\n /* corresponds to \"rename\" in Ada, \"with\" in Pascal */\n\n structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);\n Ptr_Val_Par->variant.var_1.Int_Comp = 5;\n Next_Record->variant.var_1.Int_Comp\n = Ptr_Val_Par->variant.var_1.Int_Comp;\n Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;\n Proc_3 (&Next_Record->Ptr_Comp);\n /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp\n == Ptr_Glob->Ptr_Comp */\n if (Next_Record->Discr == Ident_1)\n /* then, executed */\n {\n Next_Record->variant.var_1.Int_Comp = 6;\n Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,\n &Next_Record->variant.var_1.Enum_Comp);\n Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;\n Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,\n &Next_Record->variant.var_1.Int_Comp);\n }\n else /* not executed */\n structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);\n} /* Proc_1 */\n\n\nvoid\nProc_2 (Int_Par_Ref)\n/******************/\n /* executed once */\n /* *Int_Par_Ref == 1, becomes 4 */\n\nOne_Fifty *Int_Par_Ref;\n{\n One_Fifty Int_Loc;\n Enumeration Enum_Loc;\n\n Int_Loc = *Int_Par_Ref + 10;\n do /* executed once */\n if (Ch_1_Glob == 'A')\n /* then, executed */\n {\n Int_Loc -= 1;\n *Int_Par_Ref = Int_Loc - Int_Glob;\n Enum_Loc = Ident_1;\n } /* if */\n while (Enum_Loc != Ident_1); /* true */\n} /* Proc_2 */\n\n\nvoid\nProc_3 (Ptr_Ref_Par)\n/******************/\n /* executed once */\n /* Ptr_Ref_Par becomes Ptr_Glob */\n\nRec_Pointer *Ptr_Ref_Par;\n\n{\n if (Ptr_Glob != Null)\n /* then, executed */\n *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;\n Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);\n} /* Proc_3 */\n\n\nvoid\nProc_4 () /* without parameters */\n/*******/\n /* executed once */\n{\n Boolean Bool_Loc;\n\n Bool_Loc = Ch_1_Glob == 'A';\n Bool_Glob = Bool_Loc | Bool_Glob;\n Ch_2_Glob = 'B';\n} /* Proc_4 */\n\n\nvoid\nProc_5 () /* without parameters */\n/*******/\n /* executed once */\n{\n Ch_1_Glob = 'A';\n Bool_Glob = false;\n} /* Proc_5 */\n\n\n /* Procedure for the assignment of structures, */\n /* if the C compiler doesn't support this feature */\n#ifdef NOSTRUCTASSIGN\nmemcpy (d, s, l)\nregister char *d;\nregister char *s;\nregister int l;\n{\n while (l--) *d++ = *s++;\n}\n#endif\n\n\n" }, { "path": "testbench/tests/dhry/dhry_2.c", "content": "/*\n ****************************************************************************\n *\n * \"DHRYSTONE\" Benchmark Program\n * -----------------------------\n *\n * Version: C, Version 2.1\n *\n * File: dhry_2.c (part 3 of 3)\n *\n * Date: May 25, 1988\n *\n * Author: Reinhold P. Weicker\n *\n ****************************************************************************\n */\n\n#include \"dhry.h\"\n\n#ifndef REG\n#define REG\n /* REG becomes defined as empty */\n /* i.e. no register variables */\n#endif\n\nextern int Int_Glob;\nextern char Ch_1_Glob;\n\n#if 0\nint\nstrcmp(const char* s1, const char* s2)\n{\n while (*s1 && *s1 == *s2)\n {\n s1++;\n s2++;\n }\n if (*s1 == *s2)\n return 0;\n return *s1 > *s2? 1 : -1;\n}\n#else\nextern int strcmp( char* s1, char* s2);\n#endif\n\nBoolean Func_3 (Enumeration Enum_Par_Val);\n\n\nvoid\nProc_6 (Enum_Val_Par, Enum_Ref_Par)\n/*********************************/\n /* executed once */\n /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */\n\nEnumeration Enum_Val_Par;\nEnumeration *Enum_Ref_Par;\n{\n *Enum_Ref_Par = Enum_Val_Par;\n if (! Func_3 (Enum_Val_Par))\n /* then, not executed */\n *Enum_Ref_Par = Ident_4;\n switch (Enum_Val_Par)\n {\n case Ident_1:\n *Enum_Ref_Par = Ident_1;\n break;\n case Ident_2:\n if (Int_Glob > 100)\n /* then */\n *Enum_Ref_Par = Ident_1;\n else *Enum_Ref_Par = Ident_4;\n break;\n case Ident_3: /* executed */\n *Enum_Ref_Par = Ident_2;\n break;\n case Ident_4: break;\n case Ident_5:\n *Enum_Ref_Par = Ident_3;\n break;\n } /* switch */\n} /* Proc_6 */\n\n\nvoid\nProc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)\n/**********************************************/\n /* executed three times */\n /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */\n /* Int_Par_Ref becomes 7 */\n /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */\n /* Int_Par_Ref becomes 17 */\n /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */\n /* Int_Par_Ref becomes 18 */\nOne_Fifty Int_1_Par_Val;\nOne_Fifty Int_2_Par_Val;\nOne_Fifty *Int_Par_Ref;\n{\n One_Fifty Int_Loc;\n\n Int_Loc = Int_1_Par_Val + 2;\n *Int_Par_Ref = Int_2_Par_Val + Int_Loc;\n} /* Proc_7 */\n\n\nvoid\nProc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)\n/*********************************************************************/\n /* executed once */\n /* Int_Par_Val_1 == 3 */\n /* Int_Par_Val_2 == 7 */\nArr_1_Dim Arr_1_Par_Ref;\nArr_2_Dim Arr_2_Par_Ref;\nint Int_1_Par_Val;\nint Int_2_Par_Val;\n{\n REG One_Fifty Int_Index;\n REG One_Fifty Int_Loc;\n\n Int_Loc = Int_1_Par_Val + 5;\n Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;\n Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];\n Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;\n for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)\n Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;\n Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;\n Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];\n Int_Glob = 5;\n} /* Proc_8 */\n\n\nEnumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)\n/*************************************************/\n /* executed three times */\n /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */\n /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */\n /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */\n\nCapital_Letter Ch_1_Par_Val;\nCapital_Letter Ch_2_Par_Val;\n{\n Capital_Letter Ch_1_Loc;\n Capital_Letter Ch_2_Loc;\n\n Ch_1_Loc = Ch_1_Par_Val;\n Ch_2_Loc = Ch_1_Loc;\n if (Ch_2_Loc != Ch_2_Par_Val)\n /* then, executed */\n return (Ident_1);\n else /* not executed */\n {\n Ch_1_Glob = Ch_1_Loc;\n return (Ident_2);\n }\n} /* Func_1 */\n\n\nBoolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)\n/*************************************************/\n /* executed once */\n /* Str_1_Par_Ref == \"DHRYSTONE PROGRAM, 1'ST STRING\" */\n /* Str_2_Par_Ref == \"DHRYSTONE PROGRAM, 2'ND STRING\" */\n\nStr_30 Str_1_Par_Ref;\nStr_30 Str_2_Par_Ref;\n{\n REG One_Thirty Int_Loc;\n Capital_Letter Ch_Loc;\n\n Int_Loc = 2;\n while (Int_Loc <= 2) /* loop body executed once */\n if (Func_1 (Str_1_Par_Ref[Int_Loc],\n Str_2_Par_Ref[Int_Loc+1]) == Ident_1)\n /* then, executed */\n {\n Ch_Loc = 'A';\n Int_Loc += 1;\n } /* if, while */\n if (Ch_Loc >= 'W' && Ch_Loc < 'Z')\n /* then, not executed */\n Int_Loc = 7;\n if (Ch_Loc == 'R')\n /* then, not executed */\n return (true);\n else /* executed */\n {\n if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)\n /* then, not executed */\n {\n Int_Loc += 7;\n Int_Glob = Int_Loc;\n return (true);\n }\n else /* executed */\n return (false);\n } /* if Ch_Loc */\n} /* Func_2 */\n\n\nBoolean Func_3 (Enum_Par_Val)\n/***************************/\n /* executed once */\n /* Enum_Par_Val == Ident_3 */\nEnumeration Enum_Par_Val;\n{\n Enumeration Enum_Loc;\n\n Enum_Loc = Enum_Par_Val;\n if (Enum_Loc == Ident_3)\n /* then, executed */\n return (true);\n else /* not executed */\n return (false);\n} /* Func_3 */\n\n" }, { "path": "testbench/tests/ecc/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n#include \"defines.h\"\n\n.section .text.init\n.global _start\n_start:\n // enable caching, except region 0xd\n li t0, 0x59555555\n csrw 0x7c0, t0\n\n la sp, STACK\n\n la t0, _trap_handler\n csrw mtvec, t0\n\n call main\n\n.global _finish\n_finish:\n la t0, tohost\n li t1, 0xff\n sb t1, 0(t0) // DemoTB test termination\n li t1, 1\n sw t1, 0(t0) // Whisper test termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.global _trap_handler\n_trap_handler:\n call trap_handler\n j _start\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/tests/ecc/ecc.c", "content": "/* SPDX-License-Identifier: Apache-2.0\n * Copyright 2024 Antmicro \n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \n#include \n\n#define STDOUT 0xd0580000\nvolatile char* stdout = (char *)STDOUT;\n\n#define MFDC_DISABLE_ECC_MASK 0x100\n#define INJECT_ICCM_SINGLE_BIT 0xe0\n#define INJECT_ICCM_DOUBLE_BIT 0xe1\n#define INJECT_DCCM_SINGLE_BIT 0xe2\n#define INJECT_DCCM_DOUBLE_BIT 0xe3\n#define DISABLE_ERROR_INJECTION 0xe4\n#define TEST_PASSED 0xff\n#define TEST_FAILED 0x01\n\n\n#define ICCM_SADDR 0xee000000\n#define DCCM_SADDR 0xf0040000\n\nvoid execute_from_iccm (void) __attribute__ ((aligned(4),section(\".iccm_data0\")));\nvolatile uint32_t boot_count __attribute__((section(\".dccm.persistent\"))) = 0;\nuint32_t dccm_test, iccm_test;\nextern const int ICCM_ADDR, DCCM_ADDR;\nextern uintptr_t iccm_start, iccm_end;\nextern int printf(const char* format, ...);\nextern int putchar(int c);\n\n\nvoid sleep(uint32_t count) {\n for (uint32_t slp = 0; slp < count; slp++) {\n __asm__ volatile (\"nop\"); // Sleep loop as \"nop\"\n }\n}\n\nint read_mcause(void) {\n uint32_t mcause;\n\n __asm__ volatile (\"csrr %0, %1\"\n : \"=r\" (mcause) /* output: variable */\n : \"i\" (0x342) /* input : immediate */\n : /* clobbers: none */);\n\n return mcause;\n}\n\nint read_mscause(void) {\n uint32_t mscause;\n\n __asm__ volatile (\"csrr %0, %1\"\n : \"=r\" (mscause) /* output: variable */\n : \"i\" (0x7FF) /* input : immediate */\n : /* clobbers: none */);\n\n return mscause;\n}\n\nint read_mfdc(void) {\n uint32_t mfdc;\n\n __asm__ volatile (\"csrr %0, %1\"\n : \"=r\" (mfdc) /* output: variable */\n : \"i\" (0x7F9) /* input : immediate */\n : /* clobbers: none */);\n\n return mfdc;\n}\n\nint read_mdccmect(void) {\n uint32_t mdccmect;\n\n __asm__ volatile (\"csrr %0, %1\"\n : \"=r\" (mdccmect) /* output: variable */\n : \"i\" (0x7F2) /* input : immediate */\n : /* clobbers: none */);\n\n return mdccmect;\n}\n\nint read_miccmect(void) {\n uint32_t miccmect;\n\n __asm__ volatile (\"csrr %0, %1\"\n : \"=r\" (miccmect) /* output: variable */\n : \"i\" (0x7F1) /* input : immediate */\n : /* clobbers: none */);\n\n return miccmect;\n}\n\nvoid clear_causes(void) {\n __asm__ volatile (\"csrw %0, %1\"\n : /* output: none */\n : \"i\" (0x342), \"i\" (0) /* input : immediate */\n : /* clobbers: none */);\n __asm__ volatile (\"csrw %0, %1\"\n : /* output: none */\n : \"i\" (0x7FF), \"i\" (0) /* input : immediate */\n : /* clobbers: none */);\n}\n\nvoid disable_ecc_check(void) {\n uint32_t mfdc_disable_ecc_mask = MFDC_DISABLE_ECC_MASK;\n\n __asm__ volatile (\"csrs %0, %1\"\n : /* output: none */\n : \"i\" (0x7F9), \"r\" (mfdc_disable_ecc_mask) /* input : immediate */\n : /* clobbers: none */);\n}\n\nvoid enable_ecc_check(void) {\n uint32_t mfdc_disable_ecc_mask = MFDC_DISABLE_ECC_MASK;\n\n __asm__ volatile (\"csrc %0, %1\"\n : /* output: none */\n : \"i\" (0x7F9), \"r\" (mfdc_disable_ecc_mask) /* input : immediate */\n : /* clobbers: none */);\n}\n\nvoid trap_handler(void) {\n uint32_t mcause, mscause, mfdc;\n\n mfdc = read_mfdc();\n\n if (mfdc & MFDC_DISABLE_ECC_MASK) {\n printf(\"Trap hit while ECC check is disabled!\\n\");\n putchar(TEST_FAILED);\n }\n\n mcause = read_mcause();\n mscause = read_mscause();\n clear_causes();\n\n if (((mcause == 0x5 && mscause == 0x1) ||\n (mcause == 0x7 && mscause == 0x1)) &&\n dccm_test == 1) {\n printf(\"DCCM double bit error\\n\");\n putchar(DISABLE_ERROR_INJECTION);\n } else if (mcause == 0x1 && mscause == 0x1 && iccm_test == 1) {\n printf(\"ICCM double bit error\\n\");\n putchar(DISABLE_ERROR_INJECTION);\n } else {\n printf(\"Error unrelated to ECC\\n\");\n putchar(TEST_FAILED);\n }\n}\n\nvoid run_iccm_err_test(int execute) {\n uint32_t *iccm_data = (uint32_t *)ICCM_SADDR;\n uint32_t *iccm = iccm_data;\n void (* iccm_fn) (void) = (void*)iccm_data;\n uint32_t *code_word = 0;\n uint32_t *actual_iccm_code_end = 0;\n uint32_t mfdc, miccmect;\n\n // Inject single bit ICCM error\n putchar(INJECT_ICCM_SINGLE_BIT);\n\n code_word = (uint32_t *) &iccm_start;\n printf(\"Copy code from %x [thru %x] to %x\\n\", (uintptr_t) code_word, &iccm_end, (uintptr_t) iccm);\n while (code_word < (uint32_t *) &iccm_end) {\n printf(\"at %x: %x\\n\", (uintptr_t) code_word, *code_word);\n *iccm++ = *code_word++;\n }\n putchar(DISABLE_ERROR_INJECTION);\n if (execute) {\n iccm_fn();\n }\n\n mfdc = read_mfdc();\n miccmect = read_miccmect();\n\n if ((mfdc & MFDC_DISABLE_ECC_MASK) && (miccmect != 0)) {\n printf(\"Unexpected ECC single-bit error detected!\\n\");\n putchar(TEST_FAILED);\n } else if (!(mfdc & MFDC_DISABLE_ECC_MASK) && (miccmect == 0)) {\n printf(\"Did not register expected ECC single-bit error!\\n\");\n putchar(TEST_FAILED);\n }\n\n // Inject double bit ICCM error\n putchar(INJECT_ICCM_DOUBLE_BIT);\n\n code_word = (uint32_t *) &iccm_start;\n iccm = iccm_data;\n printf(\"Copy code from %x [thru %x] to %x\\n\", (uintptr_t) code_word, &iccm_end, (uintptr_t) iccm);\n while (code_word < (uint32_t *) &iccm_end) {\n printf(\"at %x: %x\\n\", (uintptr_t) code_word, *code_word);\n *iccm++ = *code_word++;\n }\n putchar(DISABLE_ERROR_INJECTION);\n if (execute) {\n iccm_fn();\n }\n}\n\nvoid run_dccm_err_test(void) {\n uint32_t *dccm_data = (uint32_t *)DCCM_SADDR;\n uint32_t *dccm = dccm_data;\n uint32_t mfdc, mdccmect;\n\n // Inject single bit DCCM error\n putchar(INJECT_DCCM_SINGLE_BIT);\n *dccm = 0x12345678;\n putchar(DISABLE_ERROR_INJECTION);\n printf(\"DCCM value: 0x%x\\n\", *dccm);\n\n mfdc = read_mfdc();\n mdccmect = read_mdccmect();\n\n if ((mfdc & MFDC_DISABLE_ECC_MASK) && (mdccmect != 0)) {\n printf(\"Unexpected ECC single-bit error detected!\\n\");\n putchar(TEST_FAILED);\n } else if (!(mfdc & MFDC_DISABLE_ECC_MASK) && (mdccmect == 0)) {\n printf(\"Did not register expected ECC single-bit error!\\n\");\n putchar(TEST_FAILED);\n }\n\n // Inject double bit DCCM error\n putchar(INJECT_DCCM_DOUBLE_BIT);\n *dccm = 0xDEADBEEF;\n putchar(DISABLE_ERROR_INJECTION);\n printf(\"DCCM value: 0x%x\\n\", *dccm);\n}\n\nvoid execute_from_iccm (void) {\n printf(\"Executed from ICCM!\\n\");\n}\n\nvoid main(void)\n{\n boot_count++;\n\n printf(\"------------------------\\n\");\n printf(\"Test ECC error injection\\n\");\n printf(\"------------------------\\n\\n\");\n\n printf(\"Boot count: %d\\n\", boot_count);\n\n if (boot_count == 1) {\n iccm_test = 0;\n dccm_test = 1;\n\n printf(\"Disable ECC checks\\n\\n\");\n disable_ecc_check();\n\n run_dccm_err_test();\n\n printf(\"\\nEnable ECC checks\\n\\n\");\n enable_ecc_check();\n\n run_dccm_err_test();\n\n // Should not reach here if ECC error is triggerred correctly\n\n printf(\"Did not hit ECC error when expected!\\n\");\n putchar(TEST_FAILED);\n } else if (boot_count == 2) {\n iccm_test = 1;\n dccm_test = 0;\n\n printf(\"Disable ECC checks\\n\\n\");\n disable_ecc_check();\n\n // Inject errors without executing due to disabled error correction\n run_iccm_err_test(0);\n\n printf(\"\\nEnable ECC checks\\n\\n\");\n enable_ecc_check();\n\n run_iccm_err_test(1);\n\n // Should not reach here if ECC error is triggerred correctly\n\n printf(\"Did not hit ECC error when expected!\\n\");\n putchar(TEST_FAILED);\n } else if (boot_count == 3) {\n printf(\"Finished\\n\");\n } else {\n printf(\"Unexpected reset\\n\");\n putchar(TEST_FAILED);\n }\n}\n" }, { "path": "testbench/tests/ecc/ecc.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS\n{\n . = 0x80000000;\n .text : { *(.text*) }\n _end = .;\n\n /* STDOUT */\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n\n /* DCCM */\n . = 0xf0040000;\n dccm = .;\n .data : { *(.*data) *(.rodata*) *(.sbss)}\n .bss : { *(.bss); . = ALIGN(4); }\n STACK = ALIGN(16) + 0x1000;\n\n /* ICCM */\n iccm_start = .;\n .iccm_data0 0xee000000 : AT(iccm_start) {\n KEEP(*(.iccm_data0));\n . = ALIGN(4);\n } = 0x0000,\n iccm_end = iccm_start + SIZEOF(.iccm_data0);\n\n . = 0xfffffff8;\n .data.ctl : AT(0xfffffff8) { LONG(0xf0040000); LONG(STACK) }\n}\n" }, { "path": "testbench/tests/ecc/ecc.mki", "content": "OFILES = crt0.o ecc.o printf.o\nTEST_CFLAGS = -g -O3\n" }, { "path": "testbench/tests/insns/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.section .text.init\n.global _start\n_start:\n\n # Setup stack\n la sp, STACK\n\n # Setup trap handler\n la t0, _trap\n csrw mtvec, t0\n\n # Setup PMP\n # Region 0 TOR 0x00000000-0xFFFFFFFF RWX\n li t0, 0xFFFFFFFF\n csrw pmpaddr0, t0\n li t0, 0x0000000F\n csrw pmpcfg0, t0\n\n # Call main()\n call main\n\n # Map exit code: == 0 - success, != 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n_trap:\n\n # Push stuff\n addi sp, sp, -17*4\n\n sw ra, 0*4(sp)\n sw a0, 1*4(sp)\n sw a1, 2*4(sp)\n sw a2, 3*4(sp)\n sw a3, 4*4(sp)\n sw a4, 5*4(sp)\n sw a5, 6*4(sp)\n sw a6, 7*4(sp)\n sw a7, 8*4(sp)\n sw t0, 9*4(sp)\n sw t1, 10*4(sp)\n sw t2, 11*4(sp)\n sw t3, 12*4(sp)\n sw t4, 13*4(sp)\n sw t5, 14*4(sp)\n sw t6, 15*4(sp)\n\n call trap_handler\n\n # Advance mepc if the cause is not an external interrupt\n csrr t0, mcause\n li t1, 0x80000000\n and t0, t0, t1\n bne t0, x0, _is_irq\n\n csrr t0, mepc\n addi t0, t0, 4\n csrw mepc, t0\n\n_is_irq:\n\n # Pop stuff\n lw ra, 0*4(sp)\n lw a0, 1*4(sp)\n lw a1, 2*4(sp)\n lw a2, 3*4(sp)\n lw a3, 4*4(sp)\n lw a4, 5*4(sp)\n lw a5, 6*4(sp)\n lw a6, 7*4(sp)\n lw a7, 8*4(sp)\n lw t0, 9*4(sp)\n lw t1, 10*4(sp)\n lw t2, 11*4(sp)\n lw t3, 12*4(sp)\n lw t4, 13*4(sp)\n lw t5, 14*4(sp)\n lw t6, 15*4(sp)\n\n addi sp, sp, 17*4\n\n mret\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/tests/insns/insns.c", "content": "#include \n\n#define read_csr(csr) ({ \\\n unsigned long res; \\\n asm volatile (\"csrr %0, \" #csr : \"=r\"(res)); \\\n res; \\\n})\n\n#define write_csr(csr, val) { \\\n asm volatile (\"csrw \" #csr \", %0\" : : \"r\"(val)); \\\n}\n\n#define MISA_U (1 << 20)\n\n#define do_ecall() asm volatile (\"ecall\")\n#define do_ebreak() asm volatile (\"ebreak\\nnop\") // EBREAK can translate to C.EBREAK. Insert a nop to align to 4\n#define do_wfi() asm volatile (\"wfi\")\n#define do_sret() asm volatile (\"sret\")\n#define do_mret() asm volatile (\"mret\")\n\n#define is_ecall(x) ((x) == 0x00000073)\n#define is_ebreak(x) ((x) == 0x00100073 || ((x) & 0xFFFF) == 0x9002) // EBREAK or C.EBREAK\n#define is_wfi(x) ((x) == 0x10500073)\n#define is_sret(x) ((x) == 0x10200073)\n#define is_mret(x) ((x) == 0x30200073)\n\nstruct trap_info_t {\n uint32_t mcause;\n uint32_t insn;\n};\n\nvolatile struct trap_info_t trap_info;\n\nvoid trap_handler () {\n\n uint32_t mstatus = read_csr(mstatus);\n uint32_t mepc = read_csr(mepc);\n\n trap_info.mcause = read_csr(mcause);\n trap_info.insn = *((uint32_t*)mepc);\n\n printf(\"trap! mstatus=0x%08X, mcause=0x%08X, mepc=0x%08X, insn=0x%08X\\n\",\n mstatus, trap_info.mcause, mepc, trap_info.insn);\n}\n\nvoid clear_trap () {\n trap_info.mcause = 0x00;\n trap_info.insn = 0x00;\n}\n\nvolatile int global_result = 1; // Success\n\nvoid check (int cond) {\n if (cond) {\n printf(\"pass\\n\");\n } else {\n printf(\"fail\\n\");\n global_result = 0;\n }\n}\n\nvoid user_main ();\n\nint main () {\n printf(\"Hello VeeR\\n\");\n\n // The test requires user mode support\n if ((read_csr(misa) & MISA_U) == 0) {\n printf(\"ERROR: The test requires user mode support. Aborting.\\n\");\n return -1;\n }\n\n // Do EBREAK\n printf(\"testing EBREAK\\n\");\n clear_trap();\n do_ebreak();\n check(trap_info.mcause == 0x3 && is_ebreak(trap_info.insn));\n\n // Do ECALL\n printf(\"testing ECALL\\n\");\n clear_trap();\n do_ecall();\n check(trap_info.mcause == 0xb && is_ecall(trap_info.insn));\n\n // Do WFI\n printf(\"testing WFI\\n\");\n clear_trap();\n do_wfi();\n check(!trap_info.mcause); // No trap expected\n\n // Do SRET\n printf(\"testing SRET\\n\");\n clear_trap();\n do_sret();\n check(trap_info.mcause == 0x2 && is_sret(trap_info.insn));\n\n // Do not test MRET here. It is going to be used to go to user mode later\n // anyways.\n\n // Go to user mode\n unsigned long mstatus = read_csr(mstatus);\n mstatus &= ~(3 << 11); // MPP = 00 (user)\n mstatus &= ~(1 << 17); // MPRV = 0\n write_csr(mstatus, mstatus);\n\n void* ptr = (void*)user_main;\n write_csr(mepc, (unsigned long)ptr);\n asm volatile (\"mret\");\n\n return 0;\n}\n\n__attribute__((noreturn)) void user_main () {\n printf(\"Hello from user_main()\\n\");\n\n // Do EBREAK\n printf(\"testing EBREAK\\n\");\n clear_trap();\n do_ebreak();\n check(trap_info.mcause == 0x3 && is_ebreak(trap_info.insn));\n\n // Do ECALL\n printf(\"testing ECALL\\n\");\n clear_trap();\n do_ecall();\n check(trap_info.mcause == 0x8 && is_ecall(trap_info.insn));\n\n // Do WFI\n printf(\"testing WFI\\n\");\n clear_trap();\n do_wfi();\n check(!trap_info.mcause); // No trap expected\n\n // Do SRET\n printf(\"testing SRET\\n\");\n clear_trap();\n do_sret();\n check(trap_info.mcause == 0x2 && is_sret(trap_info.insn));\n\n // Do MRET\n printf(\"testing MRET\\n\");\n clear_trap();\n do_mret();\n check(trap_info.mcause == 0x2 && is_mret(trap_info.insn));\n\n // Terminate the simulation\n // set the exit code to 0xFF or 0x1 and jump to _finish.\n unsigned char res = (global_result) ? 0xFF : 1;\n asm volatile (\n \"mv a0, %0\\n\"\n \"j _finish\\n\"\n : : \"r\"(res)\n );\n\n while (1); // Make compiler not complain\n}\n" }, { "path": "testbench/tests/insns/insns.ld", "content": "/* SPDX-License-Identifier: Apache-2.0 */\n\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text.init*) *(.text*) }\n _end = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n}\n" }, { "path": "testbench/tests/insns/insns.mki", "content": "# SPDX-License-Identifier: Apache-2.0\n\nOFILES = crt0.o insns.o printf.o\nTEST_CFLAGS = -g -O3 -falign-functions=16\n" }, { "path": "testbench/tests/irq/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.option norvc\n.option nopic\n\n.section .text.init\n.align 4\n.global _start\n_start:\n\n # Setup stack\n la sp, STACK\n\n # Setup trap handler\n la t0, _trap\n csrw mtvec, t0\n\n # Setup PMP\n # Region 0 TOR 0x00000000-0xFFFFFFFF RWX\n li t0, 0xFFFFFFFF\n csrw pmpaddr0, t0\n li t0, 0x0000000F\n csrw pmpcfg0, t0\n\n # Call main()\n call main\n\n # Map exit code: == 0 - success, != 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.align 4\n_trap:\n\n # Push stuff\n addi sp, sp, -17*4\n\n sw ra, 0*4(sp)\n sw a0, 1*4(sp)\n sw a1, 2*4(sp)\n sw a2, 3*4(sp)\n sw a3, 4*4(sp)\n sw a4, 5*4(sp)\n sw a5, 6*4(sp)\n sw a6, 7*4(sp)\n sw a7, 8*4(sp)\n sw t0, 9*4(sp)\n sw t1, 10*4(sp)\n sw t2, 11*4(sp)\n sw t3, 12*4(sp)\n sw t4, 13*4(sp)\n sw t5, 14*4(sp)\n sw t6, 15*4(sp)\n\n call trap_handler\n\n # Advance mepc if the cause is not an external interrupt\n csrr t0, mcause\n li t1, 0x80000000\n and t0, t0, t1\n bne t0, x0, _is_irq\n\n csrr t0, mepc\n addi t0, t0, 4\n csrw mepc, t0\n\n_is_irq:\n\n # Pop stuff\n lw ra, 0*4(sp)\n lw a0, 1*4(sp)\n lw a1, 2*4(sp)\n lw a2, 3*4(sp)\n lw a3, 4*4(sp)\n lw a4, 5*4(sp)\n lw a5, 6*4(sp)\n lw a6, 7*4(sp)\n lw a7, 8*4(sp)\n lw t0, 9*4(sp)\n lw t1, 10*4(sp)\n lw t2, 11*4(sp)\n lw t3, 12*4(sp)\n lw t4, 13*4(sp)\n lw t5, 14*4(sp)\n lw t6, 15*4(sp)\n\n addi sp, sp, 17*4\n\n mret\n\n.section .text.nmi\n.align 4\n_nmi:\n\n # Push stuff\n addi sp, sp, -17*4\n\n sw ra, 0(sp)\n sw a0, 1*4(sp)\n sw a1, 2*4(sp)\n sw a2, 3*4(sp)\n sw a3, 4*4(sp)\n sw a4, 5*4(sp)\n sw a5, 6*4(sp)\n sw a6, 7*4(sp)\n sw a7, 8*4(sp)\n sw t0, 9*4(sp)\n sw t1, 10*4(sp)\n sw t2, 11*4(sp)\n sw t3, 12*4(sp)\n sw t4, 13*4(sp)\n sw t5, 14*4(sp)\n sw t6, 15*4(sp)\n\n call nmi_handler\n\n # Pop stuff\n lw ra, 0*4(sp)\n lw a0, 1*4(sp)\n lw a1, 2*4(sp)\n lw a2, 3*4(sp)\n lw a3, 4*4(sp)\n lw a4, 5*4(sp)\n lw a5, 6*4(sp)\n lw a6, 7*4(sp)\n lw a7, 8*4(sp)\n lw t0, 9*4(sp)\n lw t1, 10*4(sp)\n lw t2, 11*4(sp)\n lw t3, 12*4(sp)\n lw t4, 13*4(sp)\n lw t5, 14*4(sp)\n lw t6, 15*4(sp)\n\n addi sp, sp, 17*4\n\n mret\n\n.section .data.io\n.global tohost\ntohost: .word 0\n" }, { "path": "testbench/tests/irq/irq.c", "content": "#include \n#include \n\n// ============================================================================\n\n#define read_csr(csr) ({ \\\n unsigned long res; \\\n asm volatile (\"csrr %0, \" #csr : \"=r\"(res)); \\\n res; \\\n})\n\n#define write_csr(csr, val) { \\\n asm volatile (\"csrw \" #csr \", %0\" : : \"r\"(val)); \\\n}\n\n#define MISA_U (1 << 20)\n\n#define MSTATUS_MPP_MASK (3 << 11)\n#define MSTATUS_MPP_MACHINE (3 << 11)\n#define MSTATUS_MPP_USER (0 << 11)\n#define MSTATUS_MPP_MPRV (1 << 17)\n#define MSTATUS_MIE (1 << 3)\n#define MSTATUS_MPIE (1 << 7)\n\n#define MIE_MEIE (1 << 11)\n#define MIE_MTIE (1 << 7)\n#define MIE_MSIE (1 << 3)\n\n#define MCAUSE_NMI 0x0\n#define MCAUSE_TIMER_M 0x80000007\n#define MCAUSE_SOFTINT_M 0x80000003\n\n#define TEST_RESULT_SUCCESS 0xFF\n#define TEST_RESULT_FAILURE 1\n\n// ============================================================================\n\n#define CMD_EXT_IRQ_CLR 0x80\n#define CMD_EXT_IRQ_SET 0x81\n#define CMD_CORE_IRQ_CLR 0x82\n#define CMD_CORE_IRQ_SET 0x83\n#define CMD_IRQ_CLR_ALL 0x90\n\n#define CORE_IRQ_NMI (1 << 8)\n#define CORE_IRQ_TIMER (2 << 8)\n#define CORE_IRQ_SOFT (4 << 8)\n\nextern uint32_t tohost;\n\nvoid trigger_nmi_irq (int state) {\n uint32_t cmd = (state) ? CMD_CORE_IRQ_SET : CMD_CORE_IRQ_CLR;\n tohost = cmd | CORE_IRQ_NMI;\n}\n\nvoid trigger_timer_irq (int state) {\n uint32_t cmd = (state) ? CMD_CORE_IRQ_SET : CMD_CORE_IRQ_CLR;\n tohost = cmd | CORE_IRQ_TIMER;\n}\n\nvoid trigger_soft_irq (int state) {\n uint32_t cmd = (state) ? CMD_CORE_IRQ_SET : CMD_CORE_IRQ_CLR;\n tohost = cmd | CORE_IRQ_SOFT;\n}\n\nvoid trigger_ext_irq (int state, int irq) {\n uint32_t cmd = (state) ? CMD_EXT_IRQ_SET : CMD_EXT_IRQ_CLR;\n tohost = cmd | (irq << 8);\n}\n\nvoid release_all_irqs () {\n tohost = CMD_IRQ_CLR_ALL;\n}\n\n// ============================================================================\n\nstruct trap_data_t {\n uint32_t mcause;\n uint32_t mstatus;\n};\n\nvolatile struct trap_data_t trap_data[32];\nvolatile uint32_t trap_count = 0;\n\nvoid trap_handler () {\n\n uint32_t mstatus = read_csr(mstatus);\n uint32_t mcause = read_csr(mcause);\n uint32_t mepc = read_csr(mepc);\n\n // Release interrupt lines\n release_all_irqs();\n\n printf(\"trap! mstatus=0x%08X, mcause=0x%08X, mepc=0x%08X\\n\", mstatus, mcause, mepc);\n\n // Store trap data\n if (trap_count < (sizeof(trap_data) / sizeof(trap_data[0]))) {\n trap_data[trap_count].mcause = mcause;\n trap_data[trap_count].mstatus = mstatus;\n trap_count++;\n }\n}\n\nvoid nmi_handler () {\n // Handle NMIs as regular traps. For purpose of this test it is sufficient\n trap_handler();\n}\n\n// ============================================================================\n\nvoid user_main ();\n\nint main () {\n printf(\"Hello VeeR\\n\");\n\n // Enable interrupts\n unsigned long mie = read_csr(mie);\n mie |= MIE_MEIE | MIE_MTIE | MIE_MSIE;\n write_csr(mie, mie);\n\n // ..............................\n // Set mstatus.MIE to 0. This should disable interrupts in M mode\n printf(\"Machine mode, MIE=0\\n\");\n\n unsigned long mstatus = read_csr(mstatus);\n mstatus &= ~MSTATUS_MIE;\n write_csr(mstatus, mstatus);\n\n // NMI\n trigger_nmi_irq(1);\n printf(\" NMI triggered\\n\");\n\n // Timer IRQ\n trigger_timer_irq(1);\n printf(\" timer irq triggered\\n\");\n\n // Soft IRQ\n trigger_soft_irq(1);\n printf(\" soft IRQ triggered\\n\");\n\n // No exceptions should have occurred\n // Release interrupt lines\n release_all_irqs();\n\n // ..............................\n // Set mstatus.MIE to 1. This should enable interrupts in M mode\n printf(\"Machine mode, MIE=1\\n\");\n\n mstatus = read_csr(mstatus);\n mstatus |= MSTATUS_MIE;\n write_csr(mstatus, mstatus);\n\n // NMI\n trigger_nmi_irq(1);\n printf(\" NMI triggered\\n\");\n\n // Timer IRQ\n trigger_timer_irq(1);\n printf(\" timer irq triggered\\n\");\n\n // Soft IRQ\n trigger_soft_irq(1);\n printf(\" soft IRQ triggered\\n\");\n\n // Exceptions should have occurred and got recorded.\n // Release interrupt lines\n release_all_irqs();\n\n // ..............................\n // User mode not supported\n if ((read_csr(misa) & MISA_U) == 0) {\n printf(\"WARNING: User mode not supported\\n\");\n\n // Report traps\n printf(\"traps taken: %d\\n\", trap_count);\n for (unsigned long i=0; i\n#include \n\n#define read_csr(csr) ({ \\\n unsigned long res; \\\n asm volatile (\"csrr %0, \" #csr : \"=r\"(res)); \\\n res; \\\n})\n\n#define write_csr(csr, val) { \\\n asm volatile (\"csrw \" #csr \", %0\" : : \"r\"(val)); \\\n}\n\n#define MISA_U (1 << 20)\n\n#define MSTATUS_MPRV (1 << 17)\n\n#define MSTATUS_MPP_MASK (3 << 11)\n#define MSTATUS_MPP_MACHINE (3 << 11)\n#define MSTATUS_MPP_USER (0 << 11)\n\n#define MCAUSE_ECALL_U 0x8\n#define MCAUSE_ECALL_M 0xb\n\nextern int32_t do_ecall (uint32_t cmd, uint32_t arg);\n\n#define ECALL_HELLO 0x10\n#define ECALL_CLR_MPRV 0x20\n#define ECALL_SET_MPRV 0x21\n#define ECALL_GET_MSTATUS 0x30\n\nstruct trap_data_t {\n uint32_t mcause;\n uint32_t mstatus;\n};\n\nstruct trap_data_t trap_data[32];\nuint32_t trap_count = 0;\n\nvolatile int32_t global_fail = 0;\n\nint32_t trap_handler (uint32_t cmd, uint32_t arg) {\n\n unsigned long mstatus = read_csr(mstatus);\n unsigned long mcause = read_csr(mcause);\n unsigned long mepc = read_csr(mepc);\n\n // Store trap data\n if (trap_count < (sizeof(trap_data) / sizeof(trap_data[0]))) {\n trap_data[trap_count].mcause = mcause;\n trap_data[trap_count].mstatus = mstatus;\n trap_count++;\n }\n\n printf(\"trap! mstatus=0x%08X, mcause=0x%08X, mepc=0x%08X\\n\", mstatus, mcause, mepc);\n\n // Handle ecall\n if (mcause == MCAUSE_ECALL_U || mcause == MCAUSE_ECALL_M) {\n printf(\"Hello ECALL.%c\\n\", (mcause == MCAUSE_ECALL_U) ? 'U' :\n (mcause == MCAUSE_ECALL_M) ? 'M' : '?');\n if (cmd == ECALL_HELLO) {\n return 0;\n }\n if (cmd == ECALL_CLR_MPRV) {\n printf(\" clearing mstatus.MPRV\\n\");\n mstatus &= ~MSTATUS_MPRV;\n write_csr(mstatus, mstatus);\n return mstatus;\n }\n if (cmd == ECALL_SET_MPRV) {\n printf(\" setting mstatus.MPRV\\n\");\n mstatus |= MSTATUS_MPRV;\n write_csr(mstatus, mstatus);\n return mstatus;\n }\n if (cmd == ECALL_GET_MSTATUS) {\n return mstatus;\n }\n\n printf(\" unknown ECALL code 0x%08X !\\n\", cmd);\n return -1;\n }\n\n return 0; // Ignored\n}\n\nvoid user_main ();\n\nint main () {\n\n // The test requires user mode support\n if ((read_csr(misa) & MISA_U) == 0) {\n printf(\"ERROR: The test requires user mode support. Aborting.\\n\");\n return -1;\n }\n\n uint32_t mstatus = read_csr(mstatus);\n\n // main() gets called from _start. We should be in machine mode.\n printf(\"Hello VeeR\\n\");\n\n // Verify initial state of mstatus after reset\n if (!(mstatus & MSTATUS_MPRV)) {\n printf(\"[ OK ] MPRV cleared\\n\");\n } else {\n printf(\"[ FAIL ] MPRV is set!\\n\");\n global_fail = 1;\n }\n\n // Check if MPP is set to 11\n if ((mstatus & MSTATUS_MPP_MASK) == MSTATUS_MPP_MACHINE) {\n printf(\"[ OK ] MPP is 11\\n\");\n } else {\n printf(\"[ FAIL ] MPP is not 11\\n\");\n global_fail = 1;\n }\n\n // Clear MPRV, make an ECALL which should set mcause to 11 (0xB) and\n // leave MPRV \n mstatus = read_csr(mstatus);\n mstatus &= ~MSTATUS_MPRV;\n write_csr(mstatus, mstatus);\n\n printf(\"doing ECALL (MPRV=0)...\\n\");\n do_ecall(ECALL_HELLO, 0);\n\n // Check if MPRV is cleared\n mstatus = read_csr(mstatus);\n if (!(mstatus & MSTATUS_MPRV)) {\n printf(\"[ OK ] MPRV cleared\\n\");\n } else {\n printf(\"[ FAIL ] MPRV is set!\\n\");\n global_fail = 1;\n }\n\n // Check if MPP is set to 00\n if ((mstatus & MSTATUS_MPP_MASK) == MSTATUS_MPP_USER) {\n printf(\"[ OK ] MPP is 00\\n\");\n } else {\n printf(\"[ FAIL ] MPP is not 00\\n\");\n global_fail = 1;\n }\n\n // Set MPRV and do the ECALL again\n mstatus = read_csr(mstatus);\n mstatus |= MSTATUS_MPRV;\n write_csr(mstatus, mstatus);\n\n printf(\"doing ECALL (MPRV=1)\\n\");\n do_ecall(ECALL_HELLO, 0);\n\n // Check if MPRV is set\n mstatus = read_csr(mstatus);\n if (mstatus & MSTATUS_MPRV) {\n printf(\"[ OK ] MPRV is set\\n\");\n } else {\n printf(\"[ FAIL ] MPRV is cleared!\\n\");\n global_fail = 1;\n }\n\n // Check if MPP is set to 00\n if ((mstatus & MSTATUS_MPP_MASK) == MSTATUS_MPP_USER) {\n printf(\"[ OK ] MPP is 00\\n\");\n } else {\n printf(\"[ FAIL ] MPP is not 00\\n\");\n global_fail = 1;\n }\n\n // Go to user mode, clear MPRV\n mstatus = read_csr(mstatus);\n mstatus &= ~MSTATUS_MPP_MASK;\n mstatus &= ~MSTATUS_MPRV;\n write_csr(mstatus, mstatus);\n\n void* ptr = (void*)user_main;\n write_csr(mepc, (unsigned long)ptr);\n asm volatile (\"mret\");\n\n return 0;\n}\n\n__attribute__((noreturn)) void user_main () {\n\n uint32_t mstatus;\n\n // We should be now in user mode\n printf(\"Hello from user_main()\\n\");\n\n // Do an ECALL to clear MPRV\n printf(\"doing ECALL...\\n\");\n mstatus = do_ecall(ECALL_CLR_MPRV, 0);\n\n // ECALL returns mstatus value right before returning to user mode.\n // Check if MPP is set to 00 as we called from user mode\n if ((mstatus & MSTATUS_MPP_MASK) == MSTATUS_MPP_USER) {\n printf(\"[ OK ] MPP is 00\\n\");\n } else {\n printf(\"[ FAIL ] MPP is not 00\\n\");\n global_fail = 1;\n }\n\n // Do an ECALL to get mstatus\n printf(\"doing ECALL...\\n\");\n mstatus = do_ecall(ECALL_GET_MSTATUS, 0);\n\n // Check if MPRV was cleared\n if (!(mstatus & MSTATUS_MPRV)) {\n printf(\"[ OK ] MPRV was cleared\\n\");\n } else {\n printf(\"[ FAIL ] MPRV was set!\\n\");\n global_fail = 1;\n }\n\n // Do an ECALL to set MPRV\n printf(\"doing ECALL...\\n\");\n mstatus = do_ecall(ECALL_SET_MPRV, 0);\n\n // ECALL returns mstatus value right before returning to user mode.\n // Check if MPP is set to 00 as we called from user mode\n if ((mstatus & MSTATUS_MPP_MASK) == MSTATUS_MPP_USER) {\n printf(\"[ OK ] MPP is 00\\n\");\n } else {\n printf(\"[ FAIL ] MPP is not 00\\n\");\n global_fail = 1;\n }\n\n // Do an ECALL to get mstatus\n printf(\"doing ECALL...\\n\");\n mstatus = do_ecall(ECALL_GET_MSTATUS, 0);\n\n // Check if MPRV was cleared\n if (!(mstatus & MSTATUS_MPRV)) {\n printf(\"[ OK ] MPRV was cleared\\n\");\n } else {\n printf(\"[ FAIL ] MPRV was set!\\n\");\n global_fail = 1;\n }\n\n // Verify trap data\n unsigned char res = 0xFF;\n\n printf(\"traps taken:\\n\");\n for (unsigned long i=0; i\n#include \n#include \n\n// Clear the destination reg before reading so that when the read fails the\n// returned value is 0\n#define read_csr(csr) ({ \\\n unsigned long res; \\\n asm volatile ( \\\n \"li %0, 0\\n\" \\\n \"csrr %0, %1\" \\\n : \"=r\"(res) : \"i\"(csr) \\\n ); \\\n res; \\\n})\n\n#define write_csr(csr, val) { \\\n asm volatile (\"csrw %0, %1\" : : \"i\"(csr), \"r\"(val)); \\\n}\n\n#define MISA_U (1 << 20)\n\n#define CSR_MISA 0x301\n#define CSR_MSTATUS 0x300\n#define CSR_MCAUSE 0x342\n#define CSR_MEPC 0x341\n\n#define CSR_MCOUNTEREN 0x306\n#define CSR_CYCLE 0xC00\n#define CSR_CYCLEH 0xC80\n#define CSR_INSTRET 0xC02\n#define CSR_INSTRETH 0xC82\n\n#define CSR_HPMCOUNTER3 0xC03\n#define CSR_HPMCOUNTER3H 0xC83\n#define CSR_HPMCOUNTER4 0xC04\n#define CSR_HPMCOUNTER4H 0xC84\n#define CSR_HPMCOUNTER5 0xC05\n#define CSR_HPMCOUNTER5H 0xC85\n#define CSR_HPMCOUNTER6 0xC06\n#define CSR_HPMCOUNTER6H 0xC86\n\n#define CSR_MHPMEVENT3 0x323\n#define CSR_MHPMEVENT4 0x324\n#define CSR_MHPMEVENT5 0x325\n#define CSR_MHPMEVENT6 0x326\n\n#define ECALL_GET_MCOUNTEREN 0x10\n#define ECALL_SET_MCOUNTEREN 0x20\n\n#define MSTATUS_MPP_MASK (3 << 11)\n#define MSTATUS_MPRV (1 << 17)\n\n#define MCAUSE_ILLEGAL_INSTR 0x2\n#define MCAUSE_ECALL_U 0x8\n#define MCAUSE_ECALL_M 0xb\n\n#define MCOUNTEREN_CY (1 << 0)\n#define MCOUNTEREN_IR (1 << 2)\n#define MCOUNTEREN_HPM3 (1 << 3)\n#define MCOUNTEREN_HPM4 (1 << 4)\n#define MCOUNTEREN_HPM5 (1 << 5)\n#define MCOUNTEREN_HPM6 (1 << 6)\n#define MCOUNTEREN_ALL 0x7D\n#define MCOUNTEREN_NONE 0x00\n\n#define TEST_RESULT_SUCCESS 0xFF\n#define TEST_RESULT_FAILURE 1\n\n#define VEER_EVT_INSTR_COMMITTED_16 5\n#define VEER_EVT_INSTR_COMMITTED_32 6\n#define VEER_EVT_BRANCHES_COMMITTED 24\n#define VEER_EVT_BRANCHES_MISPREDICTED 25\n\n#define COUNTER_COUNT 6\n\nvolatile int32_t global_result = 0;\nvolatile uint32_t last_trap = 0xFFFFFFFF;\n\nint32_t do_ecall (uint32_t cmd, uint32_t arg);\n\nint32_t ecall_handler (uint32_t cmd, uint32_t arg) {\n\n if (cmd == ECALL_GET_MCOUNTEREN) {\n return read_csr(CSR_MCOUNTEREN);\n }\n if (cmd == ECALL_SET_MCOUNTEREN) {\n printf(\"set mcounteren=0x%08X\\n\", arg);\n write_csr(CSR_MCOUNTEREN, arg);\n return 0;\n }\n\n printf(\"unknown ECALL code 0x%08X\\n\", cmd);\n global_result = -1;\n\n return -1;\n}\n\nint32_t trap_handler (uint32_t a0, uint32_t a1) {\n\n uint32_t mstatus = read_csr(CSR_MSTATUS);\n uint32_t mcause = read_csr(CSR_MCAUSE);\n printf(\"trap! mstatus=0x%08X, mcause=0x%08X\\n\", mstatus, mcause);\n\n // Handle ECALL\n if (mcause == MCAUSE_ECALL_U || mcause == MCAUSE_ECALL_M) {\n return ecall_handler(a0, a1);\n }\n\n // Store mcause code\n last_trap = mcause;\n\n return 0;\n}\n\nvoid user_main ();\n\nint main () {\n printf(\"\\nHello VeeR\\n\");\n\n // The test requires user mode support\n if ((read_csr(CSR_MISA) & MISA_U) == 0) {\n printf(\"ERROR: The test requires user mode support. Aborting.\\n\");\n return -1;\n }\n\n // Setup VeeR performance counter events. See VeeR EL2 manual table 7-1\n // for the complete event list and their codes.\n write_csr(CSR_MHPMEVENT3, VEER_EVT_INSTR_COMMITTED_16);\n write_csr(CSR_MHPMEVENT4, VEER_EVT_INSTR_COMMITTED_32);\n write_csr(CSR_MHPMEVENT5, VEER_EVT_BRANCHES_COMMITTED);\n write_csr(CSR_MHPMEVENT6, VEER_EVT_BRANCHES_MISPREDICTED);\n\n // Write mcounteren to allow counter access from user_mode\n write_csr(CSR_MCOUNTEREN, MCOUNTEREN_ALL);\n\n // Go to user mode\n uint32_t mstatus = read_csr(CSR_MSTATUS);\n mstatus &= ~MSTATUS_MPP_MASK; // MPP = 00 (user)\n mstatus &= ~MSTATUS_MPRV; // MPRV = 0\n write_csr(CSR_MSTATUS, mstatus);\n\n void* ptr = (void*)user_main;\n write_csr(CSR_MEPC, (unsigned long)ptr);\n asm volatile (\"mret\");\n\n return 0;\n}\n\nconst char* get_csr_name (int32_t csr) {\n\n switch (csr)\n {\n case CSR_CYCLE: return \"cycle\";\n case CSR_CYCLEH: return \"cycleh\";\n case CSR_INSTRET: return \"instret\";\n case CSR_INSTRETH: return \"instreth\";\n case CSR_HPMCOUNTER3: return \"hpmcounter3\";\n case CSR_HPMCOUNTER3H: return \"hpmcounter3h\";\n case CSR_HPMCOUNTER4: return \"hpmcounter4\";\n case CSR_HPMCOUNTER4H: return \"hpmcounter4h\";\n case CSR_HPMCOUNTER5: return \"hpmcounter5\";\n case CSR_HPMCOUNTER5H: return \"hpmcounter5h\";\n case CSR_HPMCOUNTER6: return \"hpmcounter6\";\n case CSR_HPMCOUNTER6H: return \"hpmcounter6h\";\n }\n\n return \"\";\n}\n\nuint32_t read_and_check (int32_t csr, int should_succeed) {\n\n // Clear trap code\n last_trap = 0xFFFFFFFF;\n\n // Read the CSR of interest\n uint32_t val = 0;\n switch (csr)\n {\n case CSR_CYCLE: val = read_csr(CSR_CYCLE); break;\n case CSR_CYCLEH: val = read_csr(CSR_CYCLEH); break;\n case CSR_INSTRET: val = read_csr(CSR_INSTRET); break;\n case CSR_INSTRETH: val = read_csr(CSR_INSTRETH); break;\n case CSR_HPMCOUNTER3: val = read_csr(CSR_HPMCOUNTER3); break;\n case CSR_HPMCOUNTER3H: val = read_csr(CSR_HPMCOUNTER3H); break;\n case CSR_HPMCOUNTER4: val = read_csr(CSR_HPMCOUNTER4); break;\n case CSR_HPMCOUNTER4H: val = read_csr(CSR_HPMCOUNTER4H); break;\n case CSR_HPMCOUNTER5: val = read_csr(CSR_HPMCOUNTER5); break;\n case CSR_HPMCOUNTER5H: val = read_csr(CSR_HPMCOUNTER5H); break;\n case CSR_HPMCOUNTER6: val = read_csr(CSR_HPMCOUNTER6); break;\n case CSR_HPMCOUNTER6H: val = read_csr(CSR_HPMCOUNTER6H); break;\n }\n\n // Check\n if (should_succeed) {\n if (last_trap != 0xFFFFFFFF) {\n printf(\"[ FAILED ] %s access should succeed, but trap encountered\\n\", get_csr_name(csr));\n global_result = -1;\n return 0;\n }\n }\n else {\n if (last_trap != MCAUSE_ILLEGAL_INSTR) { // Illegal instruction\n if (last_trap == 0xFFFFFFFF) {\n printf(\"[ FAILED ] %s access should fail, but no trap encountered\\n\", get_csr_name(csr));\n } else {\n printf(\"[ FAILED ] %s access should fail, but with different mcause code\\n\", get_csr_name(csr));\n }\n global_result = -1;\n return 0;\n }\n }\n \n printf(\"[ OK ] %s = %d\\n\", get_csr_name(csr), val);\n return val;\n}\n\nuint64_t read_and_check64(int32_t csr_base, int should_succeed) {\n // CSRs for high 32-bit parts of counters have the same addresses but\n // logically or-ed with 0x80.\n uint32_t hi = read_and_check(csr_base | 0x80, should_succeed);\n uint32_t lo = read_and_check(csr_base, should_succeed);\n return (((uint64_t)hi) << 32) | lo;\n}\n\nvoid check_counters (const uint64_t* cur_counters) {\n\n const char* counter_names[COUNTER_COUNT] = {\n \"cycle \",\n \"instret\",\n \"hpm3 \",\n \"hpm4 \",\n \"hpm5 \",\n \"hpm6 \"\n };\n\n static uint64_t prv_counters [COUNTER_COUNT] = {0};\n\n // Compute and print diffs\n int counters_ok = 1;\n for (int i=0; i\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \n#include \n\nextern volatile char tohost;\n\n\n__attribute__((__noreturn__)) void _exit (int status)\n{\n if (!status) tohost = 0xff;\n else tohost = 0x01;\n while (1) {};\n}\n\nint veer_tb_putc(char c, FILE *stream)\n{\n (void) stream;\n tohost = c;\n return c;\n}\n\nstatic FILE __stdio = FDEV_SETUP_STREAM(veer_tb_putc, NULL, NULL, _FDEV_SETUP_WRITE);\nFILE *const stdin = &__stdio;\n__strong_reference(stdin, stdout);\n__strong_reference(stdin, stderr);\n" }, { "path": "testbench/tests/pmp/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.option norvc\n.option nopic\n\n.section .text.init\n.align 4\n.global _start\n_start:\n\n # Setup stack\n la sp, _stack_hi\n\n # Setup trap handler\n la t0, _trap_entry\n csrw mtvec, t0\n\n # Clear .bss\n la t0, _bss\n la t1, _data_end\nbss: sw x0, 0(t0)\n addi t0, t0, 4\n bne t0, t1, bss\n\n # Call main()\n call main\n\n # Map exit code: 0 - success, not 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination, a0 holds the exit code\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.align 8\n_trap_entry:\n\n # Push one reg\n addi sp, sp, -4\n sw t0, 0(sp)\n\n # Check for ECALL.U\n csrr t0, mcause\n addi t0, t0, -8\n bnez t0, _trap_not_ecall_u\n\n # Pop one reg\n lw t0, 0(sp)\n addi sp, sp, +4\n\n # \"return\" to the ucall\n j _ucall_ret\n\n_trap_not_ecall_u:\n\n # Pop one reg\n # FIXME: Integrate pushing and popping\n lw t0, 0(sp)\n addi sp, sp, +4\n\n # Push stuff\n addi sp, sp, -35*4 # (32 regs + 3 CSRs)\n\n sw x0 , 0*4(sp)\n sw x1 , 1*4(sp)\n sw x2 , 2*4(sp)\n sw x3 , 3*4(sp)\n sw x4 , 4*4(sp)\n sw x5 , 5*4(sp)\n sw x6 , 6*4(sp)\n sw x7 , 7*4(sp)\n sw x8 , 8*4(sp)\n sw x9 , 9*4(sp)\n sw x10, 10*4(sp)\n sw x11, 11*4(sp)\n sw x12, 12*4(sp)\n sw x13, 13*4(sp)\n sw x14, 14*4(sp)\n sw x15, 15*4(sp)\n sw x16, 16*4(sp)\n sw x17, 17*4(sp)\n sw x18, 18*4(sp)\n sw x19, 19*4(sp)\n sw x20, 20*4(sp)\n sw x21, 21*4(sp)\n sw x22, 22*4(sp)\n sw x23, 23*4(sp)\n sw x24, 24*4(sp)\n sw x25, 25*4(sp)\n sw x26, 26*4(sp)\n sw x27, 27*4(sp)\n sw x28, 28*4(sp)\n sw x29, 29*4(sp)\n sw x30, 30*4(sp)\n sw x31, 31*4(sp)\n\n # push CSRs\n csrr t0, mepc\n sw t0, 32*4(sp)\n csrr t0, mcause\n sw t0, 33*4(sp)\n csrr t0, mtval\n sw t0, 34*4(sp)\n\n # Make a0 point to the stack frame which layout matches the fault struct\n mv a0, sp\n\n # Call trap handler\n call trap_handler\n\n # Advance mepc if the cause is not an external interrupt\n lw t0, 33*4(sp)\n li t1, 0x80000000\n and t0, t0, t1\n bne t0, x0, _trap_is_irq\n\n csrr t0, mepc\n addi t0, t0, 4\n csrw mepc, t0\n\n_trap_is_irq:\n\n # Pop stuff\n lw x0 , 0*4(sp)\n lw x1 , 1*4(sp)\n lw x2 , 2*4(sp)\n lw x3 , 3*4(sp)\n lw x4 , 4*4(sp)\n lw x5 , 5*4(sp)\n lw x6 , 6*4(sp)\n lw x7 , 7*4(sp)\n lw x8 , 8*4(sp)\n lw x9 , 9*4(sp)\n lw x10, 10*4(sp)\n lw x11, 11*4(sp)\n lw x12, 12*4(sp)\n lw x13, 13*4(sp)\n lw x14, 14*4(sp)\n lw x15, 15*4(sp)\n lw x16, 16*4(sp)\n lw x17, 17*4(sp)\n lw x18, 18*4(sp)\n lw x19, 19*4(sp)\n lw x20, 20*4(sp)\n lw x21, 21*4(sp)\n lw x22, 22*4(sp)\n lw x23, 23*4(sp)\n lw x24, 24*4(sp)\n lw x25, 25*4(sp)\n lw x26, 26*4(sp)\n lw x27, 27*4(sp)\n lw x28, 28*4(sp)\n lw x29, 29*4(sp)\n lw x30, 30*4(sp)\n lw x31, 31*4(sp)\n\n addi sp, sp, 35*4\n\n # Return\n mret\n\n.section .text\n.global ucall\nucall:\n\n # Prologue\n addi sp, sp, -4*4\n sw ra, 0*4(sp)\n sw s0, 1*4(sp)\n sw s1, 2*4(sp)\n\n # Clear mstatus MPP\n csrr s0, mstatus\n li s1, 0xFFFFE7FF\n and s0, s0, s1\n csrw mstatus, s0\n # Set the call vector (first arg)\n csrw mepc, a0\n # Store the return address to proxy code in ra\n la ra, _ucall_proxy\n # Shift arguments a[n] <- a[n+1]\n mv a0, a1\n mv a1, a2\n mv a2, a3\n mv a3, a4\n mv a4, a5\n mv a5, a6\n mv a6, a7\n li a7, 0\n # Jump\n mret\n\n_ucall_ret:\n\n # Epilogue\n lw ra, 0*4(sp)\n lw s0, 1*4(sp)\n lw s1, 2*4(sp)\n addi sp, sp, +4*4\n ret\n\n_ucall_proxy:\n ecall\n\n\n.global rv_setjmp_m\nrv_setjmp_m:\n\n # Save PC\n sw s0, -4(sp)\n auipc s0, 0\n addi s0, s0, -4\n sw s0, 0(a0)\n lw s0, -4(sp)\n\n # Save context to the buffer pointed by a0\n # the first word is the PC\n sw x1 , 1*4(a0)\n sw x2 , 2*4(a0)\n sw x3 , 3*4(a0)\n sw x4 , 4*4(a0)\n sw x5 , 5*4(a0)\n sw x6 , 6*4(a0)\n sw x7 , 7*4(a0)\n sw x8 , 8*4(a0)\n sw x9 , 9*4(a0)\n sw x10, 10*4(a0)\n sw x11, 11*4(a0)\n sw x12, 12*4(a0)\n sw x13, 13*4(a0)\n sw x14, 14*4(a0)\n sw x15, 15*4(a0)\n sw x16, 16*4(a0)\n sw x17, 17*4(a0)\n sw x18, 18*4(a0)\n sw x19, 19*4(a0)\n sw x20, 20*4(a0)\n sw x21, 21*4(a0)\n sw x22, 22*4(a0)\n sw x23, 23*4(a0)\n sw x24, 24*4(a0)\n sw x25, 25*4(a0)\n sw x26, 26*4(a0)\n sw x27, 27*4(a0)\n sw x28, 28*4(a0)\n sw x29, 29*4(a0)\n sw x30, 30*4(a0)\n sw x31, 31*4(a0)\n\n # Return the exit code set by rv_longjmp if any\n lw a0, 32*4(a0)\n ret\n\n.global rv_longjmp_m\nrv_longjmp_m:\n\n # Set return address\n lw s0, 0(a0)\n csrw mepc, s0\n\n # Set rv_setjmp exit code\n sw a1, 32*4(a0)\n\n # Make sure that we return to M mode\n csrr s0, mstatus\n li s1, 0x00001800\n or s0, s0, s1\n csrw mstatus, s0\n\n # Restore the context to what's pointed by a0\n lw x1 , 1*4(a0)\n lw x2 , 2*4(a0)\n lw x3 , 3*4(a0)\n lw x4 , 4*4(a0)\n lw x5 , 5*4(a0)\n lw x6 , 6*4(a0)\n lw x7 , 7*4(a0)\n lw x8 , 8*4(a0)\n lw x9 , 9*4(a0)\n lw x10, 10*4(a0)\n lw x11, 11*4(a0)\n lw x12, 12*4(a0)\n lw x13, 13*4(a0)\n lw x14, 14*4(a0)\n lw x15, 15*4(a0)\n lw x16, 16*4(a0)\n lw x17, 17*4(a0)\n lw x18, 18*4(a0)\n lw x19, 19*4(a0)\n lw x20, 20*4(a0)\n lw x21, 21*4(a0)\n lw x22, 22*4(a0)\n lw x23, 23*4(a0)\n lw x24, 24*4(a0)\n lw x25, 25*4(a0)\n lw x26, 26*4(a0)\n lw x27, 27*4(a0)\n lw x28, 28*4(a0)\n lw x29, 29*4(a0)\n lw x30, 30*4(a0)\n lw x31, 31*4(a0)\n\n # Return\n mret\n\n.section .data.io\n.global tohost\ntohost: .dword 0\n.global fromhost\nfromhost: .dword 0\n" }, { "path": "testbench/tests/pmp/fault.c", "content": "/* SPDX-License-Identifier: Apache-2.0\n * Copyright 2023 Antmicro, Ltd. \n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \n#include \n#include \"veer.h\"\n#include \"trap.h\"\n#include \"fault.h\"\n\nvolatile struct rv_jmp_buf* fault_jmp_env = NULL;\nvolatile struct fault fault_last;\n\nvoid fault_setjmp(struct rv_jmp_buf* env)\n{\n fault_jmp_env = env;\n}\n\nstruct fault fault_last_get(void)\n{\n return fault_last;\n}\n\nvoid fault_return(const struct fault *fault)\n{\n // Save register state for later usage\n memcpy((struct fault*)&fault_last, fault, sizeof(fault_last));\n\n // Return to program if setjmp-based try-catch was used\n if (fault_jmp_env != NULL) {\n struct rv_jmp_buf* env = (struct rv_jmp_buf*)fault_jmp_env;\n fault_jmp_env = NULL;\n rv_longjmp_m(env, 1);\n }\n}\n" }, { "path": "testbench/tests/pmp/fault.h", "content": "/* SPDX-License-Identifier: Apache-2.0\n * Copyright 2023 Antmicro, Ltd. \n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _FAULT_H\n#define _FAULT_H\n\n#include \"veer.h\"\n#include \"trap.h\"\n\n#define EXC_INSTRUCTION_ACC_FAULT 1\n#define EXC_LOAD_ACC_FAULT 5\n#define EXC_STORE_ACC_FAULT 7\n\nvoid fault_setjmp(struct rv_jmp_buf* env);\nstruct fault fault_last_get(void);\nvoid fault_return(const struct fault *fault);\n\n#endif\n" }, { "path": "testbench/tests/pmp/main.c", "content": "/* SPDX-License-Identifier: Apache-2.0\n * Copyright 2023 Antmicro, Ltd. \n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \n#include \n#include \n#include \n#include \"veer.h\"\n#include \"fault.h\"\n#include \"pmp.h\"\n\n#ifndef RV_SMEPMP\n#define RV_SMEPMP 0\n#endif\n\n#define CSR_MSTATUS 0x300\n#define CSR_MISA 0x301\n#define CSR_MEPC 0x341\n\n#define MISA_U (1 << 20)\n\nextern uint32_t _text;\nextern uint32_t _text_end;\nextern uint32_t _data;\nextern uint32_t _data_end;\nextern uint32_t _stack_lo;\nextern uint32_t _stack_hi;\nextern uint32_t _area;\nextern uint32_t tohost;\n\nextern int ucall (void* ptr, ...);\n\n// ============================================================================\n\nvolatile uint32_t test_area [16] __attribute__((section(\".area.bufr\")));\n\nconst uint32_t test_pattern_a [] = {\n 0xE8C50A2E,\n 0x017F84CA,\n 0xFB8A3138,\n 0xFDF0F930,\n 0xA5F12034,\n 0x4A67B7B6,\n 0xD03C9377,\n 0xD124A11C,\n 0xAB319961,\n 0xF94AF557,\n 0xDD743AE6,\n 0xAAB99BC3,\n 0xE992D7FA,\n 0x5C6A76FA,\n 0xD8D63FE2,\n 0x8616CFC6\n};\n\nconst uint32_t test_pattern_b [] = {\n 0x2B0B56F2,\n 0x6B78B6FF,\n 0xE7B61C7A,\n 0x66FB04DB,\n 0xC2F2BE9D,\n 0x2D569A89,\n 0x905BF8E6,\n 0x2798E7CE,\n 0x509BA997,\n 0xBF0147EB,\n 0x09065BEF,\n 0x04146267,\n 0xC421C6E3,\n 0xD6C76040,\n 0x773AA931,\n 0x01C01BDE\n};\n\nvolatile unsigned long did_execute = 0;\n\nvoid __attribute__((noinline)) test_hello () {\n did_execute = 1;\n printf(\" hello\\n\");\n}\n\nint __attribute__((noinline)) test_read (const uint32_t* pattern) {\n did_execute = 1;\n printf(\" reading from .area...\\n\");\n\n uint32_t arr[16];\n for (size_t i=0; i<16; ++i) {\n arr[i] = test_area[i];\n }\n\n if (memcmp(arr, pattern, sizeof(arr))) {\n printf(\" data mismatch\\n\");\n return -1;\n }\n else {\n printf(\" data match\\n\");\n }\n\n return 0;\n}\n\nvoid __attribute__((noinline)) test_write (const uint32_t* pattern) {\n did_execute = 1;\n printf(\" writing to .area...\\n\");\n\n for (size_t i=0; i<16; ++i) {\n test_area[i] = pattern[i];\n }\n}\n\nvoid __attribute__((noinline, section(\".area.code\"))) test_exec () {\n printf(\" hello from .area\\n\");\n}\n\n// ============================================================================\n\nvolatile unsigned long trap_count = 0;\n\nint trap_handler (const struct fault* fault) {\n printf(\" Trap! mcause=0x%08x, mepc=0x%08X, sp=0x%08X\\n\", fault->mcause, fault->mepc, fault->r[2]);\n\n // Terminate the simulation if too many traps got triggered\n if (++trap_count > 100) {\n printf(\"Too many traps, aborting...\\n\");\n _exit(-1);\n }\n\n // If setjmp-based try-catch was used return to the program\n fault_return(fault);\n return 0;\n}\n\n// ============================================================================\n\n// Convert byte address for PMP. Effectively does \"ceil(x / 4)\"\n#define ADDR2PMP(x) ((((uint32_t)(x)) & 3) ? ((((uint32_t)(x)) >> 2) + 1) : \\\n (((uint32_t)(x)) >> 2))\n\n// Set mstatus MPRV\n#define set_mprv(x) { \\\n uint32_t mstatus; \\\n CSRR_READ(mstatus, CSR_MSTATUS); \\\n if (x) mstatus |= (1 << 17); \\\n else mstatus &= ~(1 << 17); \\\n CSRR_WRITE(mstatus, CSR_MSTATUS); \\\n}\n\n// Set mstatus MPP to 00 or 11\n#define set_mpp(x) { \\\n uint32_t mstatus; \\\n CSRR_READ(mstatus, CSR_MSTATUS); \\\n if (x) mstatus |= (3 << 11); \\\n else mstatus &= ~(3 << 11); \\\n CSRR_WRITE(mstatus, CSR_MSTATUS); \\\n}\n\n#define TST_R 1\n#define TST_W 2\n#define TST_X 4\n#define TST_M 16\n#define TST_MPRV 32\n#define TST_MPP 64\n\n// ============================================================================\n\nint main () {\n printf(\"Hello VeeR (M mode)\\n\");\n\n#if RV_SMEPMP\n printf(\"VeeR has Smepmp\\n\");\n#else\n printf(\"VeeR does not have Smepmp\\n\");\n#endif\n\n // Check if we have user mode support\n uint32_t misa = 0;\n CSRR_READ(misa, CSR_MISA);\n int have_user_mode = (misa & MISA_U) != 0;\n\n#if RV_SMEPMP\n // Set MSECCFG\n uint32_t mseccfg = 0;\n CSRR_WRITE(mseccfg, 0x747);\n#endif\n\n // .......................................................................\n // Determine PMP granularity\n uintptr_t tmp = 0;\n pmp_write_pmpcfg (0, &tmp);\n tmp = 0xFFFFFFFF;\n pmp_write_pmpaddr(0, &tmp);\n pmp_read_pmpaddr (0, &tmp);\n\n int g = 0;\n for (; g < 32; ++g) {\n if (tmp & 1) break;\n tmp >>= 1;\n }\n\n printf(\"PMP G=%d, granularity is %d\\n\", g, 1 << (g + 2));\n\n // .......................................................................\n struct pmp_entry_s entry;\n int tid = 0;\n int failed = 0;\n\n pmp_clear();\n\n // .......................................................................\n // Check if user mode has access to everything by default when PMP is not\n // configured. Just call a simple function.\n if (have_user_mode) {\n printf(\"%02d - User mode RWX in default state\\n\", tid++);\n\n printf(\" testing...\\n\");\n#if RV_SMEPMP\n TRY {\n ucall(test_hello);\n printf(\" fail\\n\");\n failed++;\n }\n CATCH {\n printf(\" pass\\n\");\n }\n END_TRY;\n#else\n TRY {\n ucall(test_hello);\n printf(\" pass\\n\");\n }\n CATCH {\n printf(\" fail\\n\");\n failed++;\n }\n END_TRY;\n#endif\n }\n\n // .......................................................................\n // Configure a single region in PMP and call user mode function. It should\n // not have access to code and stack hence it should not execute\n if (have_user_mode) {\n printf(\"%02d - User mode RWX with one (any) PMP region enabled\\n\", tid++);\n\n // Allow area1 user access\n entry.addr = ADDR2PMP(&_area);\n entry.addr = (entry.addr & 0xFFFFFC00) | 0x000001FF; // NAPOT, 2^12\n entry.cfg = PMP_NAPOT | PMP_R | PMP_W | PMP_X;\n pmp_entry_write(5, &entry);\n\n printf(\" testing...\\n\");\n TRY {\n ucall(test_hello);\n printf(\" fail\\n\");\n failed++;\n }\n CATCH {\n printf(\" pass\\n\");\n }\n END_TRY;\n }\n\n // .......................................................................\n // Configure PMP to allow user mode access to code and stack\n if (have_user_mode) {\n printf(\"%02d - User mode RWX with code, data and stack access allowed\\n\", tid++);\n\n // Allow user access to \"tohost\" and \"fromhost\"\n entry.addr = ADDR2PMP(&tohost);\n entry.addr = (entry.addr & 0xFFFFFFFC) | 1; // NAPOT 2^4\n entry.cfg = PMP_NAPOT | PMP_R | PMP_W;\n pmp_entry_write(0, &entry);\n\n // Allow user access to code\n entry.addr = ADDR2PMP(&_text);\n entry.cfg = 0;\n pmp_entry_write(1, &entry);\n entry.addr = ADDR2PMP(&_text_end) + 1; // upper bound is not inclusive\n entry.cfg = PMP_TOR | PMP_R | PMP_X;\n pmp_entry_write(2, &entry);\n\n // Allow user access to data\n entry.addr = ADDR2PMP(&_data);\n entry.addr = (entry.addr & 0xFFFFFC00) | 0x000001FF; // NAPOT, 2^12\n entry.cfg = PMP_NAPOT | PMP_R | PMP_W;\n pmp_entry_write(3, &entry);\n entry.addr = ADDR2PMP(&_data);\n\n // Allow user access to stack\n entry.addr = ADDR2PMP(&_stack_lo);\n entry.addr = (entry.addr & 0xFFFFF800) | 0x000003FF; // NAPOT, 2^13\n entry.cfg = PMP_NAPOT | PMP_R | PMP_W;\n pmp_entry_write(4, &entry);\n\n printf(\" testing...\\n\");\n TRY {\n ucall(test_hello);\n printf(\" pass\\n\");\n }\n CATCH {\n printf(\" fail\\n\");\n failed++;\n }\n END_TRY;\n }\n\n // .......................................................................\n // Test PMP operation for all possible RWX combinations in U and M mode.\n\n // Generate test cases. A test case is encoded on a byte:\n // bit 0: R\n // bit 1: W\n // bit 2: X\n // bit 4: 0-user, 1-machine\n // bit 5: mstatus.MPRV\n // bit 6: mstatus.MPP (0 for 00, 1 for 11)\n uint8_t test_cases [32];\n uint32_t test_count = 0;\n\n // Test cases for all RWX combinations in user mode\n if (have_user_mode) {\n for (size_t i=0; i<8; ++i) {\n uint32_t r = (i & 1) ? PMP_R : 0;\n uint32_t w = (i & 2) ? PMP_W : 0;\n uint32_t x = (i & 4) ? PMP_X : 0;\n\n#if RV_SMEPMP\n // Skip -W- and -WX combinations\n if (!r && w && !x) continue;\n if (!r && w && x) continue;\n#endif\n test_cases[test_count++] = i;\n }\n }\n\n // Test cases for all RWX combinations in machine mode\n for (size_t i=0; i<8; ++i) {\n uint32_t r = (i & 1) ? PMP_R : 0;\n uint32_t w = (i & 2) ? PMP_W : 0;\n uint32_t x = (i & 4) ? PMP_X : 0;\n\n#if RV_SMEPMP\n // Skip -W- and -WX combinations\n if (!r && w && !x) continue;\n if (!r && w && x) continue;\n#endif\n test_cases[test_count++] = TST_M | i;\n }\n\n // Test cases for all RWX combinations in machine mode with MPRV set\n if (have_user_mode) {\n for (size_t i=0; i<16; ++i) {\n uint32_t r = (i & 1) ? PMP_R : 0;\n uint32_t w = (i & 2) ? PMP_W : 0;\n uint32_t x = (i & 4) ? PMP_X : 0;\n uint32_t mpp = (i & 8) != 0;\n\n#if RV_SMEPMP\n // Skip -W- and -WX combinations\n if (!r && w && !x) continue;\n if (!r && w && x) continue;\n#endif\n test_cases[test_count++] = (TST_MPP * mpp) | TST_MPRV | TST_M | i;\n }\n }\n\n // ................................\n // Do the tests\n\n for (size_t i=0; i\n#include \"pmp.h\"\n\nint pmp_clear ()\n{\n const int pmp_entries = 16; // FIXME: Parametrize that\n\n uintptr_t zero = 0;\n int res = 0;\n\n for (int i=0; i<(pmp_entries + 3)/4; ++i) {\n if (pmp_write_pmpcfg(i, &zero)) {\n res = -1;\n }\n }\n for (int i=0; i> 2) & ((__riscv_xlen == 32) ? (~0) : (~1));\n unsigned int pmpcfg_id_fine = id & ((__riscv_xlen == 32) ? 3 : 7);\n\n uintptr_t pmpcfg_csr;\n uintptr_t pmpaddr_csr;\n\n /* One PMPCFGx register contains configuration\n * for 4 entries (RV32) or 8 entries (RV64).\n */\n\n if (!entry) return 1;\n if (id > 64) return 2;\n\n /* Read PMPADDRx CSR */\n if (pmp_read_pmpaddr(id, &pmpaddr_csr) != 0) return 3;\n\n /* Read PMPCFGx CSR */\n if (pmp_read_pmpcfg(pmpcfg_id_coarse, &pmpcfg_csr) != 0) return 4;\n\n entry->addr = pmpaddr_csr;\n entry->cfg = (pmpcfg_csr >> (8 * pmpcfg_id_fine)) & 0xff;\n\n return 0;\n}\n\nint pmp_entry_write(unsigned int id, struct pmp_entry_s * entry)\n{\n unsigned int pmpcfg_id_coarse = (id >> 2) & ((__riscv_xlen == 32) ? (~0) : (~1));\n unsigned int pmpcfg_id_fine = id & ((__riscv_xlen == 32) ? 3 : 7);\n\n unsigned int pmpcfg_csr;\n unsigned int pmpaddr_csr;\n\n /* One PMPCFGx register contains configuration\n * for 4 entries (RV32) or 8 entries (RV64).\n */\n\n if (!entry) return 1;\n if (id > 64) return 2;\n\n /* Write entry to PMPADDRx CSR */\n pmpaddr_csr = entry->addr;\n if (pmp_write_pmpaddr(id, &pmpaddr_csr) != 0) return 3;\n\n /* Write entry to PMPCFGx CSR. Other entries in the same CSR are left intact */\n if (pmp_read_pmpcfg(pmpcfg_id_coarse, &pmpcfg_csr) != 0) return 4;\n pmpcfg_csr = pmpcfg_csr & (~(0xff << (pmpcfg_id_fine * 8))) | (entry->cfg << (pmpcfg_id_fine * 8));\n if (pmp_write_pmpcfg(pmpcfg_id_coarse, &pmpcfg_csr) != 0) return 5;\n\n return 0;\n}\n\nint pmp_is_cfg_legal (unsigned int cfg) {\n // Check if RWX combination is legal according to\n // RISC-V privilege spec v1.12 chapter 3.7.1\n\n cfg &= (PMP_R | PMP_W | PMP_X);\n\n if (cfg == (PMP_W))\n return 0;\n if (cfg == (PMP_W | PMP_X))\n return 0;\n\n return 1;\n}\n" }, { "path": "testbench/tests/pmp/pmp.h", "content": "#include \n\n#define PMP_LOCK (1<<7)\n#define PMP_OFF (0<<3)\n#define PMP_TOR (1<<3)\n#define PMP_NA4 (2<<3)\n#define PMP_NAPOT (3<<3)\n#define PMP_X (1<<2)\n#define PMP_W (1<<1)\n#define PMP_R (1<<0)\n\n#define PMP_MODE_MASK (3<<3)\n#define PMP_RWX_MASK (7)\n\n#define CSR_PMPCFG_BASE 0x3A0\n#define CSR_PMPADDR_BASE 0x3B0\n\n#define CSRR_READ(v, csr) \\\n/* CSRR_READ(v, csr): \\\n * csr: MUST be a compile time integer 12-bit constant (0-4095) \\\n */ \\\n__asm__ __volatile__ (\"csrr %0, %1\" \\\n : \"=r\" (v) \\\n : \"n\" (csr) \\\n : /* clobbers: none */ )\n\n#define CSRR_WRITE(v, csr) \\\n/* CSRR_WRITE(v, csr): \\\n * csr: MUST be a compile time integer 12-bit constant (0-4095) \\\n */ \\\n__asm__ __volatile__ (\"csrw %0, %1\" \\\n : \\\n : \"n\" (csr), \"rK\" (v) \\\n : /* clobbers: none */ )\n\nstruct pmp_entry_s {\n uintptr_t addr;\n uint8_t cfg;\n};\n\nint pmp_clear();\nint pmp_read_pmpcfg(unsigned int offset, uintptr_t * dest);\nint pmp_read_pmpaddr(unsigned int offset, uintptr_t * dest);\nint pmp_write_pmpcfg(unsigned int offset, uintptr_t * src);\nint pmp_write_pmpaddr(unsigned int offset, uintptr_t * src);\nint pmp_entry_read(unsigned int id, struct pmp_entry_s * entry);\nint pmp_entry_write(unsigned int id, struct pmp_entry_s * entry);\nint pmp_is_cfg_legal(unsigned int cfg);\n" }, { "path": "testbench/tests/pmp/pmp.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n\n . = 0x80000000;\n _text = .;\n .text : { *(.text.init*) *(.text*) }\n _text_end = .;\n _end = .;\n\n . = ALIGN(4096);\n _data = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) }\n _bss = .;\n .bss : { *(.bss) }\n _data_end = .;\n\n . = ALIGN(4096);\n _area = .;\n .area : { *(.area.bufr) *(.area.code) }\n . = ALIGN(4096);\n\n . = ALIGN(8192);\n _stack_lo = .;\n . += 8192;\n _stack_hi = .;\n\n . = 0xd0580000;\n .data.io . (NOLOAD) : { KEEP( *(.data.io) ) }\n}\n" }, { "path": "testbench/tests/pmp/pmp.mki", "content": "OFILES = crt0.o main.o pmp.o veer.o fault.o\nTEST_CFLAGS = -g -O3 -falign-functions=16\n" }, { "path": "testbench/tests/pmp/trap.h", "content": "/*\n * SPDX-License-Identifier: BSD-3-Clause\n *\n * Copyright © 2020 Sebastian Meyer\n * Copyright 2023 Antmicro, Ltd. \n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above\n * copyright notice, this list of conditions and the following\n * disclaimer in the documentation and/or other materials provided\n * with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,\n * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* Derived from picolibc: picocrt/machine/riscv/crt0.c\n */\n\n#ifndef _TRAP_H\n#define _TRAP_H\n\nstruct fault {\n unsigned long r[32];\n unsigned long mepc;\n unsigned long mcause;\n unsigned long mtval;\n};\n\n#endif\n" }, { "path": "testbench/tests/pmp/veer.c", "content": "/* SPDX-License-Identifier: Apache-2.0\n * Copyright 2023 Antmicro, Ltd. \n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \n#include \n\n#include \"veer.h\"\n\n#if USE_HTIF\n\nextern volatile uint64_t tohost;\nextern volatile uint64_t fromhost;\n\nint64_t veer_syscall (int64_t a0, int64_t a1, int64_t a2, int64_t a3) {\n\n // HTIF syscall command. It uses 8 args but for most cases 4 is enough.\n volatile int64_t cmd[8] = {\n a0, a1, a2, a3,\n 0, 0, 0, 0\n };\n\n // Write a pointer to the command buffer to \"tohost\"\n tohost = (uint64_t)(uintptr_t)cmd;\n\n // Wait for response in \"fromhost\"\n while (1) {\n volatile uint64_t fh = fromhost;\n if (fh != 0) {\n fromhost = 0; // reply\n break;\n }\n }\n\n return cmd[0];\n}\n#else\n\nextern volatile char tohost;\n\n#endif\n\n__attribute__((__noreturn__)) void _exit (int status)\n{\n#if USE_HTIF\n veer_syscall (HTIF_SYSCALL_EXIT, status, 0, 0);\n#else\n if (!status) tohost = 0xff;\n else tohost = 0x01;\n#endif\n while (1);\n}\n\nint veer_tb_putc(char c, FILE *stream)\n{\n (void) stream;\n\n#if USE_HTIF\n // Do putc() via htif \"bcd\" device in Spike\n tohost = (1LL << 56) | (1LL << 48) | c;\n while (tohost != 0); // wait for reply\n#else\n tohost = c;\n#endif\n\n return c;\n}\n\nstatic FILE __stdio = FDEV_SETUP_STREAM(veer_tb_putc, NULL, NULL, _FDEV_SETUP_WRITE);\nFILE *const stdin = &__stdio;\n__strong_reference(stdin, stdout);\n__strong_reference(stdin, stderr);\n" }, { "path": "testbench/tests/pmp/veer.h", "content": "/* SPDX-License-Identifier: Apache-2.0\n * Copyright 2023 Antmicro, Ltd. \n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __VEER_H\n#define __VEER_H\n\n// Set to 1 if using HTIF interface eg. in Spike\n#define USE_HTIF 0\n\n#include \n\nstruct rv_jmp_buf {\n long pc;\n unsigned long regs[31];\n long exitcode;\n};\n\n// RISC-V specific setjmp() variant. Must be called from M-mode\nextern long rv_setjmp_m (struct rv_jmp_buf*);\n// RISC-V specific longjmp() variant. Must be called from M-mode\nextern void rv_longjmp_m (struct rv_jmp_buf*, long exitcode);\n\n#define TRY do { struct rv_jmp_buf try_buf = {0}; if(!rv_setjmp_m(&try_buf)) { fault_setjmp(&try_buf);\n#define CATCH } else {\n#define END_TRY } } while(0)\n\n__attribute__((__noreturn__)) void _exit (int status);\n\n#if USE_HTIF\n#define HTIF_SYSCALL_WRITE 64\n#define HTIF_SYSCALL_EXIT 93\n\nint64_t veer_syscall (int64_t a0, int64_t a1, int64_t a2, int64_t a3);\n#endif\n\n#endif\n" }, { "path": "testbench/tests/pmp_random/generate_random.sh", "content": "#!/usr/bin/env bash\n\nset -e\n\noutfile=random_data.h\niterations=100\n\nprintf '// This file was generated with generate_random.sh\\n\\n' > $outfile\n\necho \"#define RANDOM_ITERATIONS $iterations\" >> $outfile\necho 'const uint32_t rand_address [] = {' >> $outfile\n\n# generate random data in hex, fold each 8 hex digits, prepend '0x', append ',' \ntr -dc 'A-F0-9' < /dev/urandom | dd bs=1 count=$((8 * $iterations)) 2>/dev/null | \\\n fold -w8 | \\\n sed 's/^/ 0x/' | \\\n sed 's/$/,/' >> $outfile\necho >> $outfile\necho '};' >> $outfile\n\necho 'const uint32_t rand_config [] = {' >> $outfile\n# generate random data in hex, fold each 8 hex digits, prepend '0x', append ',' \ntr -dc 'A-F0-9' < /dev/urandom | dd bs=1 count=$((8 * $iterations)) 2>/dev/null | \\\n fold -w8 | \\\n sed 's/^/ 0x/' | \\\n sed 's/$/,/' >> $outfile\necho >> $outfile\necho '};' >> $outfile\n\n" }, { "path": "testbench/tests/pmp_random/main.c", "content": "/* SPDX-License-Identifier: Apache-2.0\n * Copyright 2025 Antmicro, Ltd. \n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \n#include \n#include \n#include \n#include \"veer.h\"\n#include \"fault.h\"\n#include \"pmp.h\"\n#include \"random_data.h\"\n\n#define mailbox_addr 0xd0580000\n\nextern uint32_t _text;\nextern uint32_t _text_end;\nextern uint32_t _data;\nextern uint32_t _data_end;\nextern uint32_t _stack_lo;\nextern uint32_t _stack_hi;\nextern uint32_t _area;\nextern uint32_t tohost;\n\n// ============================================================================\n\nconst uint32_t test_pattern_a [] = {\n 0xE8C50A2E,\n 0x017F84CA,\n 0xFB8A3138,\n 0xFDF0F930,\n 0xA5F12034,\n 0x4A67B7B6,\n 0xD03C9377,\n 0xD124A11C,\n 0xAB319961,\n 0xF94AF557,\n 0xDD743AE6,\n 0xAAB99BC3,\n 0xE992D7FA,\n 0x5C6A76FA,\n 0xD8D63FE2,\n 0x8616CFC6\n};\n\nconst uint32_t test_pattern_b [] = {\n 0x2B0B56F2,\n 0x6B78B6FF,\n 0xE7B61C7A,\n 0x66FB04DB,\n 0xC2F2BE9D,\n 0x2D569A89,\n 0x905BF8E6,\n 0x2798E7CE,\n 0x509BA997,\n 0xBF0147EB,\n 0x09065BEF,\n 0x04146267,\n 0xC421C6E3,\n 0xD6C76040,\n 0x773AA931,\n 0x01C01BDE\n};\n\nvolatile unsigned long did_execute = 0;\n\nvoid __attribute__((noinline)) test_hello () {\n did_execute = 1;\n printf(\" hello\\n\");\n}\n\nint __attribute__((noinline)) test_read (const uint32_t* pattern, uint32_t* source, size_t size) {\n did_execute = 1;\n printf(\" reading from 0x%x...\\n\", source);\n\n if (memcmp(source, pattern, size)) {\n printf(\" data mismatch\\n\");\n return -1;\n }\n else {\n printf(\" data match\\n\");\n }\n\n return 0;\n}\n\nvoid __attribute__((noinline)) test_write (const uint32_t* pattern, uint32_t* target, size_t size) {\n did_execute = 1;\n printf(\" writing to 0x%x...\\n\", target);\n\n memcpy((void*)target, pattern, size);\n}\n\nvoid __attribute__((noinline, naked, optimize(\"O0\"), section(\".area.code\"))) test_exec () {\n asm volatile (\"ret\");\n}\n\n// ============================================================================\n\nvolatile unsigned long trap_count = 0;\n\nint trap_handler (const struct fault* fault) {\n printf(\" Trap! mcause=0x%08x, mepc=0x%08X, sp=0x%08X\\n\", fault->mcause, fault->mepc, fault->r[2]);\n\n // Terminate the simulation if too many traps got triggered\n if (++trap_count > 100) {\n printf(\"Too many traps, aborting...\\n\");\n _exit(-1);\n }\n\n // If setjmp-based try-catch was used return to the program\n fault_return(fault);\n return 0;\n}\n\n// ============================================================================\n\n// Convert byte address for PMP. Effectively does \"ceil(x / 4)\"\n#define ADDR2PMP(x) ((((uint32_t)(x)) & 3) ? ((((uint32_t)(x)) >> 2) + 1) : \\\n (((uint32_t)(x)) >> 2))\n\nenum RegionType {\n OFF = 0,\n TOR = 1,\n NA4 = 2,\n NAPOT = 3\n};\n\nuint32_t reconcile_address(uint32_t address) {\n uint32_t area_end = ((uint32_t)&_area) + 0x40;\n address &= 0x7fffffff; // do not use 0xf region\n while (((address < (uint32_t)&_stack_hi && address >= (uint32_t)&_stack_lo)\n ||(address >= (uint32_t)&_text && address < (uint32_t)&_text_end)\n ||(address >= (uint32_t)&_data && address < (uint32_t)&_data_end)\n ||(address >= (uint32_t)&_area && address < area_end)\n ||(address >= 0x10000000 && address < 0x20000000) // csrs\n ||(address >= 0x00000 && address < 0x40000) // reserved\n ||(address >= 0x60000 && address < 0x80000) // reserved\n ||(address >= 0x60000 && address < 0x80000) // reserved\n ||(address >= 0xa0000 && address < 0x10000000) // reserved\n ||(address == mailbox_addr))\n && (address != 0)\n ) {\n address >>= 1;\n }\n if (address == 0) {\n // 0 is reserved, fallback\n address = 0x76543210;\n }\n\n return address;\n}\n\nuint32_t legalize_address(uintptr_t address, enum RegionType region_type) {\n switch (region_type) {\n case OFF:\n return 0;\n case TOR:\n return 0;\n case NA4:\n // Do not use two most significant bits, VeeR ties them to 0 anyway.\n address &= 0x3fffffff;\n break;\n case NAPOT:\n // Do not use regions smaller than 32-bytes\n address |= 3;\n // Do not use large regions.\n if ((address & 0x3ff) == 0x3ff) address &= ~(1<<7);\n // Do not use two most significant bits, VeeR ties them to 0 anyway.\n address &= 0x3fffffff;\n break;\n default:\n break;\n }\n\n return address;\n}\n\nuint8_t legalize_config(uint32_t config) {\n uint32_t tmp_config = config;\n // if not enabled, shift right until it's a valid enabled region.\n // if it's 0, give up.\n while ((((config & PMP_MODE_MASK) == PMP_OFF) || ((config & PMP_MODE_MASK) == PMP_TOR))\n && (tmp_config>>3) !=0) {\n config &= ~PMP_MODE_MASK;\n config |= tmp_config & PMP_MODE_MASK;\n tmp_config >>= 1;\n }\n\n // if no valid mode was found in the random data, fallback to NAPOT\n if (((config & PMP_MODE_MASK) == PMP_OFF)\n ||(config & PMP_MODE_MASK) == PMP_TOR) {\n config &= ~PMP_MODE_MASK;\n config |= PMP_NAPOT;\n }\n\n tmp_config = config;\n while ((((config & PMP_RWX_MASK) == PMP_W) || ((config & PMP_RWX_MASK) == (PMP_W | PMP_X)))\n & (tmp_config != 0)) {\n // -W- is illegal, -WX is illegal, find another config\n config &= ~PMP_RWX_MASK;\n config |= tmp_config & PMP_RWX_MASK;\n tmp_config >>= 1;\n }\n\n // This test assumes Lock is 0\n config &= ~PMP_LOCK;\n\n // config registers are 8bit\n config &= 0xff;\n return (uint8_t)config;\n}\n\n#define TST_R 1\n#define TST_W 2\n#define TST_X 4\n#define TST_M 16\n\n#define trailing_ones(x) __builtin_ctz(~x & (x + 1))\n\nuint32_t generate_napot_mask(uint32_t value) {\n // Find the position of the first zero\n uint32_t pos = trailing_ones(value);\n // Create a mask with 'pos' number of ones\n uint32_t mask = (1U << pos) - 1;\n return mask;\n}\n\nint get_effective_range(uintptr_t * const address, enum RegionType region_type, uintptr_t * const addr_hi, uintptr_t * const addr_lo) {\n *address = legalize_address(*address, region_type);\n\n // address is the value to be written to address register\n // addr_hi and addr_lo should hold actual addresses\n uint32_t mask = generate_napot_mask(*address);\n uintptr_t new_address = 0;\n switch (region_type) {\n case OFF:\n *addr_lo = 0;\n *addr_hi = 0;\n break;\n case TOR:\n *addr_lo = 0;\n *addr_hi = *address << 2;\n break;\n case NA4:\n *addr_lo = *address << 2;\n new_address = reconcile_address(*addr_lo);\n if (new_address != (*addr_lo)) {\n *addr_lo = new_address;\n // need to update the address to be written to register as well\n *address = *addr_lo >> 2;\n }\n *addr_hi = *addr_lo + 3;\n break;\n case NAPOT:\n *addr_lo = ((uint32_t)*address & ~mask) << 2;\n new_address = reconcile_address(*addr_lo);\n if (new_address != (*addr_lo)) {\n *addr_lo = new_address;\n // need to update the address to be written to register as well\n *address &= ~mask;\n *address |= ((new_address >> 2) & ~mask);\n }\n *addr_hi = *addr_lo + (1 << (trailing_ones(*address)+3)) - 1;\n break;\n default:\n break;\n }\n return 0;\n}\n\nint main () {\n printf(\"Hello VeeR (M mode)\\n\");\n // .......................................................................\n // Determine PMP granularity\n uintptr_t tmp = 0;\n pmp_write_pmpcfg (0, &tmp);\n tmp = 0xFFFFFFFF;\n pmp_write_pmpaddr(0, &tmp);\n pmp_read_pmpaddr (0, &tmp);\n\n int g = 0;\n for (; g < 32; ++g) {\n if (tmp & 1) break;\n tmp >>= 1;\n }\n\n printf(\"PMP G=%d, granularity is %d\\n\", g, 1 << (g + 2));\n\n // .......................................................................\n struct pmp_entry_s random_entry;\n int tid = 0;\n int failed = 0;\n\n pmp_clear();\n // ................................\n // Do the tests\n\n // This test iterates over random data (see random_data.h)\n // which contains values for address and configuration.\n // Random data needs to be adjusted to represent legal configurations. \n // Currently each iteration configures only one region and the others remain OFF.\n // TOR regions are not used.\n\n // use regions 6..15 for random data\n int region_for_rand_data = 6;\n\n for (int rand_test_i = 0; rand_test_i> 3) & 3;\n uintptr_t addr_hi = 0;\n uintptr_t addr_lo = 0;\n uint32_t region_size = 0;\n\n // Get access rights from `config`.\n uint32_t r = ((config & PMP_R) == PMP_R) ? 1 : 0;\n uint32_t w = ((config & PMP_W) == PMP_W) ? 1 : 0;\n uint32_t x = ((config & PMP_X) == PMP_X) ? 1 : 0;\n\n /* Calculate effective range using type and addr. */\n get_effective_range(&address, region_type, &addr_hi, &addr_lo);\n region_size = addr_hi - addr_lo + 1;\n\n // Effective mode\n uint32_t r_eff = 1; // not using user mode or Lock\n uint32_t w_eff = 1; // not using user mode or Lock\n uint32_t x_eff = x;\n\n char pstr[4] = {\n r ? 'R' : '-',\n w ? 'W' : '-',\n x ? 'X' : '-',\n 0x00\n };\n\n printf(\"%02d - Machine mode: test %s in region(%d): 0x%x - 0x%x, size:0x%x\\n\",\n tid++, pstr, region_type, addr_lo, addr_hi, region_size);\n\n // Write data to the tested region before configuring PMP.\n const uint32_t* pattern = (i & 1) ? test_pattern_b : test_pattern_a;\n const uint32_t* other = (i & 1) ? test_pattern_a : test_pattern_b;\n\n size_t test_size = (region_size > sizeof(other)) ? sizeof(other) : region_size;\n\n memcpy((void*)addr_lo, other, test_size);\n\n // Disable the region previously used for random data.\n random_entry.cfg = PMP_OFF;\n random_entry.addr = 0;\n pmp_entry_write(region_for_rand_data, &random_entry);\n\n // Use the next region for random data (from the range 6..15)\n region_for_rand_data = (region_for_rand_data < 15) ? region_for_rand_data+1 : 6;\n\n random_entry.cfg = config;\n random_entry.addr = address;\n pmp_entry_write(region_for_rand_data, &random_entry);\n\n // Check\n struct pmp_entry_s readback;\n pmp_entry_read(region_for_rand_data, &readback);\n\n // An illegal PMP region configuration has been written and readback\n // this is an error\n //\n // -W- and -WX combinations are reserved except for when Smepmp is\n // present and mseccfg.MML=1. This test does not enable the latter\n // so the combinations are not legal.\n if (!pmp_is_cfg_legal(readback.cfg)) {\n printf(\" error, an illegal PMP configuration accepted by the core\\n\", readback.cfg);\n failed++;\n continue;\n }\n\n int exc;\n int cmp;\n int any_fail = 0;\n\n // Test writing. Write pattern from user mode and check if it was\n // successfully written.\n printf(\" testing W...\\n\");\n did_execute = 0;\n exc = 0;\n TRY { test_write(pattern, (uint32_t *)addr_lo, test_size); }\n CATCH { exc = 1; }\n END_TRY;\n\n cmp = memcmp((void*)addr_lo, pattern, test_size);\n if (cmp) {\n printf(\" data mismatch\\n\");\n } else {\n printf(\" data match\\n\");\n }\n\n if (did_execute && ((!w_eff && exc && cmp) || (w_eff && !exc && !cmp))) {\n printf(\" pass\\n\");\n } else {\n printf(\" fail\\n\");\n any_fail = 1;\n }\n\n // Test reading. Read area from user mode and compare against the\n // pattern\n printf(\" testing R...\\n\");\n\n // Write pattern\n if (!w_eff) {\n memcpy((void*)addr_lo, pattern, test_size);\n }\n\n did_execute = 0;\n exc = 0;\n TRY { cmp = test_read(pattern, (uint32_t *)addr_lo, test_size); }\n CATCH { exc = 1; }\n END_TRY;\n\n if (did_execute && ((!r_eff && exc) || (r_eff && !exc && !cmp))) {\n printf(\" pass\\n\");\n } else {\n printf(\" fail\\n\");\n any_fail = 1;\n }\n\n#ifdef TEST_X // TODO test execution rights\n\n void (*copied_test_exec)();\n\n random_entry.cfg = PMP_OFF;\n pmp_entry_write(region_for_rand_data, &random_entry);\n\n // Copy `test_exec` into the region\n // test_exec contains only 'ret' and any region is at least 4 bytes in size\n memcpy((void*)addr_lo, &test_exec, 4);\n\n random_entry.cfg = config;\n pmp_entry_write(region_for_rand_data, &random_entry);\n\n copied_test_exec = (void(*)())addr_lo;\n // Call a function placed in the designated area\n printf(\" testing X...\\n\");\n TRY {\n copied_test_exec();\n if (x_eff) {\n printf(\" pass\\n\");\n } else {\n printf(\" fail\\n\");\n any_fail = 1;\n }\n }\n CATCH {\n if (x_eff) {\n printf(\" fail\\n\");\n any_fail = 1;\n } else {\n printf(\" pass\\n\");\n }\n }\n END_TRY;\n#endif // TEST_X\n\n if (any_fail)\n printf(\" random data used:\\n addr: 0x%x,\\n cfg: 0x%x\\n\", rand_address[rand_test_i], rand_config[rand_test_i]);\n // Count fails\n failed += any_fail;\n }\n\n // .......................................................................\n\n printf(\" %d/%d passed\\n\", tid - failed, tid);\n int res = (failed == 0) ? 0 : -1;\n\n if (!res) printf(\"*** PASSED ***\\n\");\n else printf(\"*** FAILED ***\\n\");\n\n printf(\"Goodbye VeeR (M mode)\\n\");\n\n _exit(res);\n return res;\n}\n\n" }, { "path": "testbench/tests/pmp_random/pmp_random.mki", "content": "OFILES = crt0.o main.o pmp.o veer.o fault.o\nTEST_CFLAGS = -g -O3 -falign-functions=16\n" }, { "path": "testbench/tests/pmp_random/random_data.h", "content": "// This file was generated with generate_random.sh\n\n#define RANDOM_ITERATIONS 100\nconst uint32_t rand_address [] = {\n 0x0B83C7A8,\n 0x932F8872,\n 0x706A93B6,\n 0x70CB16E2,\n 0x4C44A3AC,\n 0x2A59C3F9,\n 0x25E88A72,\n 0x59E5C411,\n 0x337EF084,\n 0xA4468545,\n 0xEC472E58,\n 0x62186731,\n 0xABBBC86F,\n 0xF47EF033,\n 0x455B1035,\n 0x8EC8CAC1,\n 0x735DB130,\n 0x59A9DEE0,\n 0x836F7C3D,\n 0x1548C4E8,\n 0xE54DF150,\n 0x0352C401,\n 0x94E97F84,\n 0x3E39566D,\n 0x160BEFAE,\n 0x96872866,\n 0x2042BFA2,\n 0x66899B2A,\n 0x8EE30A51,\n 0x382ACF88,\n 0x45E5CBB8,\n 0xB7DA90F4,\n 0x2B7EAC8B,\n 0x72EB2667,\n 0x3A8F29E9,\n 0xFFE2EB46,\n 0x8F1938F4,\n 0x0B20F017,\n 0x48FB3EE6,\n 0x8F13D256,\n 0x9010A66A,\n 0x9EAAB8FE,\n 0x8172F809,\n 0x679D4C64,\n 0xA72CB05B,\n 0x6F37C8C0,\n 0xC5EF0789,\n 0x21ADC433,\n 0x14F798D9,\n 0xEABFC6CC,\n 0x4D125944,\n 0x0E7B7BF2,\n 0x65054B8D,\n 0x357F8EE9,\n 0x536E0B7A,\n 0xF42E6D48,\n 0x3B5A273B,\n 0x13A45B43,\n 0xFF2F7EC9,\n 0x8314E3FF,\n 0x6C7C5F2F,\n 0x95C0DADD,\n 0x94C6E8BD,\n 0x6ACCB9A6,\n 0x50E25BF3,\n 0x0C16BDAE,\n 0xE87B24FB,\n 0x60998517,\n 0xA29CB152,\n 0xED404EE7,\n 0x26389409,\n 0x7CFE1BC9,\n 0xB345E605,\n 0x6BEA3E3C,\n 0xB440CC05,\n 0xFD53FE05,\n 0xDF905CA7,\n 0xE8A5F3C4,\n 0x7BE1511F,\n 0x18937217,\n 0xA9301272,\n 0x4A820E35,\n 0xF9ABCD6C,\n 0x37C7DD03,\n 0x5FB938C7,\n 0xE208800E,\n 0xD5D9A331,\n 0xB8431823,\n 0x870E5AC9,\n 0x269EE21B,\n 0x6B04E971,\n 0x06225C28,\n 0x10AA81F0,\n 0x35A5705B,\n 0xFED7C35D,\n 0x8E1662BC,\n 0xC3A465BC,\n 0x33D21CEC,\n 0xD9B6A900,\n 0x2C52B111,\n};\nconst uint32_t rand_config [] = {\n 0xDCB82A76,\n 0xAC807B43,\n 0x69565CFC,\n 0x1A1BAD9A,\n 0x489B02B1,\n 0xF816E1A5,\n 0xA9A09ECD,\n 0x5B1665D6,\n 0xBFFB4CD6,\n 0x38B55DF1,\n 0x25D726FF,\n 0x5C10A678,\n 0x4F906A7C,\n 0xA389B951,\n 0xB0A9BED9,\n 0x168DE1E7,\n 0x6CAF04D2,\n 0x38BEE72E,\n 0x66C17FDB,\n 0x91DBA709,\n 0xC67F07D5,\n 0xB7F1294C,\n 0xE64F7874,\n 0x905BE8F4,\n 0x0B5F8D27,\n 0x77C09D20,\n 0x00764B23,\n 0x69BEAF8C,\n 0xDA9ABA16,\n 0x4717E8A7,\n 0x56FBDFD2,\n 0x267AF0D3,\n 0x3BBDB755,\n 0xE2E93169,\n 0xD2908EF7,\n 0x90B41356,\n 0x7D99B034,\n 0x25B56A53,\n 0x95E2C49F,\n 0x0C744355,\n 0xB013AE0A,\n 0x7AB0770A,\n 0x32E23805,\n 0x08229CC3,\n 0x2A15888A,\n 0x2F832722,\n 0x1E8C1189,\n 0x95119BCD,\n 0x05FA1928,\n 0x8E47DEAE,\n 0xE4C912B1,\n 0xD06BBE96,\n 0x4720C888,\n 0xFE1921DE,\n 0x78C857E4,\n 0x850B6219,\n 0xB8CDEEA5,\n 0xD957D370,\n 0xEF543FAE,\n 0x61DA6905,\n 0xB1954F69,\n 0xB21BC2DA,\n 0x1A135E21,\n 0x9A335436,\n 0x92A1555F,\n 0xEAAE8153,\n 0x48375B22,\n 0x418D23EA,\n 0x8D9B518F,\n 0x91EE2305,\n 0x6C5874EA,\n 0x908D875B,\n 0xB0E38A8F,\n 0x7B605FFD,\n 0xDDD51177,\n 0x7546C6C6,\n 0x45907EC7,\n 0x5DF27880,\n 0x304AF3FB,\n 0x190AE837,\n 0x7B6EF9DD,\n 0x98EEDFBC,\n 0x5639192B,\n 0xC008C201,\n 0xF291065C,\n 0xFAA092FA,\n 0x92C2BCEA,\n 0x93D8F8FC,\n 0xFC980FDD,\n 0x98D97B3F,\n 0x9C37EACB,\n 0xD99ABF8B,\n 0x81B3B931,\n 0xF9CA2C36,\n 0x3424181B,\n 0x98A4BF18,\n 0x2FD986FA,\n 0x379C629D,\n 0x0D1221E5,\n 0x7E3D572F,\n};\n" }, { "path": "testbench/tests/write_unaligned/crt0.s", "content": "# SPDX-License-Identifier: Apache-2.0\n\n.section .text.init\n.global _start\n_start:\n\n # Setup stack\n la sp, STACK\n\n # Call main()\n call main\n\n # Map exit code: == 0 - success, != 0 - failure\n mv a1, a0\n li a0, 0xff # ok\n beq a1, x0, _finish\n li a0, 1 # fail\n\n.global _finish\n_finish:\n la t0, tohost\n sb a0, 0(t0) # Signal testbench termination\n beq x0, x0, _finish\n .rept 10\n nop\n .endr\n\n.section .data.io\n.global tohost\ntohost: .word 0\n\n" }, { "path": "testbench/tests/write_unaligned/write_unaligned.c", "content": "#include \n\nint handler() __attribute__((section(\".handler\")));\n\nint handler() {\n return 0;\n}\n\nint main () {\n int (*func)() = (int (*)())0x70000001;\n volatile uint32_t csr_value;\n\n printf(\"jumping to 0x70000001\\n\");\n func();\n printf(\"jumping to 0x80001\\n\");\n func = 0x80001;\n func();\n printf(\"jumping to 0xe000001\\n\");\n func = 0xe000001;\n func();\n printf(\"jumping to 0x3fffffff\\n\");\n func = 0x3fffffff;\n func();\n printf(\"jumping to 0xa001\\n\");\n func = 0xa001;\n func();\n\n // read CSR at address 0x7FF (mscause)\n __asm__ volatile (\"csrr %0, 0x7FF\" : \"=r\"(csr_value));\n\n return 0;\n}\n" }, { "path": "testbench/tests/write_unaligned/write_unaligned.ld", "content": "/* SPDX-License-Identifier: Apache-2.0 */\n\nOUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n .handler : {\n KEEP(*(.handler))\n } > RAM = 0x0\n\n . = 0x80000000;\n .text : { *(.text.init*) *(.text*) }\n _end = .;\n .data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}\n .bss : { *(.bss) }\n . = 0xd0580000;\n .data.io . : { *(.data.io) }\n}\n" }, { "path": "testbench/tests/write_unaligned/write_unaligned.mki", "content": "# SPDX-License-Identifier: Apache-2.0\n\nOFILES = crt0.o write_unaligned.o printf.o\nTEST_CFLAGS = -g -O3 -falign-functions=16\n" }, { "path": "testbench/user_cells.sv", "content": "\n// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n// This file contains examples of user (technology specific) cells that can\n// be used thruought the core\n\n// Clock gate example\nmodule user_clock_gate (\n input logic CK,\n output logic Q,\n input logic EN\n);\n\n logic gate;\n\n initial gate = 0;\n always @(negedge CK)\n gate <= EN;\n\n assign Q = CK & gate;\n\nendmodule\n" }, { "path": "testbench/veer_wrapper.sv", "content": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2.0\n// Copyright (c) 2023 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//********************************************************************************\n\nmodule veer_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n input logic clk,\n input logic rst_l,\n input logic dbg_rst_l,\n input logic [31:1] rst_vec,\n input logic nmi_int,\n input logic [31:1] nmi_vec,\n input logic [31:1] jtag_id,\n\n\n output logic [31:0] trace_rv_i_insn_ip,\n output logic [31:0] trace_rv_i_address_ip,\n output logic trace_rv_i_valid_ip,\n output logic trace_rv_i_exception_ip,\n output logic [ 4:0] trace_rv_i_ecause_ip,\n output logic trace_rv_i_interrupt_ip,\n output logic [31:0] trace_rv_i_tval_ip,\n\n // Bus signals\n`ifdef RV_BUILD_AXI4\n //-------------------------- LSU AXI signals--------------------------\n // AXI Write Channels\n output logic lsu_axi_awvalid,\n input logic lsu_axi_awready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,\n output logic [ 31:0] lsu_axi_awaddr,\n output logic [ 3:0] lsu_axi_awregion,\n output logic [ 7:0] lsu_axi_awlen,\n output logic [ 2:0] lsu_axi_awsize,\n output logic [ 1:0] lsu_axi_awburst,\n output logic lsu_axi_awlock,\n output logic [ 3:0] lsu_axi_awcache,\n output logic [ 2:0] lsu_axi_awprot,\n output logic [ 3:0] lsu_axi_awqos,\n\n output logic lsu_axi_wvalid,\n input logic lsu_axi_wready,\n output logic [63:0] lsu_axi_wdata,\n output logic [ 7:0] lsu_axi_wstrb,\n output logic lsu_axi_wlast,\n\n input logic lsu_axi_bvalid,\n output logic lsu_axi_bready,\n input logic [ 1:0] lsu_axi_bresp,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,\n\n // AXI Read Channels\n output logic lsu_axi_arvalid,\n input logic lsu_axi_arready,\n output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,\n output logic [ 31:0] lsu_axi_araddr,\n output logic [ 3:0] lsu_axi_arregion,\n output logic [ 7:0] lsu_axi_arlen,\n output logic [ 2:0] lsu_axi_arsize,\n output logic [ 1:0] lsu_axi_arburst,\n output logic lsu_axi_arlock,\n output logic [ 3:0] lsu_axi_arcache,\n output logic [ 2:0] lsu_axi_arprot,\n output logic [ 3:0] lsu_axi_arqos,\n\n input logic lsu_axi_rvalid,\n output logic lsu_axi_rready,\n input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,\n input logic [ 63:0] lsu_axi_rdata,\n input logic [ 1:0] lsu_axi_rresp,\n input logic lsu_axi_rlast,\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n output logic ifu_axi_awvalid,\n input logic ifu_axi_awready,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,\n output logic [ 31:0] ifu_axi_awaddr,\n output logic [ 3:0] ifu_axi_awregion,\n output logic [ 7:0] ifu_axi_awlen,\n output logic [ 2:0] ifu_axi_awsize,\n output logic [ 1:0] ifu_axi_awburst,\n output logic ifu_axi_awlock,\n output logic [ 3:0] ifu_axi_awcache,\n output logic [ 2:0] ifu_axi_awprot,\n output logic [ 3:0] ifu_axi_awqos,\n\n output logic ifu_axi_wvalid,\n input logic ifu_axi_wready,\n output logic [63:0] ifu_axi_wdata,\n output logic [ 7:0] ifu_axi_wstrb,\n output logic ifu_axi_wlast,\n\n input logic ifu_axi_bvalid,\n output logic ifu_axi_bready,\n input logic [ 1:0] ifu_axi_bresp,\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,\n\n // AXI Read Channels\n output logic ifu_axi_arvalid,\n input logic ifu_axi_arready,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,\n output logic [ 31:0] ifu_axi_araddr,\n output logic [ 3:0] ifu_axi_arregion,\n output logic [ 7:0] ifu_axi_arlen,\n output logic [ 2:0] ifu_axi_arsize,\n output logic [ 1:0] ifu_axi_arburst,\n output logic ifu_axi_arlock,\n output logic [ 3:0] ifu_axi_arcache,\n output logic [ 2:0] ifu_axi_arprot,\n output logic [ 3:0] ifu_axi_arqos,\n\n input logic ifu_axi_rvalid,\n output logic ifu_axi_rready,\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,\n input logic [ 63:0] ifu_axi_rdata,\n input logic [ 1:0] ifu_axi_rresp,\n input logic ifu_axi_rlast,\n\n //-------------------------- SB AXI signals--------------------------\n // AXI Write Channels\n output logic sb_axi_awvalid,\n input logic sb_axi_awready,\n output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,\n output logic [ 31:0] sb_axi_awaddr,\n output logic [ 3:0] sb_axi_awregion,\n output logic [ 7:0] sb_axi_awlen,\n output logic [ 2:0] sb_axi_awsize,\n output logic [ 1:0] sb_axi_awburst,\n output logic sb_axi_awlock,\n output logic [ 3:0] sb_axi_awcache,\n output logic [ 2:0] sb_axi_awprot,\n output logic [ 3:0] sb_axi_awqos,\n\n output logic sb_axi_wvalid,\n input logic sb_axi_wready,\n output logic [63:0] sb_axi_wdata,\n output logic [ 7:0] sb_axi_wstrb,\n output logic sb_axi_wlast,\n\n input logic sb_axi_bvalid,\n output logic sb_axi_bready,\n input logic [ 1:0] sb_axi_bresp,\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,\n\n // AXI Read Channels\n output logic sb_axi_arvalid,\n input logic sb_axi_arready,\n output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,\n output logic [ 31:0] sb_axi_araddr,\n output logic [ 3:0] sb_axi_arregion,\n output logic [ 7:0] sb_axi_arlen,\n output logic [ 2:0] sb_axi_arsize,\n output logic [ 1:0] sb_axi_arburst,\n output logic sb_axi_arlock,\n output logic [ 3:0] sb_axi_arcache,\n output logic [ 2:0] sb_axi_arprot,\n output logic [ 3:0] sb_axi_arqos,\n\n input logic sb_axi_rvalid,\n output logic sb_axi_rready,\n input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,\n input logic [ 63:0] sb_axi_rdata,\n input logic [ 1:0] sb_axi_rresp,\n input logic sb_axi_rlast,\n\n //-------------------------- DMA AXI signals--------------------------\n // AXI Write Channels\n input logic dma_axi_awvalid,\n output logic dma_axi_awready,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,\n input logic [ 31:0] dma_axi_awaddr,\n input logic [ 2:0] dma_axi_awsize,\n input logic [ 2:0] dma_axi_awprot,\n input logic [ 7:0] dma_axi_awlen,\n input logic [ 1:0] dma_axi_awburst,\n\n\n input logic dma_axi_wvalid,\n output logic dma_axi_wready,\n input logic [63:0] dma_axi_wdata,\n input logic [ 7:0] dma_axi_wstrb,\n input logic dma_axi_wlast,\n\n output logic dma_axi_bvalid,\n input logic dma_axi_bready,\n output logic [ 1:0] dma_axi_bresp,\n output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,\n\n // AXI Read Channels\n input logic dma_axi_arvalid,\n output logic dma_axi_arready,\n input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,\n input logic [ 31:0] dma_axi_araddr,\n input logic [ 2:0] dma_axi_arsize,\n input logic [ 2:0] dma_axi_arprot,\n input logic [ 7:0] dma_axi_arlen,\n input logic [ 1:0] dma_axi_arburst,\n\n output logic dma_axi_rvalid,\n input logic dma_axi_rready,\n output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,\n output logic [ 63:0] dma_axi_rdata,\n output logic [ 1:0] dma_axi_rresp,\n output logic dma_axi_rlast,\n`endif\n\n`ifdef RV_BUILD_AHB_LITE\n //// AHB LITE BUS\n output logic [31:0] haddr,\n output logic [ 2:0] hburst,\n output logic hmastlock,\n output logic [ 3:0] hprot,\n output logic [ 2:0] hsize,\n output logic [ 1:0] htrans,\n output logic hwrite,\n\n input logic [63:0] hrdata,\n input logic hready,\n input logic hresp,\n\n // LSU AHB Master\n output logic [31:0] lsu_haddr,\n output logic [ 2:0] lsu_hburst,\n output logic lsu_hmastlock,\n output logic [ 3:0] lsu_hprot,\n output logic [ 2:0] lsu_hsize,\n output logic [ 1:0] lsu_htrans,\n output logic lsu_hwrite,\n output logic [63:0] lsu_hwdata,\n\n input logic [63:0] lsu_hrdata,\n input logic lsu_hready,\n input logic lsu_hresp,\n // Debug Syster Bus AHB\n output logic [31:0] sb_haddr,\n output logic [ 2:0] sb_hburst,\n output logic sb_hmastlock,\n output logic [ 3:0] sb_hprot,\n output logic [ 2:0] sb_hsize,\n output logic [ 1:0] sb_htrans,\n output logic sb_hwrite,\n output logic [63:0] sb_hwdata,\n\n input logic [63:0] sb_hrdata,\n input logic sb_hready,\n input logic sb_hresp,\n\n // DMA Slave\n input logic dma_hsel,\n input logic [31:0] dma_haddr,\n input logic [ 2:0] dma_hburst,\n input logic dma_hmastlock,\n input logic [ 3:0] dma_hprot,\n input logic [ 2:0] dma_hsize,\n input logic [ 1:0] dma_htrans,\n input logic dma_hwrite,\n input logic [63:0] dma_hwdata,\n input logic dma_hreadyin,\n\n output logic [63:0] dma_hrdata,\n output logic dma_hreadyout,\n output logic dma_hresp,\n`endif\n // clk ratio signals\n input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface\n input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface\n input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface\n input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface\n\n input logic timer_int,\n input logic soft_int,\n input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,\n\n output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc\n output logic dec_tlu_perfcnt1,\n output logic dec_tlu_perfcnt2,\n output logic dec_tlu_perfcnt3,\n\n // ports added by the soc team\n input logic jtag_tck, // JTAG clk\n input logic jtag_tms, // JTAG TMS\n input logic jtag_tdi, // JTAG tdi\n input logic jtag_trst_n, // JTAG Reset\n output logic jtag_tdo, // JTAG TDO\n output logic jtag_tdoEn, // JTAG Test Data Output enable\n\n input logic [31:4] core_id,\n\n // Memory Export Interface\n output logic mem_clk,\n // ICCM\n output logic [pt.ICCM_NUM_BANKS-1:0] iccm_clken,\n output logic [pt.ICCM_NUM_BANKS-1:0] iccm_wren_bank,\n output logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank,\n output logic [pt.ICCM_NUM_BANKS-1:0][31:0] iccm_bank_wr_data,\n output logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc,\n input logic [pt.ICCM_NUM_BANKS-1:0][31:0] iccm_bank_dout,\n input logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc,\n // DCCM\n output logic [pt.DCCM_NUM_BANKS-1:0] dccm_clken,\n output logic [pt.DCCM_NUM_BANKS-1:0] dccm_wren_bank,\n output logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank,\n output logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank,\n output logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-pt.DCCM_DATA_WIDTH-1:0] dccm_wr_ecc_bank,\n input logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout,\n input logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_FDATA_WIDTH-pt.DCCM_DATA_WIDTH-1:0] dccm_bank_ecc,\n\n // ICache Export Interface\n // ICache Data\n output logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] ic_b_sb_wren,\n output logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] ic_b_sb_bit_en_vec,\n output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_sb_wr_data,\n output logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q,\n output logic [pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final,\n output logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final_up,\n input logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] wb_packeddout_pre,\n input logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][71-1:0] wb_dout_pre_up,\n // ICache Tag\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_clken_final,\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_wren_q,\n output logic [(26*pt.ICACHE_NUM_WAYS)-1 :0] ic_tag_wren_biten_vec,\n output logic [25:0] ic_tag_wr_data,\n output logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO] ic_rw_addr_q,\n input logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] ic_tag_data_raw_pre,\n input logic [(26*pt.ICACHE_NUM_WAYS)-1 :0] ic_tag_data_raw_packed_pre,\n\n // ICCM/DCCM ECC status\n output logic iccm_ecc_single_error,\n output logic iccm_ecc_double_error,\n output logic dccm_ecc_single_error,\n output logic dccm_ecc_double_error,\n\n`ifdef RV_LOCKSTEP_ENABLE\n input logic disable_corruption_detection_i,\n input logic lockstep_err_injection_en_i,\n output logic corruption_detected_o,\n`endif\n\n // external MPC halt/run interface\n input logic mpc_debug_halt_req, // Async halt request\n input logic mpc_debug_run_req, // Async run request\n input logic mpc_reset_run_req, // Run/halt after reset\n output logic mpc_debug_halt_ack, // Halt ack\n output logic mpc_debug_run_ack, // Run ack\n output logic debug_brkpt_status, // debug breakpoint\n\n input logic i_cpu_halt_req, // Async halt req to CPU\n output logic o_cpu_halt_ack, // core response to halt\n output logic o_cpu_halt_status, // 1'b1 indicates core is halted\n output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request\n input logic i_cpu_run_req, // Async restart req to CPU\n output logic o_cpu_run_ack, // Core response to run req\n input logic scan_mode, // To enable scan mode\n input logic mbist_mode, // to enable mbist\n\n input logic dmi_core_enable,\n // DMI port for uncore\n input logic dmi_uncore_enable,\n output logic dmi_uncore_en,\n output logic dmi_uncore_wr_en,\n output logic [ 6:0] dmi_uncore_addr,\n output logic [31:0] dmi_uncore_wdata,\n input logic [31:0] dmi_uncore_rdata,\n\n output logic dmi_active\n);\n\n el2_mem_if mem_export ();\n assign mem_clk = mem_export.clk;\n assign dccm_clken = mem_export.dccm_clken;\n assign dccm_wren_bank = mem_export.dccm_wren_bank;\n assign dccm_addr_bank = mem_export.dccm_addr_bank;\n assign dccm_wr_data_bank = mem_export.dccm_wr_data_bank;\n assign dccm_wr_ecc_bank = mem_export.dccm_wr_ecc_bank;\n assign mem_export.dccm_bank_dout = dccm_bank_dout;\n assign mem_export.dccm_bank_ecc = dccm_bank_ecc;\n assign iccm_clken = mem_export.iccm_clken;\n assign iccm_wren_bank = mem_export.iccm_wren_bank;\n assign iccm_addr_bank = mem_export.iccm_addr_bank;\n assign iccm_bank_wr_data = mem_export.iccm_bank_wr_data;\n assign iccm_bank_wr_ecc = mem_export.iccm_bank_wr_ecc;\n assign mem_export.iccm_bank_dout = iccm_bank_dout;\n assign mem_export.iccm_bank_ecc = iccm_bank_ecc;\n // ICache Data\n assign ic_b_sb_wren = mem_export.ic_b_sb_wren;\n assign ic_b_sb_bit_en_vec = mem_export.ic_b_sb_bit_en_vec;\n assign ic_sb_wr_data = mem_export.ic_sb_wr_data;\n assign ic_rw_addr_bank_q = mem_export.ic_rw_addr_bank_q;\n assign ic_bank_way_clken_final = mem_export.ic_bank_way_clken_final;\n assign ic_bank_way_clken_final_up = mem_export.ic_bank_way_clken_final_up;\n assign mem_export.wb_packeddout_pre = wb_packeddout_pre;\n assign mem_export.wb_dout_pre_up = wb_dout_pre_up;\n // ICache Data\n assign ic_tag_clken_final = mem_export.ic_tag_clken_final;\n assign ic_tag_wren_q = mem_export.ic_tag_wren_q;\n assign ic_tag_wren_biten_vec = mem_export.ic_tag_wren_biten_vec;\n assign ic_tag_wr_data = mem_export.ic_tag_wr_data;\n assign ic_rw_addr_q = mem_export.ic_rw_addr_q;\n assign mem_export.ic_tag_data_raw_packed_pre = ic_tag_data_raw_packed_pre;\n assign mem_export.ic_tag_data_raw_pre = ic_tag_data_raw_pre;\n\n el2_veer_wrapper rvtop (\n .el2_mem_export(mem_export.veer_sram_src),\n .el2_icache_export(mem_export.veer_icache_src),\n .dmi_core_enable(dmi_core_enable),\n .dmi_active(dmi_active),\n .*\n );\n\nendmodule\n" }, { "path": "tools/JSON.pm", "content": "package JSON;\n\n\nuse strict;\nuse Carp ();\nuse base qw(Exporter);\n@JSON::EXPORT = qw(from_json to_json jsonToObj objToJson encode_json decode_json);\n\nBEGIN {\n $JSON::VERSION = '2.53';\n $JSON::DEBUG = 0 unless (defined $JSON::DEBUG);\n $JSON::DEBUG = $ENV{ PERL_JSON_DEBUG } if exists $ENV{ PERL_JSON_DEBUG };\n}\n\nmy $Module_XS = 'JSON::XS';\nmy $Module_PP = 'JSON::PP';\nmy $Module_bp = 'JSON::backportPP'; # included in JSON distribution\nmy $PP_Version = '2.27200';\nmy $XS_Version = '2.27';\n\n\n# XS and PP common methods\n\nmy @PublicMethods = qw/\n ascii latin1 utf8 pretty indent space_before space_after relaxed canonical allow_nonref\n allow_blessed convert_blessed filter_json_object filter_json_single_key_object\n shrink max_depth max_size encode decode decode_prefix allow_unknown\n/;\n\nmy @Properties = qw/\n ascii latin1 utf8 indent space_before space_after relaxed canonical allow_nonref\n allow_blessed convert_blessed shrink max_depth max_size allow_unknown\n/;\n\nmy @XSOnlyMethods = qw//; # Currently nothing\n\nmy @PPOnlyMethods = qw/\n indent_length sort_by\n allow_singlequote allow_bignum loose allow_barekey escape_slash as_nonblessed\n/; # JSON::PP specific\n\n\n# used in _load_xs and _load_pp ($INSTALL_ONLY is not used currently)\nmy $_INSTALL_DONT_DIE = 1; # When _load_xs fails to load XS, don't die.\nmy $_INSTALL_ONLY = 2; # Don't call _set_methods()\nmy $_ALLOW_UNSUPPORTED = 0;\nmy $_UNIV_CONV_BLESSED = 0;\nmy $_USSING_bpPP = 0;\n\n\n# Check the environment variable to decide worker module.\n\nunless ($JSON::Backend) {\n $JSON::DEBUG and Carp::carp(\"Check used worker module...\");\n\n my $backend = exists $ENV{PERL_JSON_BACKEND} ? $ENV{PERL_JSON_BACKEND} : 1;\n\n if ($backend eq '1' or $backend =~ /JSON::XS\\s*,\\s*JSON::PP/) {\n _load_xs($_INSTALL_DONT_DIE) or _load_pp();\n }\n elsif ($backend eq '0' or $backend eq 'JSON::PP') {\n _load_pp();\n }\n elsif ($backend eq '2' or $backend eq 'JSON::XS') {\n _load_xs();\n }\n elsif ($backend eq 'JSON::backportPP') {\n $_USSING_bpPP = 1;\n _load_pp();\n }\n else {\n Carp::croak \"The value of environmental variable 'PERL_JSON_BACKEND' is invalid.\";\n }\n}\n\n\nsub import {\n my $pkg = shift;\n my @what_to_export;\n my $no_export;\n\n for my $tag (@_) {\n if ($tag eq '-support_by_pp') {\n if (!$_ALLOW_UNSUPPORTED++) {\n JSON::Backend::XS\n ->support_by_pp(@PPOnlyMethods) if ($JSON::Backend eq $Module_XS);\n }\n next;\n }\n elsif ($tag eq '-no_export') {\n $no_export++, next;\n }\n elsif ( $tag eq '-convert_blessed_universally' ) {\n eval q|\n require B;\n *UNIVERSAL::TO_JSON = sub {\n my $b_obj = B::svref_2object( $_[0] );\n return $b_obj->isa('B::HV') ? { %{ $_[0] } }\n : $b_obj->isa('B::AV') ? [ @{ $_[0] } ]\n : undef\n ;\n }\n | if ( !$_UNIV_CONV_BLESSED++ );\n next;\n }\n push @what_to_export, $tag;\n }\n\n return if ($no_export);\n\n __PACKAGE__->export_to_level(1, $pkg, @what_to_export);\n}\n\n\n# OBSOLETED\n\nsub jsonToObj {\n my $alternative = 'from_json';\n if (defined $_[0] and UNIVERSAL::isa($_[0], 'JSON')) {\n shift @_; $alternative = 'decode';\n }\n Carp::carp \"'jsonToObj' will be obsoleted. Please use '$alternative' instead.\";\n return JSON::from_json(@_);\n};\n\nsub objToJson {\n my $alternative = 'to_json';\n if (defined $_[0] and UNIVERSAL::isa($_[0], 'JSON')) {\n shift @_; $alternative = 'encode';\n }\n Carp::carp \"'objToJson' will be obsoleted. Please use '$alternative' instead.\";\n JSON::to_json(@_);\n};\n\n\n# INTERFACES\n\nsub to_json ($@) {\n if (\n ref($_[0]) eq 'JSON'\n or (@_ > 2 and $_[0] eq 'JSON')\n ) {\n Carp::croak \"to_json should not be called as a method.\";\n }\n my $json = new JSON;\n\n if (@_ == 2 and ref $_[1] eq 'HASH') {\n my $opt = $_[1];\n for my $method (keys %$opt) {\n $json->$method( $opt->{$method} );\n }\n }\n\n $json->encode($_[0]);\n}\n\n\nsub from_json ($@) {\n if ( ref($_[0]) eq 'JSON' or $_[0] eq 'JSON' ) {\n Carp::croak \"from_json should not be called as a method.\";\n }\n my $json = new JSON;\n\n if (@_ == 2 and ref $_[1] eq 'HASH') {\n my $opt = $_[1];\n for my $method (keys %$opt) {\n $json->$method( $opt->{$method} );\n }\n }\n\n return $json->decode( $_[0] );\n}\n\n\nsub true { $JSON::true }\n\nsub false { $JSON::false }\n\nsub null { undef; }\n\n\nsub require_xs_version { $XS_Version; }\n\nsub backend {\n my $proto = shift;\n $JSON::Backend;\n}\n\n#*module = *backend;\n\n\nsub is_xs {\n return $_[0]->module eq $Module_XS;\n}\n\n\nsub is_pp {\n return not $_[0]->xs;\n}\n\n\nsub pureperl_only_methods { @PPOnlyMethods; }\n\n\nsub property {\n my ($self, $name, $value) = @_;\n\n if (@_ == 1) {\n my %props;\n for $name (@Properties) {\n my $method = 'get_' . $name;\n if ($name eq 'max_size') {\n my $value = $self->$method();\n $props{$name} = $value == 1 ? 0 : $value;\n next;\n }\n $props{$name} = $self->$method();\n }\n return \\%props;\n }\n elsif (@_ > 3) {\n Carp::croak('property() can take only the option within 2 arguments.');\n }\n elsif (@_ == 2) {\n if ( my $method = $self->can('get_' . $name) ) {\n if ($name eq 'max_size') {\n my $value = $self->$method();\n return $value == 1 ? 0 : $value;\n }\n $self->$method();\n }\n }\n else {\n $self->$name($value);\n }\n\n}\n\n\n\n# INTERNAL\n\nsub _load_xs {\n my $opt = shift;\n\n $JSON::DEBUG and Carp::carp \"Load $Module_XS.\";\n\n # if called after install module, overload is disable.... why?\n JSON::Boolean::_overrride_overload($Module_XS);\n JSON::Boolean::_overrride_overload($Module_PP);\n\n eval qq|\n use $Module_XS $XS_Version ();\n |;\n\n if ($@) {\n if (defined $opt and $opt & $_INSTALL_DONT_DIE) {\n $JSON::DEBUG and Carp::carp \"Can't load $Module_XS...($@)\";\n return 0;\n }\n Carp::croak $@;\n }\n\n unless (defined $opt and $opt & $_INSTALL_ONLY) {\n _set_module( $JSON::Backend = $Module_XS );\n my $data = join(\"\", ); # this code is from Jcode 2.xx.\n close(DATA);\n eval $data;\n JSON::Backend::XS->init;\n }\n\n return 1;\n};\n\n\nsub _load_pp {\n my $opt = shift;\n my $backend = $_USSING_bpPP ? $Module_bp : $Module_PP;\n\n $JSON::DEBUG and Carp::carp \"Load $backend.\";\n\n # if called after install module, overload is disable.... why?\n JSON::Boolean::_overrride_overload($Module_XS);\n JSON::Boolean::_overrride_overload($backend);\n\n if ( $_USSING_bpPP ) {\n eval qq| require $backend |;\n }\n else {\n eval qq| use $backend $PP_Version () |;\n }\n\n if ($@) {\n if ( $backend eq $Module_PP ) {\n $JSON::DEBUG and Carp::carp \"Can't load $Module_PP ($@), so try to load $Module_bp\";\n $_USSING_bpPP++;\n $backend = $Module_bp;\n JSON::Boolean::_overrride_overload($backend);\n local $^W; # if PP installed but invalid version, backportPP redifines methods.\n eval qq| require $Module_bp |;\n }\n Carp::croak $@ if $@;\n }\n\n unless (defined $opt and $opt & $_INSTALL_ONLY) {\n _set_module( $JSON::Backend = $Module_PP ); # even if backportPP, set $Backend with 'JSON::PP'\n JSON::Backend::PP->init;\n }\n};\n\n\nsub _set_module {\n return if defined $JSON::true;\n\n my $module = shift;\n\n local $^W;\n no strict qw(refs);\n\n $JSON::true = ${\"$module\\::true\"};\n $JSON::false = ${\"$module\\::false\"};\n\n push @JSON::ISA, $module;\n push @{\"$module\\::Boolean::ISA\"}, qw(JSON::Boolean);\n\n *{\"JSON::is_bool\"} = \\&{\"$module\\::is_bool\"};\n\n for my $method ($module eq $Module_XS ? @PPOnlyMethods : @XSOnlyMethods) {\n *{\"JSON::$method\"} = sub {\n Carp::carp(\"$method is not supported in $module.\");\n $_[0];\n };\n }\n\n return 1;\n}\n\n\n\n#\n# JSON Boolean\n#\n\npackage JSON::Boolean;\n\nmy %Installed;\n\nsub _overrride_overload {\n return if ($Installed{ $_[0] }++);\n\n my $boolean = $_[0] . '::Boolean';\n\n eval sprintf(q|\n package %s;\n use overload (\n '\"\"' => sub { ${$_[0]} == 1 ? 'true' : 'false' },\n 'eq' => sub {\n my ($obj, $op) = ref ($_[0]) ? ($_[0], $_[1]) : ($_[1], $_[0]);\n if ($op eq 'true' or $op eq 'false') {\n return \"$obj\" eq 'true' ? 'true' eq $op : 'false' eq $op;\n }\n else {\n return $obj ? 1 == $op : 0 == $op;\n }\n },\n );\n |, $boolean);\n\n if ($@) { Carp::croak $@; }\n\n return 1;\n}\n\n\n#\n# Helper classes for Backend Module (PP)\n#\n\npackage JSON::Backend::PP;\n\nsub init {\n local $^W;\n no strict qw(refs); # this routine may be called after JSON::Backend::XS init was called.\n *{\"JSON::decode_json\"} = \\&{\"JSON::PP::decode_json\"};\n *{\"JSON::encode_json\"} = \\&{\"JSON::PP::encode_json\"};\n *{\"JSON::PP::is_xs\"} = sub { 0 };\n *{\"JSON::PP::is_pp\"} = sub { 1 };\n return 1;\n}\n\n#\n# To save memory, the below lines are read only when XS backend is used.\n#\n\npackage JSON;\n\n1;\n__DATA__\n\n\n#\n# Helper classes for Backend Module (XS)\n#\n\npackage JSON::Backend::XS;\n\nuse constant INDENT_LENGTH_FLAG => 15 << 12;\n\nuse constant UNSUPPORTED_ENCODE_FLAG => {\n ESCAPE_SLASH => 0x00000010,\n ALLOW_BIGNUM => 0x00000020,\n AS_NONBLESSED => 0x00000040,\n EXPANDED => 0x10000000, # for developer's\n};\n\nuse constant UNSUPPORTED_DECODE_FLAG => {\n LOOSE => 0x00000001,\n ALLOW_BIGNUM => 0x00000002,\n ALLOW_BAREKEY => 0x00000004,\n ALLOW_SINGLEQUOTE => 0x00000008,\n EXPANDED => 0x20000000, # for developer's\n};\n\n\nsub init {\n local $^W;\n no strict qw(refs);\n *{\"JSON::decode_json\"} = \\&{\"JSON::XS::decode_json\"};\n *{\"JSON::encode_json\"} = \\&{\"JSON::XS::encode_json\"};\n *{\"JSON::XS::is_xs\"} = sub { 1 };\n *{\"JSON::XS::is_pp\"} = sub { 0 };\n return 1;\n}\n\n\nsub support_by_pp {\n my ($class, @methods) = @_;\n\n local $^W;\n no strict qw(refs);\n\n my $JSON_XS_encode_orignal = \\&JSON::XS::encode;\n my $JSON_XS_decode_orignal = \\&JSON::XS::decode;\n my $JSON_XS_incr_parse_orignal = \\&JSON::XS::incr_parse;\n\n *JSON::XS::decode = \\&JSON::Backend::XS::Supportable::_decode;\n *JSON::XS::encode = \\&JSON::Backend::XS::Supportable::_encode;\n *JSON::XS::incr_parse = \\&JSON::Backend::XS::Supportable::_incr_parse;\n\n *{JSON::XS::_original_decode} = $JSON_XS_decode_orignal;\n *{JSON::XS::_original_encode} = $JSON_XS_encode_orignal;\n *{JSON::XS::_original_incr_parse} = $JSON_XS_incr_parse_orignal;\n\n push @JSON::Backend::XS::Supportable::ISA, 'JSON';\n\n my $pkg = 'JSON::Backend::XS::Supportable';\n\n *{JSON::new} = sub {\n my $proto = new JSON::XS; $$proto = 0;\n bless $proto, $pkg;\n };\n\n\n for my $method (@methods) {\n my $flag = uc($method);\n my $type |= (UNSUPPORTED_ENCODE_FLAG->{$flag} || 0);\n $type |= (UNSUPPORTED_DECODE_FLAG->{$flag} || 0);\n\n next unless($type);\n\n $pkg->_make_unsupported_method($method => $type);\n }\n\n push @{\"JSON::XS::Boolean::ISA\"}, qw(JSON::PP::Boolean);\n push @{\"JSON::PP::Boolean::ISA\"}, qw(JSON::Boolean);\n\n $JSON::DEBUG and Carp::carp(\"set -support_by_pp mode.\");\n\n return 1;\n}\n\n\n\n\n#\n# Helper classes for XS\n#\n\npackage JSON::Backend::XS::Supportable;\n\n$Carp::Internal{'JSON::Backend::XS::Supportable'} = 1;\n\nsub _make_unsupported_method {\n my ($pkg, $method, $type) = @_;\n\n local $^W;\n no strict qw(refs);\n\n *{\"$pkg\\::$method\"} = sub {\n local $^W;\n if (defined $_[1] ? $_[1] : 1) {\n ${$_[0]} |= $type;\n }\n else {\n ${$_[0]} &= ~$type;\n }\n $_[0];\n };\n\n *{\"$pkg\\::get_$method\"} = sub {\n ${$_[0]} & $type ? 1 : '';\n };\n\n}\n\n\nsub _set_for_pp {\n JSON::_load_pp( $_INSTALL_ONLY );\n\n my $type = shift;\n my $pp = new JSON::PP;\n my $prop = $_[0]->property;\n\n for my $name (keys %$prop) {\n $pp->$name( $prop->{$name} ? $prop->{$name} : 0 );\n }\n\n my $unsupported = $type eq 'encode' ? JSON::Backend::XS::UNSUPPORTED_ENCODE_FLAG\n : JSON::Backend::XS::UNSUPPORTED_DECODE_FLAG;\n my $flags = ${$_[0]} || 0;\n\n for my $name (keys %$unsupported) {\n next if ($name eq 'EXPANDED'); # for developer's\n my $enable = ($flags & $unsupported->{$name}) ? 1 : 0;\n my $method = lc $name;\n $pp->$method($enable);\n }\n\n $pp->indent_length( $_[0]->get_indent_length );\n\n return $pp;\n}\n\nsub _encode { # using with PP encod\n if (${$_[0]}) {\n _set_for_pp('encode' => @_)->encode($_[1]);\n }\n else {\n $_[0]->_original_encode( $_[1] );\n }\n}\n\n\nsub _decode { # if unsupported-flag is set, use PP\n if (${$_[0]}) {\n _set_for_pp('decode' => @_)->decode($_[1]);\n }\n else {\n $_[0]->_original_decode( $_[1] );\n }\n}\n\n\nsub decode_prefix { # if unsupported-flag is set, use PP\n _set_for_pp('decode' => @_)->decode_prefix($_[1]);\n}\n\n\nsub _incr_parse {\n if (${$_[0]}) {\n _set_for_pp('decode' => @_)->incr_parse($_[1]);\n }\n else {\n $_[0]->_original_incr_parse( $_[1] );\n }\n}\n\n\nsub get_indent_length {\n ${$_[0]} << 4 >> 16;\n}\n\n\nsub indent_length {\n my $length = $_[1];\n\n if (!defined $length or $length > 15 or $length < 0) {\n Carp::carp \"The acceptable range of indent_length() is 0 to 15.\";\n }\n else {\n local $^W;\n $length <<= 12;\n ${$_[0]} &= ~ JSON::Backend::XS::INDENT_LENGTH_FLAG;\n ${$_[0]} |= $length;\n *JSON::XS::encode = \\&JSON::Backend::XS::Supportable::_encode;\n }\n\n $_[0];\n}\n\n\n1;\n__END__\n\n=head1 NAME\n\nJSON - JSON (JavaScript Object Notation) encoder/decoder\n\n=head1 SYNOPSIS\n\n use JSON; # imports encode_json, decode_json, to_json and from_json.\n\n # simple and fast interfaces (expect/generate UTF-8)\n\n $utf8_encoded_json_text = encode_json $perl_hash_or_arrayref;\n $perl_hash_or_arrayref = decode_json $utf8_encoded_json_text;\n\n # OO-interface\n\n $json = JSON->new->allow_nonref;\n\n $json_text = $json->encode( $perl_scalar );\n $perl_scalar = $json->decode( $json_text );\n\n $pretty_printed = $json->pretty->encode( $perl_scalar ); # pretty-printing\n\n # If you want to use PP only support features, call with '-support_by_pp'\n # When XS unsupported feature is enable, using PP (de|en)code instead of XS ones.\n\n use JSON -support_by_pp;\n\n # option-acceptable interfaces (expect/generate UNICODE by default)\n\n $json_text = to_json( $perl_scalar, { ascii => 1, pretty => 1 } );\n $perl_scalar = from_json( $json_text, { utf8 => 1 } );\n\n # Between (en|de)code_json and (to|from)_json, if you want to write\n # a code which communicates to an outer world (encoded in UTF-8),\n # recommend to use (en|de)code_json.\n\n=head1 VERSION\n\n 2.53\n\nThis version is compatible with JSON::XS B<2.27> and later.\n\n\n=head1 NOTE\n\nJSON::PP was inculded in C distribution.\nIt comes to be a perl core module in Perl 5.14.\nAnd L will be split away it.\n\nC distribution will inculde yet another JSON::PP modules.\nThey are JSNO::backportPP and so on. JSON.pm should work as it did at all.\n\n=head1 DESCRIPTION\n\n ************************** CAUTION ********************************\n * This is 'JSON module version 2' and there are many differences *\n * to version 1.xx *\n * Please check your applications useing old version. *\n * See to 'INCOMPATIBLE CHANGES TO OLD VERSION' *\n *******************************************************************\n\nJSON (JavaScript Object Notation) is a simple data format.\nSee to L and C(L).\n\nThis module converts Perl data structures to JSON and vice versa using either\nL or L.\n\nJSON::XS is the fastest and most proper JSON module on CPAN which must be\ncompiled and installed in your environment.\nJSON::PP is a pure-Perl module which is bundled in this distribution and\nhas a strong compatibility to JSON::XS.\n\nThis module try to use JSON::XS by default and fail to it, use JSON::PP instead.\nSo its features completely depend on JSON::XS or JSON::PP.\n\nSee to L.\n\nTo distinguish the module name 'JSON' and the format type JSON,\nthe former is quoted by CEE (its results vary with your using media),\nand the latter is left just as it is.\n\nModule name : C\n\nFormat type : JSON\n\n=head2 FEATURES\n\n=over\n\n=item * correct unicode handling\n\nThis module (i.e. backend modules) knows how to handle Unicode, documents\nhow and when it does so, and even documents what \"correct\" means.\n\nEven though there are limitations, this feature is available since Perl version 5.6.\n\nJSON::XS requires Perl 5.8.2 (but works correctly in 5.8.8 or later), so in older versions\nC sholud call JSON::PP as the backend which can be used since Perl 5.005.\n\nWith Perl 5.8.x JSON::PP works, but from 5.8.0 to 5.8.2, because of a Perl side problem,\nJSON::PP works slower in the versions. And in 5.005, the Unicode handling is not available.\nSee to L for more information.\n\nSee also to L\nand L.\n\n\n=item * round-trip integrity\n\nWhen you serialise a perl data structure using only data types supported\nby JSON and Perl, the deserialised data structure is identical on the Perl\nlevel. (e.g. the string \"2.0\" doesn't suddenly become \"2\" just because\nit looks like a number). There I minor exceptions to this, read the\nL section below to learn about those.\n\n\n=item * strict checking of JSON correctness\n\nThere is no guessing, no generating of illegal JSON texts by default,\nand only JSON is accepted as input by default (the latter is a security\nfeature).\n\nSee to L and L.\n\n=item * fast\n\nThis module returns a JSON::XS object itself if available.\nCompared to other JSON modules and other serialisers such as Storable,\nJSON::XS usually compares favourably in terms of speed, too.\n\nIf not available, C returns a JSON::PP object instead of JSON::XS and\nit is very slow as pure-Perl.\n\n=item * simple to use\n\nThis module has both a simple functional interface as well as an\nobject oriented interface interface.\n\n=item * reasonably versatile output formats\n\nYou can choose between the most compact guaranteed-single-line format possible\n(nice for simple line-based protocols), a pure-ASCII format (for when your transport\nis not 8-bit clean, still supports the whole Unicode range), or a pretty-printed\nformat (for when you want to read that stuff). Or you can combine those features\nin whatever way you like.\n\n=back\n\n=head1 FUNCTIONAL INTERFACE\n\nSome documents are copied and modified from L.\nC and C are additional functions.\n\n=head2 encode_json\n\n $json_text = encode_json $perl_scalar\n\nConverts the given Perl data structure to a UTF-8 encoded, binary string.\n\nThis function call is functionally identical to:\n\n $json_text = JSON->new->utf8->encode($perl_scalar)\n\n=head2 decode_json\n\n $perl_scalar = decode_json $json_text\n\nThe opposite of C: expects an UTF-8 (binary) string and tries\nto parse that as an UTF-8 encoded JSON text, returning the resulting\nreference.\n\nThis function call is functionally identical to:\n\n $perl_scalar = JSON->new->utf8->decode($json_text)\n\n\n=head2 to_json\n\n $json_text = to_json($perl_scalar)\n\nConverts the given Perl data structure to a json string.\n\nThis function call is functionally identical to:\n\n $json_text = JSON->new->encode($perl_scalar)\n\nTakes a hash reference as the second.\n\n $json_text = to_json($perl_scalar, $flag_hashref)\n\nSo,\n\n $json_text = to_json($perl_scalar, {utf8 => 1, pretty => 1})\n\nequivalent to:\n\n $json_text = JSON->new->utf8(1)->pretty(1)->encode($perl_scalar)\n\nIf you want to write a modern perl code which communicates to outer world,\nyou should use C (supposed that JSON data are encoded in UTF-8).\n\n=head2 from_json\n\n $perl_scalar = from_json($json_text)\n\nThe opposite of C: expects a json string and tries\nto parse it, returning the resulting reference.\n\nThis function call is functionally identical to:\n\n $perl_scalar = JSON->decode($json_text)\n\nTakes a hash reference as the second.\n\n $perl_scalar = from_json($json_text, $flag_hashref)\n\nSo,\n\n $perl_scalar = from_json($json_text, {utf8 => 1})\n\nequivalent to:\n\n $perl_scalar = JSON->new->utf8(1)->decode($json_text)\n\nIf you want to write a modern perl code which communicates to outer world,\nyou should use C (supposed that JSON data are encoded in UTF-8).\n\n=head2 JSON::is_bool\n\n $is_boolean = JSON::is_bool($scalar)\n\nReturns true if the passed scalar represents either JSON::true or\nJSON::false, two constants that act like C<1> and C<0> respectively\nand are also used to represent JSON C and C in Perl strings.\n\n=head2 JSON::true\n\nReturns JSON true value which is blessed object.\nIt C JSON::Boolean object.\n\n=head2 JSON::false\n\nReturns JSON false value which is blessed object.\nIt C JSON::Boolean object.\n\n=head2 JSON::null\n\nReturns C.\n\nSee L, below, for more information on how JSON values are mapped to\nPerl.\n\n=head1 HOW DO I DECODE A DATA FROM OUTER AND ENCODE TO OUTER\n\nThis section supposes that your perl vresion is 5.8 or later.\n\nIf you know a JSON text from an outer world - a network, a file content, and so on,\nis encoded in UTF-8, you should use C or C module object\nwith C enable. And the decoded result will contain UNICODE characters.\n\n # from network\n my $json = JSON->new->utf8;\n my $json_text = CGI->new->param( 'json_data' );\n my $perl_scalar = $json->decode( $json_text );\n\n # from file content\n local $/;\n open( my $fh, '<', 'json.data' );\n $json_text = <$fh>;\n $perl_scalar = decode_json( $json_text );\n\nIf an outer data is not encoded in UTF-8, firstly you should C it.\n\n use Encode;\n local $/;\n open( my $fh, '<', 'json.data' );\n my $encoding = 'cp932';\n my $unicode_json_text = decode( $encoding, <$fh> ); # UNICODE\n\n # or you can write the below code.\n #\n # open( my $fh, \"<:encoding($encoding)\", 'json.data' );\n # $unicode_json_text = <$fh>;\n\nIn this case, C<$unicode_json_text> is of course UNICODE string.\nSo you B use C nor C module object with C enable.\nInstead of them, you use C module object with C disable or C.\n\n $perl_scalar = $json->utf8(0)->decode( $unicode_json_text );\n # or\n $perl_scalar = from_json( $unicode_json_text );\n\nOr C and C:\n\n $perl_scalar = decode_json( encode( 'utf8', $unicode_json_text ) );\n # this way is not efficient.\n\nAnd now, you want to convert your C<$perl_scalar> into JSON data and\nsend it to an outer world - a network or a file content, and so on.\n\nYour data usually contains UNICODE strings and you want the converted data to be encoded\nin UTF-8, you should use C or C module object with C enable.\n\n print encode_json( $perl_scalar ); # to a network? file? or display?\n # or\n print $json->utf8->encode( $perl_scalar );\n\nIf C<$perl_scalar> does not contain UNICODE but C<$encoding>-encoded strings\nfor some reason, then its characters are regarded as B for perl\n(because it does not concern with your $encoding).\nYou B use C nor C module object with C enable.\nInstead of them, you use C module object with C disable or C.\nNote that the resulted text is a UNICODE string but no problem to print it.\n\n # $perl_scalar contains $encoding encoded string values\n $unicode_json_text = $json->utf8(0)->encode( $perl_scalar );\n # or\n $unicode_json_text = to_json( $perl_scalar );\n # $unicode_json_text consists of characters less than 0x100\n print $unicode_json_text;\n\nOr C all string values and C:\n\n $perl_scalar->{ foo } = decode( $encoding, $perl_scalar->{ foo } );\n # ... do it to each string values, then encode_json\n $json_text = encode_json( $perl_scalar );\n\nThis method is a proper way but probably not efficient.\n\nSee to L, L.\n\n\n=head1 COMMON OBJECT-ORIENTED INTERFACE\n\n=head2 new\n\n $json = new JSON\n\nReturns a new C object inherited from either JSON::XS or JSON::PP\nthat can be used to de/encode JSON strings.\n\nAll boolean flags described below are by default I.\n\nThe mutators for flags all return the JSON object again and thus calls can\nbe chained:\n\n my $json = JSON->new->utf8->space_after->encode({a => [1,2]})\n => {\"a\": [1, 2]}\n\n=head2 ascii\n\n $json = $json->ascii([$enable])\n\n $enabled = $json->get_ascii\n\nIf $enable is true (or missing), then the encode method will not generate characters outside\nthe code range 0..127. Any Unicode characters outside that range will be escaped using either\na single \\uXXXX or a double \\uHHHH\\uLLLLL escape sequence, as per RFC4627.\n\nIf $enable is false, then the encode method will not escape Unicode characters unless\nrequired by the JSON syntax or other flags. This results in a faster and more compact format.\n\nThis feature depends on the used Perl version and environment.\n\nSee to L if the backend is PP.\n\n JSON->new->ascii(1)->encode([chr 0x10401])\n => [\"\\ud801\\udc01\"]\n\n=head2 latin1\n\n $json = $json->latin1([$enable])\n\n $enabled = $json->get_latin1\n\nIf $enable is true (or missing), then the encode method will encode the resulting JSON\ntext as latin1 (or iso-8859-1), escaping any characters outside the code range 0..255.\n\nIf $enable is false, then the encode method will not escape Unicode characters\nunless required by the JSON syntax or other flags.\n\n JSON->new->latin1->encode ([\"\\x{89}\\x{abc}\"]\n => [\"\\x{89}\\\\u0abc\"] # (perl syntax, U+abc escaped, U+89 not)\n\n=head2 utf8\n\n $json = $json->utf8([$enable])\n\n $enabled = $json->get_utf8\n\nIf $enable is true (or missing), then the encode method will encode the JSON result\ninto UTF-8, as required by many protocols, while the decode method expects to be handled\nan UTF-8-encoded string. Please note that UTF-8-encoded strings do not contain any\ncharacters outside the range 0..255, they are thus useful for bytewise/binary I/O.\n\nIn future versions, enabling this option might enable autodetection of the UTF-16 and UTF-32\nencoding families, as described in RFC4627.\n\nIf $enable is false, then the encode method will return the JSON string as a (non-encoded)\nUnicode string, while decode expects thus a Unicode string. Any decoding or encoding\n(e.g. to UTF-8 or UTF-16) needs to be done yourself, e.g. using the Encode module.\n\n\nExample, output UTF-16BE-encoded JSON:\n\n use Encode;\n $jsontext = encode \"UTF-16BE\", JSON::XS->new->encode ($object);\n\nExample, decode UTF-32LE-encoded JSON:\n\n use Encode;\n $object = JSON::XS->new->decode (decode \"UTF-32LE\", $jsontext);\n\nSee to L if the backend is PP.\n\n\n=head2 pretty\n\n $json = $json->pretty([$enable])\n\nThis enables (or disables) all of the C, C and\nC (and in the future possibly more) flags in one call to\ngenerate the most readable (or most compact) form possible.\n\nEquivalent to:\n\n $json->indent->space_before->space_after\n\nThe indent space length is three and JSON::XS cannot change the indent\nspace length.\n\n=head2 indent\n\n $json = $json->indent([$enable])\n\n $enabled = $json->get_indent\n\nIf C<$enable> is true (or missing), then the C method will use a multiline\nformat as output, putting every array member or object/hash key-value pair\ninto its own line, identing them properly.\n\nIf C<$enable> is false, no newlines or indenting will be produced, and the\nresulting JSON text is guarenteed not to contain any C.\n\nThis setting has no effect when decoding JSON texts.\n\nThe indent space length is three.\nWith JSON::PP, you can also access C to change indent space length.\n\n\n=head2 space_before\n\n $json = $json->space_before([$enable])\n\n $enabled = $json->get_space_before\n\nIf C<$enable> is true (or missing), then the C method will add an extra\noptional space before the C<:> separating keys from values in JSON objects.\n\nIf C<$enable> is false, then the C method will not add any extra\nspace at those places.\n\nThis setting has no effect when decoding JSON texts.\n\nExample, space_before enabled, space_after and indent disabled:\n\n {\"key\" :\"value\"}\n\n\n=head2 space_after\n\n $json = $json->space_after([$enable])\n\n $enabled = $json->get_space_after\n\nIf C<$enable> is true (or missing), then the C method will add an extra\noptional space after the C<:> separating keys from values in JSON objects\nand extra whitespace after the C<,> separating key-value pairs and array\nmembers.\n\nIf C<$enable> is false, then the C method will not add any extra\nspace at those places.\n\nThis setting has no effect when decoding JSON texts.\n\nExample, space_before and indent disabled, space_after enabled:\n\n {\"key\": \"value\"}\n\n\n=head2 relaxed\n\n $json = $json->relaxed([$enable])\n\n $enabled = $json->get_relaxed\n\nIf C<$enable> is true (or missing), then C will accept some\nextensions to normal JSON syntax (see below). C will not be\naffected in anyway. I. I suggest only to use this option to\nparse application-specific files written by humans (configuration files,\nresource files etc.)\n\nIf C<$enable> is false (the default), then C will only accept\nvalid JSON texts.\n\nCurrently accepted extensions are:\n\n=over 4\n\n=item * list items can have an end-comma\n\nJSON I array elements and key-value pairs with commas. This\ncan be annoying if you write JSON texts manually and want to be able to\nquickly append elements, so this extension accepts comma at the end of\nsuch items not just between them:\n\n [\n 1,\n 2, <- this comma not normally allowed\n ]\n {\n \"k1\": \"v1\",\n \"k2\": \"v2\", <- this comma not normally allowed\n }\n\n=item * shell-style '#'-comments\n\nWhenever JSON allows whitespace, shell-style comments are additionally\nallowed. They are terminated by the first carriage-return or line-feed\ncharacter, after which more white-space and comments are allowed.\n\n [\n 1, # this comment not allowed in JSON\n # neither this one...\n ]\n\n=back\n\n\n=head2 canonical\n\n $json = $json->canonical([$enable])\n\n $enabled = $json->get_canonical\n\nIf C<$enable> is true (or missing), then the C method will output JSON objects\nby sorting their keys. This is adding a comparatively high overhead.\n\nIf C<$enable> is false, then the C method will output key-value\npairs in the order Perl stores them (which will likely change between runs\nof the same script).\n\nThis option is useful if you want the same data structure to be encoded as\nthe same JSON text (given the same overall settings). If it is disabled,\nthe same hash might be encoded differently even if contains the same data,\nas key-value pairs have no inherent ordering in Perl.\n\nThis setting has no effect when decoding JSON texts.\n\n=head2 allow_nonref\n\n $json = $json->allow_nonref([$enable])\n\n $enabled = $json->get_allow_nonref\n\nIf C<$enable> is true (or missing), then the C method can convert a\nnon-reference into its corresponding string, number or null JSON value,\nwhich is an extension to RFC4627. Likewise, C will accept those JSON\nvalues instead of croaking.\n\nIf C<$enable> is false, then the C method will croak if it isn't\npassed an arrayref or hashref, as JSON texts must either be an object\nor array. Likewise, C will croak if given something that is not a\nJSON object or array.\n\n JSON->new->allow_nonref->encode (\"Hello, World!\")\n => \"Hello, World!\"\n\n=head2 allow_unknown\n\n $json = $json->allow_unknown ([$enable])\n\n $enabled = $json->get_allow_unknown\n\nIf $enable is true (or missing), then \"encode\" will *not* throw an\nexception when it encounters values it cannot represent in JSON (for\nexample, filehandles) but instead will encode a JSON \"null\" value.\nNote that blessed objects are not included here and are handled\nseparately by c.\n\nIf $enable is false (the default), then \"encode\" will throw an\nexception when it encounters anything it cannot encode as JSON.\n\nThis option does not affect \"decode\" in any way, and it is\nrecommended to leave it off unless you know your communications\npartner.\n\n=head2 allow_blessed\n\n $json = $json->allow_blessed([$enable])\n\n $enabled = $json->get_allow_blessed\n\nIf C<$enable> is true (or missing), then the C method will not\nbarf when it encounters a blessed reference. Instead, the value of the\nB option will decide whether C (C\ndisabled or no C method found) or a representation of the\nobject (C enabled and C method found) is being\nencoded. Has no effect on C.\n\nIf C<$enable> is false (the default), then C will throw an\nexception when it encounters a blessed object.\n\n\n=head2 convert_blessed\n\n $json = $json->convert_blessed([$enable])\n\n $enabled = $json->get_convert_blessed\n\nIf C<$enable> is true (or missing), then C, upon encountering a\nblessed object, will check for the availability of the C method\non the object's class. If found, it will be called in scalar context\nand the resulting scalar will be encoded instead of the object. If no\nC method is found, the value of C will decide what\nto do.\n\nThe C method may safely call die if it wants. If C\nreturns other blessed objects, those will be handled in the same\nway. C must take care of not causing an endless recursion cycle\n(== crash) in this case. The name of C was chosen because other\nmethods called by the Perl core (== not by the user of the object) are\nusually in upper case letters and to avoid collisions with the C\nfunction or method.\n\nThis setting does not yet influence C in any way.\n\nIf C<$enable> is false, then the C setting will decide what\nto do when a blessed object is found.\n\n=over\n\n=item convert_blessed_universally mode\n\nIf use C with C<-convert_blessed_universally>, the C\nsubroutine is defined as the below code:\n\n *UNIVERSAL::TO_JSON = sub {\n my $b_obj = B::svref_2object( $_[0] );\n return $b_obj->isa('B::HV') ? { %{ $_[0] } }\n : $b_obj->isa('B::AV') ? [ @{ $_[0] } ]\n : undef\n ;\n }\n\nThis will cause that C method converts simple blessed objects into\nJSON objects as non-blessed object.\n\n JSON -convert_blessed_universally;\n $json->allow_blessed->convert_blessed->encode( $blessed_object )\n\nThis feature is experimental and may be removed in the future.\n\n=back\n\n=head2 filter_json_object\n\n $json = $json->filter_json_object([$coderef])\n\nWhen C<$coderef> is specified, it will be called from C each\ntime it decodes a JSON object. The only argument passed to the coderef\nis a reference to the newly-created hash. If the code references returns\na single scalar (which need not be a reference), this value\n(i.e. a copy of that scalar to avoid aliasing) is inserted into the\ndeserialised data structure. If it returns an empty list\n(NOTE: I C, which is a valid scalar), the original deserialised\nhash will be inserted. This setting can slow down decoding considerably.\n\nWhen C<$coderef> is omitted or undefined, any existing callback will\nbe removed and C will not change the deserialised hash in any\nway.\n\nExample, convert all JSON objects into the integer 5:\n\n my $js = JSON->new->filter_json_object (sub { 5 });\n # returns [5]\n $js->decode ('[{}]'); # the given subroutine takes a hash reference.\n # throw an exception because allow_nonref is not enabled\n # so a lone 5 is not allowed.\n $js->decode ('{\"a\":1, \"b\":2}');\n\n\n=head2 filter_json_single_key_object\n\n $json = $json->filter_json_single_key_object($key [=> $coderef])\n\nWorks remotely similar to C, but is only called for\nJSON objects having a single key named C<$key>.\n\nThis C<$coderef> is called before the one specified via\nC, if any. It gets passed the single value in the JSON\nobject. If it returns a single value, it will be inserted into the data\nstructure. If it returns nothing (not even C but the empty list),\nthe callback from C will be called next, as if no\nsingle-key callback were specified.\n\nIf C<$coderef> is omitted or undefined, the corresponding callback will be\ndisabled. There can only ever be one callback for a given key.\n\nAs this callback gets called less often then the C\none, decoding speed will not usually suffer as much. Therefore, single-key\nobjects make excellent targets to serialise Perl objects into, especially\nas single-key JSON objects are as close to the type-tagged value concept\nas JSON gets (it's basically an ID/VALUE tuple). Of course, JSON does not\nsupport this in any way, so you need to make sure your data never looks\nlike a serialised Perl hash.\n\nTypical names for the single object key are C<__class_whatever__>, or\nC<$__dollars_are_rarely_used__$> or C<}ugly_brace_placement>, or even\nthings like C<__class_md5sum(classname)__>, to reduce the risk of clashing\nwith real hashes.\n\nExample, decode JSON objects of the form C<< { \"__widget__\" => } >>\ninto the corresponding C<< $WIDGET{} >> object:\n\n # return whatever is in $WIDGET{5}:\n JSON\n ->new\n ->filter_json_single_key_object (__widget__ => sub {\n $WIDGET{ $_[0] }\n })\n ->decode ('{\"__widget__\": 5')\n\n # this can be used with a TO_JSON method in some \"widget\" class\n # for serialisation to json:\n sub WidgetBase::TO_JSON {\n my ($self) = @_;\n\n unless ($self->{id}) {\n $self->{id} = ..get..some..id..;\n $WIDGET{$self->{id}} = $self;\n }\n\n { __widget__ => $self->{id} }\n }\n\n\n=head2 shrink\n\n $json = $json->shrink([$enable])\n\n $enabled = $json->get_shrink\n\nWith JSON::XS, this flag resizes strings generated by either\nC or C to their minimum size possible. This can save\nmemory when your JSON texts are either very very long or you have many\nshort strings. It will also try to downgrade any strings to octet-form\nif possible: perl stores strings internally either in an encoding called\nUTF-X or in octet-form. The latter cannot store everything but uses less\nspace in general (and some buggy Perl or C code might even rely on that\ninternal representation being used).\n\nWith JSON::PP, it is noop about resizing strings but tries\nC to the returned string by C. See to L.\n\nSee to L and L.\n\n=head2 max_depth\n\n $json = $json->max_depth([$maximum_nesting_depth])\n\n $max_depth = $json->get_max_depth\n\nSets the maximum nesting level (default C<512>) accepted while encoding\nor decoding. If a higher nesting level is detected in JSON text or a Perl\ndata structure, then the encoder and decoder will stop and croak at that\npoint.\n\nNesting level is defined by number of hash- or arrayrefs that the encoder\nneeds to traverse to reach a given point or the number of C<{> or C<[>\ncharacters without their matching closing parenthesis crossed to reach a\ngiven character in a string.\n\nIf no argument is given, the highest possible setting will be used, which\nis rarely useful.\n\nNote that nesting is implemented by recursion in C. The default value has\nbeen chosen to be as large as typical operating systems allow without\ncrashing. (JSON::XS)\n\nWith JSON::PP as the backend, when a large value (100 or more) was set and\nit de/encodes a deep nested object/text, it may raise a warning\n'Deep recursion on subroutin' at the perl runtime phase.\n\nSee L for more info on why this is useful.\n\n=head2 max_size\n\n $json = $json->max_size([$maximum_string_size])\n\n $max_size = $json->get_max_size\n\nSet the maximum length a JSON text may have (in bytes) where decoding is\nbeing attempted. The default is C<0>, meaning no limit. When C\nis called on a string that is longer then this many bytes, it will not\nattempt to decode the string but throw an exception. This setting has no\neffect on C (yet).\n\nIf no argument is given, the limit check will be deactivated (same as when\nC<0> is specified).\n\nSee L, below, for more info on why this is useful.\n\n=head2 encode\n\n $json_text = $json->encode($perl_scalar)\n\nConverts the given Perl data structure (a simple scalar or a reference\nto a hash or array) to its JSON representation. Simple scalars will be\nconverted into JSON string or number sequences, while references to arrays\nbecome JSON arrays and references to hashes become JSON objects. Undefined\nPerl values (e.g. C) become JSON C values.\nReferences to the integers C<0> and C<1> are converted into C and C.\n\n=head2 decode\n\n $perl_scalar = $json->decode($json_text)\n\nThe opposite of C: expects a JSON text and tries to parse it,\nreturning the resulting simple scalar or reference. Croaks on error.\n\nJSON numbers and strings become simple Perl scalars. JSON arrays become\nPerl arrayrefs and JSON objects become Perl hashrefs. C becomes\nC<1> (C), C becomes C<0> (C) and\nC becomes C.\n\n=head2 decode_prefix\n\n ($perl_scalar, $characters) = $json->decode_prefix($json_text)\n\nThis works like the C method, but instead of raising an exception\nwhen there is trailing garbage after the first JSON object, it will\nsilently stop parsing there and return the number of characters consumed\nso far.\n\n JSON->new->decode_prefix (\"[1] the tail\")\n => ([], 3)\n\nSee to L\n\n=head2 property\n\n $boolean = $json->property($property_name)\n\nReturns a boolean value about above some properties.\n\nThe available properties are C, C, C,\nC,C, C, C, C,\nC, C, C, C,\nC, C and C.\n\n $boolean = $json->property('utf8');\n => 0\n $json->utf8;\n $boolean = $json->property('utf8');\n => 1\n\nSets the property with a given boolean value.\n\n $json = $json->property($property_name => $boolean);\n\nWith no argumnt, it returns all the above properties as a hash reference.\n\n $flag_hashref = $json->property();\n\n=head1 INCREMENTAL PARSING\n\nMost of this section are copied and modified from L.\n\nIn some cases, there is the need for incremental parsing of JSON texts.\nThis module does allow you to parse a JSON stream incrementally.\nIt does so by accumulating text until it has a full JSON object, which\nit then can decode. This process is similar to using C\nto see if a full JSON object is available, but is much more efficient\n(and can be implemented with a minimum of method calls).\n\nThe backend module will only attempt to parse the JSON text once it is sure it\nhas enough text to get a decisive result, using a very simple but\ntruly incremental parser. This means that it sometimes won't stop as\nearly as the full parser, for example, it doesn't detect parenthese\nmismatches. The only thing it guarantees is that it starts decoding as\nsoon as a syntactically valid JSON text has been seen. This means you need\nto set resource limits (e.g. C) to ensure the parser will stop\nparsing in the presence if syntax errors.\n\nThe following methods implement this incremental parser.\n\n=head2 incr_parse\n\n $json->incr_parse( [$string] ) # void context\n\n $obj_or_undef = $json->incr_parse( [$string] ) # scalar context\n\n @obj_or_empty = $json->incr_parse( [$string] ) # list context\n\nThis is the central parsing function. It can both append new text and\nextract objects from the stream accumulated so far (both of these\nfunctions are optional).\n\nIf C<$string> is given, then this string is appended to the already\nexisting JSON fragment stored in the C<$json> object.\n\nAfter that, if the function is called in void context, it will simply\nreturn without doing anything further. This can be used to add more text\nin as many chunks as you want.\n\nIf the method is called in scalar context, then it will try to extract\nexactly I JSON object. If that is successful, it will return this\nobject, otherwise it will return C. If there is a parse error,\nthis method will croak just as C would do (one can then use\nC to skip the errornous part). This is the most common way of\nusing the method.\n\nAnd finally, in list context, it will try to extract as many objects\nfrom the stream as it can find and return them, or the empty list\notherwise. For this to work, there must be no separators between the JSON\nobjects or arrays, instead they must be concatenated back-to-back. If\nan error occurs, an exception will be raised as in the scalar context\ncase. Note that in this case, any previously-parsed JSON texts will be\nlost.\n\nExample: Parse some JSON arrays/objects in a given string and return them.\n\n my @objs = JSON->new->incr_parse (\"[5][7][1,2]\");\n\n=head2 incr_text\n\n $lvalue_string = $json->incr_text\n\nThis method returns the currently stored JSON fragment as an lvalue, that\nis, you can manipulate it. This I works when a preceding call to\nC in I successfully returned an object. Under\nall other circumstances you must not call this function (I mean it.\nalthough in simple tests it might actually work, it I fail under\nreal world conditions). As a special exception, you can also call this\nmethod before having parsed anything.\n\nThis function is useful in two cases: a) finding the trailing text after a\nJSON object or b) parsing multiple JSON objects separated by non-JSON text\n(such as commas).\n\n $json->incr_text =~ s/\\s*,\\s*//;\n\nIn Perl 5.005, C attribute is not available.\nYou must write codes like the below:\n\n $string = $json->incr_text;\n $string =~ s/\\s*,\\s*//;\n $json->incr_text( $string );\n\n=head2 incr_skip\n\n $json->incr_skip\n\nThis will reset the state of the incremental parser and will remove the\nparsed text from the input buffer. This is useful after C\ndied, in which case the input buffer and incremental parser state is left\nunchanged, to skip the text parsed so far and to reset the parse state.\n\n=head2 incr_reset\n\n $json->incr_reset\n\nThis completely resets the incremental parser, that is, after this call,\nit will be as if the parser had never parsed anything.\n\nThis is useful if you want ot repeatedly parse JSON objects and want to\nignore any trailing data, which means you have to reset the parser after\neach successful decode.\n\nSee to L for examples.\n\n\n=head1 JSON::PP SUPPORT METHODS\n\nThe below methods are JSON::PP own methods, so when C works\nwith JSON::PP (i.e. the created object is a JSON::PP object), available.\nSee to L in detail.\n\nIf you use C with additonal C<-support_by_pp>, some methods\nare available even with JSON::XS. See to L.\n\n BEING { $ENV{PERL_JSON_BACKEND} = 'JSON::XS' }\n\n use JSON -support_by_pp;\n\n my $json = new JSON;\n $json->allow_nonref->escape_slash->encode(\"/\");\n\n # functional interfaces too.\n print to_json([\"/\"], {escape_slash => 1});\n print from_json('[\"foo\"]', {utf8 => 1});\n\nIf you do not want to all functions but C<-support_by_pp>,\nuse C<-no_export>.\n\n use JSON -support_by_pp, -no_export;\n # functional interfaces are not exported.\n\n=head2 allow_singlequote\n\n $json = $json->allow_singlequote([$enable])\n\nIf C<$enable> is true (or missing), then C will accept\nany JSON strings quoted by single quotations that are invalid JSON\nformat.\n\n $json->allow_singlequote->decode({\"foo\":'bar'});\n $json->allow_singlequote->decode({'foo':\"bar\"});\n $json->allow_singlequote->decode({'foo':'bar'});\n\nAs same as the C option, this option may be used to parse\napplication-specific files written by humans.\n\n=head2 allow_barekey\n\n $json = $json->allow_barekey([$enable])\n\nIf C<$enable> is true (or missing), then C will accept\nbare keys of JSON object that are invalid JSON format.\n\nAs same as the C option, this option may be used to parse\napplication-specific files written by humans.\n\n $json->allow_barekey->decode('{foo:\"bar\"}');\n\n=head2 allow_bignum\n\n $json = $json->allow_bignum([$enable])\n\nIf C<$enable> is true (or missing), then C will convert\nthe big integer Perl cannot handle as integer into a L\nobject and convert a floating number (any) into a L.\n\nOn the contary, C converts C objects and C\nobjects into JSON numbers with C enable.\n\n $json->allow_nonref->allow_blessed->allow_bignum;\n $bigfloat = $json->decode('2.000000000000000000000000001');\n print $json->encode($bigfloat);\n # => 2.000000000000000000000000001\n\nSee to L aboout the conversion of JSON number.\n\n=head2 loose\n\n $json = $json->loose([$enable])\n\nThe unescaped [\\x00-\\x1f\\x22\\x2f\\x5c] strings are invalid in JSON strings\nand the module doesn't allow to C to these (except for \\x2f).\nIf C<$enable> is true (or missing), then C will accept these\nunescaped strings.\n\n $json->loose->decode(qq|[\"abc\n def\"]|);\n\nSee to L.\n\n=head2 escape_slash\n\n $json = $json->escape_slash([$enable])\n\nAccording to JSON Grammar, I (U+002F) is escaped. But by default\nJSON backend modules encode strings without escaping slash.\n\nIf C<$enable> is true (or missing), then C will escape slashes.\n\n=head2 indent_length\n\n $json = $json->indent_length($length)\n\nWith JSON::XS, The indent space length is 3 and cannot be changed.\nWith JSON::PP, it sets the indent space length with the given $length.\nThe default is 3. The acceptable range is 0 to 15.\n\n=head2 sort_by\n\n $json = $json->sort_by($function_name)\n $json = $json->sort_by($subroutine_ref)\n\nIf $function_name or $subroutine_ref are set, its sort routine are used.\n\n $js = $pc->sort_by(sub { $JSON::PP::a cmp $JSON::PP::b })->encode($obj);\n # is($js, q|{\"a\":1,\"b\":2,\"c\":3,\"d\":4,\"e\":5,\"f\":6,\"g\":7,\"h\":8,\"i\":9}|);\n\n $js = $pc->sort_by('own_sort')->encode($obj);\n # is($js, q|{\"a\":1,\"b\":2,\"c\":3,\"d\":4,\"e\":5,\"f\":6,\"g\":7,\"h\":8,\"i\":9}|);\n\n sub JSON::PP::own_sort { $JSON::PP::a cmp $JSON::PP::b }\n\nAs the sorting routine runs in the JSON::PP scope, the given\nsubroutine name and the special variables C<$a>, C<$b> will begin\nwith 'JSON::PP::'.\n\nIf $integer is set, then the effect is same as C on.\n\nSee to L.\n\n=head1 MAPPING\n\nThis section is copied from JSON::XS and modified to C.\nJSON::XS and JSON::PP mapping mechanisms are almost equivalent.\n\nSee to L.\n\n=head2 JSON -> PERL\n\n=over 4\n\n=item object\n\nA JSON object becomes a reference to a hash in Perl. No ordering of object\nkeys is preserved (JSON does not preserver object key ordering itself).\n\n=item array\n\nA JSON array becomes a reference to an array in Perl.\n\n=item string\n\nA JSON string becomes a string scalar in Perl - Unicode codepoints in JSON\nare represented by the same codepoints in the Perl string, so no manual\ndecoding is necessary.\n\n=item number\n\nA JSON number becomes either an integer, numeric (floating point) or\nstring scalar in perl, depending on its range and any fractional parts. On\nthe Perl level, there is no difference between those as Perl handles all\nthe conversion details, but an integer may take slightly less memory and\nmight represent more values exactly than floating point numbers.\n\nIf the number consists of digits only, C will try to represent\nit as an integer value. If that fails, it will try to represent it as\na numeric (floating point) value if that is possible without loss of\nprecision. Otherwise it will preserve the number as a string value (in\nwhich case you lose roundtripping ability, as the JSON number will be\nre-encoded toa JSON string).\n\nNumbers containing a fractional or exponential part will always be\nrepresented as numeric (floating point) values, possibly at a loss of\nprecision (in which case you might lose perfect roundtripping ability, but\nthe JSON number will still be re-encoded as a JSON number).\n\nNote that precision is not accuracy - binary floating point values cannot\nrepresent most decimal fractions exactly, and when converting from and to\nfloating point, C only guarantees precision up to but not including\nthe leats significant bit.\n\nIf the backend is JSON::PP and C is enable, the big integers\nand the numeric can be optionally converted into L and\nL objects.\n\n=item true, false\n\nThese JSON atoms become C and C,\nrespectively. They are overloaded to act almost exactly like the numbers\nC<1> and C<0>. You can check wether a scalar is a JSON boolean by using\nthe C function.\n\nIf C and C are used as strings or compared as strings,\nthey represent as C and C respectively.\n\n print JSON::true . \"\\n\";\n => true\n print JSON::true + 1;\n => 1\n\n ok(JSON::true eq 'true');\n ok(JSON::true eq '1');\n ok(JSON::true == 1);\n\nC will install these missing overloading features to the backend modules.\n\n\n=item null\n\nA JSON null atom becomes C in Perl.\n\nC returns C.\n\n=back\n\n\n=head2 PERL -> JSON\n\nThe mapping from Perl to JSON is slightly more difficult, as Perl is a\ntruly typeless language, so we can only guess which JSON type is meant by\na Perl value.\n\n=over 4\n\n=item hash references\n\nPerl hash references become JSON objects. As there is no inherent ordering\nin hash keys (or JSON objects), they will usually be encoded in a\npseudo-random order that can change between runs of the same program but\nstays generally the same within a single run of a program. C\noptionally sort the hash keys (determined by the I flag), so\nthe same datastructure will serialise to the same JSON text (given same\nsettings and version of JSON::XS), but this incurs a runtime overhead\nand is only rarely useful, e.g. when you want to compare some JSON text\nagainst another for equality.\n\nIn future, the ordered object feature will be added to JSON::PP using C mechanism.\n\n\n=item array references\n\nPerl array references become JSON arrays.\n\n=item other references\n\nOther unblessed references are generally not allowed and will cause an\nexception to be thrown, except for references to the integers C<0> and\nC<1>, which get turned into C and C atoms in JSON. You can\nalso use C and C to improve readability.\n\n to_json [\\0,JSON::true] # yields [false,true]\n\n=item JSON::true, JSON::false, JSON::null\n\nThese special values become JSON true and JSON false values,\nrespectively. You can also use C<\\1> and C<\\0> directly if you want.\n\nJSON::null returns C.\n\n=item blessed objects\n\nBlessed objects are not directly representable in JSON. See the\nC and C methods on various options on\nhow to deal with this: basically, you can choose between throwing an\nexception, encoding the reference as if it weren't blessed, or provide\nyour own serialiser method.\n\nWith C mode, C converts blessed\nhash references or blessed array references (contains other blessed references)\ninto JSON members and arrays.\n\n use JSON -convert_blessed_universally;\n JSON->new->allow_blessed->convert_blessed->encode( $blessed_object );\n\nSee to L.\n\n=item simple scalars\n\nSimple Perl scalars (any scalar that is not a reference) are the most\ndifficult objects to encode: JSON::XS and JSON::PP will encode undefined scalars as\nJSON C values, scalars that have last been used in a string context\nbefore encoding as JSON strings, and anything else as number value:\n\n # dump as number\n encode_json [2] # yields [2]\n encode_json [-3.0e17] # yields [-3e+17]\n my $value = 5; encode_json [$value] # yields [5]\n\n # used as string, so dump as string\n print $value;\n encode_json [$value] # yields [\"5\"]\n\n # undef becomes null\n encode_json [undef] # yields [null]\n\nYou can force the type to be a string by stringifying it:\n\n my $x = 3.1; # some variable containing a number\n \"$x\"; # stringified\n $x .= \"\"; # another, more awkward way to stringify\n print $x; # perl does it for you, too, quite often\n\nYou can force the type to be a number by numifying it:\n\n my $x = \"3\"; # some variable containing a string\n $x += 0; # numify it, ensuring it will be dumped as a number\n $x *= 1; # same thing, the choise is yours.\n\nYou can not currently force the type in other, less obscure, ways.\n\nNote that numerical precision has the same meaning as under Perl (so\nbinary to decimal conversion follows the same rules as in Perl, which\ncan differ to other languages). Also, your perl interpreter might expose\nextensions to the floating point numbers of your platform, such as\ninfinities or NaN's - these cannot be represented in JSON, and it is an\nerror to pass those in.\n\n=item Big Number\n\nIf the backend is JSON::PP and C is enable,\nC converts C objects and C\nobjects into JSON numbers.\n\n\n=back\n\n=head1 JSON and ECMAscript\n\nSee to L.\n\n=head1 JSON and YAML\n\nJSON is not a subset of YAML.\nSee to L.\n\n\n=head1 BACKEND MODULE DECISION\n\nWhen you use C, C tries to C JSON::XS. If this call failed, it will\nC JSON::PP. The required JSON::XS version is I<2.2> or later.\n\nThe C constructor method returns an object inherited from the backend module,\nand JSON::XS object is a blessed scaler reference while JSON::PP is a blessed hash\nreference.\n\nSo, your program should not depend on the backend module, especially\nreturned objects should not be modified.\n\n my $json = JSON->new; # XS or PP?\n $json->{stash} = 'this is xs object'; # this code may raise an error!\n\nTo check the backend module, there are some methods - C, C and C.\n\n JSON->backend; # 'JSON::XS' or 'JSON::PP'\n\n JSON->backend->is_pp: # 0 or 1\n\n JSON->backend->is_xs: # 1 or 0\n\n $json->is_xs; # 1 or 0\n\n $json->is_pp; # 0 or 1\n\n\nIf you set an enviornment variable C, The calling action will be changed.\n\n=over\n\n=item PERL_JSON_BACKEND = 0 or PERL_JSON_BACKEND = 'JSON::PP'\n\nAlways use JSON::PP\n\n=item PERL_JSON_BACKEND == 1 or PERL_JSON_BACKEND = 'JSON::XS,JSON::PP'\n\n(The default) Use compiled JSON::XS if it is properly compiled & installed,\notherwise use JSON::PP.\n\n=item PERL_JSON_BACKEND == 2 or PERL_JSON_BACKEND = 'JSON::XS'\n\nAlways use compiled JSON::XS, die if it isn't properly compiled & installed.\n\n=item PERL_JSON_BACKEND = 'JSON::backportPP'\n\nAlways use JSON::backportPP.\nJSON::backportPP is JSON::PP back port module.\nC includs JSON::backportPP instead of JSON::PP.\n\n=back\n\nThese ideas come from L mechanism.\n\nexample:\n\n BEGIN { $ENV{PERL_JSON_BACKEND} = 'JSON::PP' }\n use JSON; # always uses JSON::PP\n\nIn future, it may be able to specify another module.\n\n=head1 USE PP FEATURES EVEN THOUGH XS BACKEND\n\nMany methods are available with either JSON::XS or JSON::PP and\nwhen the backend module is JSON::XS, if any JSON::PP specific (i.e. JSON::XS unspported)\nmethod is called, it will C and be noop.\n\nBut If you C C passing the optional string C<-support_by_pp>,\nit makes a part of those unupported methods available.\nThis feature is achieved by using JSON::PP in C.\n\n BEGIN { $ENV{PERL_JSON_BACKEND} = 2 } # with JSON::XS\n use JSON -support_by_pp;\n my $json = new JSON;\n $json->allow_nonref->escape_slash->encode(\"/\");\n\nAt this time, the returned object is a C\nobject (re-blessed XS object), and by checking JSON::XS unsupported flags\nin de/encoding, can support some unsupported methods - C, C,\nC, C, C and C.\n\nWhen any unsupported methods are not enable, C will be\nused as is. The switch is achieved by changing the symbolic tables.\n\nC<-support_by_pp> is effective only when the backend module is JSON::XS\nand it makes the de/encoding speed down a bit.\n\nSee to L.\n\n=head1 INCOMPATIBLE CHANGES TO OLD VERSION\n\nThere are big incompatibility between new version (2.00) and old (1.xx).\nIf you use old C 1.xx in your code, please check it.\n\nSee to L\n\n=over\n\n=item jsonToObj and objToJson are obsoleted.\n\nNon Perl-style name C and C are obsoleted\n(but not yet deleted from the source).\nIf you use these functions in your code, please replace them\nwith C and C.\n\n\n=item Global variables are no longer available.\n\nC class variables - C<$JSON::AUTOCONVERT>, C<$JSON::BareKey>, etc...\n- are not available any longer.\nInstead, various features can be used through object methods.\n\n\n=item Package JSON::Converter and JSON::Parser are deleted.\n\nNow C bundles with JSON::PP which can handle JSON more properly than them.\n\n=item Package JSON::NotString is deleted.\n\nThere was C class which represents JSON value C, C, C\nand numbers. It was deleted and replaced by C.\n\nC represents C and C.\n\nC does not represent C.\n\nC returns C.\n\nC makes L and L is-a relation\nto L.\n\n=item function JSON::Number is obsoleted.\n\nC is now needless because JSON::XS and JSON::PP have\nround-trip integrity.\n\n=item JSONRPC modules are deleted.\n\nPerl implementation of JSON-RPC protocol - C, C\nand C are deleted in this distribution.\nInstead of them, there is L which supports JSON-RPC protocol version 1.1.\n\n=back\n\n=head2 Transition ways from 1.xx to 2.xx.\n\nYou should set C mode firstly, because\nit is always successful for the below codes even with JSON::XS.\n\n use JSON -support_by_pp;\n\n=over\n\n=item Exported jsonToObj (simple)\n\n from_json($json_text);\n\n=item Exported objToJson (simple)\n\n to_json($perl_scalar);\n\n=item Exported jsonToObj (advanced)\n\n $flags = {allow_barekey => 1, allow_singlequote => 1};\n from_json($json_text, $flags);\n\nequivalent to:\n\n $JSON::BareKey = 1;\n $JSON::QuotApos = 1;\n jsonToObj($json_text);\n\n=item Exported objToJson (advanced)\n\n $flags = {allow_blessed => 1, allow_barekey => 1};\n to_json($perl_scalar, $flags);\n\nequivalent to:\n\n $JSON::BareKey = 1;\n objToJson($perl_scalar);\n\n=item jsonToObj as object method\n\n $json->decode($json_text);\n\n=item objToJson as object method\n\n $json->encode($perl_scalar);\n\n=item new method with parameters\n\nThe C method in 2.x takes any parameters no longer.\nYou can set parameters instead;\n\n $json = JSON->new->pretty;\n\n=item $JSON::Pretty, $JSON::Indent, $JSON::Delimiter\n\nIf C is enable, that means C<$JSON::Pretty> flag set. And\nC<$JSON::Delimiter> was substituted by C and C.\nIn conclusion:\n\n $json->indent->space_before->space_after;\n\nEquivalent to:\n\n $json->pretty;\n\nTo change indent length, use C.\n\n(Only with JSON::PP, if C<-support_by_pp> is not used.)\n\n $json->pretty->indent_length(2)->encode($perl_scalar);\n\n=item $JSON::BareKey\n\n(Only with JSON::PP, if C<-support_by_pp> is not used.)\n\n $json->allow_barekey->decode($json_text)\n\n=item $JSON::ConvBlessed\n\nuse C<-convert_blessed_universally>. See to L.\n\n=item $JSON::QuotApos\n\n(Only with JSON::PP, if C<-support_by_pp> is not used.)\n\n $json->allow_singlequote->decode($json_text)\n\n=item $JSON::SingleQuote\n\nDisable. C does not make such a invalid JSON string any longer.\n\n=item $JSON::KeySort\n\n $json->canonical->encode($perl_scalar)\n\nThis is the ascii sort.\n\nIf you want to use with your own sort routine, check the C method.\n\n(Only with JSON::PP, even if C<-support_by_pp> is used currently.)\n\n $json->sort_by($sort_routine_ref)->encode($perl_scalar)\n\n $json->sort_by(sub { $JSON::PP::a <=> $JSON::PP::b })->encode($perl_scalar)\n\nCan't access C<$a> and C<$b> but C<$JSON::PP::a> and C<$JSON::PP::b>.\n\n=item $JSON::SkipInvalid\n\n $json->allow_unknown\n\n=item $JSON::AUTOCONVERT\n\nNeedless. C backend modules have the round-trip integrity.\n\n=item $JSON::UTF8\n\nNeedless because C (JSON::XS/JSON::PP) sets\nthe UTF8 flag on properly.\n\n # With UTF8-flagged strings\n\n $json->allow_nonref;\n $str = chr(1000); # UTF8-flagged\n\n $json_text = $json->utf8(0)->encode($str);\n utf8::is_utf8($json_text);\n # true\n $json_text = $json->utf8(1)->encode($str);\n utf8::is_utf8($json_text);\n # false\n\n $str = '\"' . chr(1000) . '\"'; # UTF8-flagged\n\n $perl_scalar = $json->utf8(0)->decode($str);\n utf8::is_utf8($perl_scalar);\n # true\n $perl_scalar = $json->utf8(1)->decode($str);\n # died because of 'Wide character in subroutine'\n\nSee to L.\n\n=item $JSON::UnMapping\n\nDisable. See to L.\n\n=item $JSON::SelfConvert\n\nThis option was deleted.\nInstead of it, if a givien blessed object has the C method,\nC will be executed with C.\n\n $json->convert_blessed->encode($bleesed_hashref_or_arrayref)\n # if need, call allow_blessed\n\nNote that it was C in old version, but now not C but C.\n\n=back\n\n=head1 TODO\n\n=over\n\n=item example programs\n\n=back\n\n=head1 THREADS\n\nNo test with JSON::PP. If with JSON::XS, See to L.\n\n\n=head1 BUGS\n\nPlease report bugs relevant to C to Emakamaka[at]cpan.orgE.\n\n\n=head1 SEE ALSO\n\nMost of the document is copied and modified from JSON::XS doc.\n\nL, L\n\nC(L)\n\n=head1 AUTHOR\n\nMakamaka Hannyaharamitu, Emakamaka[at]cpan.orgE\n\nJSON::XS was written by Marc Lehmann \n\nThe relese of this new version owes to the courtesy of Marc Lehmann.\n\n\n=head1 COPYRIGHT AND LICENSE\n\nCopyright 2005-2011 by Makamaka Hannyaharamitu\n\nThis library is free software; you can redistribute it and/or modify\nit under the same terms as Perl itself.\n\n=cut\n\n" }, { "path": "tools/Makefile", "content": "# SPDX-License-Identifier: Apache-2.0\n# Copyright 2020 Western Digital Corporation or its affiliates.\n# Copyright 2024 Antmicro \n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\n\nifeq ($(USER_MODE),1)\nUSER_MODE_OPTS = -set=user_mode=1\nelse\nUSER_MODE_OPTS =\nendif\n\nCONF_PARAMS ?= -set build_axi4 $(USER_MODE_OPTS)\n\nTEST_CFLAGS = -g -gdwarf -O3 -funroll-all-loops\nABI = -mabi=ilp32\nLD_ABI = $(ABI) -march=rv32imac\n\nTB_EXTRA_ARGS ?= --test-halt\n\n# Check for RV_ROOT\nifeq (,$(wildcard ${RV_ROOT}/configs/veer.config))\n$(error env var RV_ROOT does not point to a valid dir! Exiting!)\nendif\n\n# Allow snapshot override\ntarget = default\nsnapshot = $(target)\n\n# Allow tool override\nVEER_CONFIG = ${RV_ROOT}/configs/veer.config\nIRUN = xrun\nVCS = vcs\nVLOG = qverilog\nVERILATOR = verilator\nRIVIERA = riviera\nGCC_PREFIX = riscv64-unknown-elf\nBUILD_DIR = snapshots/${snapshot}\nTBDIR = ${RV_ROOT}/testbench\nPICOLIBC_DIR = ${RV_ROOT}/third_party/picolibc/install\n\n# Override march depending on used GCC version\nifneq ($(shell which $(GCC_PREFIX)-gcc 2> /dev/null),)\n\tGCCVERSIONGT11 := $(shell expr `$(GCC_PREFIX)-gcc -dumpversion | cut -f1 -d.` \\>= 11)\n\tifeq \"$(GCCVERSIONGT11)\" \"1\"\n\t\tCC_ABI = $(ABI) -march=rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs\n\telse\n\t\tCC_ABI = $(ABI) -march=rv32imc\n\tendif\nendif\n\n# Determine verilator version if possible. Set the flag accordingly. Since\n# version v5.006 -Wno-IMPLICIT was renamed to -Wno-IMPLICITSTATIC\nVERILATOR_NOIMPLICIT := -Wno-IMPLICITSTATIC\nVERILATOR_VERSION := $(subst .,,$(word 2,$(shell $(VERILATOR) --version)))\n\nifneq ($(TB_MAX_CYCLES),)\n\tVERILATOR_EXTRA_ARGS := -GMAX_CYCLES=$(TB_MAX_CYCLES)\nendif\n\nifeq (\"$(.SHELLSTATUS)\", \"0\")\n $(shell test $(VERILATOR_VERSION) -lt 5006)\n ifeq (\"$(.SHELLSTATUS)\", \"0\")\n VERILATOR_NOIMPLICIT := -Wno-IMPLICIT\n endif\nendif\n\nVERILATOR_SKIP_WARNINGS = $(VERILATOR_NOIMPLICIT) -Wno-TIMESCALEMOD -Wno-ASCRANGE \\\n\t-Wno-CASEINCOMPLETE -Wno-INITIALDLY -Wno-WIDTH -Wno-UNOPTFLAT -Wno-SIDEEFFECT \\\n\t-Wno-LATCH\n\n# Define test name\nTEST = hello_world\nTEST_DIR = ${TBDIR}/asm\nHEX_DIR = ${TBDIR}/hex\n\n# Coverage reporting\n# TODO: Set flags for other tools here as well\nifeq (\"$(COVERAGE)\", \"all\")\n VERILATOR_COVERAGE = --coverage\nelse ifeq (\"$(COVERAGE)\", \"branch\")\n VERILATOR_COVERAGE = --coverage-line\nelse ifeq (\"$(COVERAGE)\", \"toggle\")\n VERILATOR_COVERAGE = --coverage-toggle\nelse ifeq (\"$(COVERAGE)\", \"functional\")\n VERILATOR_COVERAGE = --coverage-user\nelse ifneq (\"$(COVERAGE)\", \"\")\n $(error Unknown COVERAGE value '$(COVERAGE)')\nendif\n\n# Determine test directory\nifneq (,$(wildcard $(TBDIR)/tests/$(TEST)))\n TEST_DIR = $(TBDIR)/tests/$(TEST)\nendif\n\nOFILES = $(TEST).o\n\nifdef debug\n DEBUG_PLUS = +dumpon\n IRUN_DEBUG = -access +rc\n IRUN_DEBUG_RUN = -input ${RV_ROOT}/testbench/input.tcl\n VCS_DEBUG = -debug_access\n VERILATOR_DEBUG = --trace\n RIVIERA_DEBUG = +access +r\nendif\n\nifdef assert\n ASSERT_DEFINES = +define+RV_ASSERT_ON\nendif\n\n# Prevent testbench from returning a non-zero exit code\nifdef tb_silent_fail\n TB_SILENT_FAIL = +define+TB_SILENT_FAIL\nendif\n\n# provide specific link file\nifeq (,$(wildcard $(TEST_DIR)/$(TEST).ld))\n\tLINK = $(BUILD_DIR)/link.ld\nelse\n\tLINK = $(TEST_DIR)/$(TEST).ld\nendif\n\nVPATH = $(TEST_DIR) $(BUILD_DIR) $(TBDIR)\n\n-include $(TEST_DIR)/$(TEST).mki\n\n# Testbench DPI sources\nTB_DPI_SRCS = jtagdpi/jtagdpi.c \\\n tcp_server/tcp_server.c\n\nTB_DPI_INCS := $(addprefix -I$(TBDIR)/,$(dir $(TB_DPI_SRCS)))\n# Add testbench include paths\nCFLAGS += $(TB_DPI_INCS)\n\nTB_DPI_SRCS := $(addprefix $(TBDIR)/,$(TB_DPI_SRCS))\n\n# Testbench sources\nTB_VERILATOR_SRCS = $(TBDIR)/test_tb_top.cpp $(TB_DPI_SRCS)\n\nTBFILES = $(TBDIR)/tb_top_pkg.sv \\\n $(TBDIR)/tb_top.sv \\\n $(TBDIR)/ahb_sif.sv \\\n $(TBDIR)/jtagdpi/jtagdpi.sv \\\n $(TBDIR)/ahb_lite_2to1_mux.sv \\\n $(TBDIR)/ahb_lsu_dma_bridge.sv \\\n $(TBDIR)/axi4_mux/axi_crossbar_wrap_2x1.v \\\n $(TBDIR)/axi4_mux/arbiter.v \\\n $(TBDIR)/axi4_mux/axi_crossbar_addr.v \\\n $(TBDIR)/axi4_mux/axi_crossbar_rd.v \\\n $(TBDIR)/axi4_mux/axi_crossbar.v \\\n $(TBDIR)/axi4_mux/axi_crossbar_wr.v \\\n $(TBDIR)/axi4_mux/axi_register_rd.v \\\n $(TBDIR)/axi4_mux/axi_register_wr.v \\\n $(TBDIR)/axi4_mux/priority_encoder.v\n\ndefines = $(BUILD_DIR)/common_defines.vh\ndefines += ${RV_ROOT}/design/include/el2_def.sv\ndefines += $(BUILD_DIR)/el2_pdef.vh\nincludes = -I${BUILD_DIR} -I$(TBDIR)/axi4_mux\n\nCM_HIER_FILE = $(RV_ROOT)/cm.cfg\n\n# Verilator supports only C++14 and newer\nCFLAGS += -std=c++14\n\n# Optimization for better performance; alternative is nothing for\n# slower runtime (faster compiles) -O2 for faster runtime (slower\n# compiles), or -O for balance.\nVERILATOR_MAKE_FLAGS = OPT_FAST=\"-Os\"\n\n# Targets\nall: clean verilator\n\nclean:\n\trm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* *.map snapshots \\\n\tverilator* *.exe obj* *.o *.sym ucli.key vc_hdrs.h csrc *.csv work \\\n\tdataset.asdb library.cfg vsimsa.cfg riviera-build wave.asdb\n\n\n\n############ Model Builds ###############################\n\n# If define files do not exist, then run veer.config.\n${BUILD_DIR}/defines.h:\n\tBUILD_PATH=${BUILD_DIR} ${RV_ROOT}/configs/veer.config -target=$(target) $(CONF_PARAMS)\n\nverilator-build: ${TBFILES} ${BUILD_DIR}/defines.h $(TB_VERILATOR_SRCS)\n\t$(VERILATOR) --cc -CFLAGS \"${CFLAGS}\" --coverage-max-width 20000 $(defines) \\\n\t $(includes) -I${RV_ROOT}/testbench -f ${RV_ROOT}/testbench/flist \\\n\t $(VERILATOR_SKIP_WARNINGS) $(VERILATOR_EXTRA_ARGS) ${TB_SILENT_FAIL} ${TBFILES} --top-module tb_top \\\n\t -exe $(TB_VERILATOR_SRCS) --autoflush --timing $(VERILATOR_DEBUG) $(VERILATOR_COVERAGE) -fno-table\n\tcp ${RV_ROOT}/testbench/test_tb_top.cpp obj_dir/\n\t$(MAKE) -e -C obj_dir/ -f Vtb_top.mk $(VERILATOR_MAKE_FLAGS)\n\ttouch verilator-build\n\nvcs-build: ${TBFILES} ${BUILD_DIR}/defines.h\n\t$(VCS) -full64 -assert svaext -sverilog +define+RV_OPENSOURCE $(ASSERT_DEFINES) \\\n\t +error+500 +incdir+${RV_ROOT}/design/lib \\\n\t +incdir+${RV_ROOT}/design/include ${BUILD_DIR}/common_defines.vh \\\n\t +incdir+$(BUILD_DIR) +libext+.v $(defines) -CFLAGS \"${CFLAGS}\" \\\n\t -cm_hier $(CM_HIER_FILE) \\\n\t -f ${RV_ROOT}/testbench/flist ${TBFILES} ${TB_DPI_SRCS} -l vcs.log\n\ttouch vcs-build\n\nirun-build: ${TBFILES} ${BUILD_DIR}/defines.h\n\t$(IRUN) -64bit -elaborate $(IRUN_DEBUG) $(ASSERT_DEFINES) -q -sv -sysv -nowarn CUVIHR \\\n\t -xmlibdirpath . -xmlibdirname veer.build \\\n\t -incdir ${RV_ROOT}/design/lib -incdir ${RV_ROOT}/design/include \\\n\t -vlog_ext +.vh+.h $(defines) -incdir $(BUILD_DIR) \\\n\t -f ${RV_ROOT}/testbench/flist -top tb_top ${TBFILES} \\\n\t -I${RV_ROOT}/testbench -elaborate -snapshot ${snapshot} $(profile)\n\ttouch irun-build\n\nriviera-build: ${TBFILES} ${BUILD_DIR}/defines.h\n\tvlib work\n\tvlog -work work ${ASSERT_DEFINES} \\\n\t\t+incdir+${RV_ROOT}/design/lib \\\n\t\t+incdir+${RV_ROOT}/design/include \\\n\t\t+incdir+${BUILD_DIR} \\\n\t\t-y ${RV_ROOT}/design/lib +libext+.v+.vh \\\n\t\t$(defines) \\\n\t\t-f ${RV_ROOT}/testbench/flist \\\n\t\t${TBFILES}\n\ttouch riviera-build\n\n############ TEST Simulation ###############################\n\nverilator: program.hex verilator-build\n\t# FIXME: Assuming here that either begin_signature or end_signature implies\n\t# that both symbols are present.\n\tgrep -E \"(begin|end)_signature\" $(TEST).sym >/dev/null 2>&1; \\\n\tif [ $$? -eq 0 ]; then \\\n\t\tBEG=`grep \"begin_signature\" $(TEST).sym | cut -d\\ -f 1`;\\\n\t\tEND=`grep \"end_signature\" $(TEST).sym | cut -d\\ -f 1`;\\\n\t\t./obj_dir/Vtb_top ${TB_EXTRA_ARGS} --mem-signature $${BEG} $${END}; \\\n\telse \\\n\t\t./obj_dir/Vtb_top ${TB_EXTRA_ARGS}; \\\n\tfi\n\nirun: program.hex irun-build\n\t$(IRUN) -64bit -abvglobalfailurelimit 1 +lic_queue -licqueue \\\n\t -status -xmlibdirpath . -xmlibdirname veer.build \\\n\t -snapshot ${snapshot} -r $(snapshot) $(IRUN_DEBUG_RUN) $(profile)\n\nvcs: program.hex vcs-build\n\t./simv $(DEBUG_PLUS) +vcs+lic+wait -l vcs.log\n\nvlog: program.hex ${TBFILES} ${BUILD_DIR}/defines.h\n\t$(VLOG) -l vlog.log -sv -mfcu +incdir+${BUILD_DIR}+${RV_ROOT}/design/include+${RV_ROOT}/design/lib -ccflags \"${CFLAGS}\"\\\n $(ASSERT_DEFINES) $(defines) -f ${RV_ROOT}/testbench/flist ${TBFILES} ${TB_DPI_SRCS} -R +nowarn3829 +nowarn2583 ${DEBUG_PLUS} -suppress 14408 -suppress 16154\n\nriviera: program.hex riviera-build\n\tvsim -c -lib work ${DEBUG_PLUS} ${RIVIERA_DEBUG} tb_top -do \"run -all; exit\" -l riviera.log\n\n\n\n############ TEST build ###############################\n\npicolibc:\n\t$(MAKE) -f ${RV_ROOT}/tools/picolibc.mk all\n\nifeq ($(shell which $(GCC_PREFIX)-gcc 2> /dev/null),)\nprogram.hex: ${BUILD_DIR}/defines.h\n\t@echo \" !!! No $(GCC_PREFIX)-gcc in path, using canned hex files !!\"\n\t$(eval USER_MODE := $(if $(shell grep \"define \\+RV_USER_MODE \\+1\" ${BUILD_DIR}/defines.h),1,0))\n\tstat ${HEX_DIR}/user_mode${USER_MODE}/$(TEST).hex >/dev/null 2>&1; \\\n\tif [ $$? -eq 0 ]; then \\\n\t\tcp ${HEX_DIR}/user_mode${USER_MODE}/$(TEST).hex program.hex; \\\n\telse \\\n\t\techo \"Canned hex not found: ${HEX_DIR}/user_mode${USER_MODE}/$(TEST).hex\"; \\\n\t\texit 1; \\\n\tfi\nelse\nifneq (,$(wildcard $(TEST_DIR)/$(TEST).makefile))\nprogram.hex: picolibc\n\t@echo Building $(TEST) via $(TEST_DIR)/$(TEST).makefile\n\t$(MAKE) -f $(TEST_DIR)/$(TEST).makefile\nelse\nprogram.hex: picolibc $(OFILES) ${BUILD_DIR}/defines.h\n\t@echo Building $(TEST)\n\t$(GCC_PREFIX)-gcc $(LD_ABI) --verbose -Wl,-Map=$(TEST).map -T$(LINK) --specs=$(PICOLIBC_DIR)/picolibc.specs $(TEST_LIBS) -nostartfiles $(OFILES) -o $(TEST).exe\n\t$(GCC_PREFIX)-objcopy -O verilog $(TEST).exe program.hex\n\t$(GCC_PREFIX)-objdump -S $(TEST).exe > $(TEST).dis\n\t$(GCC_PREFIX)-nm -B -n $(TEST).exe > $(TEST).sym\n\t@echo Completed building $(TEST)\n\n\n%.o : %.s ${BUILD_DIR}/defines.h\n\t$(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $*.cpp.s\n\t$(GCC_PREFIX)-as ${CC_ABI} $*.cpp.s -o $@\n\n\n%.o : %.c picolibc ${BUILD_DIR}/defines.h\n\t$(GCC_PREFIX)-gcc ${includes} --specs=$(PICOLIBC_DIR)/picolibc.specs ${TEST_CFLAGS} -DCOMPILER_FLAGS=\"\\\"${TEST_CFLAGS}\\\"\" ${CC_ABI} -c $< -o $@\n\nendif\nendif\n\n\nhelp:\n\t@echo Make sure the environment variable RV_ROOT is set.\n\t@echo Possible targets: verilator vcs irun vlog riviera help clean all verilator-build irun-build vcs-build riviera-build program.hex\n\n.PHONY: help clean picolibc verilator vcs irun vlog riviera\n\n" }, { "path": "tools/addassign", "content": "#!/usr/bin/perl\n\nuse Getopt::Long;\n\n$helpusage = \"placeholder\";\n\nGetOptions ('in=s' => \\$in,\n 'prefix=s' => \\$prefix) || die(\"$helpusage\");\n\n\n\n@in=`cat $in`;\n\n\nforeach $line (@in) {\n\n if ($line=~/\\#/) { next; }\n\n if ($line=~/([^=]+)=/) {\n $sig=$1;\n $sig=~s/\\s+//g;\n printf(\"logic $sig;\\n\");\n }\n}\n\nforeach $line (@in) {\n\n if ($line=~/\\#/) { next; }\n\n if ($line=~/([^=]+)=\\s*;/) {\n printf(\"assign ${prefix}$1 = 1'b0;\\n\");\n next;\n }\n\n if ($line=~/([^=]+)=\\s*\\(\\s*\\);/) {\n printf(\"assign ${prefix}$1 = 1'b0;\\n\");\n next;\n }\n\n if ($line =~ /=/) { printf(\"assign ${prefix}$line\"); }\n else { printf(\"$line\"); }\n}\n\n\nexit;\n\n" }, { "path": "tools/coredecode", "content": "#!/usr/bin/perl\n\nuse Getopt::Long;\n\n$helpusage = \"placeholder\";\n\nGetOptions ('legal' => \\$legal,\n 'in=s' => \\$in,\n 'out=s' => \\$out,\n 'view=s' => \\$view ) || die(\"$helpusage\");\n\n\nif (!defined($in)) { die(\"must define -in=input\"); }\nif (!defined($out)) { $out=\"${in}.out\"; }\n\nif ($in eq \"decode\") { $view=\"rv32i\"; }\nelsif ($in eq \"cdecode\") { $view=\"rv32c\"; }\nelsif (rindex($in,\"csrdecode\",0) == 0) { $view=\"csr\"; }\n\nif (defined($in)) { printf(\"in=$in\\n\"); }\nif (defined($out)) { printf(\"out=$out\\n\"); }\nif (defined($view)) { printf(\"view=$view\\n\"); }\n\n@in=`cat $in`;\n\n$gather=0;\n\n$TIMEOUT=50;\n\nforeach $line (@in) {\n\n #printf(\"$pstate: $line\");\n\n if ($line=~/^\\s*\\#/) { #printf(\"skip $line\");\n next; }\n\n if ($gather==1) {\n if ($line=~/(\\S+)/) {\n if ($line=~/}/) { $gather=0; $position=0; next; }\n $label=$1;\n $label=~s/,//g;\n if ($pstate==2) {\n if (defined($INPUT{$CVIEW}{$label})) { die(\"input $label already defined\"); }\n $INPUT{$CVIEW}{$label}=$position++;\n $INPUTLEN{$CVIEW}++;\n $INPUTSTR{$CVIEW}.=\" $label\";\n }\n elsif ($pstate==3) {\n if (defined($OUTPUT{$CVIEW}{$label})) { die(\"output $label already defined\"); }\n $OUTPUT{$CVIEW}{$label}=$position++;\n $OUTPUTLEN{$CVIEW}++;\n $OUTPUTSTR{$CVIEW}.=\" $label\";\n }\n else { die(\"unknown pstate $pstate in gather\"); }\n }\n }\n\n if ($line=~/^.definition/) {\n $pstate=1; next;\n }\n if ($pstate==1) { # definition\n if ($line!~/^.output/) {\n if ($line=~/(\\S+)\\s*=\\s*(\\S+)/) {\n $key=$1; $value=$2;\n $value=~s/\\./-/g;\n $value=~s/\\[//g;\n $value=~s/\\]//g;\n $DEFINITION{$key}=$value;\n }\n }\n else { $pstate=2; next; }\n }\n\n if ($line=~/^.input/) {\n $pstate=2; next;\n }\n\n if ($pstate==2) { # input\n if ($line=~/(\\S+)\\s*=\\s*\\{/) {\n $CVIEW=$1; $gather=1; next;\n }\n }\n\n if ($line=~/^.output/) {\n $pstate=3; next;\n }\n\n if ($pstate==3) { # output\n if ($line=~/(\\S+)\\s*=\\s*\\{/) {\n $CVIEW=$1; $gather=1; next;\n }\n }\n\n if ($line=~/^.decode/) {\n $pstate=4; next;\n }\n\n if ($pstate==4) { # decode\n if ($line=~/([^\\[]+)\\[([^\\]]+)\\]\\s*=\\s*\\{([^\\}]+)\\}/) {\n $dview=$1; $inst=$2; $body=$3;\n $dview=~s/\\s+//g;\n $inst=~s/\\s+//g;\n #printf(\"$dview $inst $body\\n\");\n if ($inst=~/([^\\{]+)\\{([^-]+)-([^\\}]+)\\}/) {\n $base=$1; $lo=$2; $hi=$3;\n $hi++;\n for ($i=0; $i<$TIMEOUT && $lo ne $hi; $i++) {\n #printf(\"decode $dview $base$lo\\n\");\n\n $expand=$base.$lo;\n if (!defined($DEFINITION{$expand})) { die(\"could not find instruction definition for inst $expand\"); }\n\n $DECODE{$dview}{$expand}=$body;\n $lo++;\n }\n if ($i == $TIMEOUT) { die(\"timeout in decode expansion\"); }\n\n }\n else {\n if (!defined($DEFINITION{$inst})) { die(\"could not find instruction definition for inst $inst\"); }\n $DECODE{$dview}{$inst}=$body;\n }\n }\n }\n\n}\n\n\n#printf(\"view $view len %d\\n\",$OUTPUTLEN{$view});\n\n#printf(\"$OUTPUTSTR{$view}\\n\");\n\n\n# need to switch this somehow based on 16/32\nprintf(\".i %d\\n\",$INPUTLEN{$view});\n\nif (defined($legal)) {\n printf(\".o 1\\n\");\n}\nelse {\n printf(\".o %d\\n\",$OUTPUTLEN{$view});\n}\n\nprintf(\".ilb %s\\n\",$INPUTSTR{$view});\n\nif (defined($legal)) {\n printf(\".ob legal\\n\");\n}\nelse {\n printf(\".ob %s\\n\",$OUTPUTSTR{$view});\n}\n\nif (defined($legal)) {\n printf(\".type fd\\n\");\n}\nelse {\n printf(\".type fr\\n\");\n}\n\n$DEFAULT_TEMPLATE='0'x$OUTPUTLEN{$view};\n\nforeach $inst (sort keys %{ $DECODE{$view} }) {\n\n $body=$DECODE{$view}{$inst};\n @sigs=split(' ',$body);\n\n $template=$DEFAULT_TEMPLATE;\n foreach $sig (@sigs) {\n if (!defined($OUTPUT{$view}{$sig})) { die(\"could not find output definition for sig $sig in view $view\"); }\n $position=$OUTPUT{$view}{$sig};\n substr($template,$position,1,1);\n }\n\n# if (!defined($DEFINITION{$inst})) { die(\"could not find instruction defintion for inst $inst\"); }\n\n printf(\"# $inst\\n\");\n if (defined($legal)) {\n printf(\"$DEFINITION{$inst} 1\\n\");\n }\n else {\n printf(\"$DEFINITION{$inst} $template\\n\");\n }\n\n}\n\n\nexit;\n\nforeach $inst (sort keys %DEFINITION) {\n $value=$DEFINITION{$inst};\n printf(\"%-10s = $value\\n\",$inst);\n}\n\n\nforeach $sig (sort keys %{ $OUTPUT{$view} }) {\n $position=$OUTPUT{$view}{$sig};\n printf(\"$sig $position\\n\");\n}\n" }, { "path": "tools/hex_canned_update.sh", "content": "#!/bin/bash\n# Expected usage:\n# export RV_ROOT=/path/to/cores-veer-el2\n# bash tools/hex_canned_update.sh\n\nif [[ -z \"$RV_ROOT\" ]]; then\n echo \"RV_ROOT is not set\" 1>&2\n exit 1\nfi\n\nASM=($(find $RV_ROOT/testbench/asm -maxdepth 1 -regex \".*\\.\\(s\\|mki\\)\" -printf \"%f\\n\" | sed 's/\\.\\(s\\|mki\\)$//' | grep -vE \"(common|crt0)\"))\nCT=($(find $RV_ROOT/testbench/tests -mindepth 1 -type d -printf \"%f\\n\"))\nTESTS=(\"${ASM[@]}\" \"${CT[@]}\")\necho \"Detected tests:\"\necho \"---------------\"\necho \"${TESTS[@]}\"\necho \"---------------\"\n\nUSER_MODES=(\"0\" \"1\")\n\nMAKE_CMD=\"make -f $RV_ROOT/tools/Makefile\"\nHEX_DIR=testbench/hex\n\n# Clear old hex files\nrm -rdf $HEX_DIR/*\n\nPARAMS=\"\"\nfor umode in ${USER_MODES[@]}; do\n mkdir -p $HEX_DIR/user_mode$umode\n for test in ${TESTS[@]}; do\n if [[ \"$umode\" == \"1\" ]]; then\n PARAMS=\"-set=user_mode=1 -set=smepmp=1 $PARAMS\"\n # csr_mseccfg test is only available in user mode\n elif [[ \"$test\" == \"csr_mseccfg\" ]]; then\n continue\n fi\n $MAKE_CMD clean >/dev/null\n $MAKE_CMD program.hex CONF_PARAMS=\"$PARAMS\" TEST=$test >/dev/null\n HEX_PATH=\"$HEX_DIR/user_mode$umode/$test.hex\"\n echo \"TEST = \" $test\n if [ -f \"program.hex\" ]; then\n echo \"Copying $test:program.hex to [\"$HEX_PATH\"]\"\n cp program.hex $HEX_PATH\n else\n echo \"program.hex not found. Possible build error.\"\n exit 1\n fi\n done\ndone\nexit 0\n" }, { "path": "tools/picmap", "content": "#!/usr/bin/perl\n\nuse Getopt::Long;\n\nuse integer;\n\n$helpusage = \"placeholder\";\n\nGetOptions ('total_int=s' => \\$total_int)|| die(\"$helpusage\");\n\n$LEN=15;\n\n#printf(\"logic [2:0] mask;\\n\");\n\nprintf(\"// mask[3:0] = { 4'b1000 - 30b mask,4'b0100 - 31b mask, 4'b0010 - 28b mask, 4'b0001 - 32b mask }\\n\");\nprintf(\"always_comb begin\\n\");\nprintf(\" case \\(address[14:0]\\)\\n\");\nprintf(\" 15'b011000000000000 : mask[3:0] = 4'b0100;\\n\");\nfor ($i=1; $i<=$total_int; $i++) {\n $j=hex(\"4000\");\n printf(\" 15'b%s : mask[3:0] = 4'b1000;\\n\",d2b($j+$i*4));\n}\nfor ($i=1; $i<=$total_int; $i++) {\n $j=hex(\"2000\");\n printf(\" 15'b%s : mask[3:0] = 4'b0100;\\n\",d2b($j+$i*4));\n}\nfor ($i=1; $i<=$total_int; $i++) {\n $j=hex(\"0\");\n printf(\" 15'b%s : mask[3:0] = 4'b0010;\\n\",d2b($j+$i*4));\n}\n printf(\" %-17s : mask[3:0] = 4'b0001;\\n\",\"default\");\nprintf(\" endcase\\n\");\nprintf(\"end\\n\");\n\n\nsub b2d {\n my ($v) = @_;\n\n $v = oct(\"0b\" . $v);\n\n return($v);\n}\n\nsub d2b {\n my ($v) = @_;\n\n my $repeat;\n\n $v = sprintf \"%b\",$v;\n if (length($v)<$LEN) {\n $repeat=$LEN-length($v);\n $v=\"0\"x$repeat.$v;\n }\n elsif (length($v)>$LEN) {\n $v=substr($v,length($v)-$LEN,$LEN);\n }\n\n return($v);\n}\n" }, { "path": "tools/picolibc.mk", "content": "GCC_PREFIX ?= riscv64-unknown-elf\nMAKEFILE_PATH = $(shell dirname $(realpath $(firstword $(MAKEFILE_LIST))))\nPICOLIBC_PATH = $(abspath $(MAKEFILE_PATH)/../third_party/picolibc)\nBUILD_PATH = $(PICOLIBC_PATH)/build\nINSTALL_PATH = $(PICOLIBC_PATH)/install\n\nifeq ($(CCACHE), )\n\tMESON_CROSS_CC = '$(GCC_PREFIX)-gcc'\nelse\n\tMESON_CROSS_CC = ['$(CCACHE)', '$(GCC_PREFIX)-gcc']\nendif\n\ndefine CROSSFILE\n[binaries]\nc = $(MESON_CROSS_CC)\nar = '$(GCC_PREFIX)-gcc-ar'\nas = '$(GCC_PREFIX)-as'\nnm = '$(GCC_PREFIX)-gcc-nm'\nstrip = '$(GCC_PREFIX)-strip'\n\n[host_machine]\nsystem = 'unknown'\ncpu_family = 'riscv64'\ncpu = 'riscv'\nendian = 'little'\n\n[properties]\n# this uses shorter but slower function entry code\nc_args = [ '-msave-restore' ]\n# default multilib is 64 bit\nc_args_ = [ '-mcmodel=medany' ]\nendef\n\nexport CROSSFILE\n\n$(BUILD_PATH):\n\tmkdir -p $@\n\n$(BUILD_PATH)/cross.txt: | $(BUILD_PATH)\n\t@echo \"$$CROSSFILE\" > $@\n\n$(INSTALL_PATH)/picolibc.specs: $(BUILD_PATH)/cross.txt | $(BUILD_PATH)\n\n\tcd $(PICOLIBC_PATH) && meson $(BUILD_PATH) \\\n\t\t-Dmultilib=true \\\n\t\t-Dmultilib-list=rv32imac/ilp32 \\\n\t\t-Dpicocrt=false \\\n\t\t-Datomic-ungetc=false \\\n\t\t-Dthread-local-storage=false \\\n\t\t-Dio-long-long=true \\\n\t\t-Dformat-default=integer \\\n\t\t-Dincludedir=picolibc/$(GCC_PREFIX)/include \\\n\t\t-Dlibdir=picolibc/$(GCC_PREFIX)/lib \\\n -Dprefix=$(INSTALL_PATH) \\\n -Dspecsdir=$(INSTALL_PATH) \\\n\t\t--cross-file $(BUILD_PATH)/cross.txt\n\n\tcd $(BUILD_PATH) && meson install\n\nall: $(INSTALL_PATH)/picolibc.specs\n\nclean:\n\trm -rf $(BUILD_PATH)\n\n.PHONY: all clean\n" }, { "path": "tools/prefix_macros.sh", "content": "# !/bin/bash\n\n# Set flag to exit the script on first error\nset -e\n\n# Check if RV_ROOT is set\nif [ -z \"$RV_ROOT\" ]; then\n echo \"Error: RV_ROOT is not set.\"\n exit 1\nfi\n\n# Prefix that will be added to all required macro/struct/module names\nPREFIX=\"${PREFIX:-veer0_}\"\n# Path to directory where common_defines.vh, el2_param.vh, el2_pdef.vh and pd_defines.vh reside\nDEFINES_PATH=\"${DEFINES_PATH:-${RV_ROOT}/snapshots/default}\"\n# Path to directory hierarchy where RTL sources reside\nDESIGN_DIR=\"${DESIGN_DIR:-${RV_ROOT}/design}\"\n\nCOMMON_DEFINES=\"$DEFINES_PATH/common_defines.vh\"\nEL2_PARAM=\"$DEFINES_PATH/el2_param.vh\"\nEL2_PDEF=\"$DEFINES_PATH/el2_pdef.vh\"\nPD_DEFINES=\"$DEFINES_PATH/pd_defines.vh\"\nEL2_DEF=\"$DESIGN_DIR/include/el2_def.sv\"\nEL2_IFU_IC_MEM=\"$DESIGN_DIR/ifu/el2_ifu_ic_mem.sv\"\n\necho \"Starting script with following settings:\"\necho \"PREFIX=$PREFIX\"\necho \"DEFINES_PATH=$DEFINES_PATH\"\necho -e \"DESIGN_DIR=$DESIGN_DIR\\n\"\n\n# Define regex patterns for matching defines\nDEFINES_REGEX=\"s/((\\`define)|(\\`ifndef)|(\\`undef)) ([A-Z0-9_]+).*/\\5/p\"\nDEFINES_REPLACE_REGEX=\"s/((\\`define)|(\\`ifndef)|(\\`undef)) ([A-Z0-9_]+)/\\1 \"$PREFIX\"\\5/\"\nSTRUCT_REPLACE_REGEX=\"s/el2_param_t/\"$PREFIX\"el2_param_t/g\"\nMODULES_REGEX=\"s/^module ([\\`A-Za-z0-9_]+).*/\\1/p\"\n\n# Extract unique defines from all sources\nDEFINES=\"$(sed -nr \"$DEFINES_REGEX\" $COMMON_DEFINES $PD_DEFINES $EL2_IFU_IC_MEM | sort -ur)\"\n\n# Skip files that should not be processed\nSKIP_DESIGN_FILES=\"el2_param.vh\\|el2_pdef.vh\\|common_defines.vh\\|pd_defines.vh\"\nDESIGN_FILES=\"$(find $DESIGN_DIR -name \"*.sv\" -o -name \"*.vh\" -o -name \"*.v\" | grep -v $SKIP_DESIGN_FILES)\"\nDESIGN_FILES+=\" $EXTRA_DESIGN_FILES\"\nMODULES=\"$(sed -nr \"$MODULES_REGEX\" $DESIGN_FILES | sort -ur)\"\n\nif [ \"${DEBUG}\" = \"1\" ]; then\n\techo \"DEBUG: DEFINES_REGEX=$DEFINES_REGEX\"\n\techo \"DEBUG: DEFINES_REPLACE_REGEX=$DEFINES_REPLACE_REGEX\"\n\techo \"DEBUG: STRUCT_REPLACE_REGEX=$STRUCT_REPLACE_REGEX\"\n\techo \"DEBUG: MODULES_REGEX=$MODULES_REGEX\"\n\techo\n\techo \"DEBUG: DEFINES=$DEFINES\"\n\techo \"DEBUG: DESIGN_FILES=$DESIGN_FILES\"\n\techo \"DEBUG: MODULES=$MODULES\"\n\techo\nfi\n\n# Add prefix to macro names\nOUTPUT_COMMON_DEFINES=$DEFINES_PATH/\"$PREFIX\"common_defines.vh\nOUTPUT_PD_DEFINES=$DEFINES_PATH/\"$PREFIX\"pd_defines.vh\necho \"Adding prefix to macro names in $OUTPUT_COMMON_DEFINES and $OUTPUT_PD_DEFINES\"\nsed -E \"$DEFINES_REPLACE_REGEX\" $COMMON_DEFINES >$OUTPUT_COMMON_DEFINES\nsed -E \"$DEFINES_REPLACE_REGEX\" $PD_DEFINES >$OUTPUT_PD_DEFINES\n\n# Add prefix to RV_RCG macros\nRV_RCG_REPLACE_REGEX=\"s/^(\\`define \"${PREFIX}\"\\w+_RV_ICG )(\\w+)/\\1\"${PREFIX}\"\\2/g\"\nsed -i -E \"$RV_RCG_REPLACE_REGEX\" $OUTPUT_COMMON_DEFINES\n\n# Add prefix to VeeR config struct\nOUTPUT_EL2_PARAM=$DEFINES_PATH/\"$PREFIX\"el2_param.vh\nOUTPUT_EL2_PDEF=$DEFINES_PATH/\"$PREFIX\"el2_pdef.vh\necho \"Adding prefix to VeeR config struct in $OUTPUT_EL2_PARAM and $OUTPUT_EL2_PDEF\"\n\nsed \"$STRUCT_REPLACE_REGEX\" \"$EL2_PARAM\" >$OUTPUT_EL2_PARAM\nsed \"$STRUCT_REPLACE_REGEX\" \"$EL2_PDEF\" >$OUTPUT_EL2_PDEF\nsed -i \"$STRUCT_REPLACE_REGEX\" $DESIGN_FILES\n\n# Replace renamed macros in RTL sources\necho \"Replacing renamed macros in RTL sources\"\nfor DEFINE in $DEFINES; do\n\tsed -i \"s/\\`$DEFINE/\\`\"$PREFIX\"$DEFINE/g\" $DESIGN_FILES\n\tsed -i -E \"s/((\\`ifdef)|(\\`ifndef)) $DEFINE/\\1 \"$PREFIX\"$DEFINE/g\" $DESIGN_FILES\ndone\n\n# Replace include names in RTL sources\necho \"Replacing include names in RTL sources\"\nsed -i \"s/include \\\"el2_param.vh\\\"/include \\\"\"$PREFIX\"el2_param.vh\\\"/g\" $DESIGN_FILES\nsed -i \"s/include \\\"el2_pdef.vh\\\"/include \\\"\"$PREFIX\"el2_pdef.vh\\\"/g\" $DESIGN_FILES\nsed -i \"s/include \\\"common_defines.vh\\\"/include \\\"\"$PREFIX\"common_defines.vh\\\"/g\" $OUTPUT_PD_DEFINES\n\n# Replace package name and its imports in RTL sources\necho \"Replacing package name and its imports in RTL sources\"\nsed -i \"s/import el2_pkg/import \"$PREFIX\"el2_pkg/g\" $DESIGN_FILES\nsed -i \"s/package el2_pkg/package \"$PREFIX\"el2_pkg/g\" $EL2_DEF\n\n# Add prefix to all module names\necho \"Adding prefix to all module names\"\nperl -pi -e \"s/module \\`?(?!${PREFIX})([A-Za-z0-9_]+)/module ${PREFIX}\\1/g\" $DESIGN_FILES\n\n# Add prefix to all module instantiations\necho \"Adding prefix to all module instantiations\"\nfor MODULE in $MODULES; do\n # Exclude the prefix from the MODULE name if it already contains the prefix\n MODULE=$(echo $MODULE | perl -pe \"s/${PREFIX}//\")\n echo \"Processing MODULE=$MODULE\"\n perl -pi -e \"s/(^|[^A-Za-z0-9_])(?/tests/requirements.txt\n ```\n1. For your shell run (assuming that Renode is in your system's `PATH`):\n ```shell\n renode-test veer.robot\n ```\n\n## Directory structure\n\n* [veer.resc](veer.resc) - Renode script defining the simulation environment\n* [veer.repl](veer.repl) - Renode platform description used in user mode tests\n* [veer.robot](veer.robot) - [Robot Framework](https://robotframework.org/) test file, listing all test cases to be run in Renode\n* [build-all-tests.sh](build-all-tests.sh) - Shell script used for building test binaries\n* [run-tests.sh](run-tests.sh) - Shell script used to simplify executing user mode tests.\n" }, { "path": "tools/renode/build-all-tests.sh", "content": "#!/usr/bin/env bash\nset -x\nset -e\n\ntest_dir=${RV_ROOT}/testbench/tests/\ntests=\"csr_access csr_misa csr_mstatus dhry insns irq modesw perf_counters pmp\"\n\nmkdir -p build\ncd build\nfor test in ${tests}; do\n test_name=$(basename ${test})\n make CFLAGS=-DUSE_HTIF=false -f ${RV_ROOT}/tools/Makefile TEST=${test_name} USER_MODE=1 program.hex\n mv ${test_name}.exe ../${test_name}.elf\n make -f ${RV_ROOT}/tools/Makefile clean\ndone\ncd -\n" }, { "path": "tools/renode/veer.repl", "content": "mem: Memory.MappedMemory @sysbus 0x80000000\n size: 0x10000000\n\nhtif_mem: Memory.MappedMemory @sysbus 0xD0580000\n size: 0x1000\n\ncpu: CPU.VeeR_EL2 @ sysbus\n hartId: 0\n\ndhry_mem: Memory.MappedMemory @sysbus 0xF0040000\n size: 0x10000\n" }, { "path": "tools/renode/veer.resc", "content": ":name: VeeR\n$name?=\"VeeR\"\n\n# Set to path of the ELF program to run\n$bin?=$ORIGIN/csr_access.elf\n\nusing sysbus\nmach create $name\n\n$platform?=$ORIGIN/veer.repl\nmachine LoadPlatformDescription $platform\n\nmacro reset\n\"\"\"\n\tsysbus LoadELF $bin\n\"\"\"\n\nrunMacro $reset\n\nmachine CreateVirtualConsole \"htif\"\n\npython \"\"\"\nfrom Antmicro.Renode.Peripherals.Bus import Access, SysbusAccessWidth\nhtif = monitor.Machine[\"sysbus.htif\"]\nbus = monitor.Machine.SystemBus\n\ndef store_char(_, __, ___, value):\n if(value not in (0x1, 0xFF) and value < 0xFF):\n htif.DisplayChar(value)\n else:\n for x in [ord(c) for c in \"\\nFinished: \" + (\"FAILED\\n\" if value == 0x1 else \"PASSED\\n\")]:\n htif.DisplayChar(x)\n htif.DebugLog(\"TEST FINISHED\")\n monitor.Machine.Pause()\n\nbus.AddWatchpointHook(bus.GetSymbolAddress(\"tohost\"), SysbusAccessWidth.DoubleWord, Access.Write, store_char)\nbus.AddWatchpointHook(bus.GetSymbolAddress(\"tohost\"), SysbusAccessWidth.Byte, Access.Write, store_char)\n\"\"\"\n\ncpu WfiAsNop true\nshowAnalyzer htif\n" }, { "path": "tools/renode/veer.robot", "content": "*** Keywords ***\nPrepare Machine\n [Arguments] ${bin}\n Execute Command $bin=@${bin}\n Execute Command i @${CURDIR}/veer.resc\n Create Terminal Tester sysbus.htif timeout=0 defaultMatchNextLine=true\n Create Log Tester 1\n Execute Command logLevel 0 sysbus.htif\n Wait For Log Entry TEST FINISHED level=Debug\n\nWait For Regex\n [Arguments] ${pattern}\n Wait For Line On Uart ${pattern} treatAsRegex=true\n\nWait For OK Message\n [Arguments] ${pattern}\n Wait For Regex \\\\[\\\\s+OK\\\\s+\\\\] ${pattern}\n\nCheck CSR Access\n [Arguments] ${pattern} ${expect_trap}=${False}\n IF ${expect_trap}\n Wait For Line On Uart trap! mstatus=0x00000000, mcause=0x00000002\n END\n Wait For OK Message ${pattern}\n\n*** Test Cases ***\nShould Have All CSRs\n # We are testing SMEPMP registers here, so make sure the extension is active (mseccfg, mseccfgh)\n Execute Command $platform=@${CURDIR}/veer_smepmp.repl\n Prepare Machine ${CURDIR}/csr_access.elf\n\n Wait For Line On Uart ${EMPTY}\n Wait For Line On Uart Hello VeeR\n Wait For Line On Uart Testing CSR read...\n Check CSR Access 0xF11 'mvendorid'\n Check CSR Access 0xF12 'marchid'\n Check CSR Access 0xF13 'mimpid'\n Check CSR Access 0xF14 'mhartid'\n Check CSR Access 0x300 'mstatus'\n Check CSR Access 0x301 'misa'\n Check CSR Access 0x304 'mie'\n Check CSR Access 0x305 'mtvec'\n Check CSR Access 0x306 'mcounteren'\n Check CSR Access 0x320 'mcountinhibit'\n Check CSR Access 0x340 'mscratch'\n Check CSR Access 0x341 'mepc'\n Check CSR Access 0x342 'mcause'\n Check CSR Access 0x343 'mtval'\n Check CSR Access 0x344 'mip'\n Check CSR Access 0xB00 'mcycle'\n Check CSR Access 0xB02 'minstret'\n Check CSR Access 0xB80 'mcycleh'\n Check CSR Access 0xB82 'minstreth'\n Check CSR Access 0x30A 'menvcfg'\n Check CSR Access 0x31A 'menvcfgh'\n Check CSR Access 0x747 'mseccfg'\n Check CSR Access 0x757 'mseccfgh'\n Check CSR Access 0x3A0 'pmpcfg0'\n Check CSR Access 0x3B0 'pmpaddr0'\n Check CSR Access 0x3C0 'pmpaddr16'\n Check CSR Access 0x3D0 'pmpaddr32'\n Check CSR Access 0x3E0 'pmpaddr48'\n Check CSR Access 0xC00 'cycle'\n Check CSR Access 0xC80 'cycleh'\n Check CSR Access 0xC02 'instret'\n Check CSR Access 0xC82 'instreth'\n Check CSR Access 0x7FF 'mscause'\n Check CSR Access 0xBC0 'mdeau'\n Check CSR Access 0xFC0 'mdseac'\n Check CSR Access 0xBC8 'meivt'\n Check CSR Access 0xFC8 'meihap'\n Check CSR Access 0xBC9 'meipt'\n Check CSR Access 0xBCC 'meicurpl'\n Check CSR Access 0xBCB 'meicidpl'\n Check CSR Access 0x7A0 'mtsel'\n Check CSR Access 0x7A1 'mtdata1'\n Check CSR Access 0x7A2 'mtdata2'\n Check CSR Access 0x7C0 'mrac'\n Check CSR Access 0xB03 'mhpmc3'\n Check CSR Access 0xB04 'mhpmc4'\n Check CSR Access 0xB05 'mhpmc5'\n Check CSR Access 0xB06 'mhpmc6'\n Check CSR Access 0xB83 'mhpmc3h'\n Check CSR Access 0xB84 'mhpmc4h'\n Check CSR Access 0xB85 'mhpmc5h'\n Check CSR Access 0xB86 'mhpmc6h'\n Check CSR Access 0x323 'mhpme3'\n Check CSR Access 0x324 'mhpme4'\n Check CSR Access 0x325 'mhpme5'\n Check CSR Access 0x326 'mhpme6'\n Check CSR Access 0x7F0 'micect'\n Check CSR Access 0x7F1 'miccmect'\n Check CSR Access 0x7F2 'mdccmect'\n Check CSR Access 0x7C6 'mpmc'\n Check CSR Access 0x7F8 'mcgc'\n Check CSR Access 0x7C2 'mcpc'\n Check CSR Access 0x7F9 'mfdc'\n Check CSR Access 0x7D4 'mitctl0'\n Check CSR Access 0x7D7 'mitctl1'\n Check CSR Access 0x7D3 'mitb0'\n Check CSR Access 0x7D6 'mitb1'\n Check CSR Access 0x7D2 'mitcnt0'\n Check CSR Access 0x7D5 'mitcnt1'\n Check CSR Access 0xB07 'perfva'\n Check CSR Access 0xB08 'perfvb'\n Check CSR Access 0xB10 'perfvc'\n Check CSR Access 0xB87 'perfvd'\n Check CSR Access 0xB88 'perfve'\n Check CSR Access 0xB90 'perfvf'\n Check CSR Access 0x327 'perfvg'\n Check CSR Access 0x328 'perfvh'\n Check CSR Access 0x330 'perfvi'\n Check CSR Access 0x7CE 'mfdht'\n Check CSR Access 0x7CF 'mfdhs'\n Wait For Line On Uart Testing CSR write...\n Check CSR Access 0x304 'mie'\n Check CSR Access 0x340 'mscratch'\n Check CSR Access 0x30A 'menvcfg'\n Check CSR Access 0x31A 'menvcfgh'\n Wait For Line On Uart ${EMPTY}\n Wait For Line On Uart Hello from user_main()\n Wait For Line On Uart Testing CSR read...\n Check CSR Access 0xF11 'mvendorid' expect_trap=${True}\n Check CSR Access 0xF12 'marchid' expect_trap=${True}\n Check CSR Access 0xF13 'mimpid' expect_trap=${True}\n Check CSR Access 0xF14 'mhartid' expect_trap=${True}\n Check CSR Access 0x300 'mstatus' expect_trap=${True}\n Check CSR Access 0x301 'misa' expect_trap=${True}\n Check CSR Access 0x304 'mie' expect_trap=${True}\n Check CSR Access 0x305 'mtvec' expect_trap=${True}\n Check CSR Access 0x306 'mcounteren' expect_trap=${True}\n Check CSR Access 0x320 'mcountinhibit' expect_trap=${True}\n Check CSR Access 0x340 'mscratch' expect_trap=${True}\n Check CSR Access 0x341 'mepc' expect_trap=${True}\n Check CSR Access 0x342 'mcause' expect_trap=${True}\n Check CSR Access 0x343 'mtval' expect_trap=${True}\n Check CSR Access 0x344 'mip' expect_trap=${True}\n Check CSR Access 0xB00 'mcycle' expect_trap=${True}\n Check CSR Access 0xB02 'minstret' expect_trap=${True}\n Check CSR Access 0xB80 'mcycleh' expect_trap=${True}\n Check CSR Access 0xB82 'minstreth' expect_trap=${True}\n Check CSR Access 0x30A 'menvcfg' expect_trap=${True}\n Check CSR Access 0x31A 'menvcfgh' expect_trap=${True}\n Check CSR Access 0x747 'mseccfg' expect_trap=${True}\n Check CSR Access 0x757 'mseccfgh' expect_trap=${True}\n Check CSR Access 0x3A0 'pmpcfg0' expect_trap=${True}\n Check CSR Access 0x3B0 'pmpaddr0' expect_trap=${True}\n Check CSR Access 0x3C0 'pmpaddr16' expect_trap=${True}\n Check CSR Access 0x3D0 'pmpaddr32' expect_trap=${True}\n Check CSR Access 0x3E0 'pmpaddr48' expect_trap=${True}\n Check CSR Access 0xC00 'cycle'\n Check CSR Access 0xC80 'cycleh'\n Check CSR Access 0xC02 'instret'\n Check CSR Access 0xC82 'instreth'\n Check CSR Access 0x7FF 'mscause' expect_trap=${True}\n Check CSR Access 0xBC0 'mdeau' expect_trap=${True}\n Check CSR Access 0xFC0 'mdseac' expect_trap=${True}\n Check CSR Access 0xBC8 'meivt' expect_trap=${True}\n Check CSR Access 0xFC8 'meihap' expect_trap=${True}\n Check CSR Access 0xBC9 'meipt' expect_trap=${True}\n Check CSR Access 0xBCC 'meicurpl' expect_trap=${True}\n Check CSR Access 0xBCB 'meicidpl' expect_trap=${True}\n Check CSR Access 0x7A0 'mtsel' expect_trap=${True}\n Check CSR Access 0x7A1 'mtdata1' expect_trap=${True}\n Check CSR Access 0x7A2 'mtdata2' expect_trap=${True}\n Check CSR Access 0x7C0 'mrac' expect_trap=${True}\n Check CSR Access 0xB03 'mhpmc3' expect_trap=${True}\n Check CSR Access 0xB04 'mhpmc4' expect_trap=${True}\n Check CSR Access 0xB05 'mhpmc5' expect_trap=${True}\n Check CSR Access 0xB06 'mhpmc6' expect_trap=${True}\n Check CSR Access 0xB83 'mhpmc3h' expect_trap=${True}\n Check CSR Access 0xB84 'mhpmc4h' expect_trap=${True}\n Check CSR Access 0xB85 'mhpmc5h' expect_trap=${True}\n Check CSR Access 0xB86 'mhpmc6h' expect_trap=${True}\n Check CSR Access 0x323 'mhpme3' expect_trap=${True}\n Check CSR Access 0x324 'mhpme4' expect_trap=${True}\n Check CSR Access 0x325 'mhpme5' expect_trap=${True}\n Check CSR Access 0x326 'mhpme6' expect_trap=${True}\n Check CSR Access 0x7F0 'micect' expect_trap=${True}\n Check CSR Access 0x7F1 'miccmect' expect_trap=${True}\n Check CSR Access 0x7F2 'mdccmect' expect_trap=${True}\n Check CSR Access 0x7C6 'mpmc' expect_trap=${True}\n Check CSR Access 0x7F8 'mcgc' expect_trap=${True}\n Check CSR Access 0x7C2 'mcpc' expect_trap=${True}\n Check CSR Access 0x7F9 'mfdc' expect_trap=${True}\n Check CSR Access 0x7D4 'mitctl0' expect_trap=${True}\n Check CSR Access 0x7D7 'mitctl1' expect_trap=${True}\n Check CSR Access 0x7D3 'mitb0' expect_trap=${True}\n Check CSR Access 0x7D6 'mitb1' expect_trap=${True}\n Check CSR Access 0x7D2 'mitcnt0' expect_trap=${True}\n Check CSR Access 0x7D5 'mitcnt1' expect_trap=${True}\n Check CSR Access 0xB07 'perfva' expect_trap=${True}\n Check CSR Access 0xB08 'perfvb' expect_trap=${True}\n Check CSR Access 0xB10 'perfvc' expect_trap=${True}\n Check CSR Access 0xB87 'perfvd' expect_trap=${True}\n Check CSR Access 0xB88 'perfve' expect_trap=${True}\n Check CSR Access 0xB90 'perfvf' expect_trap=${True}\n Check CSR Access 0x327 'perfvg' expect_trap=${True}\n Check CSR Access 0x328 'perfvh' expect_trap=${True}\n Check CSR Access 0x330 'perfvi' expect_trap=${True}\n Check CSR Access 0x7CE 'mfdht' expect_trap=${True}\n Check CSR Access 0x7CF 'mfdhs' expect_trap=${True}\n Wait For Line On Uart Testing CSR write...\n Check CSR Access 0x304 'mie' expect_trap=${True}\n Check CSR Access 0x340 'mscratch' expect_trap=${True}\n Check CSR Access 0x30A 'menvcfg' expect_trap=${True}\n Check CSR Access 0x31A 'menvcfgh' expect_trap=${True}\n Wait For Line On Uart Attempting to write mscratch...\n Wait For Line On Uart trap! mstatus=0x00000000, mcause=0x00000002\n Wait For Line On Uart trap! mstatus=0x00000000, mcause=0x00000008\n Wait For Line On Uart ${EMPTY}\n Wait For Line On Uart Hello from machine_main()\n Wait For Line On Uart Reading mscratch...\n Wait For Regex \\\\[\\\\s+OK\\\\s+\\\\]\n\n Wait For Line On Uart Finished: PASSED matchNextLine=false\n\nShould Have Correct MStatus\n Prepare Machine ${CURDIR}/csr_mstatus.elf\n\n Wait For Line On Uart M mode:\n Wait For Line On Uart 0x1800\n Wait For Line On Uart 0x1800\n Wait For Line On Uart ok.\n Wait For Line On Uart S mode:\n Wait For Line On Uart 0x800\n Wait For Line On Uart 0x1800\n Wait For Line On Uart not supported.\n Wait For Line On Uart U mode:\n Wait For Line On Uart 0x0\n Wait For Line On Uart 0x0\n Wait For Line On Uart ok.\n Wait For Line On Uart MPRV\n Wait For Line On Uart 0x20000\n Wait For Line On Uart 0x20000\n Wait For Line On Uart ok.\n Wait For Line On Uart 0x0\n Wait For Line On Uart 0x0\n Wait For Line On Uart ok.\n\n Wait For Line On Uart Finished: PASSED matchNextLine=false\n\nShould Have Correct MISA\n Prepare Machine ${CURDIR}/csr_misa.elf\n\n Wait For Line On Uart misa = 0x40101104 vs. 0x40101104\n Wait For Line On Uart Finished: PASSED matchNextLine=false\n\nShould Pass Dhrystone Benchmark\n Prepare Machine ${CURDIR}/dhry.elf\n Wait For Line On Uart Finished: PASSED matchNextLine=false\n\nShould Implement Insn\n Prepare Machine ${CURDIR}/insns.elf\n\n Wait For Line On Uart Hello VeeR\n Wait For Line On Uart testing EBREAK\n Wait For Line On Uart trap! mstatus=0x1800, mcause=0x3, mepc=0x800002f6, insn=0x19002\n Wait For Line On Uart pass\n Wait For Line On Uart testing ECALL\n Wait For Line On Uart trap! mstatus=0x1800, mcause=0xb, mepc=0x80000332, insn=0x73\n Wait For Line On Uart pass\n Wait For Line On Uart testing WFI\n Wait For Line On Uart pass\n Wait For Line On Uart testing SRET\n Wait For Line On Uart trap! mstatus=0x1800, mcause=0x2, mepc=0x80000378, insn=0x10200073\n Wait For Line On Uart pass\n Wait For Line On Uart Hello from user_main()\n Wait For Line On Uart testing EBREAK\n Wait For Line On Uart trap! mstatus=0x80, mcause=0x3, mepc=0x8000010c, insn=0x19002\n Wait For Line On Uart pass\n Wait For Line On Uart testing ECALL\n Wait For Line On Uart trap! mstatus=0x80, mcause=0x8, mepc=0x8000014c, insn=0x73\n Wait For Line On Uart pass\n Wait For Line On Uart testing WFI\n Wait For Line On Uart pass\n Wait For Line On Uart testing SRET\n Wait For Line On Uart trap! mstatus=0x80, mcause=0x2, mepc=0x80000196, insn=0x10200073\n Wait For Line On Uart pass\n Wait For Line On Uart testing MRET\n Wait For Line On Uart trap! mstatus=0x80, mcause=0x2, mepc=0x800001c4, insn=0x30200073\n Wait For Line On Uart pass\n\n Wait For Line On Uart Finished: PASSED matchNextLine=false\n\nShould Correctly Implement Mode Switch\n Prepare machine ${CURDIR}/modesw.elf\n\n Wait For Line On Uart Hello VeeR\n Wait For OK Message MPRV cleared\n Wait For OK Message MPP is 11\n Wait For Line On Uart doing ECALL (MPRV=0)...\n Wait For Line On Uart trap! mstatus=0x1800, mcause=0xb, mepc=0x80000136\n Wait For Line On Uart Hello ECALL.M\n Wait For OK Message MPRV cleared\n Wait For OK Message MPP is 00\n Wait For Line On Uart doing ECALL (MPRV=1)\n Wait For Line On Uart trap! mstatus=0x21800, mcause=0xb, mepc=0x80000136\n Wait For Line On Uart Hello ECALL.M\n Wait For OK Message MPRV is set\n Wait For OK Message MPP is 00\n Wait For Line On Uart Hello from user_main()\n Wait For Line On Uart doing ECALL...\n Wait For Line On Uart trap! mstatus=0x80, mcause=0x8, mepc=0x80000136\n Wait For Line On Uart Hello ECALL.U\n Wait For Line On Uart clearing mstatus.MPRV\n Wait For OK Message MPP is 00\n Wait For Line On Uart doing ECALL...\n Wait For Line On Uart trap! mstatus=0x80, mcause=0x8, mepc=0x80000136\n Wait For Line On Uart Hello ECALL.U\n Wait For OK Message MPRV was cleared\n Wait For Line On Uart doing ECALL...\n Wait For Line On Uart trap! mstatus=0x80, mcause=0x8, mepc=0x80000136\n Wait For Line On Uart Hello ECALL.U\n Wait For Line On Uart setting mstatus.MPRV\n Wait For OK Message MPP is 00\n Wait For Line On Uart doing ECALL...\n Wait For Line On Uart trap! mstatus=0x80, mcause=0x8, mepc=0x80000136\n Wait For Line On Uart Hello ECALL.U\n Wait For OK Message MPRV was cleared\n Wait For Line On Uart traps taken:\n Wait For Line On Uart 0. mcause=0xb mstatus=0x1800\n Wait For Line On Uart 1. mcause=0xb mstatus=0x21800\n Wait For Line On Uart 2. mcause=0x8 mstatus=0x80\n Wait For Line On Uart 3. mcause=0x8 mstatus=0x80\n Wait For Line On Uart 4. mcause=0x8 mstatus=0x80\n Wait For Line On Uart 5. mcause=0x8 mstatus=0x80\n Wait For OK Message trap sequence verified\n\n Wait For Line On Uart Finished: PASSED matchNextLine=false\n\nShould Implement PMP\n Prepare Machine ${CURDIR}/pmp.elf\n Wait For Line On Uart Hello VeeR (M mode)\n Wait For Line On Uart VeeR does not have Smepmp\n Wait For Line On Uart PMP G=0, granularity is 4\n Wait For Line On Uart 00 - User mode RWX in default state\n Wait For Line On Uart testing...\n Wait For Line On Uart hello\n Wait For Line On Uart pass\n Wait For Line On Uart 01 - User mode RWX with one (any) PMP region enabled\n Wait For Line On Uart testing...\n Wait For Line On Uart Trap! mcause=0x00000001, mepc=0x80000420, sp=0x80007E34\n Wait For Line On Uart pass\n Wait For Line On Uart 02 - User mode RWX with code, data and stack access allowed\n Wait For Line On Uart testing...\n Wait For Line On Uart hello\n Wait For Line On Uart pass\n Wait For Line On Uart 03 - User mode (MPRV=0, MPP=0) --- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart Trap! mcause=0x00000007, mepc=0x8000046C, sp=0x80007E24\n Wait For Line On Uart data mismatch\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart Trap! mcause=0x00000005, mepc=0x800004DC, sp=0x80007DD4\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart Trap! mcause=0x00000001, mepc=0x80004040, sp=0x80007E34\n Wait For Line On Uart pass\n Wait For Line On Uart 04 - User mode (MPRV=0, MPP=0) R-- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart Trap! mcause=0x00000007, mepc=0x8000046C, sp=0x80007E24\n Wait For Line On Uart data mismatch\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart Trap! mcause=0x00000001, mepc=0x80004040, sp=0x80007E34\n Wait For Line On Uart pass\n Wait For Line On Uart 05 - User mode (MPRV=0, MPP=0) -W- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart 06 - User mode (MPRV=0, MPP=0) RW- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart Trap! mcause=0x00000001, mepc=0x80004040, sp=0x80007E34\n Wait For Line On Uart pass\n Wait For Line On Uart 07 - User mode (MPRV=0, MPP=0) --X from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart Trap! mcause=0x00000007, mepc=0x8000046C, sp=0x80007E24\n Wait For Line On Uart data mismatch\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart Trap! mcause=0x00000005, mepc=0x800004DC, sp=0x80007DD4\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 08 - User mode (MPRV=0, MPP=0) R-X from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart Trap! mcause=0x00000007, mepc=0x8000046C, sp=0x80007E24\n Wait For Line On Uart data mismatch\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 09 - User mode (MPRV=0, MPP=0) -WX from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart 10 - User mode (MPRV=0, MPP=0) RWX from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 11 - Machine mode (MPRV=0, MPP=0) --- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 12 - Machine mode (MPRV=0, MPP=0) R-- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 13 - Machine mode (MPRV=0, MPP=0) -W- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart 14 - Machine mode (MPRV=0, MPP=0) RW- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 15 - Machine mode (MPRV=0, MPP=0) --X from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 16 - Machine mode (MPRV=0, MPP=0) R-X from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 17 - Machine mode (MPRV=0, MPP=0) -WX from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart 18 - Machine mode (MPRV=0, MPP=0) RWX from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 19 - Machine mode (MPRV=1, MPP=0) --- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart Trap! mcause=0x00000007, mepc=0x8000046C, sp=0x80007E34\n Wait For Line On Uart data mismatch\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart Trap! mcause=0x00000005, mepc=0x800004DC, sp=0x80007DE4\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 20 - Machine mode (MPRV=1, MPP=0) R-- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart Trap! mcause=0x00000007, mepc=0x8000046C, sp=0x80007E34\n Wait For Line On Uart data mismatch\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 21 - Machine mode (MPRV=1, MPP=0) -W- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart 22 - Machine mode (MPRV=1, MPP=0) RW- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 23 - Machine mode (MPRV=1, MPP=0) --X from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart Trap! mcause=0x00000007, mepc=0x8000046C, sp=0x80007E34\n Wait For Line On Uart data mismatch\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart Trap! mcause=0x00000005, mepc=0x800004DC, sp=0x80007DE4\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 24 - Machine mode (MPRV=1, MPP=0) R-X from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart Trap! mcause=0x00000007, mepc=0x8000046C, sp=0x80007E34\n Wait For Line On Uart data mismatch\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 25 - Machine mode (MPRV=1, MPP=0) -WX from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart 26 - Machine mode (MPRV=1, MPP=0) RWX from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 27 - Machine mode (MPRV=1, MPP=1) --- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 28 - Machine mode (MPRV=1, MPP=1) R-- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 29 - Machine mode (MPRV=1, MPP=1) -W- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart 30 - Machine mode (MPRV=1, MPP=1) RW- from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 31 - Machine mode (MPRV=1, MPP=1) --X from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 32 - Machine mode (MPRV=1, MPP=1) R-X from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 33 - Machine mode (MPRV=1, MPP=1) -WX from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart 34 - Machine mode (MPRV=1, MPP=1) RWX from designated areas\n Wait For Line On Uart configuring PMP...\n Wait For Line On Uart testing W...\n Wait For Line On Uart writing to .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing R...\n Wait For Line On Uart reading from .area...\n Wait For Line On Uart data match\n Wait For Line On Uart pass\n Wait For Line On Uart testing X...\n Wait For Line On Uart hello from .area\n Wait For Line On Uart pass\n Wait For Line On Uart 35 - Testing execution from a locked region in U and M mode\n Wait For Line On Uart testing from U mode...\n Wait For Line On Uart Trap! mcause=0x00000001, mepc=0x80004040, sp=0x80007E34\n Wait For Line On Uart pass\n Wait For Line On Uart testing from M mode...\n Wait For Line On Uart Trap! mcause=0x00000001, mepc=0x80004040, sp=0x80007E44\n Wait For Line On Uart pass\n Wait For Line On Uart attempting to unlock region...\n Wait For Line On Uart testing from U mode...\n Wait For Line On Uart Trap! mcause=0x00000001, mepc=0x80004040, sp=0x80007E34\n Wait For Line On Uart pass\n Wait For Line On Uart testing from M mode...\n Wait For Line On Uart Trap! mcause=0x00000001, mepc=0x80004040, sp=0x80007E44\n Wait For Line On Uart pass\n Wait For Line On Uart 36/36 passed\n\n Wait For Line On Uart Finished: PASSED matchNextLine=false\n" }, { "path": "tools/renode/veer_smepmp.repl", "content": "mem: Memory.MappedMemory @sysbus 0x80000000\n size: 0x10000000\n\nhtif_mem: Memory.MappedMemory @sysbus 0xD0580000\n size: 0x1000\n\ncpu: CPU.VeeR_EL2 @ sysbus\n cpuType: \"rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs_Smepmp\"\n hartId: 0\n\ndhry_mem: Memory.MappedMemory @sysbus 0xF0040000\n size: 0x10000\n" }, { "path": "tools/riscof/README.md", "content": "# RISCOF for VeeR-EL2 Core\n\nThis folder stores configuration files and plugins needed for running [RISCOF](https://riscof.readthedocs.io/en/stable/) tests for VeeR-EL2 Core.\n\nRISCOF is an official RISC-V core testing framework. Testing is done by executing predefined test programs on the simulated core (RTL simulation) and using an Instruction Set Simulator (ISS) followed comparing memory signatures. A memory signature is a memory region defined by a particular test program which content is compared.\n\n## Install prerequisities\n\n1. Verilator\n\nInstallation instructions are available in the [Verilator's User Guide](https://veripool.org/guide/latest/install.html). Make sure that the verilator executable is available (eg. by setting `PATH`).\n\n2. Spike (Instruction Set Simulator)\n\nFollow the instruction from the [documentation](https://github.com/riscv-software-src/riscv-isa-sim#build-steps). After installation make sure that the spike binary is visible in the current path.\n\n3. RISC-V toolchain\n\nDownload and install RISC-V GCC toolchain capable for targeting RV32IMC architecture. Depending on your system this may be done either via the system package manager or manually by downloading binaries / building them.\n\n## Setup\n\n1. Clone VeeR-EL2 Core repository with submodules and set `RV_ROOT` to the repository path:\n\n```\ngit clone --recurse-submodules git@github.com:chipsalliance/Cores-VeeR-EL2.git\ncd Cores-Veer-EL2\nexport RV_ROOT=$(pwd)\n```\n\n2. Build verilated model of VeeR-EL2 Core\n\n```\n${RV_ROOT}/configs/veer.config\nmake -f ${RV_ROOT}/tools/Makefile verilator-build\n```\n\n3. Install RISCOF (in a Python virtual environment)\n\n```\npython3 -m venv env\nsource env/bin/activate\npip install git+https://github.com/riscv/riscof\n```\n\n4. Clone RISCOF official tests\n\nThe RISCOF framework uses manually developed official test programs. These need to be installed:\n\n```\nmkdir work\ncd work\nriscof --verbose info arch-test --clone\n```\n\n5. Configure RISCOF\n\nCopy RISCOF configuration from VeeR-EL2 Core repository to the working directory and build the test list:\n```\ncp ${RV_ROOT}/tools/riscof/config.ini ./\ncp -r ${RV_ROOT}/tools/riscof/spike ./\ncp -r ${RV_ROOT}/tools/riscof/veer ./\nriscof testlist --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env\n```\n\n## Running the tests\n\nTo run the tests issue the following command. Once the tests finish a HTML report will be generated\n```\nriscof run --no-browser --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env\n```\n\n## CI\n\nRISCOF tests are run in CI. See `.github/workflows/test-riscof.yml` for GitHub actions workflow description.\n" }, { "path": "tools/riscof/config.ini", "content": "[RISCOF]\nReferencePlugin=spike\nReferencePluginPath=spike\nDUTPlugin=veer\nDUTPluginPath=veer\n\n[veer]\npluginpath=veer\nispec=veer/veer_isa.yaml\npspec=veer/veer_platform.yaml\nsim_binary=obj_dir/Vtb_top\ntarget_run=1\njobs=4\n\n[spike]\npluginpath=spike\nispec=spike/spike_isa.yaml\npspec=spike/spike_platform.yaml\ntarget_run=1\njobs=4\n" }, { "path": "tools/riscof/spike/env/link.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(rvtest_entry_point)\n\nSECTIONS\n{\n . = 0x80000000;\n .text.init : { *(.text.init) }\n . = ALIGN(0x1000);\n .tohost : { *(.tohost) }\n . = ALIGN(0x1000);\n .text : { *(.text) }\n . = ALIGN(0x1000);\n .data : { *(.data) }\n .data.string : { *(.data.string)}\n .bss : { *(.bss) }\n _end = .;\n}\n\n" }, { "path": "tools/riscof/spike/env/model_test.h", "content": "#ifndef _COMPLIANCE_MODEL_H\r\n#define _COMPLIANCE_MODEL_H\r\n#define RVMODEL_DATA_SECTION \\\r\n .pushsection .tohost,\"aw\",@progbits; \\\r\n .align 8; .global tohost; tohost: .dword 0; \\\r\n .align 8; .global fromhost; fromhost: .dword 0; \\\r\n .popsection; \\\r\n .align 8; .global begin_regstate; begin_regstate: \\\r\n .word 128; \\\r\n .align 8; .global end_regstate; end_regstate: \\\r\n .word 4;\r\n\r\n//RV_COMPLIANCE_HALT\r\n#define RVMODEL_HALT \\\r\n li x1, 1; \\\r\n write_tohost: \\\r\n sw x1, tohost, t5; \\\r\n j write_tohost;\r\n\r\n#define MTIMECMP_BASE 0x2004000\r\n\r\n#define RVMODEL_BOOT \\\r\n /* Set MTIMECMP to UINT64_MAX so that there isn't a timer interrupt pending in MIP */ \\\r\n li t0, -1; \\\r\n la t1, MTIMECMP_BASE; \\\r\n sw t0, (t1); \\\r\n sw t0, 4(t1);\r\n\r\n//RV_COMPLIANCE_DATA_BEGIN\r\n#define RVMODEL_DATA_BEGIN \\\r\n RVMODEL_DATA_SECTION \\\r\n .align 4;\\\r\n .global begin_signature; begin_signature:\r\n\r\n//RV_COMPLIANCE_DATA_END\r\n#define RVMODEL_DATA_END \\\r\n .align 4;\\\r\n .global end_signature; end_signature: \r\n\r\n//RVTEST_IO_INIT\r\n#define RVMODEL_IO_INIT\r\n//RVTEST_IO_WRITE_STR\r\n#define RVMODEL_IO_WRITE_STR(_R, _STR)\r\n//RVTEST_IO_CHECK\r\n#define RVMODEL_IO_CHECK()\r\n//RVTEST_IO_ASSERT_GPR_EQ\r\n#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)\r\n//RVTEST_IO_ASSERT_SFPR_EQ\r\n#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)\r\n//RVTEST_IO_ASSERT_DFPR_EQ\r\n#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)\r\n\r\n#define RVMODEL_SET_MSW_INT \\\r\n li t1, 1; \\\r\n li t2, 0x2000000; \\\r\n sw t1, 0(t2);\r\n\r\n#define RVMODEL_CLEAR_MSW_INT \\\r\n li t2, 0x2000000; \\\r\n sw x0, 0(t2);\r\n\r\n#define RVMODEL_CLEAR_MTIMER_INT\r\n\r\n#define RVMODEL_CLEAR_MEXT_INT\r\n\r\n\r\n#endif // _COMPLIANCE_MODEL_H\r\n" }, { "path": "tools/riscof/spike/riscof_spike.py", "content": "import os\nimport re\nimport shutil\nimport subprocess\nimport shlex\nimport logging\nimport random\nimport string\nfrom string import Template\nimport sys\n\nimport riscof.utils as utils\nimport riscof.constants as constants\nfrom riscof.pluginTemplate import pluginTemplate\n\nlogger = logging.getLogger()\n\nclass spike(pluginTemplate):\n __model__ = \"spike\"\n __version__ = \"1.0\"\n\n def __init__(self, *args, **kwargs):\n super().__init__(*args, **kwargs)\n\n config = kwargs.get('config')\n\n # If the config node for this DUT is missing or empty. Raise an error. At minimum we need\n # the paths to the ispec and pspec files\n if config is None:\n print(\"Please enter input file paths in configuration.\")\n raise SystemExit(1)\n\n # In case of an RTL based DUT, this would be point to the final binary executable of your\n # test-bench produced by a simulator (like verilator, vcs, incisive, etc). In case of an iss or\n # emulator, this variable could point to where the iss binary is located. If 'PATH variable\n # is missing in the config.ini we can hardcode the alternate here.\n self.dut_exe = os.path.join(config['PATH'] if 'PATH' in config else \"\",\"spike\")\n\n # Number of parallel jobs that can be spawned off by RISCOF\n # for various actions performed in later functions, specifically to run the tests in\n # parallel on the DUT executable. Can also be used in the build function if required.\n self.num_jobs = str(config['jobs'] if 'jobs' in config else 1)\n\n # Path to the directory where this python file is located. Collect it from the config.ini\n self.pluginpath=os.path.abspath(config['pluginpath'])\n\n # Collect the paths to the riscv-config absed ISA and platform yaml files. One can choose\n # to hardcode these here itself instead of picking it from the config.ini file.\n self.isa_spec = os.path.abspath(config['ispec'])\n self.platform_spec = os.path.abspath(config['pspec'])\n\n #We capture if the user would like the run the tests on the target or\n #not. If you are interested in just compiling the tests and not running\n #them on the target, then following variable should be set to False\n if 'target_run' in config and config['target_run']=='0':\n self.target_run = False\n else:\n self.target_run = True\n\n def initialise(self, suite, work_dir, archtest_env):\n\n # capture the working directory. Any artifacts that the DUT creates should be placed in this\n # directory. Other artifacts from the framework and the Reference plugin will also be placed\n # here itself.\n self.work_dir = work_dir\n\n # capture the architectural test-suite directory.\n self.suite_dir = suite\n\n # Note the march is not hardwired here, because it will change for each\n # test. Similarly the output elf name and compile macros will be assigned later in the\n # runTests function\n self.compile_cmd = 'riscv64-unknown-elf-gcc -march={0} \\\n -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g\\\n -T '+self.pluginpath+'/env/link.ld\\\n -I '+self.pluginpath+'/env/\\\n -I ' + archtest_env + ' {2} -o {3} {4}'\n\n # add more utility snippets here\n\n def build(self, isa_yaml, platform_yaml):\n\n # load the isa yaml as a dictionary in python.\n ispec = utils.load_yaml(isa_yaml)['hart0']\n\n # capture the XLEN value by picking the max value in 'supported_xlen' field of isa yaml. This\n # will be useful in setting integer value in the compiler string (if not already hardcoded);\n self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')\n\n # for spike start building the '--isa' argument. the self.isa is dutnmae specific and may not be\n # useful for all DUTs\n self.isa = 'rv' + self.xlen\n if \"I\" in ispec[\"ISA\"]:\n self.isa += 'i'\n if \"M\" in ispec[\"ISA\"]:\n self.isa += 'm'\n if \"F\" in ispec[\"ISA\"]:\n self.isa += 'f'\n if \"D\" in ispec[\"ISA\"]:\n self.isa += 'd'\n if \"C\" in ispec[\"ISA\"]:\n self.isa += 'c'\n\n #TODO: The following assumes you are using the riscv-gcc toolchain. If\n # not please change appropriately\n self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')\n\n def runTests(self, testList):\n\n # Delete Makefile if it already exists.\n makefile = self.work_dir + \"/Makefile.\" + self.name[:-1]\n if os.path.exists(makefile):\n os.remove(makefile)\n\n # create an instance the makeUtil class that we will use to create targets.\n make = utils.makeUtil(makefilePath=makefile)\n\n # set the make command that will be used. The num_jobs parameter was set in the __init__\n # function earlier\n make.makeCommand = 'make -k -j' + self.num_jobs\n\n # we will iterate over each entry in the testList. Each entry node will be refered to by the\n # variable testname.\n for testname in testList:\n\n # for each testname we get all its fields (as described by the testList format)\n testentry = testList[testname]\n\n # we capture the path to the assembly file of this test\n test = testentry['test_path']\n\n # capture the directory where the artifacts of this test will be dumped/created. RISCOF is\n # going to look into this directory for the signature files\n test_dir = testentry['work_dir']\n\n # name of the elf file after compilation of the test\n elf = 'my.elf'\n\n # name of the signature file as per requirement of RISCOF. RISCOF expects the signature to\n # be named as DUT-.signature. The below variable creates an absolute path of\n # signature file.\n sig_file = os.path.join(test_dir, self.name[:-1] + \".signature\")\n\n # Save Spike's execution log\n exec_log_file = os.path.join(test_dir, \"exec.log\")\n\n # for each test there are specific compile macros that need to be enabled. The macros in\n # the testList node only contain the macros/values. For the gcc toolchain we need to\n # prefix with \"-D\". The following does precisely that.\n compile_macros= ' -D' + \" -D\".join(testentry['macros'])\n\n # substitute all variables in the compile command that we created in the initialize\n # function\n isa = testentry['isa'].lower()\n\n # Force the zicsr extension to -march.\n # Some tests seem to depend on it in order to compile at all, despite it not being in testentry?\n if \"zicsr\" not in isa:\n isa += \"_zicsr\"\n\n cmd = self.compile_cmd.format(isa, self.xlen, test, elf, compile_macros)\n\n\t # if the user wants to disable running the tests and only compile the tests, then\n\t # the \"else\" clause is executed below assigning the sim command to simple no action\n\t # echo statement.\n if self.target_run:\n # set up the simulation command. Template is for spike. Please change.\n simcmd = self.dut_exe + ' -l --log={3} --misaligned --isa={0} +signature={1} +signature-granularity=4 {2}'.format(self.isa, sig_file, elf, exec_log_file)\n else:\n simcmd = 'echo \"NO RUN\"'\n\n # concatenate all commands that need to be executed within a make-target.\n execute = '@cd {0}&& {1}&& {2}'.format(testentry['work_dir'], cmd, simcmd)\n\n # create a target. The makeutil will create a target with the name \"TARGET\" where num\n # starts from 0 and increments automatically for each new target that is added\n make.add_target(execute)\n\n # once the make-targets are done and the makefile has been created, run all the targets in\n # parallel using the make command set above.\n make.execute_all(self.work_dir, timeout=7200)\n\n # if target runs are not required then we simply exit as this point after running all\n # the makefile targets.\n if not self.target_run:\n raise SystemExit(0)\n" }, { "path": "tools/riscof/spike/spike_isa.yaml", "content": "hart_ids: [0]\nhart0:\n ISA: RV32IMCZicsr_Zifencei\n physical_addr_sz: 32\n User_Spec_Version: '2.3'\n supported_xlen: [32]\n hw_data_misaligned_support: true\n misa:\n reset-val: 0x40001104\n rv32:\n accessible: true\n mxl:\n implemented: true\n type:\n warl:\n dependency_fields: []\n legal:\n - mxl[1:0] in [0x1]\n wr_illegal:\n - Unchanged\n extensions:\n implemented: true\n type:\n warl:\n dependency_fields: []\n legal:\n - extensions[25:0] bitmask [0x0001104, 0x0000000]\n wr_illegal:\n - Unchanged\n \n" }, { "path": "tools/riscof/spike/spike_platform.yaml", "content": "mtime:\n implemented: true\n address: 0xbff8\nmtimecmp:\n implemented: true\n address: 0x4000\nnmi:\n label: nmi_vector\nreset:\n label: reset_vector\n" }, { "path": "tools/riscof/veer/env/link.ld", "content": "OUTPUT_ARCH( \"riscv\" )\nENTRY(rvtest_entry_point)\n\nSECTIONS\n{\n . = 0x80000000;\n .text.init : { *(.text.init) }\n . = ALIGN(0x1000);\n .text : { *(.text) }\n . = ALIGN(0x1000);\n .data : { *(.data) }\n .data.string : { *(.data.string)}\n .bss : { *(.bss) }\n _end = .;\n . = 0xd0580000;\n .tohost : { *(.tohost) }\n}\n\n" }, { "path": "tools/riscof/veer/env/model_test.h", "content": "#ifndef _COMPLIANCE_MODEL_H\r\n#define _COMPLIANCE_MODEL_H\r\n#define RVMODEL_DATA_SECTION \\\r\n .pushsection .tohost,\"aw\",@progbits; \\\r\n .align 8; .global tohost; tohost: .dword 0; \\\r\n .align 8; .global fromhost; fromhost: .dword 0; \\\r\n .popsection; \\\r\n .align 8; .global begin_regstate; begin_regstate: \\\r\n .word 128; \\\r\n .align 8; .global end_regstate; end_regstate: \\\r\n .word 4;\r\n\r\n//RV_COMPLIANCE_HALT\r\n#define RVMODEL_HALT \\\r\n li x1, 0xFF; \\\r\n write_tohost: \\\r\n sw x1, tohost, t5; \\\r\n j write_tohost;\r\n\r\n#define RVMODEL_BOOT \\\r\n /* Length of RVMODEL_BOOT must be the same in both VeeR and Spike, to align PC */ \\\r\n .rept 4; \\\r\n nop; \\\r\n .endr;\r\n\r\n//RV_COMPLIANCE_DATA_BEGIN\r\n#define RVMODEL_DATA_BEGIN \\\r\n RVMODEL_DATA_SECTION \\\r\n .align 4;\\\r\n .global begin_signature; begin_signature:\r\n\r\n//RV_COMPLIANCE_DATA_END\r\n#define RVMODEL_DATA_END \\\r\n .align 4;\\\r\n .global end_signature; end_signature: \r\n\r\n//RVTEST_IO_INIT\r\n#define RVMODEL_IO_INIT\r\n//RVTEST_IO_WRITE_STR\r\n#define RVMODEL_IO_WRITE_STR(_R, _STR)\r\n//RVTEST_IO_CHECK\r\n#define RVMODEL_IO_CHECK()\r\n//RVTEST_IO_ASSERT_GPR_EQ\r\n#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)\r\n//RVTEST_IO_ASSERT_SFPR_EQ\r\n#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)\r\n//RVTEST_IO_ASSERT_DFPR_EQ\r\n#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)\r\n\r\n#define RVMODEL_SET_MSW_INT \\\r\n li t1, 1; \\\r\n li t2, 0x2000000; \\\r\n sw t1, 0(t2);\r\n\r\n#define RVMODEL_CLEAR_MSW_INT \\\r\n li t2, 0x2000000; \\\r\n sw x0, 0(t2);\r\n\r\n#define RVMODEL_CLEAR_MTIMER_INT\r\n\r\n#define RVMODEL_CLEAR_MEXT_INT\r\n\r\n\r\n#endif // _COMPLIANCE_MODEL_H\r\n" }, { "path": "tools/riscof/veer/riscof_veer.py", "content": "import os\nimport re\nimport shutil\nimport subprocess\nimport shlex\nimport logging\nimport random\nimport string\nfrom string import Template\nimport sys\n\nimport riscof.utils as utils\nimport riscof.constants as constants\nfrom riscof.pluginTemplate import pluginTemplate\n\nlogger = logging.getLogger()\n\nclass veer(pluginTemplate):\n __model__ = \"VeeR\"\n __version__ = \"1.0\"\n\n def __init__(self, *args, **kwargs):\n super().__init__(*args, **kwargs)\n\n config = kwargs.get('config')\n\n # If the config node for this DUT is missing or empty. Raise an error. At minimum we need\n # the paths to the ispec and pspec files\n if config is None:\n print(\"Please enter input file paths in configuration.\")\n raise SystemExit(1)\n\n # Number of parallel jobs that can be spawned off by RISCOF\n # for various actions performed in later functions, specifically to run the tests in\n # parallel on the DUT executable. Can also be used in the build function if required.\n self.num_jobs = str(config['jobs'] if 'jobs' in config else 1)\n\n # Path to the directory where this python file is located. Collect it from the config.ini\n self.pluginpath = os.path.abspath(config['pluginpath'])\n\n # Collect the paths to the riscv-config absed ISA and platform yaml files. One can choose\n # to hardcode these here itself instead of picking it from the config.ini file.\n self.isa_spec = os.path.abspath(config['ispec'])\n self.platform_spec = os.path.abspath(config['pspec'])\n\n # We capture if the user would like the run the tests on the target or\n # not. If you are interested in just compiling the tests and not running\n # them on the target, then following variable should be set to False\n if 'target_run' in config and config['target_run']=='0':\n self.target_run = False\n else:\n self.target_run = True\n\n # Verilated simulation binary path\n self.sim_binary = os.path.abspath(config['sim_binary'])\n\n def initialise(self, suite, work_dir, archtest_env):\n\n # capture the working directory. Any artifacts that the DUT creates should be placed in this\n # directory. Other artifacts from the framework and the Reference plugin will also be placed\n # here itself.\n self.work_dir = work_dir\n\n # capture the architectural test-suite directory.\n self.suite_dir = suite\n\n # Note the march is not hardwired here, because it will change for each\n # test. Similarly the output elf name and compile macros will be assigned later in the\n # runTests function\n self.compile_cmd = 'riscv64-unknown-elf-gcc -march={0} \\\n -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g\\\n -T '+self.pluginpath+'/env/link.ld\\\n -I '+self.pluginpath+'/env/\\\n -I ' + archtest_env + ' {2} -o {3} {4}'\n\n # Conversion command. Make a HEX file from the ELF for the verilated\n # simulation\n self.convert_cmd = 'riscv64-unknown-elf-objcopy -O verilog {3} program.hex'\n\n # Symbol address extraction command\n self.symbols_cmd = 'riscv64-unknown-elf-nm -B -n {3} > program.sym'\n\n def build(self, isa_yaml, platform_yaml):\n\n # load the isa yaml as a dictionary in python.\n ispec = utils.load_yaml(isa_yaml)['hart0']\n\n # capture the XLEN value by picking the max value in 'supported_xlen' field of isa yaml. This\n # will be useful in setting integer value in the compiler string (if not already hardcoded);\n self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')\n\n # for veer start building the '--isa' argument. the self.isa is dutnmae specific and may not be\n # useful for all DUTs\n self.isa = 'rv' + self.xlen\n if \"I\" in ispec[\"ISA\"]:\n self.isa += 'i'\n if \"M\" in ispec[\"ISA\"]:\n self.isa += 'm'\n if \"F\" in ispec[\"ISA\"]:\n self.isa += 'f'\n if \"D\" in ispec[\"ISA\"]:\n self.isa += 'd'\n if \"C\" in ispec[\"ISA\"]:\n self.isa += 'c'\n\n self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')\n\n def runTests(self, testList):\n\n # Delete Makefile if it already exists.\n makefile = self.work_dir + \"/Makefile.\" + self.name[:-1]\n if os.path.exists(makefile):\n os.remove(makefile)\n\n # create an instance the makeUtil class that we will use to create targets.\n make = utils.makeUtil(makefilePath=makefile)\n\n # set the make command that will be used. The num_jobs parameter was set in the __init__\n # function earlier\n make.makeCommand = 'make -k -j' + self.num_jobs\n\n # we will iterate over each entry in the testList. Each entry node will be refered to by the\n # variable testname.\n for testname in testList:\n\n # for each testname we get all its fields (as described by the testList format)\n testentry = testList[testname]\n\n # we capture the path to the assembly file of this test\n test = testentry['test_path']\n\n # capture the directory where the artifacts of this test will be dumped/created. RISCOF is\n # going to look into this directory for the signature files\n test_dir = testentry['work_dir']\n\n # name of the elf file after compilation of the test\n elf = 'my.elf'\n\n # name of the signature file as per requirement of RISCOF. RISCOF expects the signature to\n # be named as DUT-.signature. The below variable creates an absolute path of\n # signature file.\n sig_file = os.path.join(test_dir, self.name[:-1] + \".signature\")\n\n # for each test there are specific compile macros that need to be enabled. The macros in\n # the testList node only contain the macros/values. For the gcc toolchain we need to\n # prefix with \"-D\". The following does precisely that.\n compile_macros= ' -D' + \" -D\".join(testentry['macros'])\n\n # substitute all variables in the commands that we created in the initialize\n # function\n isa = testentry['isa'].lower()\n\n # Force the zicsr extension to -march.\n # Some tests seem to depend on it in order to compile at all, despite it not being in testentry?\n if \"zicsr\" not in isa:\n isa += \"_zicsr\"\n\n cmds = [\n self.compile_cmd.format(isa, self.xlen, test, elf, compile_macros),\n self.convert_cmd.format(isa, self.xlen, test, elf),\n self.symbols_cmd.format(isa, self.xlen, test, elf),\n ]\n\n\t # if the user wants to disable running the tests and only compile the tests, then\n\t # the \"else\" clause is executed below assigning the sim command to simple no action\n\t # echo statement.\n if self.target_run:\n simcmd = [\n self.sim_binary + \" --symbols program.sym\",\n 'mv veer.signature DUT-{}.signature'.format(veer.__model__),\n ]\n else:\n simcmd = [\n 'echo \"NO RUN\"',\n ]\n\n # concatenate all commands that need to be executed within a make-target.\n execute = 'cd ' + testentry['work_dir'] + '&& '\n execute += '&& '.join(cmds + simcmd)\n\n # create a target. The makeutil will create a target with the name \"TARGET\" where num\n # starts from 0 and increments automatically for each new target that is added\n make.add_target(execute)\n\n # once the make-targets are done and the makefile has been created, run all the targets in\n # parallel using the make command set above.\n make.execute_all(self.work_dir, timeout=7200)\n\n # if target runs are not required then we simply exit as this point after running all\n # the makefile targets.\n if not self.target_run:\n raise SystemExit(0)\n" }, { "path": "tools/riscof/veer/veer_isa.yaml", "content": "hart_ids: [0]\nhart0:\n ISA: RV32IMCZicsr\n physical_addr_sz: 32\n User_Spec_Version: '2.3'\n supported_xlen: [32]\n hw_data_misaligned_support: true\n misa:\n reset-val: 0x40001104\n rv32:\n accessible: true\n mxl:\n implemented: true\n type:\n warl:\n dependency_fields: []\n legal:\n - mxl[1:0] in [0x1]\n wr_illegal:\n - Unchanged\n extensions:\n implemented: true\n type:\n warl:\n dependency_fields: []\n legal:\n - extensions[25:0] bitmask [0x0001104, 0x0000000]\n wr_illegal:\n - Unchanged\n \n" }, { "path": "tools/riscof/veer/veer_platform.yaml", "content": "mtime:\n implemented: true\n address: 0xbff8\nmtimecmp:\n implemented: true\n address: 0x4000\nnmi:\n label: nmi_vector\nreset:\n label: reset_vector\n" }, { "path": "tools/riscv-dv/Makefile", "content": "SHELL = /bin/bash -o pipefail\n\nGCC_PREFIX ?= riscv64-unknown-elf\n\nRISCV_DV_PATH = $(RV_ROOT)/third_party/riscv-dv\nRISCV_DV_SIM ?= pyflow\nRISCV_DV_ISS ?= spike\nRISCV_DV_TEST ?= riscv_arithmetic_basic_test\nRISCV_DV_SEED ?= 999\nRISCV_DV_ITER ?= 1\nRISCV_DV_BATCH ?= 1\nRISCV_DV_PRIV ?= m\n\nexport RISCV_GCC ?= $(GCC_PREFIX)-gcc\nexport RISCV_OBJCOPY ?= $(GCC_PREFIX)-objcopy\nexport RISCV_NM ?= $(GCC_PREFIX)-nm\n\nWORK_DIR ?= work\nTEST_DIR = $(WORK_DIR)/test_$(RISCV_DV_TEST)\nSIM_DIR = $(TEST_DIR)/hdl_sim\n\nifeq ($(findstring u, $(RISCV_DV_PRIV)), u)\n\tVEER_EXTRA_CONF = \"-set=user_mode=1 -set=smepmp=1\"\nelse\n\tVEER_EXTRA_CONF = \"\"\nendif\n\nVEER_TARGET = default\nVEER_CONF = -set build_axi4 \\\n -set reset_vec=0x80000000 \\\n -set fpga_optimize=0 \\\n $(VEER_EXTRA_CONF)\n\n# Coverage reporting\nifeq (\"$(COVERAGE)\", \"all\")\n VERILATOR_COVERAGE = --coverage\nelse ifeq (\"$(COVERAGE)\", \"branch\")\n VERILATOR_COVERAGE = --coverage-line\nelse ifeq (\"$(COVERAGE)\", \"toggle\")\n VERILATOR_COVERAGE = --coverage-toggle\nelse ifeq (\"$(COVERAGE)\", \"functional\")\n VERILATOR_COVERAGE = --coverage-user\nelse ifneq (\"$(COVERAGE)\", \"\")\n $(error Unknown COVERAGE value '$(COVERAGE)')\nendif\n\nVERILATOR = verilator\nVERILATOR_CFLAGS= \"-std=c++14\"\nVERILATOR_INC = -I$(WORK_DIR) -I$(RV_ROOT)/testbench\nVERILATOR_EXE = $(RV_ROOT)/testbench/test_tb_top.cpp\n# Set `TB_SILENT_FAIL` as generated instruction sequences may cause TB errors\n# Errors are to be reported when execution flows discrepancy is encountered\nVERILATOR_EXTRA_DEFS = +define+TB_SILENT_FAIL\n\nHDL_FILES = $(WORK_DIR)/common_defines.vh \\\n $(WORK_DIR)/el2_pdef.vh \\\n $(RV_ROOT)/testbench/tb_top_pkg.sv \\\n $(RV_ROOT)/testbench/tb_top.sv \\\n $(RV_ROOT)/testbench/ahb_sif.sv \\\n $(RV_ROOT)/design/include/el2_def.sv\n\n# Determine verilator version if possible. Set the flag accordingly. Since\n# version v5.006 -Wno-IMPLICIT was renamed to -Wno-IMPLICITSTATIC\nVERILATOR_NOIMPLICIT := -Wno-IMPLICITSTATIC\nVERILATOR_VERSION := $(subst .,,$(word 2,$(shell $(VERILATOR) --version)))\n\nifeq (\"$(.SHELLSTATUS)\", \"0\")\n $(shell test $(VERILATOR_VERSION) -lt 5006)\n ifeq (\"$(.SHELLSTATUS)\", \"0\")\n VERILATOR_NOIMPLICIT := -Wno-IMPLICIT\n endif\nendif\n\nISA_STRING = rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs\n# If compiled with U-mode we implicitly also compile with Smepmp in these tests\nifeq ($(findstring u, $(RISCV_DV_PRIV)), u)\n\tISA_STRING := \"${ISA_STRING}\"_smepmp\nendif\n\nRISCV_DV_SIM_ARGS= \\\n --priv ${RISCV_DV_PRIV}\n\n# Append Renode-specific options\nifeq (\"$(RISCV_DV_ISS)\", \"renode\")\n ISS_OPTS += --cpu-type='VeeR_EL2'\n ISS_OPTS += --additional-cpu-parameters=''\n RISCV_DV_SIM_ARGS += \\\n --iss_opts=\" ${ISS_OPTS} \"\nendif\n\n# riscv-dv args\nRISCV_DV_ARGS = \\\n --simulator $(RISCV_DV_SIM) \\\n --test $(RISCV_DV_TEST) \\\n --iss $(RISCV_DV_ISS) \\\n --iss_timeout 120 \\\n --start_seed $(RISCV_DV_SEED) \\\n --iterations $(RISCV_DV_ITER) \\\n --batch_size $(RISCV_DV_BATCH) \\\n --isa ${ISA_STRING} \\\n --mabi ilp32 \\\n --custom_target $(PWD) \\\n --testlist $(PWD)/testlist.yaml \\\n -v -o $(TEST_DIR)\n\nMAKEFILE = $(abspath $(MAKEFILE_LIST))\n\nall:\n\t@echo \"Use 'make run'\"\n\n# Directory rules\n$(WORK_DIR):\n\tmkdir -p $@\n\n$(TEST_DIR):\n\tmkdir -p $@\n\n# VeeR config\n$(WORK_DIR)/defines.h: | $(WORK_DIR)\n\tBUILD_PATH=$(WORK_DIR) $(RV_ROOT)/configs/veer.config -target=$(VEER_TARGET) $(VEER_CONF)\n\techo '`undef RV_ASSERT_ON' >> $(WORK_DIR)/common_defines.vh\n\n# Verilated testbench rules\n$(WORK_DIR)/verilator/Vtb_top.mk: $(WORK_DIR)/defines.h\n\t$(VERILATOR) --cc -CFLAGS $(VERILATOR_CFLAGS) $(VERILATOR_INC) $(VERILATOR_EXTRA_DEFS)\\\n $(HDL_FILES) -f $(RV_ROOT)/testbench/flist --top-module tb_top \\\n\t\t-exe $(VERILATOR_EXE) -Wno-WIDTH -Wno-UNOPTFLAT $(VERILATOR_NOIMPLICIT) --autoflush \\\n\t\t--timing $(VERILATOR_COVERAGE) -fno-table -Wno-LATCH\\\n\t\t-Mdir $(WORK_DIR)/verilator\n\n$(WORK_DIR)/verilator/Vtb_top: $(WORK_DIR)/verilator/Vtb_top.mk\n\t$(MAKE) -C $(WORK_DIR)/verilator -f Vtb_top.mk OPT_FAST=\"-O3\"\n\n# Code generation\n$(TEST_DIR)/generate.log: | $(TEST_DIR)\n\tPYTHONPATH=$(RISCV_DV_PATH)/pygen python3 $(RISCV_DV_PATH)/run.py $(RISCV_DV_ARGS) \\\n --steps gen\n\t@touch $@\n\n# Code patching & compilation\n# remove _smepmp from ISA string, as it's not recognized by GCC\n$(TEST_DIR)/compile.log: $(TEST_DIR)\n\t# Patch the code\n\tfind $(TEST_DIR)/asm_test -name \"*.S\" -exec python3 code_fixup.py -i {} -o {} \\;\n\t# Compile, simulate\n\tPYTHONPATH=$(RISCV_DV_PATH)/pygen python3 $(RISCV_DV_PATH)/run.py $(subst _smepmp,,$(RISCV_DV_ARGS)) \\\n --steps gcc_compile 2>&1 | tee $@\n\n# ISS simulation\n$(TEST_DIR)/iss_sim.log: $(TEST_DIR)/compile.log | $(TEST_DIR)\n\t# Compile, simulate\n\tPYTHONPATH=$(RISCV_DV_PATH)/pygen python3 $(RISCV_DV_PATH)/run.py $(RISCV_DV_ARGS) $(RISCV_DV_SIM_ARGS) \\\n --steps iss_sim 2>&1 | tee $@\n\tif grep -q ERROR $(TEST_DIR)/iss_sim.log; then \\\n\t\techo \"ISS simulation failed\"; \\\n\t\texit 1; \\\n\tfi\n\n# Tests are built by `run.py` script, they shouldn't be constructed by this Makefile directly\n%.o:\n\t$(warning There are additional test files ($@), which will not be compiled. Hint: you might need to set \"RISCV_DV_ITER\" to a higher value)\n\n# Generate symbols of executables\n%.sym: %.o\n\t$(RISCV_NM) -B -n $< > $@\n\n# Convert executables\n%.hex: %.o\n\t$(RISCV_OBJCOPY) -O verilog $< $@\n\n# HDL simulation\n$(SIM_DIR)/%.log: $(TEST_DIR)/asm_test/%.hex $(TEST_DIR)/asm_test/%.sym $(WORK_DIR)/verilator/Vtb_top\n\tmkdir -p $(basename $@)\n\tcp $< $(basename $@)/program.hex\n\tcp $(basename $<).sym $(basename $@)/program.sym\n\tcd $(basename $@) && $(abspath $(WORK_DIR)/verilator/Vtb_top) --symbols program.sym --mailbox-sym tohost\n\tmv $(basename $@)/exec.log $@\n\n# Log conversion rules\n$(TEST_DIR)/spike_sim/%.csv: $(TEST_DIR)/spike_sim/%.log\n\tpython3 $(RISCV_DV_PATH)/scripts/spike_log_to_trace_csv.py --log $< --csv $@\n\n$(TEST_DIR)/renode_sim/%.csv: $(TEST_DIR)/renode_sim/%.log\n\tpython3 $(RISCV_DV_PATH)/scripts/renode_log_to_trace_csv.py --log $< --csv $@\n\n$(SIM_DIR)/%.csv: $(SIM_DIR)/%.log veer_log_to_trace_csv.py\n\tPYTHONPATH=$(RISCV_DV_PATH)/scripts python3 veer_log_to_trace_csv.py --log $< --csv $@\n\n# Trace comparison\n$(TEST_DIR)/comp_%.log: $(TEST_DIR)/$(RISCV_DV_ISS)_sim/%.csv $(SIM_DIR)/%.csv\n\trm -rf $@\n\tpython3 $(RISCV_DV_PATH)/scripts/instr_trace_compare.py \\\n\t\t--csv_file_1 $(word 1, $^) --csv_name_1 ISS --csv_file_2 $(word 2, $^) --csv_name_2 HDL \\\n\t\t--in_order_mode 1 --log $@ --verbose 10 --mismatch_print_limit 20\n\tcat $@\n\n%.sv: %.py\n\t./$< $(RISCV_DV_PATH) $(RV_ROOT) > $@\n\ngenerate:\n\t# Generate *.sv configuration\n\t#$(MAKE) -f $(MAKEFILE) riscv_core_setting.sv\n\t\n\t# Run RISC-V DV code generation\n\t$(MAKE) -f $(MAKEFILE) $(TEST_DIR)/generate.log\n\ncompile: $(TEST_DIR)/compile.log | $(TEST_DIR)\n\tfind $(TEST_DIR)/asm_test -name \"*.S\" | sed 's|\\.S|.hex|g' | xargs $(MAKE) -f $(MAKEFILE)\n\nrun:\n\t# Run RISC-V DV compilation and simulation\n\t$(MAKE) -f $(MAKEFILE) $(TEST_DIR)/iss_sim.log\n\t# Run HDL simulation(s) and trace comparison\n\tfind $(TEST_DIR)/$(RISCV_DV_ISS)_sim -name \"*.log\" | sed 's|sim/|sim/../comp_|g' | xargs realpath --relative-to=$(PWD) | xargs $(MAKE) -f $(MAKEFILE)\n\t# Check for errors\n\tfor F in $(TEST_DIR)/comp_*.log; do grep \"\\[PASSED\\]\" $$F; if [ $$? -ne 0 ]; then exit 255; fi; done\n\nclean:\n\trm -rf $(TEST_DIR)\n\nfullclean:\n\trm -rf $(WORK_DIR)\n\n.PHONY: all generate run clean fullclean\n.SECONDARY:\n# Disable any default actions Makefile might invoke for suffix rules (e.g. invoking CC for our tests)\n.SUFFIXES:\n" }, { "path": "tools/riscv-dv/README.md", "content": "# RISCV-DV for VeeR-EL2 Core\n\nThis folder contains utilities necessary for running [RISCV-DV](https://htmlpreview.github.io/?https://github.com/google/riscv-dv/blob/master/docs/build/singlehtml/index.html#) tests with VeeR-EL2 Core as well as the master Makefile which facilitates the process.\n\nRISCV-DV is a framework for testing RISC-V cores by generating random instructions, executing them in a reference ISS (instruction set simulator) as well as on the tested core (RTL simulation) and comparing execution trace logs. The trace logs contain executed instructions and core state changes (register writes) after each one which allows to precisely track the core behavior.\n\n## Setup\n\n1. Clone VeeR-EL2 Core repository with submodules and set `RV_ROOT` to the repository path:\n\n```\ngit clone --recurse-submodules git@github.com:chipsalliance/Cores-VeeR-EL2.git\ncd Cores-Veer-EL2\nexport RV_ROOT=$(pwd)\n```\n\n2. Setup the RISCV-DV framework\n\nThe framework should be already cloned in `Cores-Veer-EL2/third_party/riscv-dv`. Install its dependencies, best using a Python virtual environment:\n\n```\npython3 -m venv env\nsource env/bin/activate\npip install -r ${RV_ROOT}/third_party/riscv-dv/requirements.txt\n```\n\n3. Setup Verilator\n\nInstallation instructions are available in the [Verilator's User Guide](https://veripool.org/guide/latest/install.html). Make sure that the verilator executable is available (eg. by setting `PATH`).\n\n4. Setup instruction set simulator (ISS)\n\nRISCV-DV tests require a reference RISC-V program executor in a form of instruction set simulator. The RISCV-DV flow for VeeR-EL2 Core supports three of them:\n\n - Spike\n \n Follow the instruction from the [documentation](https://github.com/riscv-software-src/riscv-isa-sim#build-steps). After installation make sure that the spike binary is visible in the current path.\n \n - Renode\n \n [Renode](www.renode.io) is a full-fledged embedded system simulator developed at Antmicro. Its capabilities go beyond simulating a RISC-V core. In configuration for RISCV-DV only basic features are used just to be able to produce execution trace log.\n \n Renode can be downloaded as a pre-built binary. Download the latest \"linux-portable\" release from https://github.com/renode/renode/releases and unpack it. For example:\n ```\n wget https://github.com/renode/renode/releases/download/v1.13.3/renode-1.13.3.linux-portable.tar.gz\n tar -zxf renode-1.13.3.linux-portable.tar.gz\n export PATH=${PATH}:`realpath renode_1.13.3_portable`\n ```\n\n5. Setup RISC-V toolchain\n\nDownload and install RISC-V GCC toolchain capable for targeting RV32IMC architecture. Depending on your system this may be done either via the system package manager or manually by downloading binaries / building them.\n\nExport environmental variables required by RISCV-DV:\n```\nexport RISCV_TOOLCHAIN=\nexport RISCV_GCC=\"$RISCV_TOOLCHAIN/bin/riscv32-unknown-elf-gcc\"\nexport RISCV_OBJCOPY=\"$RISCV_TOOLCHAIN/bin/riscv32-unknown-elf-objcopy\"\nexport RISCV_NM=\"$RISCV_TOOLCHAIN/bin/riscv32-unknown-elf-nm\"\n```\n\n## Running tests\n\nTo run the tests using the default setup do the following:\n```\ncd ${RV_ROOT}/tools/riscv-dv\nmake run\n```\n\nTest execution environment is configurable by setting environment variables, which can be done either in the `Makefile` or in the CLI command,e.g;\n```\nRISCV_DV_ISS=whisper` make all\n```\n\nFull list of supported options is presented in the table below:\n\n| Variable | Default value | Allowed values | Description |\n| :---------------: | :----------------------------:| :-------------------------------: | :-------------------------------------------------------: |\n| `RISCV_DV_ISS` | `spike` | `spike`, `whisper`, `renode` | Controls which ISS is used as the reference. |\n| `RISCV_DV_TEST` | `riscv_arithmetic_basic_test` | | Test name. The complete list of tests can be found in [RISCV-DV documentation](https://github.com/chipsalliance/riscv-dv/tree/master/pygen/pygen_src) |\n| `RISCV_DV_ITER` | 1 | >= 1 | Test iteration count, default 1. |\n| `RISCV_DV_BATCH` | 1 | >= 1 | Test batch count, default 1. |\n| `RISCV_DV_SEED` | 999 | | Random generator seed for RISCV-DV instruction randomizer.|\n| `COVERAGE` | | `branch`, `toggle`, `functional` | Enables coverage data collection in Verilator. More information about coverage in Verilator can be found in its [documentation](https://veripool.org/guide/latest/simulating.html#coverage-analysis). |\n\n## CI\n\nRISCV-DV tests are run in GitHub actions CI. The workflow responsible for them can be found at `.github/workflows/test-riscv-dv.yml`\n" }, { "path": "tools/riscv-dv/code_fixup.py", "content": "#!/usr/bin/env python3\nimport argparse\nimport re\n\n# =============================================================================\n\nclass AssemblyLine:\n \"\"\"\n Simple assembly line representation\n \"\"\"\n\n RE_INSTR = re.compile(r\"(?P\\S+)\\s+(?P.*)\")\n\n def __init__(self, text):\n self.text = text\n self.mnemonic = None\n self.operands = None\n\n # Strip label if any\n if \":\" in text:\n text = text.split(\":\", maxsplit=1)[1]\n\n # Strip comment if any\n if \"#\" in text:\n text = text.split(\"#\", maxsplit=1)[0]\n\n # Get instruction and operands\n m = self.RE_INSTR.match(text.strip())\n if m is not None:\n\n if m.group(\"mnemonic\")[0] == \".\":\n return\n\n self.mnemonic = m.group(\"mnemonic\").lower()\n self.operands = [op.strip() for op in m.group(\"operands\").split(\",\")]\n\n def __str__(self):\n return self.text\n\n# =============================================================================\n\nMNEMONICS = {\"div\", \"divu\", \"rem\", \"remu\",\n \"lb\", \"lbu\", \"lh\", \"lhu\", \"lw\", \"c.lw\", \"c.lwsp\"}\n\ndef main():\n parser = argparse.ArgumentParser()\n parser.add_argument(\n \"-i\",\n type=str,\n required=True,\n help=\"Input assembly file\"\n )\n parser.add_argument(\n \"-o\",\n type=str,\n required=True,\n help=\"Output assembly file\"\n )\n\n args = parser.parse_args()\n\n max_nops = 10\n\n # Read and parse\n with open(args.i, \"r\") as fp:\n inp_lines = [AssemblyLine(l) for l in fp.readlines()]\n\n # Identify a delayed write instruction followed by another one which writes\n # to the same register\n out_lines = []\n for i in range(len(inp_lines)):\n line = inp_lines[i]\n out_lines.append(line)\n\n # Bypass\n if not line.mnemonic:\n continue\n\n # Check if it is a delayed write. If not then bypass\n is_delayed = line.mnemonic in MNEMONICS\n if not is_delayed:\n continue\n\n # Get next 2 instructions\n following = []\n for j in range(i+1, len(inp_lines)):\n if inp_lines[j].mnemonic is not None:\n following.append(inp_lines[j])\n if len(following) >= 2:\n break\n\n # If any of the instructions targets the same register insert NOPs\n dst = line.operands[0]\n for j, l in enumerate(following):\n if l.operands and l.operands[0] == dst:\n nops = max(0, max_nops - j)\n pad = \" \" * 18\n out_lines.append(pad + \"# FIXME: Inserting {} NOPs to prevent VeeR from cancelling a delayed write #\\n\".format(nops))\n for k in range(nops):\n out_lines.append(pad + \"nop\\n\")\n out_lines.append(pad + \"# end of nop insertion #\\n\")\n break\n\n # Write\n with open(args.o, \"w\") as fp:\n for l in out_lines:\n fp.write(str(l))\n\n\nif __name__ == \"__main__\":\n main()\n" }, { "path": "tools/riscv-dv/riscv_core_setting.py", "content": "#!/usr/bin/env python3\n\nimport argparse\nimport hashlib\nimport logging\nimport re\nfrom pathlib import Path\nfrom typing import Dict, List, Set\n\nlogger = logging.getLogger(__name__)\n\n\nRISCV_INSTR_PKG_REL_PATH = \"src/riscv_instr_pkg.sv\"\nRISCV_INSTR_PKG_SHA = \"90b58f1c998f1116fb4ff8c652a7e7fe4345867739ac4f6f852f452427b0ebed\"\n\nVEER_DECODE_REL_PATH = \"design/dec/decode\"\nVEER_DECODE_SHA = \"62dc85fad17b27d041678447c401bfee9725d6889a8d4cb68b9e38c34a6b8e79\"\n\nVEER_CSRDECODE_REL_PATH = \"design/dec/csrdecode\"\nVEER_CSRDECODE_SHA = \"f5ba0a4da487c6f760d20467b4647018eef196b2ad7956f7ee86cea29375796d\"\n\nVEER_EL2_DEC_TLU_CTRL_PATH = \"design/dec/el2_dec_tlu_ctl.sv\"\nVEER_EL2_DEC_TLU_CTRL_SHA = \"d472b88fd419f8ebd8e1db3ee701b464d02a3cffd8de01aeb702d600736ec547\"\n\n\ndef check_sha256(path: Path, exp_sha256: str):\n with open(path, \"rb\") as fd:\n sha256 = hashlib.sha256(fd.read())\n if sha256.hexdigest() != exp_sha256:\n logger.warning(\n f\"Script prepared for a different version of {path} file. ({sha256.hexdigest()} vs {exp_sha256})\"\n )\n logger.warning(\"Verify if the output is correct\")\n\n\ndef _parse_enum_with_one_hex(content: List[str], regexp: str, lower: int, upper: int) -> Dict[str, int]:\n result = {}\n for i, line in enumerate(content[lower:upper]):\n reg_data = re.findall(regexp, line)\n\n if len(reg_data) == 0:\n continue\n\n if len(reg_data) > 1:\n raise Exception(\"Found more matching values than expected\")\n\n (name, str_val) = reg_data[0]\n val = int(str_val, 16)\n result[val] = name\n\n return result\n\n\ndef _parse_enum_with_insn(content: List[str], lower: int, upper: int):\n insn_to_cat = {}\n category = \"\"\n for i, line in enumerate(content[lower:upper]):\n reg_insn = re.findall(r\"^\\s*(? 0 and len(reg_insn_comment) > 0)\n or (len(reg_insn) > 1)\n or (len(reg_insn_comment) > 1)\n ):\n raise Exception(\"Found different number of matchin values than expected\")\n\n if len(reg_insn_comment) == 1:\n category = reg_insn_comment[0]\n\n if len(reg_insn) == 1:\n insn_name = reg_insn[0]\n\n if category == \"\":\n raise Exception(\"Instruction category not found\")\n\n insn_to_cat[insn_name] = category\n\n return insn_to_cat\n\n\ndef parse_riscv_instr_pkg(riscv_instr_pkg_path: Path):\n \"\"\"Parses riscv_instr_pkg.sv and returns dictionaries with defined enums\"\"\"\n\n with open(riscv_instr_pkg_path) as fd:\n content = fd.readlines()\n\n csrs = _parse_enum_with_one_hex(content, r\"(\\S+)\\s*=\\s*'h([0-9a-zA-Z]+)\", 749, 1101)\n intr = _parse_enum_with_one_hex(content, r\"(\\S+)\\s*=\\s*4'h([0-9a-zA-Z]+)\", 1146, 1156)\n excp = _parse_enum_with_one_hex(content, r\"(\\S+)\\s*=\\s*4'h([0-9a-zA-Z]+)\", 1158, 1173)\n insn = _parse_enum_with_insn(content, 115, 649)\n\n return (csrs, intr, excp, insn)\n\n\ndef _parse_veer_decode(content: List[str], lower: int, upper: int, replace_dict: Dict[str, str] = {}):\n regexp = r\"^\\s*(? 1:\n raise Exception(\"Found more matching values than expected\")\n\n (name, str_val) = reg_data[0]\n veer_csrs[name] = str_val\n\n return veer_csrs\n\n\ndef parse_veer_csrdecode(csrdecode_path: Path):\n with open(csrdecode_path) as fd:\n content = fd.readlines()\n return _parse_veer_csrdecode(content, 4, 82)\n\n\ndef _parse_veer_irqs_and_excp(content: List[str], lower: int, upper: int):\n regexp = r\"\\{5\\{.*\\}\\}\\s*&\\s*5'h([a-zA-Z0-9]+)\"\n result = set()\n for i, line in enumerate(content[lower:upper]):\n reg_data = re.findall(regexp, line)\n if len(reg_data) == 0:\n continue\n\n if len(reg_data) > 1:\n raise Exception(\"Not expected\")\n\n str_val = reg_data[0]\n result.add(int(str_val, 16))\n\n return result\n\n\ndef parse_veer_dec_tlu_ctl(dec_tlu_ctl_path: Path):\n with open(dec_tlu_ctl_path) as fd:\n content = fd.readlines()\n\n irqs = _parse_veer_irqs_and_excp(content, 983, 988)\n excp = _parse_veer_irqs_and_excp(content, 989, 996)\n return (irqs, excp)\n\n\n# preparing data\n\n\ndef inv_dict(data: Dict) -> Dict:\n result = {}\n for k, v in data.items():\n result[v] = result.get(v, []) + [k]\n return result\n\n\ndef remove_suffix_number(string: str) -> str:\n return re.sub(r\"\\d+$\", \"\", string)\n\ndef count_nonempty(d: Dict) -> int:\n count = 0\n for k, v in d.items():\n if v:\n count += 1\n return count\n\nif __name__ == \"__main__\":\n parser = argparse.ArgumentParser(description=\"Create VeeR core settings file for riscv-dv\")\n parser.add_argument(\"riscvdv\", help=\"Path to riscv-dv project\")\n parser.add_argument(\"veer\", help=\"Path to veer project\")\n args = parser.parse_args()\n\n # verify arguments\n\n riscvdv_instr_pkg_path = Path(args.riscvdv, RISCV_INSTR_PKG_REL_PATH)\n if not riscvdv_instr_pkg_path.exists():\n raise FileNotFoundError(f\"{riscvdv_instr_pkg_path} not found\")\n check_sha256(riscvdv_instr_pkg_path, RISCV_INSTR_PKG_SHA)\n\n veer_decode_path = Path(args.veer, VEER_DECODE_REL_PATH)\n if not veer_decode_path.exists():\n raise FileNotFoundError(f\"{veer_decode_path} not found\")\n check_sha256(veer_decode_path, VEER_DECODE_SHA)\n\n veer_csrdecode_path = Path(args.veer, VEER_CSRDECODE_REL_PATH)\n if not veer_csrdecode_path.exists():\n raise FileNotFoundError(f\"{veer_csrdecode_path} not found\")\n check_sha256(veer_csrdecode_path, VEER_CSRDECODE_SHA)\n\n veer_dec_tlu_ctrl_path = Path(args.veer, VEER_EL2_DEC_TLU_CTRL_PATH)\n if not veer_dec_tlu_ctrl_path.exists():\n raise FileNotFoundError(f\"{veer_dec_tlu_ctrl_path} not found\")\n check_sha256(veer_dec_tlu_ctrl_path, VEER_EL2_DEC_TLU_CTRL_SHA)\n\n # parse\n\n (rdv_csrs, rdv_ints, rdv_excs, rdv_insn_to_cat) = parse_riscv_instr_pkg(riscvdv_instr_pkg_path)\n veer_insn: List[str] = parse_veer_decode(veer_decode_path)\n veer_csrs: Dict[str, int] = parse_veer_csrdecode(veer_csrdecode_path)\n (veer_ints, veer_excs) = parse_veer_dec_tlu_ctl(veer_dec_tlu_ctrl_path)\n\n # adjust data\n\n rdv_adj_insn_to_cat = dict(rdv_insn_to_cat)\n rdv_adj_insn_to_cat[\"WFI\"] = \"RV32I\"\n rdv_adj_insn_to_cat[\"MRET\"] = \"RV32I\"\n rdv_adj_cat_to_insn: Dict[str, str] = inv_dict(rdv_adj_insn_to_cat)\n\n veer_adj_insn = set()\n for insn in veer_insn:\n if insn == \"rev\":\n insn = \"REV8\"\n for x in [\n \"pack\",\n \"grevi\",\n \"gorci\",\n \"csrw\",\n \"csrrwi\",\n \"csrrs\",\n \"csrrc\",\n \"csrrci\",\n \"csrrw\",\n ]:\n if x in insn:\n insn = remove_suffix_number(insn)\n\n for val, new_val in [(\".\", \"_\"), (\"_rw\", \"\"), (\"_ro\", \"\")]:\n insn = insn.replace(val, new_val)\n\n veer_adj_insn.add(insn.upper())\n\n veer_adj_csrs = {int(v.replace(\".\", \"0\"), 2): k for k, v in veer_csrs.items()}\n\n # prepare data\n\n veer_found_insn: Set[str] = {insn for insn in veer_adj_insn if insn in rdv_adj_insn_to_cat}\n veer_not_found_insn: List[str] = {insn for insn in veer_adj_insn if insn not in rdv_adj_insn_to_cat}\n veer_found_insn_to_cat: Dict[str, str] = {insn: rdv_adj_insn_to_cat[insn] for insn in veer_found_insn}\n veer_found_cat_to_insn: Dict[str, str] = inv_dict(veer_found_insn_to_cat)\n veer_isas: Set[str] = set(veer_found_insn_to_cat.values())\n\n veer_unsupp_cat_to_insn: Dict[str, str] = {}\n for cat, insns in rdv_adj_cat_to_insn.items():\n if cat in veer_found_cat_to_insn:\n veer_unsupp_cat_to_insn[cat] = set(insns) - set(veer_found_cat_to_insn[cat])\n\n veer_found_csrs: Dict[str, str] = {\n csr: rdv_csrs[csr] for csr in veer_adj_csrs.keys() if csr in rdv_csrs.keys()\n }\n veer_not_found_csrs: Dict[str, str] = {\n csr: veer_adj_csrs[csr].upper() for csr in (set(veer_adj_csrs.keys() - set(veer_found_csrs.keys())))\n }\n veer_found_ints: Dict[int, str] = {intr: rdv_ints[intr] for intr in veer_ints if intr in rdv_ints}\n veer_not_found_ints: Set[str] = {intr for intr in veer_ints if intr not in rdv_ints}\n veer_found_excs: Dict[int, str] = {excp: rdv_excs[excp] for excp in veer_excs if excp in rdv_excs}\n veer_not_found_excs: Set[str] = {excp for excp in veer_excs if excp not in rdv_excs}\n\n # print info\n\n print(\"//-----------------------------------------------------------------------------\")\n print(\"// Processor feature configuration\")\n print(\"//-----------------------------------------------------------------------------\")\n print(\"//\")\n print(\"parameter int XLEN = 32;\")\n print(\"parameter satp_mode_t SATP_MODE = BARE;\")\n print(\"privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE, USER_MODE};\")\n print(\"\")\n print(\"// NOTE: To get supported and unsupported instructions compare\")\n print(\"// riscv-dv/src/riscv_instr_pkg.sv and Cores-VeeR-EL2/design/dec/decode files\")\n print(\"\")\n print(\"// Unsupported instructions\")\n print(\"riscv_instr_name_t unsupported_instr[] = {\")\n cnt = 0\n for i, (cat, insns) in enumerate(veer_unsupp_cat_to_insn.items()):\n if insns:\n sep = \",\" if cnt != (count_nonempty(veer_unsupp_cat_to_insn) - 1) else \"\"\n print(f\" {', '.join(insns)}{sep} // {cat}\")\n cnt += 1\n print(\"};\")\n print()\n print(\"// ISA supported by the processor\")\n print(\"riscv_instr_group_t supported_isa[$] = {\")\n for i, isa in enumerate(veer_isas):\n sep = \",\" if i != (len(veer_isas) - 1) else \"\"\n print(f\" {isa}{sep}\")\n print(\"};\")\n print()\n print(\"// Interrupt mode support\")\n print(\"mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED};\")\n print(\"\")\n print(\"// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is supported\")\n print(\"int max_interrupt_vector_num = 16;\")\n print(\"\")\n print(\"// Physical memory protection support\")\n print(\"bit support_pmp = 1;\")\n print(\"\")\n print(\"// Enhanced physical memory protection support\")\n print(\"// NOTE: Not supported by VeeR, described in:\")\n print(\"// https://raw.githubusercontent.com/riscv/riscv-tee/main/Smepmp/Smepmp.pdf\")\n print(\"bit support_epmp = 0;\")\n print(\"\")\n print(\"// Debug mode support\")\n print(\"bit support_debug_mode = 0;\")\n print(\"\")\n print(\"// Support delegate trap to user mode\")\n print(\"// When implementing UCAUSE, UTVEC, UTVAL, UEPC, USCRATCH, USTATUS, UIE, UIP\")\n print(\"bit support_umode_trap = 0;\")\n print(\"\")\n print(\"// Support sfence.vma instruction\")\n print(\"bit support_sfence = 0;\")\n print(\"\")\n print(\"// Support unaligned load/store\")\n print(\"bit support_unaligned_load_store = 1'b1;\")\n print(\"\")\n print(\"// GPR setting\")\n print(\"parameter int NUM_FLOAT_GPR = 32;\")\n print(\"parameter int NUM_GPR = 32;\")\n print(\"parameter int NUM_VEC_GPR = 32;\")\n print(\"\")\n print(\"// ----------------------------------------------------------------------------\")\n print(\"// Vector extension configuration\")\n print(\"// ----------------------------------------------------------------------------\")\n print(\"// Parameter for vector extension\")\n print(\"parameter int VECTOR_EXTENSION_ENABLE = 0;\")\n print(\"\")\n print(\"parameter int VLEN = 512;\")\n print(\"\")\n print(\"// Maximum size of a single vector element\")\n print(\"parameter int ELEN = 32;\")\n print(\"\")\n print(\"// Minimum size of a sub-element, which must be at most 8-bits.\")\n print(\"parameter int SELEN = 8;\")\n print(\"\")\n print(\"// Maximum size of a single vector element (encoded in vsew format)\")\n print(\"parameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3;\")\n print(\"\")\n print(\"// Maxium LMUL supported by the core\")\n print(\"parameter int MAX_LMUL = 8;\")\n print(\"// ----------------------------------------------------------------------------\")\n print(\"// Multi-harts configuration\")\n print(\"// ----------------------------------------------------------------------------\")\n print(\"\")\n print(\"// Number of harts\")\n print(\"parameter int NUM_HARTS = 1;\")\n print(\"\")\n print(\"// ----------------------------------------------------------------------------\")\n print(\"// Previleged CSR implementation\")\n print(\"// ----------------------------------------------------------------------------\")\n print(\"\")\n print(\"// Implemented previlieged CSR list\")\n print(\"`ifdef DSIM\")\n print(\"privileged_reg_t implemented_csr[] = {\")\n print(\"`else\")\n print(\"const privileged_reg_t implemented_csr[] = {\")\n print(\"`endif\")\n for i, (addr, name) in enumerate(veer_found_csrs.items()):\n sep = \",\" if i != len(veer_found_csrs) - 1 else \"\"\n print(f\" {name}{sep}\")\n print(\"};\")\n print(\"\")\n print(\"// Implementation-specific custom CSRs\")\n print(\"// By default all not found registers are put to custom csrs\")\n print(\"bit [11:0] custom_csr[] = {\")\n for i, (addr, name) in enumerate(veer_not_found_csrs.items()):\n sep = \",\" if i != len(veer_not_found_csrs) - 1 else \"\"\n print(f\" 12'h{addr:X}{sep} // {name}\")\n print(\"};\")\n print(\"\")\n print(\"// ----------------------------------------------------------------------------\")\n print(\"// Supported interrupt/exception setting, used for functional coverage\")\n print(\"// ----------------------------------------------------------------------------\")\n print(\"\")\n print(\"`ifdef DSIM\")\n print(\"interrupt_cause_t implemented_interrupt[] = {\")\n print(\"`else\")\n print(\"const interrupt_cause_t implemented_interrupt[] = {\")\n print(\"`endif\")\n for i, (intr, name) in enumerate(veer_found_ints.items()):\n sep = \",\" if i != len(veer_found_ints) - 1 else \"\"\n print(f\" {name}{sep}\")\n for i, intr in enumerate(veer_not_found_ints):\n if intr in (list(range(24, 32)) + list(range(48, 64))):\n print(f\" //{hex(intr)} custom interrupt used\")\n elif intr in ([14] + list(range(16, 20)) + list(range(32, 48))):\n print(f\" //{hex(intr)} reserved interrupt used\")\n else:\n print(f\" //{hex(intr)} not supported\")\n print(\"};\")\n print(\"\")\n print(\"`ifdef DSIM\")\n print(\"exception_cause_t implemented_exception[] = {\")\n print(\"`else\")\n print(\"const exception_cause_t implemented_exception[] = {\")\n for i, (exc, name) in enumerate(veer_found_excs.items()):\n sep = \",\" if i != len(veer_found_excs) - 1 else \"\"\n print(f\" {name}{sep}\")\n for i, exc in enumerate(veer_not_found_excs):\n print(f\" //{hex(exc)} not supported\")\n print(\"};\")\n print(\"`endif\")\n" }, { "path": "tools/riscv-dv/riscv_core_setting.sv", "content": "//-----------------------------------------------------------------------------\n// Processor feature configuration\n//-----------------------------------------------------------------------------\n//\nparameter int XLEN = 32;\nparameter satp_mode_t SATP_MODE = BARE;\nprivileged_mode_t supported_privileged_mode[] = {MACHINE_MODE, USER_MODE};\n\n// NOTE: To get supported and unsupported instructions compare\n// riscv-dv/src/riscv_instr_pkg.sv and Cores-VeeR-EL2/design/dec/decode files\n\n// Unsupported instructions\nriscv_instr_name_t unsupported_instr[] = {\n NOP, // RV32I\n CLZ, // RV32ZBB\n SROI, CMIX, FSRI, FSR, CMOV, SRO, SLO, FSL, SLOI, // RV32B\n // FIXME: As of date, the decision on which bitmanip extensions should go\n // into the `B` collection is not yet ratified.\n //\n // To stay on the safe side, let's assume here that *all of them* are\n // enabled by the `B` extension collection.\n CRC32C_B, CRC32C_H, CRC32C_W, CRC32_B, CRC32_H, CRC32_W, // RV32ZBR\n GORC, GORCI, GREV, GREVI, SHFL, SHFLI, UNSHFL, UNSHFLI, // RV32ZBP\n BCOMPRESS, BDECOMPRESS, // RV32ZBE\n BFP, // RV32ZBF\n XPERM_B, XPERM_H, XPERM_N // RV32ZBP\n};\n\n// ISA supported by the processor\nriscv_instr_group_t supported_isa[$] = {\n RV32I,\n RV32M,\n RV32C,\n RV32B,\n RV32ZBA,\n RV32ZBB,\n RV32ZBC,\n RV32ZBS\n};\n\n// Interrupt mode support\nmtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED};\n\n// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is supported\nint max_interrupt_vector_num = 16;\n\n// Physical memory protection support\nbit support_pmp = 1;\n\n// Enhanced physical memory protection support\n// NOTE: Not supported by VeeR, described in:\n// https://raw.githubusercontent.com/riscv/riscv-tee/main/Smepmp/Smepmp.pdf\nbit support_epmp = 0;\n\n// Debug mode support\nbit support_debug_mode = 0;\n\n// Support delegate trap to user mode\n// When implementing UCAUSE, UTVEC, UTVAL, UEPC, USCRATCH, USTATUS, UIE, UIP\nbit support_umode_trap = 0;\n\n// Support sfence.vma instruction\nbit support_sfence = 0;\n\n// Support unaligned load/store\nbit support_unaligned_load_store = 1'b1;\n\n// GPR setting\nparameter int NUM_FLOAT_GPR = 32;\nparameter int NUM_GPR = 32;\nparameter int NUM_VEC_GPR = 32;\n\n// ----------------------------------------------------------------------------\n// Vector extension configuration\n// ----------------------------------------------------------------------------\n// Parameter for vector extension\nparameter int VECTOR_EXTENSION_ENABLE = 0;\n\nparameter int VLEN = 512;\n\n// Maximum size of a single vector element\nparameter int ELEN = 32;\n\n// Minimum size of a sub-element, which must be at most 8-bits.\nparameter int SELEN = 8;\n\n// Maximum size of a single vector element (encoded in vsew format)\nparameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3;\n\n// Maxium LMUL supported by the core\nparameter int MAX_LMUL = 8;\n// ----------------------------------------------------------------------------\n// Multi-harts configuration\n// ----------------------------------------------------------------------------\n\n// Number of harts\nparameter int NUM_HARTS = 1;\n\n// ----------------------------------------------------------------------------\n// Previleged CSR implementation\n// ----------------------------------------------------------------------------\n\n// Implemented previlieged CSR list\n`ifdef DSIM\nprivileged_reg_t implemented_csr[] = {\n`else\nconst privileged_reg_t implemented_csr[] = {\n`endif\n MARCHID,\n MIMPID,\n MHARTID,\n MSTATUS,\n MTVEC,\n MIP,\n MIE,\n MCYCLE,\n MCYCLEH,\n MINSTRET,\n MINSTRETH,\n MSCRATCH,\n MEPC,\n MCAUSE,\n MTVAL,\n DCSR,\n DPC,\n TSELECT,\n TDATA1,\n TDATA2,\n MHPMCOUNTER3,\n MHPMCOUNTER4,\n MHPMCOUNTER5,\n MHPMCOUNTER6,\n MHPMCOUNTER3H,\n MHPMCOUNTER4H,\n MHPMCOUNTER5H,\n MHPMCOUNTER6H,\n MHPMEVENT3,\n MHPMEVENT4,\n MHPMEVENT5,\n MHPMEVENT6,\n MHPMCOUNTER7,\n MHPMCOUNTER8,\n MHPMCOUNTER16,\n MHPMCOUNTER7H,\n MHPMCOUNTER8H,\n MHPMCOUNTER16H,\n MHPMEVENT7,\n MHPMEVENT8,\n MHPMEVENT16,\n MCOUNTINHIBIT,\n MSECCFG,\n PMPCFG0,\n PMPCFG1,\n PMPCFG2,\n PMPCFG3,\n PMPADDR0,\n PMPADDR1,\n PMPADDR2,\n PMPADDR3,\n PMPADDR4,\n PMPADDR5,\n PMPADDR6,\n PMPADDR7,\n PMPADDR8,\n PMPADDR9,\n PMPADDR10,\n PMPADDR11,\n PMPADDR12,\n PMPADDR13,\n PMPADDR14,\n PMPADDR15\n};\n\n// Implementation-specific custom CSRs\n// By default all not found registers are put to custom csrs\nbit [11:0] custom_csr[] = {\n 12'h3D0, // CSR_PMPADDR32\n 12'h7C0, // CSR_MRAC\n 12'hBC0, // CSR_MDEAU\n 12'hFC0, // CSR_MDSEAC\n 12'h7C2, // CSR_MCPC\n 12'h7C4, // CSR_DMST\n 12'h3C0, // CSR_PMPADDR16\n 12'h7C6, // CSR_MPMC\n 12'hBC8, // CSR_MEIVT\n 12'hFC8, // CSR_MEIHAP\n 12'hBC9, // CSR_MEIPT\n 12'hBCA, // CSR_MEICPCT\n 12'hBCC, // CSR_MEICURPL\n 12'hBCB, // CSR_MEICIDPL\n 12'h7CE, // CSR_MFDHT\n 12'h7CF, // CSR_MFDHS\n 12'h7C8, // CSR_DICAWICS\n 12'h7CC, // CSR_DICAD0H\n 12'h7C9, // CSR_DICAD0\n 12'h7CA, // CSR_DICAD1\n 12'h7CB, // CSR_DICAGO\n 12'h7D3, // CSR_MITB0\n 12'h7D4, // CSR_MITCTL0\n 12'h7D2, // CSR_MITCNT0\n 12'h7D6, // CSR_MITB1\n 12'h7D7, // CSR_MITCTL1\n 12'h7D5, // CSR_MITCNT1\n 12'h3E0, // CSR_PMPADDR48\n 12'h7F0, // CSR_MICECT\n 12'h7F1, // CSR_MICCMECT\n 12'h7F2, // CSR_MDCCMECT\n 12'h7F8, // CSR_MCGC\n 12'h7F9, // CSR_MFDC\n 12'h7FF // CSR_MSCAUSE\n};\n\n// ----------------------------------------------------------------------------\n// Supported interrupt/exception setting, used for functional coverage\n// ----------------------------------------------------------------------------\n\n`ifdef DSIM\ninterrupt_cause_t implemented_interrupt[] = {\n`else\nconst interrupt_cause_t implemented_interrupt[] = {\n`endif\n M_SOFTWARE_INTR,\n M_TIMER_INTR,\n M_EXTERNAL_INTR\n //0x1c custom interrupt used\n //0x1d custom interrupt used\n //0x1e custom interrupt used\n};\n\n`ifdef DSIM\nexception_cause_t implemented_exception[] = {\n`else\nconst exception_cause_t implemented_exception[] = {\n INSTRUCTION_ACCESS_FAULT,\n BREAKPOINT,\n LOAD_ADDRESS_MISALIGNED,\n LOAD_ACCESS_FAULT,\n STORE_AMO_ADDRESS_MISALIGNED,\n STORE_AMO_ACCESS_FAULT,\n ECALL_MMODE\n};\n`endif\n" }, { "path": "tools/riscv-dv/testlist.yaml", "content": "- import: /target/rv32imc/testlist.yaml\n\n- test: riscv_pmp_disable_all_regions_test_veer\n desc: >\n Disable all permissions from PMP regions, randomize the boot mode,\n and randomize mstatus.mprv.\n Expect that all appropriate faults are taken, and that the core\n finishes executing successfully.\n iterations: 50\n gen_test: riscv_rand_instr_test\n gen_opts: >\n +instr_cnt=6000\n +set_mstatus_mprv=1\n +pmp_max_offset=00024000\n +pmp_region_1=L:1,X:0,W:0,R:0\n +pmp_region_2=L:1,X:0,W:0,R:0\n +pmp_region_3=L:1,X:0,W:0,R:0\n +pmp_region_4=L:1,X:0,W:0,R:0\n +pmp_region_5=L:1,X:0,W:0,R:0\n +pmp_region_6=L:1,X:0,W:0,R:0\n +pmp_region_7=L:1,X:0,W:0,R:0\n +pmp_region_8=L:1,X:0,W:0,R:0\n +pmp_region_9=L:1,X:0,W:0,R:0\n +pmp_region_10=L:1,X:0,W:0,R:0\n +pmp_region_11=L:1,X:0,W:0,R:0\n +pmp_region_12=L:1,X:0,W:0,R:0\n +pmp_region_13=L:1,X:0,W:0,R:0\n +pmp_region_14=L:1,X:0,W:0,R:0\n +pmp_region_15=L:1,X:0,W:0,R:0\n +enable_write_pmp_csr=1\n +mseccfg=MML:0,MMWP:0,RLB:0\n rtl_test: core_base_test\n\n- test: riscv_pmp_out_of_bounds_test_veer\n desc: >\n Default PMP settings - enable all regions with full permissions. Randomize\n mstatus.mprv and the boot mode. Insert streams of memory instructions that\n access addresses out of PMP boundaries.\n iterations: 50\n gen_test: riscv_rand_instr_test\n gen_opts: >\n +instr_cnt=6000\n +set_mstatus_mprv=1\n +pmp_max_offset=00024000\n +enable_write_pmp_csr=1\n +directed_instr_0=veer_load_store_rand_addr_instr_stream,50\n +mseccfg=MML:0,MMWP:0,RLB:0\n rtl_test: core_base_test\n sim_opts: >\n +is_double_fault_detected_fatal=0\n +enable_bad_intg_on_uninit_access=0\n\n- test: riscv_pmp_full_random_test_veer\n desc: >\n Completely randomize the boot mode, mstatus.mprv, and all PMP\n configuration, and allow PMP regions to overlap. A large number of\n iterations will be required since this introduces a huge state space of\n configurations. Some configurations result in very slow execution as every\n instruction ends up generating a fault. As this is still a useful test a\n short timeout with pass on timeout is enabled.\n iterations: 600\n gen_test: riscv_rand_instr_test\n gen_opts: >\n +instr_cnt=6000\n +set_mstatus_mprv=1\n +pmp_randomize=1\n +pmp_max_offset=00040000\n +pmp_allow_illegal_tor=1\n +directed_instr_0=riscv_load_store_rand_instr_stream,40\n +directed_instr_1=riscv_load_store_hazard_instr_stream,40\n +directed_instr_2=veer_load_store_rand_addr_instr_stream,40\n +enable_unaligned_load_store=1\n sim_opts: >\n +is_double_fault_detected_fatal=0\n +is_timeout_s_fatal=0\n +enable_bad_intg_on_uninit_access=0\n rtl_test: core_base_test\n\n- test: riscv_pmp_region_exec_test_veer\n desc: >\n A more specialised pmp_full_random_test that attempts to make regions\n executable whilst MML is set.\n iterations: 20\n gen_test: riscv_rand_instr_test\n gen_opts: >\n +instr_cnt=6000\n +set_mstatus_mprv=1\n +pmp_randomize=1\n +pmp_max_offset=00040000\n +pmp_allow_illegal_tor=1\n +directed_instr_0=riscv_load_store_rand_instr_stream,40\n +enable_unaligned_load_store=1\n +boot_mode=m\n +mseccfg=MML:1,MMWP:0,RLB:0\n sim_opts: >\n +is_double_fault_detected_fatal=0\n +is_timeout_s_fatal=0\n +enable_bad_intg_on_uninit_access=0\n rtl_test: core_base_test\n\n- test: riscv_bitmanip_full_test_veer\n desc: >\n Random instruction test with supported B extension instructions in full\n configuration.\n iterations: 10\n gen_test: riscv_rand_instr_test\n gen_opts: >\n +enable_zba_extension=1\n +enable_zbb_extension=1\n +enable_zbc_extension=1\n +enable_zbs_extension=1\n +enable_b_extension=1\n +enable_bitmanip_groups=zbe,zbf,zbp,zbr,zbt\n rtl_test: core_base_test\n\n- test: riscv_bitmanip_balanced_test_veer\n desc: >\n Random instruction test with supported B extension instructions in\n balanced configuration.\n iterations: 10\n gen_test: riscv_rand_instr_test\n gen_opts: >\n +enable_zba_extension=1\n +enable_zbb_extension=1\n +enable_zbs_extension=1\n +enable_b_extension=1\n +enable_bitmanip_groups=zbf,zbt\n\n- test: riscv_user_mode_rand_test\n desc: >\n User mode random instruction test\n iterations: 100\n gen_test: riscv_instr_base_test\n gen_opts: >\n +instr_cnt=10000\n +boot_mode=u\n rtl_test: core_base_test\n" }, { "path": "tools/riscv-dv/user_extension.svh", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright (c) 2024 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n`include \"veer_directed_instr_lib.sv\"\n" }, { "path": "tools/riscv-dv/veer_directed_instr_lib.sv", "content": "// SPDX-License-Identifier: Apache-2.0\n// Copyright (c) 2024 Antmicro \n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\nclass veer_load_store_rand_addr_instr_stream extends riscv_load_store_rand_addr_instr_stream;\n\n // Avoid writing in higher memory regions\n constraint addr_offset_veer_c {addr_offset[XLEN-1:30] == 0;}\n\n `uvm_object_utils(veer_load_store_rand_addr_instr_stream)\n `uvm_object_new\n\nendclass\n" }, { "path": "tools/riscv-dv/veer_log_to_trace_csv.py", "content": "#!/usr/bin/env python3\nimport argparse\nimport re\n\nfrom riscv_trace_csv import RiscvInstructionTraceEntry, RiscvInstructionTraceCsv\n\n# =============================================================================\n\nINSTR_RE = re.compile(r\"^\\s*(?P[0-9]+)\\s+:\\s+#(?P[0-9]+)\\s+0\\s+\"\n r\"(?P[0-9a-f]+)\\s+(?P[0-9a-f]+)\\s+\"\n r\"((?P[^=;]+)=(?P[0-9a-f]+))?\\s+\"\n r\"((?P[^=;]+)=(?P[0-9a-f]+))?\"\n r\"\\s+;\\s+(?P.*)\")\n\nNB_RE = re.compile(r\"^\\s*(?P[0-9]+)\\s+:\\s+\"\n r\"(?P[^=;]+)=(?P[0-9a-f]+)\"\n r\"\\s+;\\s+(?P(nbL|nbD))\")\n\nLD_MNEMONICS = [\"lb\", \"lbu\", \"lh\", \"lhu\", \"lw\", \"c.lw\", \"c.lwsp\"]\n\nDIV_MNEMONICS = [\"div\", \"divu\", \"rem\", \"remu\"]\n\n# =============================================================================\n\ndef parse_log(file_name):\n \"\"\"\n Parses VeeR-EL2 execution log generated by HDL simulation.\n\n The core is in-order however, due to pipelined implementation certain\n instructions may have an effect in different clock cycle than they are\n executed. The testbench trace handes this by emitting special \"nbL\" and\n \"nbD\" entries which need to be correlated with the actual instruction.\n\n Most of the logic of this parser does exactly that. Every trace entry is\n put into a temporary queue. Whenever a \"nbL\"/\"nbD\" is encountered, the\n queue is searched for a matching counterpart. This happens in the opposite\n way as well eg. when a \"div\" is encountered the queue is searched for \"nbD\"\n Once an entry is found, relevant data is filled in.\n\n Entires are poped of the queue only when they contain all the information\n for the complete trace.\n \"\"\"\n\n # Read the log\n with open(file_name, \"r\") as fp:\n lines = fp.readlines()\n\n data = []\n queue = []\n\n for line in lines:\n line = line.strip()\n\n # Instruction\n match = INSTR_RE.match(line)\n if match is not None:\n groups = match.groupdict()\n\n gpr = None\n csr = None\n if groups[\"reg\"] and groups[\"val\"]:\n gpr = (\"{}:{}\".format(groups[\"reg\"], groups[\"val\"]))\n if groups[\"csr\"] and groups[\"csr_val\"]:\n csr = (\"{}:{}\".format(groups[\"csr\"], groups[\"csr_val\"]))\n\n fields = groups[\"mnemonic\"].split()\n mnemonic = fields[0]\n operands = fields[1].split(\",\") if len(fields) > 1 else []\n\n entry = None\n\n # Stop on ecall\n if mnemonic == \"ecall\":\n break\n\n # Delayed effect, search the queue\n if gpr is None and mnemonic in LD_MNEMONICS + DIV_MNEMONICS:\n\n # Skip if targets x0 (zero) which makes no sense\n if operands[0] == \"zero\":\n continue \n\n for ent in reversed(queue):\n\n if (ent.operand == \"nbL\" and mnemonic in LD_MNEMONICS) or \\\n (ent.operand == \"nbD\" and mnemonic in DIV_MNEMONICS):\n\n assert len(operands), line\n assert len(ent.gpr), ent.get_trace_string()\n\n reg, val = ent.gpr[0].split(\":\") # FIXME: Assuming single GPR\n if reg == operands[0]:\n entry = ent\n break\n\n # Enqueue or not\n enqueue = entry is None and (gpr is not None or mnemonic in \\\n LD_MNEMONICS + DIV_MNEMONICS)\n\n # Entry not found in the queue, create it\n if not entry:\n entry = RiscvInstructionTraceEntry()\n\n # Fill data\n entry.pc = groups[\"pc\"]\n entry.binary = groups[\"opc\"]\n entry.operand = groups[\"mnemonic\"]\n entry.mode = \"0\" # TODO\n\n # Append GPR if any\n if gpr:\n entry.gpr.append(gpr)\n if csr:\n entry.csr.append(csr)\n\n # Enqueue\n if enqueue:\n queue.append(entry)\n\n # nbL / nbD\n match = NB_RE.match(line)\n if match is not None:\n groups = match.groupdict()\n\n assert groups[\"reg\"] and groups[\"val\"], line\n gpr = (\"{}:{}\".format(groups[\"reg\"], groups[\"val\"]))\n\n # Skip if targets x0 (zero) which makes no sense\n if groups[\"reg\"] == \"zero\":\n continue \n\n # Find an existing nbL/nbD entry in the queue. Match destination GPR\n for entry in reversed(queue):\n\n fields = entry.operand.split()\n mnemonic = fields[0]\n operands = fields[1].split(\",\") if len(fields) > 1 else []\n\n if (groups[\"mnemonic\"] == \"nbL\" and mnemonic in LD_MNEMONICS) or \\\n (groups[\"mnemonic\"] == \"nbD\" and mnemonic in DIV_MNEMONICS):\n assert len(operands), entry\n if groups[\"reg\"] == operands[0]:\n entry.gpr.append(gpr)\n break\n\n # Add a new entry\n else:\n entry = RiscvInstructionTraceEntry()\n entry.operand = groups[\"mnemonic\"]\n entry.gpr.append(gpr)\n\n queue.append(entry)\n\n # Dequeue entries that have all they need. Stop at the first one which\n # is missing something.\n while len(queue):\n entry = queue[0]\n\n # Cannot dequeue, break\n if not entry.pc or not entry.gpr:\n break\n\n # Pop\n data.append(entry)\n queue = queue[1:]\n\n # Safeguard\n if len(queue) >= 1000:\n print(\"ERROR: Malformed trace, the queue grew too much\")\n for entry in reversed(queue):\n print(\"\", entry.get_trace_string())\n assert False\n\n return data\n\n\ndef write_csv(file_name, data):\n \"\"\"\n Writes the trace to CSV\n \"\"\"\n\n with open(file_name, \"w\") as fp:\n\n writer = RiscvInstructionTraceCsv(fp)\n writer.start_new_trace()\n\n for entry in data:\n writer.write_trace_entry(entry)\n\n# =============================================================================\n\n\ndef main():\n parser = argparse.ArgumentParser()\n parser.add_argument(\n \"--log\",\n type=str,\n required=True,\n help=\"HDL simulation trace log\"\n )\n parser.add_argument(\n \"--csv\",\n type=str,\n required=True,\n help=\"Output CSV file\"\n )\n\n args = parser.parse_args()\n\n # Parse log\n data = parse_log(args.log)\n\n # Write CSV\n write_csv(args.csv, data)\n\nif __name__ == \"__main__\":\n main()\n" }, { "path": "tools/smalldiv", "content": "#!/usr/bin/perl\n\nuse Getopt::Long;\n\nuse integer;\n\n$helpusage = \"placeholder\";\n\nGetOptions ('len=s' => \\$len,\n 'num=s' => \\$num,\n 'den=s' => \\$den,\n 'skip' => \\$skip) || die(\"$helpusage\");\n\nif (!defined($len)) { $len=8; }\n$LEN=$len;\n\n$n=d2b($num); # numerator - quotient\n$m=d2b($den); # denominator - divisor\n\n\nprintf(\".i 8\\n\");\nprintf(\".o 4\\n\");\nprintf(\".ilb q_ff[3] q_ff[2] q_ff[1] q_ff[0] m_ff[3] m_ff[2] m_ff[1] m_ff[0]\\n\");\nprintf(\".ob smallnum[3] smallnum[2] smallnum[1] smallnum[0]\\n\");\nprintf(\".type fr\\n\");\nfor ($q=0; $q<16; $q++) {\n for ($m=0; $m<16; $m++) {\n if ($m==0) { next; }\n $result=int($q/$m);\n printf(\"%s %s %s\\n\",d2bl($q,4),d2bl($m,4),d2bl($result,4));\n }\n}\n\nexit;\n\n#$LEN=length($n);\n\n$a=\"0\"x$LEN;\n$q=$n;\n\n#printf(\"n=%s, m=%s\\n\",$n,$m);\n#printf(\"a=%s, q=%s\\n\",$a,$q);\n\nfor ($i=1; $i<=$LEN; $i++) {\n\n #printf(\"iteration $n:\\n\");\n\n printf(\"$i: a=%s q=%s\\n\",$a,$q);\n\n\n $signa = substr($a,0,1);\n\n\n $a = substr($a.$q,1,$LEN); # new a with q shifted in\n\n if ($signa==0) { $a=b2d($a)-b2d($m); }\n else { $a=b2d($a)+b2d($m); }\n\n $a=d2b($a);\n\n\n $signa = substr($a,0,1);\n if ($signa==0) { $q=substr($q,1,$LEN-1).\"1\"; }\n else { $q=substr($q,1,$LEN-1).\"0\"; }\n\n}\n\n\n#printf(\"a=$a\\n\");\n$signa = substr($a,0,1);\nif ($signa==1 && !defined($skip)) {\n printf(\"correction:\\n\");\n $a=b2d($a)+b2d($m);\n $a=d2b($a);\n}\n#printf(\"a=$a\\n\");\nprintf(\"%d / %d = %d R %d \",b2d($n),b2d($m),b2d($q),b2d($a));\nif ($a eq $n) { printf(\"-> remainder equal numerator\\n\"); }\nelse { printf(\"\\n\"); }\n\nsub b2d {\n my ($v) = @_;\n\n $v = oct(\"0b\" . $v);\n\n return($v);\n}\n\nsub d2b {\n my ($v) = @_;\n\n my $repeat;\n\n $v = sprintf \"%b\",$v;\n if (length($v)<$LEN) {\n $repeat=$LEN-length($v);\n $v=\"0\"x$repeat.$v;\n }\n elsif (length($v)>$LEN) {\n $v=substr($v,length($v)-$LEN,$LEN);\n }\n\n return($v);\n}\n\nsub d2bl {\n my ($v,$LEN) = @_;\n\n my $repeat;\n\n $v = sprintf \"%b\",$v;\n if (length($v)<$LEN) {\n $repeat=$LEN-length($v);\n $v=\"0\"x$repeat.$v;\n }\n elsif (length($v)>$LEN) {\n $v=substr($v,length($v)-$LEN,$LEN);\n }\n\n return($v);\n}\n" }, { "path": "tools/unrollforverilator", "content": "#!/usr/bin/perl\n#use strict;\n#use warnings;\n\nmy $RV_ROOT = $ENV{RV_ROOT};\n\nmy $TOTAL_INT=$ARGV[0];\nprint \"// argv=\".$ARGV[0].\"\\n\";\nmy $NUM_LEVELS;\nif($TOTAL_INT==2){$NUM_LEVELS=1;}\nelsif ($TOTAL_INT==4){$NUM_LEVELS=2;}\nelsif ($TOTAL_INT==8){$NUM_LEVELS=3;}\nelsif ($TOTAL_INT==16){$NUM_LEVELS=4;}\nelsif ($TOTAL_INT==32){$NUM_LEVELS=5;}\nelsif ($TOTAL_INT==64){$NUM_LEVELS=6;}\nelsif ($TOTAL_INT==128){$NUM_LEVELS=7;}\nelsif ($TOTAL_INT==256){$NUM_LEVELS=8;}\nelsif ($TOTAL_INT==512){$NUM_LEVELS=9;}\nelsif ($TOTAL_INT==1024){$NUM_LEVELS=10;}\nelse {$NUM_LEVELS=int(log($TOTAL_INT)/log(2))+1;}\nprint (\"// TOTAL_INT=\".$TOTAL_INT.\" NUM_LEVELS=\".$NUM_LEVELS.\"\\n\");\n$next_level = 1;\nprint (\"`ifdef RV_PIC_2CYCLE\\n\");\nif($TOTAL_INT > 2){\nprint (\"// LEVEL0\\n\");\nprint (\"logic [TOTAL_INT+2:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en_\".$next_level.\";\\n\");\nprint (\"logic [TOTAL_INT+2:0] [ID_BITS-1:0] level_intpend_id_\".$next_level.\";\\n\");\nprint (\" for (m=0; m<=(TOTAL_INT)/(2**(\".$next_level.\")) ; m++) begin : COMPARE0\\n\");\nprint (\" if ( m == (TOTAL_INT)/(2**(\".$next_level.\"))) begin \\n\");\nprint (\" assign level_intpend_w_prior_en_\".$next_level.\"[m+1] = '0 ;\\n\");\nprint (\" assign level_intpend_id_\".$next_level.\"[m+1] = '0 ;\\n\");\nprint (\" end\\n\");\nprint (\" cmp_and_mux #(\\n\");\nprint (\" .ID_BITS(ID_BITS),\\n\");\nprint (\" .INTPRIORITY_BITS(INTPRIORITY_BITS)) cmp_l\".$next_level.\" (\\n\");\nprint (\" .a_id(level_intpend_id[0][2*m]),\\n\");\nprint (\" .a_priority(level_intpend_w_prior_en[0][2*m]),\\n\");\nprint (\" .b_id(level_intpend_id[0][2*m+1]),\\n\");\nprint (\" .b_priority(level_intpend_w_prior_en[0][2*m+1]),\\n\");\nprint (\" .out_id(level_intpend_id_\".$next_level.\"[m]),\\n\");\nprint (\" .out_priority(level_intpend_w_prior_en_\".$next_level.\"[m])) ;\\n\");\nprint (\" \\n\");\nprint (\" end\\n\\n\");\nfor (my $l=1; $l> i) & 1\n\n\ndef _prevent_11_pairs(value):\n new_value = 0\n for i in reversed(range(0, 31, 2)):\n new_value = new_value << 2\n b0 = get_bit(value, i)\n b1 = get_bit(value, i + 1)\n new_value |= (b1 << 1) | (b0 & (not b1))\n return new_value\n\n\ndef _mhpme_zero_event(value):\n return (\n (value > 516)\n | ((value < 512) & (value > 56))\n | ((value < 54) & (value > 50))\n | (value == 29)\n | (value == 33)\n )\n\n\ndef _m_ect(value):\n if ((value >> 27) & 0x1F) > 26:\n value = value & 0x07FFFFFF\n value = value | (26 << 27)\n return value\n\n\ndef _dicawics(value):\n value = value & 0x1FFFFFF\n value = value & ~(1 << 23)\n value = value & ~(1 << 22)\n value = value & ~(1 << 19)\n value = value & ~(1 << 18)\n value = value & ~(1 << 17)\n value = value & ~(1 << 2)\n value = value & ~(1 << 1)\n value = value & ~(1 << 0)\n return value\n\n\ndef _dcsr(value):\n value = (value & 0xFFFF) | (0x4 << 28)\n value = (value & 0xFFFFFFFC) | 0x3\n value = value & ~(1 << 14) # reserved\n value = value & ~(1 << 13) # ebreaks (0 for VeeR-EL2)\n value = value & ~(1 << 12) # ebreaku (0 for VeeR-EL2)\n value = value & ~(1 << 9) # stoptime (0 for VeeR-EL2)\n value = value & ~(1 << 8) # reserved\n value = (value & ~(1 << 7)) | (1 << 7)\n value = (value & ~(1 << 6)) | (1 << 6)\n value = value & ~(1 << 5) # reserved\n value = value & ~(1 << 4) # reserved\n value = value & ~(1 << 3) # reserved\n return value\n\n\n# Dbus Error Address Unlock register\nMDEAU = CSR(0xBC0)\n# Dbus Store Error Address Capture register\nMDSEAC = CSR(0xFC0)\n\nMEICPCT = CSR(0xBCA)\nMEIVT = CSR(0xBC8)\n# MTSEL (R/W)\n# [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count\nMTSEL = CSR(0x7A0)\n\n# MTDATA1 (R/W)\n# [31:0] : Trigger Data 1\nMTDATA1 = CSR(0x7A1)\n\n# MTDATA2 (R/W)\n# [31:0] : Trigger Data 2\nMTDATA2 = CSR(0x7A2)\n\n# External Interrupt Priority Threshold\nMEIPT = CSR(0xBC9, lambda _: _ & 0xF)\n# [31:2] BASE : Trap vector base address\n# [1] - Reserved, not implemented, reads zero\n# [0] MODE : 0 = Direct, 1 = Asyncs\nMTVEC = CSR(0x305, lambda _: _ & 0xFFFFFFFD)\n# Region Access Control Register, 16 regions\nMRAC = CSR(0x7C0, _prevent_11_pairs)\nMCOUNTINHIBIT = CSR(0x320, lambda _: _ & 0x7D)\nMFDHT = CSR(0x7CE, lambda _: _ & 0x3F)\nMEICURPL = CSR(0xBCC, lambda _: _ & 0xF)\nMFDC = CSR(0xBCC, lambda _: _ & 0x71FBF)\n# performance counters\nMHPMC3 = CSR(0xB03)\nMHPMC3H = CSR(0xB83)\nMHPMC4 = CSR(0xB04)\nMHPMC4H = CSR(0xB84)\nMHPMC5 = CSR(0xB05)\nMHPMC5H = CSR(0xB85)\nMHPMC6 = CSR(0xB06)\nMHPMC6H = CSR(0xB86)\nMINSTRETL = CSR(0xB02)\nMINSTRETH = CSR(0xB82)\nMCYCLEL = CSR(0xB00)\nMCYCLEH = CSR(0xB80)\n\n# hardware performance monitors\nMHPME3 = CSR(0x323, lambda x: 0 if _mhpme_zero_event(x) else x)\nMHPME4 = CSR(0x324, lambda x: 0 if _mhpme_zero_event(x) else x)\nMHPME5 = CSR(0x325, lambda x: 0 if _mhpme_zero_event(x) else x)\nMHPME6 = CSR(0x326, lambda x: 0 if _mhpme_zero_event(x) else x)\n\nMICECT = CSR(0x7F0, _m_ect)\nMICCMECT = CSR(0x7F1, _m_ect)\nMDCCMECT = CSR(0x7F2, _m_ect)\n\n# debug mode CSRs\nDICAD0 = CSR(0x7C9)\nDICAD0H = CSR(0x7CC)\nDICAD1 = CSR(0x7CA)\nDICAWICS = CSR(0x7C8, _dicawics)\nDPC = CSR(0x7B1, lambda _: _ & ~(0x1))\nDCSR = CSR(0x7B0, _dcsr) # upper 4 bits hardcoded to 0x4\n\nMEICIDPL = CSR(0xBCB, lambda _: _ & 0xF)\n" }, { "path": "verification/block/common/utils.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\nimport logging\nfrom collections.abc import Callable\n\nfrom scipy.stats import binom\n\n# ==============================================================================\n\n\ndef collect_signals(signals, uut, obj, uut_prefix=\"\", obj_prefix=\"\", signal_map=None):\n \"\"\"\n Collects signal objects from UUT and attaches them to the given object.\n Optionally UUT signals can be prefixed with the uut_prefix and object\n signals with the obj_prefix. If signal_map is given it should be a dict\n mapping signal names to actual UUT signal names.\n \"\"\"\n\n for sig in signals:\n if signal_map is not None:\n uut_sig = signal_map.get(sig, uut_prefix + sig)\n else:\n uut_sig = uut_prefix + sig\n obj_sig = obj_prefix + sig\n if hasattr(uut, uut_sig):\n s = getattr(uut, uut_sig)\n\n else:\n s = None\n logging.error(\"Module {} does not have a signal '{}'\".format(str(uut), sig))\n\n setattr(obj, obj_sig, s)\n\n\ndef collect_bytes(data, strb=None):\n \"\"\"\n Collects data bytes asserted on a data bus. Uses the strb value to\n determine which octets are valid. Both data and strb must be cocotb\n signals. strb can be None.\n \"\"\"\n\n if strb is not None:\n assert len(data) == 8 * len(strb)\n\n res = []\n for i in range(len(data) // 8):\n if strb is None or strb.value & (1 << i):\n dat = (int(data.value) >> (8 * i)) & 0xFF\n res.append(dat)\n\n return bytes(res)\n\n\ndef smallest_number_of_trials(p: float, k: int, j: float):\n \"\"\"\n This function is used to calculate the minimum number of clock cycles that\n need to pass for an event to be successful given the probability of its\n conditions occurring.\n\n Example:\n Let module under test enter into a busy state with probability `p`.\n For an event A to occur the module must not be in the busy state.\n\n Then, n = smallest_number_of_trials(p, 1, 99.9) is the smallest number\n of clock cycles that need to pass for there being 99.9% chance that at least\n one event A occurs in this n-cycle period.\n\n (see verification/block/dma)\n\n Based on https://math.stackexchange.com/a/4776687.\n\n Returns the smallest n such that\n P(X >= k) >= j / 100, where X is Binomial(n, p).\n \"\"\"\n\n def function_bisect(f: Callable[[int], float], target: float) -> float:\n \"\"\"\n f is an increasing function from the nonnegative integers to floats.\n Returns the smallest x such that f(x) >= target.\n WARNING: This loops forever if there is no x for which f(x) >= target.\n \"\"\"\n\n lower_lim = 0\n if f(lower_lim) >= target:\n return lower_lim\n\n upper_lim = 2\n while f(upper_lim) < target:\n upper_lim *= 2\n\n while upper_lim - lower_lim >= 2:\n mid = (lower_lim + upper_lim) // 2\n if f(mid) >= target:\n upper_lim = mid\n elif f(mid) < target:\n lower_lim = mid\n return upper_lim\n\n def prob_X_ge_k(n):\n return 1 - binom.cdf(k - 1, n, p)\n\n return function_bisect(prob_X_ge_k, j / 100)\n" }, { "path": "verification/block/common.mk", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\n$(info $(shell cocotb-config --makefiles))\n\nTOPLEVEL_LANG = verilog\nSIM ?= verilator\nWAVES ?= 1\n\n# Paths\nCURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nCFGDIR := $(abspath $(CURDIR)/snapshots/default)\nCONFIG := $(abspath $(CURDIR)/../../configs)\n\n# Set pythonpath so that tests can access common modules\nexport PYTHONPATH := $(CURDIR)/common\n\n# Common sources\nCOMMON_SOURCES = $(CFGDIR)/common_defines.vh\nCOMMON_SOURCES += $(CFGDIR)/el2_pdef.vh\nCOMMON_SOURCES += $(SRCDIR)/include/el2_def.sv\nCOMMON_SOURCES += $(SRCDIR)/lib/beh_lib.sv\n\nVERILOG_SOURCES := $(COMMON_SOURCES) $(VERILOG_SOURCES)\n\n# Coverage reporting\nCOVERAGE_TYPE ?= \"\"\nifeq (\"$(COVERAGE_TYPE)\", \"all\")\n VERILATOR_COVERAGE = --coverage\nelse ifeq (\"$(COVERAGE_TYPE)\", \"branch\")\n VERILATOR_COVERAGE = --coverage-line\nelse ifeq (\"$(COVERAGE_TYPE)\", \"toggle\")\n VERILATOR_COVERAGE = --coverage-toggle\nelse ifeq (\"$(COVERAGE_TYPE)\", \"functional\")\n VERILATOR_COVERAGE = --coverage-user\nelse\n VERILATOR_COVERAGE = \"\"\nendif\n\nifeq ($(SIM), verilator)\n COMPILE_ARGS += --coverage-max-width 20000\n COMPILE_ARGS += --timing\n COMPILE_ARGS += -Wall\n COMPILE_ARGS += $(CURDIR)/config.vlt\n\n EXTRA_ARGS += --trace --trace-structs\n EXTRA_ARGS += $(VERILATOR_COVERAGE)\n EXTRA_ARGS += -I$(CFGDIR) -Wno-DECLFILENAME\n\n # Include test specific Verilator config if it exists\n ifneq (\"$(wildcard $(TEST_DIR)/config.vlt)\",\"\")\n COMPILE_ARGS += $(TEST_DIR)/config.vlt\n endif\n\n PARALLEL_THREADS := $(shell echo $$(( $(shell nproc) - 1 )))\n BUILD_ARGS += -j $(PARALLEL_THREADS)\n\nelse ifeq ($(SIM), vcs)\n ifneq ($(CM_FILE),)\n EXTRA_ARGS += -cm_hier $(TEST_DIR)/$(CM_FILE)\n endif\n EXTRA_ARGS += +incdir+$(CFGDIR) +incdir+$(SRCDIR)/include -assert svaext -cm line+cond+fsm+tgl+branch +vcs+lic+wait\nendif\n\n# Produces verilog.dump VCD file\nifneq ($(VCS_DEBUG),)\n EXTRA_ARGS = +vcs+dumpon +vcs+dumpvars\nendif\n\nCOCOTB_HDL_TIMEUNIT = 1ns\nCOCOTB_HDL_TIMEPRECISION = 10ps\n\n# Build directory\nifeq ($(COVERAGE_TYPE),\"\")\n SIM_BUILD ?= sim-build\nelse\n SIM_BUILD ?= sim-build-$(COVERAGE_TYPE)\nendif\n\ninclude $(shell cocotb-config --makefiles)/Makefile.sim\n\nifeq ($(PMP_TEST),)\n EXTRA_CONFIG_OPTS = \"\"\nelse\n EXTRA_CONFIG_OPTS = \"-set=pmp_entries=64\"\nendif\n\nifneq ($(DEC_TEST),)\n EXTRA_CONFIG_OPTS += \"-set=fast_interrupt_redirect=0\"\nendif\n\n# Rules for generating VeeR config\n$(CFGDIR)/common_defines.vh:\n\tcd $(CURDIR) && $(CONFIG)/veer.config -fpga_optimize=0 $(EXTRA_CONFIG_OPTS) $(EXTRA_VEER_CONFIG)\n" }, { "path": "verification/block/config.vlt", "content": "`verilator_config\n\n// Unnamed blocks do not influence logic\nlint_off -rule GENUNNAMED\n\n// Unconnected IC memory output pins\nlint_off -rule PINCONNECTEMPTY -file \"*/el2_ifu_ic_mem.sv\"\n\n// These require revisit to remove multiple definitions of variables with same names\nlint_off -rule VARHIDDEN -file \"*/axi4_to_ahb.sv\"\nlint_off -rule VARHIDDEN -file \"*/el2_ifu_bp_ctl.sv\"\nlint_off -rule VARHIDDEN -file \"*/el2_ifu_mem_ctl.sv\"\nlint_off -rule VARHIDDEN -file \"*/el2_exu_alu_ctl.sv\"\nlint_off -rule VARHIDDEN -file \"*/el2_pic_ctrl.sv\"\n\n// Width related warning require explicit type casting\nlint_off -rule WIDTHTRUNC -file \"*/ahb_to_axi4.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/axi4_to_ahb.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_dma_ctrl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_ifu_ifc_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_ifu_bp_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_ifu_aln_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_dec_decode_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_dec_ib_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_dec_tlu_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_dec_trigger.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_lib.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/beh_lib.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_lsu_bus_buffer.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_dec_pmp_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_lsu_addrcheck.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_lsu_dccm_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_lsu_dccm_mem.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_lsu_trigger.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_ifu_iccm_mem.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_ifu_mem_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_exu.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_exu_alu_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_exu_div_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_exu_mul_ctl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_dbg.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_pic_ctrl.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_pmp.sv\"\nlint_off -rule WIDTHTRUNC -file \"*/el2_mem_if.sv\"\n\nlint_off -rule WIDTHEXPAND -file \"*/el2_exu.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_pic_ctrl.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_ifu_bp_ctl.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_ifu_mem_ctl.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_ifu_iccm_mem.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_lsu_addrcheck.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_lsu_bus_buffer.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_lsu_stbuf.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_lsu_dccm_ctl.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_lsu_dccm_mem.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_exu_mul_ctl.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_dec_tlu_ctl.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_dma_ctrl.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_dbg.sv\"\nlint_off -rule WIDTHEXPAND -file \"*/el2_veer_lockstep.sv\" -lines 383\n\n// Unused parameters are probably safe to remove from RTL\nlint_off -rule UNUSEDPARAM -file \"*/axi4_to_ahb.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_ifu.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_pic_ctrl.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_dma_ctrl.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_ifu_bp_ctl.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_ifu_mem_ctl.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_dec_tlu_ctl.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_lsu_dccm_ctl.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_lsu_dccm_mem.sv\"\n\n// Gated clock, expected latch\nlint_off -rule LATCH -file \"*/beh_lib.sv\" -lines 781\n\nlint_off -rule BLKSEQ -file \"*/beh_lib.sv\" -lines 783\n\n// The Verilator reports that `core_rst_l` is being used in sync and async nets,\n// pointing to `rvdff` module as a source of the problem. Since the `rvdff` looks\n// unrelated to `core_rst_l`, it requires a closer investigation.\nlint_off -rule SYNCASYNCNET -file \"*/el2_veer.sv\" -lines 41\n\n// Unused clocks from shadow core\nlint_off -rule PINCONNECTEMPTY -file \"*/el2_veer_lockstep.sv\" -lines 1057-1058\n\n// Logic that might be not optimal for event based model used by Verilator\nlint_off -rule UNOPTFLAT -file \"*/axi4_to_ahb.sv\"\nlint_off -rule UNOPTFLAT -file \"*/el2_ifu_ifc_ctl.sv\"\nlint_off -rule UNOPTFLAT -file \"*/el2_dec_decode_ctl.sv\"\nlint_off -rule UNOPTFLAT -file \"*/el2_exu_mul_ctl.sv\"\nlint_off -rule UNOPTFLAT -file \"*/el2_exu_div_ctl.sv\"\nlint_off -rule UNOPTFLAT -file \"*/el2_lsu.sv\"\nlint_off -rule UNOPTFLAT -file \"*/el2_lsu_lsc_ctl.sv\"\nlint_off -rule UNOPTFLAT -file \"*/el2_pic_ctrl.sv\"\n\n// Warnings related to the generated `el2_param.vh`\nlint_off -rule UNUSEDPARAM -file \"*/el2_ifu_compress_ctl.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_dec_gpr_ctl.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_dec_trigger.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_lsu_trigger.sv\"\nlint_off -rule UNUSEDPARAM -file \"*/el2_lsu_clkdomain.sv\"\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_ifu_compress_ctl.sv\"\n" }, { "path": "verification/block/dccm/Makefile", "content": "\nnull :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_lsu_dccm_mem_wrapper\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/lib/el2_mem_if.sv \\\n $(TEST_DIR)/el2_lsu_dccm_mem_wrapper.sv \\\n $(SRCDIR)/lsu/el2_lsu_dccm_mem.sv \\\n $(SRCDIR)/lib/mem_lib.sv\n\n# Undefine the VERILATOR macro to make the code use actual RAM cells instead\n# of simulation models\nEXTRA_ARGS += -UVERILATOR\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/dccm/config.vlt", "content": "`verilator_config\n\nlint_off -rule PINCONNECTEMPTY -file \"*/el2_lsu_dccm_mem_wrapper.sv\"\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_lsu_dccm_mem_wrapper.sv\"\n\nlint_off -rule IMPORTSTAR -file \"*/el2_mem_if.sv\"\n" }, { "path": "verification/block/dccm/el2_lsu_dccm_mem_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro \n// SPDX-License-Identifier: Apache-2.0\n\nmodule el2_lsu_dccm_mem_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n input logic clk,\n input logic active_clk,\n input logic rst_l,\n input logic clk_override,\n\n input logic dccm_wren,\n input logic dccm_rden,\n input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,\n input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,\n input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,\n input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,\n input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,\n\n // el2_dccm_ext_in_pkt_t\n input logic dccm_ext_in_pkt_TEST1,\n input logic dccm_ext_in_pkt_RME,\n input logic [3:0] dccm_ext_in_pkt_RM,\n input logic dccm_ext_in_pkt_LS,\n input logic dccm_ext_in_pkt_DS,\n input logic dccm_ext_in_pkt_SD,\n input logic dccm_ext_in_pkt_TEST_RNM,\n input logic dccm_ext_in_pkt_BC1,\n input logic dccm_ext_in_pkt_BC2,\n\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,\n output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,\n\n input logic scan_mode\n);\n\n localparam DCCM_ECC_WIDTH = pt.DCCM_FDATA_WIDTH - pt.DCCM_DATA_WIDTH;\n\n logic [pt.DCCM_NUM_BANKS-1:0] dccm_clken;\n logic [pt.DCCM_NUM_BANKS-1:0] dccm_wren_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][ DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;\n logic [pt.DCCM_NUM_BANKS-1:0][ DCCM_ECC_WIDTH-1:0] dccm_bank_ecc;\n\n logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_fdata_bank;\n logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_FDATA_WIDTH-1:0] dccm_bank_fdout;\n\n el2_mem_if mem_export ();\n assign dccm_clken = mem_export.dccm_clken;\n assign dccm_wren_bank = mem_export.dccm_wren_bank;\n assign dccm_addr_bank = mem_export.dccm_addr_bank;\n assign dccm_wr_data_bank = mem_export.dccm_wr_data_bank;\n assign dccm_wr_ecc_bank = mem_export.dccm_wr_ecc_bank;\n\n // Pack dccm_ext_in_pkt\n el2_dccm_ext_in_pkt_t [pt.DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt;\n\n for (genvar i = 0; i < pt.DCCM_NUM_BANKS; i++) begin : gen_dccm_ext_pkt\n assign dccm_ext_in_pkt[i].TEST1 = dccm_ext_in_pkt_TEST1;\n assign dccm_ext_in_pkt[i].RME = dccm_ext_in_pkt_RME;\n assign dccm_ext_in_pkt[i].RM = dccm_ext_in_pkt_RM;\n assign dccm_ext_in_pkt[i].LS = dccm_ext_in_pkt_LS;\n assign dccm_ext_in_pkt[i].DS = dccm_ext_in_pkt_DS;\n assign dccm_ext_in_pkt[i].SD = dccm_ext_in_pkt_SD;\n assign dccm_ext_in_pkt[i].TEST_RNM = dccm_ext_in_pkt_TEST_RNM;\n assign dccm_ext_in_pkt[i].BC1 = dccm_ext_in_pkt_BC1;\n assign dccm_ext_in_pkt[i].BC2 = dccm_ext_in_pkt_BC2;\n end : gen_dccm_ext_pkt\n\n localparam DCCM_INDEX_DEPTH = ((pt.DCCM_SIZE)*1024)/((pt.DCCM_BYTE_WIDTH)*(pt.DCCM_NUM_BANKS)); // Depth of memory bank\n\n // 8 Banks, 16KB each (2048 x 72)\n for (genvar i = 0; i < pt.DCCM_NUM_BANKS; i++) begin : gen_dccm_mem\n assign dccm_wr_fdata_bank[i] = {\n mem_export.dccm_wr_ecc_bank[i], mem_export.dccm_wr_data_bank[i]\n };\n assign mem_export.dccm_bank_dout[i] = dccm_bank_fdout[i][pt.DCCM_DATA_WIDTH-1:0];\n assign mem_export.dccm_bank_ecc[i] = dccm_bank_fdout[i][pt.DCCM_FDATA_WIDTH-1:pt.DCCM_DATA_WIDTH];\n\n el2_ram #(DCCM_INDEX_DEPTH, 39) ram (\n // Primary ports\n .ME(dccm_clken[i]),\n .CLK(clk),\n .WE(dccm_wren_bank[i]),\n .ADR(dccm_addr_bank[i]),\n .D(dccm_wr_fdata_bank[i][pt.DCCM_FDATA_WIDTH-1:0]),\n .Q(dccm_bank_fdout[i][pt.DCCM_FDATA_WIDTH-1:0]),\n .ROP(),\n // These are used by SoC\n .TEST1(dccm_ext_in_pkt[i].TEST1),\n .RME(dccm_ext_in_pkt[i].RME),\n .RM(dccm_ext_in_pkt[i].RM),\n .LS(dccm_ext_in_pkt[i].LS),\n .DS(dccm_ext_in_pkt[i].DS),\n .SD(dccm_ext_in_pkt[i].SD),\n .TEST_RNM(dccm_ext_in_pkt[i].TEST_RNM),\n .BC1(dccm_ext_in_pkt[i].BC1),\n .BC2(dccm_ext_in_pkt[i].BC2),\n .*\n );\n end : gen_dccm_mem\n\n el2_lsu_dccm_mem mem (\n .dccm_mem_export(mem_export.veer_dccm),\n .*\n );\n\nendmodule\n" }, { "path": "verification/block/dccm/test_readwrite.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseTest, MemReadItem, MemWriteItem\n\n# =============================================================================\n\n\nclass ReadWriteSequence(uvm_sequence):\n \"\"\"\n A sequencer that issues a random sequence of writes followed by a\n randomized sequence of reads containing the same addresses previously\n written to.\n \"\"\"\n\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n burst = ConfigDB().get(None, \"\", \"TEST_BURST_LEN\")\n\n awidth = ConfigDB().get(None, \"\", \"DCCM_BITS\")\n dwidth = ConfigDB().get(None, \"\", \"DCCM_FDATA_WIDTH\")\n\n for i in range(count):\n # Randomize unique addresses (aligned)\n addrs = set([random.randrange(0, 1 << awidth) & 0xFFFFFFFC for i in range(burst)])\n\n # Issue writes, randomize data\n for addr in addrs:\n data = random.randrange(0, 1 << dwidth)\n\n item = MemWriteItem(addr, data)\n await self.start_item(item)\n await self.finish_item(item)\n\n # Issue random reads for written addresses\n random.shuffle(list(set(addrs)))\n for addr in addrs:\n item = MemReadItem(addr, data)\n await self.start_item(item)\n await self.finish_item(item)\n\n\n@pyuvm.test()\nclass TestReadWrite(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = ReadWriteSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.mem_seqr)\n" }, { "path": "verification/block/dccm/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport os\n\nimport pyuvm\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, FallingEdge, RisingEdge\nfrom pyuvm import *\n\n# ==============================================================================\n\n\nclass MemWriteItem(uvm_sequence_item):\n \"\"\"\n Memory write item\n \"\"\"\n\n def __init__(self, addr, data):\n super().__init__(\"MemWriteItem\")\n self.addr = addr\n self.data = data\n\n\nclass MemReadItem(uvm_sequence_item):\n \"\"\"\n Memory read item\n \"\"\"\n\n def __init__(self, addr, data=None):\n super().__init__(\"MemReadItem\")\n self.addr = addr\n self.data = data\n\n\n# ==============================================================================\n\n\nclass MemDriver(uvm_driver):\n \"\"\"\n Memory interface driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n # Write\n if isinstance(it, MemWriteItem):\n # Wait for rising edge, do the write\n await RisingEdge(self.dut.clk)\n self.dut.dccm_wren.value = 1\n\n self.dut.dccm_wr_addr_lo.value = it.addr\n self.dut.dccm_wr_data_lo.value = it.data\n\n self.dut.dccm_wr_addr_hi.value = it.addr\n self.dut.dccm_wr_data_hi.value = it.data\n\n # Wait for rising edge, deassert write\n await RisingEdge(self.dut.clk)\n self.dut.dccm_wren.value = 0\n\n # Read\n elif isinstance(it, MemReadItem):\n # Wait for rising edge, do the read\n await RisingEdge(self.dut.clk)\n self.dut.dccm_rden.value = 1\n\n self.dut.dccm_rd_addr_lo.value = it.addr\n self.dut.dccm_rd_addr_hi.value = it.addr\n\n # Wait for rising edge, deassert read\n await RisingEdge(self.dut.clk)\n self.dut.dccm_rden.value = 0\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass MemMonitor(uvm_component):\n \"\"\"\n Memory interface monitor\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Act on rising edges\n await RisingEdge(self.dut.clk)\n\n # Since the driver drives both lo and hi with the same values\n # here we sample only lo\n\n # Write\n if self.dut.dccm_wren.value:\n addr = int(self.dut.dccm_wr_addr_lo)\n data = int(self.dut.dccm_wr_data_lo)\n self.ap.write(MemWriteItem(addr, data))\n\n # Read\n if self.dut.dccm_rden.value:\n addr = int(self.dut.dccm_rd_addr_lo)\n\n # Wait additional clock cycle\n await RisingEdge(self.dut.clk)\n\n data = int(self.dut.dccm_rd_data_lo)\n self.ap.write(MemReadItem(addr, data))\n\n\n# ==============================================================================\n\n\nclass Scoreboard(uvm_component):\n \"\"\"\n A scoreboard that tracks memory writes and compares them agains data read\n from the memory. It also checks if both reads and writes took place\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n self.passed = None\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n did_write = False\n did_read = False\n mem_content = dict()\n\n # Process items\n while self.port.can_get():\n # Get an item\n got_item, item = self.port.try_get()\n assert got_item\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # Memory write\n if isinstance(item, MemWriteItem):\n mem_content[item.addr] = item.data\n did_write = True\n\n self.logger.debug(\"[0x{:08X}] <= 0x{:08X}\".format(item.addr, item.data))\n\n # Memory read\n elif isinstance(item, MemReadItem):\n data = mem_content.get(item.addr, None)\n did_read = True\n\n self.logger.debug(\n \"[0x{:08X}] == 0x{:08X} vs. 0x{:08X} {}\".format(\n item.addr, item.data, data, item.data == data\n )\n )\n\n if data != item.data:\n self.logger.error(\n \"Data mismatch, mem[0x{:08X}] is 0x{:08X}, should be 0x{:08X}\".format(\n item.addr, item.data, data\n )\n )\n self.passed = False\n\n # There were no writes\n if not did_write:\n self.logger.error(\"There were no writes\")\n self.passed = False\n\n # There were no reads\n if not did_read:\n self.logger.error(\"There were no reads\")\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 50)\n ConfigDB().set(None, \"*\", \"TEST_BURST_LEN\", 10)\n\n ConfigDB().set(None, \"*\", \"DCCM_BITS\", 0x10)\n ConfigDB().set(None, \"*\", \"DCCM_FDATA_WIDTH\", 0x20)\n\n # Sequencers\n self.mem_seqr = uvm_sequencer(\"mem_seqr\", self)\n\n # Driver\n self.mem_drv = MemDriver(\"mem_drv\", self, dut=cocotb.top)\n\n # Monitor\n self.mem_mon = MemMonitor(\"mem_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.mem_drv.seq_item_port.connect(self.mem_seqr.seq_item_export)\n self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n self.start_clock(\"active_clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/dcls/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_veer_lockstep_wrapper\nCM_FILE = cm.cfg\n\nEXTRA_VEER_CONFIG = -set lockstep_enable=1 -set lockstep_regfile_enable=1\n\nVERILOG_INCLUDE_DIRS += \\\n\t${RV_ROOT}/testbench \\\n\t${RV_ROOT}/design/include\n\nVERILOG_SOURCES = \\\n\t${SRCDIR}/lib/el2_mem_if.sv \\\n\t${SRCDIR}/lib/el2_regfile_if.sv \\\n\t${SRCDIR}/el2_veer_wrapper.sv \\\n\t${SRCDIR}/el2_mem.sv \\\n\t${SRCDIR}/el2_pic_ctrl.sv \\\n\t${SRCDIR}/el2_veer.sv \\\n\t${SRCDIR}/el2_dma_ctrl.sv \\\n\t${SRCDIR}/el2_pmp.sv \\\n\t${SRCDIR}/ifu/el2_ifu_aln_ctl.sv \\\n\t${SRCDIR}/ifu/el2_ifu_compress_ctl.sv \\\n\t${SRCDIR}/ifu/el2_ifu_ifc_ctl.sv \\\n\t${SRCDIR}/ifu/el2_ifu_bp_ctl.sv \\\n\t${SRCDIR}/ifu/el2_ifu_ic_mem.sv \\\n\t${SRCDIR}/ifu/el2_ifu_mem_ctl.sv \\\n\t${SRCDIR}/ifu/el2_ifu_iccm_mem.sv \\\n\t${SRCDIR}/ifu/el2_ifu.sv \\\n\t${SRCDIR}/dec/el2_dec_decode_ctl.sv \\\n\t${SRCDIR}/dec/el2_dec_gpr_ctl.sv \\\n\t${SRCDIR}/dec/el2_dec_ib_ctl.sv \\\n\t${SRCDIR}/dec/el2_dec_pmp_ctl.sv \\\n\t${SRCDIR}/dec/el2_dec_tlu_ctl.sv \\\n\t${SRCDIR}/dec/el2_dec_trigger.sv \\\n\t${SRCDIR}/dec/el2_dec.sv \\\n\t${SRCDIR}/exu/el2_exu_alu_ctl.sv \\\n\t${SRCDIR}/exu/el2_exu_mul_ctl.sv \\\n\t${SRCDIR}/exu/el2_exu_div_ctl.sv \\\n\t${SRCDIR}/exu/el2_exu.sv \\\n\t${SRCDIR}/lsu/el2_lsu.sv \\\n\t${SRCDIR}/lsu/el2_lsu_clkdomain.sv \\\n\t${SRCDIR}/lsu/el2_lsu_addrcheck.sv \\\n\t${SRCDIR}/lsu/el2_lsu_lsc_ctl.sv \\\n\t${SRCDIR}/lsu/el2_lsu_stbuf.sv \\\n\t${SRCDIR}/lsu/el2_lsu_bus_buffer.sv \\\n\t${SRCDIR}/lsu/el2_lsu_bus_intf.sv \\\n\t${SRCDIR}/lsu/el2_lsu_ecc.sv \\\n\t${SRCDIR}/lsu/el2_lsu_dccm_mem.sv \\\n\t${SRCDIR}/lsu/el2_lsu_dccm_ctl.sv \\\n\t${SRCDIR}/lsu/el2_lsu_trigger.sv \\\n\t${SRCDIR}/dbg/el2_dbg.sv \\\n\t${SRCDIR}/dmi/dmi_mux.v \\\n\t${SRCDIR}/dmi/dmi_wrapper.v \\\n\t${SRCDIR}/dmi/dmi_jtag_to_core_sync.v \\\n\t${SRCDIR}/dmi/rvjtag_tap.v \\\n\t${SRCDIR}/lib/el2_lib.sv \\\n\t$(SRCDIR)/el2_veer_lockstep.sv \\\n\t$(TEST_DIR)/el2_veer_lockstep_wrapper.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/dcls/cm.cfg", "content": "+tree el2_veer_lockstep_wrapper\n-module el2_veer_lockstep_wrapper\n\n////////////////////////////////// MAIN CORE //////////////////////////////////\n///////////////////////////////////////////////////////////////////////////////\n\n//////////////////////////////// rvrangecheck /////////////////////////////////\n// 'start_addr' and 'region' are tied to module parameters\n-node el2_veer_lockstep_wrapper.veer*rangecheck.start_addr\n-node el2_veer_lockstep_wrapper.veer*rangecheck.region\n\n/////////////////////////////////// el2_veer //////////////////////////////////\n-node el2_veer_lockstep_wrapper.veer.trace_rv_i_address_ip[0]\n-node el2_veer_lockstep_wrapper.veer.trace_rv_trace_pkt.trace_rv_i_address_ip[0]\n-node el2_veer_lockstep_wrapper.veer.*hprot[3:1] // Tied to 3'001\n\n/////////////////////////////////// el2_dbg ///////////////////////////////////\n// Tied to '0\n-node el2_veer_lockstep_wrapper.veer.dbg.abstractcs_reg[31:13]\n-node el2_veer_lockstep_wrapper.veer.dbg.abstractcs_reg[11]\n-node el2_veer_lockstep_wrapper.veer.dbg.abstractcs_reg[7:4]\n-node el2_veer_lockstep_wrapper.veer.dbg.dmcontrol_reg[29]\n-node el2_veer_lockstep_wrapper.veer.dbg.dmcontrol_reg[27:2]\n-node el2_veer_lockstep_wrapper.veer.dbg.dmstatus_reg[31:20]\n-node el2_veer_lockstep_wrapper.veer.dbg.dmstatus_reg[15:14]\n-node el2_veer_lockstep_wrapper.veer.dbg.dmstatus_reg[6:4]\n-node el2_veer_lockstep_wrapper.veer.dbg.haltsum0_reg[31:1]\n-node el2_veer_lockstep_wrapper.veer.dbg.sbcs_reg[31:30]\n-node el2_veer_lockstep_wrapper.veer.dbg.sbcs_reg[28:23]\n\n-node el2_veer_lockstep_wrapper.veer.dbg.dmstatus_reg[7] // Tied to '1\n-node el2_veer_lockstep_wrapper.veer.dbg.dmstatus_reg[3:0] // Tied to 4'h2\n-node el2_veer_lockstep_wrapper.veer.dbg.abstractcs_reg[3:0] // Tied to 4'h2\n-node el2_veer_lockstep_wrapper.veer.dbg.sbcs_reg[29] // Tied to '1\n-node el2_veer_lockstep_wrapper.veer.dbg.sbcs_reg[11:5] // Tied to 7'h20\n-node el2_veer_lockstep_wrapper.veer.dbg.sbcs_reg[4:0] // Tied to 5'b01111\n\n/////////////////////////////////// el2_exu ///////////////////////////////////\n-node el2_veer_lockstep_wrapper.veer.exu.i_mul.crc32_poly_rev // Tied to 32'hEDB88320\n-node el2_veer_lockstep_wrapper.veer.exu.i_mul.crc32c_poly_rev // Tied to 32'h82F63B78\n\n///////////////////////////////// dec_tlu_ctl /////////////////////////////////\n// Tied to '0\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.dcsr[14]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.dcsr[9]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.dcsr[5:4]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.dcsr_ns[14]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.dcsr_ns[9]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.dcsr_ns[5:4]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.ifu_mscause[2]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mcgc[6]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mcgc_int[6]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mcgc_ns[6]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mcountinhibit[1]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mepc_rf[0]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mie_rf[31]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mie_rf[27:12]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mie_rf[10:8]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mie_rf[6:4]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mie_rf[2:0]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mip_rf[27:12]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mip_rf[10:8]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mip_rf[6:4]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mip_rf[2:0]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mstatus_rf[31:17]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mstatus_rf[15:12]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mstatus_rf[10:8]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mstatus_rf[6:4]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mstatus_rf[2:0]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mtdata1_tsel_out[26]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mtdata1_tsel_out[18:13]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mtdata1_tsel_out[10:8]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mtdata1_tsel_out[5:3]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.mtvec_rf[1]\n\n/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////\n// Tied to '0\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.pmp.*pmpcfg_ff.din[6:5]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.pmp.*pmpcfg_ff.dout[6:5]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.pmp.*csr_wdata[6:5]\n\n// Aggregation of four 'el2_pmp_cfg_pkt_t' entries\n// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[30:29]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[22:21]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[14:13]\n-node el2_veer_lockstep_wrapper.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[6:5]\n\n////////////////////////////////// LOCKSTEP ///////////////////////////////////\n///////////////////////////////////////////////////////////////////////////////\n\n//////////////////////////////// rvrangecheck /////////////////////////////////\n// 'start_addr' and 'region' are tied to module parameters\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core*rangecheck.start_addr\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core*rangecheck.region\n\n////////////////////////////// el2_veer_lockstep //////////////////////////////\n-node el2_veer_lockstep_wrapper.lockstep.trace_rv_i_address_ip[0]\n-node el2_veer_lockstep_wrapper.lockstep.*trace_rv_i_address_ip[0]\n\n/////////////////////////////////// el2_veer //////////////////////////////////\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.trace_rv_i_address_ip[0]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.trace_rv_trace_pkt.trace_rv_i_address_ip[0]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.*hprot[3:1] // Tied to 3'001\n\n/////////////////////////////////// el2_dbg ///////////////////////////////////\n// Tied to '0\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.abstractcs_reg[31:13]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.abstractcs_reg[11]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.abstractcs_reg[7:4]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.dmcontrol_reg[29]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.dmcontrol_reg[27:2]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.dmstatus_reg[31:20]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.dmstatus_reg[15:14]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.dmstatus_reg[6:4]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.haltsum0_reg[31:1]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.sbcs_reg[31:30]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.sbcs_reg[28:23]\n\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.dmstatus_reg[7] // Tied to '1\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.dmstatus_reg[3:0] // Tied to 4'h2\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.abstractcs_reg[3:0] // Tied to 4'h2\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.sbcs_reg[29] // Tied to '1\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.sbcs_reg[11:5] // Tied to 7'h20\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dbg.sbcs_reg[4:0] // Tied to 5'b01111\n\n/////////////////////////////////// el2_exu ///////////////////////////////////\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.exu.i_mul.crc32_poly_rev // Tied to 32'hEDB88320\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.exu.i_mul.crc32c_poly_rev // Tied to 32'h82F63B78\n\n///////////////////////////////// dec_tlu_ctl /////////////////////////////////\n// Tied to '0\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.dcsr[14]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.dcsr[9]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.dcsr[5:4]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.dcsr_ns[14]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.dcsr_ns[9]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.dcsr_ns[5:4]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.ifu_mscause[2]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mcgc[6]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mcgc_int[6]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mcgc_ns[6]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mcountinhibit[1]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mepc_rf[0]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mie_rf[31]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mie_rf[27:12]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mie_rf[10:8]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mie_rf[6:4]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mie_rf[2:0]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mip_rf[27:12]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mip_rf[10:8]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mip_rf[6:4]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mip_rf[2:0]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mstatus_rf[31:17]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mstatus_rf[15:12]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mstatus_rf[10:8]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mstatus_rf[6:4]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mstatus_rf[2:0]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[26]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[18:13]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[10:8]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[5:3]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.mtvec_rf[1]\n\n/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////\n// Tied to '0\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.pmp.*pmpcfg_ff.din[6:5]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.pmp.*pmpcfg_ff.dout[6:5]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.pmp.*csr_wdata[6:5]\n\n// Aggregation of four 'el2_pmp_cfg_pkt_t' entries\n// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[30:29]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[22:21]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[14:13]\n-node el2_veer_lockstep_wrapper.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[6:5]\n" }, { "path": "verification/block/dcls/el2_veer_lockstep_wrapper.sv", "content": "// Copyright (c) 2024 Antmicro \n// SPDX-License-Identifier: Apache-2.0\n\nmodule el2_veer_lockstep_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n input logic clk,\n input logic rst_l,\n input logic dbg_rst_l,\n\n output logic shadow_reset,\n output logic shadow_dbg_reset,\n\n // Shadow Core control\n input logic disable_corruption_detection_i,\n input logic lockstep_err_injection_en_i,\n\n // Equivalency Checker\n output logic corruption_detected_o\n);\n logic core_rst_l; // This is \"rst_l | dbg_rst_l\"\n\n logic [31:1] rst_vec;\n logic [31:1] nmi_vec;\n\n logic nmi_int;\n logic timer_int;\n logic soft_int;\n\n logic [pt.PIC_TOTAL_INT:1] extintsrc_req;\n\n logic active_l2clk;\n logic free_l2clk;\n\n logic [31:0] trace_rv_i_insn_ip;\n logic [31:0] trace_rv_i_address_ip;\n logic trace_rv_i_valid_ip;\n logic trace_rv_i_exception_ip;\n logic [ 4:0] trace_rv_i_ecause_ip;\n logic trace_rv_i_interrupt_ip;\n logic [31:0] trace_rv_i_tval_ip;\n\n\n logic dccm_clk_override;\n logic icm_clk_override;\n logic dec_tlu_core_ecc_disable;\n\n // external halt/run interface\n logic i_cpu_halt_req; // Asynchronous Halt request to CPU\n logic i_cpu_run_req; // Asynchronous Restart request to CPU\n logic o_cpu_halt_ack; // Core Acknowledge to Halt request\n logic o_cpu_halt_status; // 1'b1 indicates processor is halted\n logic o_cpu_run_ack; // Core Acknowledge to run request\n logic o_debug_mode_status; // Core to the PMU that core is in debug mode. When core is in debug mode; the PMU should refrain from sendng a halt or run request\n\n logic [31:4] core_id; // CORE ID\n\n // external MPC halt/run interface\n logic mpc_debug_halt_req; // Async halt request\n logic mpc_debug_run_req; // Async run request\n logic mpc_reset_run_req; // Run/halt after reset\n logic mpc_debug_halt_ack; // Halt ack\n logic mpc_debug_run_ack; // Run ack\n logic debug_brkpt_status; // debug breakpoint\n\n logic dec_tlu_perfcnt0; // toggles when slot0 perf counter 0 has an event inc\n logic dec_tlu_perfcnt1;\n logic dec_tlu_perfcnt2;\n logic dec_tlu_perfcnt3;\n\n // DCCM ports\n logic dccm_wren;\n logic dccm_rden;\n logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_lo;\n logic [ pt.DCCM_BITS-1:0] dccm_wr_addr_hi;\n logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_lo;\n logic [ pt.DCCM_BITS-1:0] dccm_rd_addr_hi;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi;\n\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;\n logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;\n\n // ICCM ports\n logic [pt.ICCM_BITS-1:1] iccm_rw_addr;\n logic iccm_wren;\n logic iccm_rden;\n logic [ 2:0] iccm_wr_size;\n logic [ 77:0] iccm_wr_data;\n logic iccm_buf_correct_ecc;\n logic iccm_correction_state;\n\n logic [63:0] iccm_rd_data;\n logic [77:0] iccm_rd_data_ecc;\n\n // ICache ; ITAG ports\n logic [ 31:1] ic_rw_addr;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid;\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en;\n logic ic_rd_en;\n\n logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data; // Data to fill to the Icache. With ECC\n logic [ 63:0] ic_rd_data ; // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n logic [ 70:0] ic_debug_rd_data ; // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n logic [ 25:0] ictag_debug_rd_data;// Debug icache tag.\n logic [ 70:0] ic_debug_wr_data; // Debug wr cache.\n\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;\n logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;\n logic [ 63:0] ic_premux_data; // Premux data to be muxed with each way of the Icache.\n logic ic_sel_premux_data; // Select premux data\n\n\n logic [ pt.ICACHE_INDEX_HI:3] ic_debug_addr; // Read/Write addresss to the Icache.\n logic ic_debug_rd_en; // Icache debug rd\n logic ic_debug_wr_en; // Icache debug wr\n logic ic_debug_tag_array; // Debug tag array\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way; // Debug way. Rd or Wr.\n\n\n\n logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit;\n logic ic_tag_perr; // Icache Tag parity error\n\n //-------------------------- LSU AXI signals--------------------------\n // AXI Write Channels\n logic lsu_axi_awvalid;\n logic lsu_axi_awready;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;\n logic [ 31:0] lsu_axi_awaddr;\n logic [ 3:0] lsu_axi_awregion;\n logic [ 7:0] lsu_axi_awlen;\n logic [ 2:0] lsu_axi_awsize;\n logic [ 1:0] lsu_axi_awburst;\n logic lsu_axi_awlock;\n logic [ 3:0] lsu_axi_awcache;\n logic [ 2:0] lsu_axi_awprot;\n logic [ 3:0] lsu_axi_awqos;\n\n logic lsu_axi_wvalid;\n logic lsu_axi_wready;\n logic [63:0] lsu_axi_wdata;\n logic [ 7:0] lsu_axi_wstrb;\n logic lsu_axi_wlast;\n\n logic lsu_axi_bvalid;\n logic lsu_axi_bready;\n logic [ 1:0] lsu_axi_bresp;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;\n\n // AXI Read Channels\n logic lsu_axi_arvalid;\n logic lsu_axi_arready;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;\n logic [ 31:0] lsu_axi_araddr;\n logic [ 3:0] lsu_axi_arregion;\n logic [ 7:0] lsu_axi_arlen;\n logic [ 2:0] lsu_axi_arsize;\n logic [ 1:0] lsu_axi_arburst;\n logic lsu_axi_arlock;\n logic [ 3:0] lsu_axi_arcache;\n logic [ 2:0] lsu_axi_arprot;\n logic [ 3:0] lsu_axi_arqos;\n\n logic lsu_axi_rvalid;\n logic lsu_axi_rready;\n logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;\n logic [ 63:0] lsu_axi_rdata;\n logic [ 1:0] lsu_axi_rresp;\n logic lsu_axi_rlast;\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n logic ifu_axi_awvalid;\n logic ifu_axi_awready;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;\n logic [ 31:0] ifu_axi_awaddr;\n logic [ 3:0] ifu_axi_awregion;\n logic [ 7:0] ifu_axi_awlen;\n logic [ 2:0] ifu_axi_awsize;\n logic [ 1:0] ifu_axi_awburst;\n logic ifu_axi_awlock;\n logic [ 3:0] ifu_axi_awcache;\n logic [ 2:0] ifu_axi_awprot;\n logic [ 3:0] ifu_axi_awqos;\n\n logic ifu_axi_wvalid;\n logic ifu_axi_wready;\n logic [63:0] ifu_axi_wdata;\n logic [ 7:0] ifu_axi_wstrb;\n logic ifu_axi_wlast;\n\n logic ifu_axi_bvalid;\n logic ifu_axi_bready;\n logic [ 1:0] ifu_axi_bresp;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid;\n\n // AXI Read Channels\n logic ifu_axi_arvalid;\n logic ifu_axi_arready;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid;\n logic [ 31:0] ifu_axi_araddr;\n logic [ 3:0] ifu_axi_arregion;\n logic [ 7:0] ifu_axi_arlen;\n logic [ 2:0] ifu_axi_arsize;\n logic [ 1:0] ifu_axi_arburst;\n logic ifu_axi_arlock;\n logic [ 3:0] ifu_axi_arcache;\n logic [ 2:0] ifu_axi_arprot;\n logic [ 3:0] ifu_axi_arqos;\n\n logic ifu_axi_rvalid;\n logic ifu_axi_rready;\n logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid;\n logic [ 63:0] ifu_axi_rdata;\n logic [ 1:0] ifu_axi_rresp;\n logic ifu_axi_rlast;\n\n //-------------------------- SB AXI signals--------------------------\n // AXI Write Channels\n logic sb_axi_awvalid;\n logic sb_axi_awready;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_awid;\n logic [ 31:0] sb_axi_awaddr;\n logic [ 3:0] sb_axi_awregion;\n logic [ 7:0] sb_axi_awlen;\n logic [ 2:0] sb_axi_awsize;\n logic [ 1:0] sb_axi_awburst;\n logic sb_axi_awlock;\n logic [ 3:0] sb_axi_awcache;\n logic [ 2:0] sb_axi_awprot;\n logic [ 3:0] sb_axi_awqos;\n\n logic sb_axi_wvalid;\n logic sb_axi_wready;\n logic [63:0] sb_axi_wdata;\n logic [ 7:0] sb_axi_wstrb;\n logic sb_axi_wlast;\n\n logic sb_axi_bvalid;\n logic sb_axi_bready;\n logic [ 1:0] sb_axi_bresp;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_bid;\n\n // AXI Read Channels\n logic sb_axi_arvalid;\n logic sb_axi_arready;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_arid;\n logic [ 31:0] sb_axi_araddr;\n logic [ 3:0] sb_axi_arregion;\n logic [ 7:0] sb_axi_arlen;\n logic [ 2:0] sb_axi_arsize;\n logic [ 1:0] sb_axi_arburst;\n logic sb_axi_arlock;\n logic [ 3:0] sb_axi_arcache;\n logic [ 2:0] sb_axi_arprot;\n logic [ 3:0] sb_axi_arqos;\n\n logic sb_axi_rvalid;\n logic sb_axi_rready;\n logic [pt.SB_BUS_TAG-1:0] sb_axi_rid;\n logic [ 63:0] sb_axi_rdata;\n logic [ 1:0] sb_axi_rresp;\n logic sb_axi_rlast;\n\n //-------------------------- DMA AXI signals--------------------------\n // AXI Write Channels\n logic dma_axi_awvalid;\n logic dma_axi_awready;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid;\n logic [ 31:0] dma_axi_awaddr;\n logic [ 2:0] dma_axi_awsize;\n logic [ 2:0] dma_axi_awprot;\n logic [ 7:0] dma_axi_awlen;\n logic [ 1:0] dma_axi_awburst;\n\n\n logic dma_axi_wvalid;\n logic dma_axi_wready;\n logic [63:0] dma_axi_wdata;\n logic [ 7:0] dma_axi_wstrb;\n logic dma_axi_wlast;\n\n logic dma_axi_bvalid;\n logic dma_axi_bready;\n logic [ 1:0] dma_axi_bresp;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid;\n\n // AXI Read Channels\n logic dma_axi_arvalid;\n logic dma_axi_arready;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid;\n logic [ 31:0] dma_axi_araddr;\n logic [ 2:0] dma_axi_arsize;\n logic [ 2:0] dma_axi_arprot;\n logic [ 7:0] dma_axi_arlen;\n logic [ 1:0] dma_axi_arburst;\n\n logic dma_axi_rvalid;\n logic dma_axi_rready;\n logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid;\n logic [ 63:0] dma_axi_rdata;\n logic [ 1:0] dma_axi_rresp;\n logic dma_axi_rlast;\n\n\n //// AHB LITE BUS\n logic [31:0] haddr;\n logic [ 2:0] hburst;\n logic hmastlock;\n logic [ 3:0] hprot;\n logic [ 2:0] hsize;\n logic [ 1:0] htrans;\n logic hwrite;\n\n logic [63:0] hrdata;\n logic hready;\n logic hresp;\n\n // LSU AHB Master\n logic [31:0] lsu_haddr;\n logic [ 2:0] lsu_hburst;\n logic lsu_hmastlock;\n logic [ 3:0] lsu_hprot;\n logic [ 2:0] lsu_hsize;\n logic [ 1:0] lsu_htrans;\n logic lsu_hwrite;\n logic [63:0] lsu_hwdata;\n\n logic [63:0] lsu_hrdata;\n logic lsu_hready;\n logic lsu_hresp;\n\n //System Bus Debug Master\n logic [31:0] sb_haddr;\n logic [ 2:0] sb_hburst;\n logic sb_hmastlock;\n logic [ 3:0] sb_hprot;\n logic [ 2:0] sb_hsize;\n logic [ 1:0] sb_htrans;\n logic sb_hwrite;\n logic [63:0] sb_hwdata;\n\n logic [63:0] sb_hrdata;\n logic sb_hready;\n logic sb_hresp;\n\n // DMA Slave\n logic dma_hsel;\n logic [31:0] dma_haddr;\n logic [ 2:0] dma_hburst;\n logic dma_hmastlock;\n logic [ 3:0] dma_hprot;\n logic [ 2:0] dma_hsize;\n logic [ 1:0] dma_htrans;\n logic dma_hwrite;\n logic [63:0] dma_hwdata;\n logic dma_hreadyin;\n\n logic [63:0] dma_hrdata;\n logic dma_hreadyout;\n logic dma_hresp;\n\n logic lsu_bus_clk_en;\n logic ifu_bus_clk_en;\n logic dbg_bus_clk_en;\n logic dma_bus_clk_en;\n\n logic dmi_reg_en; // read or write\n logic [ 6:0] dmi_reg_addr; // address of DM register\n logic dmi_reg_wr_en; // write instruction\n logic [31:0] dmi_reg_wdata; // write data\n logic [31:0] dmi_reg_rdata;\n\n // ICCM/DCCM ECC status\n logic iccm_ecc_single_error;\n logic iccm_ecc_double_error;\n logic dccm_ecc_single_error;\n logic dccm_ecc_double_error;\n\n logic scan_mode;\n\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n el2_regfile_if regfile ();\n`endif // `ifdef RV_LOCKSTEP_REGFILE_ENABLE\n\n el2_veer #(.pt(pt)) veer (\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .regfile(regfile.veer_rf_src),\n`endif // `ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .*\n );\n\n el2_veer_lockstep #(.pt(pt)) lockstep (\n`ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .main_core_regfile(regfile.veer_rf_sink),\n`endif // `ifdef RV_LOCKSTEP_REGFILE_ENABLE\n .*\n );\n\n assign shadow_reset = lockstep.rst_shadow;\n assign shadow_dbg_reset = lockstep.rst_dbg_shadow;\nendmodule\n" }, { "path": "verification/block/dcls/test_lockstep.py", "content": "# Copyright (c) 2024 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nfrom random import randrange\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles, ReadOnly, RisingEdge\nfrom cocotb.utils import get_sim_time\nfrom pyuvm import ConfigDB\nfrom testbench import BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestReset(BaseTest):\n \"\"\"\n A basic test that resets the DUT and ensures shadow core gets out of reset\n after the configured delay\n \"\"\"\n\n def assert_signals(self, signals):\n time = get_sim_time(units=\"ns\")\n self.logger.info(f\"Validating signals at {time}\")\n for name, value in signals.items():\n try:\n sig = getattr(self.dut, name)\n except AttributeError:\n print(f\"DUT does not contain signal named {name}\")\n exit(1)\n self.logger.info(f\"Assert that {name}={value}\")\n assert sig.value == value\n\n async def test_reset(self):\n lockstep_delay = ConfigDB().get(None, \"\", \"LOCKSTEP_DELAY\")\n signals = {\n \"shadow_reset\": 0,\n \"shadow_dbg_reset\": 0,\n \"corruption_detected_o\": 0,\n }\n # The shadow core should go into the reset regardless of the delay\n for _ in range(lockstep_delay):\n await ReadOnly()\n self.assert_signals(signals)\n await RisingEdge(self.clk)\n\n # After the delay shadow core should be out of reset without corruption detected\n signals.update({\"shadow_reset\": 1, \"shadow_dbg_reset\": 1})\n await ReadOnly()\n self.assert_signals(signals)\n await RisingEdge(self.clk)\n\n async def run(self):\n await self.test_reset()\n\n\n@pyuvm.test()\nclass TestErrorInjection(TestReset):\n \"\"\"\n A test that ensures the Shadow Core reports a corruption after enabling an error injection.\n \"\"\"\n\n async def run(self):\n # Get out of reset\n await self.test_reset()\n\n # Await few cycles (arbitrary number)\n await ClockCycles(self.clk, 10)\n\n # Enable error injection\n self.dut.lockstep_err_injection_en_i.value = 1\n await RisingEdge(self.clk)\n\n # Assert that an error is detected\n signals = {\n \"shadow_reset\": 1,\n \"shadow_dbg_reset\": 1,\n \"corruption_detected_o\": 1,\n }\n self.assert_signals(signals)\n\n # Disable the Shadow Core\n self.dut.disable_corruption_detection_i.value = 1\n await RisingEdge(self.clk)\n\n # Assert that an error is not detected\n signals.update({\"corruption_detected_o\": 0})\n self.assert_signals(signals)\n" }, { "path": "verification/block/dcls/testbench.py", "content": "# Copyright (c) 2024 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport logging\nimport os\n\nimport cocotb\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, FallingEdge, RisingEdge\nfrom pyuvm import ConfigDB, uvm_env, uvm_report_object, uvm_test\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"LOCKSTEP_DELAY\", 3)\n\n def connect_phase(self):\n pass\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n self.dut = cocotb.top\n self.clk = self.dut.clk\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(self.dut, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n self.dut.rst_l.value = 0\n self.dut.dbg_rst_l.value = 0\n await ClockCycles(self.dut.clk, 2)\n await FallingEdge(self.dut.clk)\n self.dut.rst_l.value = 1\n self.dut.dbg_rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n await RisingEdge(self.clk)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(self.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/dec/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_dec_wrapper\nDEC_TEST := 1\nCM_FILE = cm.cfg\n\nEXTRA_ARGS = -I$(SRCDIR)/include/\n\nVERILOG_SOURCES = \\\n $(TEST_DIR)/el2_dec_wrapper.sv \\\n $(SRCDIR)/dec/el2_dec.sv \\\n $(SRCDIR)/dec/el2_dec_decode_ctl.sv \\\n $(SRCDIR)/dec/el2_dec_gpr_ctl.sv \\\n $(SRCDIR)/dec/el2_dec_ib_ctl.sv \\\n $(SRCDIR)/dec/el2_dec_pmp_ctl.sv \\\n $(SRCDIR)/dec/el2_dec_tlu_ctl.sv \\\n $(SRCDIR)/dec/el2_dec_trigger.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/dec/cm.cfg", "content": "+tree el2_dec_wrapper.dut\n\n///////////////////////////////// dec_tlu_ctl /////////////////////////////////\n// Tied to '0\n-node el2_dec_wrapper.dut.tlu.dcsr[14]\n-node el2_dec_wrapper.dut.tlu.dcsr[9]\n-node el2_dec_wrapper.dut.tlu.dcsr[5:4]\n-node el2_dec_wrapper.dut.tlu.dcsr_ns[14]\n-node el2_dec_wrapper.dut.tlu.dcsr_ns[9]\n-node el2_dec_wrapper.dut.tlu.dcsr_ns[5:4]\n-node el2_dec_wrapper.dut.tlu.ifu_mscause[2]\n-node el2_dec_wrapper.dut.tlu.mcgc[6]\n-node el2_dec_wrapper.dut.tlu.mcgc_int[6]\n-node el2_dec_wrapper.dut.tlu.mcgc_ns[6]\n-node el2_dec_wrapper.dut.tlu.mcountinhibit[1]\n-node el2_dec_wrapper.dut.tlu.mepc_rf[0]\n-node el2_dec_wrapper.dut.tlu.mie_rf[31]\n-node el2_dec_wrapper.dut.tlu.mie_rf[27:12]\n-node el2_dec_wrapper.dut.tlu.mie_rf[10:8]\n-node el2_dec_wrapper.dut.tlu.mie_rf[6:4]\n-node el2_dec_wrapper.dut.tlu.mie_rf[2:0]\n-node el2_dec_wrapper.dut.tlu.mip_rf[27:12]\n-node el2_dec_wrapper.dut.tlu.mip_rf[10:8]\n-node el2_dec_wrapper.dut.tlu.mip_rf[6:4]\n-node el2_dec_wrapper.dut.tlu.mip_rf[2:0]\n-node el2_dec_wrapper.dut.tlu.mstatus_rf[31:17]\n-node el2_dec_wrapper.dut.tlu.mstatus_rf[15:12]\n-node el2_dec_wrapper.dut.tlu.mstatus_rf[10:8]\n-node el2_dec_wrapper.dut.tlu.mstatus_rf[6:4]\n-node el2_dec_wrapper.dut.tlu.mstatus_rf[2:0]\n-node el2_dec_wrapper.dut.tlu.mtdata1_tsel_out[26]\n-node el2_dec_wrapper.dut.tlu.mtdata1_tsel_out[18:13]\n-node el2_dec_wrapper.dut.tlu.mtdata1_tsel_out[10:8]\n-node el2_dec_wrapper.dut.tlu.mtdata1_tsel_out[5:3]\n-node el2_dec_wrapper.dut.tlu.mtvec_rf[1]\n\n/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////\n// Tied to '0\n-node el2_dec_wrapper.dut.tlu.pmp.*pmpcfg_ff.din[6:5]\n-node el2_dec_wrapper.dut.tlu.pmp.*pmpcfg_ff.dout[6:5]\n-node el2_dec_wrapper.dut.tlu.pmp.*csr_wdata[6:5]\n\n// Aggregation of four 'el2_pmp_cfg_pkt_t' entries\n// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0\n-node el2_dec_wrapper.dut.tlu.pmp.pmp_pmpcfg_rddata[30:29]\n-node el2_dec_wrapper.dut.tlu.pmp.pmp_pmpcfg_rddata[22:21]\n-node el2_dec_wrapper.dut.tlu.pmp.pmp_pmpcfg_rddata[14:13]\n-node el2_dec_wrapper.dut.tlu.pmp.pmp_pmpcfg_rddata[6:5]\n" }, { "path": "verification/block/dec/el2_dec_wrapper.sv", "content": "module el2_dec_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic free_clk, // Clock always. Through two clock headers. For flops without second clock header built in.\n input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.\n\n input logic lsu_fastint_stall_any, // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle\n\n output logic dec_extint_stall, // Stall on external interrupt\n\n output logic dec_i0_decode_d, // Valid instruction at D-stage and not blocked\n output logic dec_pause_state_cg, // to top for active state clock gating\n\n output logic dec_tlu_core_empty,\n\n input logic rst_l, // reset, active low\n // rst_vec is supposed to be connected to a constant in the top level\n /*pragma coverage off*/\n input logic [31:1] rst_vec, // reset vector, from core pins\n /*pragma coverage on*/\n\n input logic nmi_int, // NMI pin\n // nmi_vec is supposed to be connected to a constant in the top level\n /*pragma coverage off*/\n input logic [31:1] nmi_vec, // NMI vector, from pins\n /*pragma coverage on*/\n\n input logic i_cpu_halt_req, // Asynchronous Halt request to CPU\n input logic i_cpu_run_req, // Asynchronous Restart request to CPU\n\n output logic o_cpu_halt_status, // Halt status of core (pmu/fw)\n output logic o_cpu_halt_ack, // Halt request ack\n output logic o_cpu_run_ack, // Run request ack\n output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request\n\n /*pragma coverage off*/\n input logic [31:4] core_id, // CORE ID\n /*pragma coverage on*/\n\n // external MPC halt/run interface\n input logic mpc_debug_halt_req, // Async halt request\n input logic mpc_debug_run_req, // Async run request\n input logic mpc_reset_run_req, // Run/halt after reset\n output logic mpc_debug_halt_ack, // Halt ack\n output logic mpc_debug_run_ack, // Run ack\n output logic debug_brkpt_status, // debug breakpoint\n\n input logic exu_pmu_i0_br_misp, // slot 0 branch misp\n input logic exu_pmu_i0_br_ataken, // slot 0 branch actual taken\n input logic exu_pmu_i0_pc4, // slot 0 4 byte branch\n\n\n input logic lsu_nonblock_load_valid_m, // valid nonblock load at m\n input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag\n input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r\n input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag\n input logic lsu_nonblock_load_data_valid, // valid nonblock load data back\n input logic lsu_nonblock_load_data_error, // nonblock load bus error\n input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag\n input logic [31:0] lsu_nonblock_load_data, // nonblock load data\n\n input logic lsu_pmu_bus_trxn, // D side bus transaction\n input logic lsu_pmu_bus_misaligned, // D side bus misaligned\n input logic lsu_pmu_bus_error, // D side bus error\n input logic lsu_pmu_bus_busy, // D side bus busy\n input logic lsu_pmu_misaligned_m, // D side load or store misaligned\n input logic lsu_pmu_load_external_m, // D side bus load\n input logic lsu_pmu_store_external_m, // D side bus store\n input logic dma_pmu_dccm_read, // DMA DCCM read\n input logic dma_pmu_dccm_write, // DMA DCCM write\n input logic dma_pmu_any_read, // DMA read\n input logic dma_pmu_any_write, // DMA write\n\n input logic [31:1] lsu_fir_addr, // Fast int address\n input logic [ 1:0] lsu_fir_error, // Fast int lookup error\n\n input logic ifu_pmu_instr_aligned, // aligned instructions\n input logic ifu_pmu_fetch_stall, // fetch unit stalled\n input logic ifu_pmu_ic_miss, // icache miss\n input logic ifu_pmu_ic_hit, // icache hit\n input logic ifu_pmu_bus_error, // Instruction side bus error\n input logic ifu_pmu_bus_busy, // Instruction side bus busy\n input logic ifu_pmu_bus_trxn, // Instruction side bus transaction\n\n input logic ifu_ic_error_start, // IC single bit error\n input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error\n\n input logic [ 3:0] lsu_trigger_match_m,\n input logic dbg_cmd_valid, // debugger abstract command valid\n input logic dbg_cmd_write, // command is a write\n input logic [ 1:0] dbg_cmd_type, // command type\n input logic [31:0] dbg_cmd_addr, // command address\n input logic [ 1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i\n\n\n input logic ifu_i0_icaf, // icache access fault\n input logic [1:0] ifu_i0_icaf_type, // icache access fault type\n\n input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst\n input logic ifu_i0_dbecc, // icache/iccm double-bit error\n\n input logic lsu_idle_any, // lsu idle for halting\n\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index\n input logic [ pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR\n input logic [ pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag\n input logic [ $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index\n\n input logic lsu_single_ecc_error_incr, // LSU inc SB error counter\n\n input logic lsu_imprecise_error_load_any, // LSU imprecise load bus error\n input logic lsu_imprecise_error_store_any, // LSU imprecise store bus error\n input logic [31:0] lsu_imprecise_error_addr_any, // LSU imprecise bus error address\n\n input logic [31:0] exu_div_result, // final div result\n input logic exu_div_wren, // Divide write enable to GPR\n\n input logic [31:0] exu_csr_rs1_x, // rs1 for csr instruction\n\n input logic [31:0] lsu_result_m, // load result\n input logic [31:0] lsu_result_corr_r, // load result - corrected load data\n\n input logic lsu_load_stall_any, // This is for blocking loads\n input logic lsu_store_stall_any, // This is for blocking stores\n input logic dma_dccm_stall_any, // stall any load/store at decode, pmu event\n input logic dma_iccm_stall_any, // iccm stalled, pmu event\n\n input logic iccm_dma_sb_error, // ICCM DMA single bit error\n\n input logic exu_flush_final, // slot0 flush\n\n input logic [31:1] exu_npc_r, // next PC\n\n input logic [31:0] exu_i0_result_x, // alu result x\n\n\n input logic ifu_i0_valid, // fetch valids to instruction buffer\n input logic [31:0] ifu_i0_instr, // fetch inst's to instruction buffer\n input logic [31:1] ifu_i0_pc, // pc's for instruction buffer\n input logic ifu_i0_pc4, // indication of 4B or 2B for corresponding inst\n input logic [31:1] exu_i0_pc_x, // pc's for e1 from the alu's\n\n input logic mexintpend, // External interrupt pending\n input logic timer_int, // Timer interrupt pending (from pin)\n input logic soft_int, // Software interrupt pending (from pin)\n\n input logic [7:0] pic_claimid, // PIC claimid\n input logic [3:0] pic_pl, // PIC priv level\n input logic mhwakeup, // High priority wakeup\n\n output logic [3:0] dec_tlu_meicurpl, // to PIC, Current priv level\n output logic [3:0] dec_tlu_meipt, // to PIC\n\n input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data\n input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid\n output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics\n\n\n // Debug start\n input logic dbg_halt_req, // DM requests a halt\n input logic dbg_resume_req, // DM requests a resume\n input logic ifu_miss_state_idle, // I-side miss buffer empty\n\n output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command\n output logic dec_tlu_debug_mode, // Core is in debug mode\n output logic dec_tlu_resume_ack, // Resume acknowledge\n output logic dec_tlu_flush_noredir_r, // Tell fetch to idle on this flush\n output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC\n output logic dec_tlu_flush_leak_one_r, // single step\n output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc\n output logic [31:2] dec_tlu_meihap, // Fast ext int base\n\n output logic dec_debug_wdata_rs1_d, // insert debug write data into rs1 at decode\n\n output logic [31:0] dec_dbg_rddata, // debug command read data\n\n output logic dec_dbg_cmd_done, // abstract command is done\n output logic dec_dbg_cmd_fail, // abstract command failed (illegal reg address)\n\n // el2_trigger_pkt_t broken down to allow driving from cocotb by both SIMs\n // info needed by debug trigger blocks\n output logic [3:0] trigger_pkt_any_select,\n output logic [3:0] trigger_pkt_any_match,\n output logic [3:0] trigger_pkt_any_store,\n output logic [3:0] trigger_pkt_any_load,\n output logic [3:0] trigger_pkt_any_execute,\n output logic [3:0] trigger_pkt_any_m,\n output logic [3:0][31:0] trigger_pkt_any_tdata2,\n\n output logic dec_tlu_force_halt, // halt has been forced\n // Debug end\n // branch info from pipe0 for errors or counter updates\n input logic [1:0] exu_i0_br_hist_r, // history\n input logic exu_i0_br_error_r, // error\n input logic exu_i0_br_start_error_r, // start error\n input logic exu_i0_br_valid_r, // valid\n input logic exu_i0_br_mp_r, // mispredict\n input logic exu_i0_br_middle_r, // middle of bank\n\n // branch info from pipe1 for errors or counter updates\n\n input logic exu_i0_br_way_r, // way hit or repl\n\n output logic dec_i0_rs1_en_d, // Qualify GPR RS1 data\n output logic dec_i0_rs2_en_d, // Qualify GPR RS2 data\n output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data\n output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data\n\n output logic [31:0] dec_i0_immed_d, // immediate data\n output logic [12:1] dec_i0_br_immed_d, // br immediate data\n\n output el2_alu_pkt_t i0_ap, // alu packet\n\n output logic dec_i0_alu_decode_d, // schedule on D-stage alu\n output logic dec_i0_branch_d, // Branch in D-stage\n\n output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's\n\n output logic [31:1] dec_i0_pc_d, // pc's at decode\n output logic [ 3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable\n output logic [ 3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable\n\n output logic [31:0] dec_i0_result_r, // Result R-stage\n\n output el2_lsu_pkt_t lsu_p, // lsu packet\n output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands\n output el2_mul_pkt_t mul_p, // mul packet\n output el2_div_pkt_t div_p, // div packet\n output logic dec_div_cancel, // cancel divide operation\n\n output logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses\n\n output logic dec_csr_ren_d, // CSR read enable\n output logic [31:0] dec_csr_rddata_d, // CSR read data\n\n output logic dec_tlu_flush_lower_r, // tlu flush due to late mp, exception, rfpc, or int\n output logic dec_tlu_flush_lower_wb,\n output logic [31:1] dec_tlu_flush_path_r, // tlu flush target\n output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state\n output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache\n\n output logic [31:1] pred_correct_npc_x, // npc if prediction is correct at e2 stage\n\n output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot 0 branch predictor update packet\n\n output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc\n output logic dec_tlu_perfcnt1, // toggles when slot0 perf counter 1 has an event inc\n output logic dec_tlu_perfcnt2, // toggles when slot0 perf counter 2 has an event inc\n output logic dec_tlu_perfcnt3, // toggles when slot0 perf counter 3 has an event inc\n\n output el2_predict_pkt_t dec_i0_predict_p_d, // prediction packet to alus\n output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index\n output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag\n\n output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index\n\n output logic dec_lsu_valid_raw_d,\n\n output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control\n\n output logic [1:0] dec_data_en, // clock-gate control logic\n output logic [1:0] dec_ctl_en,\n\n input logic [15:0] ifu_i0_cinst, // 16b compressed instruction\n\n output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet\n\n // PMP signals\n output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],\n output logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],\n\n`ifdef RV_USER_MODE\n\n // Privilege mode\n output logic priv_mode,\n output logic priv_mode_eff,\n output logic priv_mode_ns,\n\n // mseccfg CSR content for PMP\n output el2_mseccfg_pkt_t mseccfg,\n\n`endif\n\n // feature disable from mfdc\n output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding\n output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address\n output logic dec_tlu_core_ecc_disable, // disable core ECC\n output logic dec_tlu_bpred_disable, // disable branch prediction\n output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing\n output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16]\n\n // clock gating overrides from mcgc\n output logic dec_tlu_misc_clk_override, // override misc clock domain gating\n output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating\n output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating\n output logic dec_tlu_bus_clk_override, // override bus clock domain gating\n output logic dec_tlu_pic_clk_override, // override PIC clock domain gating\n output logic dec_tlu_picio_clk_override, // override PICIO clock domain gating\n output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating\n output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating\n\n output logic dec_tlu_i0_commit_cmt, // committed i0 instruction\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode // Flop scan mode control\n /*pragma coverage on*/\n\n);\n\n el2_br_pkt_t i0_brp; // branch packet\n el2_lsu_error_pkt_t lsu_error_pkt_r; // LSU exception/error packet\n el2_trigger_pkt_t [3:0] trigger_pkt_any;\n // Unwrap structure support both simulators\n for (genvar i = 0; i < 4; i++) begin : g_unwrap_el2_trigger_pkt_t\n assign trigger_pkt_any_select[i] = trigger_pkt_any[i][37];\n assign trigger_pkt_any_match[i] = trigger_pkt_any[i][36];\n assign trigger_pkt_any_store[i] = trigger_pkt_any[i][35];\n assign trigger_pkt_any_load[i] = trigger_pkt_any[i][34];\n assign trigger_pkt_any_execute[i] = trigger_pkt_any[i][33];\n assign trigger_pkt_any_m[i] = trigger_pkt_any[i][32];\n assign trigger_pkt_any_tdata2[i] = trigger_pkt_any[i][31:0];\n end\n\n assign i0_brp = '0;\n assign lsu_error_pkt_r = '0;\n\n el2_dec dut (.*);\nendmodule\n" }, { "path": "verification/block/dec/test_dec.py", "content": "# Copyright (c) 2025 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport pyuvm\nfrom pyuvm import ConfigDB\nfrom testbench import BaseEnv, BaseTest, DecSequence\n\n# =============================================================================\n\n\nclass DecTluCtlTest(BaseTest):\n def __init__(self, test_name, name, parent, env_class=BaseEnv):\n self.test_name = test_name\n super().__init__(name, parent, env_class)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n ConfigDB().set(None, \"*\", \"TEST\", self.test_name)\n self.seq = DecSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.dec_seqr)\n\n\n@pyuvm.test()\nclass TestMeihap(DecTluCtlTest):\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(\"meihap\", name, parent, env_class)\n\n\n@pyuvm.test()\nclass TestMtdata(DecTluCtlTest):\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(\"mtdata\", name, parent, env_class)\n\n\n@pyuvm.test()\nclass TestCsrAccess(DecTluCtlTest):\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(\"csr_access\", name, parent, env_class)\n\n\n@pyuvm.test()\nclass TestDebugICCache(DecTluCtlTest):\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(\"debug_ic_cache\", name, parent, env_class)\n\n\n@pyuvm.test()\nclass TestDebugCSRs(DecTluCtlTest):\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(\"debug_csrs_access\", name, parent, env_class)\n\n\n@pyuvm.test()\nclass TestMeicidpl(DecTluCtlTest):\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(\"meicidpl\", name, parent, env_class)\n" }, { "path": "verification/block/dec/testbench.py", "content": "# Copyright (c) 2025 Antmicro\n# SPDX-License-Identifier: Apache-2.0\nimport logging\nimport os\nimport random\nfrom dataclasses import dataclass\nfrom enum import IntEnum\n\nimport cocotb\nimport csrs\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, FallingEdge, RisingEdge\nfrom csrs import get_bit\nfrom pyuvm import (\n ConfigDB,\n uvm_analysis_port,\n uvm_component,\n uvm_driver,\n uvm_env,\n uvm_get_port,\n uvm_report_object,\n uvm_sequence,\n uvm_sequence_item,\n uvm_sequencer,\n uvm_test,\n uvm_tlm_analysis_fifo,\n)\n\n# ==============================================================================\n\n\n@dataclass\nclass TriggerAnyPktT:\n select: int = 0\n match: int = 0\n store: int = 0\n load: int = 0\n execute: int = 0\n m: int = 0\n tdata2: int = 0\n\n @staticmethod\n def get_from_dut(dut):\n trigger_pkt_any_select = int(dut.trigger_pkt_any_select.value)\n trigger_pkt_any_match = int(dut.trigger_pkt_any_match.value)\n trigger_pkt_any_store = int(dut.trigger_pkt_any_store.value)\n trigger_pkt_any_load = int(dut.trigger_pkt_any_load.value)\n trigger_pkt_any_execute = int(dut.trigger_pkt_any_execute.value)\n trigger_pkt_any_m = int(dut.trigger_pkt_any_m.value)\n trigger_pkt_any_tdata2 = int(dut.trigger_pkt_any_tdata2.value)\n return TriggerAnyPktT(\n trigger_pkt_any_select,\n trigger_pkt_any_match,\n trigger_pkt_any_store,\n trigger_pkt_any_load,\n trigger_pkt_any_execute,\n trigger_pkt_any_m,\n trigger_pkt_any_tdata2,\n )\n\n\ndef log_mismatch_error(logger, name, expected, got):\n logger.error(f\"{name} {hex(expected)} != {hex(got)} (should be {hex(expected)})\")\n\n\ncsr_list = [getattr(csrs, mod) for mod in dir(csrs) if isinstance(getattr(csrs, mod), csrs.CSR)]\nCSR_OPCODE = 0b1110011\n\n\nclass Funct3(IntEnum):\n CSRRW = 0b001\n CSRRS = 0b010\n CSRRC = 0b011\n CSRRWI = 0b101\n CSRRSI = 0b110\n CSRRCI = 0b111\n\n\ndef csr_access_inst(csr, rs1, funct3, rd, opcode):\n csr_mask = (1 << 13) - 1\n rs1_mask = (1 << 6) - 1\n funct3_mask = (1 << 4) - 1\n rd_mask = (1 << 6) - 1\n opcode_mask = (1 << 8) - 1\n return (\n (csr & csr_mask) << 20\n | (rs1 & rs1_mask) << 15\n | (funct3 & funct3_mask) << 12\n | (rd & rd_mask) << 7\n | (opcode & opcode_mask)\n )\n\n\n@dataclass\nclass ReadCSRInst:\n csr: int = 0\n funct3: Funct3 = Funct3.CSRRS\n\n def encode(self):\n return csr_access_inst(self.csr, 0, self.funct3, 0, CSR_OPCODE)\n\n\n@dataclass\nclass WriteCSRInst:\n csr: int = 0\n funct3: Funct3 = Funct3.CSRRW\n\n def encode(self):\n return csr_access_inst(self.csr, 0, self.funct3, 0, CSR_OPCODE)\n\n\ndef randint(width=32):\n return random.randint(0, 2 ** (width) - 1)\n\n\nclass DecInputItem(uvm_sequence_item):\n \"\"\"\n Trigger Logic input data\n \"\"\"\n\n def __init__(\n self,\n pic_pl=0,\n pic_claimid=0,\n exu_i0_result_x=0,\n ifu_ic_debug_rd_data=0,\n csrw_instr=0,\n csrr_instr=0,\n csr_addr=0,\n mtdata1=0,\n mtdata2=0,\n mtsel=0,\n ):\n super().__init__(\"DecInputItem\")\n self.exu_i0_result_x = exu_i0_result_x\n self.csr_addr = csr_addr\n self.csrw_instr = csrw_instr\n self.csrr_instr = csrr_instr\n self.pic_pl = pic_pl\n self.pic_claimid = pic_claimid\n self.ifu_ic_debug_rd_data = ifu_ic_debug_rd_data\n self.mtdata1 = mtdata1\n self.mtdata2 = mtdata2\n self.mtsel = mtsel\n\n def randomize(self, test):\n if test == \"meihap\":\n self.pic_claimid = randint(8)\n self.exu_i0_result_x = randint(22) << 10\n self.csr_addr = csrs.MEIVT\n self.csrw_instr = WriteCSRInst(self.csr_addr).encode()\n self.csrr_instr = ReadCSRInst(self.csr_addr).encode()\n elif test == \"mtdata\":\n # bits 31:28 are hardcoded to 0x2\n mtdata1 = \"0010\"\n for _ in range(28):\n mtdata1 += random.choice([\"0\", \"1\"])\n # set DMODE (bit 27) to 0 so that the settings are actually taken into account\n # in the list, bits are numbered from 0\n tmp = list(mtdata1)\n tmp[31 - 27] = \"0\"\n mtdata1 = \"\".join(tmp)\n self.mtdata1 = int(mtdata1, 2)\n self.mtdata2 = randint(32)\n self.mtsel = randint(2)\n elif test == \"csr_access\":\n self.csr_addr = random.choice(\n [\n csrs.MCOUNTINHIBIT,\n csrs.MDCCMECT,\n csrs.MEICURPL,\n csrs.MEIPT,\n csrs.MFDC,\n csrs.MFDHT,\n csrs.MHPMC3,\n csrs.MHPMC3H,\n csrs.MHPMC4,\n csrs.MHPMC4H,\n csrs.MHPMC5,\n csrs.MHPMC5H,\n csrs.MHPMC6,\n csrs.MHPMC6H,\n csrs.MHPME3,\n csrs.MHPME4,\n csrs.MHPME5,\n csrs.MHPME6,\n csrs.MICCMECT,\n csrs.MICECT,\n csrs.MINSTRETH,\n csrs.MINSTRETL,\n csrs.MRAC,\n csrs.MTVEC,\n ]\n )\n self.exu_i0_result_x = randint()\n self.csrw_instr = WriteCSRInst(self.csr_addr).encode()\n self.csrr_instr = ReadCSRInst(self.csr_addr).encode()\n elif test == \"debug_ic_cache\":\n self.ifu_ic_debug_rd_data = randint(71)\n elif test == \"debug_csrs_access\":\n self.exu_i0_result_x = randint(32)\n self.csr_addr = random.choice(\n [csrs.DICAD0, csrs.DICAD0H, csrs.DICAWICS, csrs.DPC, csrs.DCSR]\n )\n self.csrw_instr = WriteCSRInst(self.csr_addr).encode()\n self.csrr_instr = ReadCSRInst(self.csr_addr).encode()\n elif test == \"meicidpl\":\n self.pic_pl = randint(4)\n self.csr_addr = csrs.MEICIDPL\n self.csrw_instr = WriteCSRInst(self.csr_addr).encode()\n self.csrr_instr = ReadCSRInst(self.csr_addr).encode()\n\n\nclass DecOutputItem(uvm_sequence_item):\n \"\"\"\n Trigger Logic output data\n \"\"\"\n\n def __init__(\n self,\n csrr_instr=0,\n dec_csr_wrdata_r=0,\n dec_csr_rddata_d=0,\n dec_tlu_meihap=0,\n trigger_pkt_any=TriggerAnyPktT(),\n ifu_ic_debug_rd_data=0,\n ):\n super().__init__(\"DecOutputItem\")\n self.csrr_instr = csrr_instr\n self.dec_csr_wrdata_r = dec_csr_wrdata_r\n self.dec_csr_rddata_d = dec_csr_rddata_d\n self.dec_tlu_meihap = dec_tlu_meihap\n self.trigger_pkt_any = trigger_pkt_any\n self.ifu_ic_debug_rd_data = ifu_ic_debug_rd_data\n\n\n# ==============================================================================\n\n\nclass DecDriver(uvm_driver):\n \"\"\"\n Trigger Logic driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def read_csr(self, instr):\n self.dut.ifu_i0_valid.value = 0\n await RisingEdge(self.dut.clk)\n self.dut.ifu_i0_valid.value = 1\n self.dut.ifu_i0_instr.value = instr\n await RisingEdge(self.dut.clk)\n self.dut.ifu_i0_valid.value = 0\n self.dut.ifu_i0_instr.value = 0\n\n async def write_csr(self, instr, data):\n self.dut.ifu_i0_valid.value = 0\n await RisingEdge(self.dut.clk)\n self.dut.ifu_i0_valid.value = 1\n self.dut.ifu_i0_instr.value = instr\n await RisingEdge(self.dut.clk)\n self.dut.ifu_i0_instr.value = 0\n self.dut.exu_i0_result_x.value = data\n self.dut.ifu_i0_valid.value = 0\n await RisingEdge(self.dut.clk)\n self.dut.exu_i0_result_x.value = 0\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n if isinstance(it, DecInputItem):\n test = ConfigDB().get(self, \"\", \"TEST\")\n if test == \"meihap\":\n # Write MEIVT\n await self.write_csr(it.csrw_instr, it.exu_i0_result_x)\n await ClockCycles(self.dut.clk, 2)\n # Write pic_claimid via MEICPCT\n self.dut.pic_claimid.value = it.pic_claimid\n instr = WriteCSRInst(csrs.MEICPCT).encode()\n await self.write_csr(instr, it.exu_i0_result_x)\n # Allow output monitor to catch the data on the outputs\n await ClockCycles(self.dut.clk, 2)\n elif test == \"mtdata\":\n await self.write_csr(WriteCSRInst(csrs.MTSEL).encode(), it.mtsel)\n await self.write_csr(WriteCSRInst(csrs.MTDATA1).encode(), it.mtdata1)\n await self.write_csr(WriteCSRInst(csrs.MTDATA2).encode(), it.mtdata2)\n await ClockCycles(self.dut.clk, 4)\n elif test in [\"csr_access\"]:\n # Write CSR\n await self.write_csr(it.csrw_instr, it.exu_i0_result_x)\n await ClockCycles(self.dut.clk, 2)\n # Read the CSR back\n await self.read_csr(it.csrr_instr)\n await RisingEdge(self.dut.clk)\n elif test == \"debug_ic_cache\":\n self.dut.ifu_ic_debug_rd_data_valid.value = 1\n self.dut.ifu_ic_debug_rd_data.value = it.ifu_ic_debug_rd_data\n await RisingEdge(self.dut.clk)\n self.dut.ifu_ic_debug_rd_data_valid.value = 0\n await self.read_csr(ReadCSRInst(csrs.DICAD0).encode())\n await self.read_csr(ReadCSRInst(csrs.DICAD0H).encode())\n await self.read_csr(ReadCSRInst(csrs.DICAD1).encode())\n elif test == \"debug_csrs_access\":\n await self.write_csr(it.csrw_instr, it.exu_i0_result_x)\n await ClockCycles(self.dut.clk, 2)\n await self.read_csr(it.csrr_instr)\n await ClockCycles(self.dut.clk, 2)\n elif test == \"meicidpl\":\n self.dut.pic_pl.value = it.pic_pl\n await self.write_csr(it.csrw_instr, 0)\n await ClockCycles(self.dut.clk, 2)\n await self.read_csr(it.csrr_instr)\n await RisingEdge(self.dut.clk)\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass DecInputMonitor(uvm_component):\n \"\"\"\n Monitor for Trigger Logic inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n test = ConfigDB().get(self, \"\", \"TEST\")\n if test == \"meihap\":\n await RisingEdge(self.dut.ifu_i0_valid)\n await ClockCycles(self.dut.clk, 2)\n exu_i0_result_x = int(self.dut.exu_i0_result_x.value)\n await RisingEdge(self.dut.ifu_i0_valid)\n pic_claimid = int(self.dut.pic_claimid.value)\n self.ap.write(\n DecInputItem(pic_claimid=pic_claimid, exu_i0_result_x=exu_i0_result_x)\n )\n elif test == \"mtdata\":\n await RisingEdge(self.dut.ifu_i0_valid)\n await ClockCycles(self.dut.clk, 2)\n mtsel = int(self.dut.exu_i0_result_x.value)\n await RisingEdge(self.dut.ifu_i0_valid)\n await ClockCycles(self.dut.clk, 2)\n mtdata1 = int(self.dut.exu_i0_result_x.value)\n await RisingEdge(self.dut.ifu_i0_valid)\n await ClockCycles(self.dut.clk, 2)\n mtdata2 = int(self.dut.exu_i0_result_x.value)\n self.ap.write(DecInputItem(mtdata1=mtdata1, mtdata2=mtdata2, mtsel=mtsel))\n elif test in [\"csr_access\"]:\n # Wait for CSR write\n await RisingEdge(self.dut.ifu_i0_valid)\n await RisingEdge(self.dut.clk)\n csrw_instr = int(self.dut.ifu_i0_instr.value)\n await RisingEdge(self.dut.clk)\n exu_i0_result_x = int(self.dut.exu_i0_result_x.value)\n # Wait for CSR read\n await RisingEdge(self.dut.ifu_i0_valid)\n await RisingEdge(self.dut.clk)\n csrr_instr = int(self.dut.ifu_i0_instr.value)\n self.ap.write(\n DecInputItem(\n csrw_instr=csrw_instr,\n csrr_instr=csrr_instr,\n exu_i0_result_x=exu_i0_result_x,\n )\n )\n elif test == \"debug_ic_cache\":\n # Wait for CSR write\n await RisingEdge(self.dut.ifu_ic_debug_rd_data_valid)\n await RisingEdge(self.dut.clk)\n ic_debug_rd_data = int(self.dut.ifu_ic_debug_rd_data.value)\n self.ap.write(DecInputItem(ifu_ic_debug_rd_data=ic_debug_rd_data))\n # Wait for CSR reads\n await ClockCycles(self.dut.clk, 4)\n elif test == \"debug_csrs_access\":\n await RisingEdge(self.dut.ifu_i0_valid)\n await RisingEdge(self.dut.clk)\n csr_addr = int(self.dut.ifu_i0_instr.value) >> 20\n await ClockCycles(self.dut.clk, 1)\n exu_i0_result_x = int(self.dut.exu_i0_result_x.value)\n # Await CSR read\n await RisingEdge(self.dut.ifu_i0_valid)\n await RisingEdge(self.dut.clk)\n self.ap.write(DecInputItem(csr_addr=csr_addr, exu_i0_result_x=exu_i0_result_x))\n elif test == \"meicidpl\":\n await RisingEdge(self.dut.ifu_i0_valid)\n csr_addr = int(self.dut.ifu_i0_instr.value) >> 20\n await ClockCycles(self.dut.clk, 2)\n exu_i0_result_x = int(self.dut.exu_i0_result_x.value)\n await RisingEdge(self.dut.ifu_i0_valid)\n self.ap.write(DecInputItem(csr_addr=csr_addr, exu_i0_result_x=exu_i0_result_x))\n\n\nclass DecOutputMonitor(uvm_component):\n \"\"\"\n Monitor for Trigger Logic outputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n test = ConfigDB().get(self, \"\", \"TEST\")\n if test == \"meihap\":\n for _ in range(2):\n await RisingEdge(self.dut.ifu_i0_valid)\n await ClockCycles(self.dut.clk, 4)\n dec_tlu_meihap = int(self.dut.dec_tlu_meihap.value)\n self.ap.write(DecOutputItem(dec_tlu_meihap=dec_tlu_meihap))\n elif test == \"mtdata\":\n # Wait for CSR writes\n for _ in range(3):\n await RisingEdge(self.dut.ifu_i0_valid)\n # Wait for the outputs\n await ClockCycles(self.dut.clk, 4)\n trigger_pkt_any = TriggerAnyPktT.get_from_dut(self.dut)\n self.ap.write(DecOutputItem(trigger_pkt_any=trigger_pkt_any))\n elif test in [\"csr_access\"]:\n for _ in range(2):\n await RisingEdge(self.dut.ifu_i0_valid)\n await RisingEdge(self.dut.clk)\n csrr_instr = int(self.dut.ifu_i0_instr.value)\n dec_csr_rddata_d = int(self.dut.dec_csr_rddata_d.value)\n self.ap.write(\n DecOutputItem(\n csrr_instr=csrr_instr,\n dec_csr_rddata_d=dec_csr_rddata_d,\n )\n )\n elif test == \"debug_ic_cache\":\n await RisingEdge(self.dut.ifu_ic_debug_rd_data_valid)\n await RisingEdge(self.dut.ifu_i0_valid)\n await RisingEdge(self.dut.clk)\n dicad0 = int(self.dut.dec_csr_rddata_d.value)\n await RisingEdge(self.dut.ifu_i0_valid)\n await RisingEdge(self.dut.clk)\n dicad0h = int(self.dut.dec_csr_rddata_d.value)\n await RisingEdge(self.dut.ifu_i0_valid)\n await RisingEdge(self.dut.clk)\n dicad1 = int(self.dut.dec_csr_rddata_d.value)\n ifu_ic_debug_rd_data = dicad0 | (dicad0h << 32) | (dicad1 << 64)\n self.ap.write(DecOutputItem(ifu_ic_debug_rd_data=ifu_ic_debug_rd_data))\n elif test == \"debug_csrs_access\":\n for _ in range(2):\n await RisingEdge(self.dut.ifu_i0_valid)\n await RisingEdge(self.dut.clk)\n dec_csr_rddata_d = int(self.dut.dec_csr_rddata_d.value)\n self.ap.write(DecOutputItem(dec_csr_rddata_d=dec_csr_rddata_d))\n elif test == \"meicidpl\":\n for _ in range(2):\n await RisingEdge(self.dut.ifu_i0_valid)\n csrr_instr = int(self.dut.ifu_i0_instr.value)\n await RisingEdge(self.dut.clk)\n dec_csr_rddata_d = int(self.dut.dec_csr_rddata_d.value)\n self.ap.write(\n DecOutputItem(\n csrr_instr=csrr_instr,\n dec_csr_rddata_d=dec_csr_rddata_d,\n )\n )\n\n\n# ==============================================================================\n\n\nclass DecScoreboard(uvm_component):\n \"\"\"\n Trigger Logic scoreboard\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self): # noqa: C901\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n test = ConfigDB().get(self, \"\", \"TEST\")\n if test == \"meihap\":\n pic_claimid_i = item_inp.pic_claimid\n pic_claimid_o = item_out.dec_tlu_meihap & 0xFF\n meivt_i = item_inp.exu_i0_result_x >> 12\n meivt_o = item_out.dec_tlu_meihap >> 10\n\n if pic_claimid_i != pic_claimid_o:\n log_mismatch_error(self.logger, \"pic_claimid\", pic_claimid_i, pic_claimid_o)\n self.passed = False\n\n if meivt_i != meivt_o:\n log_mismatch_error(self.logger, \"meivt\", meivt_i, meivt_o)\n self.passed = False\n\n elif test == \"mtdata\":\n tdata2_mask = 0xFFFFFFFF\n mtsel = item_inp.mtsel\n\n mtdata1_i = item_inp.mtdata1\n mtdata2_i = item_inp.mtdata2\n trigger_pkt_any = item_out.trigger_pkt_any\n\n select_i = get_bit(mtdata1_i, 19)\n match_i = get_bit(mtdata1_i, 7)\n store_i = get_bit(mtdata1_i, 1)\n load_i = get_bit(mtdata1_i, 0) & ~get_bit(mtdata1_i, 19)\n execute_i = get_bit(mtdata1_i, 2) & ~get_bit(mtdata1_i, 19)\n m_i = get_bit(mtdata1_i, 6)\n\n select_o = get_bit(trigger_pkt_any.select, mtsel)\n match_o = get_bit(trigger_pkt_any.match, mtsel)\n store_o = get_bit(trigger_pkt_any.store, mtsel)\n load_o = get_bit(trigger_pkt_any.load, mtsel)\n execute_o = get_bit(trigger_pkt_any.execute, mtsel)\n m_o = get_bit(trigger_pkt_any.m, mtsel)\n\n mtdata2_o = (trigger_pkt_any.tdata2 >> (mtsel * 32)) & tdata2_mask\n\n if mtdata2_i != mtdata2_o:\n log_mismatch_error(self.logger, \"mtdata2\", mtdata2_i, mtdata2_o)\n self.passed = False\n if select_i != select_o:\n log_mismatch_error(self.logger, \"select\", select_i, select_o)\n self.passed = False\n if match_i != match_o:\n log_mismatch_error(self.logger, \"match\", match_i, match_o)\n self.passed = False\n if store_i != store_o:\n log_mismatch_error(self.logger, \"store\", store_i, store_o)\n self.passed = False\n if load_i != load_o:\n log_mismatch_error(self.logger, \"load\", load_i, load_o)\n self.passed = False\n if execute_i != execute_o:\n log_mismatch_error(self.logger, \"execute\", execute_i, execute_o)\n self.passed = False\n if m_i != m_o:\n log_mismatch_error(self.logger, \"m\", m_i, m_o)\n self.passed = False\n\n elif test == \"csr_access\":\n i0 = item_inp.csrw_instr\n i1 = item_inp.csrr_instr\n\n wr_addr = (i0 >> 20) & ((1 << 13) - 1)\n rd_addr = (i1 >> 20) & ((1 << 13) - 1)\n\n if wr_addr != rd_addr:\n err_msg = f\"Write to reg[{hex(wr_addr)}] but read from reg[{hex(rd_addr)}]\"\n self.logger.error(err_msg)\n self.passed = False\n\n csr = rd_addr\n data_in = item_inp.exu_i0_result_x\n data_out = item_out.dec_csr_rddata_d\n\n for c in csr_list:\n if c == csr:\n data_in = c.out(data_in)\n break\n\n if data_in != data_out:\n log_mismatch_error(self.logger, f\"reg_val[{hex(csr)}]\", data_in, data_out)\n self.passed = False\n\n elif test == \"debug_ic_cache\":\n ifu_ic_debug_rd_data_in = item_inp.ifu_ic_debug_rd_data\n ifu_ic_debug_rd_data_out = item_out.ifu_ic_debug_rd_data\n\n if ifu_ic_debug_rd_data_in != ifu_ic_debug_rd_data_out:\n log_mismatch_error(\n self.logger, \"read_data\", ifu_ic_debug_rd_data_in, ifu_ic_debug_rd_data_out\n )\n self.passed = False\n\n elif test == \"debug_csrs_access\":\n csr = item_inp.csr_addr\n reg_val_i = item_inp.exu_i0_result_x\n reg_val_o = item_out.dec_csr_rddata_d\n\n dbg_csrs = [csrs.DICAD0, csrs.DICAD0H, csrs.DICAWICS, csrs.DPC, csrs.DCSR]\n for c in dbg_csrs:\n if c == csr:\n reg_val_i = c.out(reg_val_i)\n break\n if reg_val_i != reg_val_o:\n log_mismatch_error(self.logger, f\"reg_val[{hex(csr)}]\", reg_val_i, reg_val_o)\n self.passed = False\n\n elif test == \"meicidpl\":\n reg_val_i = item_inp.exu_i0_result_x\n reg_val_o = item_out.dec_csr_rddata_d\n reg_val_i = csrs.MEICIDPL.out(reg_val_i)\n if reg_val_i != reg_val_o:\n log_mismatch_error(self.logger, f\"reg_val[{hex(csr)}]\", reg_val_i, reg_val_o)\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass DecSequence(uvm_sequence):\n\n def __init__(self, name, ops=None):\n super().__init__(name)\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n test = ConfigDB().get(None, \"\", \"TEST\")\n\n for _ in range(count):\n item = DecInputItem()\n item.randomize(test)\n\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 5000)\n\n # Sequencers\n self.dec_seqr = uvm_sequencer(\"dec_seqr\", self)\n\n # Driver\n self.dec_drv = DecDriver(\"dec_drv\", self, dut=cocotb.top)\n\n # Monitors\n self.inp_mon = DecInputMonitor(\"inp_mon\", self, dut=cocotb.top)\n self.out_mon = DecOutputMonitor(\"out_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = DecScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.dec_drv.seq_item_port.connect(self.dec_seqr.seq_item_export)\n\n self.inp_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.out_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def enter_debug_mode(self):\n cocotb.top.dbg_halt_req.value = 1\n await ClockCycles(cocotb.top.clk, 2)\n cocotb.top.dbg_halt_req.value = 0\n if not cocotb.top.o_debug_mode_status.value:\n await RisingEdge(cocotb.top.o_debug_mode_status)\n\n async def do_reset(self):\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n test = ConfigDB().get(self, \"\", \"TEST\")\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n self.start_clock(\"active_clk\")\n self.start_clock(\"free_clk\")\n self.start_clock(\"free_l2clk\")\n\n # Enable run after reset\n cocotb.top.mpc_reset_run_req.value = 1\n # Drive status indicators of non-included modules\n cocotb.top.lsu_idle_any.value = 1\n cocotb.top.ifu_miss_state_idle.value = 1\n\n cocotb.top.lsu_fastint_stall_any.value = 0\n cocotb.top.rst_vec.value = 0\n cocotb.top.nmi_int.value = 0\n cocotb.top.nmi_vec.value = 0\n cocotb.top.i_cpu_halt_req.value = 0\n cocotb.top.i_cpu_run_req.value = 0\n cocotb.top.core_id.value = 0\n cocotb.top.mpc_debug_halt_req.value = 0\n cocotb.top.mpc_debug_run_req.value = 0\n cocotb.top.exu_pmu_i0_br_misp.value = 0\n cocotb.top.exu_pmu_i0_br_ataken.value = 0\n cocotb.top.exu_pmu_i0_pc4.value = 0\n cocotb.top.lsu_nonblock_load_valid_m.value = 0\n cocotb.top.lsu_nonblock_load_tag_m.value = 0\n cocotb.top.lsu_nonblock_load_inv_r.value = 0\n cocotb.top.lsu_nonblock_load_inv_tag_r.value = 0\n cocotb.top.lsu_nonblock_load_data_valid.value = 0\n cocotb.top.lsu_nonblock_load_data_error.value = 0\n cocotb.top.lsu_nonblock_load_data_tag.value = 0\n cocotb.top.lsu_nonblock_load_data.value = 0\n cocotb.top.lsu_pmu_bus_trxn.value = 0\n cocotb.top.lsu_pmu_bus_misaligned.value = 0\n cocotb.top.lsu_pmu_bus_error.value = 0\n cocotb.top.lsu_pmu_bus_busy.value = 0\n cocotb.top.lsu_pmu_misaligned_m.value = 0\n cocotb.top.lsu_pmu_load_external_m.value = 0\n cocotb.top.lsu_pmu_store_external_m.value = 0\n cocotb.top.dma_pmu_dccm_read.value = 0\n cocotb.top.dma_pmu_dccm_write.value = 0\n cocotb.top.dma_pmu_any_read.value = 0\n cocotb.top.dma_pmu_any_write.value = 0\n cocotb.top.lsu_fir_addr.value = 0\n cocotb.top.lsu_fir_error.value = 0\n cocotb.top.ifu_pmu_instr_aligned.value = 0\n cocotb.top.ifu_pmu_fetch_stall.value = 0\n cocotb.top.ifu_pmu_ic_miss.value = 0\n cocotb.top.ifu_pmu_ic_hit.value = 0\n cocotb.top.ifu_pmu_bus_error.value = 0\n cocotb.top.ifu_pmu_bus_busy.value = 0\n cocotb.top.ifu_pmu_bus_trxn.value = 0\n cocotb.top.ifu_ic_error_start.value = 0\n cocotb.top.ifu_iccm_rd_ecc_single_err.value = 0\n cocotb.top.lsu_trigger_match_m.value = 0\n cocotb.top.dbg_cmd_valid.value = 0\n cocotb.top.dbg_cmd_write.value = 0\n cocotb.top.dbg_cmd_type.value = 0\n cocotb.top.dbg_cmd_addr.value = 0\n cocotb.top.dbg_cmd_wrdata.value = 0\n cocotb.top.ifu_i0_icaf.value = 0\n cocotb.top.ifu_i0_icaf_type.value = 0\n cocotb.top.ifu_i0_icaf_second.value = 0\n cocotb.top.ifu_i0_dbecc.value = 0\n cocotb.top.ifu_i0_bp_index.value = 0\n cocotb.top.ifu_i0_bp_fghr.value = 0\n cocotb.top.ifu_i0_bp_btag.value = 0\n cocotb.top.ifu_i0_fa_index.value = 0\n cocotb.top.lsu_single_ecc_error_incr.value = 0\n cocotb.top.lsu_imprecise_error_load_any.value = 0\n cocotb.top.lsu_imprecise_error_store_any.value = 0\n cocotb.top.lsu_imprecise_error_addr_any.value = 0\n cocotb.top.exu_div_result.value = 0\n cocotb.top.exu_div_wren.value = 0\n cocotb.top.exu_csr_rs1_x.value = 0\n cocotb.top.lsu_result_m.value = 0\n cocotb.top.lsu_result_corr_r.value = 0\n cocotb.top.lsu_load_stall_any.value = 0\n cocotb.top.lsu_store_stall_any.value = 0\n cocotb.top.dma_dccm_stall_any.value = 0\n cocotb.top.dma_iccm_stall_any.value = 0\n cocotb.top.iccm_dma_sb_error.value = 0\n cocotb.top.exu_flush_final.value = 0\n cocotb.top.exu_npc_r.value = 0\n cocotb.top.exu_i0_result_x.value = 0\n cocotb.top.ifu_i0_valid.value = 0\n cocotb.top.ifu_i0_instr.value = 0\n cocotb.top.ifu_i0_pc.value = 0\n cocotb.top.ifu_i0_pc4.value = 0\n cocotb.top.exu_i0_pc_x.value = 0\n cocotb.top.mexintpend.value = 0\n cocotb.top.timer_int.value = 0\n cocotb.top.soft_int.value = 0\n cocotb.top.pic_claimid.value = 0\n cocotb.top.pic_pl.value = 0\n cocotb.top.mhwakeup.value = 0\n cocotb.top.ifu_ic_debug_rd_data.value = 0\n cocotb.top.ifu_ic_debug_rd_data_valid.value = 0\n cocotb.top.dbg_halt_req.value = 0\n cocotb.top.dbg_resume_req.value = 0\n cocotb.top.exu_i0_br_hist_r.value = 0\n cocotb.top.exu_i0_br_error_r.value = 0\n cocotb.top.exu_i0_br_start_error_r.value = 0\n cocotb.top.exu_i0_br_valid_r.value = 0\n cocotb.top.exu_i0_br_mp_r.value = 0\n cocotb.top.exu_i0_br_middle_r.value = 0\n cocotb.top.exu_i0_br_way_r.value = 0\n cocotb.top.ifu_i0_cinst.value = 0\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n if test == \"debug_csrs_access\":\n await self.enter_debug_mode()\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/dec_ib/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_dec_ib_ctl_wrapper\n\nVERILOG_SOURCES = \\\n $(TEST_DIR)/el2_dec_ib_ctl_wrapper.sv \\\n $(SRCDIR)/dec/el2_dec_ib_ctl.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/dec_ib/config.vlt", "content": "`verilator_config\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_dec_ib_ctl_wrapper.sv\"\n" }, { "path": "verification/block/dec_ib/el2_dec_ib_ctl_wrapper.sv", "content": "// Copyright (c) 2024 Antmicro\n// SPDX-License-Identifier: Apache-2.0\nmodule el2_dec_ib_ctl_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n input logic dbg_cmd_valid, // valid dbg cmd\n input logic dbg_cmd_write, // dbg cmd is write\n input logic [ 1:0] dbg_cmd_type, // dbg type\n input logic [31:0] dbg_cmd_addr, // expand to 31:0\n\n // Unpacked input el2_br_pkt_t i0_brp // i0 branch packet from aligner\n input logic i0_brp_valid,\n input logic [11:0] i0_brp_toffset,\n input logic [1:0] i0_brp_hist,\n input logic i0_brp_br_error,\n input logic i0_brp_br_start_error,\n input logic i0_brp_bank,\n input logic [31:1] i0_brp_prett, // predicted ret target\n input logic i0_brp_way,\n input logic i0_brp_ret,\n\n input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index\n input logic [ pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR\n input logic [ pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag\n input logic [ $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index\n\n input logic ifu_i0_pc4, // i0 is 4B inst else 2B\n input logic ifu_i0_valid, // i0 valid from ifu\n input logic ifu_i0_icaf, // i0 instruction access fault\n input logic [1:0] ifu_i0_icaf_type, // i0 instruction access fault type\n\n input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst\n input logic ifu_i0_dbecc, // i0 double-bit error\n input logic [31:0] ifu_i0_instr, // i0 instruction from the aligner\n input logic [31:1] ifu_i0_pc, // i0 pc from the aligner\n\n\n output logic dec_ib0_valid_d, // ib0 valid\n output logic dec_debug_valid_d, // Debug read or write at D-stage\n\n\n output logic [31:0] dec_i0_instr_d, // i0 inst at decode\n\n output logic [31:1] dec_i0_pc_d, // i0 pc at decode\n\n output logic dec_i0_pc4_d, // i0 is 4B inst else 2B\n\n // Unpacked output el2_br_pkt_t dec_i0_brp // i0 branch packet at decode\n output logic dec_i0_brp_valid,\n output logic [11:0] dec_i0_brp_toffset,\n output logic [1:0] dec_i0_brp_hist,\n output logic dec_i0_brp_br_error,\n output logic dec_i0_brp_br_start_error,\n output logic dec_i0_brp_bank,\n output logic [31:1] dec_i0_brp_prett, // predicted ret target\n output logic dec_i0_brp_way,\n output logic dec_i0_brp_ret,\n\n output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index\n output logic [ pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR\n output logic [ pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag\n output logic [ $clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index\n\n output logic dec_i0_icaf_d, // i0 instruction access fault at decode\n output logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst\n output logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type\n output logic dec_i0_dbecc_d, // i0 double-bit error at decode\n output logic dec_debug_wdata_rs1_d, // put debug write data onto rs1 source: machine is halted\n\n output logic dec_debug_fence_d // debug fence inst\n);\n\n el2_br_pkt_t i0_brp;\n el2_br_pkt_t dec_i0_brp;\n\n assign i0_brp.valid = i0_brp_valid;\n assign i0_brp.toffset = i0_brp_toffset;\n assign i0_brp.hist = i0_brp_hist;\n assign i0_brp.br_error = i0_brp_br_error;\n assign i0_brp.br_start_error = i0_brp_br_start_error;\n assign i0_brp.bank = i0_brp_bank;\n assign i0_brp.prett = i0_brp_prett;\n assign i0_brp.way = i0_brp_way;\n assign i0_brp.ret = i0_brp_ret;\n\n assign dec_i0_brp_valid = dec_i0_brp.valid;\n assign dec_i0_brp_toffset = dec_i0_brp.toffset;\n assign dec_i0_brp_hist = dec_i0_brp.hist;\n assign dec_i0_brp_br_error = dec_i0_brp.br_error;\n assign dec_i0_brp_br_start_error = dec_i0_brp.br_start_error;\n assign dec_i0_brp_bank = dec_i0_brp.bank;\n assign dec_i0_brp_prett = dec_i0_brp.prett;\n assign dec_i0_brp_way = dec_i0_brp.way;\n assign dec_i0_brp_ret = dec_i0_brp.ret;\n\n // The trigger unit\n el2_dec_ib_ctl tu (.*);\n\nendmodule\n" }, { "path": "verification/block/dec_ib/test_dec_ib.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseTest, IbCtlSequence\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestIbCtlLogic(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = IbCtlSequence(\"stimulus\")\n\n async def run_phase(self):\n self.raise_objection()\n\n # Run the actual test\n await self.run()\n\n self.drop_objection()\n\n async def run(self):\n await self.seq.start(self.env.seqr)\n" }, { "path": "verification/block/dec_ib/testbench.py", "content": "# Copyright (c) 2024 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport copy\nimport math\nimport os\nimport random\nimport struct\nimport subprocess\nimport textwrap\nfrom dataclasses import dataclass\n\nimport pyuvm\nfrom cocotb.binary import BinaryValue\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import (\n ClockCycles,\n Event,\n FallingEdge,\n First,\n Lock,\n RisingEdge,\n Timer,\n)\nfrom cocotb.types import Array, Range\nfrom pyuvm import *\n\n# ==============================================================================\n\n\ndef get_opcode(asm_line, ext=\"rv32i_zicsr\", size=32):\n \"\"\"\n Generates opcode int based on a line of assembly\n \"\"\"\n\n cmd = f\"echo '{asm_line}' | riscv64-unknown-elf-as -march={ext} -o /dev/null -al | tail -n 1\"\n\n # Take instruction hex (3rd column) and change its endianess\n out = subprocess.check_output([cmd], shell=True).decode().split()[2]\n out = \"\".join(textwrap.wrap(out, 2)[::-1])\n\n assert len(out) == size // 4, f\"instruction '{asm_line}' assembled to unexpected width\"\n\n return int(out, 16)\n\n\nclass DebugCmdType(IntEnum):\n GPR = 0\n CSR = 1\n MEMORY = 2\n\n\n@dataclass\nclass DebugCmd:\n write: int\n type: DebugCmdType\n addr: int\n\n\nclass IbCtlInputItem(uvm_sequence_item):\n def __init__(self, debug_cmd, ifu_instr):\n super().__init__(\"IbCtlInputItem\")\n\n self.debug_cmd = debug_cmd\n self.ifu_instr = ifu_instr\n\n @property\n def debug_instr(self):\n if self.debug_cmd.type == DebugCmdType.GPR:\n if self.debug_cmd.write:\n return get_opcode(f\"or x{self.debug_cmd.addr}, x0, x0\")\n else:\n return get_opcode(f\"or x0, x{self.debug_cmd.addr}, x0\")\n elif self.debug_cmd.type == DebugCmdType.CSR:\n if self.debug_cmd.write:\n return get_opcode(f\"csrrw x0, {self.debug_cmd.addr}, x0\")\n else:\n return get_opcode(f\"csrrs x0, {self.debug_cmd.addr}, x0\")\n return 0\n\n\nclass IbCtlOutputItem(uvm_sequence_item):\n def __init__(self, instr):\n self.instr = instr\n super().__init__(\"IbCtlOutputItem\")\n\n\n# ==============================================================================\n\n\nclass IbCtlDriver(uvm_driver):\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n while True:\n item = await self.seq_item_port.get_next_item()\n\n self.dut.dbg_cmd_valid.value = 1\n self.dut.dbg_cmd_write.value = item.debug_cmd.write\n self.dut.dbg_cmd_type.value = int(item.debug_cmd.type)\n self.dut.dbg_cmd_addr.value = item.debug_cmd.addr\n self.dut.ifu_i0_instr.value = item.ifu_instr\n await Timer(period, \"ns\")\n\n self.seq_item_port.item_done()\n\n\nclass IbCtlInputMonitor(uvm_component):\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n while True:\n # Wait for the driver to set the input signals\n await Timer(period, \"ns\")\n\n write = int(self.dut.dbg_cmd_write.value)\n type = int(self.dut.dbg_cmd_type.value)\n addr = int(self.dut.dbg_cmd_addr.value)\n ifu_instr = int(self.dut.ifu_i0_instr.value)\n\n self.ap.write(IbCtlInputItem(DebugCmd(write, DebugCmdType(type), addr), ifu_instr))\n\n\nclass IbCtlOutputMonitor(uvm_component):\n \"\"\"\n Monitor for Trigger Logic outputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n while True:\n # Wait for the driver to set the input signals\n await Timer(period, \"ns\")\n\n instr = int(self.dut.dec_i0_instr_d.value)\n\n self.ap.write(IbCtlOutputItem(instr))\n\n\n# ==============================================================================\n\n\nclass IbCtlScoreboard(uvm_component):\n def __init__(self, name, parent):\n super().__init__(name, parent)\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self):\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n if item_inp.debug_instr != item_out.instr:\n self.logger.error(f\"Expected {item_inp.debug_instr:08x} got {item_out.instr:08x}\")\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass IbCtlSequence(uvm_sequence):\n def __init__(self, name, ops=None):\n super().__init__(name)\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n\n for i in range(count):\n write = random.randint(0, 1)\n type = random.choice([DebugCmdType.GPR, DebugCmdType.CSR])\n if type == DebugCmdType.GPR:\n addr = random.randrange(2**5)\n elif type == DebugCmdType.CSR:\n addr = random.randrange(2**12)\n\n debug_cmd = DebugCmd(\n write=write,\n type=type,\n addr=addr,\n )\n ifu_instr = random.randrange(2**31)\n\n item = IbCtlInputItem(debug_cmd, ifu_instr)\n\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 1000)\n\n # Sequencers\n self.seqr = uvm_sequencer(\"seqr\", self)\n\n # Driver\n self.drv = IbCtlDriver(\"drv\", self, dut=cocotb.top)\n\n # Monitors\n self.inp_mon = IbCtlInputMonitor(\"inp_mon\", self, dut=cocotb.top)\n self.out_mon = IbCtlOutputMonitor(\"out_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = IbCtlScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.drv.seq_item_port.connect(self.seqr.seq_item_export)\n\n self.inp_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.out_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/dec_pmp_ctl/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_dec_tlu_ctl\nPMP_TEST := 1\nCM_FILE = cm.cfg\n\nEXTRA_ARGS = -I$(SRCDIR)/include/\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/dec/el2_dec_tlu_ctl.sv \\\n $(SRCDIR)/dec/el2_dec_pmp_ctl.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/dec_pmp_ctl/cm.cfg", "content": "+tree el2_dec_tlu_ctl\n\n///////////////////////////////// dec_tlu_ctl /////////////////////////////////\n// Tied to '0\n-node el2_dec_tlu_ctl.dcsr[14]\n-node el2_dec_tlu_ctl.dcsr[9]\n-node el2_dec_tlu_ctl.dcsr[5:4]\n-node el2_dec_tlu_ctl.dcsr_ns[14]\n-node el2_dec_tlu_ctl.dcsr_ns[9]\n-node el2_dec_tlu_ctl.dcsr_ns[5:4]\n-node el2_dec_tlu_ctl.ifu_mscause[2]\n-node el2_dec_tlu_ctl.mcgc[6]\n-node el2_dec_tlu_ctl.mcgc_int[6]\n-node el2_dec_tlu_ctl.mcgc_ns[6]\n-node el2_dec_tlu_ctl.mcountinhibit[1]\n-node el2_dec_tlu_ctl.mepc_rf[0]\n-node el2_dec_tlu_ctl.mie_rf[31]\n-node el2_dec_tlu_ctl.mie_rf[27:12]\n-node el2_dec_tlu_ctl.mie_rf[10:8]\n-node el2_dec_tlu_ctl.mie_rf[6:4]\n-node el2_dec_tlu_ctl.mie_rf[2:0]\n-node el2_dec_tlu_ctl.mip_rf[27:12]\n-node el2_dec_tlu_ctl.mip_rf[10:8]\n-node el2_dec_tlu_ctl.mip_rf[6:4]\n-node el2_dec_tlu_ctl.mip_rf[2:0]\n-node el2_dec_tlu_ctl.mstatus_rf[31:17]\n-node el2_dec_tlu_ctl.mstatus_rf[15:12]\n-node el2_dec_tlu_ctl.mstatus_rf[10:8]\n-node el2_dec_tlu_ctl.mstatus_rf[6:4]\n-node el2_dec_tlu_ctl.mstatus_rf[2:0]\n-node el2_dec_tlu_ctl.mtdata1_tsel_out[26]\n-node el2_dec_tlu_ctl.mtdata1_tsel_out[18:13]\n-node el2_dec_tlu_ctl.mtdata1_tsel_out[10:8]\n-node el2_dec_tlu_ctl.mtdata1_tsel_out[5:3]\n-node el2_dec_tlu_ctl.mtvec_rf[1]\n\n/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////\n// Tied to '0\n-node el2_dec_tlu_ctl.pmp.*pmpcfg_ff.din[6:5]\n-node el2_dec_tlu_ctl.pmp.*pmpcfg_ff.dout[6:5]\n-node el2_dec_tlu_ctl.pmp.*csr_wdata[6:5]\n\n// Aggregation of four 'el2_pmp_cfg_pkt_t' entries\n// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0\n-node el2_dec_tlu_ctl.pmp.pmp_pmpcfg_rddata[30:29]\n-node el2_dec_tlu_ctl.pmp.pmp_pmpcfg_rddata[22:21]\n-node el2_dec_tlu_ctl.pmp.pmp_pmpcfg_rddata[14:13]\n-node el2_dec_tlu_ctl.pmp.pmp_pmpcfg_rddata[6:5]\n" }, { "path": "verification/block/dec_pmp_ctl/test_dec_pmp_ctl.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import (\n PMPADDR0,\n PMPADDR16,\n PMPADDR32,\n PMPADDR48,\n PMPCFG,\n BaseTest,\n InputItem,\n)\n\n# =============================================================================\n\n\nclass CsrSequence(uvm_sequence):\n \"\"\"\n A random sequence of PMP CSR items with random addresses and data\n \"\"\"\n\n def __init__(self, name):\n super().__init__(name)\n\n # Generate\n self.items = []\n addrs = set()\n for i in range(5):\n\n while True:\n item = InputItem(PMPCFG)\n item.randomize()\n if item.addr not in addrs:\n break\n self.legalize_pmpcfg(item)\n self.items.append(item)\n addrs.add(item.addr)\n\n for base in [PMPADDR0, PMPADDR16, PMPADDR32, PMPADDR48]:\n while True:\n item = InputItem(base)\n item.randomize()\n if item.addr not in addrs:\n break\n self.legalize_pmpaddr(item)\n self.items.append(item)\n addrs.add(item.addr)\n\n def legalize_pmpcfg(self, item):\n \"\"\"\n Leave only A, X and R fields as any combination of them is leagal and\n does not influence PMPADDR access. Setting L would interfere with the\n test.\n \"\"\"\n mask = 0b00011101\n item.data &= (mask << 24) | (mask << 16) | (mask << 8) | mask\n\n def legalize_pmpaddr(self, item):\n \"\"\"\n Mask out two MSBs\n \"\"\"\n item.data &= 0x3FFFFFFF\n\n async def body(self):\n\n # Run\n for item in self.items:\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass PmpCfgLockSequence(uvm_sequence):\n \"\"\"\n A random sequence of PMPCFG accesses that also do entry locking\n \"\"\"\n\n def __init__(self, name):\n super().__init__(name)\n\n # Generate\n self.items = []\n addrs = set()\n for i in range(10):\n\n while True:\n item = InputItem(PMPCFG)\n item.randomize()\n if item.addr not in addrs:\n break\n self.legalize_pmpcfg(item)\n self.items.append(item)\n addrs.add(item.addr)\n\n def legalize_pmpcfg(self, item):\n \"\"\"\n Leave only L, A, X and R fields as any combination of them is leagal and\n does not influence PMPADDR access.\n \"\"\"\n mask = 0b10011101\n item.data &= (mask << 24) | (mask << 16) | (mask << 8) | mask\n\n async def body(self):\n\n # Run\n for item in self.items:\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestCsrAccess(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n self.seq = [CsrSequence(\"stimulus\") for i in range(count)]\n\n async def run(self):\n for seq in self.seq:\n await seq.start(self.env.pmp_wr_seqr)\n await seq.start(self.env.pmp_rd_seqr)\n\n\n@pyuvm.test()\nclass TestPmpCfgLock(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n self.seq = [PmpCfgLockSequence(\"stimulus\") for i in range(count)]\n\n async def run(self):\n for seq in self.seq:\n\n # Do sequence of PMPCFG lock writes\n await seq.start(self.env.pmp_wr_seqr)\n await seq.start(self.env.pmp_rd_seqr)\n\n # Reset the module (there's no other way to clear the locks)\n await self.do_reset()\n" }, { "path": "verification/block/dec_pmp_ctl/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport copy\nimport math\nimport os\nimport random\nimport struct\n\nimport pyuvm\nfrom cocotb.binary import BinaryValue\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import (\n ClockCycles,\n Event,\n FallingEdge,\n First,\n Lock,\n RisingEdge,\n Timer,\n)\nfrom cocotb.types import Array, Range\nfrom pyuvm import *\n\n# ==============================================================================\n\nPMPCFG = 0x3A0\nPMPADDR0 = 0x3B0\nPMPADDR16 = 0x3C0\nPMPADDR32 = 0x3D0\nPMPADDR48 = 0x3E0\n\n# ==============================================================================\n\n\nclass InputItem(uvm_sequence_item):\n \"\"\"\n PMP input item\n \"\"\"\n\n RANGE = 16\n\n def __init__(self, addr=0, data=0):\n super().__init__(\"InputItem\")\n\n self.addr = addr\n self.data = data\n\n def randomize(self):\n \"\"\"\n Randomize data and address offset\n \"\"\"\n self.addr += random.randint(0, self.RANGE - 1)\n self.data = random.randint(0, 0xFFFFFFFF)\n\n\n# ==============================================================================\n\n\nclass CsrWriteDriver(uvm_driver):\n \"\"\"\n PMP CSR write port driver driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, InputItem):\n\n # Write\n await RisingEdge(self.dut.clk)\n self.dut.dec_csr_wen_r.value = 1\n self.dut.dec_csr_wraddr_r.value = it.addr\n self.dut.dec_csr_wrdata_r.value = it.data\n await RisingEdge(self.dut.clk)\n self.dut.dec_csr_wen_r.value = 0\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass CsrReadDriver(uvm_driver):\n \"\"\"\n PMP CSR read port driver driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, InputItem):\n\n # Read\n await RisingEdge(self.dut.clk)\n self.dut.dec_csr_rdaddr_d.value = it.addr\n\n await RisingEdge(self.dut.clk)\n self.dut.dec_csr_rdaddr_d.value = 0\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\n# ==============================================================================\n\n\nclass WriteMonitor(uvm_component):\n \"\"\"\n Monitor for CSR write inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n\n while True:\n\n # A write to a CSR\n await RisingEdge(self.dut.clk)\n if self.dut.dec_csr_wen_r.value:\n addr = int(self.dut.dec_csr_wraddr_r)\n data = int(self.dut.dec_csr_wrdata_r)\n\n item = InputItem(addr, data)\n self.ap.write(item)\n\n\nclass ReadMonitor(uvm_component):\n \"\"\"\n Monitor for CSR read inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n\n while True:\n\n # A read from a CSR\n await RisingEdge(self.dut.clk)\n addr = int(self.dut.dec_csr_rdaddr_d) & 0x3F0\n if addr in [PMPCFG, PMPADDR0, PMPADDR16, PMPADDR32, PMPADDR48]:\n addr = int(self.dut.dec_csr_rdaddr_d)\n data = int(self.dut.dec_csr_rddata_d)\n\n item = InputItem(addr, data)\n self.ap.write(item)\n\n\n# ==============================================================================\n\n\nclass Scoreboard(uvm_component):\n \"\"\"\n PMP dec ctl scoreboard\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self):\n self.passed = None\n\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n # Compare addresses and data\n if item_inp.addr != item_out.addr or item_inp.data != item_out.data:\n istr = f\"{item_inp.addr:04X}:{item_inp.data:08X}\"\n ostr = f\"{item_out.addr:04X}:{item_out.data:08X}\"\n self.logger.error(f\"Mismatch {istr} vs. {ostr}\")\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 5000)\n\n # Sequencers\n self.pmp_wr_seqr = uvm_sequencer(\"pmp_wr_seqr\", self)\n self.pmp_rd_seqr = uvm_sequencer(\"pmp_rd_seqr\", self)\n\n # Drivers\n self.pmp_wr_drv = CsrWriteDriver(\"pmp_wr_drv\", self, dut=cocotb.top)\n self.pmp_rd_drv = CsrReadDriver(\"pmp_rd_drv\", self, dut=cocotb.top)\n\n # Monitors\n self.wr_mon = WriteMonitor(\"wr_mon\", self, dut=cocotb.top)\n self.rd_mon = ReadMonitor(\"rd_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.pmp_wr_drv.seq_item_port.connect(self.pmp_wr_seqr.seq_item_export)\n self.pmp_rd_drv.seq_item_port.connect(self.pmp_rd_seqr.seq_item_export)\n\n self.wr_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.rd_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n cocotb.top.rst_l.value = 0\n cocotb.top.dec_csr_rdaddr_d.value = 0\n cocotb.top.i_cpu_halt_req.value = 0\n cocotb.top.i_cpu_run_req.value = 0\n cocotb.top.lsu_fastint_stall_any.value = 0\n cocotb.top.ifu_pmu_instr_aligned.value = 0\n cocotb.top.ifu_pmu_fetch_stall.value = 0\n cocotb.top.ifu_pmu_ic_miss.value = 0\n cocotb.top.ifu_pmu_ic_hit.value = 0\n cocotb.top.ifu_pmu_bus_error.value = 0\n cocotb.top.ifu_pmu_bus_busy.value = 0\n cocotb.top.ifu_pmu_bus_trxn.value = 0\n cocotb.top.dec_pmu_instr_decoded.value = 0\n cocotb.top.dec_pmu_decode_stall.value = 0\n cocotb.top.dec_pmu_presync_stall.value = 0\n cocotb.top.dec_pmu_postsync_stall.value = 0\n cocotb.top.lsu_store_stall_any.value = 0\n cocotb.top.dma_dccm_stall_any.value = 0\n cocotb.top.dma_iccm_stall_any.value = 0\n cocotb.top.exu_pmu_i0_br_misp.value = 0\n cocotb.top.exu_pmu_i0_br_ataken.value = 0\n cocotb.top.exu_pmu_i0_pc4.value = 0\n cocotb.top.lsu_pmu_bus_trxn.value = 0\n cocotb.top.lsu_pmu_bus_misaligned.value = 0\n cocotb.top.lsu_pmu_bus_error.value = 0\n cocotb.top.lsu_pmu_bus_busy.value = 0\n cocotb.top.lsu_pmu_load_external_m.value = 0\n cocotb.top.lsu_pmu_store_external_m.value = 0\n cocotb.top.dma_pmu_dccm_read.value = 0\n cocotb.top.dma_pmu_dccm_write.value = 0\n cocotb.top.dma_pmu_any_read.value = 0\n cocotb.top.dma_pmu_any_write.value = 0\n cocotb.top.lsu_fir_addr.value = 0\n cocotb.top.lsu_fir_error.value = 0\n cocotb.top.iccm_dma_sb_error.value = 0\n cocotb.top.lsu_single_ecc_error_incr.value = 0\n cocotb.top.dec_pause_state.value = 0\n cocotb.top.lsu_imprecise_error_store_any.value = 0\n cocotb.top.lsu_imprecise_error_load_any.value = 0\n cocotb.top.lsu_imprecise_error_addr_any.value = 0\n cocotb.top.dec_csr_wen_unq_d.value = 0\n cocotb.top.dec_csr_any_unq_d.value = 0\n cocotb.top.dec_csr_rdaddr_d.value = 0\n cocotb.top.dec_csr_wen_r.value = 0\n cocotb.top.dec_csr_rdaddr_r.value = 0\n cocotb.top.dec_csr_wraddr_r.value = 0\n cocotb.top.dec_csr_wrdata_r.value = 0\n cocotb.top.dec_csr_stall_int_ff.value = 0\n cocotb.top.dec_tlu_i0_valid_r.value = 0\n cocotb.top.exu_npc_r.value = 0\n cocotb.top.dec_tlu_i0_pc_r.value = 0\n cocotb.top.dec_illegal_inst.value = 0\n cocotb.top.dec_i0_decode_d.value = 0\n cocotb.top.exu_i0_br_hist_r.value = 0\n cocotb.top.exu_i0_br_error_r.value = 0\n cocotb.top.exu_i0_br_start_error_r.value = 0\n cocotb.top.exu_i0_br_valid_r.value = 0\n cocotb.top.exu_i0_br_mp_r.value = 0\n cocotb.top.exu_i0_br_middle_r.value = 0\n cocotb.top.exu_i0_br_way_r.value = 0\n cocotb.top.dec_csr_stall_int_ff.value = 0\n cocotb.top.dbg_halt_req.value = 0\n cocotb.top.dbg_resume_req.value = 0\n cocotb.top.lsu_idle_any.value = 0\n cocotb.top.dec_div_active.value = 0\n cocotb.top.ifu_ic_error_start.value = 0\n cocotb.top.ifu_iccm_rd_ecc_single_err.value = 0\n cocotb.top.ifu_ic_debug_rd_data.value = 0\n cocotb.top.ifu_ic_debug_rd_data_valid.value = 0\n cocotb.top.core_id.value = 0\n await ClockCycles(cocotb.top.clk, 10)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n self.start_clock(\"free_clk\")\n self.start_clock(\"csr_wr_clk\")\n self.start_clock(\"free_l2clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/dec_tl/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_dec_trigger_wrapper\n\nVERILOG_SOURCES = \\\n $(TEST_DIR)/el2_dec_trigger_wrapper.sv \\\n $(SRCDIR)/dec/el2_dec_trigger.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/dec_tl/config.vlt", "content": "`verilator_config\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_dec_trigger_wrapper.sv\"\n\nlint_off -rule UNUSEDPARAM -file \"*/el2_dec_trigger_wrapper.sv\"\n" }, { "path": "verification/block/dec_tl/el2_dec_trigger_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro\n// SPDX-License-Identifier: Apache-2.0\nmodule el2_dec_trigger_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n input logic [31:1] dec_i0_pc_d,\n\n // Unpacked [3:0] trigger_pkt_t\n input logic [3:0] select,\n input logic [3:0] match,\n input logic [3:0] store,\n input logic [3:0] load,\n input logic [3:0] execute,\n input logic [3:0] m,\n\n input logic [31:0] tdata[4],\n\n output logic [3:0] dec_i0_trigger_match_d\n);\n\n // Pack triggers\n el2_trigger_pkt_t [3:0] trigger_pkt_any;\n for (genvar i = 0; i < 4; i++) begin : g_trigger_assigns\n assign trigger_pkt_any[i].select = select[i];\n assign trigger_pkt_any[i].match = match[i];\n assign trigger_pkt_any[i].store = store[i];\n assign trigger_pkt_any[i].load = load[i];\n assign trigger_pkt_any[i].execute = execute[i];\n assign trigger_pkt_any[i].m = m[i];\n assign trigger_pkt_any[i].tdata2 = tdata[i];\n end\n\n // The trigger unit\n el2_dec_trigger tu (\n .dec_i0_pc_d(dec_i0_pc_d[31:1]),\n .*\n );\n\nendmodule\n" }, { "path": "verification/block/dec_tl/test_dec_tl.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseTest, TlSequence\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestTriggerLogic(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TlSequence(\"stimulus\")\n\n async def run_phase(self):\n self.raise_objection()\n\n # Run the actual test\n await self.run()\n\n self.drop_objection()\n\n async def run(self):\n await self.seq.start(self.env.tl_seqr)\n" }, { "path": "verification/block/dec_tl/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport copy\nimport math\nimport os\nimport random\nimport struct\n\nimport pyuvm\nfrom cocotb.binary import BinaryValue\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import (\n ClockCycles,\n Event,\n FallingEdge,\n First,\n Lock,\n RisingEdge,\n Timer,\n)\nfrom cocotb.types import Array, Range\nfrom pyuvm import *\n\n# ==============================================================================\n\n\nclass TlInputItem(uvm_sequence_item):\n \"\"\"\n Trigger Logic output data\n \"\"\"\n\n def __init__(self, data=0, tdata=None, match=0):\n super().__init__(\"TlOutputItem\")\n\n self.match = match\n self.data = data\n self.tdata = [None] * 4\n if tdata is not None:\n for i in range(4):\n self.tdata[i] = tdata[i]\n\n def randomize(self):\n data = \"\"\n for i in range(31): # Sic. Last bit of PC is always 0\n data += random.choice([\"0\", \"1\"])\n data += \"0\"\n\n self.data = int(data, 2)\n\n self.match = 0\n for i in range(4):\n matching = random.choice([False, True])\n trigger = self.random_trigger(data, matching)\n self.match |= trigger[\"match\"] << i\n self.tdata[i] = trigger[\"tdata\"]\n\n def random_trigger(self, data, matching):\n \"\"\"\n Creates a trigger packet for data vector.\n\n It can be precised if the packet will be matching or not.\n \"\"\"\n\n # Select determines if we match against the PC or opcode,\n # TL in TLU does the first thing\n match = \"\"\n tdata = \"\"\n\n # Generate the matched part\n length = 0\n if matching:\n length = random.randrange(32 + 1)\n if length > 0:\n tdata += data[:length]\n else:\n length = random.randrange(1, 32)\n for i in range(length):\n tdata += random.choice([\"0\", \"1\"])\n\n # Assure a mismatch\n i = random.randrange(length)\n b = \"1\" if data[i] == \"0\" else \"0\"\n tdata = tdata[:i] + b + tdata[i + 1 :]\n\n # Generate the mask\n length = 32 - length\n if length == 0:\n match = \"0\" # Do full match\n else:\n match = \"1\"\n tdata += \"0\" + \"1\" * (length - 1)\n\n return {\"match\": int(match, 2), \"tdata\": int(tdata, 2)}\n\n\nclass TlOutputItem(uvm_sequence_item):\n \"\"\"\n Trigger Logic output data\n \"\"\"\n\n def __init__(self, matches):\n super().__init__(\"TlOutputItem\")\n\n self.matches = matches\n\n\n# ==============================================================================\n\n\nclass TlDriver(uvm_driver):\n \"\"\"\n Trigger Logic driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, TlInputItem):\n self.dut.dec_i0_pc_d.value = it.data >> 1\n\n for i in range(4):\n self.dut.tdata[i].value = it.tdata[i]\n\n self.dut.match.value = it.match\n\n self.dut.select.value = 0b0000\n self.dut.store.value = 0b1111\n self.dut.load.value = 0b1111\n self.dut.execute.value = 0b1111\n self.dut.m.value = 0b1111\n\n # Wait for monitors to read the values\n await Timer(period, \"ns\")\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass TlInputMonitor(uvm_component):\n \"\"\"\n Monitor for Trigger Logic inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n while True:\n # Wait for the driver to set the input signals\n await Timer(period, \"ns\")\n\n data = int(self.dut.dec_i0_pc_d.value)\n tdata = [None] * 4\n\n for i in range(4):\n tdata[i] = int(self.dut.tdata[i].value)\n\n match = int(self.dut.match.value)\n\n self.ap.write(TlInputItem(data, tdata, match))\n\n\nclass TlOutputMonitor(uvm_component):\n \"\"\"\n Monitor for Trigger Logic outputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n while True:\n # Wait for the driver to set the input signals\n await Timer(period, \"ns\")\n\n matches = int(self.dut.dec_i0_trigger_match_d.value)\n\n self.ap.write(TlOutputItem(matches))\n\n\n# ==============================================================================\n\n\nclass TlScoreboard(uvm_component):\n \"\"\"\n Trigger Logic scoreboard\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self):\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n # Change outputs to str and reproduce what TL does\n res = 0\n match = item_inp.match\n data = f\"{item_inp.data:031b}\"\n for i in range(4):\n tdata = f\"{item_inp.tdata[i] >> 1:031b}\"\n if match & (1 << i):\n length = tdata.rindex(\"0\")\n res |= (tdata[:length] == data[:length]) << i\n else:\n res |= (tdata == data) << i\n\n if item_out.matches != res:\n self.logger.error(f\"Expected {res:04b} got {item_out.matches:04b}\")\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass TlSequence(uvm_sequence):\n \"\"\"\n Base sequence of randomized 32-bit A and B operands along with operators\n picked randomly from the allowed set\n \"\"\"\n\n def __init__(self, name, ops=None):\n super().__init__(name)\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n\n for i in range(count):\n item = TlInputItem()\n item.randomize()\n\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 5000)\n\n # Sequencers\n self.tl_seqr = uvm_sequencer(\"tl_seqr\", self)\n\n # Driver\n self.tl_drv = TlDriver(\"tl_drv\", self, dut=cocotb.top)\n\n # Monitors\n self.inp_mon = TlInputMonitor(\"inp_mon\", self, dut=cocotb.top)\n self.out_mon = TlOutputMonitor(\"out_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = TlScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.tl_drv.seq_item_port.connect(self.tl_seqr.seq_item_export)\n\n self.inp_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.out_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/dec_tlu_ctl/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_dec_tlu_ctl_wrapper\nCM_FILE = cm.cfg\n\nEXTRA_ARGS = -I$(SRCDIR)/include/\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/dec/el2_dec_pmp_ctl.sv \\\n $(SRCDIR)/dec/el2_dec_tlu_ctl.sv \\\n $(TEST_DIR)/el2_tlu_ctl_wrapper.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/dec_tlu_ctl/cm.cfg", "content": "+tree el2_dec_tlu_ctl_wrapper.dut\n\n///////////////////////////////// dec_tlu_ctl /////////////////////////////////\n// Tied to '0\n-node el2_dec_tlu_ctl_wrapper.dut.dcsr[14]\n-node el2_dec_tlu_ctl_wrapper.dut.dcsr[9]\n-node el2_dec_tlu_ctl_wrapper.dut.dcsr[5:4]\n-node el2_dec_tlu_ctl_wrapper.dut.dcsr_ns[14]\n-node el2_dec_tlu_ctl_wrapper.dut.dcsr_ns[9]\n-node el2_dec_tlu_ctl_wrapper.dut.dcsr_ns[5:4]\n-node el2_dec_tlu_ctl_wrapper.dut.ifu_mscause[2]\n-node el2_dec_tlu_ctl_wrapper.dut.mcgc[6]\n-node el2_dec_tlu_ctl_wrapper.dut.mcgc_int[6]\n-node el2_dec_tlu_ctl_wrapper.dut.mcgc_ns[6]\n-node el2_dec_tlu_ctl_wrapper.dut.mcountinhibit[1]\n-node el2_dec_tlu_ctl_wrapper.dut.mepc_rf[0]\n-node el2_dec_tlu_ctl_wrapper.dut.mie_rf[31]\n-node el2_dec_tlu_ctl_wrapper.dut.mie_rf[27:12]\n-node el2_dec_tlu_ctl_wrapper.dut.mie_rf[10:8]\n-node el2_dec_tlu_ctl_wrapper.dut.mie_rf[6:4]\n-node el2_dec_tlu_ctl_wrapper.dut.mie_rf[2:0]\n-node el2_dec_tlu_ctl_wrapper.dut.mip_rf[27:12]\n-node el2_dec_tlu_ctl_wrapper.dut.mip_rf[10:8]\n-node el2_dec_tlu_ctl_wrapper.dut.mip_rf[6:4]\n-node el2_dec_tlu_ctl_wrapper.dut.mip_rf[2:0]\n-node el2_dec_tlu_ctl_wrapper.dut.mstatus_rf[31:17]\n-node el2_dec_tlu_ctl_wrapper.dut.mstatus_rf[15:12]\n-node el2_dec_tlu_ctl_wrapper.dut.mstatus_rf[10:8]\n-node el2_dec_tlu_ctl_wrapper.dut.mstatus_rf[6:4]\n-node el2_dec_tlu_ctl_wrapper.dut.mstatus_rf[2:0]\n-node el2_dec_tlu_ctl_wrapper.dut.mtdata1_tsel_out[26]\n-node el2_dec_tlu_ctl_wrapper.dut.mtdata1_tsel_out[18:13]\n-node el2_dec_tlu_ctl_wrapper.dut.mtdata1_tsel_out[10:8]\n-node el2_dec_tlu_ctl_wrapper.dut.mtdata1_tsel_out[5:3]\n-node el2_dec_tlu_ctl_wrapper.dut.mtvec_rf[1]\n\n/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////\n// Tied to '0\n-node el2_dec_tlu_ctl_wrapper.dut.pmp.*pmpcfg_ff.din[6:5]\n-node el2_dec_tlu_ctl_wrapper.dut.pmp.*pmpcfg_ff.dout[6:5]\n-node el2_dec_tlu_ctl_wrapper.dut.pmp.*csr_wdata[6:5]\n\n// Aggregation of four 'el2_pmp_cfg_pkt_t' entries\n// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0\n-node el2_dec_tlu_ctl_wrapper.dut.pmp.pmp_pmpcfg_rddata[30:29]\n-node el2_dec_tlu_ctl_wrapper.dut.pmp.pmp_pmpcfg_rddata[22:21]\n-node el2_dec_tlu_ctl_wrapper.dut.pmp.pmp_pmpcfg_rddata[14:13]\n-node el2_dec_tlu_ctl_wrapper.dut.pmp.pmp_pmpcfg_rddata[6:5]\n" }, { "path": "verification/block/dec_tlu_ctl/common.py", "content": "from random import randrange\n\nfrom pyuvm import ConfigDB, uvm_sequence\nfrom testbench import PMPCheckItem\n\n\nclass BaseSequence(uvm_sequence):\n MAX_ADDR = 2**32 - 4\n\n def __init__(self, name):\n super().__init__(name)\n\n self.pmp_regs = ConfigDB().get(None, \"\", \"PMP_CSRS\")\n self.pmp_seqr = ConfigDB().get(None, \"\", \"PMP_SEQR\")\n self.pmp_channels = ConfigDB().get(None, \"\", \"PMP_CHANNELS\")\n\n # Access (R, W, X) memory at a given address on all channels\n async def accessAtAddr(self, addr):\n for t in range(3):\n type = 1 << t\n for c in range(self.pmp_channels):\n item = PMPCheckItem(channel=c, addr=addr, type=type)\n await self.pmp_seqr.start_item(item)\n await self.pmp_seqr.finish_item(item)\n\n # Try to access memory at random locations in a given address range\n async def randomAccessInAddrRange(self, start_addr, end_addr):\n addr = randrange(start_addr, end_addr, 4)\n await self.accessAtAddr(addr)\n\n # Access memory at a given address and at adjacent addresses\n async def checkRangeBoundary(self, addr):\n # Ensure access address is always aligned and doesn't extend 32 bits,\n # address is assumed to be inclusive so increment it by 1 initially.\n addr = min(self.MAX_ADDR, (addr + 1) & 0xFFFFFFFC)\n\n if addr >= 4:\n await self.accessAtAddr(addr - 4)\n await self.accessAtAddr(addr)\n if addr < self.MAX_ADDR:\n await self.accessAtAddr(addr + 4)\n" }, { "path": "verification/block/dec_tlu_ctl/el2_tlu_ctl_wrapper.sv", "content": "module el2_dec_tlu_ctl_wrapper\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n )\n (\n input logic clk,\n input logic free_clk,\n input logic free_l2clk,\n input logic rst_l,\n // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.\n /*pragma coverage off*/\n input logic scan_mode,\n /*pragma coverage on*/\n\n //rst_vec is supposed to be connected to constant in the top level\n /*pragma coverage off*/\n input logic [31:1] rst_vec, // reset vector, from core pins\n /*pragma coverage on*/\n input logic nmi_int, // nmi pin\n //nmi_vec is supposed to be connected to constant in the top level\n /*pragma coverage off*/\n input logic [31:1] nmi_vec, // nmi vector\n /*pragma coverage on*/\n input logic i_cpu_halt_req, // Asynchronous Halt request to CPU\n input logic i_cpu_run_req, // Asynchronous Restart request to CPU\n\n input logic lsu_fastint_stall_any, // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle\n\n\n // perf counter inputs\n input logic ifu_pmu_instr_aligned, // aligned instructions\n input logic ifu_pmu_fetch_stall, // fetch unit stalled\n input logic ifu_pmu_ic_miss, // icache miss\n input logic ifu_pmu_ic_hit, // icache hit\n input logic ifu_pmu_bus_error, // Instruction side bus error\n input logic ifu_pmu_bus_busy, // Instruction side bus busy\n input logic ifu_pmu_bus_trxn, // Instruction side bus transaction\n input logic dec_pmu_instr_decoded, // decoded instructions\n input logic dec_pmu_decode_stall, // decode stall\n input logic dec_pmu_presync_stall, // decode stall due to presync'd inst\n input logic dec_pmu_postsync_stall,// decode stall due to postsync'd inst\n input logic lsu_store_stall_any, // SB or WB is full, stall decode\n input logic dma_dccm_stall_any, // DMA stall of lsu\n input logic dma_iccm_stall_any, // DMA stall of ifu\n input logic exu_pmu_i0_br_misp, // pipe 0 branch misp\n input logic exu_pmu_i0_br_ataken, // pipe 0 branch actual taken\n input logic exu_pmu_i0_pc4, // pipe 0 4 byte branch\n input logic lsu_pmu_bus_trxn, // D side bus transaction\n input logic lsu_pmu_bus_misaligned, // D side bus misaligned\n input logic lsu_pmu_bus_error, // D side bus error\n input logic lsu_pmu_bus_busy, // D side bus busy\n input logic lsu_pmu_load_external_m, // D side bus load\n input logic lsu_pmu_store_external_m, // D side bus store\n input logic dma_pmu_dccm_read, // DMA DCCM read\n input logic dma_pmu_dccm_write, // DMA DCCM write\n input logic dma_pmu_any_read, // DMA read\n input logic dma_pmu_any_write, // DMA write\n\n input logic [31:1] lsu_fir_addr, // Fast int address\n input logic [1:0] lsu_fir_error, // Fast int lookup error\n\n input logic iccm_dma_sb_error, // I side dma single bit error\n\n input logic lsu_single_ecc_error_incr, // LSU inc SB error counter\n\n input logic dec_pause_state, // Pause counter not zero\n input logic lsu_imprecise_error_store_any, // store bus error\n input logic lsu_imprecise_error_load_any, // store bus error\n input logic [31:0] lsu_imprecise_error_addr_any, // store bus error address\n\n input logic dec_csr_wen_unq_d, // valid csr with write - for csr legal\n input logic dec_csr_any_unq_d, // valid csr - for csr legal\n input logic [11:0] dec_csr_rdaddr_d, // read address for csr\n\n input logic dec_csr_wen_r, // csr write enable at wb\n input logic [11:0] dec_csr_rdaddr_r, // read address for csr\n input logic [11:0] dec_csr_wraddr_r, // write address for csr\n input logic [31:0] dec_csr_wrdata_r, // csr write data at wb\n\n input logic dec_csr_stall_int_ff, // csr is mie/mstatus\n\n input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid\n\n input logic [31:1] exu_npc_r, // for NPC tracking\n\n input logic [31:1] dec_tlu_i0_pc_r, // for PC/NPC tracking\n\n\n input logic [31:0] dec_illegal_inst, // For mtval\n input logic dec_i0_decode_d, // decode valid, used for clean icache diagnostics\n\n // branch info from pipe0 for errors or counter updates\n input logic [1:0] exu_i0_br_hist_r, // history\n input logic exu_i0_br_error_r, // error\n input logic exu_i0_br_start_error_r, // start error\n input logic exu_i0_br_valid_r, // valid\n input logic exu_i0_br_mp_r, // mispredict\n input logic exu_i0_br_middle_r, // middle of bank\n\n // branch info from pipe1 for errors or counter updates\n\n input logic exu_i0_br_way_r, // way hit or repl\n\n output logic dec_tlu_core_empty, // core is empty\n // Debug start\n output logic dec_dbg_cmd_done, // abstract command done\n output logic dec_dbg_cmd_fail, // abstract command failed\n output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command\n output logic dec_tlu_debug_mode, // Core is in debug mode\n output logic dec_tlu_resume_ack, // Resume acknowledge\n output logic dec_tlu_debug_stall, // stall decode while waiting on core to empty\n\n output logic dec_tlu_flush_noredir_r , // Tell fetch to idle on this flush\n output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC\n output logic dec_tlu_flush_leak_one_r, // single step\n output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc. This is the D stage of the error\n\n output logic dec_tlu_flush_extint, // fast ext int started\n output logic [31:2] dec_tlu_meihap, // meihap for fast int\n\n input logic dbg_halt_req, // DM requests a halt\n input logic dbg_resume_req, // DM requests a resume\n input logic ifu_miss_state_idle, // I-side miss buffer empty\n input logic lsu_idle_any, // lsu is idle\n input logic dec_div_active, // oop div is active\n\n // el2_trigger_pkt_t broken down to allow driving from cocotb by both SIMs\n // info needed by debug trigger blocks\n output logic [3:0] trigger_pkt_any_select,\n output logic [3:0] trigger_pkt_any_match,\n output logic [3:0] trigger_pkt_any_store,\n output logic [3:0] trigger_pkt_any_load,\n output logic [3:0] trigger_pkt_any_execute,\n output logic [3:0] trigger_pkt_any_m,\n output logic [3:0][31:0] trigger_pkt_any_tdata2,\n\n input logic ifu_ic_error_start, // IC single bit error\n input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error\n\n\n input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data\n input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid\n output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics\n // Debug end\n\n input logic [7:0] pic_claimid, // pic claimid for csr\n input logic [3:0] pic_pl, // pic priv level for csr\n input logic mhwakeup, // high priority external int, wakeup if halted\n\n input logic mexintpend, // external interrupt pending\n input logic timer_int, // timer interrupt pending\n input logic soft_int, // software interrupt pending\n\n output logic o_cpu_halt_status, // PMU interface, halted\n output logic o_cpu_halt_ack, // halt req ack\n output logic o_cpu_run_ack, // run req ack\n output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request\n\n /*pragma coverage off*/\n input logic [31:4] core_id, // Core ID\n /*pragma coverage on*/\n\n // external MPC halt/run interface\n input logic mpc_debug_halt_req, // Async halt request\n input logic mpc_debug_run_req, // Async run request\n input logic mpc_reset_run_req, // Run/halt after reset\n output logic mpc_debug_halt_ack, // Halt ack\n output logic mpc_debug_run_ack, // Run ack\n output logic debug_brkpt_status, // debug breakpoint\n\n output logic [3:0] dec_tlu_meicurpl, // to PIC\n output logic [3:0] dec_tlu_meipt, // to PIC\n\n\n output logic [31:0] dec_csr_rddata_d, // csr read data at wb\n output logic dec_csr_legal_d, // csr indicates legal operation\n\n output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp\n\n output logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state\n output logic dec_tlu_flush_lower_wb, // commit has a flush (exception, int, mispredict at e4)\n output logic dec_tlu_i0_commit_cmt, // committed an instruction\n\n output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state\n output logic dec_tlu_flush_lower_r, // commit has a flush (exception, int)\n output logic [31:1] dec_tlu_flush_path_r, // flush pc\n output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache\n output logic dec_tlu_wr_pause_r, // CSR write to pause reg is at R.\n output logic dec_tlu_flush_pause_r, // Flush is due to pause\n\n output logic dec_tlu_presync_d, // CSR read needs to be presync'd\n output logic dec_tlu_postsync_d, // CSR needs to be presync'd\n\n\n output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control\n\n output logic dec_tlu_force_halt, // halt has been forced\n\n output logic dec_tlu_perfcnt0, // toggles when pipe0 perf counter 0 has an event inc\n output logic dec_tlu_perfcnt1, // toggles when pipe0 perf counter 1 has an event inc\n output logic dec_tlu_perfcnt2, // toggles when pipe0 perf counter 2 has an event inc\n output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc\n\n output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid\n output logic dec_tlu_i0_valid_wb1, // pipe 0 valid\n output logic dec_tlu_int_valid_wb1, // pipe 2 int valid\n output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause\n output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value\n\n // feature disable from mfdc\n output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding\n output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address\n output logic dec_tlu_core_ecc_disable, // disable core ECC\n output logic dec_tlu_bpred_disable, // disable branch prediction\n output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing\n output logic dec_tlu_pipelining_disable, // disable pipelining\n output logic dec_tlu_trace_disable, // disable trace\n output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16]\n\n // clock gating overrides from mcgc\n output logic dec_tlu_misc_clk_override, // override misc clock domain gating\n output logic dec_tlu_dec_clk_override, // override decode clock domain gating\n output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating\n output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating\n output logic dec_tlu_bus_clk_override, // override bus clock domain gating\n output logic dec_tlu_pic_clk_override, // override PIC clock domain gating\n output logic dec_tlu_picio_clk_override,// override PICIO clock domain gating\n output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating\n output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating\n\n`ifdef RV_USER_MODE\n\n // Privilege mode\n // 0 - machine, 1 - user\n output logic priv_mode,\n output logic priv_mode_eff,\n output logic priv_mode_ns,\n\n // mseccfg CSR content for PMP\n output logic [2:0] mseccfg,\n\n`endif\n\n // pmp\n output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],\n output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES]\n );\n\n\n el2_lsu_error_pkt_t lsu_error_pkt_r;\n el2_trap_pkt_t dec_tlu_packet_r;\n\n el2_trigger_pkt_t [3:0] trigger_pkt_any;\n // Unwrap structure support both simulators\n for (genvar i = 0; i < 4; i++) begin : g_unwrap_el2_trigger_pkt_t\n assign trigger_pkt_any_select[i] = trigger_pkt_any[i][37];\n assign trigger_pkt_any_match[i] = trigger_pkt_any[i][36];\n assign trigger_pkt_any_store[i] = trigger_pkt_any[i][35];\n assign trigger_pkt_any_load[i] = trigger_pkt_any[i][34];\n assign trigger_pkt_any_execute[i] = trigger_pkt_any[i][33];\n assign trigger_pkt_any_m[i] = trigger_pkt_any[i][32];\n assign trigger_pkt_any_tdata2[i] = trigger_pkt_any[i][31:0];\n end\n\n assign lsu_error_pkt_r = '0;\n assign dec_tlu_packet_r = '0;\n\nel2_dec_tlu_ctl dut (\n .lsu_error_pkt_r(lsu_error_pkt_r),\n .dec_tlu_packet_r(dec_tlu_packet_r),\n .*\n);\nendmodule\n" }, { "path": "verification/block/dec_tlu_ctl/test_dec_tl.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseTest, TlSequence\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestMeihap(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n ConfigDB().set(None, \"*\", \"TEST\", \"meihap\")\n self.seq = TlSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.tl_seqr)\n\n\n@pyuvm.test()\nclass TestMtdata(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n ConfigDB().set(None, \"*\", \"TEST\", \"mtdata\")\n self.seq = TlSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.tl_seqr)\n\n\n@pyuvm.test()\nclass TestMhpme(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n ConfigDB().set(None, \"*\", \"TEST\", \"mhpme\")\n self.seq = TlSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.tl_seqr)\n\n\n@pyuvm.test()\nclass TestMdseac(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n ConfigDB().set(None, \"*\", \"TEST\", \"mdseac\")\n self.seq = TlSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.tl_seqr)\n\n\n@pyuvm.test()\nclass TestCsrAccess(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n ConfigDB().set(None, \"*\", \"TEST\", \"csrs_access\")\n self.seq = TlSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.tl_seqr)\n\n\n@pyuvm.test()\nclass TestDebugCSRs(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n ConfigDB().set(None, \"*\", \"TEST\", \"debug_csrs_access\")\n self.seq = TlSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.tl_seqr)\n\n\n@pyuvm.test()\nclass TestDebugICCache(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n ConfigDB().set(None, \"*\", \"TEST\", \"debug_ic_cache\")\n self.seq = TlSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.tl_seqr)\n" }, { "path": "verification/block/dec_tlu_ctl/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport copy\nimport math\nimport os\nimport random\nimport struct\nfrom dataclasses import dataclass\n\nimport csrs\nimport pyuvm\nfrom cocotb.binary import BinaryValue\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import (\n ClockCycles,\n Event,\n FallingEdge,\n First,\n Lock,\n RisingEdge,\n Timer,\n)\nfrom cocotb.types import Array, Range\nfrom pyuvm import *\n\n# ==============================================================================\n\ncsr_list = [getattr(csrs, mod) for mod in dir(csrs) if isinstance(getattr(csrs, mod), csrs.CSR)]\n\n\n@dataclass\nclass TriggerAnyPktT:\n select: int = 0\n match: int = 0\n store: int = 0\n load: int = 0\n execute: int = 0\n m: int = 0\n tdata2: int = 0\n\n @staticmethod\n def get_from_dut(dut):\n trigger_pkt_any_select = int(dut.trigger_pkt_any_select.value)\n trigger_pkt_any_match = int(dut.trigger_pkt_any_match.value)\n trigger_pkt_any_store = int(dut.trigger_pkt_any_store.value)\n trigger_pkt_any_load = int(dut.trigger_pkt_any_load.value)\n trigger_pkt_any_execute = int(dut.trigger_pkt_any_execute.value)\n trigger_pkt_any_m = int(dut.trigger_pkt_any_m.value)\n trigger_pkt_any_tdata2 = int(dut.trigger_pkt_any_tdata2.value)\n return TriggerAnyPktT(\n trigger_pkt_any_select,\n trigger_pkt_any_match,\n trigger_pkt_any_store,\n trigger_pkt_any_load,\n trigger_pkt_any_execute,\n trigger_pkt_any_m,\n trigger_pkt_any_tdata2,\n )\n\n\nclass TlInputItem(uvm_sequence_item):\n \"\"\"\n Trigger Logic output data\n \"\"\"\n\n def __init__(\n self,\n pic_claimid=0,\n dec_csr_wrdata_r=0,\n mtdata1=0,\n mtdata2=0,\n mtsel=0,\n mdeau=0,\n csr_addr=0,\n dec_csr_rddata_d=0,\n ifu_ic_debug_rd_data=0,\n lsu_imprecise_error_addr_any=0,\n ):\n super().__init__(\"TlOutputItem\")\n\n self.pic_claimid = pic_claimid\n self.dec_csr_wrdata_r = dec_csr_wrdata_r\n self.mtdata1 = mtdata1\n self.mtdata2 = mtdata2\n self.mtsel = mtsel\n self.csr_addr = csr_addr\n self.mtsel = mtsel\n self.mdeau = mdeau\n self.dec_csr_rddata_d = dec_csr_rddata_d\n self.ifu_ic_debug_rd_data = ifu_ic_debug_rd_data\n self.lsu_imprecise_error_addr_any = lsu_imprecise_error_addr_any\n\n def randomize(self, test):\n\n if test == \"meihap\":\n pic_claimid = \"\"\n # CSR\n dec_csr_wrdata_r = \"\"\n for _ in range(8):\n pic_claimid += random.choice([\"0\", \"1\"])\n\n for _ in range(22):\n dec_csr_wrdata_r += random.choice([\"0\", \"1\"])\n\n self.pic_claimid = int(pic_claimid, 2)\n self.dec_csr_wrdata_r = int(dec_csr_wrdata_r, 2) << 10\n elif test == \"mhpme\":\n value = \"\"\n for _ in range(10):\n value += random.choice([\"0\", \"1\"])\n self.dec_csr_wrdata_r = int(value, 2)\n self.csr_addr = random.choice(\n [\n csrs.MHPME3,\n csrs.MHPME4,\n csrs.MHPME5,\n csrs.MHPME6,\n ]\n )\n elif test == \"mtdata\":\n # bits 31:28 are hardcoded to 0x2\n mtdata1 = \"0010\"\n mtdata2 = \"\"\n mtsel = \"\"\n for _ in range(28):\n mtdata1 += random.choice([\"0\", \"1\"])\n # set DMODE (bit 27) to 0 so that the settigs are actually taken into account\n # in the list, bits are nubered from 0\n tmp = list(mtdata1)\n tmp[31 - 27] = \"0\"\n mtdata1 = \"\".join(tmp)\n self.mtdata1 = int(mtdata1, 2)\n for _ in range(32):\n mtdata2 += random.choice([\"0\", \"1\"])\n self.mtdata2 = int(mtdata2, 2)\n for _ in range(2):\n mtsel += random.choice([\"0\", \"1\"])\n self.mtsel = int(mtsel, 2)\n elif test == \"mdseac\":\n mdeau = \"\"\n for _ in range(32):\n mdeau += random.choice([\"0\", \"1\"])\n self.mdeau = int(mdeau, 2)\n value = \"\"\n for _ in range(32):\n value += random.choice([\"0\", \"1\"])\n self.lsu_imprecise_error_addr_any = int(value, 2)\n self.csr_addr = csrs.MDSEAC\n elif test == \"csrs_access\":\n value = \"\"\n for _ in range(32):\n value += random.choice([\"0\", \"1\"])\n self.dec_csr_wrdata_r = int(value, 2)\n self.csr_addr = random.choice(\n [\n csrs.MHPMC3,\n csrs.MHPMC3H,\n csrs.MHPMC4,\n csrs.MHPMC4H,\n csrs.MHPMC5,\n csrs.MHPMC5H,\n csrs.MHPMC6,\n csrs.MHPMC6H,\n csrs.MCYCLEL,\n csrs.MCYCLEH,\n csrs.MINSTRETL,\n csrs.MINSTRETH,\n csrs.MICECT,\n csrs.MICCMECT,\n csrs.MDCCMECT,\n csrs.MTVEC,\n csrs.MHPME3,\n csrs.MHPME4,\n csrs.MHPME5,\n csrs.MHPME6,\n csrs.MRAC,\n csrs.MEIPT,\n csrs.MCOUNTINHIBIT,\n csrs.MFDHT,\n csrs.MEICURPL,\n csrs.MFDC,\n ]\n )\n elif test == \"debug_csrs_access\":\n value = \"\"\n for _ in range(32):\n value += random.choice([\"0\", \"1\"])\n self.dec_csr_wrdata_r = int(value, 2)\n self.csr_addr = random.choice(\n [csrs.DICAD0, csrs.DICAD0H, csrs.DICAWICS, csrs.DPC, csrs.DCSR]\n )\n elif test == \"debug_ic_cache\":\n value = \"\"\n for _ in range(71):\n value += random.choice([\"0\", \"1\"])\n self.ifu_ic_debug_rd_data = int(value, 2)\n\n\nclass TlOutputItem(uvm_sequence_item):\n \"\"\"\n Trigger Logic output data\n \"\"\"\n\n def __init__(\n self,\n dec_tlu_meihap=0,\n mtdata1=0,\n mtdata2=0,\n mtsel=0,\n trigger_pkt_any=0,\n dec_csr_rddata_d=0,\n ifu_ic_debug_rd_data=0,\n ):\n super().__init__(\"TlOutputItem\")\n self.dec_tlu_meihap = dec_tlu_meihap\n self.mtdata1 = mtdata1\n self.mtdata2 = mtdata2\n self.mtsel = mtsel\n self.trigger_pkt_any = trigger_pkt_any\n self.dec_csr_rddata_d = dec_csr_rddata_d\n self.ifu_ic_debug_rd_data = ifu_ic_debug_rd_data\n\n\n# ==============================================================================\n\n\nclass TlDriver(uvm_driver):\n \"\"\"\n Trigger Logic driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def read_csr(self, address):\n self.dut.dec_csr_rdaddr_d.value = address\n await RisingEdge(self.dut.clk)\n\n async def write_csr(self, address, value):\n self.dut.dec_csr_wen_r.value = 0\n await RisingEdge(self.dut.clk)\n self.dut.dec_csr_wen_r.value = 1\n self.dut.dec_csr_wraddr_r.value = address\n self.dut.dec_csr_wrdata_r.value = value\n await RisingEdge(self.dut.clk)\n self.dut.dec_csr_wen_r.value = 0\n\n async def do_reset(self):\n self.dut.rst_l.value = 0\n await ClockCycles(self.dut.clk, 2)\n await FallingEdge(self.dut.clk)\n self.dut.rst_l.value = 1\n\n async def run_phase(self):\n\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, TlInputItem):\n test = ConfigDB().get(self, \"\", \"TEST\")\n if test == \"meihap\":\n # write MEIVT\n await self.write_csr(csrs.MEIVT, it.dec_csr_wrdata_r)\n # write pic_claimid\n await RisingEdge(self.dut.clk)\n self.dut.pic_claimid.value = it.pic_claimid\n self.dut.dec_csr_wen_r.value = 1\n self.dut.dec_csr_wraddr_r.value = csrs.MEICPCT\n await RisingEdge(self.dut.clk)\n self.dut.dec_csr_wen_r.value = 0\n # give two more cycles so that output monitor can catch the data on the outputs\n await RisingEdge(self.dut.clk)\n await RisingEdge(self.dut.clk)\n elif test == \"mtdata\":\n # test triggers\n await self.write_csr(csrs.MTSEL, it.mtsel)\n await self.write_csr(csrs.MTDATA1, it.mtdata1)\n await self.write_csr(csrs.MTDATA2, it.mtdata2)\n elif test == \"mdseac\":\n # Write to unlock register\n await self.write_csr(csrs.MDEAU, it.mdeau)\n if self.dut.dut.mdseac_locked_f.value:\n await FallingEdge(self.dut.mdseac_locked_f)\n await RisingEdge(self.dut.clk)\n # Write error\n self.dut.lsu_imprecise_error_addr_any.value = it.lsu_imprecise_error_addr_any\n self.dut.lsu_imprecise_error_store_any.value = 1\n await RisingEdge(self.dut.clk)\n self.dut.lsu_imprecise_error_store_any.value = 0\n await RisingEdge(self.dut.clk)\n # Read the MDSEAC register\n await self.read_csr(it.csr_addr)\n # Perform reset to clear the error\n await self.do_reset()\n elif test in [\"csrs_access\", \"mhpme\"]:\n # write a perf counter\n await self.write_csr(it.csr_addr, it.dec_csr_wrdata_r)\n # read it back\n await self.read_csr(it.csr_addr)\n elif test == \"debug_csrs_access\":\n # request halt\n self.dut.dbg_halt_req.value = 1\n for _ in range(2):\n await RisingEdge(self.dut.clk)\n # write a perf counter\n await self.write_csr(it.csr_addr, it.dec_csr_wrdata_r)\n # read it back\n await self.read_csr(it.csr_addr)\n elif test == \"debug_ic_cache\":\n self.dut.ifu_ic_debug_rd_data_valid.value = 1\n self.dut.ifu_ic_debug_rd_data.value = it.ifu_ic_debug_rd_data\n await RisingEdge(self.dut.clk)\n self.dut.ifu_ic_debug_rd_data_valid.value = 0\n self.dut.ifu_ic_debug_rd_data.value = 0\n await self.read_csr(csrs.DICAD0)\n await self.read_csr(csrs.DICAD0H)\n await self.read_csr(csrs.DICAD1)\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass TlInputMonitor(uvm_component):\n \"\"\"\n Monitor for Trigger Logic inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n\n while True:\n test = ConfigDB().get(self, \"\", \"TEST\")\n\n if test == \"meihap\":\n # Wait for the driver to set the input signals\n await RisingEdge(self.dut.dec_csr_wen_r)\n await RisingEdge(self.dut.dec_csr_wen_r)\n # for _ in range(4):\n # await RisingEdge(self.dut.clk)\n\n pic_claimid = int(self.dut.pic_claimid.value)\n meivt = int(self.dut.dec_csr_wrdata_r.value)\n\n self.ap.write(TlInputItem(pic_claimid=pic_claimid, dec_csr_wrdata_r=meivt))\n elif test == \"mtdata\":\n await RisingEdge(self.dut.dec_csr_wen_r)\n await RisingEdge(self.dut.clk)\n mtsel = int(self.dut.dec_csr_wrdata_r.value)\n await RisingEdge(self.dut.dec_csr_wen_r)\n await RisingEdge(self.dut.clk)\n mtdata1 = int(self.dut.dec_csr_wrdata_r.value)\n await RisingEdge(self.dut.dec_csr_wen_r)\n await RisingEdge(self.dut.clk)\n mtdata2 = int(self.dut.dec_csr_wrdata_r.value)\n self.ap.write(TlInputItem(mtdata1=mtdata1, mtdata2=mtdata2, mtsel=mtsel))\n elif test == \"mdseac\":\n await RisingEdge(self.dut.lsu_imprecise_error_store_any)\n await RisingEdge(self.dut.clk)\n csr_addr = int(self.dut.dec_csr_rdaddr_d.value)\n lsu_imprecise_error_addr_any = int(self.dut.lsu_imprecise_error_addr_any.value)\n self.ap.write(\n TlInputItem(\n csr_addr=csr_addr, lsu_imprecise_error_addr_any=lsu_imprecise_error_addr_any\n )\n )\n elif test in [\"csrs_access\", \"mhpme\"]:\n # wait for reg write\n await RisingEdge(self.dut.dec_csr_wen_r)\n await RisingEdge(self.dut.clk)\n csr_addr = int(self.dut.dec_csr_wraddr_r.value)\n csr_value = int(self.dut.dec_csr_wrdata_r.value)\n self.ap.write(TlInputItem(csr_addr=csr_addr, dec_csr_wrdata_r=csr_value))\n elif test == \"debug_csrs_access\":\n # wait for debug mode\n for _ in range(2):\n await RisingEdge(self.dut.clk)\n # wait for reg write\n await RisingEdge(self.dut.dec_csr_wen_r)\n await RisingEdge(self.dut.clk)\n csr_addr = int(self.dut.dec_csr_wraddr_r.value)\n csr_value = int(self.dut.dec_csr_wrdata_r.value)\n self.ap.write(TlInputItem(csr_addr=csr_addr, dec_csr_wrdata_r=csr_value))\n elif test == \"debug_ic_cache\":\n # wait for reg write\n await RisingEdge(self.dut.ifu_ic_debug_rd_data_valid)\n await RisingEdge(self.dut.clk)\n ic_debug_rd_data = int(self.dut.ifu_ic_debug_rd_data.value)\n self.ap.write(TlInputItem(ifu_ic_debug_rd_data=ic_debug_rd_data))\n\n\nclass TlOutputMonitor(uvm_component):\n \"\"\"\n Monitor for Trigger Logic outputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n\n while True:\n test = ConfigDB().get(self, \"\", \"TEST\")\n\n if test == \"meihap\":\n # Wait for the driver to set the input signals and the data goes through\n await RisingEdge(self.dut.dec_csr_wen_r)\n await RisingEdge(self.dut.dec_csr_wen_r)\n for _ in range(2):\n await RisingEdge(self.dut.clk)\n\n dec_tlu_meihap = int(self.dut.dec_tlu_meihap.value) << 2\n self.ap.write(TlOutputItem(dec_tlu_meihap))\n elif test == \"mtdata\":\n # wait for reg writes\n for _ in range(3):\n await RisingEdge(self.dut.dec_csr_wen_r)\n # wait for the outputs\n for _ in range(2):\n await RisingEdge(self.dut.clk)\n trigger_pkt_any = TriggerAnyPktT.get_from_dut(self.dut)\n self.ap.write(TlOutputItem(trigger_pkt_any=trigger_pkt_any))\n elif test == \"mdseac\":\n # Wait for when the error address is set\n await RisingEdge(self.dut.lsu_imprecise_error_store_any)\n # Wait for read\n for _ in range(3):\n await RisingEdge(self.dut.clk)\n dec_csr_rddata_d = int(self.dut.dec_csr_rddata_d.value)\n self.ap.write(TlOutputItem(dec_csr_rddata_d=dec_csr_rddata_d))\n elif test in [\"csrs_access\", \"mhpme\"]:\n # wait for reg write\n await RisingEdge(self.dut.dec_csr_wen_r)\n # wait for read\n for _ in range(2):\n await RisingEdge(self.dut.clk)\n dec_csr_rddata_d = int(self.dut.dec_csr_rddata_d.value)\n self.ap.write(TlOutputItem(dec_csr_rddata_d=dec_csr_rddata_d))\n elif test == \"debug_csrs_access\":\n # wait for debug mode\n for _ in range(2):\n await RisingEdge(self.dut.clk)\n # wait for reg write\n await RisingEdge(self.dut.dec_csr_wen_r)\n # wait for read\n for _ in range(2):\n await RisingEdge(self.dut.clk)\n dec_csr_rddata_d = int(self.dut.dec_csr_rddata_d.value)\n self.ap.write(TlOutputItem(dec_csr_rddata_d=dec_csr_rddata_d))\n elif test == \"debug_ic_cache\":\n # wait for read\n # read dicad0, dicad0h, and dicad1\n await RisingEdge(self.dut.ifu_ic_debug_rd_data_valid)\n for _ in range(2):\n await RisingEdge(self.dut.clk)\n dicad0 = int(self.dut.dec_csr_rddata_d.value)\n await RisingEdge(self.dut.clk)\n dicad0h = int(self.dut.dec_csr_rddata_d.value)\n await RisingEdge(self.dut.clk)\n dicad1 = int(self.dut.dec_csr_rddata_d.value)\n ifu_ic_debug_rd_data = dicad0 | (dicad0h << 32) | (dicad1 << 64)\n self.ap.write(TlOutputItem(ifu_ic_debug_rd_data=ifu_ic_debug_rd_data))\n\n\n# ==============================================================================\n\n\nclass TlScoreboard(uvm_component):\n \"\"\"\n Trigger Logic scoreboard\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self): # noqa: C901\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n test = ConfigDB().get(self, \"\", \"TEST\")\n\n if test == \"meihap\":\n sent_pic_claimid = item_inp.pic_claimid\n sent_meivt = item_inp.dec_csr_wrdata_r >> 12\n recv_pic_claimid = (item_out.dec_tlu_meihap >> 2) & 0xFF\n recv_meivt = item_out.dec_tlu_meihap >> 12\n\n if sent_pic_claimid != recv_pic_claimid:\n self.logger.error(\n \"pic_claimid {} != {} (should be {})\".format(\n sent_pic_claimid, recv_pic_claimid, sent_pic_claimid\n )\n )\n self.passed = False\n\n if sent_meivt != recv_meivt:\n self.logger.error(\n \"meivt {} != {} (should be {})\".format(sent_meivt, recv_meivt, sent_meivt)\n )\n self.passed = False\n elif test == \"mtdata\":\n tdata2_mask = 0xFFFFFFFF\n mtsel = item_inp.mtsel\n\n mtdata1_i = item_inp.mtdata1\n mtdata2_i = item_inp.mtdata2\n trigger_pkt_any = item_out.trigger_pkt_any\n\n select_i = (mtdata1_i >> 19) & 1\n match_i = (mtdata1_i >> 7) & 1\n store_i = (mtdata1_i >> 1) & 1\n load_i = ((mtdata1_i >> 0) & 1) & ~((mtdata1_i >> 19) & 1)\n execute_i = ((mtdata1_i >> 2) & 1) & ~((mtdata1_i >> 19) & 1)\n m_i = (mtdata1_i >> 6) & 1\n\n select_o = (trigger_pkt_any.select >> mtsel) & 1\n match_o = (trigger_pkt_any.match >> mtsel) & 1\n store_o = (trigger_pkt_any.store >> mtsel) & 1\n load_o = (trigger_pkt_any.load >> mtsel) & 1\n execute_o = (trigger_pkt_any.execute >> mtsel) & 1\n m_o = (trigger_pkt_any.m >> mtsel) & 1\n\n mtdata2_o = (trigger_pkt_any.tdata2 >> (mtsel * 32)) & tdata2_mask\n\n if mtdata2_i != mtdata2_o:\n self.logger.error(\n \"mtdata2 {} != {} (should be {})\".format(mtdata2_i, mtdata2_o, mtdata2_i)\n )\n self.passed = False\n\n if select_i != select_o:\n self.logger.error(\n \"select {} != {} (should be {})\".format(select_i, select_o, select_i)\n )\n self.passed = False\n\n if match_i != match_o:\n self.logger.error(\n \"match {} != {} (should be {})\".format(match_i, match_o, match_i)\n )\n self.passed = False\n\n if store_i != store_o:\n self.logger.error(\n \"store {} != {} (should be {})\".format(store_i, store_o, store_i)\n )\n self.passed = False\n\n if load_i != load_o:\n self.logger.error(\"load {} != {} (should be {})\".format(load_i, load_o, load_i))\n self.passed = False\n\n if execute_i != execute_o:\n self.logger.error(\n \"execute {} != {} (should be {})\".format(execute_i, execute_o, execute_i)\n )\n self.passed = False\n\n if m_i != m_o:\n self.logger.error(\"m {} != {} (should be {})\".format(m_i, m_o, m_i))\n self.passed = False\n\n elif test == \"mhpme\":\n csr = item_inp.csr_addr\n perf_reg_val_i = item_inp.dec_csr_wrdata_r\n perf_reg_val_o = item_out.dec_csr_rddata_d\n\n mhpme_lst = [csrs.MHPME3, csrs.MHPME4, csrs.MHPME5, csrs.MHPME6]\n c = [c for c in mhpme_lst if c == csr][0]\n perf_reg_val_i = c.out(perf_reg_val_i)\n\n if perf_reg_val_i != perf_reg_val_o:\n self.logger.error(\n \"reg_val[{}] {} != {} (should be {})\".format(\n hex(csr), hex(perf_reg_val_i), hex(perf_reg_val_o), hex(perf_reg_val_i)\n )\n )\n self.passed = False\n elif test == \"mdseac\":\n csr = item_inp.csr_addr\n error_val_i = item_inp.lsu_imprecise_error_addr_any\n mdseac_val_o = item_out.dec_csr_rddata_d\n\n if error_val_i != mdseac_val_o:\n self.logger.error(\n \"reg_val[{}] {} != {} (should be {})\".format(\n hex(csr), hex(error_val_i), hex(mdseac_val_o), hex(error_val_i)\n )\n )\n self.passed = False\n elif test == \"csrs_access\":\n csr = item_inp.csr_addr\n perf_reg_val_i = item_inp.dec_csr_wrdata_r\n perf_reg_val_o = item_out.dec_csr_rddata_d\n\n for c in csr_list:\n if c == csr:\n perf_reg_val_i = c.out(perf_reg_val_i)\n break\n\n if perf_reg_val_i != perf_reg_val_o:\n self.logger.error(\n \"reg_val[{}] {} != {} (should be {})\".format(\n hex(csr), hex(perf_reg_val_i), hex(perf_reg_val_o), hex(perf_reg_val_i)\n )\n )\n self.passed = False\n\n elif test == \"debug_csrs_access\":\n csr = item_inp.csr_addr\n reg_val_i = item_inp.dec_csr_wrdata_r\n reg_val_o = item_out.dec_csr_rddata_d\n\n if csr == csrs.DCSR:\n reg_val_i = csrs.DCSR.out(reg_val_i)\n elif csr == csrs.DPC:\n reg_val_i = csrs.DPC.out(reg_val_i)\n elif csr == csrs.DICAWICS:\n reg_val_i = csrs.DICAWICS.out(reg_val_i)\n\n if reg_val_i != reg_val_o:\n self.logger.error(\n \"reg_val[{}] {} != {} (should be {})\".format(\n hex(csr), hex(reg_val_i), hex(reg_val_o), hex(reg_val_i)\n )\n )\n self.passed = False\n elif test == \"debug_ic_cache\":\n ifu_ic_debug_rd_data_in = item_inp.ifu_ic_debug_rd_data\n ifu_ic_debug_rd_data_out = item_out.ifu_ic_debug_rd_data\n\n if ifu_ic_debug_rd_data_in != ifu_ic_debug_rd_data_out:\n self.logger.error(\n \"read_data {} != {} (should be {})\".format(\n hex(ifu_ic_debug_rd_data_in),\n hex(ifu_ic_debug_rd_data_out),\n hex(ifu_ic_debug_rd_data_in),\n )\n )\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass TlSequence(uvm_sequence):\n\n def __init__(self, name, ops=None):\n super().__init__(name)\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n test = ConfigDB().get(None, \"\", \"TEST\")\n\n for i in range(count):\n item = TlInputItem()\n item.randomize(test)\n\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 5000)\n\n # Sequencers\n self.tl_seqr = uvm_sequencer(\"tl_seqr\", self)\n\n # Driver\n self.tl_drv = TlDriver(\"tl_drv\", self, dut=cocotb.top)\n\n # Monitors\n self.inp_mon = TlInputMonitor(\"inp_mon\", self, dut=cocotb.top)\n self.out_mon = TlOutputMonitor(\"out_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = TlScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.tl_drv.seq_item_port.connect(self.tl_seqr.seq_item_export)\n\n self.inp_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.out_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Ba5e test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n cocotb.top.rst_vec.value = 0\n cocotb.top.nmi_int.value = 0\n cocotb.top.nmi_vec.value = 0\n cocotb.top.i_cpu_halt_req.value = 0\n cocotb.top.i_cpu_run_req.value = 0\n cocotb.top.lsu_fastint_stall_any.value = 0\n cocotb.top.ifu_pmu_instr_aligned.value = 0\n cocotb.top.ifu_pmu_fetch_stall.value = 0\n cocotb.top.ifu_pmu_ic_miss.value = 0\n cocotb.top.ifu_pmu_ic_hit.value = 0\n cocotb.top.ifu_pmu_bus_error.value = 0\n cocotb.top.ifu_pmu_bus_busy.value = 0\n cocotb.top.ifu_pmu_bus_trxn.value = 0\n cocotb.top.dec_pmu_instr_decoded.value = 0\n cocotb.top.dec_pmu_decode_stall.value = 0\n cocotb.top.dec_pmu_presync_stall.value = 0\n cocotb.top.dec_pmu_postsync_stall.value = 0\n cocotb.top.lsu_store_stall_any.value = 0\n cocotb.top.dma_dccm_stall_any.value = 0\n cocotb.top.dma_iccm_stall_any.value = 0\n cocotb.top.exu_pmu_i0_br_misp.value = 0\n cocotb.top.exu_pmu_i0_br_ataken.value = 0\n cocotb.top.exu_pmu_i0_pc4.value = 0\n cocotb.top.lsu_pmu_bus_trxn.value = 0\n cocotb.top.lsu_pmu_bus_misaligned.value = 0\n cocotb.top.lsu_pmu_bus_error.value = 0\n cocotb.top.lsu_pmu_bus_busy.value = 0\n cocotb.top.lsu_pmu_load_external_m.value = 0\n cocotb.top.lsu_pmu_store_external_m.value = 0\n cocotb.top.dma_pmu_dccm_read.value = 0\n cocotb.top.dma_pmu_dccm_write.value = 0\n cocotb.top.dma_pmu_any_read.value = 0\n cocotb.top.dma_pmu_any_write.value = 0\n cocotb.top.lsu_fir_addr.value = 0\n cocotb.top.lsu_fir_error.value = 0\n cocotb.top.iccm_dma_sb_error.value = 0\n cocotb.top.lsu_single_ecc_error_incr.value = 0\n cocotb.top.dec_pause_state.value = 0\n cocotb.top.lsu_imprecise_error_store_any.value = 0\n cocotb.top.lsu_imprecise_error_load_any.value = 0\n cocotb.top.lsu_imprecise_error_addr_any.value = 0\n cocotb.top.dec_csr_wen_unq_d.value = 0\n cocotb.top.dec_csr_any_unq_d.value = 0\n cocotb.top.dec_csr_rdaddr_d.value = 0\n cocotb.top.dec_csr_wen_r.value = 0\n cocotb.top.dec_csr_rdaddr_r.value = 0\n cocotb.top.dec_csr_wraddr_r.value = 0\n cocotb.top.dec_csr_wrdata_r.value = 0\n cocotb.top.dec_csr_stall_int_ff.value = 0\n cocotb.top.dec_tlu_i0_valid_r.value = 0\n cocotb.top.exu_npc_r.value = 0\n cocotb.top.dec_tlu_i0_pc_r.value = 0\n cocotb.top.dec_illegal_inst.value = 0\n cocotb.top.dec_i0_decode_d.value = 0\n cocotb.top.exu_i0_br_hist_r.value = 0\n cocotb.top.exu_i0_br_error_r.value = 0\n cocotb.top.exu_i0_br_start_error_r.value = 0\n cocotb.top.exu_i0_br_valid_r.value = 0\n cocotb.top.exu_i0_br_mp_r.value = 0\n cocotb.top.exu_i0_br_middle_r.value = 0\n cocotb.top.exu_i0_br_way_r.value = 0\n cocotb.top.dbg_halt_req.value = 0\n cocotb.top.dbg_resume_req.value = 0\n cocotb.top.ifu_miss_state_idle.value = 0\n cocotb.top.lsu_idle_any.value = 0\n cocotb.top.dec_div_active.value = 0\n cocotb.top.ifu_ic_error_start.value = 0\n cocotb.top.ifu_iccm_rd_ecc_single_err.value = 0\n cocotb.top.ifu_ic_debug_rd_data.value = 0\n cocotb.top.ifu_ic_debug_rd_data_valid.value = 0\n cocotb.top.pic_claimid.value = 0\n cocotb.top.pic_pl.value = 0\n cocotb.top.mhwakeup.value = 0\n cocotb.top.mexintpend.value = 0\n cocotb.top.timer_int.value = 0\n cocotb.top.soft_int.value = 0\n cocotb.top.core_id.value = 0\n cocotb.top.mpc_debug_halt_req.value = 0\n cocotb.top.mpc_debug_run_req.value = 0\n cocotb.top.mpc_reset_run_req.value = 0\n\n # Start clocks\n self.start_clock(\"free_l2clk\")\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/dma/Makefile", "content": "\nnull :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_dma_ctrl\nCM_FILE = cm.cfg\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/el2_dma_ctrl.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/dma/cm.cfg", "content": "+tree el2_dma_ctrl\n\n// 'start_addr' and 'region' are tied to module parameters\n-node el2_dma_ctrl.*rangecheck.start_addr\n-node el2_dma_ctrl.*rangecheck.region\n" }, { "path": "verification/block/dma/scoreboards.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport struct\nfrom collections import defaultdict\n\nfrom pyuvm import ConfigDB, uvm_component, uvm_get_port, uvm_tlm_analysis_fifo\nfrom testbench import (\n BusReadItem,\n BusWriteItem,\n DebugReadItem,\n DebugWriteItem,\n MemReadItem,\n MemWriteItem,\n)\n\n# =============================================================================\n\n\nclass ReadScoreboard(uvm_component):\n \"\"\"\n A scoreboard that counts reads that happen on the debug/AXI and memory\n sides of the DMA module\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n self.iccm_base = ConfigDB().get(None, \"\", \"ICCM_BASE\")\n self.iccm_size = ConfigDB().get(None, \"\", \"ICCM_SIZE\")\n\n self.dccm_base = ConfigDB().get(None, \"\", \"DCCM_BASE\")\n self.dccm_size = ConfigDB().get(None, \"\", \"DCCM_SIZE\")\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def is_iccm(self, addr):\n return addr >= self.iccm_base and addr < (self.iccm_base + self.iccm_size)\n\n def is_dccm(self, addr):\n return addr >= self.dccm_base and addr < (self.dccm_base + self.dccm_size)\n\n def check_phase(self):\n iccm_reads = defaultdict(lambda: 0)\n dccm_reads = defaultdict(lambda: 0)\n\n # Process writes\n while self.port.can_get():\n # Get an item\n got_item, item = self.port.try_get()\n assert got_item\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # AXI read. Check and decode its address\n if isinstance(item, BusReadItem):\n # FIXME: Assuming the transaction is 64-bit wide\n data = struct.unpack(\"= 3: # FIXME: Unclear\n data = item.data\n else:\n self.logger.error(\"Invalid transaction size {}\".format(item.size))\n self.passed = False\n\n if item.mem == \"ICCM\":\n iccm_reads[\n (\n item.addr,\n data,\n )\n ] += 1\n elif item.mem == \"DCCM\":\n dccm_reads[\n (\n item.addr,\n data,\n )\n ] += 1\n else:\n self.logger.error(\"Read from an unknown memory region '{}'\".format(item.mem))\n self.passed = False\n\n # Check if there is an even number of reads for (each address, data)\n # for each memory region.\n for name, d in [(\"ICCM\", iccm_reads), (\"DCCM\", dccm_reads)]:\n for key, count in d.items():\n if count & 1:\n self.logger.error(\n \"{} read count from 0x{:08X} is odd, data {}\".format(name, key[0], key[1])\n )\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# =============================================================================\n\n\nclass WriteScoreboard(uvm_component):\n \"\"\"\n A scoreboard that counts writes that happen on the debug/AXI and memory\n sides of the DMA module.\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n self.iccm_base = ConfigDB().get(None, \"\", \"ICCM_BASE\")\n self.iccm_size = ConfigDB().get(None, \"\", \"ICCM_SIZE\")\n\n self.dccm_base = ConfigDB().get(None, \"\", \"DCCM_BASE\")\n self.dccm_size = ConfigDB().get(None, \"\", \"DCCM_SIZE\")\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def is_iccm(self, addr):\n return addr >= self.iccm_base and addr < (self.iccm_base + self.iccm_size)\n\n def is_dccm(self, addr):\n return addr >= self.dccm_base and addr < (self.dccm_base + self.dccm_size)\n\n def check_phase(self):\n iccm_writes = defaultdict(lambda: 0)\n dccm_writes = defaultdict(lambda: 0)\n\n # Process writes\n while self.port.can_get():\n # Get an item\n got_item, item = self.port.try_get()\n assert got_item\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # AXI write. Check and decode its address\n if isinstance(item, BusWriteItem):\n # FIXME: Assuming the transaction is 64-bit wide\n data = struct.unpack(\"= 3: # FIXME: Unclear\n data = item.data\n else:\n self.logger.error(\"Invalid transaction size {}\".format(item.size))\n self.passed = False\n\n if item.mem == \"ICCM\":\n assert item.addr >= 0 and item.addr < self.iccm_size\n iccm_writes[\n (\n item.addr,\n data,\n )\n ] += 1\n elif item.mem == \"DCCM\":\n assert item.addr >= 0 and item.addr < self.dccm_size\n dccm_writes[\n (\n item.addr,\n data,\n )\n ] += 1\n else:\n self.logger.error(\"Write to an unknown memory region '{}'\".format(item.mem))\n self.passed = False\n\n # Check if there is an even number of writes for (each address, data)\n # for each memory region.\n for name, d in [(\"ICCM\", iccm_writes), (\"DCCM\", dccm_writes)]:\n for key, count in d.items():\n if count & 1:\n self.logger.error(\n \"{} write count to 0x{:08X} is odd, data {}\".format(name, key[0], key[1])\n )\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# =============================================================================\n\n\nclass AccessScoreboard(uvm_component):\n \"\"\"\n Checks if all Debug/AXI transfers fail with response 0x3 and that there is\n no activity on the ICCM/DCCM memory bus\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n # Process items\n while self.port.can_get():\n # Get an item\n got_item, item = self.port.try_get()\n assert got_item\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # Got a memory bus activity which is incorrect\n if isinstance(item, MemReadItem) or isinstance(item, MemWriteItem):\n self.logger.debug(\"Unexpected memory access at 0x{:08X}\".format(item.address))\n self.passed = False\n\n # Got an AXI activity, check the response code\n elif isinstance(item, BusReadItem) or isinstance(item, BusWriteItem):\n if item.resp != 0x3:\n self.logger.debug(\n \"Unexpected AXI response (0b{:03b}) for access to 0x{:08X}\".format(\n item.resp, item.address\n )\n )\n self.passed = False\n\n # Got a debug bus activity, check for failure\n elif isinstance(item, DebugReadItem) or isinstance(item, DebugWriteItem):\n if not item.fail:\n self.logger.debug(\n \"Unexpected debug bus response (0b{:01b}) for access to 0x{:08X}\".format(\n item.fail, item.address\n )\n )\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n" }, { "path": "verification/block/dma/sequences.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport random\nimport struct\n\nimport cocotb\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import ConfigDB, uvm_sequence\nfrom testbench import BusReadItem, BusWriteItem\n\n# =============================================================================\n\n\nclass MemWriteSequence(uvm_sequence):\n \"\"\"\n A sequence of random memory writes\n \"\"\"\n\n def __init__(self, name, mem, dwidth=32):\n super().__init__(name)\n self.mem = mem\n self.dwidth = dwidth\n\n async def body(self):\n mem_base = ConfigDB().get(None, \"\", self.mem + \"_BASE\")\n mem_size = ConfigDB().get(None, \"\", self.mem + \"_SIZE\")\n\n align = ConfigDB().get(None, \"\", \"ADDR_ALIGN\")\n\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n burst = ConfigDB().get(None, \"\", \"TEST_BURST_LEN\")\n gap = ConfigDB().get(None, \"\", \"TEST_BURST_GAP\")\n\n for j in range(count):\n for i in range(burst):\n addr = mem_base + random.randrange(0, mem_size)\n addr = (addr // align) * align\n\n # Determine how to pack data to bytes\n if self.dwidth == 32:\n fmt = \"= iccm_base and addr < iccm_base + iccm_size:\n continue\n if addr >= dccm_base and addr < dccm_base + dccm_size:\n continue\n if addr >= pic_base and addr < pic_base + pic_size:\n continue\n\n break\n\n # Randomize read/write\n if random.random() >= 0.5:\n item = BusReadItem(addr)\n else:\n # Determine how to pack data to bytes\n if self.dwidth == 32:\n fmt = \"\n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom scoreboards import AccessScoreboard\nfrom sequences import InvalidAddressSequence\nfrom testbench import BaseEnv, BaseTest\n\n# =============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Add scoreboard\n self.scoreboard = AccessScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.axi_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestAddressOutOfRange(BaseTest):\n \"\"\"\n Out of range addressing test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = InvalidAddressSequence(\"stimulus\", dwidth=self.env.axi_bfm.dwidth)\n\n async def run(self):\n await self.seq.start(self.env.axi_seqr)\n" }, { "path": "verification/block/dma/test_debug_address.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom scoreboards import AccessScoreboard\nfrom sequences import InvalidAddressSequence\nfrom testbench import BaseEnv, BaseTest\n\n# =============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Add scoreboard\n self.scoreboard = AccessScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.dbg_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestAddressOutOfRange(BaseTest):\n \"\"\"\n Out of range addressing test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = InvalidAddressSequence(\"stimulus\", dwidth=32) # The debug bus is 32-bit wide\n\n async def run(self):\n await self.seq.start(self.env.dbg_seqr)\n" }, { "path": "verification/block/dma/test_debug_read.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\n\nimport pyuvm\nfrom scoreboards import ReadScoreboard\nfrom sequences import AnyMemReadSequence, MemReadSequence\nfrom testbench import BaseEnv, BaseTest\n\n# =============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Add scoreboard\n self.scoreboard = ReadScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.dbg_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestDCCMRead(BaseTest):\n \"\"\"\n DCCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = MemReadSequence(\"stimulus\", \"DCCM\")\n\n async def run(self):\n await self.seq.start(self.env.dbg_seqr)\n\n\n@pyuvm.test()\nclass TestICCMRead(BaseTest):\n \"\"\"\n ICCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = MemReadSequence(\"stimulus\", \"ICCM\")\n\n async def run(self):\n await self.seq.start(self.env.dbg_seqr)\n\n\n@pyuvm.test()\nclass TestBothRead(BaseTest):\n \"\"\"\n Randomized DCCM/ICCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = AnyMemReadSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.dbg_seqr)\n" }, { "path": "verification/block/dma/test_debug_write.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom scoreboards import WriteScoreboard\nfrom sequences import AnyMemWriteSequence, MemWriteSequence\nfrom testbench import BaseEnv, BaseTest\n\n# =============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Add scoreboard\n self.scoreboard = WriteScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.dbg_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestDCCMWrite(BaseTest):\n \"\"\"\n DCCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = MemWriteSequence(\"stimulus\", \"DCCM\", dwidth=32)\n\n async def run(self):\n await self.seq.start(self.env.dbg_seqr)\n\n\n@pyuvm.test()\nclass TestICCMWrite(BaseTest):\n \"\"\"\n ICCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = MemWriteSequence(\"stimulus\", \"ICCM\", dwidth=32)\n\n async def run(self):\n await self.seq.start(self.env.dbg_seqr)\n\n\n@pyuvm.test()\nclass TestBothWrite(BaseTest):\n \"\"\"\n Randomized DCCM/ICCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = AnyMemWriteSequence(\"stimulus\", dwidth=32)\n\n async def run(self):\n await self.seq.start(self.env.dbg_seqr)\n" }, { "path": "verification/block/dma/test_ecc.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nfrom collections import defaultdict\n\nimport pyuvm\nfrom pyuvm import ConfigDB, uvm_component, uvm_get_port, uvm_tlm_analysis_fifo\nfrom sequences import AnyMemReadSequence\nfrom testbench import BaseEnv, BaseTest, BusReadItem, MemReadItem\n\n# =============================================================================\n\n\nclass Scoreboard(uvm_component):\n \"\"\" \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n self.iccm_base = ConfigDB().get(None, \"\", \"ICCM_BASE\")\n self.iccm_size = ConfigDB().get(None, \"\", \"ICCM_SIZE\")\n\n self.dccm_base = ConfigDB().get(None, \"\", \"DCCM_BASE\")\n self.dccm_size = ConfigDB().get(None, \"\", \"DCCM_SIZE\")\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def is_iccm(self, addr):\n return addr > self.iccm_base and addr < (self.iccm_base + self.iccm_size)\n\n def is_dccm(self, addr):\n return addr > self.dccm_base and addr < (self.dccm_base + self.dccm_size)\n\n def check_phase(self):\n reads = defaultdict(lambda: dict())\n\n # Process writes\n while self.port.can_get():\n # Get an item\n got_item, item = self.port.try_get()\n assert got_item\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # AXI read. Check and decode its address\n if isinstance(item, BusReadItem):\n addr = item.addr\n reads[addr][\"axi\"] = item.resp\n\n # Memory read\n elif isinstance(item, MemReadItem):\n if item.mem == \"ICCM\":\n addr = item.addr + self.iccm_base\n reads[addr][\"mem\"] = item.resp\n elif item.mem == \"DCCM\":\n addr = item.addr + self.dccm_base\n reads[addr][\"mem\"] = item.resp\n else:\n self.logger.error(\"Read from an unknown memory region '{}'\".format(item.mem))\n self.passed = False\n\n # Check reads\n have_ecc_err = False\n have_ecc_ok = False\n\n for addr, pair in reads.items():\n if \"axi\" not in pair:\n self.logger.error(\"No AXI transfer for access to 0x{:08X}\".format(addr))\n self.passed = False\n\n if \"mem\" not in pair:\n self.logger.error(\"No memory transfer for access to 0x{:08X}\".format(addr))\n self.passed = False\n\n if \"axi\" not in pair or \"mem\" not in pair:\n continue\n\n # Check correlation between AXI response and ECC error injection\n if not pair[\"mem\"] and pair[\"axi\"] != 0x0:\n self.logger.error(\n \"AXI transfer error (0b{:03b}) for access to 0x{:08X}\".format(pair[\"axi\"], addr)\n )\n self.passed = False\n\n if pair[\"mem\"] and pair[\"axi\"] != 0x2:\n self.logger.error(\n \"Invalid AXI response (0b{:03b}) for access to 0x{:08X}\".format(\n pair[\"axi\"], addr\n )\n )\n self.passed = False\n\n # Check if there were errors injected\n if pair[\"mem\"]:\n have_ecc_err = True\n else:\n have_ecc_ok = True\n\n if not have_ecc_err:\n self.logger.error(\"There were no ECC errors injected!\")\n self.passed = False\n\n if not have_ecc_ok:\n self.logger.error(\"There were only ECC errors injected!\")\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# =============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Enable ECC error injection\n ConfigDB().set(self.mem_bfm, \"\", \"ECC_ERROR_RATE\", 0.5)\n\n # Add scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.axi_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestEccError(BaseTest):\n \"\"\"\n Tests the DMA reaction on ICCM/DCCM ECC error\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = AnyMemReadSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.axi_seqr)\n" }, { "path": "verification/block/dma/test_read.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom scoreboards import ReadScoreboard\nfrom sequences import AnyMemReadSequence, MemReadSequence\nfrom testbench import BaseEnv, BaseTest\n\n# =============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Add scoreboard\n self.scoreboard = ReadScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.axi_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestDCCMRead(BaseTest):\n \"\"\"\n DCCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = MemReadSequence(\"stimulus\", \"DCCM\")\n\n async def run(self):\n await self.seq.start(self.env.axi_seqr)\n\n\n@pyuvm.test()\nclass TestICCMRead(BaseTest):\n \"\"\"\n ICCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = MemReadSequence(\"stimulus\", \"ICCM\")\n\n async def run(self):\n await self.seq.start(self.env.axi_seqr)\n\n\n@pyuvm.test()\nclass TestBothRead(BaseTest):\n \"\"\"\n Randomized DCCM/ICCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = AnyMemReadSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.axi_seqr)\n" }, { "path": "verification/block/dma/test_reset.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport cocotb\nimport pyuvm\nfrom testbench import BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestReset(BaseTest):\n \"\"\"\n A basic test that resets the DUT\n \"\"\"\n\n async def run(self):\n # Check state of DUT signals after reset\n state = {\n \"dma_dbg_cmd_done\": 0,\n \"dma_dbg_cmd_fail\": 0,\n \"dma_dccm_req\": 0,\n \"dma_iccm_req\": 0,\n \"dma_active\": 0,\n \"dma_dccm_stall_any\": 0,\n \"dma_iccm_stall_any\": 0,\n \"dma_pmu_dccm_read\": 0,\n \"dma_pmu_dccm_write\": 0,\n \"dma_pmu_any_read\": 0,\n \"dma_pmu_any_write\": 0,\n \"dma_axi_bvalid\": 0,\n \"dma_axi_rvalid\": 0,\n }\n\n for name, value in state.items():\n signal = getattr(cocotb.top, name)\n assert signal.value == value, \"{}={}, should be {}\".format(name, signal.value, value)\n" }, { "path": "verification/block/dma/test_write.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom scoreboards import WriteScoreboard\nfrom sequences import AnyMemWriteSequence, MemWriteSequence\nfrom testbench import BaseEnv, BaseTest\n\n# =============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Add scoreboard\n self.scoreboard = WriteScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.axi_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestDCCMWrite(BaseTest):\n \"\"\"\n DCCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = MemWriteSequence(\"stimulus\", \"DCCM\", dwidth=self.env.axi_bfm.dwidth)\n\n async def run(self):\n await self.seq.start(self.env.axi_seqr)\n\n\n@pyuvm.test()\nclass TestICCMWrite(BaseTest):\n \"\"\"\n ICCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = MemWriteSequence(\"stimulus\", \"ICCM\", dwidth=self.env.axi_bfm.dwidth)\n\n async def run(self):\n await self.seq.start(self.env.axi_seqr)\n\n\n@pyuvm.test()\nclass TestBothWrite(BaseTest):\n \"\"\"\n Randomized DCCM/ICCM write test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = AnyMemWriteSequence(\"stimulus\", dwidth=self.env.axi_bfm.dwidth)\n\n async def run(self):\n await self.seq.start(self.env.axi_seqr)\n" }, { "path": "verification/block/dma/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport logging\nimport math\nimport os\nimport random\nimport struct\n\nimport cocotb\nfrom axi import Axi4LiteMonitor, BusReadItem, BusWriteItem\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, FallingEdge, Lock, ReadOnly, RisingEdge\nfrom pyuvm import (\n ConfigDB,\n uvm_analysis_port,\n uvm_component,\n uvm_driver,\n uvm_env,\n uvm_report_object,\n uvm_sequence_item,\n uvm_sequencer,\n uvm_test,\n)\nfrom utils import collect_bytes, collect_signals, smallest_number_of_trials\n\n# ==============================================================================\n\n\nclass MemWriteItem(uvm_sequence_item):\n \"\"\"\n A generic memory bus write item\n \"\"\"\n\n def __init__(self, mem, addr, data, size=64, resp=None):\n super().__init__(\"MemWriteItem\")\n self.mem = mem\n self.addr = addr\n self.data = data\n self.size = size\n self.resp = resp\n\n\nclass MemReadItem(uvm_sequence_item):\n \"\"\"\n A generic memory bus read item\n \"\"\"\n\n def __init__(self, mem, addr, data, size=64, resp=None):\n super().__init__(\"MemReadItem\")\n self.mem = mem\n self.addr = addr\n self.data = data\n self.size = size\n self.resp = resp\n\n\nclass DebugWriteItem(uvm_sequence_item):\n \"\"\"\n A debug bus write item\n \"\"\"\n\n def __init__(self, addr, data, size=32, fail=False):\n super().__init__(\"DebugWriteItem\")\n self.addr = addr\n self.data = data\n self.size = size\n self.fail = fail\n\n\nclass DebugReadItem(uvm_sequence_item):\n \"\"\"\n A debug bus read item\n \"\"\"\n\n def __init__(self, addr, data=None, size=32, fail=False):\n super().__init__(\"DebugReadItem\")\n self.addr = addr\n self.data = data\n self.size = size\n self.fail = fail\n\n\n# ==============================================================================\n\n\nclass CoreMemoryBFM(uvm_component):\n \"\"\"\n A BFM for the memory side interface of the DMA module\n \"\"\"\n\n SIGNALS = [\n \"clk\",\n \"dma_dccm_req\",\n \"dma_iccm_req\",\n \"dma_mem_tag\",\n \"dma_mem_addr\",\n \"dma_mem_sz\",\n \"dma_mem_write\",\n \"dma_mem_wdata\",\n \"dccm_dma_rvalid\",\n \"dccm_dma_ecc_error\",\n \"dccm_dma_rtag\",\n \"dccm_dma_rdata\",\n \"iccm_dma_rvalid\",\n \"iccm_dma_ecc_error\",\n \"iccm_dma_rtag\",\n \"iccm_dma_rdata\",\n \"dccm_ready\",\n \"iccm_ready\",\n ]\n\n def __init__(self, name, parent, uut):\n super().__init__(name, parent)\n\n # Collect signals\n collect_signals(self.SIGNALS, uut, self)\n\n # Memory content\n self.iccm_data = dict()\n self.dccm_data = dict()\n\n def build_phase(self):\n # Get base addresses and sizes\n self.iccm_base = ConfigDB().get(None, \"\", \"ICCM_BASE\")\n self.dccm_base = ConfigDB().get(None, \"\", \"DCCM_BASE\")\n\n self.iccm_size = ConfigDB().get(None, \"\", \"ICCM_SIZE\")\n self.dccm_size = ConfigDB().get(None, \"\", \"DCCM_SIZE\")\n\n # Get parameters\n self.iccm_busy = ConfigDB().get(self, \"\", \"ICCM_BUSY_PROB\")\n self.dccm_busy = ConfigDB().get(self, \"\", \"DCCM_BUSY_PROB\")\n\n self.busy_range = (\n ConfigDB().get(self, \"\", \"MEM_BUSY_MIN\"),\n ConfigDB().get(self, \"\", \"MEM_BUSY_MAX\"),\n )\n\n self.ecc_err_rate = ConfigDB().get(self, \"\", \"ECC_ERROR_RATE\")\n\n async def iccm_busy_task(self):\n \"\"\"\n A task that randomly makes ICCM busy\n \"\"\"\n\n while True:\n await RisingEdge(self.clk)\n\n # Become busy at random for a random cycle count\n if random.random() < self.iccm_busy:\n self.iccm_ready.value = 0\n\n n = random.randrange(*self.busy_range)\n await ClockCycles(self.clk, n)\n\n self.iccm_ready.value = 1\n\n async def dccm_busy_task(self):\n \"\"\"\n A task that randomly makes DCCM busy\n \"\"\"\n\n while True:\n await RisingEdge(self.clk)\n\n # Become busy at random for a random cycle count\n if random.random() < self.dccm_busy:\n self.dccm_ready.value = 0\n\n n = random.randrange(*self.busy_range)\n await ClockCycles(self.clk, n)\n\n self.dccm_ready.value = 1\n\n async def responder(self):\n \"\"\"\n A task for handling read / write responses\n \"\"\"\n\n while True:\n await RisingEdge(self.clk)\n\n # Sample signals\n tag = int(self.dma_mem_tag)\n\n # DCCM access\n if self.dma_dccm_req.value:\n # Decode and check address\n addr = int(self.dma_mem_addr.value) - self.dccm_base\n assert addr >= 0 and addr < self.dccm_size\n\n # Write / read\n if self.dma_mem_write.value:\n self.dccm_data[addr] = int(self.dma_mem_wdata.value)\n\n else:\n if addr not in self.dccm_data:\n self.dccm_data[addr] = random.randrange(0, (1 << 64) - 1)\n\n self.dccm_dma_rdata.value = self.dccm_data[addr]\n self.dccm_dma_rtag.value = tag\n self.dccm_dma_rvalid.value = 1\n self.dccm_dma_ecc_error.value = random.random() < self.ecc_err_rate\n\n await RisingEdge(self.clk)\n self.dccm_dma_rvalid.value = 0\n\n # ICCM access\n elif self.dma_iccm_req.value:\n # Decode and check address\n addr = int(self.dma_mem_addr.value) - self.iccm_base\n assert addr >= 0 and addr < self.iccm_size\n\n # Write / read\n if self.dma_mem_write.value:\n self.iccm_data[addr] = int(self.dma_mem_wdata.value)\n\n else:\n if addr not in self.iccm_data:\n self.iccm_data[addr] = random.randrange(0, (1 << 64) - 1)\n\n self.iccm_dma_rdata.value = self.iccm_data[addr]\n self.iccm_dma_rtag.value = tag\n self.iccm_dma_rvalid.value = 1\n self.iccm_dma_ecc_error.value = random.random() < self.ecc_err_rate\n\n await RisingEdge(self.clk)\n self.iccm_dma_rvalid.value = 0\n\n async def run_phase(self):\n # Initially make ICCM and DCCM ready\n self.iccm_ready.value = 1\n self.dccm_ready.value = 1\n\n # Start tasks\n cocotb.start_soon(self.iccm_busy_task())\n cocotb.start_soon(self.dccm_busy_task())\n cocotb.start_soon(self.responder())\n\n\nclass CoreMemoryMonitor(uvm_component):\n \"\"\"\n A monitor for ICCM / DCCM interface\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.bfm = kwargs[\"bfm\"]\n del kwargs[\"bfm\"]\n super().__init__(*args, **kwargs)\n\n # Get base addresses\n self.iccm_base = ConfigDB().get(None, \"\", \"ICCM_BASE\")\n self.dccm_base = ConfigDB().get(None, \"\", \"DCCM_BASE\")\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n req_pending = False\n is_iccm = False\n is_dccm = False\n req_wr = False\n req_addr = 0\n req_data = 0\n req_size = 0\n\n while True:\n await RisingEdge(self.bfm.clk)\n await ReadOnly()\n\n # Monitor reads which happen one cycle after a request\n if req_pending and not req_wr:\n if is_iccm:\n addr = req_addr - self.iccm_base\n data = int(self.bfm.iccm_dma_rdata.value)\n resp = int(self.bfm.iccm_dma_ecc_error.value)\n self.ap.write(MemReadItem(\"ICCM\", addr, data, req_size, resp))\n self.logger.debug(\"ICCM RD: 0x{:08X} 0x{:016X} {}\".format(addr, data, resp))\n\n if is_dccm:\n addr = req_addr - self.dccm_base\n data = int(self.bfm.dccm_dma_rdata.value)\n resp = int(self.bfm.dccm_dma_ecc_error.value)\n self.ap.write(MemReadItem(\"DCCM\", addr, data, req_size, resp))\n self.logger.debug(\"DCCM RD: 0x{:08X} 0x{:016X} {}\".format(addr, data, resp))\n\n req_pending = False\n\n # We have a request\n is_iccm = self.bfm.dma_iccm_req.value\n is_dccm = self.bfm.dma_dccm_req.value\n\n if is_iccm or is_dccm:\n req_pending = True\n\n req_addr = int(self.bfm.dma_mem_addr.value)\n req_data = int(self.bfm.dma_mem_wdata.value)\n req_wr = int(self.bfm.dma_mem_write.value)\n req_size = int(self.bfm.dma_mem_sz.value)\n\n # Writes\n if req_wr and is_iccm:\n addr = req_addr - self.iccm_base\n self.ap.write(MemWriteItem(\"ICCM\", addr, req_data, req_size))\n self.logger.debug(\"ICCM WR: 0x{:08X} 0x{:016X}\".format(addr, req_data))\n\n if req_wr and is_dccm:\n addr = req_addr - self.dccm_base\n self.ap.write(MemWriteItem(\"DCCM\", addr, req_data, req_size))\n self.logger.debug(\"DCCM WR: 0x{:08X} 0x{:016X}\".format(addr, req_data))\n\n\n# ==============================================================================\n\n\nclass Axi4LiteBFM(uvm_component):\n \"\"\"\n A bus functional model for AXI4 Lite subordinate port.\n\n Does support multi-transfer transactions, supports overlapped transactions\n for writes\n \"\"\"\n\n SIGNALS = [\n \"clk\",\n \"rst\",\n \"awvalid\",\n \"awready\",\n \"awid\",\n \"awaddr\",\n \"awsize\",\n \"wvalid\",\n \"wready\",\n \"wdata\",\n \"wstrb\",\n \"bvalid\",\n \"bready\",\n \"bresp\",\n \"bid\",\n \"arvalid\",\n \"arready\",\n \"arid\",\n \"araddr\",\n \"arsize\",\n \"rvalid\",\n \"rready\",\n \"rid\",\n \"rdata\",\n \"rresp\",\n \"rlast\",\n ]\n\n class Transfer:\n \"\"\"\n Represents a pending AXI transfer\n \"\"\"\n\n def __init__(self, tid):\n self.tid = tid\n self.addr = None\n self.data = None\n\n self.pending = False\n\n def __init__(self, name, parent, uut, signal_map):\n super().__init__(name, parent)\n\n # Collect signals\n collect_signals(\n self.SIGNALS, uut, self, uut_prefix=\"dma_axi_\", obj_prefix=\"axi_\", signal_map=signal_map\n )\n\n # Determine bus parameters\n self.awidth = len(self.axi_awaddr)\n self.dwidth = len(self.axi_wdata)\n self.swidth = len(self.axi_wstrb)\n\n assert self.swidth == (self.dwidth // 8)\n\n self.logger.debug(\"AXI4 Lite BFM:\")\n self.logger.debug(\" awidth = {}\".format(self.awidth))\n self.logger.debug(\" dwidth = {}\".format(self.dwidth))\n self.logger.debug(\" swidth = {}\".format(self.swidth))\n\n self.xfer_lock = Lock()\n\n self.wr_xfers = {i: self.Transfer(i) for i in range(1 << len(self.axi_awid))}\n\n def build_phase(self):\n self.busy_timeout = ConfigDB().get(self, \"\", \"MEM_BUSY_TIMEOUT\")\n\n async def _wait(self, signal, max_cycles=200):\n \"\"\"\n Waits for a signal to be asserted in at most max_cycles.\n Raises an exception if it does not\n \"\"\"\n for _ in range(max_cycles):\n await RisingEdge(self.axi_clk)\n if signal.value != 0:\n break\n else:\n raise RuntimeError(\"{} timeout\".format(signal._name))\n\n async def write(self, addr, data):\n \"\"\"\n Issues a write transfer, does not wait until it completes\n \"\"\"\n\n # Wait for a free transfer id\n while True:\n await RisingEdge(self.axi_clk)\n\n async with self.xfer_lock:\n awid = None\n for tid, xfr in self.wr_xfers.items():\n if not xfr.pending:\n awid = tid\n break\n\n if awid is not None:\n xfer = self.wr_xfers[awid]\n xfer.pending = True\n xfer.addr = addr\n xfer.data = data\n break\n\n # Send write request\n self.axi_awvalid.value = 1\n self.axi_awaddr.value = addr\n self.axi_awid.value = awid\n self.axi_awsize.value = int(math.ceil(math.log2(self.dwidth)))\n await self._wait(self.axi_awready, self.busy_timeout)\n self.axi_awvalid.value = 0\n\n # Send data\n self.axi_wvalid.value = 1\n data_len = len(data)\n data_ptr = 0\n while data_len > 0:\n # Get data\n xfer_len = min(self.swidth, data_len)\n xfer_data = data[data_ptr : data_ptr + xfer_len]\n data_ptr += xfer_len\n data_len -= xfer_len\n\n # Assert data\n wdata = 0\n wstrb = 0\n for i in range(xfer_len):\n wdata <<= 8\n wstrb <<= 1\n\n wdata |= xfer_data[-(1 + i)]\n wstrb |= 1\n\n self.axi_wdata.value = wdata\n self.axi_wstrb.value = wstrb\n\n await self._wait(self.axi_wready, self.busy_timeout)\n self.axi_wvalid.value = 0\n\n async def write_handler(self):\n \"\"\"\n A handler for write transfer completion\n \"\"\"\n # Accept responses\n self.axi_bready.value = 1\n\n while True:\n # Wait for response\n await RisingEdge(self.axi_clk)\n if not self.axi_bvalid.value:\n continue\n\n bresp = int(self.axi_bresp.value)\n bid = int(self.axi_bid.value)\n\n # Find a pending transfer\n async with self.xfer_lock:\n xfer = self.wr_xfers.get(bid, None)\n if not xfer:\n self.logger.error(\"Write response for a non-pending tid {}\".format(bid))\n continue\n\n xfer.pending = False\n\n addr = xfer.addr\n data = xfer.data\n\n self.logger.debug(\n \"WR: 0x{:08X} {} 0b{:03b}\".format(addr, [\"0x{:02X}\".format(b) for b in data], bresp)\n )\n\n async def read(self, addr, data):\n \"\"\"\n Issues a read transfer and waits for its completion\n \"\"\"\n\n # Send read request\n self.axi_araddr.value = addr\n self.axi_arid.value = 1\n self.axi_arsize.value = int(math.ceil(math.log2(self.dwidth)))\n self.axi_arvalid.value = 1\n await self._wait(self.axi_arready, self.busy_timeout)\n self.axi_arvalid.value = 0\n\n self.axi_rready.value = 1\n data = bytearray()\n rresp = None\n\n while True:\n # Receive data\n await self._wait(self.axi_rvalid, self.busy_timeout)\n\n # Get the data\n data.extend(collect_bytes(self.axi_rdata))\n\n # Last, finish reception\n if self.axi_rlast.value:\n break\n\n rresp = int(self.axi_rresp.value)\n self.axi_rready.value = 0\n\n self.logger.debug(\n \"RD: 0x{:08X} {} 0b{:03b}\".format(addr, [\"0x{:02X}\".format(b) for b in data], rresp)\n )\n\n return bytes(data), rresp\n\n async def run_phase(self):\n # Start read & write handlers\n cocotb.start_soon(self.write_handler())\n\n\n# ==============================================================================\n\n\nclass Axi4LiteSubordinateDriver(uvm_driver):\n \"\"\"\n A driver component for AXI4 lite subordinate ports. Acts as an AXI Manager.\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.bfm = kwargs[\"bfm\"]\n del kwargs[\"bfm\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, BusWriteItem):\n await self.bfm.write(it.addr, it.data)\n\n elif isinstance(it, BusReadItem):\n # FIXME: Assuming that all read requests are 64-bit wide\n await self.bfm.read(it.addr, 8)\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\n# ==============================================================================\n\n\nclass DebugInterfaceBFM(uvm_component):\n \"\"\"\n A DFM for DMA debug interface\n \"\"\"\n\n SIGNALS = [\n \"clk\",\n \"dbg_cmd_addr\",\n \"dbg_cmd_wrdata\",\n \"dbg_cmd_valid\",\n \"dbg_cmd_write\",\n \"dbg_cmd_type\",\n \"dbg_cmd_size\",\n \"dbg_dma_bubble\",\n \"dma_dbg_ready\",\n \"dma_dbg_cmd_done\",\n \"dma_dbg_cmd_fail\",\n \"dma_dbg_rddata\",\n ]\n\n def __init__(self, name, parent, uut):\n super().__init__(name, parent)\n\n # Collect signals\n collect_signals(self.SIGNALS, uut, self)\n\n def build_phase(self):\n self.busy_prob = ConfigDB().get(self, \"\", \"DBG_BUSY_PROB\")\n self.busy_range = (\n ConfigDB().get(self, \"\", \"DBG_BUSY_MIN\"),\n ConfigDB().get(self, \"\", \"DBG_BUSY_MAX\"),\n )\n self.busy_timeout = ConfigDB().get(self, \"\", \"DBG_BUSY_TIMEOUT\")\n\n async def _wait(self, signal, max_cycles=150):\n \"\"\"\n Waits for a signal to be asserted for at most max_cycles.\n Raises an exception if it does not\n \"\"\"\n for i in range(max_cycles):\n await RisingEdge(self.clk)\n if signal.value != 0:\n break\n else:\n raise RuntimeError(\"{} timeout\".format(signal._name))\n\n async def write(self, addr, data):\n \"\"\"\n Performs a debug interface write. Waits for completion and returns\n status code\n \"\"\"\n\n # Wait for ready\n await self._wait(self.dma_dbg_ready, self.busy_timeout)\n\n # Issue the command\n self.dbg_cmd_valid.value = 1\n self.dbg_cmd_write.value = 1\n self.dbg_cmd_size.value = 2 # Apparently 0=8, 1=16, 2=32\n self.dbg_cmd_addr.value = addr\n self.dbg_cmd_wrdata.value = struct.unpack(\" Driver <---> Top module\n Monitor <------^\n \"\"\"\n\n def build_phase(self):\n self.seqr = uvm_sequencer(\"seqr\", self)\n ConfigDB().set(None, \"*\", \"DMI_SEQR\", self.seqr)\n\n self.monitor = DMIMonitor(\"dmi_monitor\", self, \"rsp_monitor_q_get\")\n self.driver = DMIDriver(\"dmi_driver\", self)\n\n def connect_phase(self):\n self.driver.seq_item_port.connect(self.seqr.seq_item_export)\n\n\nclass DMIDriver(uvm_driver):\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap_drv\", self)\n\n def start_of_simulation_phase(self):\n self.bfm = BFM()\n\n async def run_phase(self):\n self.bfm.start_bfm()\n\n while True:\n item = await self.seq_item_port.get_next_item()\n await self.bfm.req_driver_q_put(item)\n self.seq_item_port.item_done()\n\n\nclass DMIMonitor(uvm_component):\n def __init__(self, name, parent, method_name):\n super().__init__(name, parent)\n self.method_name = method_name\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap_mon\", self)\n self.bfm = BFM()\n self.get_method = getattr(self.bfm, self.method_name)\n\n async def run_phase(self):\n while True:\n datum = await self.get_method()\n self.logger.debug(f\"DMI Monitor req: {datum}\")\n self.ap.write(datum)\n" }, { "path": "verification/block/dmi/dmi_bfm.py", "content": "#\n# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom cocotb.triggers import FallingEdge, RisingEdge\nfrom dmi_seq import SetUncoreEnableSeqItem\nfrom pyuvm import *\n\nfrom common import Defaults, collect_signals, get_int\n\n\nclass MemoryModel:\n def __init__(self):\n self.memory = {}\n self.reset()\n\n def write(self, addr, data):\n self.memory.update({addr: data})\n\n def read(self, addr):\n return get_int(self.memory.setdefault(addr, 0))\n\n def reset(self):\n self.memory = {\n 0x01: Defaults.JTAG_ID,\n 0x10: Defaults.DTMCS,\n 0x11: 0,\n }\n\n\nclass DMITestBfm(metaclass=utility_classes.Singleton):\n \"\"\"\n A BFM for the DMI core module.\n \"\"\"\n\n SIGNALS = [\n # Control inputs\n \"core_rst_n\",\n \"core_clk\",\n \"jtag_id\",\n # DMI inputs\n \"uncore_enable\",\n \"dmi_core_rdata\",\n \"dmi_uncore_rdata\",\n # DMI outputs\n \"dmi_hard_reset\",\n \"rd_data\",\n \"dmi_core_en\",\n \"dmi_core_wr_en\",\n \"dmi_core_addr\",\n \"dmi_core_wdata\",\n \"dmi_uncore_en\",\n \"dmi_uncore_wr_en\",\n \"dmi_uncore_addr\",\n \"dmi_uncore_wdata\",\n ]\n\n def __init__(self):\n self.dut = cocotb.top\n self.req_driver_q = UVMQueue(maxsize=1)\n self.req_monitor_q = UVMQueue(maxsize=0)\n self.rsp_monitor_q = UVMQueue(maxsize=0)\n\n self.predictor = ConfigDB().get(None, \"\", \"JTAG_PREDICTOR\")\n self.core_mem = MemoryModel()\n self.uncore_mem = MemoryModel()\n\n collect_signals(self.SIGNALS, self.dut, self)\n self.rst_n = self.core_rst_n\n self.clk = self.core_clk\n\n async def req_driver_q_put(self, item):\n await self.req_driver_q.put(item)\n\n async def rsp_monitor_q_get(self):\n result = await self.rsp_monitor_q.get()\n return result\n\n async def driver_bfm(self):\n \"\"\"\n Reads a register\n \"\"\"\n\n self.dmi_core_rdata.value = 0\n self.dmi_uncore_rdata.value = 0\n self.uncore_enable.value = 0\n self.jtag_id.value = Defaults.JTAG_ID\n\n while True:\n await FallingEdge(self.clk)\n try:\n item = self.req_driver_q.get_nowait()\n\n if isinstance(item, SetUncoreEnableSeqItem):\n self.uncore_enable.value = item.uncore_enable\n\n except QueueEmpty:\n pass\n\n async def rsp_monitor_q_bfm(self):\n DMI_CORE_BOUNDARY = 0x4F\n\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n await RisingEdge(self.rst_n)\n\n await RisingEdge(self.clk)\n\n if self.dmi_hard_reset.value:\n self.core_mem.reset()\n self.uncore_mem.reset()\n pass\n\n # DMI Core memory managment\n if self.dmi_core_en.value:\n self.dmi_core_rdata.value = self.core_mem.read(get_int(self.dmi_core_addr))\n if self.dmi_core_wr_en.value:\n self.core_mem.write(get_int(self.dmi_core_addr), get_int(self.dmi_core_wdata))\n\n # DMI Uncore memory managment\n if self.dmi_uncore_en.value:\n self.dmi_uncore_rdata.value = self.uncore_mem.read(get_int(self.dmi_uncore_addr))\n if self.dmi_uncore_wr_en.value:\n self.uncore_mem.write(get_int(self.dmi_uncore_addr), get_int(self.dmi_uncore_wdata))\n\n # Pass data to the scoreboard on write/read request\n if self.dmi_uncore_en.value or self.dmi_core_en.value:\n if (self.predictor.wr_addr.integer > DMI_CORE_BOUNDARY) and self.uncore_enable:\n dmi_type = \"uncore\"\n values = [\n get_int(self.rd_data),\n get_int(self.dmi_uncore_rdata),\n get_int(self.dmi_uncore_addr),\n get_int(self.dmi_uncore_en),\n get_int(self.predictor.rd_en),\n ]\n else:\n dmi_type = \"core\"\n values = [\n get_int(self.rd_data),\n get_int(self.dmi_core_rdata),\n get_int(self.dmi_core_addr),\n get_int(self.dmi_core_en),\n get_int(self.predictor.rd_en),\n ]\n\n self.rsp_monitor_q.put_nowait((values, dmi_type))\n\n def start_bfm(self):\n cocotb.start_soon(self.driver_bfm())\n cocotb.start_soon(self.rsp_monitor_q_bfm())\n" }, { "path": "verification/block/dmi/dmi_seq.py", "content": "#\n# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom cocotb.handle import LogicArray\nfrom jtag_seq import *\nfrom pyuvm import *\n\n\nclass SetUncoreEnableSeqItem(uvm_sequence_item):\n def __init__(self, name, uncore_enable):\n super().__init__(name)\n self.uncore_enable = uncore_enable\n\n def __str__(self):\n return self.__class__.__name__\n\n def randomize(self):\n pass\n\n\nclass SetUncoreEnableSequence(BaseSeq):\n def __init__(self, name, value):\n super().__init__(name)\n self.name = name\n self.value = value\n\n async def body(self):\n item = [SetUncoreEnableSeqItem(self.name, self.value)]\n await self.run_items(item)\n\n\nclass AccessDMIRegSequence(BaseSeq):\n def __init__(self, name, addr, data=0x0, is_write=False):\n super().__init__(name)\n assert isinstance(addr, int)\n assert isinstance(data, int)\n\n self.addr = LogicArray(addr, range(7))\n self.data = LogicArray(data, range(32))\n self.is_write = 1 if is_write else 0\n\n async def body(self):\n data_bits_items = []\n addr_bits_items = []\n\n for i, val in enumerate(reversed(list(self.data))):\n data_bits_items.append(JTAGBaseSeqItem(\"write_data_bit{}\".format(i), 0, val))\n\n for i, val in enumerate(reversed(list(self.addr))):\n # Last bit must be written simultaneously with leaving SHIFT_DR state\n tms = 1 if (i == (len(list(self.addr)) - 1)) else 0\n addr_bits_items.append(JTAGBaseSeqItem(\"write_addr_bit{}\".format(i), tms, val))\n\n items = [\n JTAGBaseSeqItem(\"switch_to_select_dr_scan\", 1, 0),\n JTAGBaseSeqItem(\"switch_to_capture_dr\", 0, 0),\n JTAGBaseSeqItem(\"switch_to_shift_dr\", 0, 0),\n JTAGBaseSeqItem(\"write_rd_en_bit\", 0, 1),\n JTAGBaseSeqItem(\"write_wr_en_bit\", 0, self.is_write),\n ]\n items += data_bits_items\n items += addr_bits_items\n items += [\n JTAGBaseSeqItem(\"switch_to_update_dr\", 1, 0),\n JTAGBaseSeqItem(\"switch_to_idle\", 0, 0),\n JTAGBaseSeqItem(\"idle0\", 0, 0),\n JTAGBaseSeqItem(\"idle1\", 0, 0),\n ]\n await self.run_items(items)\n" }, { "path": "verification/block/dmi/dmi_test_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro\n// SPDX-License-Identifier: Apache-2.0\n\nmodule dmi_test_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n // JTAG signals\n input trst_n, // JTAG reset\n input tck, // JTAG clock\n input tms, // Test mode select\n input tdi, // Test Data Input\n output tdo, // Test Data Output\n output tdoEnable, // Test Data Output enable\n\n // Processor Signals\n input core_rst_n, // Core reset\n input core_clk, // Core clock\n input [31:1] jtag_id,\n output [31:0] rd_data, // 32 bit Read data from Processor\n output dmi_hard_reset,\n\n // Uncore access enable\n input wire uncore_enable,\n\n // DMI downstream for core\n output wire dmi_core_en,\n output wire dmi_core_wr_en,\n output wire [6:0] dmi_core_addr,\n output wire [31:0] dmi_core_wdata,\n input wire [31:0] dmi_core_rdata,\n\n // DMI downstream for uncore\n output wire dmi_uncore_en,\n output wire dmi_uncore_wr_en,\n output wire [6:0] dmi_uncore_addr,\n output wire [31:0] dmi_uncore_wdata,\n input wire [31:0] dmi_uncore_rdata\n);\n\n logic [ 6:0] reg_wr_addr; // Reg address to Processor\n logic [31:0] reg_wr_data; // Reg address to Processor\n logic reg_en; // Read enable to Processor\n logic reg_wr_en; // Write enable to Processor\n\n logic dmi_en;\n logic dmi_wr_en;\n logic [ 6:0] dmi_addr;\n logic [31:0] dmi_wdata;\n logic [31:0] dmi_rdata;\n logic core_enable;\n\n assign core_enable = '1;\n\n assign dmi_en = reg_en;\n assign dmi_wr_en = reg_wr_en;\n assign dmi_addr = reg_wr_addr;\n assign dmi_wdata = reg_wr_data;\n assign rd_data = dmi_rdata;\n\n dmi_wrapper wrapper (.*);\n\n dmi_mux mux (.*);\n\nendmodule\n" }, { "path": "verification/block/dmi/jtag_agent.py", "content": "from jtag_bfm import JTAGBfm as BFM\nfrom pyuvm import *\n\nfrom common import *\n\n\nclass JTAGAgent(uvm_agent):\n \"\"\"\n Seqr <---> Driver <---> Top module\n Monitor <------^\n \"\"\"\n\n def build_phase(self):\n self.seqr = uvm_sequencer(\"seqr\", self)\n ConfigDB().set(None, \"*\", \"JTAG_SEQR\", self.seqr)\n\n self.monitor = JTAGMonitor(\"jtag_monitor\", self, \"rsp_monitor_q_get\")\n self.driver = JTAGDriver(\"jtag_driver\", self)\n\n def connect_phase(self):\n self.driver.seq_item_port.connect(self.seqr.seq_item_export)\n\n\nclass JTAGDriver(uvm_driver):\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap_drv\", self)\n\n def start_of_simulation_phase(self):\n self.bfm = BFM()\n\n async def run_phase(self):\n await self.bfm.reset()\n self.bfm.start_bfm()\n\n while True:\n item = await self.seq_item_port.get_next_item()\n await self.bfm.req_driver_q_put(item.tms, item.tdi)\n self.seq_item_port.item_done()\n\n\nclass JTAGMonitor(uvm_component):\n def __init__(self, name, parent, method_name):\n super().__init__(name, parent)\n self.method_name = method_name\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap_mon\", self)\n self.bfm = BFM()\n self.get_method = getattr(self.bfm, self.method_name)\n\n async def run_phase(self):\n while True:\n datum = await self.get_method()\n self.logger.debug(f\"JTAG Monitor req: {datum}\")\n self.ap.write(datum)\n" }, { "path": "verification/block/dmi/jtag_bfm.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport cocotb\nimport pyuvm\nfrom cocotb.triggers import ClockCycles, FallingEdge, ReadOnly, RisingEdge\nfrom jtag_pkg import *\nfrom pyuvm import *\n\nfrom common import *\n\n# =============================================================================\n\n\nclass MemoryModel:\n def __init__(self):\n self.memory = {}\n\n def write(self, addr, data):\n self.memory.update({addr, data})\n\n def read(self, addr):\n self.memory.setdefault(addr, 0)\n return self.memory.get[addr]\n\n def reset(self):\n self.memory = {}\n\n\nclass JTAGBfm(metaclass=utility_classes.Singleton):\n \"\"\"\n A Bus Functional Model for JTAG TAP.\n \"\"\"\n\n SIGNALS = [\n # Inputs\n \"trst_n\",\n \"tck\",\n \"tms\",\n \"tdi\",\n # Outputs\n \"tdo\",\n \"tdoEnable\",\n ]\n\n def __init__(self):\n self.dut = cocotb.top\n self.req_driver_q = UVMQueue(maxsize=1)\n self.req_monitor_q = UVMQueue(maxsize=0)\n self.rsp_monitor_q = UVMQueue(maxsize=0)\n\n self.predictor = ConfigDB().get(None, \"\", \"JTAG_PREDICTOR\")\n\n collect_signals(self.SIGNALS, self.dut, self)\n\n async def req_driver_q_put(self, tms, tdi):\n item = (tms, tdi)\n await self.req_driver_q.put(item)\n\n async def rsp_monitor_q_get(self):\n result = await self.rsp_monitor_q.get()\n return result\n\n async def reset(self):\n await FallingEdge(self.tck)\n self.trst_n.value = 0\n self.tms.value = 1\n self.tdi.value = 0\n await ClockCycles(self.tck, 10)\n await FallingEdge(self.tck)\n self.trst_n.value = 1\n await FallingEdge(self.tck)\n\n async def driver_bfm(self):\n sigs = [self.tms, self.tdi]\n for sig in sigs:\n sig.value = 0\n while True:\n await FallingEdge(self.tck)\n try:\n tms, tdi = self.req_driver_q.get_nowait()\n self.tms.value = tms\n self.tdi.value = tdi\n except QueueEmpty:\n pass\n\n async def req_monitor_q_bfm(self):\n while True:\n if self.trst_n.value == 0:\n await RisingEdge(self.trst_n)\n await RisingEdge(self.tck)\n\n item = (get_int(self.tms), get_int(self.tdi))\n self.req_monitor_q.put_nowait(item)\n\n async def rsp_monitor_q_bfm(self):\n while True:\n if self.trst_n.value == 0:\n await RisingEdge(self.trst_n)\n\n await FallingEdge(self.tck)\n await ReadOnly()\n self.predictor.predict_jtag_outputs(edge=\"neg\")\n\n await RisingEdge(self.tck)\n await ReadOnly()\n self.predictor.predict_jtag_outputs(edge=\"pos\")\n\n curr_values = [\n get_int(self.tdo),\n get_int(self.tdoEnable),\n ]\n predicted_values = [\n get_int(self.predictor.tdo),\n get_int(self.predictor.tdoEnable),\n ]\n self.rsp_monitor_q.put_nowait((curr_values, predicted_values))\n\n def start_bfm(self):\n cocotb.start_soon(self.driver_bfm())\n cocotb.start_soon(self.req_monitor_q_bfm())\n cocotb.start_soon(self.rsp_monitor_q_bfm())\n" }, { "path": "verification/block/dmi/jtag_pkg.py", "content": "from enum import IntEnum\n\nfrom cocotb.types import LogicArray, Range\n\n\nclass JTAGDefaults:\n IDLE = LogicArray(0, Range(1, \"downto\", 0))\n DMI_STAT = LogicArray(0, Range(1, \"downto\", 0))\n VERSION = LogicArray(1, Range(3, \"downto\", 0))\n RD_STATUS = LogicArray(0, Range(1, \"downto\", 0))\n\n\nclass JTAGInstructions:\n DEVICE_ID_SEL = LogicArray(0b00001, Range(4, \"downto\", 0))\n DR_EN_0 = LogicArray(0b10000, Range(4, \"downto\", 0))\n DR_EN_1 = LogicArray(0b10001, Range(4, \"downto\", 0))\n\n\nclass JTAGStates(IntEnum):\n TEST_LOGIC_RESET_STATE = 0\n RUN_TEST_IDLE_STATE = 1\n SELECT_DR_SCAN_STATE = 2\n CAPTURE_DR_STATE = 3\n SHIFT_DR_STATE = 4\n EXIT1_DR_STATE = 5\n PAUSE_DR_STATE = 6\n EXIT2_DR_STATE = 7\n UPDATE_DR_STATE = 8\n SELECT_IR_SCAN_STATE = 9\n CAPTURE_IR_STATE = 10\n SHIFT_IR_STATE = 11\n EXIT1_IR_STATE = 12\n PAUSE_IR_STATE = 13\n EXIT2_IR_STATE = 14\n UPDATE_IR_STATE = 15\n" }, { "path": "verification/block/dmi/jtag_predictor.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport os\n\nfrom cocotb.types import Logic, LogicArray, Range, concat\nfrom jtag_pkg import *\n\nfrom common import *\n\n\nclass JTAGPredictor:\n \"\"\"\n A predictor for JTAG TAP that is able to calculate current states of\n internal FSM, registers and output ports.\n \"\"\"\n\n def __init__(self, dut):\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n\n self.AWIDTH = AWIDTH = ConfigDB().get(None, \"\", \"AWIDTH\")\n self.reg_range = Range(AWIDTH + 33, \"downto\", 0)\n self.logger = uvm_root().logger\n self.logger.setLevel(level)\n self.dut = dut\n\n # Predicted output ports\n self.tdo = Logic(0)\n self.tdo_next = Logic(0)\n self.tdoEnable = Logic(0)\n self.wr_data = LogicArray(0, Range(31, \"downto\", 0))\n self.wr_addr = LogicArray(0, Range(AWIDTH - 1, \"downto\", 0))\n self.wr_en = Logic(0)\n self.rd_en = Logic(0)\n self.dmi_hard_reset = Logic(0)\n\n # JTAG input ports\n self.rd_data = dut.rd_data\n self.trst_n = dut.trst_n\n self.tms = dut.tms\n self.tdi = dut.tdi\n\n # Internal JTAG state and registers\n self.nstate = JTAGStates.TEST_LOGIC_RESET_STATE\n self.state = self.nstate\n self.prev_nstate = self.state\n self.ir = LogicArray(0x1, Range(4, \"downto\", 0))\n self.dr = LogicArray(0x0, self.reg_range)\n self.ndr = LogicArray(0x0, self.reg_range)\n self.sr = LogicArray(0x0, self.reg_range)\n self.nsr = LogicArray(0x0, self.reg_range)\n\n def __str__(self):\n str = \"TAP Controller currently in state: {}\\n\".format(JTAGStates(self.state).name)\n str += \"Expected vs actual outputs:\\n\"\n str += \"tdo: {} vs {}\\n\".format(hex(int(self.tdo)), hex(self.dut.tdo.value))\n str += \"tdoEnable: {} vs {}\\n\".format(\n hex(int(self.tdoEnable)), hex(self.dut.tdoEnable.value)\n )\n str += \"wr_data: {} vs {}\\n\".format(\n hex(self.wr_data.integer), hex(self.dut.reg_wr_data.value)\n )\n str += \"wr_addr: {} vs {}\\n\".format(\n hex(self.wr_addr.integer), hex(self.dut.reg_wr_addr.value)\n )\n str += \"wr_en: {} vs {}\\n\".format(\n hex(int(self.wr_en)), hex(self.dut.reg_wr_en.value)\n )\n str += \"rd_en: {} vs {}\\n\".format(hex(int(self.rd_en)), hex(self.dut.reg_en.value))\n str += \"dmi_hard_reset: {} vs {}\".format(\n hex(int(self.dmi_hard_reset)), hex(self.dut.dmi_hard_reset.value)\n )\n\n return str\n\n def update_state(self):\n if self.state != self.nstate:\n self.logger.debug(\n \"Switching state {} to {}\".format(\n JTAGStates(self.state).name,\n JTAGStates(self.nstate).name,\n )\n )\n self.state = self.nstate\n\n def update_nstate(self):\n \"\"\"\n State machine compliant with TAP Controller documentation (IEEE Std 1149.1-2001)\n and VeeR EL2 specific TAP implementation.\n \"\"\"\n self.prev_nstate = self.nstate\n if self.trst_n == 0:\n self.nstate = JTAGStates.TEST_LOGIC_RESET_STATE\n pass\n\n if self.state == JTAGStates.TEST_LOGIC_RESET_STATE:\n self.nstate = (\n JTAGStates.TEST_LOGIC_RESET_STATE\n if get_int(self.tms) == 1\n else JTAGStates.RUN_TEST_IDLE_STATE\n )\n\n elif self.state == JTAGStates.RUN_TEST_IDLE_STATE:\n self.nstate = (\n JTAGStates.SELECT_DR_SCAN_STATE\n if get_int(self.tms) == 1\n else JTAGStates.RUN_TEST_IDLE_STATE\n )\n\n elif self.state == JTAGStates.SELECT_DR_SCAN_STATE:\n self.nstate = (\n JTAGStates.SELECT_IR_SCAN_STATE\n if get_int(self.tms) == 1\n else JTAGStates.CAPTURE_DR_STATE\n )\n\n elif self.state == JTAGStates.CAPTURE_DR_STATE:\n self.nstate = (\n JTAGStates.EXIT1_DR_STATE if get_int(self.tms) == 1 else JTAGStates.SHIFT_DR_STATE\n )\n\n elif self.state == JTAGStates.SHIFT_DR_STATE:\n self.nstate = (\n JTAGStates.EXIT1_DR_STATE if get_int(self.tms) == 1 else JTAGStates.SHIFT_DR_STATE\n )\n\n elif self.state == JTAGStates.EXIT1_DR_STATE:\n self.nstate = (\n JTAGStates.UPDATE_DR_STATE if get_int(self.tms) == 1 else JTAGStates.PAUSE_DR_STATE\n )\n\n elif self.state == JTAGStates.PAUSE_DR_STATE:\n self.nstate = (\n JTAGStates.EXIT2_DR_STATE if get_int(self.tms) == 1 else JTAGStates.PAUSE_DR_STATE\n )\n\n elif self.state == JTAGStates.EXIT2_DR_STATE:\n self.nstate = (\n JTAGStates.UPDATE_DR_STATE if get_int(self.tms) == 1 else JTAGStates.SHIFT_DR_STATE\n )\n\n elif self.state == JTAGStates.UPDATE_DR_STATE:\n self.nstate = (\n JTAGStates.SELECT_DR_SCAN_STATE\n if get_int(self.tms) == 1\n else JTAGStates.RUN_TEST_IDLE_STATE\n )\n\n elif self.state == JTAGStates.SELECT_IR_SCAN_STATE:\n self.nstate = (\n JTAGStates.TEST_LOGIC_RESET_STATE\n if get_int(self.tms) == 1\n else JTAGStates.CAPTURE_IR_STATE\n )\n\n elif self.state == JTAGStates.CAPTURE_IR_STATE:\n self.nstate = (\n JTAGStates.EXIT1_IR_STATE if get_int(self.tms) == 1 else JTAGStates.SHIFT_IR_STATE\n )\n\n elif self.state == JTAGStates.SHIFT_IR_STATE:\n self.nstate = (\n JTAGStates.EXIT1_IR_STATE if get_int(self.tms) == 1 else JTAGStates.SHIFT_IR_STATE\n )\n\n elif self.state == JTAGStates.EXIT1_IR_STATE:\n self.nstate = (\n JTAGStates.UPDATE_IR_STATE if get_int(self.tms) == 1 else JTAGStates.PAUSE_IR_STATE\n )\n\n elif self.state == JTAGStates.PAUSE_IR_STATE:\n self.nstate = (\n JTAGStates.EXIT2_IR_STATE if get_int(self.tms) == 1 else JTAGStates.PAUSE_IR_STATE\n )\n\n elif self.state == JTAGStates.EXIT2_IR_STATE:\n self.nstate = (\n JTAGStates.UPDATE_IR_STATE if get_int(self.tms) == 1 else JTAGStates.SHIFT_IR_STATE\n )\n\n elif self.state == JTAGStates.UPDATE_IR_STATE:\n self.nstate = (\n JTAGStates.SELECT_DR_SCAN_STATE\n if get_int(self.tms) == 1\n else JTAGStates.RUN_TEST_IDLE_STATE\n )\n\n else:\n self.nstate = JTAGStates.TEST_LOGIC_RESET_STATE\n\n if self.prev_nstate != self.nstate:\n self.logger.debug(\n \"Switching nstate {} to {}\".format(\n JTAGStates(self.prev_nstate).name,\n JTAGStates(self.nstate).name,\n )\n )\n\n def predict_regs_posedge(self):\n \"\"\"\n Calculate values of internal registers IR, DR and SR\n \"\"\"\n self.dr = self.ndr\n\n if self.trst_n == 0:\n self.sr = LogicArray(0, self.reg_range)\n else:\n self.sr = LogicArray(get_int(self.nsr), self.reg_range)\n\n if self.trst_n == 0:\n self.nsr = LogicArray(0, self.nsr.range)\n self.ir = LogicArray(1, self.ir.range)\n self.ndr = LogicArray(0, self.dr.range)\n\n if self.state == JTAGStates.UPDATE_IR_STATE:\n self.ir = (\n LogicArray(0x1F, self.ir.range) if (self.sr[4:0].integer == 0) else self.sr[4:0]\n )\n\n if self.state == JTAGStates.UPDATE_DR_STATE and self.ir == JTAGInstructions.DR_EN_1:\n self.ndr = LogicArray(get_int(self.sr), self.reg_range)\n else:\n self.ndr = concat(self.dr[self.AWIDTH + 33 : 2], LogicArray(0, range(2)))\n\n self.predict_nsr_reg()\n\n def predict_nsr_reg(self):\n \"\"\"\n Calculate next value of the SR register\n \"\"\"\n tdi_lr = LogicArray(get_int(self.tdi))\n self.nsr = LogicArray(get_int(self.sr), self.reg_range)\n\n # Predict value of nsr register\n if self.state == JTAGStates.SHIFT_DR_STATE:\n if self.ir == JTAGInstructions.DR_EN_1:\n self.nsr = concat(tdi_lr, self.sr[self.AWIDTH + 33 : 1])\n\n elif self.ir in [JTAGInstructions.DR_EN_0, JTAGInstructions.DEVICE_ID_SEL]:\n self.nsr = concat(\n LogicArray(0, range(self.AWIDTH + 2)), concat(tdi_lr, self.sr[31:1])\n )\n\n else:\n self.nsr = LogicArray(get_int(self.tdi), self.nsr.range)\n\n elif self.state == JTAGStates.CAPTURE_DR_STATE:\n self.nsr[0] = 0\n if self.ir == JTAGInstructions.DR_EN_0:\n self.nsr = concat(\n LogicArray(0, range(self.AWIDTH + 19)),\n concat(\n concat(concat(JTAGDefaults.IDLE, JTAGDefaults.DMI_STAT), Defaults.ABITS),\n JTAGDefaults.VERSION,\n ),\n )\n\n elif self.ir == JTAGInstructions.DR_EN_1:\n self.nsr = concat(\n concat(\n LogicArray(0, range(self.AWIDTH)),\n LogicArray(self.rd_data.value, Range(31, \"downto\", 0)),\n ),\n JTAGDefaults.RD_STATUS,\n )\n\n elif self.ir == JTAGInstructions.DEVICE_ID_SEL:\n self.nsr = concat(\n LogicArray(0, range(self.AWIDTH + 2)), concat(Defaults.JTAG_ID, LogicArray(1))\n )\n\n elif self.state == JTAGStates.SHIFT_IR_STATE:\n self.nsr = concat(LogicArray(0, range(self.AWIDTH + 29)), concat(tdi_lr, self.sr[4:1]))\n\n elif self.state == JTAGStates.CAPTURE_IR_STATE:\n self.nsr = LogicArray(1, self.reg_range)\n\n def predict_regs_negedge(self):\n self.tdo = Logic(get_int(self.sr[0]))\n self.tdoEnable = (\n Logic(1)\n if self.state in [JTAGStates.SHIFT_DR_STATE, JTAGStates.SHIFT_IR_STATE]\n else Logic(0)\n )\n self.predict_nsr_reg()\n\n def predict_ports(self):\n \"\"\"\n Calculate JTAG TAP output ports' values\n \"\"\"\n\n self.tdoEnable = (\n Logic(1)\n if self.state in [JTAGStates.SHIFT_DR_STATE, JTAGStates.SHIFT_IR_STATE]\n else Logic(0)\n )\n\n self.wr_addr = LogicArray(get_int(self.dr[self.AWIDTH + 34 - 1 : 34]))\n self.wr_data = LogicArray(get_int(self.dr[33:2]))\n self.wr_en = Logic(get_int(self.dr[1]))\n self.rd_en = Logic(get_int(self.dr[0]))\n\n if self.trst_n == 0:\n self.dmi_hard_reset = Logic(0)\n if self.state == JTAGStates.UPDATE_DR_STATE and self.ir == JTAGInstructions.DR_EN_0:\n self.dmi_hard_reset = Logic(get_int(self.sr[17]))\n else:\n self.dmi_hard_reset = Logic(0)\n\n def predict_jtag_outputs(self, edge):\n \"\"\"\n Predict JTAG TAP internal state and outputs based on current inputs.\n This method is assumed to be executed just after detecting an edge of\n the clock. Since it must know previous state of the FSM, prediction\n should be executed after each clock edge.\n \"\"\"\n\n assert edge in [\"pos\", \"neg\"]\n\n self.update_nstate()\n\n if edge == \"pos\":\n self.update_state()\n self.predict_regs_posedge()\n else:\n self.predict_regs_negedge()\n\n self.predict_ports()\n self.logger.debug(str(self))\n self.logger.debug(\"Internal registers:\")\n self.logger.debug(\"nsr: {}\".format(self.nsr))\n self.logger.debug(\"sr: {}\".format(self.sr))\n self.logger.debug(\"dr: {}\".format(self.dr))\n self.logger.debug(\"ir: {}\\n\".format(self.ir))\n" }, { "path": "verification/block/dmi/jtag_seq.py", "content": "#\n# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: BSD-2-Clause\n\nfrom pyuvm import *\n\nfrom common import BaseSeq\n\n\nclass JTAGBaseSeqItem(uvm_sequence_item):\n def __init__(self, name, tms=1, tdi=0):\n super().__init__(name)\n self.name = name\n self.tms = tms\n self.tdi = tdi\n\n def __str__(self):\n return self.__class__.__name__\n\n def randomize(self):\n pass\n\n\nclass SetIRSequence(BaseSeq):\n def __init__(self, name, instruction):\n super().__init__(name)\n self.instr = instruction\n\n async def body(self):\n items = [\n JTAGBaseSeqItem(\"switch_to_select_dr_scan\", 1, 0),\n JTAGBaseSeqItem(\"switch_to_select_ir_scan\", 1, 0),\n JTAGBaseSeqItem(\"switch_to_capture_ir\", 0, 0),\n JTAGBaseSeqItem(\"switch_to_shift_ir\", 0, 0),\n JTAGBaseSeqItem(\"shift_ir_bit_0\", 0, (self.instr >> 0) & 0x1),\n JTAGBaseSeqItem(\"shift_ir_bit_1\", 0, (self.instr >> 1) & 0x1),\n JTAGBaseSeqItem(\"shift_ir_bit_2\", 0, (self.instr >> 2) & 0x1),\n JTAGBaseSeqItem(\"shift_ir_bit_3\", 0, (self.instr >> 3) & 0x1),\n JTAGBaseSeqItem(\"switch_to_exit1_ir\", 1, (self.instr >> 4) & 0x1),\n JTAGBaseSeqItem(\"switch_to_update_ir\", 1, 0),\n JTAGBaseSeqItem(\"switch_to_idle\", 0, 0),\n JTAGBaseSeqItem(\"idle0\", 0, 0),\n JTAGBaseSeqItem(\"idle1\", 0, 0),\n ]\n await self.run_items(items)\n\n\nclass ReadIDCODESequence(SetIRSequence):\n def __init__(self, name):\n super().__init__(name, 0b00001)\n\n\nclass CaptureDRSequence(BaseSeq):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n shift_dr_items = []\n for i in range(40):\n shift_dr_items.append(JTAGBaseSeqItem(\"shift_dr_bit{}\".format(i), 0, 0))\n\n items = [\n JTAGBaseSeqItem(\"switch_to_select_dr_scan\", 1, 0),\n JTAGBaseSeqItem(\"switch_to_capture_dr\", 0, 0),\n JTAGBaseSeqItem(\"switch_to_shift_dr\", 0, 0),\n ]\n items += shift_dr_items\n items += [\n JTAGBaseSeqItem(\"switch_to_exit1_dr\", 1, 0),\n JTAGBaseSeqItem(\"switch_to_update_dr\", 1, 0),\n JTAGBaseSeqItem(\"switch_to_idle\", 0, 0),\n JTAGBaseSeqItem(\"idle0\", 0, 0),\n JTAGBaseSeqItem(\"idle1\", 0, 0),\n ]\n\n await self.run_items(items)\n" }, { "path": "verification/block/dmi/test_dmi_read_write.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom dmi_seq import *\nfrom jtag_seq import *\nfrom testbench import BaseTest\n\n\n@pyuvm.test()\nclass TestDMIReadRegs(BaseTest):\n def end_of_elaboration_phase(self):\n self.seqr = ConfigDB().get(None, \"\", \"JTAG_SEQR\")\n self.set_ir_dren0_seq = SetIRSequence(\"set_ir_seq\", 0b10000)\n self.set_ir_dren1_seq = SetIRSequence(\"set_ir_seq\", 0b10001)\n self.read_dmcontrol_seq = AccessDMIRegSequence(\"read_dmcontrol_seq\", addr=0x10)\n self.read_dmstatus_seq = AccessDMIRegSequence(\"read_dmstatus_seq\", addr=0x11)\n\n async def run(self):\n await self.set_ir_dren0_seq.start(self.seqr)\n await self.read_dmcontrol_seq.start(self.seqr)\n await self.set_ir_dren1_seq.start(self.seqr)\n await self.read_dmstatus_seq.start(self.seqr)\n\n\n@pyuvm.test()\nclass TestDMIWriteRegs(BaseTest):\n def end_of_elaboration_phase(self):\n self.seqr = ConfigDB().get(None, \"\", \"JTAG_SEQR\")\n self.set_ir_dren1_seq = SetIRSequence(\"set_ir_seq\", 0b10001)\n self.write_dmcontrol_seq = AccessDMIRegSequence(\n \"write_dmcontrol_seq\", addr=0x10, data=0x01234567, is_write=True\n )\n self.write_dmstatus_seq = AccessDMIRegSequence(\n \"write_dmstatus_seq\", addr=0x11, data=0xDEADBEEF, is_write=True\n )\n\n async def run(self):\n await self.set_ir_dren1_seq.start(self.seqr)\n await self.write_dmcontrol_seq.start(self.seqr)\n await self.write_dmstatus_seq.start(self.seqr)\n\n\n@pyuvm.test()\nclass TestDMIReadWriteRegs(BaseTest):\n def end_of_elaboration_phase(self):\n self.seqr = ConfigDB().get(None, \"\", \"JTAG_SEQR\")\n self.set_ir_dren1_seq = SetIRSequence(\"set_ir_seq\", 0b10001)\n self.write_dmcontrol_seq = AccessDMIRegSequence(\n \"write_dmcontrol_seq\", addr=0x10, data=0x01234567, is_write=True\n )\n self.write_dmstatus_seq = AccessDMIRegSequence(\n \"write_dmstatus_seq\", addr=0x11, data=0xDEADBEEF, is_write=True\n )\n self.read_dmcontrol_seq = AccessDMIRegSequence(\"read_dmcontrol_seq\", addr=0x10)\n self.read_dmstatus_seq = AccessDMIRegSequence(\"read_dmstatus_seq\", addr=0x11)\n\n async def run(self):\n await self.set_ir_dren1_seq.start(self.seqr)\n await self.write_dmcontrol_seq.start(self.seqr)\n await self.write_dmstatus_seq.start(self.seqr)\n await self.read_dmcontrol_seq.start(self.seqr)\n await self.read_dmstatus_seq.start(self.seqr)\n\n\n@pyuvm.test()\nclass TestUncoreDMIReadWriteRegs(BaseTest):\n def end_of_elaboration_phase(self):\n self.jtag_seqr = ConfigDB().get(None, \"\", \"JTAG_SEQR\")\n self.dmi_seqr = ConfigDB().get(None, \"\", \"DMI_SEQR\")\n self.uncore_enable_seq = SetUncoreEnableSequence(\"uncore_enable_seq\", 1)\n self.set_ir_dren1_seq = SetIRSequence(\"set_ir_seq\", 0b10001)\n self.write_core_seq1 = AccessDMIRegSequence(\n \"write_core_seq1\", addr=0x11, data=0xDEADBEEF, is_write=True\n )\n self.write_uncore_seq1 = AccessDMIRegSequence(\n \"write_uncore_seq1\", addr=0x7F, data=0x76543210, is_write=True\n )\n self.read_core_seq1 = AccessDMIRegSequence(\"read_core_seq1\", addr=0x11)\n self.read_uncore_seq1 = AccessDMIRegSequence(\"read_uncore_seq1\", addr=0x7F)\n self.write_core_seq2 = AccessDMIRegSequence(\n \"write_core_seq2\", addr=0x4F, data=0xBEEFDEAD, is_write=True\n )\n self.write_uncore_seq2 = AccessDMIRegSequence(\n \"write_uncore_seq2\", addr=0x50, data=0xFEEDABED, is_write=True\n )\n self.read_core_seq2 = AccessDMIRegSequence(\"read_core_seq2\", addr=0x4F)\n self.read_uncore_seq2 = AccessDMIRegSequence(\"read_uncore_seq2\", addr=0x50)\n\n async def run(self):\n await self.uncore_enable_seq.start(self.dmi_seqr)\n await self.set_ir_dren1_seq.start(self.jtag_seqr)\n await self.write_core_seq1.start(self.jtag_seqr)\n await self.write_uncore_seq1.start(self.jtag_seqr)\n await self.read_core_seq1.start(self.jtag_seqr)\n await self.read_uncore_seq1.start(self.jtag_seqr)\n await self.write_core_seq2.start(self.jtag_seqr)\n await self.write_uncore_seq2.start(self.jtag_seqr)\n await self.read_core_seq2.start(self.jtag_seqr)\n await self.read_uncore_seq2.start(self.jtag_seqr)\n" }, { "path": "verification/block/dmi/test_dmi_tap_fsm.py", "content": "import cocotb\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import RisingEdge, Timer\n\n# TAP State Constants (renamed to *_STATE format)\nTEST_LOGIC_RESET_STATE = 0x0\nRUN_TEST_IDLE_STATE = 0x1\nSELECT_DR_SCAN_STATE = 0x2\nCAPTURE_DR_STATE = 0x3\nSHIFT_DR_STATE = 0x4\nEXIT1_DR_STATE = 0x5\nPAUSE_DR_STATE = 0x6\nEXIT2_DR_STATE = 0x7\nUPDATE_DR_STATE = 0x8\nSELECT_IR_SCAN_STATE = 0x9\nCAPTURE_IR_STATE = 0xA\nSHIFT_IR_STATE = 0xB\nEXIT1_IR_STATE = 0xC\nPAUSE_IR_STATE = 0xD\nEXIT2_IR_STATE = 0xE\nUPDATE_IR_STATE = 0xF\n\n# Define the TAP state transition table\nTAP_TRANSITIONS = {\n (TEST_LOGIC_RESET_STATE, TEST_LOGIC_RESET_STATE): 1,\n (TEST_LOGIC_RESET_STATE, RUN_TEST_IDLE_STATE): 0,\n (RUN_TEST_IDLE_STATE, SELECT_DR_SCAN_STATE): 1,\n (RUN_TEST_IDLE_STATE, RUN_TEST_IDLE_STATE): 0,\n (SELECT_DR_SCAN_STATE, SELECT_IR_SCAN_STATE): 1,\n (SELECT_DR_SCAN_STATE, CAPTURE_DR_STATE): 0,\n (CAPTURE_DR_STATE, EXIT1_DR_STATE): 1,\n (CAPTURE_DR_STATE, SHIFT_DR_STATE): 0,\n (SHIFT_DR_STATE, EXIT1_DR_STATE): 1,\n (SHIFT_DR_STATE, SHIFT_DR_STATE): 0,\n (EXIT1_DR_STATE, UPDATE_DR_STATE): 1,\n (EXIT1_DR_STATE, PAUSE_DR_STATE): 0,\n (PAUSE_DR_STATE, EXIT2_DR_STATE): 1,\n (PAUSE_DR_STATE, PAUSE_DR_STATE): 0,\n (EXIT2_DR_STATE, UPDATE_DR_STATE): 1,\n (EXIT2_DR_STATE, SHIFT_DR_STATE): 0,\n (UPDATE_DR_STATE, SELECT_DR_SCAN_STATE): 1,\n (UPDATE_DR_STATE, RUN_TEST_IDLE_STATE): 0,\n (SELECT_IR_SCAN_STATE, TEST_LOGIC_RESET_STATE): 1,\n (SELECT_IR_SCAN_STATE, CAPTURE_IR_STATE): 0,\n (CAPTURE_IR_STATE, EXIT1_IR_STATE): 1,\n (CAPTURE_IR_STATE, SHIFT_IR_STATE): 0,\n (SHIFT_IR_STATE, EXIT1_IR_STATE): 1,\n (SHIFT_IR_STATE, SHIFT_IR_STATE): 0,\n (EXIT1_IR_STATE, UPDATE_IR_STATE): 1,\n (EXIT1_IR_STATE, PAUSE_IR_STATE): 0,\n (PAUSE_IR_STATE, EXIT2_IR_STATE): 1,\n (PAUSE_IR_STATE, PAUSE_IR_STATE): 0,\n (EXIT2_IR_STATE, UPDATE_IR_STATE): 1,\n (EXIT2_IR_STATE, SHIFT_IR_STATE): 0,\n (UPDATE_IR_STATE, SELECT_DR_SCAN_STATE): 1,\n (UPDATE_IR_STATE, RUN_TEST_IDLE_STATE): 0,\n}\n\n# Traverse each possible transition\nTEST_PATH = [\n TEST_LOGIC_RESET_STATE,\n TEST_LOGIC_RESET_STATE,\n RUN_TEST_IDLE_STATE,\n RUN_TEST_IDLE_STATE,\n SELECT_DR_SCAN_STATE,\n CAPTURE_DR_STATE,\n SHIFT_DR_STATE,\n SHIFT_DR_STATE,\n EXIT1_DR_STATE,\n PAUSE_DR_STATE,\n PAUSE_DR_STATE,\n EXIT2_DR_STATE,\n UPDATE_DR_STATE,\n SELECT_DR_SCAN_STATE,\n CAPTURE_DR_STATE,\n EXIT1_DR_STATE,\n PAUSE_DR_STATE,\n EXIT2_DR_STATE,\n UPDATE_DR_STATE,\n RUN_TEST_IDLE_STATE,\n SELECT_DR_SCAN_STATE,\n CAPTURE_DR_STATE,\n EXIT1_DR_STATE,\n PAUSE_DR_STATE,\n EXIT2_DR_STATE,\n SHIFT_DR_STATE,\n EXIT1_DR_STATE,\n UPDATE_DR_STATE,\n RUN_TEST_IDLE_STATE,\n SELECT_DR_SCAN_STATE,\n SELECT_IR_SCAN_STATE,\n CAPTURE_IR_STATE,\n SHIFT_IR_STATE,\n SHIFT_IR_STATE,\n EXIT1_IR_STATE,\n PAUSE_IR_STATE,\n PAUSE_IR_STATE,\n EXIT2_IR_STATE,\n SHIFT_IR_STATE,\n EXIT1_IR_STATE,\n PAUSE_IR_STATE,\n EXIT2_IR_STATE,\n UPDATE_IR_STATE,\n SELECT_DR_SCAN_STATE,\n SELECT_IR_SCAN_STATE,\n TEST_LOGIC_RESET_STATE,\n RUN_TEST_IDLE_STATE,\n SELECT_DR_SCAN_STATE,\n SELECT_IR_SCAN_STATE,\n CAPTURE_IR_STATE,\n EXIT1_IR_STATE,\n UPDATE_IR_STATE,\n]\n\n\n@cocotb.test()\nasync def test_full_tap_fsm(dut):\n \"\"\"Exercise all possible TAP FSM states via TMS and TCK.\"\"\"\n cocotb.start_soon(Clock(dut.tck, 3, units=\"ns\").start())\n cocotb.start_soon(Clock(dut.core_clk, 1, units=\"ns\").start())\n\n # Assert tms to ensure entering the test with `TEST_LOGIC_RESET_STATE`\n dut.tms.value = 1\n\n # Apply reset (active-low)\n dut.trst_n.value = 0\n await Timer(20, units=\"ns\")\n dut.trst_n.value = 1\n await RisingEdge(dut.tck)\n\n # Ensure FSM starts in Test-Logic-Reset\n assert (\n dut.wrapper.i_jtag_tap.state.value == TEST_LOGIC_RESET_STATE\n ), f\"Expected state TEST_LOGIC_RESET_STATE, got {dut.wrapper.i_jtag_tap.state.value}\"\n\n assert (\n dut.wrapper.i_jtag_tap.state.value == TEST_LOGIC_RESET_STATE\n ), f\"Expected state TEST_LOGIC_RESET_STATE after reset, got {dut.wrapper.i_jtag_tap.state.value}\"\n\n # Iterate through all valid state transitions\n for i in range(len(TEST_PATH) - 1):\n s0, s1 = TEST_PATH[i], TEST_PATH[i + 1]\n tms_value = TAP_TRANSITIONS[(s0, s1)]\n\n # Apply TMS value\n dut.tms.value = tms_value\n await RisingEdge(dut.tck)\n\n assert (\n dut.wrapper.i_jtag_tap.state.value == s0 and dut.wrapper.i_jtag_tap.nstate.value == s1\n ), f\"Expected state {s0}, got {dut.wrapper.i_jtag_tap.state.value}\"\n\n # Apply reset (active-low)\n dut.trst_n.value = 0\n await RisingEdge(dut.tck)\n\n assert (\n dut.wrapper.i_jtag_tap.state.value == TEST_LOGIC_RESET_STATE\n ), f\"Expected state TEST_LOGIC_RESET_STATE after reset, got {dut.wrapper.i_jtag_tap.state.value}\"\n" }, { "path": "verification/block/dmi/test_jtag_ir.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom jtag_pkg import JTAGInstructions\nfrom jtag_seq import *\nfrom testbench import BaseTest\n\n\n@pyuvm.test()\nclass TestJTAGSetIR(BaseTest):\n def end_of_elaboration_phase(self):\n self.seqr = ConfigDB().get(None, \"\", \"JTAG_SEQR\")\n self.set_ir_seq = SetIRSequence(\"set_ir_seq\", JTAGInstructions.DEVICE_ID_SEL.integer)\n\n async def run(self):\n await self.set_ir_seq.start(self.seqr)\n\n\n@pyuvm.test()\nclass TestJTAGReadIDCODE(BaseTest):\n def end_of_elaboration_phase(self):\n self.seqr = ConfigDB().get(None, \"\", \"JTAG_SEQR\")\n self.read_idcode_seq = CaptureDRSequence(\"read_idcode_seq\")\n\n async def run(self):\n await self.read_idcode_seq.start(self.seqr)\n\n\n@pyuvm.test()\nclass TestJTAGSetIRReadDR(BaseTest):\n def end_of_elaboration_phase(self):\n self.seqr = ConfigDB().get(None, \"\", \"JTAG_SEQR\")\n self.set_ir_seq = SetIRSequence(\"set_ir_seq\", JTAGInstructions.DEVICE_ID_SEL.integer)\n self.read_idcode_seq = CaptureDRSequence(\"read_idcode_seq\")\n\n async def run(self):\n await self.set_ir_seq.start(self.seqr)\n await self.read_idcode_seq.start(self.seqr)\n" }, { "path": "verification/block/dmi/testbench.py", "content": "#\n# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport os\nfrom decimal import Decimal\n\nimport pyuvm\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, Timer\nfrom dmi_agent import DMIAgent\nfrom jtag_agent import JTAGAgent\nfrom jtag_predictor import JTAGPredictor\nfrom pyuvm import *\n\n\nclass Scoreboard(uvm_scoreboard):\n def build_phase(self):\n self.jtag_rsp_fifo = uvm_tlm_analysis_fifo(\"jtag_rsp_fifo\", self)\n self.jtag_rsp_get_port = uvm_get_port(\"jtag_rsp_get_port\", self)\n self.jtag_rsp_export = self.jtag_rsp_fifo.analysis_export\n\n self.dmi_rsp_fifo = uvm_tlm_analysis_fifo(\"dmi_rsp_fifo\", self)\n self.dmi_rsp_get_port = uvm_get_port(\"dmi_rsp_get_port\", self)\n self.dmi_rsp_export = self.dmi_rsp_fifo.analysis_export\n\n def connect_phase(self):\n self.jtag_rsp_get_port.connect(self.jtag_rsp_fifo.get_export)\n self.dmi_rsp_get_port.connect(self.dmi_rsp_fifo.get_export)\n\n def check_phase(self):\n self.logger.debug(\"Entering Scoreboard check phase\")\n self.check_jtag()\n self.check_dmi()\n\n def check_dmi(self):\n passed = True\n while self.dmi_rsp_get_port.can_get():\n _, item = self.dmi_rsp_get_port.try_get()\n\n values, dmi_type = item\n rd_data, dmi_rdata, dmi_addr, dmi_en, pred_en = values\n\n if pred_en != dmi_en:\n self.logger.error(\"Unexpected state of DMI enable signal\")\n passed = False\n\n self.logger.debug(\"Checking DMI {} at address {}\".format(dmi_type, str(hex(dmi_addr))))\n if dmi_en and (rd_data != dmi_rdata):\n self.logger.error(\n \"Read data does not match expected data ({} vs {})\".format(\n str(hex(rd_data)), str(hex(dmi_rdata))\n )\n )\n passed = False\n\n assert passed\n\n def check_jtag(self):\n passed = True\n while self.jtag_rsp_get_port.can_get():\n _, item = self.jtag_rsp_get_port.try_get()\n\n out_ports = item[0]\n predicted_ports = item[1]\n\n for i, s in enumerate([\"tdo\", \"tdoEnable\"]):\n out = out_ports[i]\n predicted = predicted_ports[i]\n\n self.logger.debug(\n \"Current check of {} (actual: {} vs expected: {})\".format(s, out, predicted)\n )\n if out != predicted:\n self.logger.error(\"Unexpected state of {} ({} vs {})\".format(s, out, predicted))\n passed = False\n\n assert passed\n\n\nclass BaseEnvironment(uvm_env):\n def __init__(self, name, test_obj):\n super().__init__(name, test_obj)\n\n def build_phase(self):\n # Config\n # JTAG clock must be at least twice as fast as core clock\n ConfigDB().set(None, \"*\", \"TEST_JTAG_CLK_PERIOD\", 3)\n ConfigDB().set(None, \"*\", \"TEST_CORE_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"AWIDTH\", 7)\n\n self.jtag_agent = JTAGAgent(\"jtag_agent\", self)\n self.dmi_agent = DMIAgent(\"dmi_agent\", self)\n self.predictor = JTAGPredictor(cocotb.top)\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n ConfigDB().set(None, \"*\", \"JTAG_PREDICTOR\", self.predictor)\n\n def connect_phase(self):\n self.jtag_agent.monitor.ap.connect(self.scoreboard.jtag_rsp_export)\n self.dmi_agent.monitor.ap.connect(self.scoreboard.dmi_rsp_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n # Synchronize pyuvm logging level with cocotb logging level.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = BaseEnvironment(\"env\", self)\n\n def start_clock(self, name, period):\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self, signals, timeLength=\"100e-9\", isActiveHigh=True):\n assert isinstance(signals, list)\n\n for s in signals:\n signal = getattr(cocotb.top, s)\n signal.value = int(isActiveHigh)\n\n await Timer(Decimal(timeLength), units=\"sec\")\n\n for s in signals:\n signal = getattr(cocotb.top, s)\n signal.value = not int(isActiveHigh)\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n core_period = ConfigDB().get(None, \"\", \"TEST_CORE_CLK_PERIOD\")\n jtag_period = ConfigDB().get(None, \"\", \"TEST_JTAG_CLK_PERIOD\")\n self.start_clock(\"core_clk\", core_period)\n self.start_clock(\"tck\", jtag_period)\n clk = getattr(cocotb.top, \"core_clk\")\n\n # Issue reset\n resetLength = \"100e-9\"\n await self.do_reset(\n signals=[\"trst_n\", \"core_rst_n\"], timeLength=resetLength, isActiveHigh=False\n )\n\n await ClockCycles(clk, 2)\n await self.run()\n await ClockCycles(clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/exu_alu/Makefile", "content": "\nnull :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_exu_alu_ctl_wrapper\n\nVERILOG_SOURCES = \\\n $(TEST_DIR)/el2_exu_alu_ctl_wrapper.sv \\\n $(SRCDIR)/exu/el2_exu_alu_ctl.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/exu_alu/config.vlt", "content": "`verilator_config\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_exu_alu_ctl_wrapper.sv\"\n\nlint_off -rule UNUSEDPARAM -file \"*/el2_exu_alu_ctl_wrapper.sv\"\n" }, { "path": "verification/block/exu_alu/el2_exu_alu_ctl_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro\n// SPDX-License-Identifier: Apache-2.0\nmodule el2_exu_alu_ctl_wrapper\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n)\n(\n input logic clk,\n input logic rst_l,\n input logic scan_mode,\n \n input logic flush_upper_x,\n input logic flush_lower_r,\n input logic enable,\n input logic valid_in,\n \n // Unpacked el2_alu_pkt_t\n input logic ap_clz,\n input logic ap_ctz,\n input logic ap_cpop,\n input logic ap_sext_b,\n input logic ap_sext_h,\n input logic ap_min,\n input logic ap_max,\n input logic ap_pack,\n input logic ap_packu,\n input logic ap_packh,\n input logic ap_rol,\n input logic ap_ror,\n input logic ap_grev,\n input logic ap_gorc,\n input logic ap_zbb,\n input logic ap_bset,\n input logic ap_bclr,\n input logic ap_binv,\n input logic ap_bext,\n input logic ap_sh1add,\n input logic ap_sh2add,\n input logic ap_sh3add,\n input logic ap_zba,\n input logic ap_land,\n input logic ap_lor,\n input logic ap_lxor,\n input logic ap_sll,\n input logic ap_srl,\n input logic ap_sra,\n input logic ap_beq,\n input logic ap_bne,\n input logic ap_blt,\n input logic ap_bge,\n input logic ap_add,\n input logic ap_sub,\n input logic ap_slt,\n input logic ap_unsignl,\n input logic ap_jall,\n input logic ap_predict_tl,\n input logic ap_predict_nt,\n input logic ap_csr_write,\n input logic ap_csr_imm,\n \n input logic csr_ren_in,\n input logic [31:0] csr_rddata_in,\n input logic signed [31:0] a_in,\n input logic [31:0] b_in,\n input logic [31:1] pc_in,\n input el2_predict_pkt_t pp_in,\n input logic [12:1] brimm_in,\n \n \n output logic [31:0] result_ff,\n output logic flush_upper_out,\n output logic flush_final_out,\n output logic [31:1] flush_path_out,\n output logic [31:1] pc_ff,\n output logic pred_correct_out,\n output el2_predict_pkt_t predict_p_out\n);\n\n // Pack ap\n el2_alu_pkt_t ap;\n assign ap.clz = ap_clz;\n assign ap.ctz = ap_ctz;\n assign ap.cpop = ap_cpop;\n assign ap.sext_b = ap_sext_b;\n assign ap.sext_h = ap_sext_h;\n assign ap.min = ap_min;\n assign ap.max = ap_max;\n assign ap.pack = ap_pack;\n assign ap.packu = ap_packu;\n assign ap.packh = ap_packh;\n assign ap.rol = ap_rol;\n assign ap.ror = ap_ror;\n assign ap.grev = ap_grev;\n assign ap.gorc = ap_gorc;\n assign ap.zbb = ap_zbb;\n assign ap.bset = ap_bset;\n assign ap.bclr = ap_bclr;\n assign ap.binv = ap_binv;\n assign ap.bext = ap_bext;\n assign ap.sh1add = ap_sh1add;\n assign ap.sh2add = ap_sh2add;\n assign ap.sh3add = ap_sh3add;\n assign ap.zba = ap_zba;\n assign ap.land = ap_land;\n assign ap.lor = ap_lor;\n assign ap.lxor = ap_lxor;\n assign ap.sll = ap_sll;\n assign ap.srl = ap_srl;\n assign ap.sra = ap_sra;\n assign ap.beq = ap_beq;\n assign ap.bne = ap_bne;\n assign ap.blt = ap_blt;\n assign ap.bge = ap_bge;\n assign ap.add = ap_add;\n assign ap.sub = ap_sub;\n assign ap.slt = ap_slt;\n assign ap.unsign = ap_unsignl;\n assign ap.jal = ap_jall;\n assign ap.predict_t = ap_predict_tl;\n assign ap.predict_nt = ap_predict_nt;\n assign ap.csr_write = ap_csr_write;\n assign ap.csr_imm = ap_csr_imm;\n\n // EXU ALU\n el2_exu_alu_ctl alu (.*);\n\nendmodule\n\n" }, { "path": "verification/block/exu_alu/test_arith.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseSequence, BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestAdd(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"add\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestSub(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"sub\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestAll(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"add\", \"sub\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n" }, { "path": "verification/block/exu_alu/test_logic.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseSequence, BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestAnd(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"and\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestOr(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"or\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestXor(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"xor\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestAll(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"and\", \"or\", \"xor\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n" }, { "path": "verification/block/exu_alu/test_zba.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseSequence, BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestSh1add(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"sh1add\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestSh2add(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"sh2add\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestSh3add(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"sh3add\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestAll(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"sh1add\", \"sh2add\", \"sh3add\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n" }, { "path": "verification/block/exu_alu/test_zbb.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseSequence, BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestClz(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"clz\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestCtz(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"ctz\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestCpop(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"cpop\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestSextb(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"sext_b\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestSexth(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"sext_h\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestRol(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"rol\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestRor(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"ror\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestAll(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\n \"stimulus\", [\"clz\", \"ctz\", \"cpop\", \"sext_b\", \"sext_h\", \"rol\", \"ror\"]\n )\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n" }, { "path": "verification/block/exu_alu/test_zbp.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseSequence, BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestPack(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"pack\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestPackh(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"packh\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestAll(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"pack\", \"packh\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n" }, { "path": "verification/block/exu_alu/test_zbs.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseSequence, BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestBset(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"bset\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestBclr(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"bclr\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestBinv(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"binv\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestBext(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"bext\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n\n\n@pyuvm.test()\nclass TestAll(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"bset\", \"bclr\", \"binv\", \"bext\"])\n\n async def run(self):\n await self.seq.start(self.env.alu_seqr)\n" }, { "path": "verification/block/exu_alu/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport math\nimport os\nimport random\nimport struct\n\nimport pyuvm\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import (\n ClockCycles,\n Event,\n FallingEdge,\n First,\n Lock,\n RisingEdge,\n Timer,\n)\nfrom pyuvm import *\n\n# ==============================================================================\n\n\nclass AluInputItem(uvm_sequence_item):\n \"\"\"\n ALU input data\n \"\"\"\n\n def __init__(self, op, a, b, csr=0, pc=0):\n super().__init__(\"AluInputItem\")\n self.op = op\n self.a = a\n self.b = b\n self.csr = csr\n self.pc = pc\n\n\nclass AluOutputItem(uvm_sequence_item):\n \"\"\"\n ALU output data\n \"\"\"\n\n def __init__(self, out):\n super().__init__(\"AluOutputItem\")\n self.out = out\n\n\n# ==============================================================================\n\n\nclass AluDriver(uvm_driver):\n \"\"\"\n ALU input driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, AluInputItem):\n # Wait for rising edge\n await RisingEdge(self.dut.clk)\n self.dut.valid_in.value = 1\n\n # Zbb\n self.dut.ap_clz.value = it.op in [\"clz\"]\n self.dut.ap_ctz.value = it.op in [\"ctz\"]\n self.dut.ap_cpop.value = it.op in [\"cpop\"]\n self.dut.ap_sext_b.value = it.op in [\"sext_b\"]\n self.dut.ap_sext_h.value = it.op in [\"sext_h\"]\n self.dut.ap_rol.value = it.op in [\"rol\"]\n self.dut.ap_ror.value = it.op in [\"ror\"]\n\n # Zbs\n self.dut.ap_bset.value = it.op in [\"bset\"]\n self.dut.ap_bclr.value = it.op in [\"bclr\"]\n self.dut.ap_binv.value = it.op in [\"binv\"]\n self.dut.ap_bext.value = it.op in [\"bext\"]\n\n # Zbp\n self.dut.ap_pack.value = it.op in [\"pack\"]\n self.dut.ap_packh.value = it.op in [\"packh\"]\n\n # Zba\n self.dut.ap_sh1add.value = it.op in [\"sh1add\"]\n self.dut.ap_sh2add.value = it.op in [\"sh2add\"]\n self.dut.ap_sh3add.value = it.op in [\"sh3add\"]\n # ap_zba has to be set to 1 to use sh??add instructions\n self.dut.ap_zba.value = it.op in [\"sh1add\", \"sh2add\", \"sh3add\"]\n\n # Arith\n self.dut.ap_add.value = it.op in [\"add\"]\n self.dut.ap_sub.value = it.op in [\"sub\"]\n self.dut.ap_land.value = it.op in [\"and\"]\n self.dut.ap_lor.value = it.op in [\"or\"]\n self.dut.ap_lxor.value = it.op in [\"xor\"]\n\n # Operands\n self.dut.a_in.value = it.a\n self.dut.b_in.value = it.b\n self.dut.csr_rddata_in.value = it.csr\n self.dut.pc_in.value = it.pc\n\n # Deassert valid after one cycle\n await RisingEdge(self.dut.clk)\n self.dut.valid_in.value = 0\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass AluInputMonitor(uvm_component):\n \"\"\"\n Monitor for ALU inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Act on rising edges\n await RisingEdge(self.dut.clk)\n\n # We got a valid input\n if self.dut.valid_in.value:\n # Sample control signals and operands\n a = int(self.dut.a_in.value)\n b = int(self.dut.b_in.value)\n\n # Decode operation\n op = None\n if int(self.dut.ap_add.value):\n op = \"add\"\n elif int(self.dut.ap_sub.value):\n op = \"sub\"\n elif int(self.dut.ap_land.value):\n op = \"and\"\n elif int(self.dut.ap_lor.value):\n op = \"or\"\n elif int(self.dut.ap_lxor.value):\n op = \"xor\"\n elif int(self.dut.ap_clz.value):\n op = \"clz\"\n elif int(self.dut.ap_ctz.value):\n op = \"ctz\"\n elif int(self.dut.ap_cpop.value):\n op = \"cpop\"\n elif int(self.dut.ap_sext_b.value):\n op = \"sext_b\"\n elif int(self.dut.ap_sext_h.value):\n op = \"sext_h\"\n elif int(self.dut.ap_rol.value):\n op = \"rol\"\n elif int(self.dut.ap_ror.value):\n op = \"ror\"\n elif int(self.dut.ap_bset.value):\n op = \"bset\"\n elif int(self.dut.ap_bclr.value):\n op = \"bclr\"\n elif int(self.dut.ap_binv.value):\n op = \"binv\"\n elif int(self.dut.ap_bext.value):\n op = \"bext\"\n elif int(self.dut.ap_pack.value):\n op = \"pack\"\n elif int(self.dut.ap_packh.value):\n op = \"packh\"\n elif int(self.dut.ap_sh1add.value):\n op = \"sh1add\"\n elif int(self.dut.ap_sh2add.value):\n op = \"sh2add\"\n elif int(self.dut.ap_sh3add.value):\n op = \"sh3add\"\n\n # Write item\n self.ap.write(\n AluInputItem(\n op=op,\n a=a,\n b=b,\n )\n )\n\n\nclass AluOutputMonitor(uvm_component):\n \"\"\"\n Monitor for ALU outputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Act on rising edges\n await RisingEdge(self.dut.clk)\n\n # We got a valid input\n if self.dut.valid_in.value:\n # Wait 1 cycle\n await RisingEdge(self.dut.clk)\n\n # Sample result & write the item\n result = int(self.dut.result_ff.value)\n self.ap.write(AluOutputItem(out=result))\n\n\n# ==============================================================================\n\n\nclass AluScoreboard(uvm_component):\n \"\"\"\n Generic ALU scoreboard\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self):\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n # Predict result\n result = None\n\n INT_MASK = 0xFFFFFFFF\n if item_inp.op == \"add\":\n result = (item_inp.a + item_inp.b) & INT_MASK\n elif item_inp.op == \"sub\":\n result = (item_inp.a - item_inp.b) & INT_MASK\n elif item_inp.op == \"and\":\n result = item_inp.a & item_inp.b\n elif item_inp.op == \"or\":\n result = item_inp.a | item_inp.b\n elif item_inp.op == \"xor\":\n result = item_inp.a ^ item_inp.b\n elif item_inp.op == \"clz\":\n result = next((i for i in range(32) if ((item_inp.a << i) & INT_MASK) >> 31), 32)\n elif item_inp.op == \"ctz\":\n result = next((i for i in range(32) if (item_inp.a >> i) & 1), 32)\n elif item_inp.op == \"cpop\":\n result = bin(item_inp.a).count(\"1\")\n elif item_inp.op == \"sext_b\":\n last_byte = item_inp.a & 0xFF\n sign = (item_inp.a & 0x00000080) >> 7\n result = (0xFFFFFF00 * sign) | last_byte\n elif item_inp.op == \"sext_h\":\n last_2_bytes = item_inp.a & 0xFFFF\n sign = (item_inp.a & 0x00008000) >> 15\n result = (0xFFFF0000 * sign) | last_2_bytes\n elif item_inp.op == \"rol\":\n shamt = item_inp.b & 31\n result = (item_inp.a << shamt) & INT_MASK | (item_inp.a >> ((32 - shamt) & 31))\n elif item_inp.op == \"ror\":\n shamt = item_inp.b & 31\n result = (item_inp.a >> shamt) | (item_inp.a << ((32 - shamt) & 31)) & INT_MASK\n elif item_inp.op == \"bset\":\n result = item_inp.a | (1 << (item_inp.b & 31))\n elif item_inp.op == \"bclr\":\n result = item_inp.a & ~(1 << (item_inp.b & 31))\n elif item_inp.op == \"binv\":\n result = item_inp.a ^ (1 << (item_inp.b & 31))\n elif item_inp.op == \"bext\":\n result = 1 & (item_inp.a >> (item_inp.b & 31))\n elif item_inp.op == \"pack\":\n result = (((item_inp.a << 16) & INT_MASK) >> 16) | (item_inp.b << 16) & INT_MASK\n elif item_inp.op == \"packh\":\n result = (item_inp.a & 0xFF) | ((item_inp.b & 0xFF) << 8)\n elif item_inp.op in [\"sh1add\", \"sh2add\", \"sh3add\"]:\n shift = int(item_inp.op[2])\n result = ((item_inp.a << shift) + item_inp.b) & INT_MASK\n else:\n self.logger.error(\"Unknown ALU operation '{}'\".format(item_inp.op))\n self.passed = False\n\n self.logger.debug(\n \"{} {} {} == {}\".format(\n item_inp.a,\n item_inp.op,\n item_inp.b,\n item_out.out,\n )\n )\n\n # Check result\n assert result is not None\n if item_out.out != result:\n self.logger.error(\n \"{} {} {} != {} (should be {})\".format(\n item_inp.a, item_inp.op, item_inp.b, item_out.out, result\n )\n )\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass BaseSequence(uvm_sequence):\n \"\"\"\n Base sequence of randomized 32-bit A and B operands along with operators\n picked randomly from the allowed set\n \"\"\"\n\n def __init__(self, name, ops=None):\n super().__init__(name)\n\n if ops is None:\n self.ops = [\"add\", \"sub\"]\n else:\n self.ops = ops\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n\n for i in range(count):\n a = random.randrange(-(1 << 31), 1 << 31)\n b = random.randrange(-(1 << 31), 1 << 31)\n op = random.choice(self.ops)\n\n item = AluInputItem(op, a, b)\n\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 50)\n\n # Sequencers\n self.alu_seqr = uvm_sequencer(\"alu_seqr\", self)\n\n # Driver\n self.alu_drv = AluDriver(\"alu_drv\", self, dut=cocotb.top)\n\n # Monitors\n self.inp_mon = AluInputMonitor(\"inp_mon\", self, dut=cocotb.top)\n self.out_mon = AluOutputMonitor(\"out_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = AluScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.alu_drv.seq_item_port.connect(self.alu_seqr.seq_item_export)\n\n self.inp_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.out_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Syncrhonize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n # zero input signals\n cocotb.top.scan_mode.value = 0\n cocotb.top.flush_upper_x.value = 0\n cocotb.top.flush_lower_r.value = 0\n cocotb.top.enable.value = 0\n cocotb.top.valid_in.value = 0\n cocotb.top.ap_clz.value = 0\n cocotb.top.ap_ctz.value = 0\n cocotb.top.ap_cpop.value = 0\n cocotb.top.ap_sext_b.value = 0\n cocotb.top.ap_sext_h.value = 0\n cocotb.top.ap_min.value = 0\n cocotb.top.ap_max.value = 0\n cocotb.top.ap_pack.value = 0\n cocotb.top.ap_packu.value = 0\n cocotb.top.ap_packh.value = 0\n cocotb.top.ap_rol.value = 0\n cocotb.top.ap_ror.value = 0\n cocotb.top.ap_grev.value = 0\n cocotb.top.ap_gorc.value = 0\n cocotb.top.ap_zbb.value = 0\n cocotb.top.ap_bset.value = 0\n cocotb.top.ap_bclr.value = 0\n cocotb.top.ap_binv.value = 0\n cocotb.top.ap_bext.value = 0\n cocotb.top.ap_sh1add.value = 0\n cocotb.top.ap_sh2add.value = 0\n cocotb.top.ap_sh3add.value = 0\n cocotb.top.ap_zba.value = 0\n cocotb.top.ap_land.value = 0\n cocotb.top.ap_lor.value = 0\n cocotb.top.ap_lxor.value = 0\n cocotb.top.ap_sll.value = 0\n cocotb.top.ap_srl.value = 0\n cocotb.top.ap_sra.value = 0\n cocotb.top.ap_beq.value = 0\n cocotb.top.ap_bne.value = 0\n cocotb.top.ap_blt.value = 0\n cocotb.top.ap_bge.value = 0\n cocotb.top.ap_add.value = 0\n cocotb.top.ap_sub.value = 0\n cocotb.top.ap_slt.value = 0\n cocotb.top.ap_unsignl.value = 0\n cocotb.top.ap_jall.value = 0\n cocotb.top.ap_predict_tl.value = 0\n cocotb.top.ap_predict_nt.value = 0\n cocotb.top.ap_csr_write.value = 0\n cocotb.top.ap_csr_imm.value = 0\n cocotb.top.csr_ren_in.value = 0\n cocotb.top.csr_rddata_in.value = 0\n cocotb.top.a_in.value = 0\n cocotb.top.b_in.value = 0\n cocotb.top.pc_in.value = 0\n cocotb.top.brimm_in.value = 0\n\n # perform reset\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Set common signals\n cocotb.top.enable.value = 1\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/exu_div/Makefile", "content": "\nnull :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_exu_div_ctl_wrapper\n\nVERILOG_SOURCES = \\\n $(TEST_DIR)/el2_exu_div_ctl_wrapper.sv \\\n $(SRCDIR)/exu/el2_exu_div_ctl.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/exu_div/config.vlt", "content": "`verilator_config\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_exu_div_ctl_wrapper.sv\"\n\nlint_off -rule UNUSEDPARAM -file \"*/el2_exu_div_ctl_wrapper.sv\"\n" }, { "path": "verification/block/exu_div/el2_exu_div_ctl_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro\n// SPDX-License-Identifier: Apache-2.0\nmodule el2_exu_div_ctl_wrapper\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n)\n(\n input logic clk,\n input logic rst_l,\n input logic scan_mode,\n\n // el2_div_pkt_t\n input logic dp_valid,\n input logic dp_unsign,\n input logic dp_rem,\n\n input logic [31:0] dividend,\n input logic [31:0] divisor,\n\n input logic cancel,\n\n output logic finish_dly,\n output logic [31:0] out\n);\n\n // Pack el2_div_pkt_t\n el2_div_pkt_t dp;\n assign dp.valid = dp_valid;\n assign dp.unsign = dp_unsign;\n assign dp.rem = dp_rem;\n\n // The divider\n el2_exu_div_ctl div (.*);\n\nendmodule\n" }, { "path": "verification/block/exu_div/test_div.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseSequence, BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestDiv(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"div\"])\n\n async def run(self):\n await self.seq.start(self.env.div_seqr)\n\n\n@pyuvm.test()\nclass TestRem(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"rem\"])\n\n async def run(self):\n await self.seq.start(self.env.div_seqr)\n\n\n@pyuvm.test()\nclass TestAll(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"div\", \"rem\"])\n\n async def run(self):\n await self.seq.start(self.env.div_seqr)\n" }, { "path": "verification/block/exu_div/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport math\nimport os\nimport random\nimport struct\n\nimport pyuvm\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import (\n ClockCycles,\n Event,\n FallingEdge,\n First,\n Lock,\n RisingEdge,\n Timer,\n)\nfrom pyuvm import *\n\n# ==============================================================================\n\n\nclass DivInputItem(uvm_sequence_item):\n \"\"\"\n Divider input data\n \"\"\"\n\n def __init__(self, op, num, den, unsign=1):\n super().__init__(\"DivInputItem\")\n self.op = op\n self.num = num\n self.den = den\n self.unsign = unsign\n\n\nclass DivOutputItem(uvm_sequence_item):\n \"\"\"\n Divider output data\n \"\"\"\n\n def __init__(self, out):\n super().__init__(\"DivOutputItem\")\n self.out = out\n\n\n# ==============================================================================\n\n\nclass DivDriver(uvm_driver):\n \"\"\"\n Divider module driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, DivInputItem):\n # Wait for rising edge\n await RisingEdge(self.dut.clk)\n self.dut.dp_valid.value = 1\n self.dut.dp_unsign.value = it.unsign\n self.dut.dp_rem.value = it.op == \"rem\"\n self.dut.dividend.value = it.num\n self.dut.divisor.value = it.den\n\n # Deassert valid, wait for finish\n for i in range(100):\n await RisingEdge(self.dut.clk)\n self.dut.dp_valid.value = 0\n\n if self.dut.finish_dly.value:\n break\n else:\n raise RuntimeError(\"Timeout\")\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass DivInputMonitor(uvm_component):\n \"\"\"\n Monitor for divider inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Act on rising edges\n await RisingEdge(self.dut.clk)\n\n # We got a valid input\n if self.dut.dp_valid.value:\n # Sample control signals and operands\n num = int(self.dut.dividend.value)\n den = int(self.dut.divisor.value)\n unsign = int(self.dut.dp_unsign.value)\n\n # Decode operation\n op = \"rem\" if self.dut.dp_rem.value else \"div\"\n\n # Write item\n self.ap.write(DivInputItem(op=op, num=num, den=den, unsign=unsign))\n\n\nclass DivOutputMonitor(uvm_component):\n \"\"\"\n Monitor for divider outputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Act on rising edges\n await RisingEdge(self.dut.clk)\n\n # We got a valid output\n if self.dut.finish_dly.value:\n # Sample result & write the item\n result = int(self.dut.out.value)\n self.ap.write(DivOutputItem(out=result))\n\n\n# ==============================================================================\n\n\nclass DivScoreboard(uvm_component):\n \"\"\"\n Divider scoreboard\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self):\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n # Predict the result\n div = item_inp.num // item_inp.den\n rem = item_inp.num - (div * item_inp.den)\n\n self.logger.debug(\n \"{} {} {} == {}\".format(\n item_inp.num,\n item_inp.op,\n item_inp.den,\n item_out.out,\n )\n )\n\n # Check\n if (item_inp.op == \"div\" and item_out.out != div) or (\n item_inp.op == \"rem\" and item_out.out != rem\n ):\n result = div if item_inp.op == \"div\" else rem\n\n self.logger.error(\n \"{} {} {} != {} ({})\".format(\n item_inp.num, item_inp.op, item_inp.den, result, item_out.out\n )\n )\n\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass BaseSequence(uvm_sequence):\n \"\"\"\n Base sequence of randomized 32-bit A and B operands along with operators\n picked randomly from the allowed set\n \"\"\"\n\n def __init__(self, name, ops=None):\n super().__init__(name)\n\n if ops is None:\n self.ops = [\"div\", \"rem\"]\n else:\n self.ops = ops\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n\n for i in range(count):\n num = random.randrange(1, 1 << 32)\n den = random.randrange(1, 1 << 16) # Make dividends from smaller range\n op = random.choice(self.ops)\n\n item = DivInputItem(op, num, den)\n\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 50)\n\n # Sequencers\n self.div_seqr = uvm_sequencer(\"div_seqr\", self)\n\n # Driver\n self.div_drv = DivDriver(\"div_drv\", self, dut=cocotb.top)\n\n # Monitors\n self.inp_mon = DivInputMonitor(\"inp_mon\", self, dut=cocotb.top)\n self.out_mon = DivOutputMonitor(\"out_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = DivScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.div_drv.seq_item_port.connect(self.div_seqr.seq_item_export)\n\n self.inp_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.out_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Syncrhonize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n\n cocotb.top.scan_mode.value = 0\n cocotb.top.dp_valid.value = 0\n cocotb.top.dp_unsign.value = 0\n cocotb.top.dp_rem.value = 0\n cocotb.top.dividend.value = 0\n cocotb.top.divisor.value = 0\n cocotb.top.cancel.value = 0\n\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/exu_mul/Makefile", "content": "\nnull :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_exu_mul_ctl_wrapper\nCM_FILE = cm.cfg\n\nVERILOG_SOURCES = \\\n $(TEST_DIR)/el2_exu_mul_ctl_wrapper.sv \\\n $(SRCDIR)/exu/el2_exu_mul_ctl.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/exu_mul/cm.cfg", "content": "+tree el2_exu_mul_ctl_wrapper.mul\n\n-node el2_exu_mul_ctl_wrapper.mul.crc32_poly_rev // Tied to 32'hEDB88320\n-node el2_exu_mul_ctl_wrapper.mul.crc32c_poly_rev // Tied to 32'h82F63B78\n" }, { "path": "verification/block/exu_mul/config.vlt", "content": "`verilator_config\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_exu_mul_ctl_wrapper.sv\"\n\nlint_off -rule UNUSEDPARAM -file \"*/el2_exu_mul_ctl_wrapper.sv\"\n" }, { "path": "verification/block/exu_mul/el2_exu_mul_ctl_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro\n// SPDX-License-Identifier: Apache-2.0\nmodule el2_exu_mul_ctl_wrapper\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n)\n(\n input logic clk,\n input logic rst_l,\n input logic scan_mode,\n\n // Unpacked mul_p\n input logic mul_p_valid,\n input logic mul_p_rs1_sign,\n input logic mul_p_rs2_sign,\n input logic mul_p_low,\n input logic mul_p_bcompress,\n input logic mul_p_bdecompress,\n input logic mul_p_clmul,\n input logic mul_p_clmulh,\n input logic mul_p_clmulr,\n input logic mul_p_grev,\n input logic mul_p_gorc,\n input logic mul_p_shfl,\n input logic mul_p_unshfl,\n input logic mul_p_crc32_b,\n input logic mul_p_crc32_h,\n input logic mul_p_crc32_w,\n input logic mul_p_crc32c_b,\n input logic mul_p_crc32c_h,\n input logic mul_p_crc32c_w,\n input logic mul_p_bfp,\n input logic mul_p_xperm_n,\n input logic mul_p_xperm_b,\n input logic mul_p_xperm_h,\n\n input logic [31:0] rs1_in,\n input logic [31:0] rs2_in,\n\n output logic [31:0] result_x\n);\n\n // Pack mul_p\n el2_mul_pkt_t mul_p;\n assign mul_p.valid = mul_p_valid;\n assign mul_p.rs1_sign = mul_p_rs1_sign;\n assign mul_p.rs2_sign = mul_p_rs2_sign;\n assign mul_p.low = mul_p_low;\n assign mul_p.bcompress = mul_p_bcompress;\n assign mul_p.bdecompress = mul_p_bdecompress;\n assign mul_p.clmul = mul_p_clmul;\n assign mul_p.clmulh = mul_p_clmulh;\n assign mul_p.clmulr = mul_p_clmulr;\n assign mul_p.grev = mul_p_grev;\n assign mul_p.gorc = mul_p_gorc;\n assign mul_p.shfl = mul_p_shfl;\n assign mul_p.unshfl = mul_p_unshfl;\n assign mul_p.crc32_b = mul_p_crc32_b;\n assign mul_p.crc32_h = mul_p_crc32_h;\n assign mul_p.crc32_w = mul_p_crc32_w;\n assign mul_p.crc32c_b = mul_p_crc32c_b;\n assign mul_p.crc32c_h = mul_p_crc32c_h;\n assign mul_p.crc32c_w = mul_p_crc32c_w;\n assign mul_p.bfp = mul_p_bfp;\n assign mul_p.xperm_n = mul_p_xperm_n;\n assign mul_p.xperm_b = mul_p_xperm_b;\n assign mul_p.xperm_h = mul_p_xperm_h;\n\n // The multiplier\n el2_exu_mul_ctl mul (.*);\n\nendmodule\n" }, { "path": "verification/block/exu_mul/test_mul.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseSequence, BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestMul(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BaseSequence(\"stimulus\", [\"mul\"])\n\n async def run(self):\n await self.seq.start(self.env.mul_seqr)\n" }, { "path": "verification/block/exu_mul/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport math\nimport os\nimport random\nimport struct\n\nimport pyuvm\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import (\n ClockCycles,\n Event,\n FallingEdge,\n First,\n Lock,\n RisingEdge,\n Timer,\n)\nfrom pyuvm import *\n\n# ==============================================================================\n\n\nclass MulInputItem(uvm_sequence_item):\n \"\"\"\n Multipiler input data\n \"\"\"\n\n def __init__(self, op, a, b, low=0):\n super().__init__(\"MulInputItem\")\n self.op = op\n self.a = a\n self.b = b\n self.low = low\n\n\nclass MulOutputItem(uvm_sequence_item):\n \"\"\"\n Multiplier output data\n \"\"\"\n\n def __init__(self, out):\n super().__init__(\"MulOutputItem\")\n self.out = out\n\n\n# ==============================================================================\n\n\nclass MulDriver(uvm_driver):\n \"\"\"\n Multiplier input driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, MulInputItem):\n # Wait for rising edge\n await RisingEdge(self.dut.clk)\n self.dut.mul_p_valid.value = 1\n\n # Operands\n self.dut.rs1_in.value = abs(it.a)\n self.dut.rs2_in.value = abs(it.b)\n self.dut.mul_p_rs1_sign.value = 0 # For now assume positive\n self.dut.mul_p_rs2_sign.value = 0\n\n # Control\n self.dut.mul_p_low.value = it.low\n\n # Deassert valid after one cycle\n await RisingEdge(self.dut.clk)\n self.dut.mul_p_valid.value = 0\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass MulInputMonitor(uvm_component):\n \"\"\"\n Monitor for Multiplier inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Act on rising edges\n await RisingEdge(self.dut.clk)\n\n # We got a valid input\n if self.dut.mul_p_valid.value:\n # Sample control signals and operands\n a = int(self.dut.rs1_in.value)\n b = int(self.dut.rs2_in.value)\n low = int(self.dut.mul_p_low.value)\n\n # Decode operation\n op = None\n\n # Write item\n self.ap.write(\n MulInputItem(\n op=op,\n a=a,\n b=b,\n low=low,\n )\n )\n\n\nclass MulOutputMonitor(uvm_component):\n \"\"\"\n Monitor for multiplier outputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Act on rising edges\n await RisingEdge(self.dut.clk)\n\n # We got a valid input\n if self.dut.mul_p_valid.value:\n # Wait 1 cycle\n await RisingEdge(self.dut.clk)\n\n # Sample result & write the item\n result = int(self.dut.result_x.value)\n self.ap.write(MulOutputItem(out=result))\n\n\n# ==============================================================================\n\n\nclass MulScoreboard(uvm_component):\n \"\"\"\n Generic ALU scoreboard\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self):\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n # Predict the result\n res = item_inp.a * item_inp.b\n if not item_inp.low:\n res >>= 32\n res &= 0xFFFFFFFF\n\n self.logger.debug(\n \"{} * {} ({}) == {}\".format(\n item_inp.a,\n item_inp.b,\n \"lo\" if item_inp.low else \"hi\",\n item_out.out,\n )\n )\n\n if item_out.out != res:\n self.logger.error(\n \"{} * {} ({}) != {} (should be {})\".format(\n item_inp.a, item_inp.b, \"lo\" if item_inp.low else \"hi\", item_out.out, res\n )\n )\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass BaseSequence(uvm_sequence):\n \"\"\"\n Base sequence of randomized 32-bit A and B operands along with operators\n picked randomly from the allowed set\n \"\"\"\n\n def __init__(self, name, ops=None):\n super().__init__(name)\n\n if ops is None:\n self.ops = [\"mul\"]\n else:\n self.ops = ops\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n\n for i in range(count):\n a = random.randrange(1, 1 << 32)\n b = random.randrange(1, 1 << 32)\n op = random.choice(self.ops)\n\n if op == \"mul\":\n low = random.choice([0, 1])\n\n item = MulInputItem(op, a, b, low=low)\n\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 50)\n\n # Sequencers\n self.mul_seqr = uvm_sequencer(\"mul_seqr\", self)\n\n # Driver\n self.mul_drv = MulDriver(\"mul_drv\", self, dut=cocotb.top)\n\n # Monitors\n self.inp_mon = MulInputMonitor(\"inp_mon\", self, dut=cocotb.top)\n self.out_mon = MulOutputMonitor(\"out_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = MulScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.mul_drv.seq_item_port.connect(self.mul_seqr.seq_item_export)\n\n self.inp_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.out_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Syncrhonize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n\n # zero input signals\n cocotb.top.scan_mode.value = 0\n cocotb.top.mul_p_valid.value = 0\n cocotb.top.mul_p_rs1_sign.value = 0\n cocotb.top.mul_p_rs2_sign.value = 0\n cocotb.top.mul_p_low.value = 0\n cocotb.top.mul_p_bcompress.value = 0\n cocotb.top.mul_p_bdecompress.value = 0\n cocotb.top.mul_p_clmul.value = 0\n cocotb.top.mul_p_clmulh.value = 0\n cocotb.top.mul_p_clmulr.value = 0\n cocotb.top.mul_p_grev.value = 0\n cocotb.top.mul_p_gorc.value = 0\n cocotb.top.mul_p_shfl.value = 0\n cocotb.top.mul_p_unshfl.value = 0\n cocotb.top.mul_p_crc32_b.value = 0\n cocotb.top.mul_p_crc32_h.value = 0\n cocotb.top.mul_p_crc32_w.value = 0\n cocotb.top.mul_p_crc32c_b.value = 0\n cocotb.top.mul_p_crc32c_h.value = 0\n cocotb.top.mul_p_crc32c_w.value = 0\n cocotb.top.mul_p_bfp.value = 0\n cocotb.top.mul_p_xperm_n.value = 0\n cocotb.top.mul_p_xperm_b.value = 0\n cocotb.top.mul_p_xperm_h.value = 0\n cocotb.top.rs1_in.value = 0\n cocotb.top.rs2_in.value = 0\n\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/iccm/Makefile", "content": "\nnull :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_ifu_iccm_mem_wrapper\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/lib/el2_mem_if.sv \\\n $(TEST_DIR)/el2_ifu_iccm_mem_wrapper.sv \\\n $(SRCDIR)/ifu/el2_ifu_iccm_mem.sv \\\n $(SRCDIR)/lib/mem_lib.sv\n\n# Undefine the VERILATOR macro to make the code use actual RAM cells instead\n# of simulation models\nEXTRA_ARGS += -UVERILATOR\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/iccm/config.vlt", "content": "`verilator_config\n\nlint_off -rule PINCONNECTEMPTY -file \"*/el2_ifu_iccm_mem_wrapper.sv\"\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_ifu_iccm_mem_wrapper.sv\"\n\nlint_off -rule IMPORTSTAR -file \"*/el2_mem_if.sv\"\n" }, { "path": "verification/block/iccm/el2_ifu_iccm_mem_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro \n// SPDX-License-Identifier: Apache-2.0\n\nmodule el2_ifu_iccm_mem_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n input logic clk,\n input logic active_clk,\n input logic rst_l,\n input logic clk_override,\n\n input logic iccm_wren,\n input logic iccm_rden,\n input logic [pt.ICCM_BITS-1:1] iccm_rw_addr,\n input logic iccm_buf_correct_ecc,\n input logic iccm_correction_state,\n input logic [2:0] iccm_wr_size,\n input logic [77:0] iccm_wr_data,\n\n // Unwrapped iccm_ext_in_pkt\n input logic iccm_ext_in_pkt_TEST1,\n input logic iccm_ext_in_pkt_RME,\n input logic [3:0] iccm_ext_in_pkt_RM,\n input logic iccm_ext_in_pkt_LS,\n input logic iccm_ext_in_pkt_DS,\n input logic iccm_ext_in_pkt_SD,\n input logic iccm_ext_in_pkt_TEST_RNM,\n input logic iccm_ext_in_pkt_BC1,\n input logic iccm_ext_in_pkt_BC2,\n\n output logic [63:0] iccm_rd_data,\n output logic [77:0] iccm_rd_data_ecc,\n input logic scan_mode\n);\n\n logic [pt.ICCM_NUM_BANKS-1:0] iccm_clken;\n logic [pt.ICCM_NUM_BANKS-1:0] iccm_wren_bank;\n logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;\n logic [pt.ICCM_NUM_BANKS-1:0][ 31:0] iccm_bank_wr_data;\n logic [pt.ICCM_NUM_BANKS-1:0][ pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc;\n logic [pt.ICCM_NUM_BANKS-1:0][ 31:0] iccm_bank_dout;\n logic [pt.ICCM_NUM_BANKS-1:0][ pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc;\n\n logic [pt.ICCM_NUM_BANKS-1:0][ 38:0] iccm_bank_wr_fdata;\n logic [pt.ICCM_NUM_BANKS-1:0][ 38:0] iccm_bank_fdout;\n\n el2_mem_if mem_export ();\n assign iccm_clken = mem_export.iccm_clken;\n assign iccm_wren_bank = mem_export.iccm_wren_bank;\n assign iccm_addr_bank = mem_export.iccm_addr_bank;\n assign iccm_bank_wr_data = mem_export.iccm_bank_wr_data;\n assign iccm_bank_wr_ecc = mem_export.iccm_bank_wr_ecc;\n\n // Pack el2_ccm_ext_in_pkt_t\n el2_ccm_ext_in_pkt_t [pt.ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt;\n\n for (genvar i = 0; i < pt.ICCM_NUM_BANKS; i++) begin : gen_iccm_ext_pkt\n assign iccm_ext_in_pkt[i].TEST1 = iccm_ext_in_pkt_TEST1;\n assign iccm_ext_in_pkt[i].RME = iccm_ext_in_pkt_RME;\n assign iccm_ext_in_pkt[i].RM = iccm_ext_in_pkt_RM;\n assign iccm_ext_in_pkt[i].LS = iccm_ext_in_pkt_LS;\n assign iccm_ext_in_pkt[i].DS = iccm_ext_in_pkt_DS;\n assign iccm_ext_in_pkt[i].SD = iccm_ext_in_pkt_SD;\n assign iccm_ext_in_pkt[i].TEST_RNM = iccm_ext_in_pkt_TEST_RNM;\n assign iccm_ext_in_pkt[i].BC1 = iccm_ext_in_pkt_BC1;\n assign iccm_ext_in_pkt[i].BC2 = iccm_ext_in_pkt_BC2;\n end : gen_iccm_ext_pkt\n\n // The ICCM module\n for (genvar i = 0; i < pt.ICCM_NUM_BANKS; i++) begin : gen_iccm_mem\n assign iccm_bank_wr_fdata[i] = {\n mem_export.iccm_bank_wr_ecc[i], mem_export.iccm_bank_wr_data[i]\n };\n assign mem_export.iccm_bank_dout[i] = iccm_bank_fdout[i][31:0];\n assign mem_export.iccm_bank_ecc[i] = iccm_bank_fdout[i][32+pt.ICCM_ECC_WIDTH-1:32];\n\n el2_ram #(\n .depth(1 << pt.ICCM_INDEX_BITS),\n .width(39)\n ) iccm_bank (\n // Primary ports\n .ME(iccm_clken[i]),\n .CLK(clk),\n .WE(iccm_wren_bank[i]),\n .ADR(iccm_addr_bank[i]),\n .D(iccm_bank_wr_fdata[i][38:0]),\n .Q(iccm_bank_fdout[i][38:0]),\n .ROP(),\n // These are used by SoC\n .TEST1(iccm_ext_in_pkt[i].TEST1),\n .RME(iccm_ext_in_pkt[i].RME),\n .RM(iccm_ext_in_pkt[i].RM),\n .LS(iccm_ext_in_pkt[i].LS),\n .DS(iccm_ext_in_pkt[i].DS),\n .SD(iccm_ext_in_pkt[i].SD),\n .TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),\n .BC1(iccm_ext_in_pkt[i].BC1),\n .BC2(iccm_ext_in_pkt[i].BC2)\n );\n end : gen_iccm_mem\n\n el2_ifu_iccm_mem mem (\n .iccm_mem_export(mem_export.veer_iccm),\n .*\n );\n\nendmodule\n" }, { "path": "verification/block/iccm/test_readwrite.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom pyuvm import *\nfrom testbench import BaseTest, MemReadItem, MemWriteItem\n\n# =============================================================================\n\n\nclass ReadWriteSequence(uvm_sequence):\n \"\"\"\n A sequencer that issues a random sequence of writes followed by a\n randomized sequence of reads containing the same addresses previously\n written to.\n \"\"\"\n\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n burst = ConfigDB().get(None, \"\", \"TEST_BURST_LEN\")\n\n awidth = (\n ConfigDB().get(None, \"\", \"ICCM_BITS\") - 1\n ) # Address input declared as [pt.ICCM_BITS-1:1]\n dwidth = 64 # Fixed\n\n for i in range(count):\n # Randomize unique addresses (aligned to 8)\n addrs = set([random.randrange(0, 1 << awidth) & ~7 for i in range(burst)])\n\n # Issue writes, randomize data\n for addr in addrs:\n data = random.randrange(0, 1 << dwidth)\n\n item = MemWriteItem(addr, data)\n await self.start_item(item)\n await self.finish_item(item)\n\n # Issue random reads for written addresses\n addrs = list(set(addrs))\n random.shuffle(addrs)\n for addr in addrs:\n item = MemReadItem(addr, data)\n await self.start_item(item)\n await self.finish_item(item)\n\n\n@pyuvm.test()\nclass TestReadWrite(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = ReadWriteSequence(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.mem_seqr)\n" }, { "path": "verification/block/iccm/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport os\n\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, FallingEdge, RisingEdge\nfrom pyuvm import *\n\n# ==============================================================================\n\n\nclass MemWriteItem(uvm_sequence_item):\n \"\"\"\n Memory write item\n \"\"\"\n\n def __init__(self, addr, data):\n super().__init__(\"MemWriteItem\")\n self.addr = addr\n self.data = data\n\n\nclass MemReadItem(uvm_sequence_item):\n \"\"\"\n Memory read item\n \"\"\"\n\n def __init__(self, addr, data=None):\n super().__init__(\"MemReadItem\")\n self.addr = addr\n self.data = data\n\n\n# ==============================================================================\n\n\nclass MemDriver(uvm_driver):\n \"\"\"\n Memory interface driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n # Write\n if isinstance(it, MemWriteItem):\n # Wait for rising edge, do the write\n await RisingEdge(self.dut.clk)\n self.dut.iccm_wren.value = 1\n\n self.dut.iccm_rw_addr.value = it.addr\n self.dut.iccm_wr_data.value = it.data\n self.dut.iccm_wr_size.value = 7 # FIXME: Fixed 64-bit writes for now\n\n # Wait for rising edge, deassert write\n await RisingEdge(self.dut.clk)\n self.dut.iccm_wren.value = 0\n\n # Read\n elif isinstance(it, MemReadItem):\n # Wait for rising edge, do the read\n await RisingEdge(self.dut.clk)\n self.dut.iccm_rden.value = 1\n\n self.dut.iccm_rw_addr.value = it.addr\n\n # Wait for rising edge, deassert read\n await RisingEdge(self.dut.clk)\n self.dut.iccm_rden.value = 0\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass MemMonitor(uvm_component):\n \"\"\"\n Memory interface monitor\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Act on rising edges\n await RisingEdge(self.dut.clk)\n\n # Since the driver drives both lo and hi with the same values\n # here we sample only lo\n\n # Write\n if self.dut.iccm_wren.value:\n addr = int(self.dut.iccm_rw_addr)\n data = int(self.dut.iccm_wr_data)\n self.ap.write(MemWriteItem(addr, data))\n\n # Read\n if self.dut.iccm_rden.value:\n addr = int(self.dut.iccm_rw_addr)\n\n # Wait additional clock cycle\n await RisingEdge(self.dut.clk)\n\n # FIXME: For now read just raw data, not the ECC-corrected part\n data = int(self.dut.iccm_rd_data_ecc)\n self.ap.write(MemReadItem(addr, data))\n\n\n# ==============================================================================\n\n\nclass Scoreboard(uvm_component):\n \"\"\"\n A scoreboard that tracks memory writes and compares them agains data read\n from the memory. It also checks if both reads and writes took place\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n self.passed = None\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n did_write = False\n did_read = False\n mem_content = dict()\n\n # Process items\n while self.port.can_get():\n # Get an item\n got_item, item = self.port.try_get()\n assert got_item\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # Memory write\n if isinstance(item, MemWriteItem):\n mem_content[item.addr] = item.data\n did_write = True\n\n self.logger.debug(\"[0x{:08X}] <= 0x{:08X}\".format(item.addr, item.data))\n\n # Memory read\n elif isinstance(item, MemReadItem):\n data = mem_content.get(item.addr, None)\n did_read = True\n\n self.logger.debug(\n \"[0x{:08X}] == 0x{:08X} vs. 0x{:08X} {}\".format(\n item.addr, item.data, data, item.data == data\n )\n )\n\n if data != item.data:\n self.logger.error(\n \"Data mismatch, mem[0x{:08X}] is 0x{:08X}, should be 0x{:08X}\".format(\n item.addr, item.data, data\n )\n )\n self.passed = False\n\n # There were no writes\n if not did_write:\n self.logger.error(\"There were no writes\")\n self.passed = False\n\n # There were no reads\n if not did_read:\n self.logger.error(\"There were no reads\")\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 50)\n ConfigDB().set(None, \"*\", \"TEST_BURST_LEN\", 10)\n\n ConfigDB().set(None, \"*\", \"ICCM_BITS\", 0x10)\n\n # Sequencers\n self.mem_seqr = uvm_sequencer(\"mem_seqr\", self)\n\n # Driver\n self.mem_drv = MemDriver(\"mem_drv\", self, dut=cocotb.top)\n\n # Monitor\n self.mem_mon = MemMonitor(\"mem_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.mem_drv.seq_item_port.connect(self.mem_seqr.seq_item_export)\n self.mem_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n\n cocotb.top.active_clk.value = 0\n cocotb.top.clk_override.value = 0\n cocotb.top.iccm_wren.value = 0\n cocotb.top.iccm_rden.value = 0\n cocotb.top.iccm_rw_addr.value = 0\n cocotb.top.iccm_buf_correct_ecc.value = 0\n cocotb.top.iccm_correction_state.value = 0\n cocotb.top.iccm_wr_size.value = 0\n cocotb.top.iccm_wr_data.value = 0\n cocotb.top.iccm_ext_in_pkt_TEST1.value = 0\n cocotb.top.iccm_ext_in_pkt_RME.value = 0\n cocotb.top.iccm_ext_in_pkt_RM.value = 0\n cocotb.top.iccm_ext_in_pkt_LS.value = 0\n cocotb.top.iccm_ext_in_pkt_DS.value = 0\n cocotb.top.iccm_ext_in_pkt_SD.value = 0\n cocotb.top.iccm_ext_in_pkt_TEST_RNM.value = 0\n cocotb.top.iccm_ext_in_pkt_BC1.value = 0\n cocotb.top.iccm_ext_in_pkt_BC2.value = 0\n cocotb.top.scan_mode.value = 0\n\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n self.start_clock(\"active_clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Set constant value signals\n cocotb.top.iccm_buf_correct_ecc.value = 0\n cocotb.top.iccm_correction_state.value = 0\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/ifu_compress/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_ifu_compress_ctl\nCM_FILE = cm.cfg\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/ifu/el2_ifu_compress_ctl.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/ifu_compress/cm.cfg", "content": "+tree *\n\n// Tied to '0\n-node el2_ifu_compress_ctl.o[31]\n-node el2_ifu_compress_ctl.o[29:21]\n-node el2_ifu_compress_ctl.o[19:15]\n-node el2_ifu_compress_ctl.o[11:7]\n\n-node el2_ifu_compress_ctl.o[1:0] // Tied to 2'b11\n-node el2_ifu_compress_ctl.l1[1:0] // Tied to o[1:0] (2'b11)\n-node el2_ifu_compress_ctl.l2[1:0] // Tied to l1[1:0] (2'b11)\n-node el2_ifu_compress_ctl.l3[1:0] // Tied to l2[1:0] (2'b11)\n\n-node el2_ifu_compress_ctl.l1[31] // Tied to o[31] ('0)\n-node el2_ifu_compress_ctl.l1[29:25] // Tied to o[29:25] ('0)\n\n-node el2_ifu_compress_ctl.rdpd[4:3] // Tied to 2'01\n-node el2_ifu_compress_ctl.rs2pd[4:3] // Tied to 2'01\n" }, { "path": "verification/block/ifu_compress/test_compress.py", "content": "import pyuvm\nfrom pyuvm import *\nfrom testbench import BaseEnv, BaseTest, CompressedSequence\n\n\n@pyuvm.test()\nclass TestDecompressor(BaseTest):\n \"\"\"\n Decompression test\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, BaseEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = CompressedSequence.create(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.dcm_seqr)\n" }, { "path": "verification/block/ifu_compress/testbench.py", "content": "import os\nimport random\nimport subprocess\nimport textwrap\nfrom queue import Queue\n\nimport pyuvm\nfrom cocotb.binary import BinaryValue\nfrom cocotb.triggers import Timer\nfrom pyuvm import *\n\n\ndef collect_signals(signals, uut, obj, uut_prefix=\"\", obj_prefix=\"\"):\n \"\"\"\n Collects signal objects from UUT and attaches them to the given object.\n Optionally UUT signals can be prefixed with the uut_prefix and object\n signals with the obj_prefix\n \"\"\"\n\n for sig in signals:\n uut_sig = uut_prefix + sig\n obj_sig = obj_prefix + sig\n if hasattr(uut, uut_sig):\n s = getattr(uut, uut_sig)\n\n else:\n s = None\n logging.error(\"Module {} does not have a signal '{}'\".format(str(uut), sig))\n\n setattr(obj, obj_sig, s)\n\n\ndef get_opcode(asm_line, ext=\"rv32i\", size=32):\n \"\"\"\n Generates binary opcode string based on a line of assembly\n \"\"\"\n\n cmd = f\"echo '{asm_line}' | riscv64-unknown-elf-as -march={ext} -o /dev/null -al | tail -n 1\"\n\n # Take instruction hex (3rd column) and change its endianess\n out = subprocess.check_output([cmd], shell=True).decode().split()[2]\n out = \"\".join(textwrap.wrap(out, 2)[::-1])\n\n assert len(out) == size // 4, f\"instruction '{asm_line}' assembled to unexpected width\"\n\n # Convert hex to bin\n opcode = f\"{int(out, 16):0{size}b}\"\n\n return opcode\n\n\ndef generate_assembly_pair():\n \"\"\"\n Generates random assembly instruction that can be compressed\n \"\"\"\n\n # For most compressed instructions only x8--x15 are allowed\n dreg = random.randrange(8, 16)\n sreg = random.randrange(8, 16)\n\n imm = random.randrange(2**11)\n sgn = random.choice([\"-\", \"\"])\n\n # In f-strings below:\n # {imm%width} -- when the immediate's magnitude has a limited width\n # {imm or 1} -- when the immediate cannot be 0\n # {sgn}{imm} -- when the immediate is signed\n return random.choice(\n [\n (f\"c.add x{dreg}, x{sreg}\", f\"add x{dreg}, x{dreg}, x{sreg}\"),\n (f\"c.or x{dreg}, x{sreg}\", f\"or x{dreg}, x{dreg}, x{sreg}\"),\n (f\"c.xor x{dreg}, x{sreg}\", f\"xor x{dreg}, x{dreg}, x{sreg}\"),\n (f\"c.sub x{dreg}, x{sreg}\", f\"sub x{dreg}, x{dreg}, x{sreg}\"),\n (f\"c.mv x{dreg}, x{sreg}\", f\"add x{dreg}, x0, x{sreg}\"),\n (f\"c.andi x{dreg}, {sgn}{imm % 5}\", f\"andi x{dreg}, x{dreg}, {sgn}{imm % 5}\"),\n (f\"c.addi x{dreg}, {sgn}{imm % 5}\", f\"addi x{dreg}, x{dreg}, {sgn}{imm % 5}\"),\n (f\"c.srli x{dreg}, {imm % 5 or 1}\", f\"srli x{dreg}, x{dreg}, {imm % 5 or 1}\"),\n (f\"c.srai x{dreg}, {imm % 5 or 1}\", f\"srai x{dreg}, x{dreg}, {imm % 5 or 1}\"),\n (f\"c.slli x{dreg}, {imm % 5 or 1}\", f\"slli x{dreg}, x{dreg}, {imm % 5 or 1}\"),\n (\"c.ebreak\", \"ebreak\"),\n ]\n )\n\n\nclass CompressedGenerator:\n \"\"\"\n Generates compressed instructions and caches their expected\n decompressed counterpart to allow fast checks\n \"\"\"\n\n lookup = {}\n\n @classmethod\n def get(self):\n \"\"\"\n Generates compressed/decompressed instruction pair\n \"\"\"\n\n asm_com, asm_dec = generate_assembly_pair()\n\n com = get_opcode(asm_com, ext=\"rv32ic\", size=16)\n dec = get_opcode(asm_dec, ext=\"rv32i\", size=32)\n\n self.lookup[com] = dec\n\n return com\n\n @classmethod\n def check(self, com, dec):\n \"\"\"\n Checks if a previously generated instruction corresponds to the\n decompressed one given\n \"\"\"\n\n assert com in self.lookup, f\"instruction 0b{com} not generated before\"\n return self.lookup[com] == dec\n\n\nclass InstructionPairItem(uvm_sequence_item):\n \"\"\"\n A generic instruction-input stimulus\n \"\"\"\n\n def __init__(self, din, dout):\n super().__init__(\"InstructionItem\")\n \"\"\"\n Records a state of decompressor's pins\n \"\"\"\n\n self.din = din\n self.dout = dout\n\n\nclass CompressedInstructionItem(uvm_sequence_item):\n \"\"\"\n A generic compressed instruction-input stimulus\n \"\"\"\n\n def __init__(self):\n super().__init__(\"CompressedInstructionItem\")\n \"\"\"\n Creates a 16-bit instruction\n \"\"\"\n\n instr = CompressedGenerator.get()\n self.instr = BinaryValue(value=instr, bigEndian=False)\n\n\nclass CompressedSequence(uvm_sequence):\n \"\"\"\n A sequencer that generates random RISC-V compressed instructions\n \"\"\"\n\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n\n for j in range(count):\n # Create a compressed instruction\n item = CompressedInstructionItem()\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass DecompressorDriver(uvm_driver):\n \"\"\"\n A driver for the IFU instruction decompressor\n \"\"\"\n\n SIGNALS = [\"din\", \"dout\"]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n super().__init__(*args, **kwargs)\n\n # Collect signals\n collect_signals(self.SIGNALS, uut, self)\n\n async def write(self, instr):\n \"\"\"\n Pushes instruction to the decompressor\n \"\"\"\n\n self.din.value = instr\n await Timer(10, \"us\")\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n if isinstance(it, CompressedInstructionItem):\n await self.write(it.instr)\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n self.seq_item_port.item_done()\n\n\nclass DecompressorMonitor(uvm_component):\n \"\"\"\n A monitor for the IFU instruction decompressor\n \"\"\"\n\n SIGNALS = [\"din\", \"dout\"]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n await Timer(10, \"us\")\n it = InstructionPairItem(self.din, self.dout)\n self.ap.write(it)\n\n\nclass Scoreboard(uvm_component):\n \"\"\"\n Checks if all decompressed instructions have the expected value\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n # Process items\n while self.port.can_get():\n # Get an item\n got_item, item = self.port.try_get()\n assert got_item\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # Got a decompressed instruction which is incorrect\n if isinstance(item, InstructionPairItem):\n if not CompressedGenerator.check(str(item.din.value), str(item.dout.value)):\n self.logger.debug(\n \"Instruction decompressed incorrectly: 0b{} -> 0b{}\".format(\n item.din, item.dout\n )\n )\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 500)\n\n # Sequencers\n self.dcm_seqr = uvm_sequencer(\"dcm_seqr\", self)\n\n # Driver\n self.dcm_drv = DecompressorDriver(\"dcm_drv\", self, uut=cocotb.top)\n\n # Monitor\n self.dcm_mon = DecompressorMonitor(\"dcm_mon\", self, uut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.dcm_drv.seq_item_port.connect(self.dcm_seqr.seq_item_export)\n self.dcm_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n async def run_phase(self):\n self.raise_objection()\n await self.run()\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/ifu_mem_ctl/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_ifu_mem_ctl_wrapper\nCM_FILE = cm.cfg\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/ifu/el2_ifu_mem_ctl.sv \\\n $(TEST_DIR)/el2_ifu_mem_ctl_wrapper.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/ifu_mem_ctl/cm.cfg", "content": "+tree el2_ifu_mem_ctl_wrapper.ifu_mem_ctl\n\n// Tied to '0\n-node el2_ifu_mem_ctl_wrapper.ifu_mem_ctl.ifu_axi_araddr[2:0]" }, { "path": "verification/block/ifu_mem_ctl/common.py", "content": "import random\n\nimport cocotb\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, FallingEdge, RisingEdge\n\nICCM_BASE = 0xEE000000\nICCM_SIZE = 0x10000\n\n\nclass Axi4LiteBFM:\n def __init__(self, dut):\n self.dut = dut\n\n async def _wait(self, signal, max_cycles=200):\n \"\"\"\n Waits for a signal to be asserted in at most max_cycles.\n Raises an exception if it does not\n \"\"\"\n for _ in range(max_cycles):\n await RisingEdge(self.dut.clk)\n if signal.value != 0:\n break\n else:\n raise RuntimeError(\"{} timeout\".format(signal._name))\n\n async def read_handler(self):\n while True:\n if not self.dut.rst_l.value:\n await RisingEdge(self.dut.rst_l)\n\n self.dut.ifu_axi_arready.value = 1\n await self._wait(self.dut.ifu_axi_arvalid)\n self.dut.ifu_axi_arready.value = 0\n\n self.dut.ifu_axi_rvalid.value = 1\n self.dut.ifu_axi_rdata.value = rand_iccm_data()\n self.dut.ifu_axi_rresp.value = 0\n\n await RisingEdge(self.dut.clk)\n\n self.dut.ifu_axi_rvalid.value = 0\n self.dut.ifu_axi_rdata.value = 0\n self.dut.ifu_axi_rresp.value = 0\n\n\nasync def reset(dut):\n # Apply reset (active-low)\n dut.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n dut.rst_l.value = 1\n await ClockCycles(cocotb.top.clk, 2)\n\n cocotb.top.ifu_bus_clk_en.value = 1\n\n\nasync def initialize(dut):\n dut.active_clk.value = 0\n dut.free_l2clk.value = 0\n dut.exu_flush_final.value = 0\n dut.dec_tlu_flush_lower_wb.value = 0\n dut.dec_tlu_flush_err_wb.value = 0\n dut.dec_tlu_i0_commit_cmt.value = 0\n dut.dec_tlu_force_halt.value = 0\n dut.ifc_fetch_addr_bf.value = 0\n dut.ifc_fetch_uncacheable_bf.value = 0\n dut.ifc_fetch_req_bf.value = 0\n dut.ifc_fetch_req_bf_raw.value = 0\n dut.ifc_iccm_access_bf.value = 0\n dut.ifc_region_acc_fault_bf.value = 0\n dut.ifc_dma_access_ok.value = 0\n dut.dec_tlu_fence_i_wb.value = 0\n dut.ifu_bp_hit_taken_f.value = 0\n dut.ifu_bp_inst_mask_f.value = 0\n dut.ifu_axi_arready.value = 0\n dut.ifu_axi_rvalid.value = 0\n dut.ifu_axi_rid.value = 0\n dut.ifu_axi_rdata.value = 0\n dut.ifu_axi_rresp.value = 0\n dut.ifu_bus_clk_en.value = 0\n dut.dma_iccm_req.value = 0\n dut.dma_mem_addr.value = 0\n dut.dma_mem_sz.value = 0\n dut.dma_mem_write.value = 0\n dut.dma_mem_wdata.value = 0\n dut.dma_mem_tag.value = 0\n dut.ic_rd_data.value = 0\n dut.ic_debug_rd_data.value = 0\n dut.ictag_debug_rd_data.value = 0\n dut.ic_eccerr.value = 0\n dut.ic_parerr.value = 0\n dut.ic_rd_hit.value = 0\n dut.ic_tag_perr.value = 0\n dut.iccm_rd_data.value = 0\n dut.iccm_rd_data_ecc.value = 0\n dut.ifu_fetch_val.value = 0\n dut.icache_wrdata.value = 0\n dut.icache_dicawics.value = 0\n dut.icache_rd_valid.value = 0\n dut.icache_wr_valid.value = 0\n dut.dec_tlu_core_ecc_disable.value = 0\n dut.ifu_pmp_error.value = 0\n dut.scan_mode.value = 0\n\n cocotb.start_soon(Clock(dut.clk, 1, units=\"ns\").start())\n cocotb.start_soon(Clock(dut.active_clk, 1, units=\"ns\").start())\n cocotb.start_soon(Clock(dut.free_l2clk, 1, units=\"ns\").start())\n\n axi_bfm = Axi4LiteBFM(dut)\n cocotb.start_soon(axi_bfm.read_handler())\n\n await reset(dut)\n\n\nasync def write(dut, addr, wdata):\n await RisingEdge(dut.clk)\n dut.dma_iccm_req.value = 1\n dut.dma_mem_addr.value = addr\n dut.dma_mem_write.value = 1\n dut.dma_mem_wdata.value = wdata\n await RisingEdge(dut.clk)\n dut.dma_iccm_req.value = 0\n dut.dma_mem_addr.value = 0\n dut.dma_mem_write.value = 0\n dut.dma_mem_wdata.value = 0\n\n\nasync def read(dut, addr):\n await RisingEdge(dut.clk)\n dut.dma_iccm_req.value = 1\n dut.dma_mem_write.value = 0\n dut.dma_mem_addr.value = addr\n\n\ndef rand_iccm_addr():\n return random.randint(ICCM_BASE, ICCM_BASE + ICCM_SIZE)\n\n\ndef rand_iccm_data():\n return random.randint(0, (2**64) - 1)\n\n\ndef rand_ifu_addr():\n return random.randint(0, (2**31) - 1)\n\n\ndef get_bitflip_mask(do_double_bit):\n return 2 << (random.randint(0, 2**32 - 1) % (37)) | ((2**40) & ((2**40) - do_double_bit))\n" }, { "path": "verification/block/ifu_mem_ctl/el2_ifu_mem_ctl_wrapper.sv", "content": "module el2_ifu_mem_ctl_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.\n input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.\n input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.\n input logic rst_l, // reset, active low\n\n input logic exu_flush_final, // Flush from the pipeline., includes flush lower\n input logic dec_tlu_flush_lower_wb, // Flush lower from the pipeline.\n input logic dec_tlu_flush_err_wb, // Flush from the pipeline due to perr.\n input logic dec_tlu_i0_commit_cmt, // committed i0 instruction\n input logic dec_tlu_force_halt, // force halt.\n\n input logic [31:1] ifc_fetch_addr_bf, // Fetch Address byte aligned always. F1 stage.\n input logic ifc_fetch_uncacheable_bf, // The fetch request is uncacheable space. F1 stage\n input logic ifc_fetch_req_bf, // Fetch request. Comes with the address. F1 stage\n input logic ifc_fetch_req_bf_raw, // Fetch request without some qualifications. Used for clock-gating. F1 stage\n input logic ifc_iccm_access_bf, // This request is to the ICCM. Do not generate misses to the bus.\n input logic ifc_region_acc_fault_bf, // Access fault. in ICCM region but offset is outside defined ICCM.\n input logic ifc_dma_access_ok, // It is OK to give dma access to the ICCM. (ICCM is not busy this cycle).\n input logic dec_tlu_fence_i_wb, // Fence.i instruction is committing. Clear all Icache valids.\n input logic ifu_bp_hit_taken_f, // Branch is predicted taken. Kill the fetch next cycle.\n\n input logic ifu_bp_inst_mask_f, // tell ic which valids to kill because of a taken branch, right justified\n\n output logic ifu_miss_state_idle, // No icache misses are outstanding.\n output logic ifu_ic_mb_empty, // Continue with normal fetching. This does not mean that miss is finished.\n output logic ic_dma_active , // In the middle of servicing dma request to ICCM. Do not make any new requests.\n output logic ic_write_stall, // Stall fetch the cycle we are writing the cache.\n\n /// PMU signals\n output logic ifu_pmu_ic_miss, // IC miss event\n output logic ifu_pmu_ic_hit, // IC hit event\n output logic ifu_pmu_bus_error, // Bus error event\n output logic ifu_pmu_bus_busy, // Bus busy event\n output logic ifu_pmu_bus_trxn, // Bus transaction\n\n //-------------------------- IFU AXI signals--------------------------\n // AXI Write Channels\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic ifu_axi_awvalid,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,\n output logic [ 31:0] ifu_axi_awaddr,\n output logic [ 3:0] ifu_axi_awregion,\n output logic [ 7:0] ifu_axi_awlen,\n output logic [ 2:0] ifu_axi_awsize,\n output logic [ 1:0] ifu_axi_awburst,\n output logic ifu_axi_awlock,\n output logic [ 3:0] ifu_axi_awcache,\n output logic [ 2:0] ifu_axi_awprot,\n output logic [ 3:0] ifu_axi_awqos,\n\n output logic ifu_axi_wvalid,\n output logic [63:0] ifu_axi_wdata,\n output logic [ 7:0] ifu_axi_wstrb,\n output logic ifu_axi_wlast,\n\n output logic ifu_axi_bready,\n /*pragma coverage on*/\n\n // AXI Read Channels\n output logic ifu_axi_arvalid,\n input logic ifu_axi_arready,\n output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,\n output logic [ 31:0] ifu_axi_araddr,\n output logic [ 3:0] ifu_axi_arregion,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic [ 7:0] ifu_axi_arlen,\n output logic [ 2:0] ifu_axi_arsize,\n output logic [ 1:0] ifu_axi_arburst,\n output logic ifu_axi_arlock,\n output logic [ 3:0] ifu_axi_arcache,\n output logic [ 2:0] ifu_axi_arprot,\n output logic [ 3:0] ifu_axi_arqos,\n /*pragma coverage on*/\n\n input logic ifu_axi_rvalid,\n /* exclude signals that are tied to constant value in this file */\n /*pragma coverage off*/\n output logic ifu_axi_rready,\n /*pragma coverage on*/\n input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,\n input logic [ 63:0] ifu_axi_rdata,\n input logic [ 1:0] ifu_axi_rresp,\n\n input logic ifu_bus_clk_en,\n\n\n input logic dma_iccm_req, // dma iccm command (read or write)\n input logic [31:0] dma_mem_addr, // dma address\n input logic [ 2:0] dma_mem_sz, // size\n input logic dma_mem_write, // write\n input logic [63:0] dma_mem_wdata, // write data\n input logic [ 2:0] dma_mem_tag, // DMA Buffer entry number\n\n output logic iccm_dma_ecc_error, // Data read from iccm has an ecc error\n output logic iccm_dma_rvalid, // Data read from iccm is valid\n output logic [63:0] iccm_dma_rdata, // dma data read from iccm\n output logic [ 2:0] iccm_dma_rtag, // Tag of the DMA req\n output logic iccm_ready, // iccm ready to accept new command.\n\n\n // I$ & ITAG Ports\n output logic [31:1] ic_rw_addr, // Read/Write addresss to the Icache.\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en, // Icache write enable, when filling the Icache.\n output logic ic_rd_en, // Icache read enable.\n\n output logic [pt.ICACHE_BANKS_WAY-1:0] [70:0] ic_wr_data, // Data to fill to the Icache. With ECC\n input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC\n input logic [25:0] ictag_debug_rd_data, // Debug icache tag.\n output logic [70:0] ic_debug_wr_data, // Debug wr cache.\n output logic [70:0] ifu_ic_debug_rd_data, // debug data read\n\n\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, //\n input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,\n\n output logic [ pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.\n output logic ic_debug_rd_en, // Icache debug rd\n output logic ic_debug_wr_en, // Icache debug wr\n output logic ic_debug_tag_array, // Debug tag array\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.\n\n\n output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid bits when accessing the Icache. One valid bit per way. F2 stage\n\n input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, // Compare hits from Icache tags. Per way. F2 stage\n input logic ic_tag_perr, // Icache Tag parity error\n\n // ICCM ports\n output logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address.\n output logic iccm_wren, // ICCM write enable (through the DMA)\n output logic iccm_rden, // ICCM read enable.\n output logic [ 77:0] iccm_wr_data, // ICCM write data.\n output logic [ 2:0] iccm_wr_size, // ICCM write location within DW.\n\n input logic [63:0] iccm_rd_data, // Data read from ICCM.\n input logic [77:0] iccm_rd_data_ecc, // Data + ECC read from ICCM.\n input logic [1:0] ifu_fetch_val,\n // IFU control signals\n output logic ic_hit_f, // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f)\n output logic [1:0] ic_access_fault_f, // Access fault (bus error or ICCM access in region but out of offset range).\n output logic [1:0] ic_access_fault_type_f, // Access fault types\n output logic iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.\n output logic [1:0] iccm_rd_ecc_double_err, // This fetch has a double ICCM ECC error.\n output logic iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error.\n output logic iccm_dma_rd_ecc_double_err, // This fetch has a double ICCM DMA ECC error.\n output logic ic_error_start, // This has any I$ errors ( data/tag/ecc/parity )\n\n output logic ifu_async_error_start, // Or of the sb iccm, and all the icache errors sent to aligner to stop\n output logic iccm_dma_sb_error, // Single Bit ECC error from a DMA access\n output logic [1:0] ic_fetch_val_f, // valid bytes for fetch. To the Aligner.\n output logic [31:0] ic_data_f, // Data read from Icache or ICCM. To the Aligner.\n output logic [63:0] ic_premux_data, // Premuxed data to be muxed with Icache data\n output logic ic_sel_premux_data, // Select premux data.\n\n ///// Debug\n // Icache/tag debug read/write packet\n input logic [70:0] icache_wrdata,\n input logic [16:0] icache_dicawics,\n input logic icache_rd_valid,\n input logic icache_wr_valid,\n\n input logic dec_tlu_core_ecc_disable, // disable the ecc checking and flagging\n output logic ifu_ic_debug_rd_data_valid, // debug data valid.\n output logic iccm_buf_correct_ecc,\n output logic iccm_correction_state,\n\n input logic ifu_pmp_error,\n\n input logic scan_mode\n);\n el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt;\n\n assign dec_tlu_ic_diag_pkt = {icache_wrdata, icache_dicawics, icache_rd_valid, icache_wr_valid};\n\n el2_ifu_mem_ctl ifu_mem_ctl (.*);\n\nendmodule // el2_ifu_mem_ctl_wrapper\n" }, { "path": "verification/block/ifu_mem_ctl/test_err.py", "content": "import cocotb\nfrom cocotb.triggers import ClockCycles, RisingEdge\n\nfrom common import (\n get_bitflip_mask,\n initialize,\n rand_iccm_addr,\n rand_ifu_addr,\n read,\n reset,\n)\n\n# Error states\nERR_IDLE = 0b000\nIC_WFF = 0b001\nECC_WFF = 0b010\nECC_CORR = 0b011\nDMA_SB_ERR = 0b100\n\n\nasync def fetch_miss(dut, addr, req_bf_raw=1, uncacheable_bf=1):\n dut.ifc_fetch_req_bf.value = 1\n dut.ifc_fetch_req_bf_raw.value = req_bf_raw\n dut.ifc_fetch_uncacheable_bf.value = uncacheable_bf\n dut.ifc_fetch_addr_bf.value = addr\n await RisingEdge(dut.clk)\n dut.ifc_fetch_req_bf_raw.value = 0\n dut.ifc_fetch_uncacheable_bf.value = 0\n dut.ifc_fetch_addr_bf.value = 0\n\n\ndef verify_state(dut, exp_state):\n state_names = [\n \"ERR_IDLE\",\n \"IC_WFF\",\n \"ECC_WFF\",\n \"ECC_CORR\",\n \"DMA_SB_ERR\",\n ]\n assert (\n dut.ifu_mem_ctl.perr_state.value == exp_state\n ), f\"Expected state {state_names[exp_state]}, got {dut.ifu_mem_ctl.perr_state.value}\"\n\n\nasync def dma_sb_error(dut, force_halt=False):\n verify_state(dut, ERR_IDLE)\n dut.ifc_dma_access_ok.value = 1\n dut.iccm_rd_data.value = 44\n dut.iccm_rd_data_ecc.value = 44 ^ get_bitflip_mask(0)\n await fetch_miss(dut, rand_ifu_addr())\n await read(dut, rand_iccm_addr())\n await RisingEdge(dut.iccm_dma_rvalid)\n # dec_tlu_force_halt must appear here to achieve DMA_SB_ERR -> ERR_IDLE transition\n # FSM always switches state from `DMA_SB_ERR` in the next cycle\n if force_halt:\n dut.dec_tlu_force_halt.value = 1\n await RisingEdge(dut.clk)\n verify_state(dut, DMA_SB_ERR)\n\n\n@cocotb.test()\nasync def test_dma_sb_error(dut):\n await initialize(dut)\n verify_state(dut, ERR_IDLE)\n\n await dma_sb_error(dut)\n\n await reset(dut)\n verify_state(dut, ERR_IDLE)\n\n\n@cocotb.test()\nasync def test_dma_sb_error_force_halt(dut):\n await initialize(dut)\n verify_state(dut, ERR_IDLE)\n\n await dma_sb_error(dut, force_halt=True)\n await ClockCycles(dut.clk, 1)\n verify_state(dut, ERR_IDLE)\n\n\n@cocotb.test()\nasync def test_ecc_corr(dut):\n await initialize(dut)\n verify_state(dut, ERR_IDLE)\n\n await dma_sb_error(dut)\n\n await RisingEdge(dut.clk)\n verify_state(dut, ECC_CORR)\n\n await reset(dut)\n verify_state(dut, ERR_IDLE)\n\n\nasync def ic_wff(dut):\n verify_state(dut, ERR_IDLE)\n\n dut.ic_tag_perr.value = 1\n dut.ifc_dma_access_ok.value = 1\n dut.iccm_rd_data.value = 44\n dut.iccm_rd_data_ecc.value = 44 ^ get_bitflip_mask(1)\n await fetch_miss(dut, rand_ifu_addr())\n await read(dut, rand_iccm_addr())\n\n await RisingEdge(dut.clk)\n verify_state(dut, IC_WFF)\n\n\n@cocotb.test()\nasync def test_ic_wff(dut):\n await initialize(dut)\n\n await ic_wff(dut)\n\n await reset(dut)\n verify_state(dut, ERR_IDLE)\n\n\n@cocotb.test()\nasync def test_ic_wff_force_halt(dut):\n await initialize(dut)\n\n await ic_wff(dut)\n\n dut.dec_tlu_force_halt.value = 1\n await ClockCycles(dut.clk, 2)\n verify_state(dut, ERR_IDLE)\n\n\nasync def ecc_wff(dut):\n await initialize(dut)\n verify_state(dut, ERR_IDLE)\n\n dut.ic_tag_perr.value = 1\n dut.ifc_dma_access_ok.value = 1\n dut.ifc_iccm_access_bf.value = 1\n dut.iccm_rd_data.value = 44\n dut.iccm_rd_data_ecc.value = 44\n await fetch_miss(dut, rand_ifu_addr())\n\n await ClockCycles(dut.clk, 2)\n verify_state(dut, ECC_WFF)\n\n\n@cocotb.test()\nasync def test_ecc_wff(dut):\n await initialize(dut)\n verify_state(dut, ERR_IDLE)\n\n await ecc_wff(dut)\n\n await reset(dut)\n verify_state(dut, ERR_IDLE)\n\n\n@cocotb.test()\nasync def test_ecc_wff_force_halt(dut):\n await initialize(dut)\n\n await ecc_wff(dut)\n\n dut.dec_tlu_force_halt.value = 1\n await ClockCycles(dut.clk, 2)\n verify_state(dut, ERR_IDLE)\n" }, { "path": "verification/block/ifu_mem_ctl/test_err_stop.py", "content": "import cocotb\nfrom cocotb.triggers import ClockCycles, RisingEdge\n\nfrom common import initialize, rand_ifu_addr\n\n# Error stop states\nERR_STOP_IDLE = 0b00\nERR_FETCH1 = 0b01\nERR_FETCH2 = 0b10\nERR_STOP_FETCH = 0b11\n\n\nasync def fetch_miss(dut, addr, req_bf_raw=1, uncacheable_bf=1):\n dut.ifc_fetch_req_bf.value = 1\n dut.ifc_fetch_req_bf_raw.value = req_bf_raw\n dut.ifc_fetch_uncacheable_bf.value = uncacheable_bf\n dut.ifc_fetch_addr_bf.value = addr\n await RisingEdge(dut.clk)\n dut.ifc_fetch_req_bf_raw.value = 0\n dut.ifc_fetch_uncacheable_bf.value = 0\n dut.ifc_fetch_addr_bf.value = 0\n\n\ndef verify_state(dut, exp_state):\n state_names = [\n \"ERR_STOP_IDLE\",\n \"ERR_FETCH1\",\n \"ERR_FETCH2\",\n \"ERR_STOP_FETCH\",\n ]\n assert (\n dut.ifu_mem_ctl.err_stop_state.value == exp_state\n ), f\"Expected state {state_names[exp_state]}, got {dut.ifu_mem_ctl.err_stop_state.value}\"\n\n\n@cocotb.test()\nasync def test_err_fetch1(dut):\n await initialize(dut)\n verify_state(dut, ERR_STOP_IDLE)\n # verify_state(dut, ERR_IDLE)\n\n dut.ic_tag_perr.value = 1\n dut.ifc_dma_access_ok.value = 1\n dut.ifc_iccm_access_bf.value = 1\n dut.iccm_rd_data.value = 44\n dut.iccm_rd_data_ecc.value = 44\n await fetch_miss(dut, rand_ifu_addr())\n\n await ClockCycles(dut.clk, 2)\n dut.dec_tlu_flush_err_wb.value = 1\n # verify_state(dut, ECC_WFF)\n await ClockCycles(dut.clk, 2)\n verify_state(dut, ERR_FETCH1)\n\n\n@cocotb.test()\nasync def test_err_fetch2(dut):\n await initialize(dut)\n verify_state(dut, ERR_STOP_IDLE)\n # verify_state(dut, ERR_IDLE)\n\n dut.ic_tag_perr.value = 1\n dut.ifc_dma_access_ok.value = 1\n dut.ifc_iccm_access_bf.value = 1\n dut.ic_rd_data.value = 2**63 - 1\n dut.iccm_rd_data.value = 44\n dut.iccm_rd_data_ecc.value = 44\n dut.ifu_fetch_val.value = 1\n await fetch_miss(dut, rand_ifu_addr())\n\n await ClockCycles(dut.clk, 2)\n dut.dec_tlu_flush_err_wb.value = 1\n # verify_state(dut, ECC_WFF)\n await ClockCycles(dut.clk, 2)\n verify_state(dut, ERR_FETCH1)\n dut.ifu_fetch_val.value = 0\n await ClockCycles(dut.clk, 1)\n verify_state(dut, ERR_FETCH2)\n await ClockCycles(dut.clk, 1)\n verify_state(dut, ERR_FETCH2)\n await ClockCycles(dut.clk, 5)\n\n dut.dec_tlu_force_halt.value = 1\n await ClockCycles(dut.clk, 2)\n verify_state(dut, ERR_STOP_IDLE)\n\n\n# ERR_STOP_FETCH -> ERR_STOP_FETCH\n@cocotb.test()\nasync def test_err_stop_fetch(dut):\n await initialize(dut)\n verify_state(dut, ERR_STOP_IDLE)\n # verify_state(dut, ERR_IDLE)\n\n dut.ic_tag_perr.value = 1\n dut.ifc_dma_access_ok.value = 1\n dut.ifc_iccm_access_bf.value = 1\n dut.ic_rd_data.value = 2**63 - 1\n dut.iccm_rd_data.value = 44\n dut.iccm_rd_data_ecc.value = 44\n dut.ifu_fetch_val.value = 1\n await fetch_miss(dut, rand_ifu_addr())\n\n await ClockCycles(dut.clk, 2)\n dut.dec_tlu_flush_err_wb.value = 1\n # verify_state(dut, ECC_WFF)\n await ClockCycles(dut.clk, 2)\n verify_state(dut, ERR_FETCH1)\n await RisingEdge(dut.clk)\n verify_state(dut, ERR_FETCH2)\n dut.dec_tlu_flush_err_wb.value = 0\n await RisingEdge(dut.clk)\n verify_state(dut, ERR_STOP_FETCH)\n await ClockCycles(dut.clk, 5)\n" }, { "path": "verification/block/ifu_mem_ctl/test_miss.py", "content": "import cocotb\nfrom cocotb.triggers import ClockCycles, RisingEdge\n\nfrom common import (\n initialize,\n rand_iccm_addr,\n rand_iccm_data,\n rand_ifu_addr,\n reset,\n write,\n)\n\n# Miss states\nIDLE = 0b000\nCRIT_BYP_OK = 0b001\nHIT_U_MISS = 0b010\nMISS_WAIT = 0b011\nCRIT_WRD_RDY = 0b100\nSCND_MISS = 0b101\nSTREAM = 0b110\nSTALL_SCND_MISS = 0b111\n\n\nasync def fetch_miss(dut, addr, req_bf_raw=1, uncacheable_bf=1, dma_access_ok=0):\n dut.ifc_fetch_req_bf.value = 1\n dut.ifc_fetch_req_bf_raw.value = req_bf_raw\n dut.ifc_fetch_uncacheable_bf.value = uncacheable_bf\n dut.ifc_fetch_addr_bf.value = addr\n dut.ifc_dma_access_ok.value = dma_access_ok\n await RisingEdge(dut.clk)\n dut.ifc_fetch_req_bf.value = 0\n dut.ifc_fetch_req_bf_raw.value = 0\n dut.ifc_fetch_uncacheable_bf.value = 0\n dut.ifc_fetch_addr_bf.value = 0\n dut.ifc_dma_access_ok.value = 0\n\n\ndef verify_state(dut, exp_state):\n state_names = [\n \"IDLE\",\n \"CRIT_BYP_OK\",\n \"HIT_U_MISS\",\n \"MISS_WAIT\",\n \"CRIT_WRD_RDY\",\n \"SCND_MISS\",\n \"STREAM\",\n \"STALL_SCND_MISS\",\n ]\n assert (\n dut.ifu_mem_ctl.miss_state.value == exp_state\n ), f\"Expected state {state_names[exp_state]}, got {dut.ifu_mem_ctl.miss_state.value}\"\n\n\nasync def crit_byp_ok(dut):\n verify_state(dut, IDLE)\n\n await fetch_miss(dut, 128, dma_access_ok=1)\n await write(dut, rand_iccm_addr(), rand_iccm_data())\n\n await RisingEdge(dut.clk)\n verify_state(dut, CRIT_BYP_OK)\n\n\n@cocotb.test()\nasync def test_crit_byp_ok(dut):\n await initialize(dut)\n await crit_byp_ok(dut)\n await reset(dut)\n verify_state(dut, IDLE)\n\n\n@cocotb.test()\nasync def test_crit_byp_ok_force_halt(dut):\n await initialize(dut)\n await crit_byp_ok(dut)\n\n dut.dec_tlu_force_halt.value = 1\n await ClockCycles(dut.clk, 2)\n verify_state(dut, IDLE)\n\n\nasync def crit_wrd_rdy(dut):\n verify_state(dut, IDLE)\n\n await fetch_miss(dut, rand_ifu_addr())\n await write(dut, rand_iccm_addr(), rand_iccm_data())\n\n await RisingEdge(dut.clk)\n verify_state(dut, CRIT_BYP_OK)\n\n await write(dut, rand_iccm_addr(), rand_iccm_data())\n\n await ClockCycles(dut.clk, 2)\n verify_state(dut, CRIT_WRD_RDY)\n\n\n@cocotb.test()\nasync def test_crit_wrd_rdy(dut):\n await initialize(dut)\n await crit_wrd_rdy(dut)\n await reset(dut)\n verify_state(dut, IDLE)\n\n\n@cocotb.test()\nasync def test_crit_wrd_rdy_force_halt(dut):\n await initialize(dut)\n await crit_wrd_rdy(dut)\n\n dut.dec_tlu_force_halt.value = 1\n await ClockCycles(dut.clk, 2)\n verify_state(dut, IDLE)\n\n\nasync def hit_u_miss(dut):\n verify_state(dut, IDLE)\n\n await fetch_miss(dut, rand_ifu_addr(), req_bf_raw=0, dma_access_ok=1)\n await write(dut, rand_iccm_addr(), rand_iccm_data())\n\n await ClockCycles(cocotb.top.clk, 1)\n verify_state(dut, CRIT_BYP_OK)\n\n dut.exu_flush_final.value = 1\n await ClockCycles(cocotb.top.clk, 2)\n verify_state(dut, HIT_U_MISS)\n dut.exu_flush_final.value = 0\n\n\n@cocotb.test()\nasync def test_hit_u_miss(dut):\n await initialize(dut)\n await hit_u_miss(dut)\n await reset(dut)\n verify_state(dut, IDLE)\n\n\n@cocotb.test()\nasync def test_hit_u_miss_force_halt(dut):\n await initialize(dut)\n await hit_u_miss(dut)\n\n dut.dec_tlu_force_halt.value = 1\n await ClockCycles(dut.clk, 2)\n verify_state(dut, IDLE)\n\n\nasync def scnd_miss(dut):\n verify_state(dut, IDLE)\n await hit_u_miss(dut)\n await fetch_miss(dut, rand_ifu_addr(), req_bf_raw=0, dma_access_ok=1)\n await write(dut, rand_iccm_addr(), rand_iccm_data())\n\n await RisingEdge(dut.clk)\n verify_state(dut, SCND_MISS)\n\n\n@cocotb.test()\nasync def test_scnd_miss(dut):\n await initialize(dut)\n await scnd_miss(dut)\n await reset(dut)\n verify_state(dut, IDLE)\n\n\n@cocotb.test()\nasync def test_scnd_miss_force_halt(dut):\n await initialize(dut)\n await scnd_miss(dut)\n\n dut.dec_tlu_force_halt.value = 1\n await ClockCycles(dut.clk, 2)\n verify_state(dut, IDLE)\n\n\nasync def stall_scnd_miss(dut):\n verify_state(dut, IDLE)\n await hit_u_miss(dut)\n await fetch_miss(dut, 0, req_bf_raw=0)\n await write(dut, rand_iccm_addr(), rand_iccm_data())\n\n await ClockCycles(dut.clk, 1)\n verify_state(dut, STALL_SCND_MISS)\n\n\n@cocotb.test()\nasync def test_stall_scnd_miss(dut):\n await initialize(dut)\n await stall_scnd_miss(dut)\n await reset(dut)\n verify_state(dut, IDLE)\n\n\n@cocotb.test()\nasync def test_stall_scnd_miss_force_halt(dut):\n await initialize(dut)\n await stall_scnd_miss(dut)\n\n dut.dec_tlu_force_halt.value = 1\n await ClockCycles(dut.clk, 2)\n verify_state(dut, IDLE)\n" }, { "path": "verification/block/lib_ahb_to_axi4/Makefile", "content": "\nnull :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = ahb_to_axi4_wrapper\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/lib/ahb_to_axi4.sv \\\n $(TEST_DIR)/ahb_to_axi4_wrapper.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/lib_ahb_to_axi4/ahb_to_axi4_wrapper.sv", "content": "module ahb_to_axi4_wrapper\n#(\n TAG = 1,\n `include \"el2_param.vh\"\n)\n(\n input clk,\n input rst_l,\n input scan_mode,\n input bus_clk_en,\n input clk_override,\n\n output logic axi_awvalid,\n input logic axi_awready,\n output logic [TAG-1:0] axi_awid,\n output logic [31:0] axi_awaddr,\n output logic [2:0] axi_awsize,\n output logic [2:0] axi_awprot,\n output logic [7:0] axi_awlen,\n output logic [1:0] axi_awburst,\n\n output logic axi_wvalid,\n input logic axi_wready,\n output logic [63:0] axi_wdata,\n output logic [7:0] axi_wstrb,\n output logic axi_wlast,\n\n input logic axi_bvalid,\n output logic axi_bready,\n input logic [1:0] axi_bresp,\n input logic [TAG-1:0] axi_bid,\n\n output logic axi_arvalid,\n input logic axi_arready,\n output logic [TAG-1:0] axi_arid,\n output logic [31:0] axi_araddr,\n output logic [2:0] axi_arsize,\n output logic [2:0] axi_arprot,\n output logic [7:0] axi_arlen,\n output logic [1:0] axi_arburst,\n\n input logic axi_rvalid,\n output logic axi_rready,\n input logic [TAG-1:0] axi_rid,\n input logic [63:0] axi_rdata,\n input logic [1:0] axi_rresp,\n\n input logic [31:0] ahb_haddr,\n input logic [2:0] ahb_hburst,\n input logic ahb_hmastlock,\n input logic [3:0] ahb_hprot,\n input logic [2:0] ahb_hsize,\n input logic [1:0] ahb_htrans,\n input logic ahb_hwrite,\n input logic [63:0] ahb_hwdata,\n input logic ahb_hsel,\n input logic ahb_hreadyin,\n\n output logic [63:0] ahb_hrdata,\n output logic ahb_hreadyout,\n output logic ahb_hresp\n);\n // set CHECK_RANGES(0), the rest remains default.\n // this allows working with the full range of addresses.\n ahb_to_axi4 #(.pt(pt),.CHECK_RANGES(0)) inst (\n .*\n );\nendmodule // ahb_to_axi4_wrapper\n" }, { "path": "verification/block/lib_ahb_to_axi4/test_read.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles, Combine\nfrom pyuvm import *\nfrom testbench import (\n AXI4LiteReadyItem,\n AXI4LiteResponseItem,\n BaseEnv,\n BaseTest,\n BusReadItem,\n)\n\n# =============================================================================\n\n\nclass AHBReadSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n align = 8\n addr = align * random.randint(0, 0x1FFFFFFF)\n\n item = BusReadItem(addr)\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass AXI4LiteReadResponseSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Respond to AR\n item = AXI4LiteResponseItem([\"ar\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n # Emulate latency\n await ClockCycles(cocotb.top.clk, 2)\n\n # Respond on R\n item = AXI4LiteResponseItem([\"r\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass AXI4LiteNoReadDataResponseSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Respond to AR but not to R\n item = AXI4LiteResponseItem([\"ar\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# =============================================================================\n\n\nclass AXI4LiteReadReadySequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Become ready\n item = AXI4LiteReadyItem([\"ar\"], True)\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# =============================================================================\n\n\nasync def later(cr, cycles):\n \"\"\"\n A helper function to start a task after a number of clock cycles\n \"\"\"\n await ClockCycles(cocotb.top.clk, cycles)\n await cr\n\n\nclass NoBackpressureReadSequence(uvm_sequence):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"AHB_SEQR\")\n axi_seqr = ConfigDB().get(None, \"\", \"AXI_SEQR\")\n\n axi_rdy = AXI4LiteReadReadySequence(\"ready\")\n ahb_seq = AHBReadSequence(\"stimulus\")\n axi_seq = AXI4LiteReadResponseSequence(\"response\")\n\n # Issue an AHB read and do a correct AXI response\n await axi_rdy.start(axi_seqr)\n\n tasks = [\n cocotb.start_soon(ahb_seq.start(ahb_seqr)),\n cocotb.start_soon(axi_seq.start(axi_seqr)),\n ]\n await Combine(*tasks)\n\n\nclass BackpressureReadSequence(uvm_sequence):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"AHB_SEQR\")\n axi_seqr = ConfigDB().get(None, \"\", \"AXI_SEQR\")\n\n ahb_seq = AHBReadSequence(\"stimulus\")\n axi_seq = AXI4LiteReadResponseSequence(\"response\")\n\n # Issue an AHB read and do a correct AXI response\n tasks = [\n cocotb.start_soon(ahb_seq.start(ahb_seqr)),\n cocotb.start_soon(later(axi_seq.start(axi_seqr), 5)),\n ]\n await Combine(*tasks)\n\n\nclass NoReadDataResponseSequence(uvm_sequence):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"AHB_SEQR\")\n axi_seqr = ConfigDB().get(None, \"\", \"AXI_SEQR\")\n\n axi_rdy = AXI4LiteReadReadySequence(\"ready\")\n ahb_seq = AHBReadSequence(\"stimulus\")\n axi_seq = AXI4LiteNoReadDataResponseSequence(\"response\")\n\n # Issue an AHB read and do a correct AXI response\n await axi_rdy.start(axi_seqr)\n\n tasks = [\n cocotb.start_soon(ahb_seq.start(ahb_seqr)),\n cocotb.start_soon(axi_seq.start(axi_seqr)),\n ]\n await Combine(*tasks)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestReadNoBackpressure(BaseTest):\n \"\"\"\n Read test with no AXI backpressure\n \"\"\"\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = NoBackpressureReadSequence()\n\n async def run(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n gap = ConfigDB().get(None, \"\", \"TEST_BURST_GAP\")\n\n for i in range(count):\n await self.seq.start()\n await ClockCycles(cocotb.top.clk, gap)\n\n\n@pyuvm.test()\nclass TestReadBackpressure(BaseTest):\n \"\"\"\n Read test with AXI backpressure\n \"\"\"\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BackpressureReadSequence()\n\n async def run(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n gap = ConfigDB().get(None, \"\", \"TEST_BURST_GAP\")\n\n for i in range(count):\n await self.seq.start()\n await ClockCycles(cocotb.top.clk, gap)\n\n\n@pyuvm.test(expect_error=TimeoutError)\nclass TestReadNoDataResponse(BaseTest):\n \"\"\"\n Read test with response on AR channel but not on R channel. A timeout should\n occur due to lack of the response.\n \"\"\"\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = NoReadDataResponseSequence()\n\n async def run(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n gap = ConfigDB().get(None, \"\", \"TEST_BURST_GAP\")\n\n for i in range(count):\n await self.seq.start()\n await ClockCycles(cocotb.top.clk, gap)\n" }, { "path": "verification/block/lib_ahb_to_axi4/test_write.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import (\n AXI4LiteReadyItem,\n AXI4LiteResponseItem,\n BaseEnv,\n BaseTest,\n BusWriteItem,\n)\n\n# =============================================================================\n\n\nclass AHBWriteSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n dwidth = 64\n align = 8\n\n addr = align * random.randint(0, 0x1FFFFFFF)\n data = [random.randrange(0, (1 << dwidth) - 1)]\n\n item = BusWriteItem(addr, data)\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass AXI4LiteWriteResponseSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Respond to AW and W\n item = AXI4LiteResponseItem([\"aw\", \"w\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n # Emulate latency\n await ClockCycles(cocotb.top.clk, 2)\n\n # Respond on B\n item = AXI4LiteResponseItem([\"b\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass AXI4LiteNoWriteDataResponseSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Respond to AW only\n item = AXI4LiteResponseItem([\"aw\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n # Emulate latency\n await ClockCycles(cocotb.top.clk, 2)\n\n # Respond on B\n item = AXI4LiteResponseItem([\"b\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass AXI4LiteNoWriteAddrResponseSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Respond to W only\n item = AXI4LiteResponseItem([\"w\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n # Emulate latency\n await ClockCycles(cocotb.top.clk, 2)\n\n # Respond on B\n item = AXI4LiteResponseItem([\"b\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass AXI4LiteNoWriteResponseSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Respond to AW and W, do NOT respond to B\n item = AXI4LiteResponseItem([\"aw\", \"w\"])\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# =============================================================================\n\n\nclass AXI4LiteWriteReadySequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Become ready\n item = AXI4LiteReadyItem([\"aw\", \"w\"], True)\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass AXI4LiteNoWriteDataReadySequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Become ready\n item = AXI4LiteReadyItem([\"aw\"], True)\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass AXI4LiteNoWriteAddrReadySequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n # Become ready\n item = AXI4LiteReadyItem([\"w\"], True)\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# =============================================================================\n\n\nclass NoBackpressureWriteSequence(uvm_sequence):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"AHB_SEQR\")\n axi_seqr = ConfigDB().get(None, \"\", \"AXI_SEQR\")\n\n axi_rdy = AXI4LiteWriteReadySequence(\"ready\")\n ahb_seq = AHBWriteSequence(\"stimulus\")\n axi_seq = AXI4LiteWriteResponseSequence(\"response\")\n\n # Issue an AHB write and do a correct AXI response\n await axi_rdy.start(axi_seqr)\n await ahb_seq.start(ahb_seqr)\n await axi_seq.start(axi_seqr)\n\n\nclass BackpressureWriteSequence(uvm_sequence):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"AHB_SEQR\")\n axi_seqr = ConfigDB().get(None, \"\", \"AXI_SEQR\")\n\n ahb_seq = AHBWriteSequence(\"stimulus\")\n axi_seq = AXI4LiteWriteResponseSequence(\"response\")\n\n # Issue an AHB write and do a correct AXI response\n await ahb_seq.start(ahb_seqr)\n await axi_seq.start(axi_seqr)\n\n\nclass NoWriteResponseSequence(uvm_sequence):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"AHB_SEQR\")\n axi_seqr = ConfigDB().get(None, \"\", \"AXI_SEQR\")\n\n axi_rdy = AXI4LiteWriteReadySequence(\"ready\")\n ahb_seq = AHBWriteSequence(\"stimulus\")\n axi_seq = AXI4LiteNoWriteResponseSequence(\"response\")\n\n await axi_rdy.start(axi_seqr)\n await ahb_seq.start(ahb_seqr)\n await axi_seq.start(axi_seqr)\n\n\nclass NoWriteDataResponseSequence(uvm_sequence):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"AHB_SEQR\")\n axi_seqr = ConfigDB().get(None, \"\", \"AXI_SEQR\")\n\n axi_rdy = AXI4LiteNoWriteDataReadySequence(\"ready\")\n ahb_seq = AHBWriteSequence(\"stimulus\")\n axi_seq = AXI4LiteNoWriteDataResponseSequence(\"response\")\n\n await axi_rdy.start(axi_seqr)\n await ahb_seq.start(ahb_seqr)\n await axi_seq.start(axi_seqr)\n\n\nclass NoWriteAddrResponseSequence(uvm_sequence):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"AHB_SEQR\")\n axi_seqr = ConfigDB().get(None, \"\", \"AXI_SEQR\")\n\n axi_rdy = AXI4LiteNoWriteAddrReadySequence(\"ready\")\n ahb_seq = AHBWriteSequence(\"stimulus\")\n axi_seq = AXI4LiteNoWriteAddrResponseSequence(\"response\")\n\n await axi_rdy.start(axi_seqr)\n await ahb_seq.start(ahb_seqr)\n await axi_seq.start(axi_seqr)\n\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestWriteNoBackpressure(BaseTest):\n \"\"\"\n Write test with no AXI backpressure\n \"\"\"\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = NoBackpressureWriteSequence()\n\n async def run(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n gap = ConfigDB().get(None, \"\", \"TEST_BURST_GAP\")\n\n for i in range(count):\n await self.seq.start()\n await ClockCycles(cocotb.top.clk, gap)\n\n\n@pyuvm.test()\nclass TestWriteBackpressure(BaseTest):\n \"\"\"\n Write test with AXI backpressure\n \"\"\"\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = BackpressureWriteSequence()\n\n async def run(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n gap = ConfigDB().get(None, \"\", \"TEST_BURST_GAP\")\n\n for i in range(count):\n await self.seq.start()\n await ClockCycles(cocotb.top.clk, gap)\n\n\n# FIXME: This test is expected to fail as the AHB to AXI bridge does not wait\n# for response on B channel and completely ignores it\n@pyuvm.test(expect_fail=True) # FIXME: should be expect_fail=False\nclass TestWriteNoResponse(BaseTest):\n \"\"\"\n Write test with no AXI backpressure but without a response on B channel\n \"\"\"\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = NoWriteResponseSequence()\n\n async def run(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n gap = ConfigDB().get(None, \"\", \"TEST_BURST_GAP\")\n\n for i in range(count):\n await self.seq.start()\n await ClockCycles(cocotb.top.clk, gap)\n\n\n@pyuvm.test(expect_error=TimeoutError)\nclass TestWriteNoAddrResponse(BaseTest):\n \"\"\"\n Write test with no AXI backpressure and no response on AW. A timeout should\n occur due to lack of the response.\n \"\"\"\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = NoWriteAddrResponseSequence()\n\n async def run(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n gap = ConfigDB().get(None, \"\", \"TEST_BURST_GAP\")\n\n for i in range(count):\n await self.seq.start()\n await ClockCycles(cocotb.top.clk, gap)\n\n\n# FIXME: The module ignores wready and does not wait until data gets accepted\n# by the subordinate.\n@pyuvm.test(expect_fail=True) # FIXME: should be expect_error=Timeout\nclass TestWriteNoDataResponse(BaseTest):\n \"\"\"\n Write test with no AXI backpressure and no response on W. A timeout should\n occur due to lack of the response.\n \"\"\"\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = NoWriteDataResponseSequence()\n\n async def run(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n gap = ConfigDB().get(None, \"\", \"TEST_BURST_GAP\")\n\n for i in range(count):\n await self.seq.start()\n await ClockCycles(cocotb.top.clk, gap)\n" }, { "path": "verification/block/lib_ahb_to_axi4/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport os\nimport random\nimport sys\nfrom enum import Enum\n\nimport pyuvm\nfrom axi import Axi4LiteMonitor, BusReadItem, BusWriteItem\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, Combine, FallingEdge, RisingEdge\nfrom pyuvm import *\nfrom utils import collect_bytes, collect_signals\n\n# ==============================================================================\n\n\nclass AXI4LiteReadyItem(uvm_sequence_item):\n \"\"\"\n An item describing ready signal assertion / deassertion for an AXI4 lite\n channel(s)\n \"\"\"\n\n def __init__(self, channels, ready=True):\n super().__init__(\"AXI4LiteReadyItem\")\n self.channels = channels\n self.ready = ready\n\n\nclass AXI4LiteResponseItem(uvm_sequence_item):\n \"\"\"\n An item describing a response for an AXI4 lite channel(s)\n \"\"\"\n\n def __init__(self, channels):\n super().__init__(\"AXI4LiteResponseItem\")\n self.channels = channels\n\n\n# ==============================================================================\n\n\nclass AHBLiteManagerBFM(uvm_component):\n \"\"\"\n AHB Lite bus BFM that operates as a manager.\n \"\"\"\n\n SIGNALS = [\n \"hclk\",\n \"hreset\",\n \"haddr\",\n \"hburst\",\n \"hmastlock\",\n \"hprot\",\n \"hsize\",\n \"htrans\",\n \"hwrite\",\n \"hwdata\",\n \"hsel\",\n \"hrdata\",\n \"hreadyout\",\n \"hresp\",\n ]\n\n class HTRANS(Enum):\n IDLE = 0b00\n BUSY = 0b01\n NONSEQ = 0b10\n SEQ = 0b11\n\n class HBURST(Enum):\n SINGLE = 0b000\n INCR = 0b001\n WRAP4 = 0b010\n INCR4 = 0b011\n WRAP8 = 0b100\n INCR8 = 0b101\n WRAP16 = 0b110\n INCR16 = 0b111\n\n def __init__(self, name, parent, uut, signal_prefix=\"\", signal_map=None):\n super().__init__(name, parent)\n\n collect_signals(\n self.SIGNALS,\n uut,\n self,\n uut_prefix=signal_prefix,\n obj_prefix=\"ahb_\",\n signal_map=signal_map,\n )\n\n # Determine bus parameters\n self.awidth = len(self.ahb_haddr)\n self.dwidth = len(self.ahb_hwdata) # Assuming hrdata is the same\n\n # Calculate HSIZE encoding\n self.hsize = {\n 64 // self.dwidth: 3,\n 128 // self.dwidth: 4,\n 256 // self.dwidth: 5,\n 512 // self.dwidth: 6,\n 1024 // self.dwidth: 7,\n }\n\n self.logger.debug(\"AHB Lite manager BFM:\")\n self.logger.debug(\" awidth = {}\".format(self.awidth))\n self.logger.debug(\" dwidth = {}\".format(self.dwidth))\n\n async def _wait(self, signal, max_cycles=200):\n \"\"\"\n Waits for a signal to be asserted for at most max_cycles.\n Raises an exception if it does not\n \"\"\"\n\n for i in range(max_cycles):\n await RisingEdge(self.ahb_hclk)\n if signal.value == 1:\n break\n else:\n raise TimeoutError(\"{} timeout\".format(str(signal)))\n\n async def write(self, addr, data):\n \"\"\"\n Issues a write transfer. Parameter data must be a list of integers\n where each one represents a full bus data word. The word count must be\n one of multiplies of data bus width supported by AHB Lite.\n \"\"\"\n\n lnt = len(data)\n assert lnt in self.hsize\n\n # Wait for reset deassertion if necessary\n if self.ahb_hreset.value == 0:\n await RisingEdge(self.ahb_hreset)\n\n # Address phase\n await RisingEdge(self.ahb_hclk)\n self.ahb_hsel.value = 1\n self.ahb_hprot.value = 1 # Indicates a data transfer\n self.ahb_hsize.value = self.hsize[lnt]\n self.ahb_haddr.value = addr\n self.ahb_hwrite.value = 1\n self.ahb_htrans.value = self.HTRANS.NONSEQ.value\n self.ahb_hburst.value = self.HBURST.SINGLE.value\n await self._wait(self.ahb_hreadyout)\n\n # Data phase\n for i, word in enumerate(data):\n if i != lnt - 1:\n addr += self.dwidth // 8\n self.ahb_haddr.value = addr\n self.ahb_htrans.value = self.HTRANS.SEQ.value\n else:\n self.ahb_htrans.value = self.HTRANS.IDLE.value\n\n self.ahb_hwdata.value = word\n await self._wait(self.ahb_hreadyout)\n\n async def read(self, addr, length):\n \"\"\"\n Issues an AHB read transfer for the given number of bus data words. The\n word count must be one of multiplies of data bus width supported by AHB\n Lite.\n \"\"\"\n\n assert length in self.hsize\n\n # Wait for reset deassertion if necessary\n if self.ahb_hreset.value == 0:\n await RisingEdge(self.ahb_hreset)\n\n # Address phase\n await RisingEdge(self.ahb_hclk)\n self.ahb_hsel.value = 1\n self.ahb_hprot.value = 1 # Data\n self.ahb_hsize.value = self.hsize[length]\n self.ahb_haddr.value = addr\n self.ahb_hwrite.value = 0\n self.ahb_htrans.value = self.HTRANS.NONSEQ.value\n self.ahb_hburst.value = self.HBURST.SINGLE.value\n await self._wait(self.ahb_hreadyout)\n\n # Data phase\n for i in range(length):\n if i != length - 1:\n addr += self.dwidth // 8\n self.ahb_haddr.value = addr\n self.ahb_htrans.value = self.HTRANS.SEQ.value\n else:\n self.ahb_htrans.value = self.HTRANS.IDLE.value\n\n await self._wait(self.ahb_hreadyout)\n\n\nclass AHBLiteManagerDriver(uvm_driver):\n \"\"\"\n A driver for AHB Lite BFM\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.bfm = kwargs[\"bfm\"]\n del kwargs[\"bfm\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, BusWriteItem):\n await self.bfm.write(it.addr, it.data)\n\n elif isinstance(it, BusReadItem):\n # TODO: Since the intended UUT does not support burst transfers\n # here we are reading only a single data word.\n await self.bfm.read(it.addr, 1)\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass AHBLiteMonitor(uvm_component):\n \"\"\"\n AHB Lite bus monitor\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.bfm = kwargs[\"bfm\"]\n del kwargs[\"bfm\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def watch(self):\n \"\"\"\n Watches the bus\n \"\"\"\n\n data_stage = False\n\n hdata = bytearray()\n haddr = None\n htrans = None\n hwrite = None\n\n await RisingEdge(self.bfm.ahb_hreset)\n while True:\n # Wait for reset deassertion if necessary\n if self.bfm.ahb_hreset.value == 0:\n await RisingEdge(self.bfm.ahb_hreset)\n\n # Wait for clock edge and hready\n await RisingEdge(self.bfm.ahb_hclk)\n hready = int(self.bfm.ahb_hreadyout)\n\n if hready:\n # Sample data\n if data_stage:\n if htrans in [AHBLiteManagerBFM.HTRANS.SEQ, AHBLiteManagerBFM.HTRANS.NONSEQ]:\n if hwrite:\n data = collect_bytes(self.bfm.ahb_hwdata)\n else:\n data = collect_bytes(self.bfm.ahb_hrdata)\n hdata += data\n\n # Transfer end\n elif htrans == AHBLiteManagerBFM.HTRANS.IDLE:\n self.logger.debug(\n \"{}: 0x{:08X} {}\".format(\n \"WR\" if hwrite else \"RD\",\n haddr,\n [\"0x{:02X}\".format(b) for b in hdata],\n )\n )\n\n data_stage = False\n\n # Send response\n if hwrite:\n cls = BusWriteItem\n else:\n cls = BusReadItem\n\n self.ap.write(cls(haddr, hdata))\n\n # Sample bus signals\n htrans = AHBLiteManagerBFM.HTRANS(self.bfm.ahb_htrans.value)\n if not data_stage:\n if htrans in [AHBLiteManagerBFM.HTRANS.SEQ, AHBLiteManagerBFM.HTRANS.NONSEQ]:\n hwrite = int(self.bfm.ahb_hwrite.value)\n haddr = int(self.bfm.ahb_haddr.value)\n hdata = bytearray()\n data_stage = True\n\n async def run_phase(self):\n cocotb.start_soon(self.watch())\n\n\n# ==============================================================================\n\n\nclass AXI4LiteSubordinateBFM(uvm_component):\n \"\"\"\n AXI 4 Lite subordinate BFM. Allows low-level per-channel acknowledgement\n control.\n \"\"\"\n\n SIGNALS = [\n \"clk\",\n \"rst\",\n \"awvalid\",\n \"awready\",\n \"awid\",\n \"awaddr\",\n \"awsize\",\n \"wvalid\",\n \"wready\",\n \"wdata\",\n \"wstrb\",\n \"bvalid\",\n \"bready\",\n \"bresp\",\n \"bid\",\n \"arvalid\",\n \"arready\",\n \"arid\",\n \"araddr\",\n \"arsize\",\n \"rvalid\",\n \"rready\",\n \"rid\",\n \"rdata\",\n \"rresp\",\n ]\n\n def __init__(self, name, parent, uut, signal_prefix=\"\", signal_map=None):\n super().__init__(name, parent)\n\n # Collect signals\n collect_signals(\n self.SIGNALS,\n uut,\n self,\n uut_prefix=signal_prefix,\n obj_prefix=\"axi_\",\n signal_map=signal_map,\n )\n\n # Determine bus parameters\n self.awidth = len(self.axi_awaddr)\n self.dwidth = len(self.axi_wdata)\n self.swidth = len(self.axi_wstrb)\n\n assert self.swidth == (self.dwidth // 8)\n\n self.logger.debug(\"AXI4 Lite BFM:\")\n self.logger.debug(\" awidth = {}\".format(self.awidth))\n self.logger.debug(\" dwidth = {}\".format(self.dwidth))\n self.logger.debug(\" swidth = {}\".format(self.swidth))\n\n self.axi_awready.value = 0\n self.axi_wready.value = 0\n self.axi_arready.value = 0\n self.axi_rvalid.value = 0\n\n async def _wait(self, signal, max_cycles=200):\n \"\"\"\n Waits for a signal to be asserted for at most max_cycles.\n Raises an exception if it does not\n \"\"\"\n\n for i in range(max_cycles):\n await RisingEdge(self.axi_clk)\n if signal.value != 0:\n break\n else:\n raise TimeoutError(\"{} timeout\".format(str(signal)))\n\n async def set_ready(self, channel, ready):\n \"\"\"\n Sets/clears ready signal for the given channel on next clock edge\n \"\"\"\n assert channel in [\"aw\", \"w\", \"ar\", \"r\"], channel\n await RisingEdge(self.axi_clk)\n\n sig = \"axi_{}ready\".format(channel)\n sig = getattr(self, sig)\n sig.value = int(ready)\n\n async def respond_aw(self):\n self.axi_awready.value = 1\n await self._wait(self.axi_awvalid)\n\n self.axi_awready.value = 0\n\n async def respond_w(self):\n self.axi_wready.value = 1\n for i in range(1):\n await self._wait(self.axi_wvalid)\n\n self.axi_wready.value = 0\n\n async def respond_b(self):\n await self._wait(self.axi_bready)\n\n self.axi_bvalid.value = 1\n self.axi_bid.value = 0 # TODO: support providing different BID values\n self.axi_bresp.value = 0 # TODO: support providing different BRESP values\n\n await RisingEdge(self.axi_clk)\n self.axi_bvalid.value = 0\n\n async def respond_ar(self):\n self.axi_arready.value = 1\n await self._wait(self.axi_arvalid)\n\n self.axi_arready.value = 0\n\n async def respond_r(self):\n await self._wait(self.axi_rready)\n\n self.axi_rvalid.value = 1\n self.axi_rdata.value = random.randrange(0, (1 << self.dwidth) - 1)\n\n await RisingEdge(self.axi_clk)\n self.axi_rvalid.value = 0\n\n\nclass AXI4LiteSubordinateDriver(uvm_driver):\n \"\"\"\n PyUVM driver for AXI 4 Lite subordinate BFM\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.bfm = kwargs[\"bfm\"]\n del kwargs[\"bfm\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n func_map = {\n \"aw\": self.bfm.respond_aw,\n \"w\": self.bfm.respond_w,\n \"b\": self.bfm.respond_b,\n \"ar\": self.bfm.respond_ar,\n \"r\": self.bfm.respond_r,\n }\n\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, AXI4LiteResponseItem):\n tasks = [cocotb.start_soon(func_map[c]()) for c in it.channels]\n await Combine(*tasks)\n\n elif isinstance(it, AXI4LiteReadyItem):\n tasks = [cocotb.start_soon(self.bfm.set_ready(c, it.ready)) for c in it.channels]\n await Combine(*tasks)\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\n# ==============================================================================\n\n\nclass Scoreboard(uvm_component):\n \"\"\"\n A scoreboard that compares AHB and AXI transfers and checks if they\n refer to the same address and contain the same data.\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.ahb_fifo = uvm_tlm_analysis_fifo(\"ahb_fifo\", self)\n self.ahb_port = uvm_get_port(\"ahb_port\", self)\n self.axi_fifo = uvm_tlm_analysis_fifo(\"axi_fifo\", self)\n self.axi_port = uvm_get_port(\"axi_port\", self)\n\n def connect_phase(self):\n self.ahb_port.connect(self.ahb_fifo.get_export)\n self.axi_port.connect(self.axi_fifo.get_export)\n\n def check_phase(self):\n # Check transactions\n while self.ahb_port.can_get() and self.axi_port.can_get():\n self.passed = True\n\n # Get items\n _, ahb_item = self.ahb_port.try_get()\n _, axi_item = self.axi_port.try_get()\n\n # Check\n msg = \"AHB: {} A:0x{:08X} D:[{}], \".format(\n type(ahb_item).__name__,\n ahb_item.addr,\n \",\".join([\"0x{:02X}\".format(d) for d in ahb_item.data]),\n )\n\n msg += \"AXI: {} A:0x{:08X} D:[{}]\".format(\n type(ahb_item).__name__,\n axi_item.addr,\n \",\".join([\"0x{:02X}\".format(d) for d in axi_item.data]),\n )\n\n if ahb_item.addr != axi_item.addr or ahb_item.data != axi_item.data:\n self.logger.error(msg)\n self.passed = False\n else:\n self.logger.debug(msg)\n\n # Indicate an error if there is any leftover transaction in any of the\n # queues.\n if self.ahb_port.can_get() or self.axi_port.can_get():\n self.logger.error(\"Spurious transaction(s) on one of the buses\")\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 50)\n ConfigDB().set(None, \"*\", \"TEST_BURST_LEN\", 10)\n ConfigDB().set(None, \"*\", \"TEST_BURST_GAP\", 10)\n\n # Sequencers\n self.ahb_seqr = uvm_sequencer(\"ahb_seqr\", self)\n self.axi_seqr = uvm_sequencer(\"axi_seqr\", self)\n\n ConfigDB().set(None, \"*\", \"AHB_SEQR\", self.ahb_seqr)\n ConfigDB().set(None, \"*\", \"AXI_SEQR\", self.axi_seqr)\n\n # BFM\n self.ahb_bfm = AHBLiteManagerBFM(\n \"ahb_bfm\",\n self,\n uut=cocotb.top,\n signal_prefix=\"ahb_\",\n signal_map={\n \"hclk\": \"clk\",\n \"hreset\": \"rst_l\",\n },\n )\n\n self.axi_bfm = AXI4LiteSubordinateBFM(\n \"axi_bfm\",\n self,\n uut=cocotb.top,\n signal_prefix=\"axi_\",\n signal_map={\n \"clk\": \"clk\",\n \"rst\": \"rst_l\",\n },\n )\n\n # Driver\n self.ahb_drv = AHBLiteManagerDriver(\"ahb_drv\", self, bfm=self.ahb_bfm)\n self.axi_drv = AXI4LiteSubordinateDriver(\"axi_drv\", self, bfm=self.axi_bfm)\n\n # Monitor\n self.ahb_mon = AHBLiteMonitor(\"ahb_mon\", self, bfm=self.ahb_bfm)\n self.axi_mon = Axi4LiteMonitor(\"axi_mon\", self, bfm=self.axi_bfm)\n\n # Scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.ahb_drv.seq_item_port.connect(self.ahb_seqr.seq_item_export)\n self.axi_drv.seq_item_port.connect(self.axi_seqr.seq_item_export)\n\n self.ahb_mon.ap.connect(self.scoreboard.ahb_fifo.analysis_export)\n self.axi_mon.ap.connect(self.scoreboard.axi_fifo.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n\n cocotb.top.scan_mode.value = 0\n cocotb.top.clk_override.value = 0\n cocotb.top.axi_awready.value = 0\n cocotb.top.axi_wready.value = 0\n cocotb.top.axi_bvalid.value = 0\n cocotb.top.axi_bresp.value = 0\n cocotb.top.axi_bid.value = 0\n cocotb.top.axi_arready.value = 0\n cocotb.top.axi_rvalid.value = 0\n cocotb.top.axi_rid.value = 0\n cocotb.top.axi_rdata.value = 0\n cocotb.top.axi_rresp.value = 0\n cocotb.top.ahb_haddr.value = 0\n cocotb.top.ahb_hburst.value = 0\n cocotb.top.ahb_hmastlock.value = 0\n cocotb.top.ahb_hprot.value = 0\n cocotb.top.ahb_hsize.value = 0\n cocotb.top.ahb_htrans.value = 0\n cocotb.top.ahb_hwrite.value = 0\n cocotb.top.ahb_hwdata.value = 0\n cocotb.top.ahb_hsel.value = 0\n\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Set common DUT signals\n cocotb.top.bus_clk_en.value = 1\n cocotb.top.ahb_hreadyin.value = 1\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/lib_ahb_to_axi4/ucli.key", "content": "" }, { "path": "verification/block/lib_axi4_to_ahb/Makefile", "content": "\nnull :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = axi4_to_ahb\nCM_FILE = cm.cfg\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/lib/axi4_to_ahb.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/lib_axi4_to_ahb/ahb_lite_agent.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport cocotb\nfrom ahb_lite_bfm import AHBLiteBFM\nfrom cocotb.queue import QueueEmpty\nfrom cocotb.triggers import RisingEdge\nfrom pyuvm import ConfigDB, uvm_agent, uvm_analysis_port, uvm_driver, uvm_sequencer\n\nfrom common import BaseMonitor, get_int\n\n\nclass AHBLiteAgent(uvm_agent):\n \"\"\"\n Seqr <---> Driver\n Monitor <--^\n \"\"\"\n\n def build_phase(self):\n self.seqr = uvm_sequencer(\"seqr\", self)\n ConfigDB().set(None, \"*\", \"ahb_seqr\", self.seqr)\n self.monitor = AHBLiteMonitor(\"axi_w_agent\", self)\n self.driver = AHBLiteDriver(\"axi_w_driver\", self)\n\n def connect_phase(self):\n self.driver.seq_item_port.connect(self.seqr.seq_item_export)\n\n\nclass AHBLiteDriver(uvm_driver):\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n self.rst_n = cocotb.top.rst_l\n self.clk = cocotb.top.clk\n\n def start_of_simulation_phase(self):\n self.bfm = AHBLiteBFM()\n\n async def run_phase(self):\n self.bfm.start_bfm()\n while True:\n if get_int(self.rst_n) == 0:\n await RisingEdge(self.rst_n)\n self.logger.info(\"Agent: AHB Lite: Reset Posedge\")\n\n await RisingEdge(self.clk)\n try:\n response = self.bfm.rsp_driver_q.get_nowait()\n self.seq_item_port.put_response(response)\n # Expect two items per one response (hready is asserted for 2 cycles)\n for _ in range(2):\n item = await self.seq_item_port.get_next_item()\n await self.drive(item)\n self.logger.debug(f\"Driven: {item}\")\n self.seq_item_port.item_done()\n except QueueEmpty:\n pass\n\n async def drive(self, item):\n await self.bfm.req_driver_q_put(\n item.ahb_hrdata,\n item.ahb_hready,\n item.ahb_hresp,\n )\n\n\nclass AHBLiteMonitor(BaseMonitor):\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n def build_phase(self):\n super().build_phase()\n self.bfm = AHBLiteBFM()\n" }, { "path": "verification/block/lib_axi4_to_ahb/ahb_lite_bfm.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport cocotb\nfrom ahb_lite_pkg import (\n AHB_LITE_NOTIFICATION,\n AHB_LITE_RESPONSE_CODES,\n AHB_LITE_TRANSFER_TYPE_ENCODING,\n AHB_RSP_SIGNALS,\n)\nfrom cocotb.queue import QueueEmpty\nfrom cocotb.triggers import RisingEdge\nfrom pyuvm import UVMQueue, utility_classes\n\nfrom common import get_int, get_signals\n\n\nclass AHBLiteBFM(metaclass=utility_classes.Singleton):\n def __init__(self):\n self.dut = cocotb.top\n self.rst_n = cocotb.top.rst_l\n self.clk = cocotb.top.clk\n self.req_driver_q = UVMQueue(maxsize=1)\n self.rsp_driver_q = UVMQueue()\n self.req_monitor_q = UVMQueue()\n self.rsp_monitor_q = UVMQueue()\n\n async def req_driver_q_put(self, ahb_hrdata, ahb_hready, ahb_hresp):\n item = (ahb_hrdata, ahb_hready, ahb_hresp)\n await self.req_driver_q.put(item)\n\n async def req_monitor_q_get(self):\n item = await self.req_monitor_q.get()\n return item\n\n async def rsp_monitor_q_get(self):\n result = await self.rsp_monitor_q.get()\n return result\n\n async def drive(self):\n prev_htrans = AHB_LITE_TRANSFER_TYPE_ENCODING.IDLE\n htrans = AHB_LITE_TRANSFER_TYPE_ENCODING.IDLE\n\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n self.dut.ahb_hrdata.value = 0\n self.dut.ahb_hready.value = 0\n self.dut.ahb_hresp.value = 0\n await RisingEdge(self.rst_n)\n await RisingEdge(self.clk)\n\n prev_htrans = htrans\n if get_int(self.dut.ahb_htrans) == AHB_LITE_TRANSFER_TYPE_ENCODING.IDLE:\n htrans = AHB_LITE_TRANSFER_TYPE_ENCODING.IDLE\n self.dut.ahb_hrdata.value = 0\n self.dut.ahb_hready.value = 0\n self.dut.ahb_hresp.value = AHB_LITE_RESPONSE_CODES.OKAY\n elif get_int(self.dut.ahb_htrans) == AHB_LITE_TRANSFER_TYPE_ENCODING.NONSEQ:\n htrans = AHB_LITE_TRANSFER_TYPE_ENCODING.NONSEQ\n if get_int(self.dut.ahb_hwrite):\n if htrans != prev_htrans:\n self.rsp_driver_q.put_nowait(AHB_LITE_NOTIFICATION.AHB_LITE_WRITE)\n else:\n if htrans != prev_htrans:\n self.rsp_driver_q.put_nowait(AHB_LITE_NOTIFICATION.AHB_LITE_READ)\n\n try:\n ahb_hrdata, ahb_hready, ahb_hresp = self.req_driver_q.get_nowait()\n self.dut.ahb_hrdata.value = ahb_hrdata\n self.dut.ahb_hready.value = ahb_hready\n self.dut.ahb_hresp.value = ahb_hresp\n except QueueEmpty:\n self.dut.ahb_hrdata.value = 0\n self.dut.ahb_hready.value = 0\n self.dut.ahb_hresp.value = 0\n\n async def req_monitor_q_bfm(self):\n while True:\n await RisingEdge(self.clk)\n if get_int(self.dut.ahb_hready):\n item = (\n get_int(self.dut.ahb_hrdata),\n get_int(self.dut.ahb_hready),\n get_int(self.dut.ahb_hresp),\n )\n await self.req_monitor_q.put(item)\n\n async def rsp_monitor_q_bfm(self):\n while True:\n await RisingEdge(self.clk)\n if get_int(self.dut.ahb_hready):\n sigs = get_signals(AHB_RSP_SIGNALS, self.dut)\n values = tuple(sig.value for sig in sigs)\n await self.rsp_monitor_q.put(values)\n\n def start_bfm(self):\n cocotb.start_soon(self.drive())\n cocotb.start_soon(self.req_monitor_q_bfm())\n cocotb.start_soon(self.rsp_monitor_q_bfm())\n" }, { "path": "verification/block/lib_axi4_to_ahb/ahb_lite_pkg.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\n\nfrom enum import IntEnum\n\nAHB_DRV_SIGNALS = [\n \"ahb_hrdata\",\n \"ahb_hready\",\n \"ahb_hresp\",\n]\n\nAHB_RSP_SIGNALS = [\n \"ahb_haddr\",\n \"ahb_hburst\",\n \"ahb_hmastlock\",\n \"ahb_hprot\",\n \"ahb_hsize\",\n \"ahb_htrans\",\n \"ahb_hwrite\",\n \"ahb_hwdata\",\n]\n\n\nclass AHB_LITE_RESPONSE_CODES(IntEnum):\n OKAY = 0\n\n\nclass AHB_LITE_TRANSFER_TYPE_ENCODING(IntEnum):\n IDLE = 0\n BUSY = 1\n NONSEQ = 2\n SEQ = 3\n\n\nclass AHB_LITE_NOTIFICATION(IntEnum):\n AHB_LITE_WRITE = 1\n AHB_LITE_READ = 2\n AHB_LITE_IDLE = 3\n" }, { "path": "verification/block/lib_axi4_to_ahb/ahb_lite_seq.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport random\n\nfrom ahb_lite_pkg import AHB_LITE_RESPONSE_CODES\nfrom pyuvm import uvm_sequence_item\n\nfrom common import BaseSeq\n\n\nclass AHBLiteBaseSeqItem(uvm_sequence_item):\n def __init__(self, name):\n super().__init__(name)\n self.ahb_hrdata = 0\n self.ahb_hready = 0\n self.ahb_hresp = 0\n\n def randomize(self):\n pass\n\n def __eq__(self, other):\n pass\n\n def __str__(self):\n return self.__class__.__name__\n\n\nclass AHBLiteInactiveSeqItem(AHBLiteBaseSeqItem):\n def __init__(self, name):\n super().__init__(name)\n\n\nclass AHBLiteReadyReadSeqItem(AHBLiteBaseSeqItem):\n def __init__(self, name):\n super().__init__(name)\n self.ahb_hready = 1\n self.ahb_hresp = AHB_LITE_RESPONSE_CODES.OKAY\n\n def randomize(self):\n self.ahb_hrdata = random.randint(0, 255)\n\n\nclass AHBLiteReadyWriteSeqItem(AHBLiteBaseSeqItem):\n def __init__(self, name):\n super().__init__(name)\n self.ahb_hready = 1\n self.ahb_hresp = AHB_LITE_RESPONSE_CODES.OKAY\n\n\nclass AHBLiteReadyNoDataSeqItem(AHBLiteBaseSeqItem):\n def __init__(self, name):\n super().__init__(name)\n self.ahb_hready = 1\n self.ahb_hresp = AHB_LITE_RESPONSE_CODES.OKAY\n\n\nclass AHBLiteAcceptWriteSeq(BaseSeq):\n async def body(self):\n items = [\n AHBLiteReadyNoDataSeqItem(\"AHBLiteReadyNoDataSeqItem\"),\n AHBLiteReadyWriteSeqItem(\"AHBLiteReadyWriteSeqItem\"),\n ]\n await self.run_items(items)\n\n\nclass AHBLiteAcceptReadSeq(BaseSeq):\n async def body(self):\n items = [\n AHBLiteReadyNoDataSeqItem(\"AHBLiteReadyNoDataSeqItem\"),\n AHBLiteReadyReadSeqItem(\"AHBLiteReadyReadSeqItem\"),\n ]\n await self.run_items(items)\n" }, { "path": "verification/block/lib_axi4_to_ahb/axi_pkg.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nfrom enum import IntEnum\n\nAXI_W_CHAN_DRV_SIGNALS = [\n \"axi_awvalid\",\n \"axi_awid\",\n \"axi_awaddr\",\n \"axi_awsize\",\n \"axi_awprot\",\n \"axi_wvalid\",\n \"axi_wdata\",\n \"axi_wstrb\",\n \"axi_wlast\",\n \"axi_bready\",\n]\n\nAXI_W_CHAN_RSP_SIGNALS = [\n \"axi_awready\",\n \"axi_wready\",\n \"axi_bvalid\",\n \"axi_bresp\",\n \"axi_bid\",\n]\n\nAXI_W_CHAN_SIGNALS = AXI_W_CHAN_DRV_SIGNALS + AXI_W_CHAN_RSP_SIGNALS\n\nAXI_R_CHAN_DRV_SIGNALS = [\n \"axi_arvalid\",\n \"axi_arid\",\n \"axi_araddr\",\n \"axi_arsize\",\n \"axi_arprot\",\n \"axi_rready\",\n]\n\nAXI_R_CHAN_RSP_SIGNALS = [\n \"axi_arready\",\n \"axi_rvalid\",\n \"axi_rid\",\n \"axi_rdata\",\n \"axi_rresp\",\n \"axi_rlast\",\n]\n\nAXI_R_CHAN_SIGNALS = AXI_R_CHAN_DRV_SIGNALS + AXI_R_CHAN_RSP_SIGNALS\n\n\nclass AXI_WRITE_RESPONSE_CODES(IntEnum):\n OKAY = 0\n EXOKAY = 1\n SLVERR = 2\n DECERR = 3\n DEFER = 4\n TRANSFAULT = 5\n RESERVED = 6\n UNSUPPORTED = 7\n\n\nclass AXI_READ_RESPONSE_CODES(IntEnum):\n OKAY = 0\n EXOKAY = 1\n SLVERR = 2\n DECERR = 3\n PREFETCHED = 4\n TRANSFAULT = 5\n OKAYDIRTY = 6\n RESERVED = 7\n\n\nclass AXI_AXSIZE_ENCODING(IntEnum):\n MAX_1B_TRANSFER = 0\n MAX_2B_TRANSFER = 1\n MAX_4B_TRANSFER = 2\n MAX_8B_TRANSFER = 3\n MAX_16B_TRANSFER = 4\n MAX_32B_TRANSFER = 5\n MAX_64B_TRANSFER = 6\n MAX_128B_TRANSFER = 7\n\n\nclass AXI_NOTIFICATION(IntEnum):\n AXI_FREE = 1\n AXI_BUSY = 2\n AXI_AREAD_HANDSHAKE = 3\n AXI_READ_HANDSHAKE = 4\n" }, { "path": "verification/block/lib_axi4_to_ahb/axi_r_agent.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport random\n\nimport cocotb\nimport pyuvm\nfrom axi_r_bfm import AXIReadChannelBFM\nfrom cocotb.queue import QueueEmpty\nfrom cocotb.triggers import RisingEdge\nfrom pyuvm import ConfigDB, uvm_agent, uvm_analysis_port, uvm_driver, uvm_sequencer\n\nfrom common import BaseMonitor\n\n\nclass AXIReadChannelAgent(uvm_agent):\n def build_phase(self):\n self.seqr = uvm_sequencer(\"seqr\", self)\n ConfigDB().set(None, \"*\", \"axi_r_seqr\", self.seqr)\n self.monitor = AXIReadChannelMonitor(\"axi_r_agent\", self)\n self.driver = AXIReadChannelDriver(\"axi_r_driver\", self)\n\n def connect_phase(self):\n self.driver.seq_item_port.connect(self.seqr.seq_item_export)\n\n\nclass AXIReadChannelDriver(uvm_driver):\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n self.rst_n = cocotb.top.rst_l\n self.clk = cocotb.top.clk\n\n def start_of_simulation_phase(self):\n self.bfm = AXIReadChannelBFM()\n\n async def run_phase(self):\n self.bfm.start_bfm()\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n await RisingEdge(self.rst_n)\n self.logger.info(\"Agent: AXI Read: Reset Posedge\")\n\n try:\n pending = 1\n axi_notification = self.bfm.rsp_driver_q.get_nowait()\n except QueueEmpty:\n pending = 0\n\n if pending:\n self.seq_item_port.put_response(axi_notification)\n\n self.seq_item_port.put_response(3)\n try:\n item = await self.seq_item_port.get_next_item()\n await self.drive(item)\n self.logger.debug(f\"Agent: AXI Read: Driven: {item}\")\n self.seq_item_port.item_done()\n except QueueEmpty:\n pass\n\n async def drive(self, item):\n await self.bfm.req_driver_q_put(\n item.axi_arvalid,\n item.axi_arid,\n item.axi_araddr,\n item.axi_arsize,\n item.axi_arprot,\n item.axi_rready,\n )\n\n\nclass AXIReadChannelMonitor(BaseMonitor):\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n def build_phase(self):\n super().build_phase()\n self.bfm = AXIReadChannelBFM()\n" }, { "path": "verification/block/lib_axi4_to_ahb/axi_r_bfm.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport cocotb\nfrom axi_pkg import AXI_NOTIFICATION, AXI_R_CHAN_RSP_SIGNALS\nfrom cocotb.queue import QueueEmpty\nfrom cocotb.triggers import RisingEdge\nfrom pyuvm import UVMQueue, utility_classes, uvm_root\n\nfrom common import get_int, get_signals\n\n\nclass AXIReadChannelBFM(metaclass=utility_classes.Singleton):\n def __init__(self):\n self.dut = cocotb.top\n self.rst_n = cocotb.top.rst_l\n self.clk = cocotb.top.clk\n self.req_driver_q = UVMQueue(maxsize=1)\n self.rsp_driver_q = UVMQueue(maxsize=1)\n self.req_monitor_q = UVMQueue(maxsize=0)\n self.rsp_monitor_q = UVMQueue(maxsize=0)\n self.TIMEOUT_THRESHOLD = 20\n\n async def req_driver_q_put(\n self,\n axi_arvalid,\n axi_arid,\n axi_araddr,\n axi_arsize,\n axi_arprot,\n axi_rready,\n ):\n item = (\n axi_arvalid,\n axi_arid,\n axi_araddr,\n axi_arsize,\n axi_arprot,\n axi_rready,\n )\n await self.req_driver_q.put(item)\n\n async def req_monitor_q_get(self):\n item = await self.req_monitor_q.get()\n return item\n\n async def rsp_monitor_q_get(self):\n result = await self.rsp_monitor_q.get()\n return result\n\n async def drive(self):\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n self.dut.axi_arvalid.value = 0\n self.dut.axi_arid.value = 0\n self.dut.axi_araddr.value = 0\n self.dut.axi_arsize.value = 0\n self.dut.axi_arprot.value = 0\n self.dut.axi_rready.value = 0\n await RisingEdge(self.rst_n)\n await RisingEdge(self.clk)\n try:\n (\n axi_arvalid,\n axi_arid,\n axi_araddr,\n axi_arsize,\n axi_arprot,\n axi_rready,\n ) = self.req_driver_q.get_nowait()\n self.dut.axi_arvalid.value = axi_arvalid\n self.dut.axi_arid.value = axi_arid\n self.dut.axi_araddr.value = axi_araddr\n self.dut.axi_arsize.value = axi_arsize\n self.dut.axi_arprot.value = axi_arprot\n self.dut.axi_rready.value = axi_rready\n except QueueEmpty:\n pass\n\n # Handshake ARVALID <-> ARREADY\n if get_int(self.dut.axi_arvalid):\n timeout = 0\n while get_int(self.dut.axi_arready) == 0:\n timeout += 1\n self.rsp_driver_q.put_nowait(AXI_NOTIFICATION.AXI_BUSY)\n await RisingEdge(self.clk)\n if timeout > self.TIMEOUT_THRESHOLD:\n raise TimeoutError(\"Transaction Request Handshake Timeout: AXI Read\")\n\n async def req_monitor_q_bfm(self):\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n await RisingEdge(self.rst_n)\n await RisingEdge(self.clk)\n if get_int(self.dut.axi_arvalid):\n if get_int(self.dut.axi_arready):\n item = (\n get_int(self.dut.axi_arvalid),\n get_int(self.dut.axi_arid),\n get_int(self.dut.axi_araddr),\n get_int(self.dut.axi_arsize),\n get_int(self.dut.axi_arprot),\n get_int(self.dut.axi_rready),\n )\n await self.req_monitor_q.put(item)\n\n async def rsp_monitor_q_bfm(self):\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n await RisingEdge(self.rst_n)\n await RisingEdge(self.clk)\n if get_int(self.dut.axi_rvalid):\n if get_int(self.dut.axi_rready):\n sigs = get_signals(AXI_R_CHAN_RSP_SIGNALS, self.dut)\n values = tuple(sig.value for sig in sigs)\n await self.rsp_monitor_q.put(values)\n\n def start_bfm(self):\n cocotb.start_soon(self.drive())\n cocotb.start_soon(self.req_monitor_q_bfm())\n cocotb.start_soon(self.rsp_monitor_q_bfm())\n" }, { "path": "verification/block/lib_axi4_to_ahb/axi_r_seq.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport random\n\nfrom axi_pkg import AXI_AXSIZE_ENCODING\nfrom pyuvm import ConfigDB, uvm_sequence_item\n\nfrom common import BaseSeq\n\n\nclass AXIReadBaseSeqItem(uvm_sequence_item):\n def __init__(self, name):\n super().__init__(name)\n self.AXI_DATA_WIDTH = ConfigDB().get(None, \"\", \"AXI_DATA_WIDTH\")\n self.AXI_NUM_STRB_BITS = int(self.AXI_DATA_WIDTH / 8)\n\n self.axi_arvalid = 0\n self.axi_arid = 0\n self.axi_araddr = 0\n self.axi_arsize = int(AXI_AXSIZE_ENCODING.MAX_8B_TRANSFER)\n self.axi_arprot = 0\n self.axi_rready = 0\n\n def randomize(self):\n pass\n\n def __eq__(self, other):\n pass\n\n def __str__(self):\n return self.__class__.__name__\n\n\nclass AXIReadTransactionRequestSeqItem(AXIReadBaseSeqItem):\n def __init__(self, name):\n super().__init__(name)\n self.axi_arvalid = 1\n\n def randomize(self):\n self.axi_araddr = 8 * random.randint(0, 0x1FFFFFFF)\n\n\nclass AXIReadResponseReadSeqItem(AXIReadBaseSeqItem):\n def __init__(\n self,\n name,\n ):\n super().__init__(name)\n self.axi_rready = 1\n\n\nclass AXIReadInactiveSeqItem(AXIReadBaseSeqItem):\n def __init__(self, name):\n super().__init__(name)\n self.axi_arsize = 0\n\n\nclass AXIReadTransactionRequestSeq(BaseSeq):\n async def body(self):\n items = [\n AXIReadTransactionRequestSeqItem(\"AXIReadTransactionRequestSeqItem\"),\n AXIReadInactiveSeqItem(\"AXIReadInactiveSeqItem\"),\n ]\n await self.run_items(items)\n\n\nclass AXIReadTransactionResponseSeq(BaseSeq):\n async def body(self):\n items = [\n AXIReadResponseReadSeqItem(\"AXIReadLastDataSeqItem\"),\n AXIReadInactiveSeqItem(\"AXIReadInactiveSeqItem\"),\n ]\n await self.run_items(items)\n" }, { "path": "verification/block/lib_axi4_to_ahb/axi_w_agent.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport cocotb\nfrom axi_w_bfm import AXIWriteChannelBFM\nfrom axi_w_seq import (\n AXIWriteInactiveSeqItem,\n AXIWriteLastDataSeqItem,\n AXIWriteResponseWriteSeqItem,\n AXIWriteTransactionRequestSeqItem,\n)\nfrom cocotb.queue import QueueEmpty\nfrom cocotb.triggers import RisingEdge\nfrom pyuvm import ConfigDB, uvm_agent, uvm_driver, uvm_sequencer\n\nfrom common import BaseMonitor\n\n\nclass AXIWriteChannelAgent(uvm_agent):\n \"\"\"\n Seqr <---> Driver\n Monitor <--^\n \"\"\"\n\n def build_phase(self):\n self.seqr = uvm_sequencer(\"seqr\", self)\n ConfigDB().set(None, \"*\", \"axi_w_seqr\", self.seqr)\n self.monitor = AXIWriteChannelMonitor(\"axi_w_agent\", self)\n self.driver = AXIWriteChannelDriver(\"axi_w_driver\", self)\n\n def connect_phase(self):\n self.driver.seq_item_port.connect(self.seqr.seq_item_export)\n\n\nclass AXIWriteChannelDriver(uvm_driver):\n def build_phase(self):\n self.rst_n = cocotb.top.rst_l\n\n def start_of_simulation_phase(self):\n self.bfm = AXIWriteChannelBFM()\n\n async def run_phase(self):\n self.bfm.start_bfm()\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n await RisingEdge(self.rst_n)\n self.logger.info(\"Agent: AXI Write: Reset Posedge\")\n\n try:\n item = await self.seq_item_port.get_next_item()\n except QueueEmpty:\n pass\n\n if isinstance(item, AXIWriteInactiveSeqItem):\n await self.drive(item)\n self.logger.debug(f\"Driven: {item}\")\n self.seq_item_port.item_done()\n\n if isinstance(item, AXIWriteTransactionRequestSeqItem):\n await self.drive(item)\n self.logger.debug(f\"Driven: {item}\")\n await self.wait_handshake(sig_name=\"axi_awready\")\n self.seq_item_port.item_done()\n\n if isinstance(item, AXIWriteLastDataSeqItem):\n await self.drive(item)\n self.logger.debug(f\"Driven: {item}\")\n await self.wait_handshake(sig_name=\"axi_wready\")\n self.seq_item_port.item_done()\n\n if isinstance(item, AXIWriteResponseWriteSeqItem):\n await self.drive(item)\n await self.wait_handshake(sig_name=\"axi_bvalid\")\n self.logger.debug(f\"Driven: {item}\")\n self.seq_item_port.item_done()\n\n async def wait_handshake(self, sig_name=None, TIMEOUT_THRESHOLD=30):\n timeout = 0\n while True:\n timeout += 1\n await RisingEdge(self.bfm.clk)\n sig_handle = getattr(self.bfm.dut, sig_name)\n if sig_handle.value:\n break\n\n if timeout > TIMEOUT_THRESHOLD:\n raise TimeoutError(f\"Transaction Request Handshake Timeout: AXI Write: {sig_name}\")\n\n async def drive(self, item):\n await self.bfm.req_driver_q_put(\n item.axi_awvalid,\n item.axi_awid,\n item.axi_awaddr,\n item.axi_awsize,\n item.axi_awprot,\n item.axi_wvalid,\n item.axi_wdata,\n item.axi_wstrb,\n item.axi_wlast,\n item.axi_bready,\n )\n\n\nclass AXIWriteChannelMonitor(BaseMonitor):\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n def build_phase(self):\n super().build_phase()\n self.bfm = AXIWriteChannelBFM()\n" }, { "path": "verification/block/lib_axi4_to_ahb/axi_w_bfm.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport cocotb\nfrom axi_pkg import AXI_W_CHAN_RSP_SIGNALS\nfrom cocotb.queue import QueueEmpty\nfrom cocotb.triggers import RisingEdge\nfrom pyuvm import UVMQueue, utility_classes, uvm_root\n\nfrom common import get_int, get_signals\n\n\nclass AXIWriteChannelBFM(metaclass=utility_classes.Singleton):\n def __init__(self):\n self.dut = cocotb.top\n self.rst_n = cocotb.top.rst_l\n self.clk = cocotb.top.clk\n self.req_driver_q = UVMQueue(maxsize=1)\n self.req_monitor_q = UVMQueue()\n self.rsp_monitor_q = UVMQueue()\n\n async def req_driver_q_put(\n self,\n axi_awvalid,\n axi_awid,\n axi_awaddr,\n axi_awsize,\n axi_awprot,\n axi_wvalid,\n axi_wdata,\n axi_wstrb,\n axi_wlast,\n axi_bready,\n ):\n item = (\n axi_awvalid,\n axi_awid,\n axi_awaddr,\n axi_awsize,\n axi_awprot,\n axi_wvalid,\n axi_wdata,\n axi_wstrb,\n axi_wlast,\n axi_bready,\n )\n await self.req_driver_q.put(item)\n\n async def req_monitor_q_get(self):\n item = await self.req_monitor_q.get()\n return item\n\n async def rsp_monitor_q_get(self):\n result = await self.rsp_monitor_q.get()\n return result\n\n async def drive(self):\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n self.dut.axi_awvalid.value = 0\n self.dut.axi_awid.value = 0\n self.dut.axi_awaddr.value = 0\n self.dut.axi_awsize.value = 0\n self.dut.axi_awprot.value = 0\n self.dut.axi_wvalid.value = 0\n self.dut.axi_wdata.value = 0\n self.dut.axi_wstrb.value = 0\n self.dut.axi_wlast.value = 0\n self.dut.axi_bready.value = 0\n await RisingEdge(self.rst_n)\n await RisingEdge(self.clk)\n try:\n (\n axi_awvalid,\n axi_awid,\n axi_awaddr,\n axi_awsize,\n axi_awprot,\n axi_wvalid,\n axi_wdata,\n axi_wstrb,\n axi_wlast,\n axi_bready,\n ) = self.req_driver_q.get_nowait()\n self.dut.axi_awvalid.value = axi_awvalid\n self.dut.axi_awid.value = axi_awid\n self.dut.axi_awaddr.value = axi_awaddr\n self.dut.axi_awsize.value = axi_awsize\n self.dut.axi_awprot.value = axi_awprot\n self.dut.axi_wvalid.value = axi_wvalid\n self.dut.axi_wdata.value = axi_wdata\n self.dut.axi_wstrb.value = axi_wstrb\n self.dut.axi_wlast.value = axi_wlast\n self.dut.axi_bready.value = axi_bready\n except QueueEmpty:\n pass\n\n async def req_monitor_q_bfm(self):\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n await RisingEdge(self.rst_n)\n await RisingEdge(self.clk)\n send_item = 0\n if get_int(self.dut.axi_awvalid):\n if get_int(self.dut.axi_awready):\n send_item = 1\n\n if get_int(self.dut.axi_wvalid):\n if get_int(self.dut.axi_wready):\n send_item = 1\n\n if send_item:\n item = (\n get_int(self.dut.axi_awvalid),\n get_int(self.dut.axi_awid),\n get_int(self.dut.axi_awaddr),\n get_int(self.dut.axi_awsize),\n get_int(self.dut.axi_awprot),\n get_int(self.dut.axi_wvalid),\n get_int(self.dut.axi_wdata),\n get_int(self.dut.axi_wstrb),\n get_int(self.dut.axi_wlast),\n get_int(self.dut.axi_bready),\n )\n await self.req_monitor_q.put(item)\n\n async def rsp_monitor_q_bfm(self):\n await RisingEdge(self.rst_n)\n while True:\n if self.rst_n.value == 0:\n await RisingEdge(self.rst_n)\n await RisingEdge(self.clk)\n if get_int(self.dut.axi_bvalid):\n if get_int(self.dut.axi_bready):\n sigs = get_signals(AXI_W_CHAN_RSP_SIGNALS, self.dut)\n values = tuple(sig.value for sig in sigs)\n await self.rsp_monitor_q.put(values)\n\n def start_bfm(self):\n cocotb.start_soon(self.drive())\n cocotb.start_soon(self.req_monitor_q_bfm())\n cocotb.start_soon(self.rsp_monitor_q_bfm())\n" }, { "path": "verification/block/lib_axi4_to_ahb/axi_w_seq.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport random\n\nfrom axi_pkg import AXI_AXSIZE_ENCODING\nfrom cocotb.types import LogicArray\nfrom pyuvm import ConfigDB, uvm_sequence_item\n\nfrom common import BaseSeq\n\n\nclass AXIWriteBaseSeqItem(uvm_sequence_item):\n def __init__(self, name):\n super().__init__(name)\n self.AXI_DATA_WIDTH = ConfigDB().get(None, \"\", \"AXI_DATA_WIDTH\")\n self.AXI_NUM_STRB_BITS = int(self.AXI_DATA_WIDTH / 8)\n\n self.axi_awvalid = 0\n self.axi_awid = 0\n self.axi_awaddr = 0\n self.axi_awsize = int(AXI_AXSIZE_ENCODING.MAX_8B_TRANSFER)\n self.axi_awprot = 0\n self.axi_wvalid = 0\n self.axi_wdata = 0\n self.axi_wstrb = LogicArray(\"1\" * self.AXI_NUM_STRB_BITS)\n self.axi_wlast = 0\n self.axi_bready = 0\n\n def randomize(self):\n pass\n\n def __eq__(self, other):\n pass\n\n def __str__(self):\n return self.__class__.__name__\n\n\nclass AXIWriteTransactionRequestSeqItem(AXIWriteBaseSeqItem):\n def __init__(self, name):\n super().__init__(name)\n self.axi_awvalid = 1\n\n def randomize(self):\n self.axi_awid = random.randint(0, 1)\n self.axi_awaddr = 8 * random.randint(0, 0x1FFFFFFF)\n\n\nclass AXIWriteDataSeqItem(AXIWriteBaseSeqItem):\n def __init__(self, name):\n super().__init__(name)\n self.axi_wvalid = 1\n self.axi_wstrb = LogicArray(\"1\" * self.AXI_NUM_STRB_BITS)\n\n def randomize(self):\n self.axi_wdata = random.randint(0, 0xFFFFFFFFFFFFFFFF)\n\n\nclass AXIWriteLastDataSeqItem(AXIWriteDataSeqItem):\n def __init__(self, name):\n super().__init__(name)\n self.axi_wlast = 1\n\n\nclass AXIWriteResponseWriteSeqItem(AXIWriteBaseSeqItem):\n def __init__(\n self,\n name,\n ):\n super().__init__(name)\n self.axi_bready = 1\n\n\nclass AXIWriteInactiveSeqItem(AXIWriteBaseSeqItem):\n def __init__(self, name):\n super().__init__(name)\n self.axi_awsize = 0\n self.axi_wstrb = 0\n\n\nclass AXIWriteTransactionRequestSeq(BaseSeq):\n async def body(self):\n items = [\n AXIWriteInactiveSeqItem(\"AXIWriteInactiveSeqItem\"),\n AXIWriteTransactionRequestSeqItem(\"AXIWriteTransactionRequestSeqItem\"),\n AXIWriteInactiveSeqItem(\"AXIWriteInactiveSeqItem\"),\n ]\n await self.run_items(items)\n\n\nclass AXIWriteDataSeq(BaseSeq):\n async def body(self):\n items = [\n AXIWriteInactiveSeqItem(\"AXIWriteInactiveSeqItem\"),\n AXIWriteLastDataSeqItem(\"AXIWriteLastDataSeqItem\"),\n AXIWriteInactiveSeqItem(\"AXIWriteInactiveSeqItem\"),\n ]\n await self.run_items(items)\n\n\nclass AXIWriteResponseSeq(BaseSeq):\n async def body(self):\n items = [\n AXIWriteInactiveSeqItem(\"AXIWriteInactiveSeqItem\"),\n AXIWriteResponseWriteSeqItem(\"AXIWriteLastDataSeqItem\"),\n AXIWriteInactiveSeqItem(\"AXIWriteInactiveSeqItem\"),\n ]\n await self.run_items(items)\n" }, { "path": "verification/block/lib_axi4_to_ahb/cm.cfg", "content": "+tree *\n\n-node axi4_to_ahb.ahb_hprot[3:1] // Tied to 3'001\n" }, { "path": "verification/block/lib_axi4_to_ahb/common.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport logging\n\nimport cocotb\nfrom pyuvm import uvm_analysis_port, uvm_component, uvm_sequence\n\n\ndef collect_signals(signals, uut, obj):\n \"\"\"\n Collects signal objects from UUT and attaches them to the given object\n \"\"\"\n\n for sig in signals:\n if hasattr(uut, sig):\n s = getattr(uut, sig)\n\n else:\n s = None\n logging.error(\"Module {} does not have a signal '{}'\".format(str(uut), sig))\n\n setattr(obj, sig, s)\n\n\ndef get_int(signal):\n try:\n sig = int(signal.value)\n except ValueError:\n sig = 0\n return sig\n\n\ndef get_signals(signals, obj):\n \"\"\"\n Returns signal objects attached to object.\n It is presumed that \"signals\" is a list of strings.\n \"\"\"\n attrs = []\n for sig in signals:\n if hasattr(obj, sig):\n attrs.append(getattr(obj, sig))\n else:\n raise Exception(f\"Module {obj} does not have a signal {sig}\")\n return attrs\n\n\nclass BaseSeq(uvm_sequence):\n async def run_items(self, items):\n for item in items:\n await self.start_item(item)\n item.randomize()\n await self.finish_item(item)\n\n\nclass BaseMonitor(uvm_component):\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n def build_phase(self):\n self.ap_req = uvm_analysis_port(\"ap_req\", self)\n self.ap_rsp = uvm_analysis_port(\"ap_rsp\", self)\n self.bfm = None\n\n async def monitor_req(self):\n while True:\n datum = await self.bfm.req_monitor_q_get()\n self.logger.debug(f\"monitor_req: {datum}\")\n self.ap_req.write(datum)\n\n async def monitor_rsp(self):\n while True:\n datum = await self.bfm.rsp_monitor_q_get()\n self.logger.debug(f\"monitor_rsp: {datum}\")\n self.ap_rsp.write(datum)\n\n async def run_phase(self):\n cocotb.start_soon(self.monitor_req())\n cocotb.start_soon(self.monitor_rsp())\n" }, { "path": "verification/block/lib_axi4_to_ahb/coordinator_seq.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport random\n\nimport cocotb\nfrom ahb_lite_pkg import AHB_LITE_NOTIFICATION\nfrom ahb_lite_seq import AHBLiteAcceptReadSeq, AHBLiteAcceptWriteSeq\nfrom axi_r_seq import AXIReadTransactionRequestSeq, AXIReadTransactionResponseSeq\nfrom axi_w_seq import (\n AXIWriteDataSeq,\n AXIWriteResponseSeq,\n AXIWriteTransactionRequestSeq,\n)\nfrom cocotb.triggers import RisingEdge\nfrom pyuvm import ConfigDB, uvm_root, uvm_sequence\n\n\nclass CoordinatorSeq(uvm_sequence):\n async def axi_write(self, axi_seqr, ahb_seqr):\n axi_trq_seq = AXIWriteTransactionRequestSeq()\n axi_w_seq = AXIWriteDataSeq()\n axi_wresp_seq = AXIWriteResponseSeq()\n\n # Write Request\n await axi_trq_seq.start(axi_seqr)\n await self.delay(5)\n\n # Write Data\n await axi_w_seq.start(axi_seqr)\n\n # Handle AHB Response\n await self.ahb_response_handler(ahb_seqr=ahb_seqr, is_read=False)\n\n # Write Response\n await axi_wresp_seq.start(axi_seqr)\n\n async def axi_read(self, axi_seqr, ahb_seqr):\n axi_trq_seq = AXIReadTransactionRequestSeq()\n axi_rresp_seq = AXIReadTransactionResponseSeq()\n\n # Read Request\n await axi_trq_seq.start(axi_seqr)\n await self.delay(5)\n\n # Handle AHB Response\n await self.ahb_response_handler(ahb_seqr=ahb_seqr, is_read=True)\n await self.delay(5)\n\n # Read Response\n await axi_rresp_seq.start(axi_seqr)\n\n async def delay(self, i):\n for _ in range(i):\n await RisingEdge(cocotb.top.clk)\n\n async def ahb_response_handler(self, ahb_seqr, is_read=True):\n ahb_read_response_seq = AHBLiteAcceptReadSeq(\"ahb_accept_read\")\n ahb_write_response_seq = AHBLiteAcceptWriteSeq(\"ahb_accept_write\")\n\n response = await ahb_seqr.seq_item_export.get_response()\n expected_response = (\n AHB_LITE_NOTIFICATION.AHB_LITE_READ if is_read else AHB_LITE_NOTIFICATION.AHB_LITE_WRITE\n )\n\n if response == expected_response:\n info_string = \"CoordinatorSeq: AHB READ\" if is_read else \"CoordinatorSeq: AHB WRITE\"\n uvm_root().logger.info(info_string)\n if is_read:\n await ahb_read_response_seq.start(ahb_seqr)\n else:\n await ahb_write_response_seq.start(ahb_seqr)\n else:\n raise ValueError(f\"Expected response: {expected_response}. Got: {response}.\")\n\n\nclass TestWriteChannelSeq(CoordinatorSeq):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"ahb_seqr\")\n axi_seqr = ConfigDB().get(None, \"\", \"axi_w_seqr\")\n\n NUM_TRANSACTIONS_PER_TEST = ConfigDB().get(None, \"\", \"NUM_TRANSACTIONS_PER_TEST\")\n for _ in range(NUM_TRANSACTIONS_PER_TEST):\n await self.axi_write(axi_seqr=axi_seqr, ahb_seqr=ahb_seqr)\n await self.delay(10)\n\n\nclass TestReadChannelSeq(CoordinatorSeq):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"ahb_seqr\")\n axi_seqr = ConfigDB().get(None, \"\", \"axi_r_seqr\")\n\n NUM_TRANSACTIONS_PER_TEST = ConfigDB().get(None, \"\", \"NUM_TRANSACTIONS_PER_TEST\")\n for _ in range(NUM_TRANSACTIONS_PER_TEST):\n await self.axi_read(axi_seqr=axi_seqr, ahb_seqr=ahb_seqr)\n await self.delay(10)\n\n\nclass TestBothChannelsSeq(CoordinatorSeq):\n async def body(self):\n ahb_seqr = ConfigDB().get(None, \"\", \"ahb_seqr\")\n axi_w_seqr = ConfigDB().get(None, \"\", \"axi_w_seqr\")\n axi_r_seqr = ConfigDB().get(None, \"\", \"axi_r_seqr\")\n NUM_TRANSACTIONS_PER_TEST = ConfigDB().get(None, \"\", \"NUM_TRANSACTIONS_PER_TEST\")\n\n test_all_q = []\n for _ in range(NUM_TRANSACTIONS_PER_TEST):\n rw = random.randint(0, 1)\n test_all_q += [\"READ\"] if rw else [\"WRITE\"]\n uvm_root().logger.info(f\"TestBothChannelsSeq: Test Sequence: {test_all_q}\")\n\n for i in range(NUM_TRANSACTIONS_PER_TEST):\n if test_all_q[i] == \"READ\":\n await self.axi_read(axi_seqr=axi_r_seqr, ahb_seqr=ahb_seqr)\n elif test_all_q[i] == \"WRITE\":\n await self.axi_write(axi_seqr=axi_w_seqr, ahb_seqr=ahb_seqr)\n else:\n raise ValueError(\"Unexpected value in sequence. Should be READ or WRITE.\")\n" }, { "path": "verification/block/lib_axi4_to_ahb/test_axi.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom cocotb.queue import QueueFull\nfrom coordinator_seq import TestBothChannelsSeq\nfrom testbench import BaseTest\n\n\n@pyuvm.test()\nclass TestAXI(BaseTest):\n def end_of_elaboration_phase(self):\n self.seq = TestBothChannelsSeq.create(\"stimulus\")\n\n async def run(self):\n self.raise_objection()\n await self.seq.start()\n self.drop_objection()\n" }, { "path": "verification/block/lib_axi4_to_ahb/test_axi_read_channel.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom cocotb.queue import QueueFull\nfrom coordinator_seq import TestReadChannelSeq\nfrom testbench import BaseTest\n\n\n@pyuvm.test()\nclass TestAXIReadChannel(BaseTest):\n def end_of_elaboration_phase(self):\n self.seq = TestReadChannelSeq.create(\"stimulus\")\n\n async def run(self):\n self.raise_objection()\n await self.seq.start()\n self.drop_objection()\n" }, { "path": "verification/block/lib_axi4_to_ahb/test_axi_write_channel.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport pyuvm\nfrom coordinator_seq import TestWriteChannelSeq\nfrom testbench import BaseTest\n\n\n@pyuvm.test()\nclass TestAXIWriteChannel(BaseTest):\n def end_of_elaboration_phase(self):\n self.seq = TestWriteChannelSeq.create(\"stimulus\")\n\n async def run(self):\n self.raise_objection()\n await self.seq.start()\n self.drop_objection()\n" }, { "path": "verification/block/lib_axi4_to_ahb/testbench.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport logging\nimport os\nfrom decimal import Decimal\n\nimport cocotb\nfrom ahb_lite_agent import AHBLiteAgent\nfrom ahb_lite_pkg import AHB_LITE_RESPONSE_CODES, AHB_LITE_TRANSFER_TYPE_ENCODING\nfrom axi_pkg import AXI_READ_RESPONSE_CODES, AXI_WRITE_RESPONSE_CODES\nfrom axi_r_agent import AXIReadChannelAgent\nfrom axi_w_agent import AXIWriteChannelAgent\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, Timer\nfrom pyuvm import (\n ConfigDB,\n uvm_component,\n uvm_env,\n uvm_get_port,\n uvm_report_object,\n uvm_test,\n uvm_tlm_analysis_fifo,\n)\n\n\nclass Scoreboard(uvm_component):\n def build_phase(self):\n self.axi_w_req_fifo = uvm_tlm_analysis_fifo(\"axi_w_req_fifo\", self)\n self.axi_w_rsp_fifo = uvm_tlm_analysis_fifo(\"axi_w_rsp_fifo\", self)\n self.axi_w_req_get_port = uvm_get_port(\"axi_w_req_get_port\", self)\n self.axi_w_rsp_get_port = uvm_get_port(\"axi_w_rsp_get_port\", self)\n self.axi_w_req_export = self.axi_w_req_fifo.analysis_export\n self.axi_w_rsp_export = self.axi_w_rsp_fifo.analysis_export\n\n self.axi_r_req_fifo = uvm_tlm_analysis_fifo(\"axi_r_req_fifo\", self)\n self.axi_r_rsp_fifo = uvm_tlm_analysis_fifo(\"axi_r_rsp_fifo\", self)\n self.axi_r_req_get_port = uvm_get_port(\"axi_r_req_get_port\", self)\n self.axi_r_rsp_get_port = uvm_get_port(\"axi_r_rsp_get_port\", self)\n self.axi_r_req_export = self.axi_r_req_fifo.analysis_export\n self.axi_r_rsp_export = self.axi_r_rsp_fifo.analysis_export\n\n self.ahb_req_fifo = uvm_tlm_analysis_fifo(\"ahb_req_fifo\", self)\n self.ahb_rsp_fifo = uvm_tlm_analysis_fifo(\"ahb_rsp_fifo\", self)\n self.ahb_req_get_port = uvm_get_port(\"ahb_req_get_port\", self)\n self.ahb_rsp_get_port = uvm_get_port(\"ahb_rsp_get_port\", self)\n self.ahb_req_export = self.ahb_req_fifo.analysis_export\n self.ahb_rsp_export = self.ahb_rsp_fifo.analysis_export\n\n def connect_phase(self):\n self.axi_w_req_get_port.connect(self.axi_w_req_fifo.get_export)\n self.axi_w_rsp_get_port.connect(self.axi_w_rsp_fifo.get_export)\n\n self.axi_r_req_get_port.connect(self.axi_r_req_fifo.get_export)\n self.axi_r_rsp_get_port.connect(self.axi_r_rsp_fifo.get_export)\n\n self.ahb_req_get_port.connect(self.ahb_req_fifo.get_export)\n self.ahb_rsp_get_port.connect(self.ahb_rsp_fifo.get_export)\n\n def check_phase(self):\n passed = True\n self.logger.info(\"Check Phase\")\n axi_w_transactions = self.check_axi_write()\n axi_r_transactions = self.check_axi_read()\n ahb_transactions = self.check_ahb()\n\n ahb_w_transactions = []\n ahb_r_transactions = []\n for transaction in ahb_transactions:\n if transaction[\"TYPE\"] == \"WRITE\":\n ahb_w_transactions.append(transaction)\n else:\n ahb_r_transactions.append(transaction)\n\n assert len(axi_w_transactions) == len(ahb_w_transactions)\n assert len(axi_r_transactions) == len(ahb_r_transactions)\n\n num_w_transactions = len(axi_w_transactions)\n for id in range(num_w_transactions):\n self.logger.info(f\"AXI Wrote {axi_w_transactions[id]}\")\n self.logger.info(f\"AHB Wrote {ahb_w_transactions[id]}\")\n assert axi_w_transactions[id] == ahb_w_transactions[id]\n\n num_r_transactions = len(axi_r_transactions)\n for id in range(num_r_transactions):\n self.logger.info(f\"AXI Read {axi_r_transactions[id]}\")\n self.logger.info(f\"AHB Read {ahb_r_transactions[id]}\")\n assert axi_r_transactions[id] == ahb_r_transactions[id]\n\n assert passed\n\n def check_axi_write(self):\n axi_w_req_list = []\n while self.axi_w_req_get_port.can_get():\n _, item = self.axi_w_req_get_port.try_get()\n axi_w_req_dict = {}\n\n awvalid = item[0]\n awaddr = item[2]\n wvalid = item[5]\n wdata = item[6]\n\n if awvalid:\n axi_w_req_dict[\"ADDRESS\"] = awaddr\n elif wvalid:\n axi_w_req_dict[\"DATA\"] = wdata\n else:\n raise ValueError(\"Unexpected item in monitor queue.\")\n\n axi_w_req_list.append(axi_w_req_dict)\n\n # For each request there should be one data item\n transaction_requests = axi_w_req_list[0::2]\n transaction_data = axi_w_req_list[1::2]\n assert len(transaction_requests) == len(transaction_data)\n\n num_transactions = len(transaction_data)\n axi_w_transactions = []\n for id in range(num_transactions):\n axi_w_transaction = {}\n axi_w_transaction[\"TYPE\"] = \"WRITE\"\n axi_w_transaction[\"ADDRESS\"] = transaction_requests[id][\"ADDRESS\"]\n axi_w_transaction[\"DATA\"] = transaction_data[id][\"DATA\"]\n axi_w_transactions.append(axi_w_transaction)\n\n # Check if each transaction is confirmed\n axi_w_rsp_list = []\n while self.axi_w_rsp_get_port.can_get():\n _, item = self.axi_w_rsp_get_port.try_get()\n axi_w_rsp_dict = {}\n\n bvalid = item[2]\n bresp = item[3]\n\n assert bvalid == 1\n assert bresp == AXI_WRITE_RESPONSE_CODES.OKAY\n axi_w_rsp_dict[\"STATUS\"] = \"OKAY\"\n axi_w_rsp_list.append(axi_w_rsp_dict)\n\n assert len(transaction_requests) == len(axi_w_rsp_list)\n\n self.logger.debug(f\"AXI WRITE TRANSACTIONS {axi_w_transactions}\")\n return axi_w_transactions\n\n def check_axi_read(self):\n axi_r_req_list = []\n while self.axi_r_req_get_port.can_get():\n _, item = self.axi_r_req_get_port.try_get()\n axi_r_req_dict = {}\n\n arvalid = item[0]\n araddr = item[2]\n\n assert arvalid == 1\n axi_r_req_dict[\"TYPE\"] = \"READ\"\n axi_r_req_dict[\"ADDRESS\"] = araddr\n axi_r_req_list.append(axi_r_req_dict)\n\n self.logger.debug(f\"AXI READ REQUESTS: {axi_r_req_list}\")\n\n axi_r_rsp_list = []\n while self.axi_r_rsp_get_port.can_get():\n _, item = self.axi_r_rsp_get_port.try_get()\n axi_r_rsp_dict = {}\n\n rvalid = item[1]\n rdata = item[3]\n rresp = item[4]\n\n assert rvalid == 1\n assert rresp == AXI_READ_RESPONSE_CODES.OKAY\n\n axi_r_rsp_dict[\"TYPE\"] = \"READ RESPONSE\"\n axi_r_rsp_dict[\"DATA\"] = int(rdata)\n axi_r_rsp_list.append(axi_r_rsp_dict)\n\n assert len(axi_r_req_list) == len(axi_r_rsp_list)\n\n axi_r_transactions = []\n num_transactions = len(axi_r_req_list)\n for id in range(num_transactions):\n axi_r_transaction = {}\n axi_r_transaction[\"TYPE\"] = \"READ\"\n axi_r_transaction[\"ADDRESS\"] = axi_r_req_list[id][\"ADDRESS\"]\n axi_r_transaction[\"DATA\"] = axi_r_rsp_list[id][\"DATA\"]\n axi_r_transactions.append(axi_r_transaction)\n\n self.logger.debug(f\"AXI READ TRANSACTIONS {axi_r_transactions}\")\n\n return axi_r_transactions\n\n def check_ahb(self):\n ahb_rsp_list = []\n is_even = True\n ahb_rsp_dict = {}\n while self.ahb_rsp_get_port.can_get():\n _, item = self.ahb_rsp_get_port.try_get()\n\n haddr = item[0]\n htrans = item[5]\n hwrite = item[6]\n hwdata = item[7]\n\n if is_even:\n assert htrans == AHB_LITE_TRANSFER_TYPE_ENCODING.NONSEQ\n\n if hwrite:\n ahb_rsp_dict[\"TYPE\"] = \"WRITE\"\n ahb_rsp_dict[\"DATA\"] = int(hwdata)\n else:\n ahb_rsp_dict[\"TYPE\"] = \"READ\"\n\n ahb_rsp_dict[\"ADDRESS\"] = int(haddr)\n\n if not is_even:\n ahb_rsp_list.append(ahb_rsp_dict)\n ahb_rsp_dict = {}\n\n is_even = not is_even\n\n self.logger.debug(f\"ahb_rsp_list {ahb_rsp_list}\")\n\n ahb_req_list = []\n is_even = True\n ahb_req_dict = {}\n while self.ahb_req_get_port.can_get():\n _, item = self.ahb_req_get_port.try_get()\n\n hrdata = item[0]\n hready = item[1]\n hresp = item[2]\n\n assert hready == 1\n assert hresp == AHB_LITE_RESPONSE_CODES.OKAY\n\n if not is_even:\n ahb_req_dict[\"DATA\"] = int(hrdata)\n ahb_req_list.append(ahb_req_dict)\n ahb_req_dict = {}\n\n is_even = not is_even\n\n self.logger.debug(f\"ahb_req_list {ahb_req_list}\")\n\n assert len(ahb_rsp_list) == len(ahb_req_list)\n\n ahb_transactions = []\n num_transactions = len(ahb_rsp_list)\n for id in range(num_transactions):\n ahb_transaction = {}\n if ahb_rsp_list[id][\"TYPE\"] == \"WRITE\":\n ahb_transaction = ahb_rsp_list[id]\n ahb_transactions.append(ahb_transaction)\n continue\n else:\n ahb_transaction[\"TYPE\"] = \"READ\"\n ahb_transaction[\"ADDRESS\"] = ahb_rsp_list[id][\"ADDRESS\"]\n ahb_transaction[\"DATA\"] = ahb_req_list[id][\"DATA\"]\n ahb_transactions.append(ahb_transaction)\n\n self.logger.debug(f\"AHB Transactions {ahb_transactions}\")\n return ahb_transactions\n\n\nclass BaseEnvironment(uvm_env):\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"AXI_DATA_WIDTH\", 64)\n ConfigDB().set(None, \"*\", \"DUT_PRTY\", cocotb.top.PRTY.value)\n ConfigDB().set(None, \"*\", \"DUT_TAG\", cocotb.top.TAG.value)\n ConfigDB().set(None, \"*\", \"DUT_ID\", cocotb.top.ID.value)\n\n ConfigDB().set(None, \"*\", \"NUM_TRANSACTIONS_PER_TEST\", 32)\n\n self.agent_axi_w = AXIWriteChannelAgent(\"axi_w_agent\", self)\n self.agent_axi_r = AXIReadChannelAgent(\"axi_r_agent\", self)\n self.agent_ahb = AHBLiteAgent(\"ahb_lite_agent\", self)\n\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.agent_axi_w.monitor.ap_req.connect(self.scoreboard.axi_w_req_export)\n self.agent_axi_w.monitor.ap_rsp.connect(self.scoreboard.axi_w_rsp_export)\n\n self.agent_axi_r.monitor.ap_req.connect(self.scoreboard.axi_r_req_export)\n self.agent_axi_r.monitor.ap_rsp.connect(self.scoreboard.axi_r_rsp_export)\n\n self.agent_ahb.monitor.ap_req.connect(self.scoreboard.ahb_req_export)\n self.agent_ahb.monitor.ap_rsp.connect(self.scoreboard.ahb_rsp_export)\n\n\nclass BaseTest(uvm_test):\n \"\"\" \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n # Synchronize pyuvm logging level with cocotb logging level.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = BaseEnvironment(\"env\", self)\n cocotb.top.rst_l.value = 0\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self, signalName, timeLength=\"100e-9\", isActiveHigh=True):\n\n cocotb.top.rst_l.value = 0\n cocotb.top.free_clk.value = 0\n cocotb.top.bus_clk_en.value = 1\n cocotb.top.clk_override.value = 0\n cocotb.top.dec_tlu_force_halt.value = 0\n cocotb.top.axi_awvalid.value = 0\n cocotb.top.axi_awid.value = 0\n cocotb.top.axi_awaddr.value = 0\n cocotb.top.axi_awsize.value = 0\n cocotb.top.axi_awprot.value = 0\n cocotb.top.axi_wvalid.value = 0\n cocotb.top.axi_wdata.value = 0\n cocotb.top.axi_wstrb.value = 0\n cocotb.top.axi_wlast.value = 0\n cocotb.top.axi_bready.value = 0\n cocotb.top.axi_arvalid.value = 0\n cocotb.top.axi_arid.value = 0\n cocotb.top.axi_araddr.value = 0\n cocotb.top.axi_arsize.value = 0\n cocotb.top.axi_arprot.value = 0\n cocotb.top.axi_rready.value = 0\n cocotb.top.ahb_hrdata.value = 0\n cocotb.top.ahb_hready.value = 0\n cocotb.top.ahb_hresp.value = 0\n\n signal = getattr(cocotb.top, signalName)\n signal.value = int(isActiveHigh)\n self.config()\n await Timer(Decimal(timeLength), units=\"sec\")\n signal.value = not int(isActiveHigh)\n\n def config(self):\n cocotb.top.scan_mode.value = 0\n cocotb.top.bus_clk_en.value = 1\n cocotb.top.clk_override.value = 0\n cocotb.top.dec_tlu_force_halt.value = 0\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n self.start_clock(\"free_clk\")\n clk = getattr(cocotb.top, \"clk\")\n\n # Issue reset\n resetLength = \"10e-9\"\n await self.do_reset(signalName=\"rst_l\", timeLength=resetLength, isActiveHigh=False)\n\n await ClockCycles(clk, 2)\n await self.run()\n await ClockCycles(clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/lib_axi4_to_ahb/ucli.key", "content": "" }, { "path": "verification/block/lsu_tl/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_lsu_trigger_wrapper\n\nVERILOG_SOURCES = \\\n $(TEST_DIR)/el2_lsu_trigger_wrapper.sv \\\n $(SRCDIR)/lsu/el2_lsu_trigger.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/lsu_tl/config.vlt", "content": "`verilator_config\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_lsu_trigger_wrapper.sv\"\n\nlint_off -rule UNUSEDPARAM -file \"*/el2_lsu_trigger_wrapper.sv\"\n" }, { "path": "verification/block/lsu_tl/el2_lsu_trigger_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro\n// SPDX-License-Identifier: Apache-2.0\nmodule el2_lsu_trigger_wrapper\n import el2_pkg::*;\n#(\n `include \"el2_param.vh\"\n) (\n // Unpacked [3:0] trigger_pkt_t\n input logic [3:0] select,\n input logic [3:0] match,\n input logic [3:0] store,\n input logic [3:0] load,\n input logic [3:0] execute,\n input logic [3:0] m,\n\n input logic [31:0] tdata[4],\n\n // Fields from lsu_pkt_m relevant in this test\n // input logic lsu_word,\n // input logic lsu_half,\n // input logic lsu_dma,\n // input logic lsu_valid,\n // input logic lsu_store,\n\n input logic [31:0] lsu_addr_m, // address\n input logic [31:0] store_data_m, // store data\n\n output logic [3:0] lsu_trigger_match_m // match result\n);\n\n // Pack triggers\n el2_trigger_pkt_t [3:0] trigger_pkt_any;\n for (genvar i = 0; i < 4; i++) begin : g_trigger_assigns\n assign trigger_pkt_any[i].select = select[i];\n assign trigger_pkt_any[i].match = match[i];\n assign trigger_pkt_any[i].store = store[i];\n assign trigger_pkt_any[i].load = load[i];\n assign trigger_pkt_any[i].execute = execute[i];\n assign trigger_pkt_any[i].m = m[i];\n assign trigger_pkt_any[i].tdata2 = tdata[i];\n end\n\n // Pack lsu_pkt_m\n el2_lsu_pkt_t lsu_pkt_m;\n assign lsu_pkt_m.word = 1; // lsu_word;\n assign lsu_pkt_m.half = 1; // lsu_half;\n assign lsu_pkt_m.dma = 0; // lsu_dma;\n assign lsu_pkt_m.valid = 1; // lsu_valid;\n assign lsu_pkt_m.store = 1; // lsu_store;\n\n // The trigger unit\n el2_lsu_trigger tu (\n .*\n );\n\nendmodule\n" }, { "path": "verification/block/lsu_tl/test_lsu_tl.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseTest, TlSequence\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestTriggerLogic(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TlSequence(\"stimulus\")\n\n async def run_phase(self):\n self.raise_objection()\n\n # Run the actual test\n await self.run()\n\n self.drop_objection()\n\n async def run(self):\n await self.seq.start(self.env.tl_seqr)\n" }, { "path": "verification/block/lsu_tl/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport copy\nimport math\nimport os\nimport random\nimport struct\n\nimport pyuvm\nfrom cocotb.binary import BinaryValue\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import (\n ClockCycles,\n Event,\n FallingEdge,\n First,\n Lock,\n RisingEdge,\n Timer,\n)\nfrom cocotb.types import Array, Range\nfrom pyuvm import *\n\n# ==============================================================================\n\n\nclass TlInputItem(uvm_sequence_item):\n \"\"\"\n Trigger Logic output data\n \"\"\"\n\n def __init__(self, data=0, tdata=None, match=0):\n super().__init__(\"TlOutputItem\")\n\n self.match = match\n self.data = data\n self.tdata = [None] * 4\n if tdata is not None:\n for i in range(4):\n self.tdata[i] = tdata[i]\n\n def randomize(self):\n data = \"\"\n for i in range(31): # Sic. Last bit of PC is always 0\n data += random.choice([\"0\", \"1\"])\n data += \"0\"\n\n self.data = int(data, 2)\n\n self.match = 0\n for i in range(4):\n matching = random.choice([False, True])\n trigger = self.random_trigger(data, matching)\n self.match |= trigger[\"match\"] << i\n self.tdata[i] = trigger[\"tdata\"]\n\n def random_trigger(self, data, matching):\n \"\"\"\n Creates a trigger packet for data vector.\n\n It can be precised if the packet will be matching or not.\n \"\"\"\n\n # Select determines if we match against the PC or opcode,\n # TL in TLU does the first thing\n match = \"\"\n tdata = \"\"\n\n # Generate the matched part\n length = 0\n if matching:\n length = random.randrange(32 + 1)\n if length > 0:\n tdata += data[:length]\n else:\n length = random.randrange(1, 32)\n for i in range(length):\n tdata += random.choice([\"0\", \"1\"])\n\n # Assure a mismatch\n i = random.randrange(length)\n b = \"1\" if data[i] == \"0\" else \"0\"\n tdata = tdata[:i] + b + tdata[i + 1 :]\n\n # Generate the mask\n length = 32 - length\n if length == 0:\n match = \"0\" # Do full match\n else:\n match = \"1\"\n tdata += \"0\" + \"1\" * (length - 1)\n\n return {\"match\": int(match, 2), \"tdata\": int(tdata, 2)}\n\n\nclass TlOutputItem(uvm_sequence_item):\n \"\"\"\n Trigger Logic output data\n \"\"\"\n\n def __init__(self, matches):\n super().__init__(\"TlOutputItem\")\n\n self.matches = matches\n\n\n# ==============================================================================\n\n\nclass TlDriver(uvm_driver):\n \"\"\"\n Trigger Logic driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, TlInputItem):\n self.dut.lsu_addr_m.value = it.data\n self.dut.store_data_m.value = it.data\n\n for i in range(4):\n self.dut.tdata[i].value = it.tdata[i]\n\n self.dut.match.value = it.match\n\n self.dut.select.value = 0b0000\n self.dut.store.value = 0b1111\n self.dut.load.value = 0b1111\n self.dut.execute.value = 0b1111\n self.dut.m.value = 0b1111\n\n # Wait for monitors to read the values\n await Timer(period, \"ns\")\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass TlInputMonitor(uvm_component):\n \"\"\"\n Monitor for Trigger Logic inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n while True:\n # Wait for the driver to set the input signals\n await Timer(period, \"ns\")\n\n data = int(self.dut.store_data_m.value)\n tdata = [None] * 4\n\n for i in range(4):\n tdata[i] = int(self.dut.tdata[i].value)\n\n match = int(self.dut.match.value)\n\n self.ap.write(TlInputItem(data, tdata, match))\n\n\nclass TlOutputMonitor(uvm_component):\n \"\"\"\n Monitor for Trigger Logic outputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n while True:\n # Wait for the driver to set the input signals\n await Timer(period, \"ns\")\n\n matches = int(self.dut.lsu_trigger_match_m.value)\n\n self.ap.write(TlOutputItem(matches))\n\n\n# ==============================================================================\n\n\nclass TlScoreboard(uvm_component):\n \"\"\"\n Trigger Logic scoreboard\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self):\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n # Change outputs to str and reproduce what TL does\n res = 0\n match = item_inp.match\n data = f\"{item_inp.data:032b}\"\n for i in range(4):\n tdata = f\"{item_inp.tdata[i]:032b}\"\n if match & (1 << i):\n length = tdata.rindex(\"0\")\n res |= (tdata[:length] == data[:length]) << i\n else:\n res |= (tdata == data) << i\n\n if item_out.matches != res:\n self.logger.error(f\"Expected {res:04b} got {item_out.matches:04b}\")\n for i in range(4):\n print(f\"{item_inp.data:032b} (match {item_inp.tdata[i]:032b}\")\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass TlSequence(uvm_sequence):\n \"\"\"\n Base sequence of randomized 32-bit A and B operands along with operators\n picked randomly from the allowed set\n \"\"\"\n\n def __init__(self, name, ops=None):\n super().__init__(name)\n\n async def body(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n\n for i in range(count):\n item = TlInputItem()\n item.randomize()\n\n await self.start_item(item)\n await self.finish_item(item)\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 5000)\n\n # Sequencers\n self.tl_seqr = uvm_sequencer(\"tl_seqr\", self)\n\n # Driver\n self.tl_drv = TlDriver(\"tl_drv\", self, dut=cocotb.top)\n\n # Monitors\n self.inp_mon = TlInputMonitor(\"inp_mon\", self, dut=cocotb.top)\n self.out_mon = TlOutputMonitor(\"out_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = TlScoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.tl_drv.seq_item_port.connect(self.tl_seqr.seq_item_export)\n\n self.inp_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.out_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/noxfile.py", "content": "# Copyright (C) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport logging\nimport os\nfrom xml.etree import ElementTree as ET\n\nimport nox\n\n# nox quirk: in status.json, return code for failure is 0\n# https://github.com/wntrblm/nox/blob/main/nox/sessions.py#L128C11-L128C11\nnox.options.report = \"status.json\"\nnox.options.reuse_existing_virtualenvs = True\n\n# Test configuration\nblockPath = \".\"\npipRequirementsPath = \"requirements.txt\"\n\n# Coverage types to collect\ncoverageTypes = [\n \"all\",\n]\n\n# Used lint tools\nlintTools = [\n \"isort\", # config in pyproject.toml\n \"black\", # config in pyproject.toml\n \"flake8\", # config in .flake8\n]\n\n\ndef isSimFailure(\n resultsFile=\"results.xml\", testsuites_name=\"results\", verbose=False, suppress_rc=False\n):\n \"\"\"\n Extract failure code from cocotb results.xml file\n Based on https://github.com/cocotb/cocotb/blob/master/bin/combine_results.py\n \"\"\"\n rc = 0\n\n # Logging\n logger = logging.getLogger()\n logger.setLevel(logging.DEBUG)\n logHandler = logging.FileHandler(filename=\"parseResultsXML.log\", mode=\"w\", encoding=\"utf-8\")\n logFormatter = logging.Formatter()\n logHandler.setFormatter(logFormatter)\n logger.addHandler(logHandler)\n logHandler.setLevel(logging.INFO)\n if verbose:\n logHandler.setLevel(logging.DEBUG)\n\n # Main\n result = ET.Element(\"testsuites\", name=testsuites_name)\n logging.debug(f\"Reading file {resultsFile}\")\n tree = ET.parse(resultsFile)\n\n for ts in tree.iter(\"testsuite\"):\n ts_name = ts.get(\"name\")\n ts_package = ts.get(\"package\")\n logging.debug(f\"Testsuite name : {ts_name}, package : {ts_package}\")\n use_element = None\n for existing in result:\n if existing.get(\"name\") == ts.get(\"name\") and existing.get(\"package\") == ts.get(\n \"package\"\n ):\n use_element = existing\n break\n if use_element is None:\n result.append(ts)\n else:\n use_element.extend(list(ts))\n\n if verbose:\n ET.dump(result)\n\n for testsuite in result.iter(\"testsuite\"):\n for testcase in testsuite.iter(\"testcase\"):\n for failure in testcase.iter(\"failure\"):\n rc = 1\n logging.info(\n \"Failure in testsuite: '{}' classname: '{}' testcase: '{}' with parameters '{}'\".format(\n testsuite.get(\"name\"),\n testcase.get(\"classname\"),\n testcase.get(\"name\"),\n testsuite.get(\"package\"),\n )\n )\n\n if suppress_rc:\n rc = 0\n logging.shutdown()\n return rc\n\n\ndef verify_block(session, blockName, testName, coverage=\"\"):\n session.install(\"-r\", pipRequirementsPath)\n testPath = os.path.join(blockPath, blockName)\n testNameXML = os.path.join(testName + \".xml\")\n testNameXMLPath = os.path.join(testPath, testNameXML)\n testNameLog = os.path.join(testName + \".log\")\n testNameLogPath = os.path.join(testPath, testNameLog)\n with open(testNameLogPath, \"w\") as testLog:\n session.run(\n \"make\",\n \"-C\",\n testPath,\n \"all\",\n \"COVERAGE_TYPE=\" + coverage,\n \"MODULE=\" + testName,\n \"COCOTB_RESULTS_FILE=\" + testNameXML,\n external=True,\n stdout=testLog,\n stderr=testLog,\n )\n # Prevent coverage.dat and test log from being overwritten\n if coverage != \"\":\n coveragePath = testPath\n coverageName = \"coverage.dat\"\n coverageNamePath = os.path.join(coveragePath, coverageName)\n newCoverageName = \"coverage_\" + testName + \"_\" + coverage + \".dat\"\n newCoverageNamePath = os.path.join(coveragePath, newCoverageName)\n os.rename(coverageNamePath, newCoverageNamePath)\n newTestNameLog = testName + \"_\" + coverage + \".log\"\n newTestNameLogPath = os.path.join(testPath, newTestNameLog)\n os.rename(testNameLogPath, newTestNameLogPath)\n # Add check from results.xml to notify nox that test failed\n isTBFailure = isSimFailure(resultsFile=testNameXMLPath)\n if isTBFailure:\n raise Exception(\"SimFailure: cocotb failed. See test logs for more information.\")\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"pic\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_reset\",\n \"test_clken\",\n \"test_config\",\n \"test_pending\",\n \"test_prioritization\",\n \"test_servicing\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef pic_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"pic_gw\"])\n@nox.parametrize(\"testName\", [\"test_gateway\"])\n@nox.parametrize(\"coverage\", coverageTypes)\ndef pic_gw_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"dec_tl\"])\n@nox.parametrize(\"testName\", [\"test_dec_tl\"])\n@nox.parametrize(\"coverage\", coverageTypes)\ndef dec_tl_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"dec_ib\"])\n@nox.parametrize(\"testName\", [\"test_dec_ib\"])\n@nox.parametrize(\"coverage\", coverageTypes)\ndef dec_ib_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"dma\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_reset\",\n \"test_read\",\n \"test_write\",\n \"test_address\",\n \"test_ecc\",\n \"test_debug_read\",\n \"test_debug_write\",\n \"test_debug_address\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef dma_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"ifu_compress\"])\n@nox.parametrize(\"testName\", [\"test_compress\"])\n@nox.parametrize(\"coverage\", coverageTypes)\ndef ifu_compress_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"ifu_mem_ctl\"])\n@nox.parametrize(\"testName\", [\"test_miss\", \"test_err\", \"test_err_stop\"])\n@nox.parametrize(\"coverage\", coverageTypes)\ndef ifu_mem_ctl_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"exu_alu\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_arith\",\n \"test_logic\",\n \"test_zbb\",\n \"test_zbs\",\n \"test_zbp\",\n \"test_zba\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef exu_alu_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"exu_mul\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_mul\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef exu_mul_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"exu_div\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_div\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef exu_div_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"iccm\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_readwrite\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef iccm_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"dccm\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_readwrite\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef dccm_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"dcls\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_lockstep\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef dcls_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"lib_axi4_to_ahb\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_axi\",\n \"test_axi_read_channel\",\n \"test_axi_write_channel\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef lib_axi4_to_ahb_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"lib_ahb_to_axi4\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_write\",\n \"test_read\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef lib_ahb_to_axi4_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"pmp\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_xwr_access\",\n \"test_address_matching\",\n \"test_multiple_configs\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef pmp_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"pmp_random\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_pmp_random\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef pmp_random_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"dec\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_dec\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef dec_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"dec_tlu_ctl\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_dec_tl\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef dec_tlu_ctl_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"dmi\"])\n@nox.parametrize(\n \"testName\",\n [\n \"test_jtag_ir\",\n \"test_dmi_read_write\",\n \"test_dmi_tap_fsm\",\n ],\n)\n@nox.parametrize(\"coverage\", coverageTypes)\ndef dmi_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"lsu_tl\"])\n@nox.parametrize(\"testName\", [\"test_lsu_tl\"])\n@nox.parametrize(\"coverage\", coverageTypes)\ndef lsu_tl_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(tags=[\"tests\"])\n@nox.parametrize(\"blockName\", [\"dec_pmp_ctl\"])\n@nox.parametrize(\"testName\", [\"test_dec_pmp_ctl\"])\n@nox.parametrize(\"coverage\", coverageTypes)\ndef dec_pmp_ctl_verify(session, blockName, testName, coverage):\n verify_block(session, blockName, testName, coverage)\n\n\n@nox.session(reuse_venv=True)\ndef lint(session: nox.Session) -> None:\n \"\"\"Options are defined in pyproject.toml and .flake8 files\"\"\"\n session.install(*lintTools)\n session.run(\"isort\", \".\")\n session.run(\"black\", \".\")\n session.run(\"flake8\", \".\")\n\n\n@nox.session()\ndef test_lint(session: nox.Session) -> None:\n session.install(*lintTools)\n session.run(\"isort\", \"--check\", \".\")\n session.run(\"black\", \"--check\", \".\")\n session.run(\"flake8\", \".\")\n" }, { "path": "verification/block/pic/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_pic_ctrl\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/el2_pic_ctrl.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/pic/test_clken.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nfrom copy import deepcopy\n\nimport cocotb\nimport pyuvm\nfrom cocotb.result import SimTimeoutError\nfrom cocotb.triggers import Edge, Lock, RisingEdge, Timer, with_timeout\nfrom pyuvm import *\nfrom testbench import BaseEnv, BaseTest, collect_signals\n\n# =============================================================================\n\n\nclass ClockEnableItem(uvm_sequence_item):\n def __init__(self, clk_en, io_clk_en):\n super().__init__(\"ClockEnableItem\")\n self.clk_en = clk_en\n self.io_clk_en = io_clk_en\n\n\nclass ClockStateItem(uvm_sequence_item):\n def __init__(self, state):\n super().__init__(\"ClockStateItem\")\n self.state = deepcopy(state)\n\n\n# =============================================================================\n\n\nclass ClkenDriver(uvm_driver):\n \"\"\"\n A driver for clock gating override signals\n \"\"\"\n\n SIGNALS = [\n \"clk_override\",\n \"io_clk_override\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, ClockEnableItem):\n self.clk_override.value = it.clk_en\n self.io_clk_override.value = it.io_clk_en\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass ClkenMonitor(uvm_component):\n \"\"\"\n A monitor for clock gating override signals\n \"\"\"\n\n SIGNALS = [\n \"clk\",\n \"clk_override\",\n \"io_clk_override\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n self.prev_clk_override = 0\n self.prev_io_clk_override = 0\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Sample control signals\n await RisingEdge(self.clk)\n clk_override = int(self.clk_override.value)\n io_clk_override = int(self.io_clk_override.value)\n\n if (\n self.prev_clk_override != clk_override\n or self.prev_io_clk_override != io_clk_override\n ):\n self.ap.write(ClockEnableItem(clk_override, io_clk_override))\n\n self.prev_clk_override = clk_override\n self.prev_io_clk_override = io_clk_override\n\n\n# =============================================================================\n\n\nclass ClockMonitor(uvm_component):\n \"\"\"\n A monitor for clock signal activity.\n\n The monitor spawns one task per clock signal. Each task waits either for a\n signal transition or a fixed time equal to twice the expected clock period\n (its actually important that the time is greater than half-period) If,\n during the waiting time, the task detects any signal transition\n (1->0, 0->1), then it marks the signal as an active clock. Otherwise, the\n signal is marked as inactive.\n\n The main task of the monitor periodically samples the state vector reported\n by monitoring tasks and sends a message through its analysis port. This is\n scheduled to happen periodically every 5 * the expected clock period. The\n scheduling is chosen arbitrarily.\n \"\"\"\n\n SIGNALS = [\n \"pic_raddr_c1_clk\",\n \"pic_data_c1_clk\",\n \"pic_pri_c1_clk\",\n \"pic_int_c1_clk\",\n \"gw_config_c1_clk\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n self.lock = Lock()\n self.state = {sig: False for sig in self.SIGNALS}\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n # Start monitoring tasks\n for name in self.SIGNALS:\n cocotb.start_soon(self.monitor_clock(name))\n\n # Periodically sample clock state and send messages\n while True:\n # Wait\n await Timer(period * 5, \"ns\")\n\n # Sample state and send item\n async with self.lock:\n self.ap.write(ClockStateItem(self.state))\n\n async def monitor_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n signal = getattr(self, name)\n\n # Monitor the clock signal\n while True:\n # Wait for clock edges with timeout\n try:\n await with_timeout(Edge(signal), 2.0 * period, \"ns\")\n toggling = True\n except SimTimeoutError:\n toggling = False\n\n # Update the state\n async with self.lock:\n self.state[name] = toggling\n\n\n# =============================================================================\n\n\nclass Scoreboard(uvm_component):\n \"\"\"\n Clock activity scoreboard.\n \"\"\"\n\n CLOCKS = [\n \"pic_raddr_c1_clk\",\n \"pic_data_c1_clk\",\n \"pic_pri_c1_clk\",\n \"pic_int_c1_clk\",\n ]\n\n IO_CLOCKS = [\n # FIXME: \"IO\" clock gates are instanced along with gateway modules\n # inside a generate block. It appears that cocotb does not have access\n # to them.\n ]\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n while self.port.can_get():\n # Get an item\n got_item, item = self.port.try_get()\n assert got_item\n\n # Got a change in clock override control\n if isinstance(item, ClockEnableItem):\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # Reject next clock state item\n got_it, it = self.port.try_get()\n assert got_it and isinstance(it, ClockStateItem)\n\n # Get next clock state item and process it\n got_it, it = self.port.try_get()\n assert got_it and isinstance(it, ClockStateItem)\n\n # Check clocks\n for clk in self.CLOCKS:\n if it.state[clk] != item.clk_en:\n self.passed = False\n self.logger.error(\n \"Clock '{}' is {}toggling\".format(\n clk,\n \"not \" if item.clk_en else \"\",\n )\n )\n\n for clk in self.IO_CLOCKS:\n if it.state[clk] != item.io_clk_en:\n self.passed = False\n self.logger.error(\n \"IO clock '{}' is {}toggling\".format(\n clk,\n \"not \" if item.io_clk_en else \"\",\n )\n )\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# =============================================================================\n\n\nclass TestSequence(uvm_sequence):\n \"\"\"\n A sequence which instructs a driver to enable/disable clock gating override\n \"\"\"\n\n async def body(self):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n\n # Disable overrides\n item = ClockEnableItem(0, 0)\n await self.start_item(item)\n await self.finish_item(item)\n\n # Wait\n await Timer(20 * period, \"ns\")\n\n # Enable clock override\n item = ClockEnableItem(1, 0)\n await self.start_item(item)\n await self.finish_item(item)\n\n # Wait\n await Timer(20 * period, \"ns\")\n\n # Disable overrides\n item = ClockEnableItem(0, 0)\n await self.start_item(item)\n await self.finish_item(item)\n\n # Wait\n await Timer(20 * period, \"ns\")\n\n # Enable clock override\n item = ClockEnableItem(0, 1)\n await self.start_item(item)\n await self.finish_item(item)\n\n # Wait\n await Timer(20 * period, \"ns\")\n\n # Disable overrides\n item = ClockEnableItem(0, 0)\n await self.start_item(item)\n await self.finish_item(item)\n\n # Wait\n await Timer(20 * period, \"ns\")\n\n\n# =============================================================================\n\n\nclass TestEnv(BaseEnv):\n \"\"\"\n Test environment\n \"\"\"\n\n def build_phase(self):\n super().build_phase()\n\n # Sequencers\n self.clken_seqr = uvm_sequencer(\"clken_seqr\", self)\n\n # Clock enable driver and monitor\n self.clken_drv = ClkenDriver(\"clken_drv\", self, uut=cocotb.top)\n self.clken_mon = ClkenMonitor(\"clken_mon\", self, uut=cocotb.top)\n\n # Clock monitor\n self.clk_mon = ClockMonitor(\"clk_mon\", self, uut=cocotb.top)\n\n # Add scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n self.clken_drv.seq_item_port.connect(self.clken_seqr.seq_item_export)\n self.clken_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.clk_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n@pyuvm.test()\nclass TestClockEnable(BaseTest):\n \"\"\"\n A test that checks forcing clock gates open\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TestSequence.create(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.clken_seqr)\n" }, { "path": "verification/block/pic/test_config.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom pyuvm import *\nfrom testbench import BaseEnv, BaseTest, BusReadItem, BusWriteItem, RegisterMap\n\n# =============================================================================\n\n\nclass TestSequence(uvm_sequence):\n \"\"\"\n A sequence of randomized register and content writes followed by randomized\n reads of them.\n \"\"\"\n\n def __init__(self, name):\n super().__init__(name)\n self.reg_map = RegisterMap()\n\n async def body(self):\n num_itr = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n max_pri = ConfigDB().get(None, \"\", \"PIC_NUM_PRIORITIES\")\n\n for i in range(num_itr):\n # Issue register writes\n names = list(self.reg_map.reg.keys())\n random.shuffle(names)\n\n written = []\n\n for name in names:\n reg = self.reg_map.reg[name]\n val = None\n\n if name == \"mpiccfg\":\n val = random.randint(0, 1)\n elif name.startswith(\"meipl\"):\n val = random.randint(0, max_pri)\n elif name.startswith(\"meigwctrl\"):\n val = random.randint(0, 3) # 2-bit combinations\n elif name.startswith(\"meie\"):\n val = random.randint(0, 1) # 1-bit combinations\n\n if val is None:\n continue\n\n item = BusWriteItem(reg, val)\n await self.start_item(item)\n await self.finish_item(item)\n\n written.append(reg)\n\n # Issue register reads for the written ones\n random.shuffle(written)\n\n for reg in written:\n item = BusReadItem(reg)\n await self.start_item(item)\n await self.finish_item(item)\n\n\nclass Scoreboard(uvm_component):\n \"\"\"\n A scoreboard that keeps track of data written to registers and compares\n it with data read afterwards.\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n self.reg_map = RegisterMap()\n self.reg_content = dict()\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n while self.port.can_get():\n # Get an item\n got_item, item = self.port.try_get()\n assert got_item\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # Bus write\n if isinstance(item, BusWriteItem):\n self.reg_content[item.addr] = item.data\n\n # Bus read\n elif isinstance(item, BusReadItem):\n # Get register name\n reg_name = \"0x{:08X}\".format(item.addr)\n name = self.reg_map.adr.get(item.addr)\n if name is not None:\n reg_name += \" '{}'\".format(name)\n\n # No entry\n golden = self.reg_content.get(item.addr)\n if golden is None:\n self.logger.error(\"Register {} was not written\".format(reg_name))\n self.passed = False\n\n # Mismatch\n elif golden != item.data:\n self.logger.error(\n \"Register {} content mismatch, is 0x{:08X} should be 0x{:08X}\".format(\n reg_name, item.data, golden\n )\n )\n self.passed = False\n else:\n self.logger.debug(\n \"Register {} ok, 0x{:08X}\".format(\n reg_name,\n item.data,\n )\n )\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Add scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.reg_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n@pyuvm.test()\nclass TestConfig(BaseTest):\n \"\"\"\n A test for PIC configuration register access\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TestSequence.create(\"stimulus\")\n\n async def run(self):\n await self.seq.start(self.env.reg_seqr)\n" }, { "path": "verification/block/pic/test_pending.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport cocotb\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseEnv, BaseTest, BusReadItem, BusWriteItem, IrqItem, RegisterMap\n\n# =============================================================================\n\n\nclass TestSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n self.reg_seqr = ConfigDB().get(None, \"\", \"REG_SEQR\")\n self.irq_seqr = ConfigDB().get(None, \"\", \"IRQ_SEQR\")\n\n self.regs = RegisterMap()\n\n async def body(self):\n num_irq = ConfigDB().get(None, \"\", \"PIC_NUM_INTERRUPTS\")\n\n # Disable all interrupts\n for i in range(1, num_irq):\n reg = self.regs.reg[\"meie{}\".format(i)]\n\n item = BusWriteItem(reg, 0)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n # Configure gateways\n for i in range(1, num_irq):\n reg = self.regs.reg[\"meigwctrl{}\".format(i)]\n val = 0x2 # Edge, active-high\n\n item = BusWriteItem(reg, val)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n # Wait\n await ClockCycles(cocotb.top.clk, 4)\n\n # Randomize IRQ\n irqs = 0\n while irqs == 0:\n for i in range(1, num_irq):\n if random.random() > 0.5:\n irqs |= 1 << i\n\n item = IrqItem(irqs)\n await self.irq_seqr.start_item(item)\n await self.irq_seqr.finish_item(item)\n\n # Read IRQ pending status register(s)\n num_meip = (num_irq + 31) // 32\n for i in range(0, num_meip):\n reg = self.regs.reg[\"meip{}\".format(i)]\n item = BusReadItem(reg)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n\n# ==============================================================================\n\n\nclass Scoreboard(uvm_component):\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n self.regs = RegisterMap()\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n\n irqs = 0\n\n while self.port.can_get():\n _, item = self.port.try_get()\n\n # Register read\n if isinstance(item, BusReadItem):\n # Get the reg name\n reg = self.regs.adr.get(item.addr)\n if not reg:\n self.logger.error(\"Unknown register address 0x{:08X}\".format(item.addr))\n self.passed = False\n continue\n\n # This is a meipX register\n if reg.startswith(\"meip\") and reg[4] != \"l\":\n x = int(reg[4:])\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # Check if the content matches current IRQ pending status\n mask = 0xFFFFFFFF << (32 * x)\n pend = item.data << (32 * x)\n if irqs & mask != pend:\n self.logger.error(\n f\"{reg} value {item.data:032b} does not match IRQ state {irqs:032b}\"\n )\n self.passed = False\n continue\n\n # IRQ state\n elif isinstance(item, IrqItem):\n irqs = item.irqs\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Increase iteration count\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", count * 2)\n\n # Add scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.reg_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.irq_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n@pyuvm.test()\nclass TestPending(BaseTest):\n \"\"\"\n Test reporting of pending IRQs\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TestSequence.create(\"stimulus\")\n\n async def run(self):\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n for i in range(count):\n await self.seq.start()\n await self.do_reset()\n" }, { "path": "verification/block/pic/test_prioritization.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport cocotb\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import (\n BaseEnv,\n BaseTest,\n BusReadItem,\n BusWriteItem,\n ClaimItem,\n IrqItem,\n PrioLvlItem,\n PriorityPredictor,\n PrioThrItem,\n RegisterMap,\n)\n\n# =============================================================================\n\n\nclass TestSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n self.reg_seqr = ConfigDB().get(None, \"\", \"REG_SEQR\")\n self.pri_seqr = ConfigDB().get(None, \"\", \"PRI_SEQR\")\n self.irq_seqr = ConfigDB().get(None, \"\", \"IRQ_SEQR\")\n\n self.regs = RegisterMap()\n\n async def body(self):\n num_irq = ConfigDB().get(None, \"\", \"PIC_NUM_INTERRUPTS\")\n max_pri = ConfigDB().get(None, \"\", \"PIC_NUM_PRIORITIES\")\n num_itr = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n ena_prob = ConfigDB().get(None, \"\", \"TEST_IRQ_ENA_PROB\")\n irq_prob = ConfigDB().get(None, \"\", \"TEST_IRQ_REQ_PROB\")\n\n # Basic PIC config\n item = BusWriteItem(self.regs.reg[\"mpiccfg\"], random.randint(0, 1))\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n for i in range(num_itr):\n # Randomize priorities\n for i in range(1, num_irq):\n reg = self.regs.reg[\"meipl{}\".format(i)]\n val = random.randint(0, max_pri)\n\n item = BusWriteItem(reg, val)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n # Randomize enables\n for i in range(1, num_irq):\n reg = self.regs.reg[\"meie{}\".format(i)]\n val = int(random.random() < ena_prob)\n\n item = BusWriteItem(reg, val)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n # Configure gateways\n for i in range(1, num_irq):\n reg = self.regs.reg[\"meigwctrl{}\".format(i)]\n val = 0x2 # Edge, active-high\n\n item = BusWriteItem(reg, val)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n # Randomize current priority and threshold\n lvl = random.randint(0, max_pri)\n thr = random.randint(0, max_pri)\n\n item = PrioLvlItem(lvl)\n await self.pri_seqr.start_item(item)\n await self.pri_seqr.finish_item(item)\n\n item = PrioThrItem(thr)\n await self.pri_seqr.start_item(item)\n await self.pri_seqr.finish_item(item)\n\n # Wait\n await ClockCycles(cocotb.top.clk, 4)\n\n # Randomize IRQ\n irqs = 0\n while irqs == 0:\n for i in range(1, num_irq):\n if random.random() > irq_prob:\n irqs |= 1 << i\n\n item = IrqItem(irqs)\n await self.irq_seqr.start_item(item)\n await self.irq_seqr.finish_item(item)\n\n # Wait\n await ClockCycles(cocotb.top.clk, 2)\n\n # Clear IRQ\n item = IrqItem(0)\n await self.irq_seqr.start_item(item)\n await self.irq_seqr.finish_item(item)\n\n # Wait\n await ClockCycles(cocotb.top.clk, 4)\n\n # Clear pending gateways\n for i in range(1, num_irq):\n if irqs & (1 << i):\n reg = self.regs.reg[\"meigwclr{}\".format(i)]\n val = 0\n\n item = BusWriteItem(reg, val)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n # Wait\n await ClockCycles(cocotb.top.clk, 5)\n\n\n# ==============================================================================\n\n\nclass Scoreboard(uvm_component):\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n self.predictor = PriorityPredictor(self.logger)\n self.regs = RegisterMap()\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n num_irq = ConfigDB().get(None, \"\", \"PIC_NUM_INTERRUPTS\")\n max_pri = ConfigDB().get(None, \"\", \"PIC_NUM_PRIORITIES\")\n\n pri_lvl = 0\n pri_thr = 0\n irqs = 0\n\n claimid = 0\n mexintpend = 0\n mhwakeup = 0\n\n while self.port.can_get():\n _, item = self.port.try_get()\n\n # Register write\n if isinstance(item, BusWriteItem):\n # Get the reg name\n reg = self.regs.adr.get(item.addr)\n if not reg:\n self.logger.error(\"Unknown register address 0x{:08X}\".format(item.addr))\n self.passed = False\n continue\n\n if reg.startswith(\"meipl\"):\n s = int(reg[5:])\n self.predictor.irqs[s].priority = item.data\n\n if reg.startswith(\"meie\"):\n s = int(reg[4:])\n self.predictor.irqs[s].enabled = bool(item.data)\n\n if reg == \"mpiccfg\":\n self.predictor.inv_order = bool(item.data)\n\n # Priority level\n elif isinstance(item, PrioLvlItem):\n pri_lvl = item.prio\n\n # Priority threshold\n elif isinstance(item, PrioThrItem):\n pri_thr = item.prio\n\n # IRQ\n elif isinstance(item, IrqItem):\n # Mark triggered interrupts\n for i in range(1, num_irq):\n if item.irqs & (1 << i):\n self.predictor.irqs[i].triggered = True\n\n # Store requested irqs\n if item.irqs != 0:\n irqs = item.irqs\n\n # Interrupt claim\n elif isinstance(item, ClaimItem):\n claimid = item.claimid\n mexintpend = item.mexintpend\n mhwakeup = item.mhwakeup\n\n # Check only if IRQs were requested\n if not irqs:\n continue\n irqs = 0\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n # Predict the claim\n pred = self.predictor.predict()\n\n # Check\n if claimid != pred.id:\n self.logger.error(\n \"Interrupt mismatch, is {} should be {}\".format(claimid, pred.id)\n )\n self.passed = False\n\n # Check if the interrupt is above the current priority level\n # and threshold. Check if it is signaled correctly.\n else:\n # Predict mexintpend\n if self.predictor.inv_order:\n pred_mexintpend = (\n pred.id != 0\n and pred.priority != max_pri\n and pred.priority < pri_thr\n and pred.priority < pri_lvl\n )\n else:\n pred_mexintpend = (\n pred.id != 0\n and pred.priority != 0\n and pred.priority > pri_thr\n and pred.priority > pri_lvl\n )\n\n # Predict mhwakeup\n if self.predictor.inv_order:\n pred_mhwakeup = pred.id != 0 and pred.priority == 0\n else:\n pred_mhwakeup = pred.id != 0 and pred.priority == max_pri\n\n # Check\n if pred_mexintpend != mexintpend:\n self.logger.error(\n \"Signaling mismatch, mexintpend is {} should be {}. irq {}, meicurpl={}, meipt={}\".format(\n bool(mexintpend),\n bool(pred_mexintpend),\n pred.id,\n pri_lvl,\n pri_thr,\n )\n )\n self.passed = False\n\n if pred_mhwakeup != mhwakeup:\n self.logger.error(\n \"Signaling mismatch, mhwakeup is {} should be {}. irq {}, meicurpl={}, meipt={}\".format(\n bool(mhwakeup),\n bool(pred_mhwakeup),\n pred.id,\n pri_lvl,\n pri_thr,\n )\n )\n self.passed = False\n\n # Clear triggers\n for i in range(1, num_irq):\n self.predictor.irqs[i].triggered = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Add scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.reg_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.pri_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.irq_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.claim_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n@pyuvm.test()\nclass TestPrioritization(BaseTest):\n \"\"\" \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TestSequence.create(\"stimulus\")\n\n async def run(self):\n await self.seq.start()\n" }, { "path": "verification/block/pic/test_reset.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nimport cocotb\nimport pyuvm\nfrom testbench import BaseTest\n\n# =============================================================================\n\n\n@pyuvm.test()\nclass TestReset(BaseTest):\n \"\"\"\n A basic test that resets the DUT\n \"\"\"\n\n async def run(self):\n # Check state of DUT signals after reset\n state = {\n \"mexintpend\": 0,\n \"mhwakeup\": 0,\n \"pl\": 0,\n \"claimid\": 0,\n }\n\n for name, value in state.items():\n signal = getattr(cocotb.top, name)\n assert signal.value == value, \"{}={}, should be {}\".format(name, signal.value, value)\n" }, { "path": "verification/block/pic/test_servicing.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport cocotb\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import (\n BaseEnv,\n BaseTest,\n BusReadItem,\n BusWriteItem,\n ClaimItem,\n IrqItem,\n PrioLvlItem,\n PriorityPredictor,\n PrioThrItem,\n RegisterMap,\n)\n\n# =============================================================================\n\n\nclass TestSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n self.reg_seqr = ConfigDB().get(None, \"\", \"REG_SEQR\")\n self.pri_seqr = ConfigDB().get(None, \"\", \"PRI_SEQR\")\n self.irq_seqr = ConfigDB().get(None, \"\", \"IRQ_SEQR\")\n\n self.regs = RegisterMap()\n\n async def body(self):\n num_irq = ConfigDB().get(None, \"\", \"PIC_NUM_INTERRUPTS\")\n max_pri = ConfigDB().get(None, \"\", \"PIC_NUM_PRIORITIES\")\n num_itr = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n ena_prob = ConfigDB().get(None, \"\", \"TEST_IRQ_ENA_PROB\")\n\n # Basic PIC config\n item = BusWriteItem(self.regs.reg[\"mpiccfg\"], 0)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n predictor = PriorityPredictor()\n enabled_irqs = list()\n\n for i in range(num_itr):\n # Randomize priorities\n for i in range(1, num_irq):\n reg = self.regs.reg[\"meipl{}\".format(i)]\n val = random.randint(0, max_pri)\n\n predictor.irqs[i].priority = val\n\n item = BusWriteItem(reg, val)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n # Randomize enables\n for i in range(1, num_irq):\n reg = self.regs.reg[\"meie{}\".format(i)]\n val = int(random.random() < ena_prob)\n\n predictor.irqs[i].enabled = val\n\n if val:\n enabled_irqs.append(i)\n\n item = BusWriteItem(reg, val)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n # Configure gateways\n for i in range(1, num_irq):\n reg = self.regs.reg[\"meigwctrl{}\".format(i)]\n val = 0x2 # Edge, active-high\n\n item = BusWriteItem(reg, val)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n # Set interrupt threshold\n item = PrioThrItem(random.randint(0, max_pri))\n await self.pri_seqr.start_item(item)\n await self.pri_seqr.finish_item(item)\n\n # Wait\n await ClockCycles(cocotb.top.clk, 4)\n\n # Request IRQs\n irqs = 0\n for i in enabled_irqs:\n predictor.irqs[i].triggered = val\n irqs |= 1 << i\n\n item = IrqItem(irqs)\n await self.irq_seqr.start_item(item)\n await self.irq_seqr.finish_item(item)\n\n # Wait\n await ClockCycles(cocotb.top.clk, 2)\n\n # Clear IRQ\n item = IrqItem(0)\n await self.irq_seqr.start_item(item)\n await self.irq_seqr.finish_item(item)\n\n # Wait\n await ClockCycles(cocotb.top.clk, 4)\n\n # Mimic interrupt servicing\n for i in range(50): # Limit iterations\n # Predict the IRQ to be serviced\n irq = predictor.predict()\n if irq.id == 0:\n break\n\n # Begin servicing, set meicurpl\n item = PrioLvlItem(irq.priority)\n await self.pri_seqr.start_item(item)\n await self.pri_seqr.finish_item(item)\n\n # Servicing period\n await ClockCycles(cocotb.top.clk, 5)\n\n # Finish servicing, set meicurpl to 0\n item = PrioLvlItem(0)\n await self.pri_seqr.start_item(item)\n await self.pri_seqr.finish_item(item)\n\n # Clear pending\n reg = self.regs.reg[\"meigwclr{}\".format(irq.id)]\n val = 0\n\n item = BusWriteItem(reg, val)\n await self.reg_seqr.start_item(item)\n await self.reg_seqr.finish_item(item)\n\n predictor.irqs[irq.id].triggered = False\n\n await ClockCycles(cocotb.top.clk, 4)\n\n\n# ==============================================================================\n\n\nclass Scoreboard(uvm_component):\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n self.predictor = PriorityPredictor(self.logger)\n self.regs = RegisterMap()\n\n def build_phase(self):\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n num_irq = ConfigDB().get(None, \"\", \"PIC_NUM_INTERRUPTS\")\n\n pri_thr = 0\n\n irq_order = []\n\n while self.port.can_get():\n _, item = self.port.try_get()\n\n # Register write\n if isinstance(item, BusWriteItem):\n # Get the reg name\n reg = self.regs.adr.get(item.addr)\n if not reg:\n self.logger.error(\"Unknown register address 0x{:08X}\".format(item.addr))\n self.passed = False\n continue\n\n if reg.startswith(\"meipl\"):\n s = int(reg[5:])\n self.predictor.irqs[s].priority = item.data\n\n if reg.startswith(\"meie\"):\n s = int(reg[4:])\n self.predictor.irqs[s].enabled = bool(item.data)\n\n # Priority threshold\n elif isinstance(item, PrioThrItem):\n pri_thr = item.prio\n\n # IRQ\n elif isinstance(item, IrqItem):\n # Nothing triggered\n if not item.irqs:\n continue\n\n # Mark triggered interrupts\n for i in range(1, num_irq):\n if item.irqs & (1 << i):\n self.predictor.irqs[i].triggered = True\n\n # Predict the order of interrupt servicing\n for i in range(50): # Limit iterations\n # Predict the IRQ to be serviced\n irq = self.predictor.predict()\n if irq.id == 0:\n break\n\n irq_order.append(irq.id)\n\n # Clear pending\n self.predictor.irqs[irq.id].triggered = False\n\n self.logger.debug(\"Interrupt order: {}\".format(irq_order))\n\n # Interrupt claim\n elif isinstance(item, ClaimItem):\n # Not waiting for any interrupt\n if not irq_order:\n continue\n\n # Initially pass\n if self.passed is None:\n self.passed = True\n\n self.logger.debug(\n \"Servicing {}, mexintpend={}\".format(\n item.claimid,\n item.mexintpend,\n )\n )\n\n # check id\n if item.claimid != irq_order[0]:\n self.logger.error(\n \"Incorrect interrupt servicing order, claimed {} should be {}\".format(\n item.claimid, irq_order[0]\n )\n )\n self.passed = False\n\n # mexintpend must be set\n if not item.mexintpend and item.claimpl > pri_thr:\n self.logger.error(\"Interrupt not reported to the core\")\n self.passed = False\n\n # Remove the serviced id\n irq_order = irq_order[1:]\n\n # Check if all interrupts were services\n if irq_order:\n self.logger.error(\"Interrupts {} were not serviced\".format(irq_order))\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass TestEnv(BaseEnv):\n def build_phase(self):\n super().build_phase()\n\n # Add scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n super().connect_phase()\n\n # Connect monitors\n self.reg_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.pri_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.irq_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n self.claim_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n@pyuvm.test()\nclass TestServicing(BaseTest):\n \"\"\" \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, TestEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TestSequence.create(\"stimulus\")\n\n async def run(self):\n await self.seq.start()\n" }, { "path": "verification/block/pic/testbench.py", "content": "#\n# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport os\n\nimport pyuvm\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, FallingEdge, RisingEdge\nfrom pyuvm import *\n\n# ==============================================================================\n\n\nclass RegisterMap:\n \"\"\"\n Map of PIC memory-mapped registers\n \"\"\"\n\n def __init__(self, max_irqs=32, base_addr=0xF00C0000):\n self.reg = dict()\n self.adr = dict()\n\n self.add_reg(\"mpiccfg\", base_addr + 0x3000)\n\n for s in range(1, max_irqs):\n name = \"meipl{}\".format(s)\n addr = base_addr + 4 * s\n self.add_reg(name, addr)\n\n for x in range(0, max_irqs // 32):\n name = \"meip{}\".format(x)\n addr = base_addr + 0x1000 + 4 * x\n self.add_reg(name, addr)\n\n for s in range(1, max_irqs):\n name = \"meie{}\".format(s)\n addr = base_addr + 0x2000 + 4 * s\n self.add_reg(name, addr)\n\n for s in range(1, max_irqs):\n name = \"meigwctrl{}\".format(s)\n addr = base_addr + 0x4000 + 4 * s\n self.add_reg(name, addr)\n\n for s in range(1, max_irqs):\n name = \"meigwclr{}\".format(s)\n addr = base_addr + 0x5000 + 4 * s\n self.add_reg(name, addr)\n\n def add_reg(self, name, addr):\n self.reg[name] = addr\n self.adr[addr] = name\n\n\n# ==============================================================================\n\n\nclass BusWriteItem(uvm_sequence_item):\n \"\"\"\n A generic data bus write request / response\n \"\"\"\n\n def __init__(self, addr, data):\n super().__init__(\"BusWriteItem\")\n self.addr = addr\n self.data = data\n\n def randomize(self):\n pass\n\n\nclass BusReadItem(uvm_sequence_item):\n \"\"\"\n A generic data bus read request / response\n \"\"\"\n\n def __init__(self, addr, data=None):\n super().__init__(\"BusReadItem\")\n self.addr = addr\n self.data = data\n\n def randomize(self):\n pass\n\n\nclass PrioLvlItem(uvm_sequence_item):\n def __init__(self, prio):\n super().__init__(\"PrioLvlItem\")\n self.prio = prio\n\n\nclass PrioThrItem(uvm_sequence_item):\n def __init__(self, prio):\n super().__init__(\"PrioThrItem\")\n self.prio = prio\n\n\nclass IrqItem(uvm_sequence_item):\n def __init__(self, irqs):\n super().__init__(\"IrqItem\")\n self.irqs = irqs\n\n\nclass ClaimItem(uvm_sequence_item):\n def __init__(self, claimid, claimpl, mexintpend, mhwakeup):\n super().__init__(\"ClaimItem\")\n self.claimid = claimid\n self.claimpl = claimpl\n\n self.mexintpend = mexintpend\n self.mhwakeup = mhwakeup\n\n\nclass WaitItem(uvm_sequence_item):\n \"\"\"\n A generic wait item. Used to instruct a driver to wait N cycles\n \"\"\"\n\n def __init__(self, cycles):\n super().__init__(\"WaitItem\")\n self.cycles = cycles\n\n def randomize(self):\n pass\n\n\n# ==============================================================================\n\n\ndef collect_signals(signals, uut, obj):\n \"\"\"\n Collects signal objects from UUT and attaches them to the given object\n \"\"\"\n\n for sig in signals:\n if hasattr(uut, sig):\n s = getattr(uut, sig)\n\n else:\n s = None\n logging.error(\"Module {} does not have a signal '{}'\".format(str(uut), sig))\n\n setattr(obj, sig, s)\n\n\n# ==============================================================================\n\n\nclass RegisterBfm:\n \"\"\"\n A BFM for the PIC configuration (registers) interface.\n \"\"\"\n\n SIGNALS = [\n \"picm_rden\",\n \"picm_rdaddr\",\n \"picm_rd_data\",\n \"picm_wren\",\n \"picm_wraddr\",\n \"picm_wr_data\",\n \"picm_mken\",\n ]\n\n def __init__(self, uut, clk):\n # Collect signals\n collect_signals(self.SIGNALS, uut, self)\n\n # Get the clock\n obj = getattr(uut, clk)\n setattr(self, \"picm_clk\", obj)\n\n async def read(self, addr):\n \"\"\"\n Reads a register\n \"\"\"\n\n await RisingEdge(self.picm_clk)\n\n self.picm_rdaddr.value = addr\n self.picm_rden.value = 1\n self.picm_mken.value = 0\n\n await RisingEdge(self.picm_clk)\n\n self.picm_rden.value = 0\n\n await FallingEdge(self.picm_clk)\n\n data = self.picm_rd_data.value\n\n return data\n\n async def write(self, addr, data):\n \"\"\"\n Writes a register\n \"\"\"\n\n await RisingEdge(self.picm_clk)\n\n self.picm_wraddr.value = addr\n self.picm_wr_data.value = data\n self.picm_wren.value = 1\n self.picm_mken.value = 0\n\n await RisingEdge(self.picm_clk)\n\n self.picm_wren.value = 0\n\n\nclass RegisterDriver(uvm_driver):\n \"\"\"\n Configuration (register) interface driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.bfm = kwargs[\"bfm\"]\n del kwargs[\"bfm\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, BusWriteItem):\n await self.bfm.write(it.addr, it.data)\n elif isinstance(it, BusReadItem):\n it.data = await self.bfm.read(it.addr)\n elif isinstance(it, WaitItem):\n await ClockCycles(self.bfm.picm_clk)\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass RegisterMonitor(uvm_component):\n \"\"\"\n Configuration (register) interface monitor\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.bfm = kwargs[\"bfm\"]\n del kwargs[\"bfm\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n await RisingEdge(self.bfm.picm_clk)\n\n # Read\n if self.bfm.picm_rden.value:\n addr = int(self.bfm.picm_rdaddr.value)\n\n await FallingEdge(self.bfm.picm_clk)\n\n data = int(self.bfm.picm_rd_data.value)\n self.logger.debug(\"read 0x{:08X} -> 0x{:08X}\".format(addr, data))\n self.ap.write(BusReadItem(addr, data))\n\n # Write\n if self.bfm.picm_wren.value:\n addr = int(self.bfm.picm_wraddr.value)\n data = int(self.bfm.picm_wr_data.value)\n self.logger.debug(\"write 0x{:08X} <- 0x{:08X}\".format(addr, data))\n self.ap.write(BusWriteItem(addr, data))\n\n\n# ==============================================================================\n\n\nclass PrioDriver(uvm_driver):\n \"\"\"\n A driver for priority and priority threshold inputs of the PIC\n \"\"\"\n\n SIGNALS = [\n \"meicurpl\",\n \"meipt\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, PrioLvlItem):\n self.meicurpl.value = it.prio\n elif isinstance(it, PrioThrItem):\n self.meipt.value = it.prio\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass PrioMonitor(uvm_component):\n \"\"\"\n A monitor for priority and priority threshold of the PIC\n \"\"\"\n\n SIGNALS = [\n \"clk\",\n \"meicurpl\",\n \"meipt\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n self.prev_meicurpl = None\n self.prev_meipt = None\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Even though the signals are not registered sample them on\n # rising clock edge\n await RisingEdge(self.clk)\n\n # Sample signals\n curr_meicurpl = int(self.meicurpl.value)\n curr_meipt = int(self.meipt.value)\n\n # Send an item in case of a change\n if self.prev_meicurpl != curr_meicurpl:\n self.ap.write(PrioLvlItem(curr_meicurpl))\n if self.prev_meipt != curr_meipt:\n self.ap.write(PrioThrItem(curr_meipt))\n\n self.prev_meicurpl = curr_meicurpl\n self.prev_meipt = curr_meipt\n\n\n# ==============================================================================\n\n\nclass IrqDriver(uvm_driver):\n \"\"\"\n A driver for interrupt requests\n \"\"\"\n\n SIGNALS = [\n \"extintsrc_req\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, IrqItem):\n self.extintsrc_req.value = it.irqs\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\nclass IrqMonitor(uvm_component):\n \"\"\"\n A monitor for interrupt requests\n \"\"\"\n\n SIGNALS = [\n \"clk\",\n \"extintsrc_req\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n self.prev_irqs = None\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Sample signals\n await RisingEdge(self.clk)\n curr_irqs = int(self.extintsrc_req.value)\n\n # Send an item in case of a change\n if self.prev_irqs != curr_irqs:\n self.ap.write(IrqItem(curr_irqs))\n\n self.prev_irqs = curr_irqs\n\n\n# ==============================================================================\n\n\nclass ClaimMonitor(uvm_component):\n SIGNALS = [\n \"clk\",\n \"extintsrc_req\",\n \"picm_wren\",\n \"claimid\",\n \"pl\",\n \"mexintpend\",\n \"mhwakeup\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n self.prev_irqs = 0\n self.prev_wren = 0\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n # Sample control signals\n await RisingEdge(self.clk)\n irqs = int(self.extintsrc_req.value)\n wren = int(self.picm_wren.value)\n\n is_wren = wren and not self.prev_wren # Rising edge of wren\n is_irqs = irqs & ~self.prev_irqs # Rising edge of any IRQ\n\n if is_wren or is_irqs:\n # Sample signals after a delay to give PIC time to react.\n # It was observed that in the simulation that the wait must\n # be at least 3 clock cycles long.\n await ClockCycles(self.clk, 3)\n\n claimid = int(self.claimid.value)\n claimpl = int(self.pl.value)\n mexintpend = int(self.mexintpend.value)\n mhwakeup = int(self.mhwakeup.value)\n\n self.ap.write(ClaimItem(claimid, claimpl, mexintpend, mhwakeup))\n\n self.prev_irqs = irqs\n self.prev_wren = wren\n\n\n# ==============================================================================\n\n\nclass PriorityPredictor:\n class Irq:\n \"\"\"\n Interrupt request state\n \"\"\"\n\n def __init__(self, n):\n self.id = n\n self.priority = 0\n self.enabled = False\n self.triggered = False\n\n def __str__(self):\n return \"id={:3d} en={} pri={:2d} trg={}\".format(\n self.id,\n int(self.enabled),\n self.priority,\n int(self.triggered),\n )\n\n def __repr__(self):\n return str(self)\n\n def __init__(self, logger=None):\n self.inv_order = False\n self.irqs = {i: self.Irq(i) for i in range(1, 32)}\n self.logger = logger\n\n if self.logger is None:\n self.logger = uvm_root().logger\n\n def predict(self):\n # Dump IRQs\n self.logger.debug(\"IRQs:\")\n keys = sorted(list(self.irqs))\n for k in keys:\n self.logger.debug(\" \" + str(self.irqs[k]))\n\n # Filter only enabled and triggered\n irqs = {k: v for k, v in self.irqs.items() if v.enabled and v.triggered}\n\n # Get the highest priority\n pred = None\n for irq in irqs.values():\n # Skip priority 0 or 15\n if self.inv_order:\n if irq.priority == 15:\n continue\n else:\n if irq.priority == 0:\n continue\n\n # Find max priority and min id\n if pred is None:\n pred = irq\n else:\n if self.inv_order:\n if irq.priority < pred.priority:\n pred = irq\n else:\n if irq.priority > pred.priority:\n pred = irq\n\n if irq.priority == pred.priority:\n if irq.id < pred.id:\n pred = irq\n\n if pred is None:\n return self.Irq(0)\n\n self.logger.debug(\"pred:\")\n self.logger.debug(\" \" + str(pred))\n\n return pred\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"PIC_NUM_INTERRUPTS\", 32)\n ConfigDB().set(None, \"*\", \"PIC_NUM_PRIORITIES\", 15)\n\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 50)\n ConfigDB().set(None, \"*\", \"TEST_IRQ_ENA_PROB\", 0.75)\n ConfigDB().set(None, \"*\", \"TEST_IRQ_REQ_PROB\", 0.90)\n\n # Sequencers\n self.reg_seqr = uvm_sequencer(\"reg_seqr\", self)\n self.pri_seqr = uvm_sequencer(\"pri_seqr\", self)\n self.irq_seqr = uvm_sequencer(\"irq_seqr\", self)\n\n # Register interface\n bfm = RegisterBfm(cocotb.top, \"clk\")\n self.reg_drv = RegisterDriver(\"reg_drv\", self, bfm=bfm)\n self.reg_mon = RegisterMonitor(\"reg_mon\", self, bfm=bfm)\n\n # Current priority and priority threshold interface\n self.pri_drv = PrioDriver(\"pri_drv\", self, uut=cocotb.top)\n self.pri_mon = PrioMonitor(\"pri_mon\", self, uut=cocotb.top)\n\n # Interrupt request\n self.irq_drv = IrqDriver(\"irq_drv\", self, uut=cocotb.top)\n self.irq_mon = IrqMonitor(\"irq_mon\", self, uut=cocotb.top)\n\n # Interrupt claim monitor\n self.claim_mon = ClaimMonitor(\"claim_mon\", self, uut=cocotb.top)\n\n ConfigDB().set(None, \"*\", \"REG_SEQR\", self.reg_seqr)\n ConfigDB().set(None, \"*\", \"PRI_SEQR\", self.pri_seqr)\n ConfigDB().set(None, \"*\", \"IRQ_SEQR\", self.irq_seqr)\n\n def connect_phase(self):\n self.reg_drv.seq_item_port.connect(self.reg_seqr.seq_item_export)\n self.pri_drv.seq_item_port.connect(self.pri_seqr.seq_item_export)\n self.irq_drv.seq_item_port.connect(self.irq_seqr.seq_item_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n\n cocotb.top.free_clk.value = 0\n cocotb.top.clk_override.value = 0\n cocotb.top.io_clk_override.value = 0\n cocotb.top.extintsrc_req.value = 0\n cocotb.top.picm_rdaddr.value = 0\n cocotb.top.picm_wraddr.value = 0\n cocotb.top.picm_wr_data.value = 0\n cocotb.top.picm_wren.value = 0\n cocotb.top.picm_rden.value = 0\n cocotb.top.picm_mken.value = 0\n cocotb.top.meicurpl.value = 0\n cocotb.top.meipt.value = 0\n cocotb.top.scan_mode.value = 0\n\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n self.start_clock(\"free_clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/pic_gw/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_configurable_gw\n\nVERILOG_SOURCES = \\\n $(SRCDIR)/el2_pic_ctrl.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/pic_gw/test_gateway.py", "content": "#\n# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport os\n\nimport cocotb\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, FallingEdge\n\n# ==============================================================================\n\n\nasync def start_clocks(dut):\n \"\"\"\n Starts DUT clocks\n \"\"\"\n\n # When VeeR is built in FPGA-optimized mode rawclk is used by rvdffs inside\n # the gateway. Otherwise the gw_clk is used. For testing start both of them.\n gw_clk = Clock(dut.gw_clk, 1, units=\"ns\")\n rawclk = Clock(dut.rawclk, 1, units=\"ns\")\n\n cocotb.start_soon(gw_clk.start(start_high=False))\n cocotb.start_soon(rawclk.start(start_high=False))\n\n # Enable\n cocotb.top.clken.value = 1\n\n\nasync def do_reset(dut):\n \"\"\"\n Resets the DUT\n \"\"\"\n\n await ClockCycles(dut.gw_clk, 2)\n\n dut.rst_l.value = 0\n\n await ClockCycles(dut.gw_clk, 1)\n await FallingEdge(dut.gw_clk)\n\n dut.rst_l.value = 1\n\n\nasync def clear_pending(dut):\n \"\"\"\n Clears the pending interrupt flag of the tested module\n \"\"\"\n\n dut.meigwclr.value = 1\n await ClockCycles(dut.gw_clk, 1)\n dut.meigwclr.value = 0\n\n await ClockCycles(dut.gw_clk, 3)\n\n\n# ==============================================================================\n\n\nasync def test_level(dut, pol):\n \"\"\"\n Tests level-sensitive interrupt\n \"\"\"\n\n # Default state\n dut.extintsrc_req.value = not pol\n\n # Level-sensitive\n dut.meigwctrl_type.value = 0\n dut.meigwctrl_polarity.value = not pol\n\n # Reset\n await do_reset(dut)\n\n # Wait\n await ClockCycles(dut.gw_clk, 3)\n\n # The request should not be pending\n assert dut.extintsrc_req_config.value == 0\n\n # Request an interrupt\n dut.extintsrc_req.value = pol\n await ClockCycles(dut.gw_clk, 3)\n\n # The request should be pending now\n assert dut.extintsrc_req_config.value == 1\n\n # Clear the pending bit\n await clear_pending(dut)\n\n # The request should be still pending (level sensitive)\n assert dut.extintsrc_req_config.value == 1\n\n # Cancel the request\n dut.extintsrc_req.value = not pol\n await ClockCycles(dut.gw_clk, 3)\n\n # The request should be still pending (latched state)\n # assert dut.extintsrc_req_config.value == 1\n\n # FIXME: It appears that the gateway does not latch the trigger state\n # in level-sensitive mode but rather passes through the interrupt request\n # signal.\n assert dut.extintsrc_req_config.value == 0\n\n # Clear the pending bit again\n await clear_pending(dut)\n\n # The request should not be pending now\n assert dut.extintsrc_req_config.value == 0\n\n # Wait\n await ClockCycles(dut.gw_clk, 3)\n\n\n@cocotb.test()\nasync def test_level_hi(dut):\n await start_clocks(dut)\n await test_level(dut, True)\n\n\n@cocotb.test()\nasync def test_level_lo(dut):\n await start_clocks(dut)\n await test_level(dut, False)\n\n\nasync def test_edge(dut, pol):\n \"\"\"\n Tests edge-sensitive interrupt\n \"\"\"\n\n # Default state\n dut.extintsrc_req.value = not pol\n\n # Edge-sensitive\n dut.meigwctrl_type.value = 1\n dut.meigwctrl_polarity.value = not pol\n\n # Reset\n await do_reset(dut)\n\n # Wait\n await ClockCycles(dut.gw_clk, 3)\n\n # The request should not be pending\n assert dut.extintsrc_req_config.value == 0\n\n # Request an interrupt\n dut.extintsrc_req.value = pol\n await ClockCycles(dut.gw_clk, 1)\n dut.extintsrc_req.value = not pol\n\n await ClockCycles(dut.gw_clk, 3)\n\n # The request should be pending now\n assert dut.extintsrc_req_config.value == 1\n\n # Wait\n await ClockCycles(dut.gw_clk, 10)\n\n # The request should still be pending now\n assert dut.extintsrc_req_config.value == 1\n\n # Clear the pending bit\n await clear_pending(dut)\n\n # The request should not be pending now\n assert dut.extintsrc_req_config.value == 0\n\n # Wait\n await ClockCycles(dut.gw_clk, 3)\n\n\n@cocotb.test()\nasync def test_edge_rising(dut):\n await start_clocks(dut)\n await test_edge(dut, True)\n\n\n# @cocotb.test() # TODO: Falling edge case is failing. Re-enable upon RTL fix\nasync def test_edge_falling(dut):\n await start_clocks(dut)\n await test_edge(dut, False)\n\n\nasync def test_edge_reset(dut, pol):\n \"\"\"\n Tests edge-sensitive interrupt\n \"\"\"\n\n # Default state\n dut.extintsrc_req.value = not pol\n\n # Edge-sensitive\n dut.meigwctrl_type.value = 1\n dut.meigwctrl_polarity.value = not pol\n\n # Reset\n await do_reset(dut)\n\n # Wait\n await ClockCycles(dut.gw_clk, 3)\n\n # The request should not be pending\n assert dut.extintsrc_req_config.value == 0\n\n # Request an interrupt\n dut.extintsrc_req.value = pol\n await ClockCycles(dut.gw_clk, 1)\n dut.extintsrc_req.value = not pol\n\n await ClockCycles(dut.gw_clk, 3)\n\n # The request should be pending now\n assert dut.extintsrc_req_config.value == 1\n\n # Wait\n await ClockCycles(dut.gw_clk, 10)\n\n # Reset\n await do_reset(dut)\n\n # Wait\n await ClockCycles(dut.gw_clk, 3)\n\n # The request should not be pending now\n assert dut.extintsrc_req_config.value == 0\n\n # Wait\n await ClockCycles(dut.gw_clk, 3)\n\n\n@cocotb.test()\nasync def test_edge_rising_reset(dut):\n await start_clocks(dut)\n await test_edge_reset(dut, True)\n\n\n# @cocotb.test() # TODO: Falling edge case is failing. Re-enable upon RTL fix\nasync def test_edge_falling_reset(dut):\n await start_clocks(dut)\n await test_edge_reset(dut, False)\n" }, { "path": "verification/block/pmp/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_pmp_wrapper\n\nVERILOG_SOURCES = \\\n $(TEST_DIR)/el2_pmp_wrapper.sv \\\n $(SRCDIR)/el2_pmp.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/pmp/common.py", "content": "from random import randrange\n\nfrom pyuvm import ConfigDB, uvm_sequence\nfrom testbench import PMPCheckItem\n\n\nclass BaseSequence(uvm_sequence):\n MAX_ADDR = 2**32 - 4\n\n def __init__(self, name):\n super().__init__(name)\n\n self.pmp_regs = ConfigDB().get(None, \"\", \"PMP_CSRS\")\n self.pmp_seqr = ConfigDB().get(None, \"\", \"PMP_SEQR\")\n self.pmp_channels = ConfigDB().get(None, \"\", \"PMP_CHANNELS\")\n\n # Access (R, W, X) memory at a given address on all channels\n async def accessAtAddr(self, addr):\n for t in range(3):\n type = 1 << t\n for c in range(self.pmp_channels):\n item = PMPCheckItem(channel=c, addr=addr, type=type)\n await self.pmp_seqr.start_item(item)\n await self.pmp_seqr.finish_item(item)\n\n # Try to access memory at random locations in a given address range\n async def randomAccessInAddrRange(self, start_addr, end_addr):\n addr = randrange(start_addr, end_addr, 4)\n await self.accessAtAddr(addr)\n\n # Access memory at a given address and at adjacent addresses\n async def checkRangeBoundary(self, addr):\n # Ensure access address is always aligned and doesn't extend 32 bits,\n # address is assumed to be inclusive so increment it by 1 initially.\n addr = min(self.MAX_ADDR, (addr + 1) & 0xFFFFFFFC)\n\n if addr >= 4:\n await self.accessAtAddr(addr - 4)\n await self.accessAtAddr(addr)\n if addr < self.MAX_ADDR:\n await self.accessAtAddr(addr + 4)\n" }, { "path": "verification/block/pmp/config.vlt", "content": "`verilator_config\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_pmp_wrapper.sv\"\n" }, { "path": "verification/block/pmp/el2_pmp_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro\n// SPDX-License-Identifier: Apache-2.0\n\nmodule el2_pmp_wrapper\n import el2_pkg::*;\n#(\n parameter PMP_CHANNELS = 3,\n `include \"el2_param.vh\"\n) (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n input logic scan_mode, // Scan mode\n\n input [7:0] pmp_pmpcfg [pt.PMP_ENTRIES],\n input logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],\n\n input logic [ 31:0] pmp_chan_addr[PMP_CHANNELS],\n input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS],\n output logic [PMP_CHANNELS-1:0] pmp_chan_err\n);\n logic pmp_chan_err_unpacked[PMP_CHANNELS];\n el2_pmp_cfg_pkt_t pmp_pmpcfg_int [pt.PMP_ENTRIES];\n\n for (genvar c = 0; c < PMP_CHANNELS; c++) begin\n assign pmp_chan_err[PMP_CHANNELS-1-c] = pmp_chan_err_unpacked[c];\n end\n\n for (genvar e = 0; e < pt.PMP_ENTRIES; e++) begin\n assign pmp_pmpcfg_int[e].lock = pmp_pmpcfg[e][7];\n assign pmp_pmpcfg_int[e].reserved = pmp_pmpcfg[e][6:5];\n assign pmp_pmpcfg_int[e].mode = el2_pkg::el2_pmp_mode_pkt_t'(pmp_pmpcfg[e][4:3]);\n assign pmp_pmpcfg_int[e].execute = pmp_pmpcfg[e][2];\n assign pmp_pmpcfg_int[e].write = pmp_pmpcfg[e][1];\n assign pmp_pmpcfg_int[e].read= pmp_pmpcfg[e][0];\n end\n\n // The PMP module\n el2_pmp pmp (\n .pmp_chan_err(pmp_chan_err_unpacked),\n .pmp_pmpcfg(pmp_pmpcfg_int),\n .*\n );\n\nendmodule\n" }, { "path": "verification/block/pmp/test_address_matching.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\n\nfrom pyuvm import ConfigDB, test\nfrom testbench import (\n BaseEnv,\n BaseTest,\n PMPWriteAddrCSRItem,\n PMPWriteCfgCSRItem,\n getDecodedEntryCfg,\n)\n\nfrom common import BaseSequence\n\npmp_configurations = [\n {\n # 0 - Entry locked but disabled, address 0x1000\n \"pmpcfg\": 0b10000000,\n \"pmpaddr\": (0x1000 >> 2),\n },\n {\n # 1 - Entry locked, allow RWX, TOR, address range 0x1000-0x1FFF\n \"pmpcfg\": 0b10001111,\n \"pmpaddr\": (0x2000 >> 2),\n },\n {\n # 2 - Entry locked, allow R, TOR, address range 0x2000-0x3FFF\n \"pmpcfg\": 0b10001001,\n \"pmpaddr\": (0x4000 >> 2),\n },\n {\n # 3 - Entry locked, allow X, TOR, address range 0x4000-0xFFFF\n \"pmpcfg\": 0b10001100,\n \"pmpaddr\": (0x10000 >> 2),\n },\n {\n # 4 - Entry locked, allow W, TOR, address range 0x10000-0x1FFFF\n \"pmpcfg\": 0b10001010,\n \"pmpaddr\": (0x20000 >> 2),\n },\n {\n # 5 - Entry unlocked, allow none, TOR, address range 0x20000-0xFFFFFFFF\n \"pmpcfg\": 0b00001000,\n \"pmpaddr\": (0x100000000 >> 2),\n },\n {\n # 6 - Entry locked, allow none, TOR, address range 0xFFFFFFFF-0x10000\n \"pmpcfg\": 0b10001000,\n \"pmpaddr\": (0x20000 >> 2),\n },\n {\n # 7 - Entry locked, allow RWX, NA4, address range 0x20000-0x20003\n \"pmpcfg\": 0b10010111,\n \"pmpaddr\": (0x20000 >> 2),\n },\n {\n # 8 - Entry locked, allow none, NA4, address range 0x30000-0x30003\n \"pmpcfg\": 0b10010000,\n \"pmpaddr\": (0x30000 >> 2),\n },\n {\n # 9 - Entry locked, allow none, NAPOT, address range 0x40000-0x5FFFF\n \"pmpcfg\": 0b10011000,\n \"pmpaddr\": (0x57FFF >> 2),\n },\n {\n # 10 - Entry locked, allow RW, NAPOT, address range 0x24000-0x25FFF\n \"pmpcfg\": 0b10011011,\n \"pmpaddr\": (0x257FF >> 2),\n },\n {\n # 11 - Entry locked, allow X, NAPOT, address range 0x26000-0x26FFF\n \"pmpcfg\": 0b10011100,\n \"pmpaddr\": (0x26BFF >> 2),\n },\n {\n # 12 - Entry locked, allow RW, NAPOT, address range 0x26000-0x26FFF\n \"pmpcfg\": 0b10011011,\n \"pmpaddr\": (0x26BFF >> 2),\n },\n]\n\n\n# =============================================================================\n\n\nclass TestSequence(BaseSequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n test_iterations = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n pmp_entries = ConfigDB().get(None, \"\", \"PMP_ENTRIES\")\n\n # Ensure to not use more configurations than PMP entries\n assert len(pmp_configurations) <= pmp_entries\n\n # Configure PMP entries\n for i, cfg in enumerate(pmp_configurations):\n item = PMPWriteAddrCSRItem(index=i, pmpaddr=cfg[\"pmpaddr\"])\n await self.pmp_seqr.start_item(item)\n await self.pmp_seqr.finish_item(item)\n\n for i, cfg in enumerate(pmp_configurations):\n item = PMPWriteCfgCSRItem(index=i, pmpcfg=cfg[\"pmpcfg\"])\n await self.pmp_seqr.start_item(item)\n await self.pmp_seqr.finish_item(item)\n\n # Check boundaries and few random addresses of each PMP entry\n for i in range(len(pmp_configurations)):\n start_addr, end_addr = getDecodedEntryCfg(self.pmp_regs, i, range_only=True)\n\n await self.checkRangeBoundary(start_addr)\n\n # Access up to 10 random memory cells\n accesses = min((end_addr - start_addr) // 4, 10)\n if start_addr != end_addr:\n for _ in range(accesses):\n await self.randomAccessInAddrRange(start_addr, end_addr)\n\n await self.checkRangeBoundary(end_addr)\n\n # In the end check accesses at random memory locations\n for _ in range(test_iterations):\n await self.randomAccessInAddrRange(0x00000000, 0xFFFFFFFF)\n\n\n# ==============================================================================\n\n\n@test()\nclass TestAddressMatching(BaseTest):\n \"\"\"\n This test provides a sequence that checks behaviour for different address\n matching schemes like:\n - Disabled entries\n - Top of range with lower boundary than previous entry\n - Top of range with higher boundary than previous entry\n - Unlocked entry that \"forbids\" access\n - Different permissions restrictions\n - Different configurations with interlacing address ranges\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, BaseEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TestSequence.create(\"stimulus\")\n\n async def run(self):\n await self.seq.start()\n" }, { "path": "verification/block/pmp/test_multiple_configs.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nfrom pyuvm import ConfigDB, test\nfrom testbench import BaseEnv, BaseTest, PMPWriteAddrCSRItem, PMPWriteCfgCSRItem\n\nfrom common import BaseSequence\n\nLOWER_BOUNDARY = 0x00000\nUPPER_BOUNDARY = 0x20000\n\npmp_configurations = [\n {\n # 0 - Entry locked, allow none, TOR, address range 0x00000-0x0FFFF\n \"pmpcfg\": 0b10001000,\n \"pmpaddr\": (0x10000 >> 2),\n },\n {\n # 1 - Entry locked, but disabled, address 0x01000\n \"pmpcfg\": 0b10000000,\n \"pmpaddr\": (0x01000 >> 2),\n },\n {\n # 2 - Entry locked, allow RWX, TOR, address range 0x01000-0x0FFFF\n \"pmpcfg\": 0b10001111,\n \"pmpaddr\": (0x10000 >> 2),\n },\n {\n # 3 - Entry unlocked, address 0x01000\n \"pmpcfg\": 0b00000000,\n \"pmpaddr\": (0x01000 >> 2),\n },\n {\n # 4 - Entry locked, allow R, TOR, address range 0x01000-0x1FFFF\n \"pmpcfg\": 0b10001001,\n \"pmpaddr\": (0x20000 >> 2),\n },\n {\n # 5 - Entry unlocked, address 0x01000\n \"pmpcfg\": 0b00000000,\n \"pmpaddr\": (0x01000 >> 2),\n },\n {\n # 6 - Entry locked, allow W, TOR, address range 0x01000-0x1FFFF\n \"pmpcfg\": 0b10001010,\n \"pmpaddr\": (0x20000 >> 2),\n },\n {\n # 7 - Entry unlocked, address 0x01000\n \"pmpcfg\": 0b00000000,\n \"pmpaddr\": (0x01000 >> 2),\n },\n {\n # 8 - Entry locked, allow X, TOR, address range 0x01000-0x1FFFF\n \"pmpcfg\": 0b10001100,\n \"pmpaddr\": (0x20000 >> 2),\n },\n]\n\n\n# =============================================================================\n\n\nclass TestSequence(BaseSequence):\n def __init__(self, name):\n super().__init__(name)\n\n async def body(self):\n test_iterations = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n pmp_entries = ConfigDB().get(None, \"\", \"PMP_ENTRIES\")\n\n # Ensure to not use more configurations than PMP entries\n assert len(pmp_configurations) <= pmp_entries\n\n # Configure PMP entries\n for i, cfg in enumerate(pmp_configurations):\n item = PMPWriteAddrCSRItem(index=i, pmpaddr=cfg[\"pmpaddr\"])\n await self.pmp_seqr.start_item(item)\n await self.pmp_seqr.finish_item(item)\n\n for i, cfg in enumerate(pmp_configurations):\n item = PMPWriteCfgCSRItem(index=i, pmpcfg=cfg[\"pmpcfg\"])\n await self.pmp_seqr.start_item(item)\n await self.pmp_seqr.finish_item(item)\n\n await self.checkRangeBoundary(LOWER_BOUNDARY)\n for _ in range(test_iterations):\n await self.randomAccessInAddrRange(LOWER_BOUNDARY, UPPER_BOUNDARY)\n await self.checkRangeBoundary(UPPER_BOUNDARY)\n\n\n# ==============================================================================\n\n\n@test()\nclass TestMultipleConfigs(BaseTest):\n \"\"\"\n This test provides a sequence that checks behaviour for multiple PMP configurations\n appplying to the same address ranges.\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, BaseEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TestSequence.create(\"stimulus\")\n\n async def run(self):\n await self.seq.start()\n" }, { "path": "verification/block/pmp/test_xwr_access.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\n\nfrom pyuvm import ConfigDB, test, uvm_sequence\nfrom testbench import (\n BaseEnv,\n BaseTest,\n PMPCheckItem,\n PMPWriteAddrCSRItem,\n PMPWriteCfgCSRItem,\n)\n\n# =============================================================================\n\n\nclass TestSequence(uvm_sequence):\n def __init__(self, name):\n super().__init__(name)\n\n self.pmp_seqr = ConfigDB().get(None, \"\", \"PMP_SEQR\")\n\n async def body(self):\n pmp_entries = ConfigDB().get(None, \"\", \"PMP_ENTRIES\")\n pmp_channels = ConfigDB().get(None, \"\", \"PMP_CHANNELS\")\n\n # Configure entries to all possible XWR configurations\n # Use TOR address matching for simplicity\n # 0b10001000\n # - bit 7 - Locked status (1 is locked)\n # - bits 6-5 - Reserved (always 0)\n # - bits 4-3 - Address Matching configuration (01 is TOR)\n # - bit 2 - Execute permission\n # - bit 1 - Write permission\n # - bit 0 - Read permission\n MAX_XWR_CONFIGS = 8\n for i in range(MAX_XWR_CONFIGS):\n addr = ((i + 1) * 0x1000) >> 2\n item = PMPWriteAddrCSRItem(index=i, pmpaddr=addr)\n await self.pmp_seqr.start_item(item)\n await self.pmp_seqr.finish_item(item)\n\n for i in range(MAX_XWR_CONFIGS):\n cfg = 0b10001000 + i\n item = PMPWriteCfgCSRItem(index=i, pmpcfg=cfg)\n await self.pmp_seqr.start_item(item)\n await self.pmp_seqr.finish_item(item)\n\n # Check all possible access variants on configured entries\n for i in range(pmp_channels):\n channel = i\n # Set type to each of 3 available (R or W or X)\n for j in range(3):\n type = 1 << j\n for k in range(pmp_entries):\n # Set address somewhere in the 0x1000 wide entry\n addr = (0x200 + (k * 0x1000)) >> 2\n\n item = PMPCheckItem(channel, addr, type)\n await self.pmp_seqr.start_item(item)\n await self.pmp_seqr.finish_item(item)\n\n\n# ==============================================================================\n\n\n@test()\nclass TestXWRAccess(BaseTest):\n \"\"\"\n This test configures few registers to covers or possible variants of RWX\n access permissions and then checks if they are properly checked.\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent, BaseEnv)\n\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n self.seq = TestSequence.create(\"stimulus\")\n\n async def run(self):\n await self.seq.start()\n" }, { "path": "verification/block/pmp/testbench.py", "content": "#\n# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport os\n\nfrom cocotb.binary import BinaryValue\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import ClockCycles, FallingEdge, RisingEdge\nfrom pyuvm import *\n\n# ==============================================================================\n\n\nACCESS_TYPE = {\n 0b001: \"R\",\n 0b010: \"W\",\n 0b100: \"X\",\n}\n\n\nclass RegisterMap:\n def __init__(self, pmp_entries):\n self.reg = dict()\n for i in range(pmp_entries):\n name = \"pmpcfg{}\".format(i)\n self.reg[name] = BinaryValue(value=0, bigEndian=False, n_bits=8)\n\n name = \"pmpaddr{}\".format(i)\n self.reg[name] = BinaryValue(value=0, bigEndian=False, n_bits=32)\n\n\ndef getDecodedEntryCfg(regs, index, range_only=False):\n \"\"\" \"\"\"\n pmpcfg = regs.reg[\"pmpcfg{}\".format(index)]\n pmpaddr = regs.reg[\"pmpaddr{}\".format(index)]\n\n # bits 0-2, (R, W, X)\n permissions = {\"R\": pmpcfg[0].integer, \"W\": pmpcfg[1].integer, \"X\": pmpcfg[2].integer}\n address_matching = pmpcfg[4:3].integer\n locked = pmpcfg[7].integer\n\n if index:\n start_address = regs.reg[\"pmpaddr{}\".format(index - 1)].integer << 2\n else:\n start_address = 0\n\n if address_matching == 0: # Entry diabled\n if range_only:\n end_address = pmpaddr.integer << 2\n return start_address, end_address\n else:\n return None\n elif address_matching == 1: # Top of range\n end_address = pmpaddr.integer << 2\n if start_address > end_address:\n if range_only:\n return start_address, end_address\n else:\n return None\n elif address_matching == 2: # Naturally aligned four-byte region\n end_address = (pmpaddr.integer << 2) + 4\n elif address_matching == 3: # Naturally aligned power-of-two region, >=8 bytes\n napot = 3\n start_address = pmpaddr\n for i in range(len(pmpaddr)):\n if pmpaddr[i].integer == 1:\n start_address[i].value = 0\n napot += 1\n else:\n continue\n\n start_address = start_address.integer << 2\n end_address = start_address + 2**napot\n\n # PMP upper address bundary is non-inclusive\n end_address -= 1\n\n if range_only:\n return start_address, end_address\n else:\n return start_address, end_address, permissions, locked\n\n\n# ==============================================================================\n\n\nclass PMPWriteCfgCSRItem(uvm_sequence_item):\n def __init__(self, index, pmpcfg):\n super().__init__(\"PMPWriteCfgCSRItem\")\n self.index = index\n self.pmpcfg = pmpcfg\n\n\nclass PMPWriteAddrCSRItem(uvm_sequence_item):\n def __init__(self, index, pmpaddr):\n super().__init__(\"PMPWriteAddrCSRItem\")\n self.index = index\n self.pmpaddr = pmpaddr\n\n\nclass PMPCheckItem(uvm_sequence_item):\n def __init__(self, channel, addr, type, err=None):\n super().__init__(\"PMPCheckItem\")\n self.channel = channel\n self.addr = addr\n self.type = type\n self.err = err\n\n\n# ==============================================================================\n\n\ndef collect_signals(signals, uut, obj):\n \"\"\"\n Collects signal objects from UUT and attaches them to the given object\n \"\"\"\n\n for sig in signals:\n if hasattr(uut, sig):\n s = getattr(uut, sig)\n\n else:\n s = None\n logging.error(\"Module {} does not have a signal '{}'\".format(str(uut), sig))\n\n setattr(obj, sig, s)\n\n\n# ==============================================================================\n\n\nclass PMPDriver(uvm_driver):\n SIGNALS = [\n \"clk\",\n # CSRs\n \"pmp_pmpcfg\",\n \"pmp_pmpaddr\",\n # PMP logic\n \"pmp_chan_addr\",\n \"pmp_chan_type\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n super().__init__(*args, **kwargs)\n self.regs = ConfigDB().get(None, \"\", \"PMP_CSRS\")\n\n # Collect signals\n collect_signals(self.SIGNALS, uut, self)\n\n async def run_phase(self):\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, PMPWriteAddrCSRItem):\n self.pmp_pmpaddr[it.index].value = it.pmpaddr\n self.regs.reg[\"pmpaddr{}\".format(it.index)].integer = it.pmpaddr\n elif isinstance(it, PMPWriteCfgCSRItem):\n self.pmp_pmpcfg[it.index].value = it.pmpcfg\n self.regs.reg[\"pmpcfg{}\".format(it.index)].integer = it.pmpcfg\n elif isinstance(it, PMPCheckItem):\n self.pmp_chan_addr[it.channel].value = it.addr\n self.pmp_chan_type[it.channel].value = it.type\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n await ClockCycles(self.clk, 1)\n self.seq_item_port.item_done()\n\n\nclass PMPMonitor(uvm_component):\n SIGNALS = [\n \"clk\",\n # CSRs\n \"pmp_pmpcfg\",\n \"pmp_pmpaddr\",\n # PMP logic\n \"pmp_chan_addr\",\n \"pmp_chan_type\",\n \"pmp_chan_err\",\n ]\n\n def __init__(self, *args, **kwargs):\n uut = kwargs[\"uut\"]\n del kwargs[\"uut\"]\n\n super().__init__(*args, **kwargs)\n\n collect_signals(self.SIGNALS, uut, self)\n\n self.pmp_channels = ConfigDB().get(None, \"\", \"PMP_CHANNELS\")\n self.pmp_entries = ConfigDB().get(None, \"\", \"PMP_ENTRIES\")\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n while True:\n await RisingEdge(self.clk)\n\n # Check all PMP channels\n for i in range(self.pmp_channels):\n access_addr = int(self.pmp_chan_addr[i].value)\n access_type = int(self.pmp_chan_type[i].value)\n access_err = int(self.pmp_chan_err.value[i])\n\n self.ap.write(PMPCheckItem(i, access_addr, access_type, access_err))\n\n\n# ==============================================================================\n\n\nclass Scoreboard(uvm_component):\n def build_phase(self):\n self.passed = True\n self.fifo = uvm_tlm_analysis_fifo(\"fifo\", self)\n self.port = uvm_get_port(\"port\", self)\n self.regs = ConfigDB().get(None, \"\", \"PMP_CSRS\")\n\n def connect_phase(self):\n self.port.connect(self.fifo.get_export)\n\n def check_phase(self):\n while self.port.can_get():\n _, item = self.port.try_get()\n\n if isinstance(item, PMPCheckItem):\n addr = item.addr\n type = item.type\n chan = item.channel\n err = item.err\n type_str = ACCESS_TYPE.get(type, \"UNKNOWN ({})\".format(type))\n\n if type_str not in ACCESS_TYPE.values():\n self.logger.debug(\n \"Unknown access type ({}), probably checking channel that doesn't request access.\".format(\n type\n )\n )\n continue\n\n # Check if address range can be matched to any PMP entry\n entry_permissions = None\n for i in range(len(self.regs.reg) // 2):\n entry = getDecodedEntryCfg(self.regs, i)\n if entry is not None:\n pmp_start_addr, pmp_end_addr, permissions, locked = entry\n else:\n continue\n\n # Check if entry address range matches channel address\n if addr in range(pmp_start_addr, pmp_end_addr):\n if locked: # If entry is locked, save it for permission checks\n entry_permissions = permissions\n break\n\n log_msg = \"PMPCheckItem: Validating access 0x{:08x}, type={} ({}), channel={}, error={}\".format(\n addr, type, type_str, chan, err\n )\n if entry_permissions is None:\n # If address range was not matched, ensure that error is not raised\n if err:\n self.logger.error(\"Error asserted when no entry was matched!\")\n self.logger.debug(log_msg)\n self.passed = False\n else:\n # If address range was matched, compare permissions to the command type\n for op in ACCESS_TYPE.values():\n if type_str == op and not (entry_permissions[op] ^ err):\n self.logger.error(\"Unexpected error state on access request!\")\n self.logger.debug(log_msg)\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n pmp_entries = 16\n ConfigDB().set(None, \"*\", \"PMP_ENTRIES\", pmp_entries)\n ConfigDB().set(None, \"*\", \"PMP_CHANNELS\", 3)\n ConfigDB().set(None, \"*\", \"PMP_GRANULARITY\", 0)\n\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 100)\n\n # PMP Registers\n self.regs = RegisterMap(pmp_entries)\n ConfigDB().set(None, \"*\", \"PMP_CSRS\", self.regs)\n\n # Sequencers\n self.pmp_seqr = uvm_sequencer(\"pmp_seqr\", self)\n\n # PMP interface\n self.pmp_drv = PMPDriver(\"pmp_drv\", self, uut=cocotb.top)\n self.pmp_mon = PMPMonitor(\"pmp_mon\", self, uut=cocotb.top)\n\n # Add scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n ConfigDB().set(None, \"*\", \"PMP_SEQR\", self.pmp_seqr)\n\n def connect_phase(self):\n self.pmp_drv.seq_item_port.connect(self.pmp_seqr.seq_item_export)\n self.pmp_mon.ap.connect(self.scoreboard.fifo.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def run_phase(self):\n self.raise_objection()\n\n cocotb.top.scan_mode.value = 0\n cocotb.top.pmp_chan_addr.value = [0, 0, 0]\n cocotb.top.pmp_chan_type.value = [0, 0, 0]\n\n self.start_clock(\"clk\")\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n await self.run()\n await ClockCycles(cocotb.top.clk, 2)\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/pmp_random/Makefile", "content": "null :=\nspace := $(null) #\ncomma := ,\n\nTEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nSRCDIR := $(abspath $(TEST_DIR)../../../../design)\n\nTEST_FILES = $(sort $(wildcard test_*.py))\n\nMODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))\nTOPLEVEL = el2_pmp_wrapper\nPMP_TEST := 1\n\nVERILOG_SOURCES = \\\n $(TEST_DIR)/el2_pmp_wrapper.sv \\\n $(SRCDIR)/el2_pmp.sv\n\ninclude $(TEST_DIR)/../common.mk\n" }, { "path": "verification/block/pmp_random/config.vlt", "content": "`verilator_config\n\nlint_off -rule WIDTHTRUNC -file \"*/el2_pmp_wrapper.sv\"\n" }, { "path": "verification/block/pmp_random/el2_pmp_wrapper.sv", "content": "// Copyright (c) 2023 Antmicro\n// SPDX-License-Identifier: Apache-2.0\n\nmodule el2_pmp_wrapper\n import el2_pkg::*;\n#(\n parameter PMP_CHANNELS = 3,\n `include \"el2_param.vh\"\n) (\n input logic clk, // Top level clock\n input logic rst_l, // Reset\n input logic scan_mode, // Scan mode\n\n input [7:0] pmp_pmpcfg [pt.PMP_ENTRIES],\n input logic [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],\n\n input logic [ 31:0] pmp_chan_addr[PMP_CHANNELS],\n input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS],\n output logic [PMP_CHANNELS-1:0] pmp_chan_err\n);\n logic pmp_chan_err_unpacked[PMP_CHANNELS];\n el2_pmp_cfg_pkt_t pmp_pmpcfg_int [pt.PMP_ENTRIES];\n\n for (genvar c = 0; c < PMP_CHANNELS; c++) begin\n assign pmp_chan_err[PMP_CHANNELS-1-c] = pmp_chan_err_unpacked[c];\n end\n\n for (genvar e = 0; e < pt.PMP_ENTRIES; e++) begin\n assign pmp_pmpcfg_int[e].lock = pmp_pmpcfg[e][7];\n assign pmp_pmpcfg_int[e].reserved = pmp_pmpcfg[e][6:5];\n assign pmp_pmpcfg_int[e].mode = el2_pkg::el2_pmp_mode_pkt_t'(pmp_pmpcfg[e][4:3]);\n assign pmp_pmpcfg_int[e].execute = pmp_pmpcfg[e][2];\n assign pmp_pmpcfg_int[e].write = pmp_pmpcfg[e][1];\n assign pmp_pmpcfg_int[e].read= pmp_pmpcfg[e][0];\n end\n\n // The PMP module\n el2_pmp pmp (\n .pmp_chan_err(pmp_chan_err_unpacked),\n .pmp_pmpcfg(pmp_pmpcfg_int),\n .*\n );\n\nendmodule\n" }, { "path": "verification/block/pmp_random/test_pmp_random.py", "content": "# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: Apache-2.0\nimport random\n\nimport pyuvm\nfrom cocotb.triggers import ClockCycles\nfrom pyuvm import *\nfrom testbench import BaseTest, InputItem\n\n# =============================================================================\n\n\nclass PMPRandomLegalSequence(uvm_sequence):\n \"\"\" \"\"\"\n\n def __init__(self, name):\n super().__init__(name)\n\n def legalize_pmpcfg(self, item):\n \"\"\"\n Leave only A, X and R fields as any combination of them is legal and\n does not influence PMPADDR access. Setting L would interfere with the\n test.\n \"\"\"\n mask = 0b00011101\n item.cfg &= (mask << 24) | (mask << 16) | (mask << 8) | mask\n\n def legalize_pmpaddr(self, item):\n \"\"\"\n Mask out two MSBs\n \"\"\"\n item.pmp_addr &= 0x3FFFFFFF\n\n async def body(self):\n\n # Run\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n\n for i in range(count):\n item = InputItem()\n item.randomize()\n self.legalize_pmpaddr(item)\n self.legalize_pmpcfg(item)\n\n await self.start_item(item)\n await self.finish_item(item)\n\n\n@pyuvm.test()\nclass TestRandomPMP(BaseTest):\n def end_of_elaboration_phase(self):\n super().end_of_elaboration_phase()\n count = ConfigDB().get(None, \"\", \"TEST_ITERATIONS\")\n self.seq = [PMPRandomLegalSequence(\"stimulus\") for i in range(count)]\n\n async def run(self):\n for seq in self.seq:\n await seq.start(self.env.pmp_wr_seqr)\n" }, { "path": "verification/block/pmp_random/testbench.py", "content": "# Copyright (c) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\nimport copy\nimport math\nimport os\nimport random\nimport struct\n\nimport pyuvm\nfrom cocotb.binary import BinaryValue\nfrom cocotb.clock import Clock\nfrom cocotb.triggers import (\n ClockCycles,\n Event,\n FallingEdge,\n First,\n Lock,\n RisingEdge,\n Timer,\n)\nfrom cocotb.types import Array, Range\nfrom pyuvm import *\n\n# ==============================================================================\n\nNONE = 0x0\nREAD = 0x1\nWRITE = 0x2\nEXEC = 0x4\n\n# ==============================================================================\n\n\nclass InputItem(uvm_sequence_item):\n \"\"\"\n PMP input item\n \"\"\"\n\n RANGE = 16\n\n def __init__(self, cfg=0, entry=0, pmp_addr=0, chan_addr=0, chan_type=0, chan=0, chan_err=0):\n super().__init__(\"InputItem\")\n\n self.cfg = cfg\n self.entry = entry\n self.pmp_addr = pmp_addr\n self.chan = chan\n self.chan_addr = chan_addr\n self.chan_type = chan_type\n self.chan_err = chan_err\n\n def randomize(self):\n \"\"\"\n Randomize cfg and addresses\n \"\"\"\n self.cfg = random.randint(0, 0xFF)\n self.entry = random.randint(0, 63)\n self.pmp_addr = random.randint(0, 0xFFFFFFFF)\n self.chan = random.randint(0, 2)\n self.chan_addr = random.randint(0, 0xFFFFFFFF)\n self.chan_type = random.randint(0, 3)\n\n\n# ==============================================================================\n\n\nclass PMPWriteDriver(uvm_driver):\n \"\"\"\n PMP CSR write port driver driver\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n async def run_phase(self):\n\n while True:\n it = await self.seq_item_port.get_next_item()\n\n if isinstance(it, InputItem):\n await RisingEdge(self.dut.clk)\n self.dut.pmp_pmpcfg[it.entry].value = it.cfg\n self.dut.pmp_pmpaddr[it.entry].value = it.pmp_addr\n self.dut.pmp_chan_addr[it.chan].value = it.chan_addr\n self.dut.pmp_chan_type[it.chan].value = it.chan_type\n\n else:\n raise RuntimeError(\"Unknown item '{}'\".format(type(it)))\n\n self.seq_item_port.item_done()\n\n\n# ==============================================================================\n\n\nclass WriteMonitor(uvm_component):\n \"\"\"\n Monitor for CSR write inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n\n while True:\n await RisingEdge(self.dut.clk)\n cfg = self.dut.pmp_pmpcfg.value\n pmp_addr = self.dut.pmp_pmpaddr.value\n chan_addr = self.dut.pmp_chan_addr.value\n chan_type = self.dut.pmp_chan_type\n item = InputItem(cfg=cfg, pmp_addr=pmp_addr, chan_addr=chan_addr, chan_type=chan_type)\n self.ap.write(item)\n\n\nclass ReadMonitor(uvm_component):\n \"\"\"\n Monitor for CSR read inputs\n \"\"\"\n\n def __init__(self, *args, **kwargs):\n self.dut = kwargs[\"dut\"]\n del kwargs[\"dut\"]\n super().__init__(*args, **kwargs)\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n async def run_phase(self):\n\n while True:\n await RisingEdge(self.dut.clk)\n chan_err = self.dut.pmp_chan_err\n item = InputItem(chan_err=chan_err)\n self.ap.write(item)\n\n\n# ==============================================================================\n\n\nclass Scoreboard(uvm_component):\n \"\"\"\n PMP dec ctl scoreboard\n \"\"\"\n\n def __init__(self, name, parent):\n super().__init__(name, parent)\n\n self.passed = None\n\n def build_phase(self):\n self.fifo_inp = uvm_tlm_analysis_fifo(\"fifo_inp\", self)\n self.fifo_out = uvm_tlm_analysis_fifo(\"fifo_out\", self)\n self.port_inp = uvm_get_port(\"port_inp\", self)\n self.port_out = uvm_get_port(\"port_out\", self)\n\n def connect_phase(self):\n self.port_inp.connect(self.fifo_inp.get_export)\n self.port_out.connect(self.fifo_out.get_export)\n\n def check_phase(self):\n self.passed = None\n\n # Get item pairs\n while True:\n got_inp, item_inp = self.port_inp.try_get()\n got_out, item_out = self.port_out.try_get()\n\n if not got_inp and got_out:\n self.logger.error(\"No input item for output item\")\n self.passed = False\n break\n\n if got_inp and not got_out:\n self.logger.error(\"No output item for input item\")\n self.passed = False\n break\n\n if not got_inp and not got_out:\n break\n\n if self.passed is None:\n self.passed = True\n\n # we should never hit PMP error in this test\n if int(item_inp.chan_err) != 0:\n self.logger.error(\"Got PMP Error\")\n self.passed = False\n\n def final_phase(self):\n if not self.passed:\n self.logger.critical(\"{} reports a failure\".format(type(self)))\n assert False\n\n\n# ==============================================================================\n\n\nclass BaseEnv(uvm_env):\n \"\"\"\n Base PyUVM test environment\n \"\"\"\n\n def build_phase(self):\n # Config\n ConfigDB().set(None, \"*\", \"TEST_CLK_PERIOD\", 1)\n ConfigDB().set(None, \"*\", \"TEST_ITERATIONS\", 200)\n\n # Sequencers\n self.pmp_wr_seqr = uvm_sequencer(\"pmp_wr_seqr\", self)\n\n # Drivers\n self.pmp_wr_drv = PMPWriteDriver(\"pmp_wr_drv\", self, dut=cocotb.top)\n\n # Monitors\n self.wr_mon = WriteMonitor(\"wr_mon\", self, dut=cocotb.top)\n self.rd_mon = ReadMonitor(\"rd_mon\", self, dut=cocotb.top)\n\n # Scoreboard\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n\n def connect_phase(self):\n self.pmp_wr_drv.seq_item_port.connect(self.pmp_wr_seqr.seq_item_export)\n\n self.wr_mon.ap.connect(self.scoreboard.fifo_inp.analysis_export)\n self.rd_mon.ap.connect(self.scoreboard.fifo_out.analysis_export)\n\n\n# ==============================================================================\n\n\nclass BaseTest(uvm_test):\n \"\"\"\n Base test for the module\n \"\"\"\n\n def __init__(self, name, parent, env_class=BaseEnv):\n super().__init__(name, parent)\n self.env_class = env_class\n\n # Synchronize pyuvm logging level with cocotb logging level. Unclear\n # why it does not happen automatically.\n level = logging.getLevelName(os.environ.get(\"COCOTB_LOG_LEVEL\", \"INFO\"))\n uvm_report_object.set_default_logging_level(level)\n\n def build_phase(self):\n self.env = self.env_class(\"env\", self)\n\n def start_clock(self, name):\n period = ConfigDB().get(None, \"\", \"TEST_CLK_PERIOD\")\n sig = getattr(cocotb.top, name)\n clock = Clock(sig, period, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n\n async def do_reset(self):\n cocotb.top.rst_l.value = 0\n await ClockCycles(cocotb.top.clk, 2)\n await FallingEdge(cocotb.top.clk)\n cocotb.top.rst_l.value = 1\n\n async def run_phase(self):\n self.raise_objection()\n\n # Start clocks\n self.start_clock(\"clk\")\n\n # Issue reset\n await self.do_reset()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 2)\n\n # Run the actual test\n await self.run()\n\n # Wait some cycles\n await ClockCycles(cocotb.top.clk, 10)\n\n self.drop_objection()\n\n async def run(self):\n raise NotImplementedError()\n" }, { "path": "verification/block/pyproject.toml", "content": "# Copyright (C) 2023 Antmicro\n# SPDX-License-Identifier: Apache-2.0\n\n[tool.black]\nline-length = 100\nexclude = '''\n(\n /(\n | \\.git\n | \\.gitignore\n | \\.gitmodules\n | \\.github\n | \\.nox\n | \\.pytest_cache\n | __pycache__\n | venv\n )/\n | docs/source/conf.py\n)\n'''\n\n[tool.isort]\nprofile = \"black\"\nmulti_line_output = 3\n" }, { "path": "verification/block/requirements.txt", "content": "cocotb==1.8.0\ncocotb-bus==0.2.1\ncocotb-coverage==1.1.0\ncocotb-test==0.2.4\npytest==7.4.1\npytest-html==3.2.0\npytest-timeout==2.1.0\npytest-md==0.2.0\npyuvm==2.9.1\nscipy==1.13.1\n" }, { "path": "verification/test_debug/test_debug.py", "content": "#\n# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: BSD-2-Clause\n\nimport pytest\nimport subprocess\n\nclass TestDebug():\n def test_debug(self):\n print(\"This test returns true\")\n assert True == True\n" }, { "path": "verification/top/README.md", "content": "# Verification\n\nThe verification directory contains [pyuvm](https://github.com/pyuvm/pyuvm) tests, which rely on [cocotb](https://github.com/cocotb/cocotb) library.\n\n## Setup\n\nIn order to run the tests, create a python virtual environment. Verilator is used as a backend simulator and must be present in the system.\n\n### Clone repository\n\nRemember to set the `RV_ROOT` environment variable, which is required to generate VeeR-EL2 Core configuration files.\n\n git clone --recurse-submodules git@github.com:chipsalliance/Cores-VeeR-EL2.git\n cd Cores-Veer-EL2\n export RV_ROOT=$(pwd)\n\n### Prepare python virtual environment\n\n cd $RV_ROOT/verification/top\n python -m venv venv\n source venv/bin/activate\n pip install -r requirements.txt\n\n### Install Verilator\n\nInstallation instructions are available in the Verilator's User Guide:\n\n https://veripool.org/guide/latest/install.html\n\n## Tests\n\nEach PyUVM test can be either run from a pytest wrapper or directly from a Makefile. The wrapper is placed to provide easier CI integration, HTML reports and Markdown summaries in job descriptions on GitHub. The Makefile execution may be more convenient during debugging.\n\n### Example: `test_pyuvm`\n\nIn `test_pyuvm` directory, a `Makefile` and a wrapper `test_pyuvm.py` are placed.\n\n ./verification/top/\n └── test_pyuvm\n ├── Makefile\n ├── test_pyuvm.py ⟵ pytest wrapper\n └── test_irq\n └── test_irq.py ⟵ PyUVM test\n\nThe pytest wrapper can be executed with a command:\n\n python -m pytest -sv test_pyuvm.py\n\nIf you need to run the test directly from the `Makefile`, please look for the decorator in the pytest wrapper to find valid `UVM_TEST` names:\n\n @pytest.mark.parametrize(\"UVM_TEST\", [\"test_irq.test_irq\"])\n\nThe test can also be run directly from the Makefile:\n\n UVM_TEST=test_irq.test_irq make all\n\nNote that HTML report can be produced with flag `--html=index.html` and a markdown report with `--md=test.md`\n\n## CI\n\nPyUVM tests are run in CI with the following workflow:\n\n .github/workflows/test-verification.yml\n" }, { "path": "verification/top/requirements.txt", "content": "# Installing custom cocotb due to:\n# cocotb scheduler incorrectly handles simulation time\n# when Verilator is used with flag --timing\n${RV_ROOT}/third_party/cocotb\n# cocotb==1.7.2\ncocotb-bus==0.2.1\ncocotb-coverage==1.1.0\ncocotb-test==0.2.4\npytest==7.4.1\npytest-html==3.2.0\npytest-timeout==2.1.0\npytest-md==0.2.0\npyuvm==2.9.1\n" }, { "path": "verification/top/test_pyuvm/Makefile", "content": "# SPDX-License-Identifier: Apache-2.0\n# Copyright 2020 Western Digital Corporation or its affiliates.\n# Copyright (c) 2023 Antmicro \n#\n# Licensed under the Apache License, Version 2.0 (the \"License\");\n# you may not use this file except in compliance with the License.\n# You may obtain a copy of the License at\n#\n# http://www.apache.org/licenses/LICENSE-2.0\n#\n# Unless required by applicable law or agreed to in writing, software\n# distributed under the License is distributed on an \"AS IS\" BASIS,\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n# See the License for the specific language governing permissions and\n# limitations under the License.\n#\n\nTOPLEVEL_LANG = verilog\nSIM ?= verilator\nWAVES ?= 1\nNPROC = $$((`nproc`-1))\n\n#Paths\nCURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))\nCFGDIR := $(abspath $(CURDIR)/snapshots/default)\nCONFIG := $(RV_ROOT)/configs\n# -------------------------------------\n# VeeR Configuration\n# -------------------------------------\nCONF_PARAMS ?= -set build_axi4\n\n# Check for RV_ROOT\nifeq (,$(wildcard ${RV_ROOT}/configs/veer.config))\n$(error env var RV_ROOT does not point to a valid dir! Exiting!)\nendif\n\n# -------------------------------------\n# Testbench setup\n# -------------------------------------\nMODULE ?= test_irq.test_irq\nTEST_FILES = $(CURDIR)/test_irq/test_irq.py\nTOPLEVEL = veer_wrapper\nSIM_BUILD ?= sim\nCM_FILE ?= cm.cfg\n\nVERILOG_SOURCES = \\\n $(CFGDIR)/common_defines.vh \\\n $(RV_ROOT)/design/include/el2_def.sv \\\n $(CFGDIR)/el2_pdef.vh\n\nSIM_FLIST_FILE = $(RV_ROOT)/testbench/flist\n\n# -------------------------------------\n# Compilation/simulation configuration\n# -------------------------------------\n\n# Coverage reporting\nCOVERAGE_TYPE?= all\nifeq (\"$(COVERAGE_TYPE)\", \"all\")\n VERILATOR_COVERAGE = --coverage\nelse ifeq (\"$(COVERAGE_TYPE)\", \"branch\")\n VERILATOR_COVERAGE = --coverage-line\nelse ifeq (\"$(COVERAGE_TYPE)\", \"toggle\")\n VERILATOR_COVERAGE = --coverage-toggle\nelse ifeq (\"$(COVERAGE_TYPE)\", \"functional\")\n VERILATOR_COVERAGE = --coverage-user\nelse\n VERILATOR_COVERAGE = \"\"\nendif\n\nifeq ($(SIM), verilator)\n COMPILE_ARGS += --coverage-max-width 20000\n COMPILE_ARGS += --timing\n COMPILE_ARGS += -Wall -Wno-fatal\n\n EXTRA_ARGS += --trace --trace-structs\n EXTRA_ARGS += $(VERILATOR_COVERAGE)\n EXTRA_ARGS += -I$(CFGDIR) -Wno-DECLFILENAME\nelse ifeq ($(SIM), vcs)\n EXTRA_ARGS += +incdir+$(CFGDIR) -assert svaext -cm line+cond+fsm+tgl+branch +vcs+lic+wait -cm_libs yv -cm_hier $(CURDIR)/$(CM_FILE)\n PLUSARGS += +dumpon\nendif\n\nCOCOTB_HDL_TIMEUNIT ?= 1ns\nCOCOTB_HDL_TIMEPRECISION ?= 1ps\n\n# Build directory\nifneq ($(COVERAGE_TYPE),)\n SIM_BUILD := sim-build-$(COVERAGE_TYPE)\nendif\n\nBUILD_ARGS = -j$(NPROC)\n\n# -------------------------------------\n# Make PyUVM test with Verilator\n# -------------------------------------\ninclude $(shell cocotb-config --makefiles)/Makefile.sim\n\n$(SIM_BUILD)/Vtop.mk: $(VERILOG_SOURCES) $(CUSTOM_COMPILE_DEPS) $(COCOTB_SHARE_DIR)/lib/verilator/verilator.cpp | $(SIM_BUILD)\n\t$(CMD) -cc --exe -Mdir $(SIM_BUILD) -DCOCOTB_SIM=1 $(TOPMODULE_ARG) $(COMPILE_ARGS) $(EXTRA_ARGS) $(VERILOG_SOURCES) -f $(SIM_FLIST_FILE) $(COCOTB_SHARE_DIR)/lib/verilator/verilator.cpp\n\n$(SIM_BUILD)/simv: $(VERILOG_SOURCES) $(SIM_BUILD)/pli.tab $(CUSTOM_COMPILE_DEPS) | $(SIM_BUILD)\n\tcd $(SIM_BUILD) && \\\n\t$(CMD) -top $(TOPLEVEL) $(PLUSARGS) +acc+1 +vpi -P pli.tab +define+COCOTB_SIM=1 -sverilog \\\n -timescale=$(COCOTB_HDL_TIMEUNIT)/$(COCOTB_HDL_TIMEPRECISION) \\\n $(EXTRA_ARGS) -debug -load $(shell cocotb-config --lib-name-path vpi vcs) \\\n\t$(COMPILE_ARGS) $(VERILOG_SOURCES) -f $(SIM_FLIST_FILE)\n\n$(CFGDIR)/common_defines.vh:\n\tcd $(CURDIR) && $(CONFIG)/veer.config -fpga_optimize=0 $(CONF_PARAMS) $(EXTRA_CONFIG_OPTS)\n\techo '`undef RV_ASSERT_ON' >> $(CFGDIR)/common_defines.vh\n" }, { "path": "verification/top/test_pyuvm/__init__.py", "content": "" }, { "path": "verification/top/test_pyuvm/cm.cfg", "content": "+tree veer_wrapper.rvtop\n\n////////////////////////////////// MAIN CORE //////////////////////////////////\n///////////////////////////////////////////////////////////////////////////////\n\n//////////////////////////////// rvrangecheck /////////////////////////////////\n// 'start_addr' and 'region' are tied to module parameters\n-node veer_wrapper.rvtop.veer*rangecheck.start_addr\n-node veer_wrapper.rvtop.veer*rangecheck.region\n\n////////////////////////////// el2_veer_wrapper ///////////////////////////////\n-node veer_wrapper.rvtop.unused_dmi_hard_reset\n-node veer_wrapper.rvtop.trace_rv_i_address_ip[0]\n\n/////////////////////////////////// el2_veer //////////////////////////////////\n-node veer_wrapper.rvtop.veer.trace_rv_i_address_ip[0]\n-node veer_wrapper.rvtop.veer.trace_rv_trace_pkt.trace_rv_i_address_ip[0]\n-node veer_wrapper.rvtop.veer.*hprot[3:1] // Tied to 3'001\n\n/////////////////////////////////// el2_dbg ///////////////////////////////////\n// Tied to '0\n-node veer_wrapper.rvtop.veer.dbg.abstractcs_reg[31:13]\n-node veer_wrapper.rvtop.veer.dbg.abstractcs_reg[11]\n-node veer_wrapper.rvtop.veer.dbg.abstractcs_reg[7:4]\n-node veer_wrapper.rvtop.veer.dbg.dmcontrol_reg[29]\n-node veer_wrapper.rvtop.veer.dbg.dmcontrol_reg[27:2]\n-node veer_wrapper.rvtop.veer.dbg.dmstatus_reg[31:20]\n-node veer_wrapper.rvtop.veer.dbg.dmstatus_reg[15:14]\n-node veer_wrapper.rvtop.veer.dbg.dmstatus_reg[6:4]\n-node veer_wrapper.rvtop.veer.dbg.haltsum0_reg[31:1]\n-node veer_wrapper.rvtop.veer.dbg.sbcs_reg[31:30]\n-node veer_wrapper.rvtop.veer.dbg.sbcs_reg[28:23]\n\n-node veer_wrapper.rvtop.veer.dbg.dmstatus_reg[7] // Tied to '1\n-node veer_wrapper.rvtop.veer.dbg.dmstatus_reg[3:0] // Tied to 4'h2\n-node veer_wrapper.rvtop.veer.dbg.abstractcs_reg[3:0] // Tied to 4'h2\n-node veer_wrapper.rvtop.veer.dbg.sbcs_reg[29] // Tied to '1\n-node veer_wrapper.rvtop.veer.dbg.sbcs_reg[11:5] // Tied to 7'h20\n-node veer_wrapper.rvtop.veer.dbg.sbcs_reg[4:0] // Tied to 5'b01111\n\n/////////////////////////////////// el2_exu ///////////////////////////////////\n-node veer_wrapper.rvtop.veer.exu.i_mul.crc32_poly_rev // Tied to 32'hEDB88320\n-node veer_wrapper.rvtop.veer.exu.i_mul.crc32c_poly_rev // Tied to 32'h82F63B78\n\n////////////////////////////////// rvjtag_tap /////////////////////////////////\n-node veer_wrapper.rvtop.dmi_wrapper.i_jtag_tap.abits // Tied to AWID[5:0]\n\n///////////////////////////////// dec_tlu_ctl /////////////////////////////////\n// Tied to '0\n-node veer_wrapper.rvtop.veer.dec.tlu.dcsr[14]\n-node veer_wrapper.rvtop.veer.dec.tlu.dcsr[9]\n-node veer_wrapper.rvtop.veer.dec.tlu.dcsr[5:4]\n-node veer_wrapper.rvtop.veer.dec.tlu.dcsr_ns[14]\n-node veer_wrapper.rvtop.veer.dec.tlu.dcsr_ns[9]\n-node veer_wrapper.rvtop.veer.dec.tlu.dcsr_ns[5:4]\n-node veer_wrapper.rvtop.veer.dec.tlu.ifu_mscause[2]\n-node veer_wrapper.rvtop.veer.dec.tlu.mcgc[6]\n-node veer_wrapper.rvtop.veer.dec.tlu.mcgc_int[6]\n-node veer_wrapper.rvtop.veer.dec.tlu.mcgc_ns[6]\n-node veer_wrapper.rvtop.veer.dec.tlu.mcountinhibit[1]\n-node veer_wrapper.rvtop.veer.dec.tlu.mepc_rf[0]\n-node veer_wrapper.rvtop.veer.dec.tlu.mie_rf[31]\n-node veer_wrapper.rvtop.veer.dec.tlu.mie_rf[27:12]\n-node veer_wrapper.rvtop.veer.dec.tlu.mie_rf[10:8]\n-node veer_wrapper.rvtop.veer.dec.tlu.mie_rf[6:4]\n-node veer_wrapper.rvtop.veer.dec.tlu.mie_rf[2:0]\n-node veer_wrapper.rvtop.veer.dec.tlu.mip_rf[27:12]\n-node veer_wrapper.rvtop.veer.dec.tlu.mip_rf[10:8]\n-node veer_wrapper.rvtop.veer.dec.tlu.mip_rf[6:4]\n-node veer_wrapper.rvtop.veer.dec.tlu.mip_rf[2:0]\n-node veer_wrapper.rvtop.veer.dec.tlu.mstatus_rf[31:17]\n-node veer_wrapper.rvtop.veer.dec.tlu.mstatus_rf[15:12]\n-node veer_wrapper.rvtop.veer.dec.tlu.mstatus_rf[10:8]\n-node veer_wrapper.rvtop.veer.dec.tlu.mstatus_rf[6:4]\n-node veer_wrapper.rvtop.veer.dec.tlu.mstatus_rf[2:0]\n-node veer_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[26]\n-node veer_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[18:13]\n-node veer_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[10:8]\n-node veer_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[5:3]\n-node veer_wrapper.rvtop.veer.dec.tlu.mtvec_rf[1]\n\n/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////\n// Tied to '0\n-node veer_wrapper.rvtop.veer.dec.tlu.pmp.*pmpcfg_ff.din[6:5]\n-node veer_wrapper.rvtop.veer.dec.tlu.pmp.*pmpcfg_ff.dout[6:5]\n-node veer_wrapper.rvtop.veer.dec.tlu.pmp.*csr_wdata[6:5]\n\n// Aggregation of four 'el2_pmp_cfg_pkt_t' entries\n// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0\n-node veer_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[30:29]\n-node veer_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[22:21]\n-node veer_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[14:13]\n-node veer_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[6:5]\n\n//////////////////////////// el2_ifu_compress_ctl /////////////////////////////\n// Tied to '0\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.o[31]\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.o[29:21]\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.o[19:15]\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.o[11:7]\n\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.o[1:0] // Tied to 2'b11\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.l1[1:0] // Tied to o[1:0] (2'b11)\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.l2[1:0] // Tied to l1[1:0] (2'b11)\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.l3[1:0] // Tied to l2[1:0] (2'b11)\n\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.l1[31] // Tied to o[31] ('0)\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.l1[29:25] // Tied to o[29:25] ('0)\n\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.rdpd[4:3] // Tied to 2'01\n-node veer_wrapper.rvtop.veer.ifu.aln.compress0.rs2pd[4:3] // Tied to 2'01\n\n\n////////////////////////////////// LOCKSTEP ///////////////////////////////////\n///////////////////////////////////////////////////////////////////////////////\n\n//////////////////////////////// rvrangecheck /////////////////////////////////\n// 'start_addr' and 'region' are tied to module parameters\n-node veer_wrapper.rvtop.lockstep.xshadow_core*rangecheck.start_addr\n-node veer_wrapper.rvtop.lockstep.xshadow_core*rangecheck.region\n\n////////////////////////////// el2_veer_lockstep //////////////////////////////\n-node veer_wrapper.rvtop.lockstep.trace_rv_i_address_ip[0]\n-node veer_wrapper.rvtop.lockstep.*trace_rv_i_address_ip[0]\n\n/////////////////////////////////// el2_veer //////////////////////////////////\n-node veer_wrapper.rvtop.lockstep.xshadow_core.trace_rv_i_address_ip[0]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.trace_rv_trace_pkt.trace_rv_i_address_ip[0]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.*hprot[3:1] // Tied to 3'001\n\n/////////////////////////////////// el2_dbg ///////////////////////////////////\n// Tied to '0\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[31:13]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[11]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[7:4]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.dmcontrol_reg[29]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.dmcontrol_reg[27:2]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[31:20]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[15:14]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[6:4]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.haltsum0_reg[31:1]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[31:30]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[28:23]\n\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[7] // Tied to '1\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[3:0] // Tied to 4'h2\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[3:0] // Tied to 4'h2\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[29] // Tied to '1\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[11:5] // Tied to 7'h20\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[4:0] // Tied to 5'b01111\n\n/////////////////////////////////// el2_exu ///////////////////////////////////\n-node veer_wrapper.rvtop.lockstep.xshadow_core.exu.i_mul.crc32_poly_rev // Tied to 32'hEDB88320\n-node veer_wrapper.rvtop.lockstep.xshadow_core.exu.i_mul.crc32c_poly_rev // Tied to 32'h82F63B78\n\n///////////////////////////////// dec_tlu_ctl /////////////////////////////////\n// Tied to '0\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr[14]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr[9]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr[5:4]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr_ns[14]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr_ns[9]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr_ns[5:4]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.ifu_mscause[2]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcgc[6]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcgc_int[6]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcgc_ns[6]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcountinhibit[1]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mepc_rf[0]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[31]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[27:12]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[10:8]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[6:4]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[2:0]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[27:12]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[10:8]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[6:4]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[2:0]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[31:17]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[15:12]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[10:8]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[6:4]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[2:0]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[26]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[18:13]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[10:8]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[5:3]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtvec_rf[1]\n\n/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////\n// Tied to '0\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.*pmpcfg_ff.din[6:5]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.*pmpcfg_ff.dout[6:5]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.*csr_wdata[6:5]\n\n// Aggregation of four 'el2_pmp_cfg_pkt_t' entries\n// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[30:29]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[22:21]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[14:13]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[6:5]\n\n//////////////////////////// el2_ifu_compress_ctl /////////////////////////////\n// Tied to '0\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[31]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[29:21]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[19:15]\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[11:7]\n\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[1:0] // Tied to 2'b11\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l1[1:0] // Tied to o[1:0] (2'b11)\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l2[1:0] // Tied to l1[1:0] (2'b11)\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l3[1:0] // Tied to l2[1:0] (2'b11)\n\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l1[31] // Tied to o[31] ('0)\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l1[29:25] // Tied to o[29:25] ('0)\n\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.rdpd[4:3] // Tied to 2'01\n-node veer_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.rs2pd[4:3] // Tied to 2'01\n" }, { "path": "verification/top/test_pyuvm/conftest.py", "content": "import pytest\n\ndef type_checker_cov(value):\n msg = \"UsageError --coverage=\"\n if value not in [\"all\", \"branch\", \"toggle\", \"functional\"]:\n raise pytest.UsageError(msg)\n return value\n\ndef type_checker_sim(value):\n msg = \"UsageError --sim=\"\n if value not in [\"verilator\", \"vcs\"]:\n raise pytest.UsageError(msg)\n return value\n\ndef pytest_addoption(parser):\n parser.addoption(\n \"--coverage\", action=\"store\", default=\"toggle\", help=\"--coverage=\",type=type_checker_cov\n )\n parser.addoption(\n \"--sim\", action=\"store\", default=\"verilator\", help=\"--sim=\",type=type_checker_sim\n )\n parser.addoption(\n \"--conf_params\", action=\"store\", default=\"-set build_axi4\", help=\"--conf_params='...'\"\n )\n\n@pytest.fixture\ndef coverage_opt(request):\n return request.config.getoption(\"--coverage\")\n\n@pytest.fixture\ndef sim_opt(request):\n return request.config.getoption(\"--sim\")\n\n@pytest.fixture\ndef conf_params(request):\n return request.config.getoption(\"--conf_params\")\n" }, { "path": "verification/top/test_pyuvm/test_irq/irq_utils.py", "content": "#\n# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: BSD-2-Clause\n\nfrom cocotb.triggers import FallingEdge\nfrom cocotb.queue import Queue\n\nfrom pyuvm import *\n\n\ndef get_int(signal):\n try:\n sig = int(signal.value)\n except ValueError:\n sig = 0\n return sig\n\n\nclass IrqBfm(metaclass=utility_classes.Singleton):\n \"\"\"\n Interrupt Bus Functional Model\n\n Drive:\n el2_veer_wrapper {\n input logic nmi_int\n input logic timer_int\n input logic soft_int\n input logic [pt.PIC_TOTAL_INT:1] extintsrc_req\n }\n Receive:\n el2_veer_wrapper {\n output logic trace_rv_i_interrupt_ip\n }\n\n \"\"\"\n\n def __init__(self):\n self.dut = cocotb.top\n self.interrupt_driver_queue = Queue(maxsize=1)\n self.interrupt_source_queue = Queue(maxsize=0)\n self.trace_interrupt_queue = Queue(maxsize=0)\n self.interrupts = (self.dut.nmi_int,\n self.dut.soft_int,\n self.dut.timer_int,\n self.dut.extintsrc_req)\n\n async def send_interrupt_source(self, ints):\n await self.interrupt_driver_queue.put(ints)\n\n async def get_interrupt_source(self):\n ints = await self.interrupt_source_queue.get()\n return ints\n\n async def get_trace_interrupt(self):\n ints = await self.trace_interrupt_queue.get()\n return ints\n\n async def reset(self):\n await FallingEdge(self.dut.clk)\n self.dut.soft_int.value = 0\n self.dut.timer_int.value = 0\n self.dut.nmi_int.value = 0\n self.dut.extintsrc_req.value = 0\n await FallingEdge(self.dut.clk)\n\n async def interrupt_driver_bfm(self):\n self.dut.soft_int.value = 0\n self.dut.timer_int.value = 0\n self.dut.nmi_int.value = 0\n self.dut.extintsrc_req.value = 0\n while True:\n await FallingEdge(self.dut.clk)\n try:\n ints = self.interrupt_driver_queue.get_nowait()\n self.dut.soft_int.value = ints.soft\n self.dut.timer_int.value = ints.timer\n self.dut.nmi_int.value = ints.nmi\n self.dut.extintsrc_req.value = ints.ext\n except QueueEmpty:\n pass\n\n async def interrupt_source_bfm(self):\n while True:\n await FallingEdge(self.dut.clk)\n item = (\n get_int(self.dut.soft_int),\n get_int(self.dut.timer_int),\n get_int(self.dut.nmi_int),\n get_int(self.dut.extintsrc_req)\n )\n self.interrupt_source_queue.put_nowait(item)\n\n async def interrupt_trace_bfm(self):\n while True:\n await FallingEdge(self.dut.clk)\n item = get_int(self.dut.trace_rv_i_interrupt_ip)\n self.trace_interrupt_queue.put_nowait(item)\n\n def start_bfm(self):\n cocotb.start_soon(self.interrupt_driver_bfm())\n cocotb.start_soon(self.interrupt_source_bfm())\n cocotb.start_soon(self.interrupt_trace_bfm())\n" }, { "path": "verification/top/test_pyuvm/test_irq/irq_uvm.py", "content": "#\n# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: BSD-2-Clause\n\nimport random\nfrom pyuvm import *\nfrom .irq_utils import IrqBfm\n\n\nclass IrqRandomSeq(uvm_sequence):\n async def body(self):\n seqr = ConfigDB().get(None, \"\", \"SEQR\")\n random = vIrqSeq(\"random\")\n await random.start(seqr)\n\n\nclass vIrqSeq(uvm_sequence):\n async def body(self):\n for i in range(10):\n int_tr = IrqTriggerSeqItem(\"irq_trigger\", 0, 0, 0, 0)\n await self.start_item(int_tr)\n int_tr.randomize()\n await self.finish_item(int_tr)\n\n\nclass IrqTriggerSeqItem(uvm_sequence_item):\n def __init__(self, name, nmi, soft, timer, ext):\n super().__init__(name)\n self.nmi = nmi\n self.soft = soft\n self.timer = timer\n self.ext = ext\n\n def __eq__(self, other):\n same = self.nmi == other.nmi and self.soft == other.soft and self.timer == other.timer and self.ext == other.ext\n return same\n\n def __str__(self):\n return f\"{self.get_name()} : NMI {self.nmi}, SOFT: {self.soft}, TIMER: {self.timer}, EXT: {self.ext:0x}\"\n\n def randomize(self):\n self.nmi = random.randrange(2)\n self.soft = random.randrange(2)\n self.timer = random.randrange(2)\n self.ext = random.randrange(2)\n\n\nclass IrqMonitor(uvm_monitor):\n def __init__(self, name, parent, method_name):\n super().__init__(name, parent)\n self.method_name = method_name\n\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n self.bfm = IrqBfm()\n self.get_method = getattr(self.bfm, self.method_name)\n\n async def run_phase(self):\n while True:\n datum = await self.get_method()\n self.logger.debug(f\"MONITORED {datum}\")\n self.ap.write(datum)\n\n\nclass Scoreboard(uvm_component):\n def build_phase(self):\n self.interrupt_source_fifo = uvm_tlm_analysis_fifo(\"interrupt_source_fifo\",self)\n self.interrupt_source_get_port = uvm_get_port(\"interrupt_source_get_port\",self)\n self.interrupt_source_export = self.interrupt_source_fifo.analysis_export\n\n self.trace_interrupt_fifo = uvm_tlm_analysis_fifo(\"trace_interrupt_fifo\",self)\n self.trace_interrupt_get_port = uvm_get_port(\"trace_interrupt_get_port\",self)\n self.trace_interrupt_export = self.trace_interrupt_fifo.analysis_export\n\n def connect_phase(self):\n self.interrupt_source_get_port.connect(self.interrupt_source_fifo.get_export)\n self.trace_interrupt_get_port.connect(self.trace_interrupt_fifo.get_export)\n\n def check_phase(self):\n passed = True\n try:\n self.errors = ConfigDB().get(self, \"\", \"CREATE_ERRORS\")\n except UVMConfigItemNotFound:\n self.errors = False\n assert passed\n\n\nclass IrqDriver(uvm_driver):\n def build_phase(self):\n self.ap = uvm_analysis_port(\"ap\", self)\n\n def start_of_simulation_phase(self):\n self.bfm = IrqBfm()\n\n async def initialize_tb(self):\n await self.bfm.reset()\n self.bfm.start_bfm()\n\n async def run_phase(self):\n await self.initialize_tb()\n while True:\n ints = await self.seq_item_port.get_next_item()\n await self.bfm.send_interrupt_source(ints)\n result = await self.bfm.get_trace_interrupt()\n self.ap.write(result)\n self.seq_item_port.item_done()\n\nclass IrqAgent(uvm_agent):\n def build_phase(self):\n self.seqr = uvm_sequencer(\"seqr\", self)\n ConfigDB().set(None, \"*\", \"SEQR\", self.seqr)\n self.monitor = IrqMonitor(\"int_monitor\", self, \"get_interrupt_source\")\n self.driver = IrqDriver(\"int_driver\", self)\n\n def connect_phase(self):\n # Driver takes sequence items from sequencer\n self.driver.seq_item_port.connect(self.seqr.seq_item_export)\n\nclass VeerEl2Env(uvm_env):\n def build_phase(self):\n self.scoreboard = Scoreboard(\"scoreboard\", self)\n self.agent = IrqAgent(\"agent\",self)\n\n def connect_phase(self):\n # Monitor pushes observed data to the scoreboard\n self.agent.monitor.ap.connect(self.scoreboard.interrupt_source_export)\n\n # Driver\n self.agent.driver.ap.connect(self.scoreboard.trace_interrupt_export)\n" }, { "path": "verification/top/test_pyuvm/test_irq/test_irq.py", "content": "#\n# Copyright (c) 2023 Antmicro \n# SPDX-License-Identifier: BSD-2-Clause\n\nimport pyuvm\nfrom pyuvm import *\nfrom .irq_uvm import VeerEl2Env, IrqRandomSeq\nfrom cocotb.clock import Clock\n\n@pyuvm.test()\nclass BaseTest(uvm_test):\n def build_phase(self):\n self.set_default_logging_level(logging.DEBUG)\n self.env = VeerEl2Env(\"env\", self)\n\n def end_of_elaboration_phase(self):\n self.test_all = IrqRandomSeq.create(\"test_irq\")\n\n async def run_phase(self):\n self.raise_objection()\n clock = Clock(cocotb.top.clk, 10, units=\"ns\")\n cocotb.start_soon(clock.start(start_high=False))\n await self.test_all.start()\n self.drop_objection()\n" }, { "path": "verification/top/test_pyuvm/test_pyuvm.py", "content": "import pytest\nimport os\nimport subprocess\n\n\nclass TestPyUVM():\n\n @pytest.mark.parametrize(\"UVM_TEST\", [\"test_irq.test_irq\"])\n def test_pyuvm(self, UVM_TEST, coverage_opt, sim_opt, conf_params):\n\n os.environ[\"UVM_TEST\"] = UVM_TEST\n py_command = []\n py_command += [f\"COVERAGE_TYPE={coverage_opt}\"]\n py_command += [f\"SIM={sim_opt}\"]\n py_command += [f\"CONF_PARAMS='{conf_params}'\"]\n py_command += [\n \"make clean all\",\n ]\n py_command = \" \".join(py_command)\n\n print(f\"\\n----- PyTest -----\")\n print(f\":: py_command >> {py_command}\")\n p = subprocess.run(py_command, shell=True,\n executable=\"/bin/bash\", bufsize=0)\n print(f\"\\n------------------\")\n\n print(f\"----- Subprocess Summary -----\")\n print(f\"p.check_returncode\")\n p.check_returncode()\n print(f\"------------------------------\")\n" }, { "path": "violations.waiver", "content": "waive --rule=module-filename --location=\"design/lib/.*_lib.sv\"\nwaive --rule=line-length --location=\"design/ifu/.*.sv\"\nwaive --rule=line-length --location=\"design/dec/.*.sv\"\nwaive --rule=line-length --location=\"design/lsu/.*.sv\"\nwaive --rule=line-length --location=\"design/el2_.*_ctrl.sv\"\nwaive --rule=no-trailing-spaces --location=\"design/ifu/.*.sv\"\nwaive --rule=no-trailing-spaces --location=\"design/el2_.*_ctrl.sv\"\nwaive --rule=generate-label --location=\"design/lsu/el2_.*.sv\"\n\nwaive --rule=explicit-parameter-storage-type --location=\"design/el2_pmp.sv\"\nwaive --rule=explicit-parameter-storage-type --location=\"design/dec/el2_dec_pmp_ctl.sv\"\n" } ]