[
  {
    "path": ".editorconfig",
    "content": "# Editor config file, see http://editorconfig.org/\nroot = true\n\n[*]\ncharset = utf-8\nindent_style = space\nend_of_line = lf\ninsert_final_newline = true\ntrim_trailing_whitespace = true\n\n[*.{h,cpp}]\nindent_size = 2\n\n[*.py]\nindent_size = 4\n\n[*.html]\nindent_size = 2\n\n[Makefile]\nindent_style = tab\n\n[*.mk]\nindent_style = tab\n"
  },
  {
    "path": ".github/dependabot.yml",
    "content": "version: 2\nupdates:\n- package-ecosystem: gitsubmodule\n  directory: \"/\"\n  schedule:\n    interval: daily\n    # UTC\n    time: \"22:00\"\n  open-pull-requests-limit: 100\n"
  },
  {
    "path": ".github/workflows/comment-pr.yml",
    "content": "name: comment-pr\n\non:\n  workflow_run:\n    workflows: [\"sv-tests-ci\"]\n    types:\n      - completed\n\njobs:\n  Comment:\n    permissions:\n      pull-requests: write\n    name: Comment\n    runs-on: [ubuntu-latest]\n    if: ${{ github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success' }}\n    steps:\n      - name: Download artifacts\n        id: get-artifacts\n        uses: actions/github-script@v7\n        with:\n          script: |\n            var artifacts = await github.rest.actions.listWorkflowRunArtifacts({\n               owner: context.repo.owner,\n               repo: context.repo.repo,\n               run_id: ${{ github.event.workflow_run.id }},\n            });\n            var matchArtifact = artifacts.data.artifacts.filter((artifact) => {\n              return artifact.name == \"tests_summary\"\n            })[0];\n            var download = await github.rest.actions.downloadArtifact({\n               owner: context.repo.owner,\n               repo: context.repo.repo,\n               artifact_id: matchArtifact.id,\n               archive_format: 'zip',\n            });\n\n            core.setOutput('artifact_id', matchArtifact.id);\n\n            var fs = require('fs');\n            fs.writeFileSync('${{github.workspace}}/tests_summary.zip', Buffer.from(download.data));\n\n      - name: Unpack artifacts\n        run: |\n          unzip tests_summary.zip\n          cat ./tests_summary.md\n\n      - name: Generate and append artifacts link\n        run: |\n          ARTIFACT_ID=${{ steps.get-artifacts.outputs.artifact_id}}\n          ARTIFACT_URL=\"https://github.com/${{ github.repository }}/actions/runs/${{ github.event.workflow_run.id }}/artifacts/$ARTIFACT_ID\"\n          MD_URL=\"[Download an archive containing all the details]($ARTIFACT_URL)\"\n          echo -e \"\\n\\n$MD_URL\" >> tests_summary.md\n\n      - name: Show summary\n        run: |\n          cat tests_summary.md > $GITHUB_STEP_SUMMARY\n\n      - name: Prepare comment\n        id: get-comment-body\n        run: |\n          {\n            echo \"body<<EOF\"\n            cat tests_summary.md\n            echo EOF\n          } >> $GITHUB_OUTPUT\n\n      - name: Get PR number\n        id: get-pr-number\n        run: |\n          num=$(cat ./issue_num)\n          echo \"num=$num\" >> $GITHUB_OUTPUT\n\n      - name: Post comment\n        uses: KeisukeYamashita/create-comment@v1\n        with:\n          number: ${{ steps.get-pr-number.outputs.num }}\n          check-only-first-line: \"true\"\n          unique: \"true\"\n          token: ${{ secrets.GITHUB_TOKEN }}\n          comment: ${{ steps.get-comment-body.outputs.body }}\n"
  },
  {
    "path": ".github/workflows/lint-review.yml",
    "content": "name: lint-review\non:\n  pull_request:\n  workflow_dispatch:\n\njobs:\n  lint_review:\n    runs-on: ubuntu-latest\n    permissions:\n      checks: write\n      contents: read\n      pull-requests: write\n    steps:\n      - uses: actions/checkout@v2\n      - name: Run Verible action\n        uses: chipsalliance/verible-linter-action@main\n        with:\n          paths:\n            ./tests\n          github_token: ${{ secrets.GITHUB_TOKEN }}\n          suggest_fixes: 'false'\n"
  },
  {
    "path": ".github/workflows/report.sh",
    "content": "#!/bin/bash\nset -euxo pipefail\nmake $@ generate-tests\ncp -ar ./out/report_*/logs ./out/\nmake $@ report\n"
  },
  {
    "path": ".github/workflows/summary.sh",
    "content": "#!/bin/bash\nset -euxo pipefail\nset -x\nset -e\n\n#environment variables for this file are set in sv-tests-ci.yml\n\n# Get base report from sv-tests master run\ngit clone https://github.com/chipsalliance/sv-tests-results.git --depth 120 $REPORTS_HISTORY\n\n# Delete headers from all report.csv\nfor file in $(find ./out/report_* -name \"*.csv\" -print); do\n\tsed -i.backup 1,1d $file\ndone\n\n# concatenate test reports\ncat $(find ./out/report_* -name \"*.csv\" -print) >> $COMPARE_REPORT\n\n# Insert header at the first line of concatenated report\nsed -i 1i\\ $(head -1 $(find ./out/report_* -name \"*.csv.backup\" -print -quit)) $COMPARE_REPORT\n\npython $ANALYZER $COMPARE_REPORT $BASE_REPORT -o $CHANGES_SUMMARY_JSON -t $CHANGES_SUMMARY_MD\n\n# generate history graph\npython $GRAPHER -n 120 -r $REPORTS_HISTORY\n\nset +e\nset +x\n"
  },
  {
    "path": ".github/workflows/sv-tests-ci.yml",
    "content": "name: sv-tests-ci\n\non:\n  push:\n    branches:\n      - master\n  pull_request:\n  workflow_dispatch:\n  schedule:\n    - cron: '0 1 * * *' # run daily at 01:00 am (UTC)\n\njobs:\n  Run:\n    strategy:\n      fail-fast: false\n      matrix:\n        tool:\n          - name: icarus\n            deps: autoconf autotools-dev bison flex libfl-dev gperf\n          - name: moore\n            rust_ver: \"1.61\"\n          - name: odin\n            repo: odin_ii\n            deps: autoconf autotools-dev bison flex libfl-dev cmake pkg-config\n          - name: slang\n            deps: cmake pkg-config\n          - name: surelog\n            repo: Surelog\n            submodules: third_party/UHDM third_party/antlr4 third_party/googletest\n            deps: cmake default-jre pkg-config tclsh uuid-dev\n          - name: sv-parser\n            deps: cargo\n            rust_ver: \"1.94\"\n          - name: tree-sitter-systemverilog\n            deps: gcc\n          - name: tree-sitter-verilog\n            deps: gcc\n          - name: verible\n            deps: bazel=7.6.1 bison flex libfl-dev\n            skip-ccache: 1\n          - name: verilator\n            deps: autoconf autotools-dev bison flex help2man libfl-dev libelf-dev\n            make_jobs_max: 4\n          - name: yosys\n            deps: bison clang tcl-dev flex libfl-dev pkg-config libreadline-dev\n          - name: yosys-synlig\n            repo: synlig\n            submodules: third_party/yosys third_party/surelog\n            deps: cmake clang tcl-dev bison default-jre flex libfl-dev libreadline-dev pkg-config tclsh uuid-dev\n            runners_filter: SynligYosys\n          - name: zachjs-sv2v\n            deps: haskell-stack\n          - name: yosys-slang\n            deps: bison clang tcl-dev flex libfl-dev pkg-config libreadline-dev cmake pkg-config\n            submodules: third_party/slang\n          - name: circt-verilog\n            deps: cmake clang ninja-build lld\n            submodules: llvm\n    env:\n      RUNNERS_FILTER: ${{ matrix.tool.runners_filter }}\n      CCACHE_DIR: \"/root/sv-tests/sv-tests/.cache/\"\n      # those generators can use a lot of RAM/cpu and starve other tests\n      # tests from those generators are run without \"-j\" flag\n      BIG_GENERATORS: \"fusesoc black-parrot\"\n      DEBIAN_FRONTEND: \"noninteractive\"\n      GHA_MACHINE_TYPE: \"n2-highmem-16\"\n\n    name: ${{ matrix.tool.name }}\n    runs-on: [self-hosted, Linux, X64, gcp-custom-runners]\n    container: ubuntu:jammy-20221130\n    steps:\n      - name: Cancel previous\n        uses: styfle/cancel-workflow-action@0.8.0\n        with:\n          access_token: ${{ github.token }}\n      - name: Show shell\n        run: |\n          echo \"$SHELL\"\n      - name: Checkout code\n        uses: actions/checkout@v2\n      - name: Update apt repos\n        run: |\n          apt-get update -qq\n      - name: Setup Node\n        run: |\n          apt -qq -y install curl\n          touch \"$HOME/.bash_profile\"\n          # From https://nodejs.org/en/download\n          curl -o- https://raw.githubusercontent.com/nvm-sh/nvm/v0.40.2/install.sh | bash\n          . \"$HOME/.nvm/nvm.sh\"\n          nvm install 22\n      - name: Add bazel repo (if needed)\n        if: ${{ contains(matrix.tool.deps, 'bazel') }}\n        run: |\n          apt -qq -y install apt-transport-https curl gnupg\n          curl -fsSL https://bazel.build/bazel-release.pub.gpg | gpg --dearmor > bazel.gpg\n          chmod a+r bazel.gpg\n          mv bazel.gpg /etc/apt/trusted.gpg.d/\n          echo \"deb [arch=amd64] https://storage.googleapis.com/bazel-apt stable jdk1.8\" | tee /etc/apt/sources.list.d/bazel.list\n          apt-get update -qq\n      - name: Install common dependencies\n        run: |\n          apt install -y python3 python3-pip git wget file\n          update-alternatives --install /usr/bin/python python /usr/bin/python3 1\n          update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1\n          pip install --use-pep517 --upgrade setuptools\n          pip install --use-pep517 -r conf/requirements.txt\n      - name: Install VeeR dependencies\n        run: |\n          apt install -y cpanminus\n          cpanm Bit::Vector JSON\n      - name: Install ccache\n        if: ${{ !matrix.tool.skip-ccache }}\n        run: |\n          apt install -y ccache\n      - name: Install tool-specific dependencies\n        if: ${{ matrix.tool.deps }}\n        run: |\n          apt -qq -y install ${{ matrix.tool.deps }}\n      - name: Setup Rust (if needed)\n        if: ${{ matrix.tool.rust_ver }}\n        run: |\n          apt -y install curl\n          curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs > setup.sh\n          sh setup.sh -y\n          source $HOME/.cargo/env\n          rustup install ${{ matrix.tool.rust_ver }}\n          rustup default ${{ matrix.tool.rust_ver }}\n      - name: Update haskell (if needed)\n        if: ${{ contains(matrix.tool.deps, 'haskell') }}\n        run: |\n          stack upgrade\n      - name: Checkout the tool submodule\n        run: |\n          # Github dropped support for unauthorized git: https://github.blog/2021-09-01-improving-git-protocol-security-github/\n          # Make sure we always use https:// instead of git://\n          git config --global url.https://github.com/.insteadOf git://github.com/\n          # take verilator from github (some tested tools still use a submodule\n          # from veripool)\n          git config --global url.\"https://github.com/verilator/verilator\".insteadOf http://git.veripool.org/git/verilator\n          REPOSITORY_NAME=${{ matrix.tool.name }}\n          if [[ ! -z \"${{ matrix.tool.repo }}\" ]]; then\n            REPOSITORY_NAME=${{ matrix.tool.repo }}\n          fi\n          git submodule update --init --depth 1 third_party/tools/${REPOSITORY_NAME}\n          if [[ ! -z \"${{ matrix.tool.submodules }}\" ]]; then\n            pushd third_party/tools/${REPOSITORY_NAME}\n            git submodule update --init --recursive --depth 1 ${{ matrix.tool.submodules }}\n            popd\n          fi\n          # yosys tool contains tests, is a dependency of other tools\n          git submodule update --init --recursive --depth 1 third_party/tools/yosys\n          # icarus contains tests\n          git submodule update --init --depth 1 third_party/tools/icarus\n      - name: Create Cache Timestamp\n        id: cache_timestamp\n        uses: nanzm/get-time-action@v1.1\n        with:\n          format: 'YYYY-MM-DD-HH-mm-ss'\n      - name: Setup cache\n        uses: actions/cache@v4\n        timeout-minutes: 3\n        continue-on-error: true\n        with:\n          path: \"/root/sv-tests/sv-tests/.cache/\"\n          key: cache_${{ matrix.tool.name }}_${{ steps.cache_timestamp.outputs.time }}\n          restore-keys: cache_${{ matrix.tool.name }}_\n      - name: Build\n        run: |\n          export PATH=\"/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH\"\n          [[ -f $HOME/.cargo/env ]] && source $HOME/.cargo/env\n          . \"$HOME/.bash_profile\"  # GitHub Actions runs bash with --noprofile\n          make ${{ matrix.tool.name }} -j$(nproc)\n      - name: Check\n        run:\n          make info\n      - name: Checkout third party tests and cores\n        run: |\n          git submodule update --init --recursive --depth 1 third_party/tests\n          git submodule update --init --recursive --depth 1 third_party/cores\n      - name: Run\n        run: |\n          BIG_GENERATORS_EXPR=$(echo $BIG_GENERATORS | sed 's/ /\\\\|/g')\n          export STABLE_GENERATORS=$(make list-generators | tr ' ' '\\n' | grep -v \"${BIG_GENERATORS_EXPR}\")\n          export UNSTABLE_GENERATORS=$(make list-generators | tr ' ' '\\n' | grep \"${BIG_GENERATORS_EXPR}\")\n          export JOBS=${{ matrix.tool.make_jobs_max }}\n          if [[ \"${JOBS}x\" == \"x\" ]]; then export JOBS=$(nproc); fi\n          for gen in ${STABLE_GENERATORS}; do echo \"==GEN stable $gen -j $JOBS\" ; make generate-$gen -j${JOBS}; make -j ${JOBS}; done\n          for gen in ${UNSTABLE_GENERATORS}; do echo \"==GEN unstable $gen\" ; make generate-$gen; make; done\n      - name: Prepare Report\n        run:\n          mv out/report/report.csv out/report/${{ matrix.tool.name }}_report.csv\n      - name: Pack results\n        run: |\n          tar -cvf out_${{ matrix.tool.name }}.tar ./out/report/${{ matrix.tool.name }}_report.csv ./out/logs/\n      - uses: actions/upload-artifact@v4\n        with:\n          name: report_${{ matrix.tool.name }}\n          path: |\n            out_${{ matrix.tool.name }}.tar\n            **/plot_*.svg\n\n  Summary:\n    name: Summary\n    runs-on: [self-hosted, Linux, X64, gcp-custom-runners]\n    container: ubuntu:jammy-20221130\n    needs: Run\n    env:\n      ANALYZER: \"$PWD/tools/report_analyzer.py\"\n      GRAPHER: \"$PWD/tools/history-graph\"\n      OUT_REPORT_DIR: \"$PWD/out/report/\"\n      COMPARE_REPORT: \"$OUT_REPORT_DIR/report.csv\"\n      REPORTS_HISTORY: \"$(mktemp -d --suffix='.history')\"\n      BASE_REPORT: \"$REPORTS_HISTORY/report.csv\"\n      CHANGES_SUMMARY_JSON: \"$OUT_REPORT_DIR/tests_summary.json\"\n      CHANGES_SUMMARY_MD: \"$OUT_REPORT_DIR/tests_summary.md\"\n      TESTS_SUMMARY_DIR: \"tests_summary/\"\n      DEBIAN_FRONTEND: \"noninteractive\"\n    steps:\n      - name: Checkout code\n        uses: actions/checkout@v2\n      - name: Setup python\n        run: |\n          apt-get update -qq\n          apt install -y python3 python3-pip wget git curl jq\n          update-alternatives --install /usr/bin/python python /usr/bin/python3 1\n          update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1\n          pip install --use-pep517 --upgrade setuptools\n          pip install --use-pep517 -r conf/requirements.txt\n      - name: Install VeeR dependencies\n        run: |\n          apt install -y cpanminus\n          cpanm Bit::Vector JSON\n      - name: Prepare output directories\n        run: |\n          mkdir -p out/report\n      - uses: actions/download-artifact@v4\n        with:\n          path: ./out/\n      - name: Extract\n        run: |\n          for file in $(find out/ -name *.tar -print); do tar -xf $file --strip-components=2 -C $(dirname $file); done\n      - name: Checkout third party tests and cores\n        run: |\n          # take verilator from github\n          git config --global url.\"https://github.com/verilator/verilator\".insteadOf http://git.veripool.org/git/verilator\n          git submodule update --init --recursive --depth 1 third_party/tests\n          git submodule update --init --recursive --depth 1 third_party/cores\n          # yosys tool also contains tests\n          git submodule update --init --recursive --depth 1 third_party/tools/yosys\n          # icarus contains tests\n          git submodule update --init --depth 1 third_party/tools/icarus\n      - name: Summary\n        run: |\n          ./.github/workflows/summary.sh\n          ./.github/workflows/report.sh\n      - name: Update sv-tests-results repository\n        if: github.ref == 'refs/heads/master'\n        run: |\n          eval $(ssh-agent -s)\n          ssh-add - <<< \"${{ secrets.REPORT_DEPLOY_KEY }}\"\n          mkdir -p ~/.ssh\n          chmod 700 ~/.ssh\n          ssh-keyscan -t rsa github.com >> ~/.ssh/known_hosts\n          ./.github/workflows/update_report.sh\n      - name: Prepare artifacts for PR commenter\n        if: github.event_name == 'pull_request'\n        run: |\n          mkdir $TESTS_SUMMARY_DIR\n          echo ${{ github.event.number }} > $TESTS_SUMMARY_DIR/issue_num\n          cp $COMPARE_REPORT $TESTS_SUMMARY_DIR/report_base.csv\n          cp $OUT_REPORT_DIR/report.csv $TESTS_SUMMARY_DIR/report_new.csv\n          cp $OUT_REPORT_DIR/new_*csv $TESTS_SUMMARY_DIR\n          cp $OUT_REPORT_DIR/tests_summary.json $TESTS_SUMMARY_DIR\n          cp $OUT_REPORT_DIR/tests_summary.md $TESTS_SUMMARY_DIR\n          find out -name plot_*.svg -exec cp {} $TESTS_SUMMARY_DIR \\;\n\n      - name: Post GitHub summary\n        run: |\n          cat $CHANGES_SUMMARY_MD > $GITHUB_STEP_SUMMARY\n\n      - name: Upload artifacts for summary\n        uses: actions/upload-artifact@v4\n        if: github.event_name == 'pull_request'\n        with:\n          name: tests_summary\n          path: |\n            ./tests_summary/\n      - name: Find artifacts that are no longer needed\n        id: get-artifacts-to-delete\n        if: github.event_name == 'pull_request'\n        run: |\n          artifacts=$(find ./out -type d -name 'report_*' -exec basename {} \\;)\n          echo $artifacts\n          artifacts=\"${artifacts//'%'/'%25'}\"\n          artifacts=\"${artifacts//$'\\n'/'%0A'}\"\n          artifacts=\"${artifacts//$'\\r'/'%0D'}\"\n          echo \"artifacts=$artifacts\" >> GITHUB_OUTPUT\n          echo $artifacts\n      - name: Delete Old Artifacts\n        if: github.event_name == 'pull_request'\n        uses: geekyeggo/delete-artifact@v5\n        with:\n          name: ${{ steps.get-artifacts-to-delete.outputs.artifacts }}\n  Automerge:\n    name: Automerge dependabot pull requests\n    permissions:\n      pull-requests: write\n      contents: write\n    runs-on: ubuntu-latest\n    needs: Summary\n    if: ${{ github.event_name == 'pull_request' && github.event.pull_request.user.login == 'dependabot[bot]' }}\n    steps:\n      - name: Dependabot metadata\n        id: metadata\n        uses: dependabot/fetch-metadata@v1.1.1\n        with:\n          github-token: \"${{ secrets.GITHUB_TOKEN }}\"\n      - name: Enable auto-merge for Dependabot PRs\n        run: gh pr merge --auto --merge \"$PR_URL\"\n        env:\n          PR_URL: ${{ github.event.pull_request.html_url }}\n          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}\n"
  },
  {
    "path": ".github/workflows/sv-tests-code-quality.yml",
    "content": "name: \"Code Quality Checks\"\n\non:\n  push:\n  pull_request:\n  workflow_dispatch:\n\njobs:\n  Test:\n    name: \"Code Quality Checks\"\n    runs-on: ubuntu-latest\n    steps:\n      - name: Checkout code\n        uses: actions/checkout@v3\n        with:\n          submodules: true\n      - uses: actions/setup-python@v4\n        with:\n          python-version: 3.8\n      - name: Script\n        run:\n          pip install -r conf/requirements.txt\n      - name: Make\n        run:\n          make format\n      - name: Test\n        run:\n          test $(git status --porcelain | wc -l) -eq 0 || { git diff; false; }\n      - name: License\n        uses: SymbiFlow/actions/checks@main\n        with:\n          exclude_directory: |\n            ./.git/\n            ./.github/\n            ./.dependabot/\n            ./miniconda.sh\n            ./build/\n          third_party: |\n            ./third_party/cores/\n            ./third_party/tests/\n            ./third_party/tools/\n\n"
  },
  {
    "path": ".github/workflows/update_report.sh",
    "content": "#!/bin/bash\nset -euxo pipefail\n\nexport CURRENT_PATH=$PWD\n\nset -ex\n\ngit clone \\\n  git@github.com:chipsalliance/sv-tests-results.git \\\n  --single-branch \\\n  --depth 1 \\\n  --branch gh-pages \\\n  output\n\ncd output || (echo \"The output directory doesn't exist! Cloning the sv-tests-results repository failed, please check the ssh-key! Exiting\"; exit 1)\n\nrm -rf *\ncp -a $CURRENT_PATH/out/report/* -t .\ntouch .nojekyll\ngit add .\n\nGIT_MESSAGE_FILE=/tmp/git-message\n  cat > $GIT_MESSAGE_FILE <<EOF\nDeploy $GITHUB_REF (build $GITHUB_RUN_ID)\nBuild from $GITHUB_SHA\nEOF\n\ngit config user.name \"SymbiFlow Robot\"\ngit config user.email \"foss-fpga-tools@google.com\"\n\ngit commit -F $GIT_MESSAGE_FILE\n\ngit show -s\n\ngit push\n"
  },
  {
    "path": ".gitignore",
    "content": "out\nbuild\ntests/generated\n__pycache__\nvenv\n"
  },
  {
    "path": ".gitmodules",
    "content": "[submodule \"third_party/tests/hdlconvertor\"]\n\tpath = third_party/tests/hdlconvertor\n\turl = https://github.com/Nic30/hdlConvertor\n[submodule \"third_party/cores/basejump_stl\"]\n\tpath = third_party/cores/basejump_stl\n\turl = https://github.com/bespoke-silicon-group/basejump_stl\n[submodule \"third_party/cores/ariane\"]\n\tpath = third_party/cores/ariane\n\turl = https://github.com/pulp-platform/ariane\n[submodule \"third_party/tools/odin_ii\"]\n\tpath = third_party/tools/odin_ii\n\turl = https://github.com/verilog-to-routing/vtr-verilog-to-routing.git\n[submodule \"third_party/tools/icarus\"]\n\tpath = third_party/tools/icarus\n\turl = https://github.com/steveicarus/iverilog.git\n[submodule \"third_party/tools/slang\"]\n\tpath = third_party/tools/slang\n\turl = https://github.com/MikePopoloski/slang.git\n[submodule \"third_party/tools/yosys\"]\n\tpath = third_party/tools/yosys\n\turl = https://github.com/YosysHQ/yosys.git\n[submodule \"third_party/tools/zachjs-sv2v\"]\n\tpath = third_party/tools/zachjs-sv2v\n\turl = https://github.com/zachjs/sv2v\n[submodule \"third_party/cores/veer-eh1\"]\n\tpath = third_party/cores/veer-eh1\n\turl = https://github.com/chipsalliance/Cores-VeeR-EH1\n[submodule \"third_party/cores/ibex\"]\n\tpath = third_party/cores/ibex\n\turl = https://github.com/lowRISC/ibex\n[submodule \"third_party/tools/tree-sitter-verilog\"]\n\tpath = third_party/tools/tree-sitter-verilog\n\turl = https://github.com/tree-sitter/tree-sitter-verilog\n[submodule \"third_party/tools/tree-sitter-systemverilog\"]\n\tpath = third_party/tools/tree-sitter-systemverilog\n\turl = https://github.com/gmlarumbe/tree-sitter-systemverilog\n[submodule \"third_party/cores/fx68k\"]\n\tpath = third_party/cores/fx68k\n\turl = https://github.com/ijor/fx68k\n[submodule \"third_party/tools/sv-parser\"]\n\tpath = third_party/tools/sv-parser\n\turl = https://github.com/dalance/sv-parser\n[submodule \"third_party/cores/scr1\"]\n\tpath = third_party/cores/scr1\n\turl = https://github.com/syntacore/scr1\n[submodule \"third_party/tools/verible\"]\n\tpath = third_party/tools/verible\n\turl = https://github.com/chipsalliance/verible.git\n[submodule \"third_party/tools/Surelog\"]\n\tpath = third_party/tools/Surelog\n\turl = https://github.com/chipsalliance/Surelog.git\n[submodule \"third_party/cores/rsd\"]\n\tpath = third_party/cores/rsd\n\turl = https://github.com/rsd-devel/rsd\n[submodule \"third_party/cores/black-parrot\"]\n\tpath = third_party/cores/black-parrot\n\turl = https://github.com/black-parrot/black-parrot\n\tbranch = dev\n[submodule \"third_party/tests/easyUVM\"]\n\tpath = third_party/tests/easyUVM\n\turl = https://github.com/antmicro/easyUVM.git\n[submodule \"third_party/tests/uvm\"]\n\tpath = third_party/tests/uvm\n\turl = https://github.com/SymbiFlow/uvm.git\n\tbranch = uvm-2020-3.1-vlt\n[submodule \"third_party/cores/tnoc\"]\n\tpath = third_party/cores/tnoc\n\turl = https://github.com/taichi-ishitani/tnoc.git\n[submodule \"third_party/tests/utd-sv\"]\n\tpath = third_party/tests/utd-sv\n\turl = https://github.com/SymbiFlow/utd-sv.git\n[submodule \"third_party/tests/axi-vip\"]\n\tpath = third_party/tests/axi-vip\n\turl = https://github.com/SymbiFlow/axi-vip.git\n[submodule \"third_party/tools/synlig\"]\n\tpath = third_party/tools/synlig\n\turl = https://github.com/chipsalliance/synlig.git\n[submodule \"third_party/tests/projf-explore\"]\n\tpath = third_party/tests/projf-explore\n\turl = https://github.com/projf/projf-explore.git\n[submodule \"third_party/tools/moore\"]\n\tpath = third_party/tools/moore\n\turl = https://github.com/fabianschuiki/moore.git\n[submodule \"third_party/cores/rggen-sample\"]\n\tpath = third_party/cores/rggen-sample\n\turl = https://github.com/rggen/rggen-sample.git\n[submodule \"third_party/cores/rggen-sv-rtl\"]\n\tpath = third_party/cores/rggen-sv-rtl\n\turl = https://github.com/rggen/rggen-sv-rtl.git\n[submodule \"third_party/cores/veer-el2\"]\n\tpath = third_party/cores/veer-el2\n\turl = https://github.com/chipsalliance/Cores-VeeR-EL2.git\n[submodule \"third_party/tools/yosys-slang\"]\n\tpath = third_party/tools/yosys-slang\n\turl = https://github.com/povik/yosys-slang.git\n[submodule \"third_party/tools/circt-verilog\"]\n\tpath = third_party/tools/circt-verilog\n\turl = https://github.com/llvm/circt.git\n\tbranch = main\n[submodule \"third_party/tools/verilator\"]\n\tpath = third_party/tools/verilator\n\turl = https://github.com/verilator/verilator\n"
  },
  {
    "path": ".style.yapf",
    "content": "[style]\nbased_on_style = pep8\nsplit_before_expression_after_opening_paren = True\nsplit_before_first_argument = True\nsplit_complex_comprehension = True\nsplit_penalty_comprehension = 2100\n"
  },
  {
    "path": "AUTHORS",
    "content": "# This is the list of sv-tests's significant contributors.\n#\n# This does not necessarily list everyone who has contributed code,\n# especially since many employees of one corporation may be contributing.\n# To see the full list of contributors, see the revision history in\n# source control.\nAntmicro\nGoogle LLC\n\nAhmad Hegazy\nFabian Schuiki\nMike Popoloski\nNaoya Hatta\nWilson Snyder\nZachary Snow\n"
  },
  {
    "path": "LICENSE",
    "content": "Copyright (C) 2020 The Symbiflow Authors\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n"
  },
  {
    "path": "Makefile",
    "content": "# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nall: report\n\nOUT_DIR ?= ./out/\nCONF_DIR ?= ./conf\nTESTS_DIR ?= ./tests\nBUILD_DIR ?= ./build\nRUNNERS_DIR ?= ./tools/runners\nTHIRD_PARTY_DIR ?= ./third_party\nGENERATORS_DIR ?= ./generators\n\nUSE_CGROUP := ${USE_CGROUP}\nCGROUP_MAX_MEMORY ?= 3221225472  # 3GiB\n\nexport OUT_DIR\nexport CONF_DIR\nexport THIRD_PARTY_DIR\nexport TESTS_DIR\nexport RUNNERS_DIR\nexport GENERATORS_DIR\n\nifneq ($(DISABLE_TEST_TIMEOUTS),)\nexport DISABLE_TEST_TIMEOUTS\nendif\n\nifneq ($(OVERRIDE_TEST_TIMEOUTS),)\nexport OVERRIDE_TEST_TIMEOUTS\nendif\n\ninclude tools/runners.mk\n\n.PHONY: clean init info tests generate-tests report\n\nclean:\n\trm -rf $(OUT_DIR)\n\trm -rf $(BUILD_DIR)\n\trm -rf $(TESTS_DIR)/generated/\n\ninit:\nifneq (,$(wildcard $(OUT_DIR)/*))\n\t@echo -e \"!!! WARNING !!!\\nThe output directory is not empty\\n\"\nendif\n\nrunners:\n\nifneq ($(RUNNER_KEEP_TMP),)\nRUNNER_PARAM := --keep-tmp\nelse\nRUNNER_PARAM := --quiet\nendif\n\n# $(1) - runner name\n# $(2) - test\ndefine runner_test_gen\n\n# Set the runner value for the log target\nifneq ($(USE_CGROUP),)\n$(OUT_DIR)/logs/$(1)/$(2).log : RUNNER = cgexec -g memory,cpu:$(USE_CGROUP)/$(1) ./tools/runner\nelse\n$(OUT_DIR)/logs/$(1)/$(2).log : RUNNER = ./tools/runner\nendif\n\n$(OUT_DIR)/logs/$(1)/$(2).log: $(TESTS_DIR)/$(2) | $(1)-cg\n\tRUNNERS_DIR=$(RUNNERS_DIR) $$(RUNNER) --runner $(1) --test $(2) --out $(OUT_DIR)/logs/$(1)/$(2).log $(RUNNER_PARAM)\n\ntests: $(OUT_DIR)/logs/$(1)/$(2).log\n\nendef\n\n# $(1) - runner name\ndefine runner_cg_gen\nifneq ($(USE_CGROUP),)\n\n/sys/fs/cgroup/memory/$(USE_CGROUP)/$(1):\n\t# Create a sub-cgroup for each runner under the $(USE_CGROUP) group.\n\tcgcreate -g memory,cpu:$(USE_CGROUP)/$(1)\n\n$(1)-cg: /sys/fs/cgroup/memory/$(USE_CGROUP)/$(1)\n\t# Limit a single runner memory\n\techo $(CGROUP_MAX_MEMORY) > /sys/fs/cgroup/memory/$(USE_CGROUP)/$(1)/memory.limit_in_bytes\n\nelse\n$(1)-cg:\n\t@true\nendif\n\nendef\n\ndefine runner_version_gen\n$(OUT_DIR)/logs/$(1)/version:\n\t./tools/runner --runner $(1) --version --out $(OUT_DIR)/logs/$(1)/version\n\nversions: $(OUT_DIR)/logs/$(1)/version\nendef\n\ndefine runner_url_gen\n$(OUT_DIR)/logs/$(1)/url:\n\t./tools/runner --runner $(1) --url --out $(OUT_DIR)/logs/$(1)/url\n\nurls: $(OUT_DIR)/logs/$(1)/url\nendef\n\ndefine generator_gen\ngenerate-$(1):\n\t$(GENERATORS_DIR)/$(1) $(1)\n\ngenerate-tests: generate-$(1)\nendef\n\nRUNNERS_FOUND := $(wildcard $(RUNNERS_DIR)/*.py)\nRUNNERS_FOUND := $(RUNNERS_FOUND:$(RUNNERS_DIR)/%=%)\nRUNNERS_FOUND := $(sort $(basename $(RUNNERS_FOUND)))\n\nifdef RUNNERS_FILTER\nFILTER := --filter $(RUNNERS_FILTER)\nendif\n\nRUNNERS := $(sort $(shell OUT_DIR=$(OUT_DIR) RUNNERS_DIR=$(RUNNERS_DIR) \\\n                          TREE_SITTER_SVERILOG_PARSER_DIR=$(TREE_SITTER_SVERILOG_PARSER_DIR) \\\n                          TREE_SITTER_VERILOG_PARSER_DIR=$(TREE_SITTER_VERILOG_PARSER_DIR) \\\n\t\t\t  ./tools/check-runners $(RUNNERS_FOUND) $(FILTER)))\nTESTS := $(shell find $(TESTS_DIR) -type f -iname *.sv)\nTESTS := $(TESTS:$(TESTS_DIR)/%=%)\nGENERATORS := $(wildcard $(GENERATORS_DIR)/*)\nGENERATORS := $(GENERATORS:$(GENERATORS_DIR)/%=%)\n\nspace := $(subst ,, )\n\nifneq ($(USE_ALL_RUNNERS),)\nifneq ($(RUNNERS), $(RUNNERS_FOUND))\n$(warning Runners found: $(RUNNERS_FOUND))\n$(warning Runners defined: $(RUNNERS))\n$(error Some runners are missing)\nendif\nendif\n\ninfo:\n\t@echo -e \"Found the following runners:$(subst $(space),\"\\\\n \\* \", $(RUNNERS))\\n\"\n\nPY_FILES := $(shell file generators/* tools/* | sed -ne 's/:.*[Pp]ython.*//p')\nPY_FILES += $(wildcard tools/*.py)\nPY_FILES += $(wildcard tools/runners/*.py)\nPY_FILES += $(wildcard conf/report/*.py)\n\nformat:\n\tpython3 -m yapf -p -i $(PY_FILES)\n\ntests:\n\ngenerate-tests:\n\nurls:\n\nversions:\n\nreport: init tests versions urls\n\t./tools/sv-report --revision $(shell git rev-parse --short HEAD)\n\tcp $(CONF_DIR)/report/*.css $(OUT_DIR)/report/\n\tcp $(CONF_DIR)/report/*.js $(OUT_DIR)/report/\n\tcp $(CONF_DIR)/report/*.png $(OUT_DIR)/report/\n\tcp $(CONF_DIR)/report/*.svg $(OUT_DIR)/report/\n\nlist-generators:\n\t@echo $(GENERATORS)\n\n$(foreach g, $(GENERATORS), $(eval $(call generator_gen,$(g))))\n$(foreach r, $(RUNNERS),$(foreach t, $(TESTS),$(eval $(call runner_test_gen,$(r),$(t)))))\n$(foreach r, $(RUNNERS),$(eval $(call runner_cg_gen,$(r))))\n$(foreach r, $(RUNNERS),$(eval $(call runner_version_gen,$(r))))\n$(foreach r, $(RUNNERS),$(eval $(call runner_url_gen,$(r))))\n"
  },
  {
    "path": "README.md",
    "content": "# SystemVerilog Tester\n\n[![License](https://img.shields.io/github/license/chipsalliance/sv-tests.svg)](https://github.com/chipsalliance/sv-tests/blob/master/LICENSE)\n[![Build Status](https://github.com/chipsalliance/sv-tests/workflows/sv-tests-ci/badge.svg?branch=master)](https://github.com/chipsalliance/sv-tests/actions)\n\nThe purpose of this project is to find all the supported and missing SystemVerilog features in various Verilog tools.\n\nThe report generated from the last passing master build can be viewed [on a dedicated dashboard:](https://chipsalliance.github.io/sv-tests-results/)\n[![Grid](./img/sv-test-grid.png)](https://chipsalliance.github.io/sv-tests-results/)\n\nHistory of the builds is also tracked and can be seen [on a separate page:](https://chipsalliance.github.io/sv-tests-results/history)\n[![History](./img/sv-test-history.png)](https://chipsalliance.github.io/sv-tests-results/history)\n\n# Running\n\nInitialize the submodules:\n\n```bash\ngit submodule update --init --recursive\n```\n\nInstall all the python dependencies and make sure the installed binaries can be called.\n\n```bash\npip3 install --user -r conf/requirements.txt\nexport PATH=~/.local/bin:$PATH\n```\n\nBuild tools (optional, tools from `PATH` can be used):\n\n```bash\nmake -k runners\n```\n\nAnd then just run:\n\n```bash\nmake generate-tests -j$(nproc)\nmake -j$(nproc)\n```\n\nThis should generate many log files for all the tools/tests combinations and an `out/report.html` file with a summary of the tested features and tools.\n\nIf you don't want to generate the report file, but are interested in just running all the tests, you can run:\n\n```bash\nmake tests\n```\n\n## Adding new test cases\n\nAdding a new test case is a two step process.\nFirst you create the test case itself which should use only a minimal required subset of SystemVerilog to test a particular feature.\nAdditionally each test should cover only a single feature.\nIf the test must use several features, each of those must be also covered in separate test cases.\n\nAfter creating a new test case it must be correctly tagged:\n\n* `name` - must be unique and should be directly related to what the test case covers.\n* `description` - should provide a short description that will be visible in the report page.\n* `should_fail_because` - must be used if the test is expected to fail and should contain the reason of failure.\n* `files` - is a list of files used by this test case, can be omitted to use only the main file with metadata.\n* `incdirs` - can be used to provide a list of include directories, can be omitted to use only the default ones.\n* `top_module` - optional, allows to specify which module is the top one.\n* `tags` - tag must be used to specify which part of SystemVerilog specification this test case covers.\n* `defines` - provides a list of macros for preprocessor.\n  If the test case uses several SystemVerilog features, only the feature directly tested should be included in tags.\n  List of existing tags is located in `conf/lrm.conf`.\n\nFinally the file containing the test case and metadata should be placed in `tests/chapter-([0-9]+)/` subdirectory based on the `tags` fields specified earlier.\n\n## Importing existing tests from a test suite/core/tool\n\n1. Add the tests as a submodule to this repository via `git submodule add <git_url> third_party/<category>/<name>`.\n   If you want to add tests from a tool that is already in `third_party/tools` you can skip this step.\n2. Add a new tag named `<name>` to `conf/lrm.conf` together with a short description.\n3. Generate wrapper `.sv` files by either:\n   * Adding a new config to `conf/generators/meta-path/` that will be used by `generators/path_generator`.\n   * Adding a new generator script to `generators/` that will create required wrappers.\n\n   First method works well with test suites in which each test case is contained in a separate Verilog file.\n   If the test suite provides metadata that must be processed or you are importing an IP core then you should create custom generator script.\n\n   Use tag that you added in the previous step.\n\n## Adding a new tool\n\n1. Add the tool as a submodule to this repository via `git submodule add <git_url> third_party/tools/<name>`.\n2. Add a target for building and installing the tool manually in `tools/runners.mk`\n3. Create a new runner script in `tools/runners/<name>.py` that will contain a subclass of `BaseRunner` named `<name>`.\n   This subclass will need to at least implement the following methods:\n   * `__init__` to provide general information about the tool.\n   * `prepare_run_cb` to prepare correct tool invocation that will be used during tests.\n\n   If the new tool is a Python library, reimplement `run` and other supporting methods instead of implementing `prepare_run_cb`.\n\n## Supported tools\n\n* [Yosys](https://github.com/yosysHQ/yosys)\n* [Odin II](https://verilogtorouting.org)\n* [Verilator](https://verilator.org)\n* [Icarus](http://iverilog.icarus.com)\n* [slang](https://github.com/MikePopoloski/slang)\n* [sv2v(zachjs)](https://github.com/zachjs/sv2v)\n* [tree-sitter-systemverilog](https://github.com/gmlarumbe/tree-sitter-systemverilog)\n* [tree-sitter-verilog](https://github.com/tree-sitter/tree-sitter-verilog)\n* [sv-parser](https://github.com/dalance/sv-parser)\n* [moore](http://llhd.io)\n* [verible](https://github.com/google/verible)\n* [circt-verilog](https://github.com/llvm/circt)\n* [yosys-slang](https://github.com/povik/yosys-slang)\n"
  },
  {
    "path": "conf/environment.yml",
    "content": "# Copyright (C) 2019-2021  The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\n\nname: sv-test-env\nchannels:\n  - LiteX-Hub\n#  - pkgw-forge\n#  - conda-forge\ndependencies:\n#  - LiteX-Hub::iverilog\n#  - LiteX-Hub::moore\n#  - LiteX-Hub::odin_ii\n#  - LiteX-Hub::slang\n#  - LiteX-Hub::surelog\n#  - LiteX-Hub::sv-parser\n#  - LiteX-Hub::tree-sitter-verilog\n#  - LiteX-Hub::yosys-uhdm\n#  - LiteX-Hub::verible\n#  - LiteX-Hub::verilator\n#  - gxx_impl_linux-64\n#  - LiteX-Hub::yosys\n#  - LiteX-Hub::antmicro-yosys-complete\n#  - LiteX-Hub::zachjs-sv2v\n  - ccache\n  - python=3.8\n  - pip\n  - pip:                            # Packages installed from PyPI\n    - -r requirements.txt\n"
  },
  {
    "path": "conf/feature-analyzer/keywords.yml",
    "content": "# Copyright (C) 2019-2021  The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\n\ntags:\n  5.6:\n    - 'accept_on'\n    - 'default'\n    - 'forkjoin'\n    - 'alias'\n    - 'defparam'\n    - 'function'\n    - 'always'\n    - 'design'\n    - 'generate'\n    - 'always_comb'\n    - 'disable'\n    - 'genvar'\n    - 'always_ff'\n    - 'dist'\n    - 'global'\n    - 'always_latch'\n    - 'do'\n    - 'highz0'\n    - 'and'\n    - 'edge'\n    - 'highz1'\n    - 'assert'\n    - 'else'\n    - 'if'\n    - 'assign'\n    - 'end'\n    - 'iff'\n    - 'assume'\n    - 'endcase'\n    - 'ifnone'\n    - 'automatic'\n    - 'endchecker'\n    - 'ignore_bins'\n    - 'before'\n    - 'endclass'\n    - 'illegal_bins'\n    - 'begin'\n    - 'endclocking'\n    - 'implements'\n    - 'bind'\n    - 'endconfig'\n    - 'implies'\n    - 'bins'\n    - 'endfunction'\n    - 'import'\n    - 'binsof'\n    - 'endgenerate'\n    - 'incdir'\n    - 'bit'\n    - 'endgroup'\n    - 'include'\n    - 'break'\n    - 'endinterface'\n    - 'initial'\n    - 'buf'\n    - 'endmodule'\n    - 'inout'\n    - 'bufif0'\n    - 'endpackage'\n    - 'input'\n    - 'bufif1'\n    - 'endprimitive'\n    - 'inside'\n    - 'byte'\n    - 'endprogram'\n    - 'instance'\n    - 'case'\n    - 'endproperty'\n    - 'int'\n    - 'casex'\n    - 'endspecify'\n    - 'integer'\n    - 'casez'\n    - 'endsequence'\n    - 'interconnect'\n    - 'cell'\n    - 'endtable'\n    - 'interface'\n    - 'chandle'\n    - 'endtask'\n    - 'intersect'\n    - 'checker'\n    - 'enum'\n    - 'join'\n    - 'class'\n    - 'event'\n    - 'join_any'\n    - 'clocking'\n    - 'eventually'\n    - 'join_none'\n    - 'cmos'\n    - 'expect'\n    - 'large'\n    - 'config'\n    - 'export'\n    - 'let'\n    - 'const'\n    - 'extends'\n    - 'liblist'\n    - 'constraint'\n    - 'extern'\n    - 'library'\n    - 'context'\n    - 'final'\n    - 'local'\n    - 'continue'\n    - 'first_match'\n    - 'localparam'\n    - 'cover'\n    - 'for'\n    - 'logic'\n    - 'covergroup'\n    - 'force'\n    - 'longint'\n    - 'coverpoint'\n    - 'foreach'\n    - 'macromodule'\n    - 'cross'\n    - 'forever'\n    - 'matches'\n    - 'deassign'\n    - 'fork'\n    - 'medium'\n    - 'modport'\n    - 'reject_on'\n    - 'time'\n    - 'module'\n    - 'release'\n    - 'timeprecision'\n    - 'nand'\n    - 'repeat'\n    - 'timeunit'\n    - 'negedge'\n    - 'restrict'\n    - 'tran'\n    - 'nettype'\n    - 'return'\n    - 'tranif0'\n    - 'new'\n    - 'rnmos'\n    - 'tranif1'\n    - 'nexttime'\n    - 'rpmos'\n    - 'tri'\n    - 'nmos'\n    - 'rtran'\n    - 'tri0'\n    - 'nor'\n    - 'rtranif0'\n    - 'tri1'\n    - 'noshowcancelled'\n    - 'rtranif1'\n    - 'triand'\n    - 'not'\n    - 's_always'\n    - 'trior'\n    - 'notif0'\n    - 's_eventually'\n    - 'trireg'\n    - 'notif1'\n    - 's_nexttime'\n    - 'type'\n    - 'null'\n    - 's_until'\n    - 'typedef'\n    - 'or'\n    - 's_until_with'\n    - 'union'\n    - 'output'\n    - 'scalared'\n    - 'unique'\n    - 'package'\n    - 'sequence'\n    - 'unique0'\n    - 'packed'\n    - 'shortint'\n    - 'unsigned'\n    - 'parameter'\n    - 'shortreal'\n    - 'until'\n    - 'pmos'\n    - 'showcancelled'\n    - 'until_with'\n    - 'posedge'\n    - 'signed'\n    - 'untyped'\n    - 'primitive'\n    - 'small'\n    - 'use'\n    - 'priority'\n    - 'soft'\n    - 'uwire'\n    - 'program'\n    - 'solve'\n    - 'var'\n    - 'property'\n    - 'specify'\n    - 'vectored'\n    - 'protected'\n    - 'specparam'\n    - 'virtual'\n    - 'pull0'\n    - 'static'\n    - 'void'\n    - 'pull1'\n    - 'string'\n    - 'wait'\n    - 'pulldown'\n    - 'strong'\n    - 'wait_order'\n    - 'pullup'\n    - 'strong0'\n    - 'wand'\n    - 'pulsestyle_ondetect'\n    - 'strong1'\n    - 'weak'\n    - 'pulsestyle_onevent'\n    - 'struct'\n    - 'weak0'\n    - 'pure'\n    - 'super'\n    - 'weak1'\n    - 'rand'\n    - 'supply0'\n    - 'while'\n    - 'randc'\n    - 'supply1'\n    - 'wildcard'\n    - 'randcase'\n    - 'sync_accept_on'\n    - 'wire'\n    - 'randsequence'\n    - 'sync_reject_on'\n    - 'with'\n    - 'rcmos'\n    - 'table'\n    - 'within'\n    - 'real'\n    - 'tagged'\n    - 'wor'\n    - 'realtime'\n    - 'task'\n    - 'xnor'\n    - 'ref'\n    - 'this'\n    - 'xor'\n    - 'reg'\n    - 'throughout'\n"
  },
  {
    "path": "conf/feature-analyzer/operators.yml",
    "content": "# Copyright (C) 2019-2021  The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\n\ntags:\n  5.5:\n    - '='\n    - '+='\n    - '-='\n    - '*='\n    - '/='\n    - '%='\n    - '&='\n    - '|='\n    - '^='\n    - '<<='\n    - '>>='\n    - '<<<='\n    - '>>>='\n    - '!'\n    - '~'\n    - '&'\n    - '~&'\n    - '|'\n    - '~|'\n    - '^'\n    - '~^'\n    - '^~'\n    - '+'\n    - '-'\n    - '*'\n    - '/'\n    - '%'\n    - '=='\n    - '!='\n    - '==='\n    - '!=='\n    - '==?'\n    - '!=?'\n    - '&&'\n    - '||'\n    - '**'\n    - '<'\n    - '<='\n    - '>'\n    - '>='\n    - '&'\n    - '>>>'\n    - '<<<'\n    - '->'\n    - '<->'\n    - '++'\n    - '--'\n    - '>>'\n    - '<<'\n  10.4:\n    - '='\n    - '+='\n    - '-='\n    - '*='\n    - '/='\n    - '%='\n    - '&='\n    - '|='\n    - '^='\n    - '<<='\n    - '>>='\n    - '<<<='\n    - '>>>='\n    - '<='\n  11.3:\n    - '='\n    - '+='\n    - '-='\n    - '*='\n    - '/='\n    - '%='\n    - '&='\n    - '|='\n    - '^='\n    - '<<='\n    - '>>='\n    - '<<<='\n    - '>>>='\n    - '?'\n    - '+'\n    - '-'\n    - '!'\n    - '~'\n    - '&'\n    - '~&'\n    - '|'\n    - '~|'\n    - '^'\n    - '~^'\n    - '^~'\n    - '*'\n    - '/'\n    - '%'\n    - '=='\n    - '!='\n    - '==='\n    - '!=='\n    - '==?'\n    - '!=?'\n    - '&&'\n    - '||'\n    - '**'\n    - '<'\n    - '<='\n    - '>'\n    - '>='\n    - '>>'\n    - '<<'\n    - '>>>'\n    - '<<<'\n    - '++'\n    - '--'\n    - '->'\n    - '<->'\n"
  },
  {
    "path": "conf/feature-analyzer/tags.yml",
    "content": "# Copyright (C) 2019-2021  The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\n\ntags:\n  5.4:\n    - '//'\n    - '/*'\n    - '*/'\n  5.6:\n    - '`__FILE__'\n    - '`__LINE__'\n    - '`begin_keywords'\n    - '`celldefine'\n    - '`default_nettype'\n    - '`define'\n    - '`else'\n    - '`elsif'\n    - '`end_keywords'\n    - '`endcelldefine'\n    - '`endif'\n    - '`ifdef'\n    - '`ifndef'\n    - '`include'\n    - '`line'\n    - '`nounconnected_drive'\n    - '`pragma'\n    - '`resetall'\n    - '`timescale'\n    - '`unconnected_drive'\n    - '`undef'\n    - '`undefineall'\n  6.3:\n    - 'small'\n    - 'medium'\n    - 'large'\n  6.6:\n    - 'wire'\n    - 'tri'\n    - 'uwire'\n    - 'wor'\n    - 'wand'\n    - 'trior'\n    - 'triand'\n    - 'trireg'\n    - 'tri0'\n    - 'tri1'\n    - 'supply0'\n    - 'supply1'\n    - 'nettype'\n    - 'interconnect'\n  6.9:\n    - 'reg'\n    - 'logic'\n    - 'bit'\n  6.11:\n    - 'logic'\n    - 'reg'\n    - 'integer'\n    - 'time'\n    - 'bit'\n    - 'int'\n    - 'byte'\n    - 'shortint'\n    - 'int'\n    - 'integer'\n    - 'longint'\n    - 'unsigned'\n    - 'signed'\n  6.12:\n    - 'real'\n    - 'shortreal'\n    - 'realtime'\n  6.13:\n    - 'void'\n  6.14:\n    - 'chandle'\n  6.15:\n    - 'class'\n  6.16:\n    - 'string'\n  6.17:\n    - 'event'\n  6.18:\n    - 'typedef'\n  6.19:\n    - 'enum'\n  6.20:\n    - 'localparam'\n    - 'parameter'\n    - 'specparam'\n    - 'const'\n  6.23:\n    - 'type'\n  6.24:\n    - '$cast'\n  7.2:\n    - 'struct'\n    - 'struct packed'\n  7.3:\n    - 'union'\n    - 'union packed'\n    - 'union tagged'\n    - 'union tagged packed'\n  7.5:\n    - '[]'\n  7.8:\n    - '[*]'\n  7.10:\n    - '[$]'\n    - 'pop_front'\n    - 'pop_back'\n    - 'push_front'\n    - 'pop_front'\n  7.11:\n    - '$left'\n    - '$right'\n    - '$low'\n    - '$high'\n    - '$increment'\n    - '$size'\n    - '$dimensions'\n    - '$unpacked_dimensions'\n  8.3:\n    - 'class'\n    - 'virtual class'\n  8.7:\n    - 'function new'\n  8.10:\n    - 'static function'\n  8.11:\n    - 'this.'\n  8.13:\n    - 'extends'\n  8.15:\n    - 'super.'\n  8.16:\n    - '$cast'\n  8.20:\n    - 'virtual function'\n  8.21:\n    - 'virtual class'\n    - 'pure virtual function'\n  8.23:\n    - '::'\n  8.26:\n    - 'interface class'\n  9.2:\n    - 'initial'\n    - 'always'\n    - 'always_comb'\n    - 'always_latch'\n    - 'always_ff'\n    - 'final'\n  9.3:\n    - 'begin'\n    - 'end'\n    - 'fork'\n    - 'join'\n    - 'join_any'\n    - 'join_none'\n  9.4:\n    - 'repeat'\n    - 'wait'\n    - 'wait fork'\n    - 'wait_order'\n  9.6:\n    - 'wait'\n    - 'wait fork'\n    - 'wait_order'\n    - 'disable'\n    - 'disable fork'\n  9.7:\n    - 'kill'\n    - 'await'\n    - 'suspend'\n    - 'resume'\n  10.3:\n    - 'assign'\n    - 'supply1'\n    - 'strong1'\n    - 'pull1'\n    - 'weak1'\n    - 'highz1'\n    - 'supply0'\n    - 'strong0'\n    - 'pull0'\n    - 'weak0'\n    - 'highz0'\n  10.6:\n    - 'assign'\n    - 'deassign'\n    - 'force'\n    - 'release'\n  10.11:\n    - 'alias'\n  11.9:\n    - 'tagged'\n  11.12:\n    - 'let'\n  12.4:\n    - 'if'\n    - 'else if'\n    - 'else'\n    - 'unique'\n    - 'unique0'\n    - 'priority'\n    - 'matches'\n  12.5:\n    - 'case'\n    - 'casez'\n    - 'casex'\n    - 'endcase'\n    - 'matches'\n    - 'inside'\n    - 'default'\n  12.6:\n    - 'matches'\n    - 'tagged'\n  12.7:\n    - 'forever'\n    - 'repeat'\n    - 'while'\n    - 'for'\n    - 'do'\n    - 'while'\n    - 'foreach'\n  12.8:\n    - 'break'\n    - 'continue'\n    - 'return'\n  13.3:\n    - 'task'\n    - 'endtask'\n  13.4:\n    - 'function'\n    - 'endfunction'\n  14.3:\n    - 'clocking'\n    - 'endclocking'\n  14.11:\n    - '##'\n  14.12:\n    - 'default clocking'\n  14.14:\n    - 'global clocking'\n  15.3:\n    - 'semaphore'\n  15.4:\n    - 'mailbox'\n  15.5:\n    - 'event'\n    - 'wait_order'\n  16.2:\n    - 'assert'\n    - 'assume'\n    - 'cover'\n    - 'restrict'\n  16.4:\n    - 'assert #0'\n    - 'assert final'\n    - 'assume #0'\n    - 'assume final'\n    - 'cover #0'\n    - 'cover final'\n  16.8:\n    - 'sequence'\n    - 'endsequence'\n  16.9:\n    - '$sampled'\n    - '$rose'\n    - '$fell'\n    - '$stable'\n    - '$changed'\n    - '$past'\n    - '$past_gclk'\n    - '$rose_gclk'\n    - '$fell_gclk'\n    - '$stable_gclk'\n    - '$changed_gclk'\n    - '$future_gclk'\n    - '$rising_gclk'\n    - '$falling_gclk'\n    - '$steady_gclk'\n    - '$changing_gclk'\n    - 'intersect'\n    - 'first_match'\n    - 'throughout'\n    - 'within'\n  16.12:\n    - 'property'\n    - 'endproperty'\n    - 'nexttime'\n    - 's_nexttime'\n    - 'iff'\n    - 'until'\n    - 's_until'\n    - 'until_with'\n    - 's_until_with'\n    - 'implies'\n    - 's_always'\n    - 'eventually'\n    - 's_eventually'\n    - 'accept_on'\n    - 'reject_on'\n    - 'sync_accept_on'\n    - 'sync_reject_on'\n    - '#-#'\n    - '#=#'\n  16.17:\n    - 'expect'\n  17.2:\n    - 'checker'\n    - 'endchecker'\n  17.6:\n    - 'covergroup'\n    - 'coverpoint'\n    - 'endgroup'\n  20.2:\n    - '$finish'\n    - '$stop'\n    - '$exit'\n  20.3:\n    - '$realtime'\n    - '$stime'\n    - '$time'\n  20.4:\n    - '$printtimescale'\n    - '$timeformat'\n  20.5:\n    - '$bitstoreal'\n    - '$realtobits'\n    - '$bitstoshortreal'\n    - '$shortrealtobits'\n    - '$itor'\n    - '$rtoi'\n    - '$signed'\n    - '$unsigned'\n    - '$cast'\n  20.6:\n    - '$bits'\n    - '$isunbounded'\n    - '$typename'\n  20.7:\n    - '$unpacked_dimensions'\n    - '$dimensions'\n    - '$left'\n    - '$right'\n    - '$low'\n    - '$high'\n    - '$increment'\n    - '$size'\n  20.8:\n    - '$clog2'\n    - '$asin'\n    - '$ln'\n    - '$acos'\n    - '$log10'\n    - '$atan'\n    - '$exp'\n    - '$atan2'\n    - '$sqrt'\n    - '$hypot'\n    - '$pow'\n    - '$sinh'\n    - '$floor'\n    - '$cosh'\n    - '$ceil'\n    - '$tanh'\n    - '$sin'\n    - '$asinh'\n    - '$cos'\n    - '$acosh'\n    - '$tan'\n    - '$atanh'\n  20.9:\n    - '$countbits'\n    - '$countones'\n    - '$onehot'\n    - '$onehot0'\n    - '$isunknown'\n  20.10:\n    - '$fatal'\n    - '$error'\n    - '$warning'\n    - '$info'\n  20.11:\n    - '$fatal'\n    - '$error'\n    - '$warning'\n    - '$info'\n  20.12:\n    - '$asserton'\n    - '$assertoff'\n    - '$assertkill'\n    - '$assertcontrol'\n    - '$assertpasson'\n    - '$assertpassoff'\n    - '$assertfailon'\n    - '$assertfailoff'\n    - '$assertnonvacuouson'\n    - '$assertvacuousoff'\n  20.13:\n    - '$sampled'\n    - '$rose'\n    - '$fell'\n    - '$stable'\n    - '$changed'\n    - '$past'\n    - '$past_gclk'\n    - '$rose_gclk'\n    - '$fell_gclk'\n    - '$stable_gclk'\n    - '$changed_gclk'\n    - '$future_gclk'\n    - '$rising_gclk'\n    - '$falling_gclk'\n    - '$steady_gclk'\n    - '$changing_gclk'\n  20.14:\n    - '$coverage_control'\n    - '$coverage_get_max'\n    - '$coverage_get'\n    - '$coverage_merge'\n    - '$coverage_save'\n    - '$get_coverage'\n    - '$set_coverage_db_name'\n    - '$load_coverage_db'\n  20.15:\n    - '$random'\n    - '$dist_chi_square'\n    - '$dist_erlang'\n    - '$dist_exponential'\n    - '$dist_normal'\n    - '$dist_poisson'\n    - '$dist_t'\n    - '$dist_uniform'\n  20.16:\n    - '$q_initialize'\n    - '$q_add'\n    - '$q_remove'\n    - '$q_full'\n    - '$q_exam'\n  20.17:\n    - '$async$and$array'\n    - '$async$and$plane'\n    - '$async$nand$array'\n    - '$async$nand$plane'\n    - '$async$or$array'\n    - '$async$or$plane'\n    - '$async$nor$array'\n    - '$async$nor$plane'\n    - '$sync$and$array'\n    - '$sync$and$plane'\n    - '$sync$nand$array'\n    - '$sync$nand$plane'\n    - '$sync$or$array'\n    - '$sync$or$plane'\n    - '$sync$nor$array'\n    - '$sync$nor$plane'\n  20.18:\n    - '$system'\n  21.2:\n    - '$display'\n    - '$displayb'\n    - '$displayh'\n    - '$displayo'\n    - '$strobe'\n    - '$strobeb'\n    - '$strobeh'\n    - '$strobeo'\n    - '$write'\n    - '$writeb'\n    - '$writeh'\n    - '$writeo'\n    - '$monitor'\n    - '$monitorb'\n    - '$monitorh'\n    - '$monitoro'\n    - '$monitoroff'\n    - '$monitoron'\n  21.3:\n    - '$fclose'\n    - '$fdisplay'\n    - '$fdisplayb'\n    - '$fdisplayh'\n    - '$fdisplayo'\n    - '$fstrobe'\n    - '$fstrobeb'\n    - '$fstrobeh'\n    - '$fstrobeo'\n    - '$swrite'\n    - '$swriteb'\n    - '$swriteh'\n    - '$swriteo'\n    - '$fscanf'\n    - '$fread'\n    - '$fseek'\n    - '$fflush'\n    - '$feof'\n    - '$fopen'\n    - '$fwrite'\n    - '$fwriteb'\n    - '$fwriteh'\n    - '$fwriteo'\n    - '$fmonitor'\n    - '$fmonitorb'\n    - '$fmonitorh'\n    - '$fmonitoro'\n    - '$sformat'\n    - '$sformatf'\n    - '$fgetc'\n    - '$ungetc'\n    - '$fgets'\n    - '$sscanf'\n    - '$rewind'\n    - '$ftell'\n    - '$ferror'\n  21.4:\n    - '$readmemb'\n    - '$readmemh'\n  21.5:\n    - '$writememb'\n    - '$writememh'\n  21.6:\n    - '$test$plusargs'\n    - '$value$plusargs'\n  21.7:\n    - '$dumpfile'\n    - 'idumpoff'\n    - '$dumpall'\n    - '$dumpflush'\n    - '$dumpportsoff'\n    - '$dumpportsall'\n    - '$dumpportsflush'\n    - '$dumpvars'\n    - '$dumpon'\n    - '$dumplimit'\n    - '$dumpports'\n    - '$dumpportson'\n    - '$dumpportslimit'\n  22.3:\n    - '`resetall'\n  22.4:\n    - '`include'\n  22.5:\n    - '`define'\n    - '`undef'\n    - '`undefineall'\n  22.6:\n    - '`else'\n    - '`elsif'\n    - '`endif'\n    - '`ifdef'\n    - '`ifndef'\n  22.7:\n    - '`timescale'\n  22.8:\n    - '`default_nettype'\n  22.9:\n    - '`unconnected_drive'\n    - '`nounconnected_drive'\n  22.10:\n    - '`celldefine'\n    - '`endcelldefine'\n  22.11:\n    - '`pragma'\n  22.12:\n    - '`line'\n  22.13:\n    - '`__FILE__'\n    - '`__LINE__'\n  22.14:\n    - '`begin_keywords'\n    - '`end_keywords'\n  23.2:\n    - 'module'\n    - 'macromodule'\n    - 'endmodule'\n  23.5:\n    - 'extern module'\n  24.3:\n    - 'program'\n    - 'endprogram'\n  25.3:\n    - 'interface'\n    - 'endinterface'\n  26.2:\n    - 'package'\n    - 'endpackage'\n  26.3:\n    - 'import'\n"
  },
  {
    "path": "conf/fusesoc-configs/ibex-sim.yml",
    "content": "# Copyright (C) 2019-2021  The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\n\nname: ibex\ndescription: Full ibex core test\ntop_module: ibex_simple_system\ntags: ibex\npath: third_party/cores/ibex\ncommand: fusesoc --cores-root third_party/cores/ibex run --target=sim --setup lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast\nconf_file: build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/lowrisc_ibex_ibex_simple_system_0.vc\ntest_file: ibex-sim.sv\ntimeout: 100\ncompatible-runners: verilator slang circt-verilog\ntype: parsing elaboration simulation_without_run\n"
  },
  {
    "path": "conf/fusesoc-configs/veer-eh1-sim.yml",
    "content": "# Copyright (C) 2019-2021  The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\n\nname: veer-eh1\ndescription: Full VeeR EH1 core test\ntop_module: tb_top\ntags: veer-eh1\npath: third_party/cores/veer-eh1\ncommand: fusesoc --cores-root third_party/cores/veer-eh1 run --target=sim --setup --build-root build/veer-eh1_sim chipsalliance.org:cores:VeeR_EH1:1.8\nconf_file: build/veer-eh1_sim/sim-verilator/chipsalliance.org_cores_VeeR_EH1_1.8.vc\ntest_file: veer-eh1-sim.sv\ntimeout: 180\ncompatible-runners: verilator slang circt-verilog\ntype: parsing elaboration simulation_without_run\n"
  },
  {
    "path": "conf/fusesoc-configs/veer-eh1-synth.yml",
    "content": "# Copyright (C) 2019-2021  The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\n\nname: veer-eh1\ndescription: Full VeeR EH1 core test\ntop_module: veer-eh1_wrapper\ntags: veer-eh1\npath: third_party/cores/veer-eh1\ncommand: fusesoc --cores-root third_party/cores/veer-eh1 run --target=synth --setup --build-root build/veer-eh1_synth chipsalliance.org:cores:VeeR_EH1:1.8\nconf_file: build/veer-eh1_synth/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.8.tcl\ntest_file: veer-eh1-synth.sv\ntimeout: 180\ncompatible-runners: yosys-synlig yosys yosys-sv zachjs-sv2v icarus moore moore-parse odin sv-parser tree-sitter-verilog verible verible_extractor Surelog slang-parse circt-verilog\ntype: parsing elaboration\n"
  },
  {
    "path": "conf/generators/meta-path/basejump.json",
    "content": "{\n\t\"name\": \"BaseJumpSTL\",\n\t\"project\": \"basejump\",\n\t\"paths\": [\n\t\t[\n\t\t\t\"cores\",\n\t\t\t\"basejump_stl\",\n\t\t\t\"*\"\n\t\t]\n\t],\n\t\"matches\": [\n\t\t\"*.sv\"\n\t],\n\t\"commons\": [\n\t\t\"cores/basejump_stl/bsg_misc/bsg_defines.sv\",\n\t\t\"cores/basejump_stl/bsg_cache/bsg_cache_pkg.sv\",\n\t\t\"cores/basejump_stl/bsg_cache/bsg_cache_non_blocking_pkg.sv\",\n\t\t\"cores/basejump_stl/bsg_dmc/bsg_dmc_pkg.sv\",\n\t\t\"cores/basejump_stl/bsg_noc/bsg_noc_pkg.sv\",\n\t\t\"cores/basejump_stl/bsg_noc/bsg_mesh_router_pkg.sv\",\n\t\t\"cores/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.sv\",\n\t\t\"cores/basejump_stl/bsg_tag/bsg_tag_pkg.sv\",\n\t\t\"cores/basejump_stl/bsg_test/bsg_dramsim3_pkg.sv\",\n\t\t\"cores/basejump_stl/bsg_axi/bsg_axi_pkg.sv\"\n\t],\n\t\"incdirs\": [\n\t\t\"cores/basejump_stl/bsg_misc\",\n\t\t\"cores/basejump_stl/bsg_noc\",\n\t\t\"cores/basejump_stl/bsg_clk_gen\"\n\t],\n\t\"timeouts\": {\n\t\t\"bsg_scatter_gather.sv\": \"60\",\n\t\t\"bsg_launch_sync_sync.sv\": \"60\",\n\t\t\"bsg_cache.sv\": \"30\",\n\t\t\"bsg_cache_non_blocking_mhu.sv\": \"30\",\n\t\t\"bsg_tag_master.sv\": \"30\",\n\t\t\"bsg_round_robin_fifo_to_fifo.sv\": \"30\"\n\t},\n\t\"blacklist\": [\n\t\t\"bsg_1_to_n_tagged_fifo_shared.sv\",\n\t\t\"bsg_cache_BaseJumpSTL_bsg_cache_to_axi.sv\",\n\t\t\"bsg_cache_BaseJumpSTL_bsg_cache_to_axi_rx.sv\",\n\t\t\"bsg_cache_BaseJumpSTL_bsg_cache_to_axi_tx.sv\",\n\t\t\"bsg_cache_non_blocking_pkg.sv\",\n\t\t\"bsg_cache_pkg.sv\",\n\t\t\"bsg_cache_to_dram_ctrl.sv\",\n\t\t\"bsg_dmc_pkg.sv\",\n\t\t\"bsg_dramsim3_pkg.sv\",\n\t\t\"bsg_mem_banked_crossbar.sv\",\n\t\t\"bsg_mem_multiport.sv\",\n\t\t\"bsg_mem_multiport_latch_write_banked_bypassing.sv\",\n\t\t\"bsg_mem_multiport_latch_write_banked_bypassing_sync.sv\",\n\t\t\"bsg_mesh_router_pkg.sv\",\n\t\t\"bsg_nonsynth_mixin_motherboard.sv\",\n\t\t\"bsg_pg_tree.sv\",\n\t\t\"bsg_sbox_ctrl.sv\",\n\t\t\"bsg_sbox_ctrl_concentrate.sv\",\n\t\t\"bsg_sparse_to_dense_boolean.sv\",\n\t\t\"bsg_tag_pkg.sv\",\n\t\t\"bsg_test_BaseJumpSTL_bsg_nonsynth_axi_mem.sv\",\n\t\t\"bsg_wormhole_router_pkg.sv\",\n\t\t\"test_bsg_clock_params.sv\",\n\t\t\"bsg_dmc_xilinx_ui_trace_replay.sv\",\n\t\t\"bsg_nonsynth_profiler.sv\"\n\t],\n\t\"fake_topmodule\": true,\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/hdlconvertor.json",
    "content": "{\n\t\"name\": \"hdlconvertor\",\n\t\"project\": \"hdlconv\",\n\t\"paths\": [\n\t\t[\"tests\", \"hdlconvertor\", \"tests\", \"sv_test\", \"others\"],\n\t\t[\"tests\", \"hdlconvertor\", \"tests\", \"verilog\", \"*\"]\n\t],\n\t\"matches\": [\"*.sv\", \"*.v\"],\n\t\"blacklist\": [\n\t\t\"aFifo.v\",\n\t\t\"adder_implicit.v\",\n\t\t\"aes.v\",\n\t\t\"directive_verilogpp.v\",\n\t\t\"fifo_rx.sv\",\n\t\t\"hierarchical_name_of_type.sv\",\n\t\t\"lfsr_updown_tb.v\",\n\t\t\"parity_using_function2.v\",\n\t\t\"stm_import.sv\"\n\t],\n\t\"type\": \"parsing\",\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/hdlconvertor_std2012.json",
    "content": "{\n\t\"name\": \"hdlconvertor_std2012\",\n\t\"project\": \"hdlconv_std2012\",\n\t\"paths\": [\n\t\t[\"tests\", \"hdlconvertor\", \"tests\", \"sv_test\", \"std2012\"]\n\t],\n\t\"matches\": [\"*.sv\", \"*.v\"],\n\t\"blacklist\": [\n\t\t\"p12.sv\",\n\t\t\"p59.sv\",\n\t\t\"p138.sv\",\n\t\t\"p140.sv\",\n\t\t\"p160_2.sv\",\n\t\t\"p76.sv\",\n\t\t\"p77.sv\",\n\t\t\"p87.sv\"\n\t],\n\t\"type\": \"parsing\",\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/hdlconvertor_std2017.json",
    "content": "{\n\t\"name\": \"hdlconvertor_std2017\",\n\t\"project\": \"hdlconv_std2017\",\n\t\"paths\": [\n\t\t[\"tests\", \"hdlconvertor\", \"tests\", \"sv_test\", \"std2017\"]\n\t],\n\t\"matches\": [\"*.sv\", \"*.v\"],\n\t\"blacklist\": [\n\t\t\"p95.sv\",\n\t\t\"p137.sv\",\n\t\t\"p141.sv\",\n\t\t\"p142.sv\",\n\t\t\"p172.sv\",\n\t\t\"p174_2.sv\",\n\t\t\"p176.sv\",\n\t\t\"p180.sv\",\n\t\t\"p180_2.sv\",\n\t\t\"p188_3.sv\",\n\t\t\"p191.sv\",\n\t\t\"p196_2.sv\",\n\t\t\"p197.sv\",\n\t\t\"p201.sv\",\n\t\t\"p220.sv\",\n\t\t\"p221.sv\",\n\t\t\"p229.sv\",\n\t\t\"p229_2.sv\",\n\t\t\"p253.sv\",\n\t\t\"p294.sv\",\n\t\t\"p295.sv\",\n\t\t\"p296.sv\",\n\t\t\"p297.sv\",\n\t\t\"p333.sv\",\n\t\t\"p335.sv\",\n\t\t\"p338.sv\",\n\t\t\"p339.sv\",\n\t\t\"p340.sv\",\n\t\t\"p341.sv\",\n\t\t\"p342.sv\",\n\t\t\"p346.sv\",\n\t\t\"p352.sv\",\n\t\t\"p477.sv\",\n\t\t\"p478.sv\",\n\t\t\"p499.sv\",\n\t\t\"p504.sv\",\n\t\t\"p504_2.sv\",\n\t\t\"p507.sv\",\n\t\t\"p510.sv\",\n\t\t\"p522.sv\",\n\t\t\"p524.sv\",\n\t\t\"p532.sv\",\n\t\t\"p535.sv\",\n\t\t\"p550.sv\",\n\t\t\"p552.sv\",\n\t\t\"p557.sv\",\n\t\t\"p558.sv\",\n\t\t\"p560.sv\",\n\t\t\"p565.sv\",\n\t\t\"p566.sv\",\n\t\t\"p568.sv\",\n\t\t\"p573.sv\",\n\t\t\"p576.sv\",\n\t\t\"p578.sv\",\n\t\t\"p580.sv\",\n\t\t\"p581.sv\",\n\t\t\"p584.sv\",\n\t\t\"p594.sv\",\n\t\t\"p621.sv\",\n\t\t\"p622.sv\",\n\t\t\"p700.sv\",\n\t\t\"p701.sv\",\n\t\t\"p702.sv\",\n\t\t\"p704.sv\",\n\t\t\"p706.sv\",\n\t\t\"p710.sv\",\n\t\t\"p711.sv\",\n\t\t\"p713.sv\",\n\t\t\"p714.sv\",\n\t\t\"p716.sv\",\n\t\t\"p720.sv\",\n\t\t\"p721.sv\",\n\t\t\"p724.sv\",\n\t\t\"p726.sv\",\n\t\t\"p731.sv\",\n\t\t\"p732.sv\",\n\t\t\"p734.sv\",\n\t\t\"p735.sv\",\n\t\t\"p736.sv\",\n\t\t\"p753.sv\",\n\t\t\"p755.sv\",\n\t\t\"p764.sv\",\n\t\t\"p772.sv\",\n\t\t\"p773.sv\",\n\t\t\"p777.sv\",\n\t\t\"p782.sv\",\n\t\t\"p793.sv\",\n\t\t\"p794.sv\",\n\t\t\"p795.sv\",\n\t\t\"p802.sv\",\n\t\t\"p825.sv\",\n\t\t\"p832.sv\",\n\t\t\"p833.sv\",\n\t\t\"p834.sv\",\n\t\t\"p836.sv\",\n\t\t\"p837.sv\",\n\t\t\"p886.sv\",\n\t\t\"p940.sv\"\n\t],\n\t\"type\": \"parsing\",\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/projf-explore.json",
    "content": "{\n\t\"name\": \"projf\",\n\t\"project\": \"projf-explore\",\n\t\"paths\": [\n\t\t[\"tests\", \"projf-explore\", \"*\", \"*\", \"*\"]\n\t],\n\t\"matches\": [\"*.sv\"],\n\t\"type\": \"parsing\",\n\t\"blacklist\": [\n\t    \"MMCME2_BASE.sv\",\n\t    \"OBUFDS.sv\",\n\t    \"OSERDESE2.sv\",\n\t    \"SB_IO.sv\",\n\t    \"SB_PLL40_PAD.sv\",\n\t    \"clock_1080p.sv\",\n\t    \"clock_480p.sv\",\n\t    \"clock_720p.sv\",\n\t    \"clock_gen_1080p.sv\",\n\t    \"clock_gen_480p.sv\",\n\t    \"clock_gen_480p_tb.sv\",\n\t    \"clock_gen_720p.sv\",\n\t    \"clock_gen_sys.sv\",\n\t    \"clock_sys.sv\",\n\t    \"clock_tb.sv\",\n\t    \"clut_simple_tb.sv\",\n\t    \"display_480p_tb.sv\",\n\t    \"display_720p_tb.sv\",\n\t    \"div_int_tb.sv\",\n\t    \"div_tb.sv\",\n\t    \"draw_char_tb.sv\",\n\t    \"draw_circle_tb.sv\",\n\t    \"draw_line_1d_tb.sv\",\n\t    \"draw_line_tb.sv\",\n\t    \"draw_rectangle_fill_tb.sv\",\n\t    \"draw_rectangle_tb.sv\",\n\t    \"draw_triangle_fill_tb.sv\",\n\t    \"draw_triangle_tb.sv\",\n\t    \"dvi_generator.sv\",\n\t    \"get_glyph_line_tb.sv\",\n\t    \"lfsr_tb.sv\",\n\t    \"life_tb.sv\",\n\t    \"linebuffer_simple_tb.sv\",\n\t    \"oserdes_10b.sv\",\n\t    \"render_circles.sv\",\n\t    \"render_circles_fill.sv\",\n\t    \"render_cube.sv\",\n\t    \"render_cube_fill.sv\",\n\t    \"render_cube_shatter.sv\",\n\t    \"render_edge.sv\",\n\t    \"render_line.sv\",\n\t    \"render_rects.sv\",\n\t    \"render_rects_fill.sv\",\n\t    \"render_square_colr.sv\",\n\t    \"render_teleport.sv\",\n\t    \"render_triangles.sv\",\n\t    \"render_triangles_fill.sv\",\n\t    \"simple_480p_tb.sv\",\n\t    \"simple_720p_tb.sv\",\n\t    \"sine_table_tb.sv\",\n\t    \"spram.sv\",\n\t    \"spram_nibble.sv\",\n\t    \"sprite_inline_tb.sv\",\n\t    \"sprite_rom_tb.sv\",\n\t    \"sprite_tb.sv\",\n\t    \"sqrt_int_tb.sv\",\n\t    \"sqrt_tb.sv\",\n\t    \"starfield_tb.sv\",\n\t    \"tmds_out.sv\",\n\t    \"top.sv\",\n\t    \"top_bounce.sv\",\n\t    \"top_castle.sv\",\n\t    \"top_colour.sv\",\n\t    \"top_colour_cycle.sv\",\n\t    \"top_david_16colr.sv\",\n\t    \"top_david_fizzle.sv\",\n\t    \"top_david_mono.sv\",\n\t    \"top_david_scale.sv\",\n\t    \"top_demo.sv\",\n\t    \"top_demo_sb.sv\",\n\t    \"top_flag_ethiopia.sv\",\n\t    \"top_flag_sweden.sv\",\n\t    \"top_graphing.sv\",\n\t    \"top_greet.sv\",\n\t    \"top_greet_v1.sv\",\n\t    \"top_hedgehog.sv\",\n\t    \"top_hello.sv\",\n\t    \"top_hello_en.sv\",\n\t    \"top_hello_jp.sv\",\n\t    \"top_hitomezashi.sv\",\n\t    \"top_hourglass.sv\",\n\t    \"top_mandel.sv\",\n\t    \"top_lfsr.sv\",\n\t    \"top_life.sv\",\n\t    \"top_pong.sv\",\n\t    \"top_rasterbars.sv\",\n\t    \"top_sinescroll.sv\",\n\t    \"top_space_f.sv\",\n\t    \"top_square.sv\",\n\t    \"top_starfields.sv\",\n\t    \"top_tinyf_inline.sv\",\n\t    \"top_tinyf_move.sv\",\n\t    \"top_tinyf_rom.sv\",\n\t    \"top_tinyf_scale.sv\",\n\t    \"top_uart.sv\",\n\t    \"xd_tb.sv\"\n\t],\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/utd-systemverilog.json",
    "content": "{\n\t\"name\": \"utd-sv\",\n\t\"project\": \"utd-sv\",\n\t\"paths\": [\n\t\t[\"tests\", \"utd-sv\"]\n\t],\n\t\"matches\": [\"*.v\"],\n\t\"type\": \"parsing\",\n\t\"results_group\": \"imported\",\n\t\"blacklist\": [\n\t    \"bw_dtl_impctl_pulldown.v\",\n\t    \"bw_dtl_impctl_pullup.v\",\n\t    \"bw_r_l2d.v\",\n\t    \"bw_zzctu_sync.v\",\n\t    \"c2i_buf.v\",\n\t    \"c2i_sdp.v\",\n\t    \"casez.v\",\n\t    \"ccx.v\",\n\t    \"ccx_arb_atomq.v\",\n\t    \"ccx_arb_srcq.v\",\n\t    \"ccx_arbc.v\",\n\t    \"chip8_config.v\",\n\t    \"cluster_header_dup.v\",\n\t    \"core1_config.v\",\n\t    \"cpx.v\",\n\t    \"cpx_buf_pt.v\",\n\t    \"cpx_buf_top.v\",\n\t    \"cpx_datacx2_ff.v\",\n\t    \"cpx_dp0.v\",\n\t    \"cpx_dp2.v\",\n\t    \"cpx_dp4.v\",\n\t    \"cpx_dp6.v\",\n\t    \"cpx_dp_array.v\",\n\t    \"cpx_dp_halfarray.v\",\n\t    \"cpx_io_grant_ff.v\",\n\t    \"ctu_bottom_rptr.v\",\n\t    \"ctu_bottom_rptr2.v\",\n\t    \"ctu_clsp_clkgn_clksel.v\",\n\t    \"ctu_clsp_clkgn_clksw.v\",\n\t    \"ctu_clsp_clkgn_ssiclk.v\",\n\t    \"ctu_clsp_cmpgif.v\",\n\t    \"ctu_clsp_jbusgif.v\",\n\t    \"ctu_clsp_synch_cljl.v\",\n\t    \"ctu_clsp_synch_dldg.v\",\n\t    \"ctu_clsp_synch_jldl.v\",\n\t    \"ctu_sync_header.v\",\n\t    \"ctu_top_rptr.v\",\n\t    \"ctu_top_rptr2.v\",\n\t    \"dbginit_mon.v\",\n\t    \"dbl_buf.v\",\n\t    \"efc_lib.v\",\n\t    \"expression_tostring.v\",\n\t    \"ff_dram_sc_bank0.v\",\n\t    \"ff_dram_sc_bank1.v\",\n\t    \"ff_dram_sc_bank2.v\",\n\t    \"ff_dram_sc_bank3.v\",\n\t    \"ff_jbi_sc0_1.v\",\n\t    \"ff_jbi_sc0_2.v\",\n\t    \"ff_jbi_sc1_1.v\",\n\t    \"ff_jbi_sc1_2.v\",\n\t    \"ff_jbi_sc2_1.v\",\n\t    \"ff_jbi_sc2_2.v\",\n\t    \"ff_jbi_sc3_1.v\",\n\t    \"ff_jbi_sc3_2.v\",\n\t    \"flop_rptrs_xa0.v\",\n\t    \"flop_rptrs_xa1.v\",\n\t    \"flop_rptrs_xb0.v\",\n\t    \"flop_rptrs_xb1.v\",\n\t    \"flop_rptrs_xb2.v\",\n\t    \"flop_rptrs_xb3.v\",\n\t    \"flop_rptrs_xc0.v\",\n\t    \"flop_rptrs_xc1.v\",\n\t    \"flop_rptrs_xc2.v\",\n\t    \"flop_rptrs_xc3.v\",\n\t    \"flop_rptrs_xc4.v\",\n\t    \"flop_rptrs_xc5.v\",\n\t    \"flop_rptrs_xc6.v\",\n\t    \"flop_rptrs_xc7.v\",\n\t    \"forever-disable.v\",\n\t    \"fpu.v\",\n\t    \"fpu_add_ctl.v\",\n\t    \"fpu_add_exp_dp.v\",\n\t    \"fpu_div.v\",\n\t    \"fpu_div_exp_dp.v\",\n\t    \"fpu_in_ctl.v\",\n\t    \"fpu_in_dp.v\",\n\t    \"fpu_mul_ctl.v\",\n\t    \"fpu_mul_exp_dp.v\",\n\t    \"fpu_out.v\",\n\t    \"fpu_out_ctl.v\",\n\t    \"fpu_out_dp.v\",\n\t    \"fpu_rptr_groups.v\",\n\t    \"generate.v\",\n\t    \"i2c_fctrl.v\",\n\t    \"i2c_fdp.v\",\n\t    \"ifdef-2.v\",\n\t    \"ifdef-2.v\",\n\t    \"io_cpx_reqdata_ff.v\",\n\t    \"lsu_dcdp.v\",\n\t    \"lsu_pcx_qmon.v\",\n\t    \"lsu_qdp1.v\",\n\t    \"lsu_qdp2.v\",\n\t    \"lsu_rrobin_picker2.v\",\n\t    \"lsu_stb_ctldp.v\",\n\t    \"lsu_stb_rwdp.v\",\n\t    \"lsu_tagdp.v\",\n\t    \"lsu_tlbdp.v\",\n\t    \"module-instance.v\",\n\t    \"operators.v\",\n\t    \"pad_ddr0.v\",\n\t    \"pad_ddr1.v\",\n\t    \"pad_ddr2.v\",\n\t    \"pad_ddr3.v\",\n\t    \"pad_jbusf.v\",\n\t    \"pad_jbusl.v\",\n\t    \"pad_jbusr.v\",\n\t    \"pcx.v\",\n\t    \"pcx_buf_pt.v\",\n\t    \"pcx_buf_pt1.v\",\n\t    \"pcx_buf_top.v\",\n\t    \"pcx_data_px2.v\",\n\t    \"pcx_dp0.v\",\n\t    \"pcx_dp1.v\",\n\t    \"pcx_dp2.v\",\n\t    \"pcx_dp3.v\",\n\t    \"pcx_dp4.v\",\n\t    \"pcx_dp_array.v\",\n\t    \"pcx_dp_array02.v\",\n\t    \"pcx_dp_array134.v\",\n\t    \"sc_0_1_dbg_rptr.v\",\n\t    \"sc_2_3_dbg_rptr.v\",\n\t    \"scbuf.v\",\n\t    \"scbuf_evict.v\",\n\t    \"scbuf_fbd.v\",\n\t    \"scbuf_rdmard.v\",\n\t    \"scdata_ctr_io.v\",\n\t    \"scdata_periph_io.v\",\n\t    \"scdata_subbank.v\",\n\t    \"sctag_arbaddrdp.v\",\n\t    \"sctag_dbgdp.v\",\n\t    \"sctag_deccdp.v\",\n\t    \"sctag_dir_ctl.v\",\n\t    \"sctag_dir_in.v\",\n\t    \"sctag_dir_out.v\",\n\t    \"sctag_dirrep.v\",\n\t    \"sctag_dirvec_dp.v\",\n\t    \"sctag_oqdp.v\",\n\t    \"sctag_retdp.v\",\n\t    \"sctag_scbufrep.v\",\n\t    \"sctag_snpctl.v\",\n\t    \"sctag_snpdp.v\",\n\t    \"sctag_tagdp.v\",\n\t    \"sctag_tagl_dp.v\",\n\t    \"sctag_ua_dp.v\",\n\t    \"sctag_vd_dp.v\",\n\t    \"sctag_vuad_ctl.v\",\n\t    \"sctag_vuad_dpm.v\",\n\t    \"sctag_vuad_io.v\",\n\t    \"sctag_vuadcol_dp.v\",\n\t    \"sctag_vuaddp_ctl.v\",\n\t    \"sctag_wbctl.v\",\n\t    \"sparc_exu_aluaddsub.v\",\n\t    \"sparc_exu_alulogic.v\",\n\t    \"sparc_exu_byp_eccgen.v\",\n\t    \"sparc_exu_ecc.v\",\n\t    \"sparc_exu_ecl_cnt6.v\",\n\t    \"sparc_exu_ecl_divcntl.v\",\n\t    \"sparc_exu_shft.v\",\n\t    \"sparc_ffu_ctl_visctl.v\",\n\t    \"sparc_ffu_vis.v\",\n\t    \"sparc_ifu_sscan.v\",\n\t    \"sparc_ifu_thrcmpl.v\",\n\t    \"spu_lsurpt1.v\",\n\t    \"spu_maexp.v\",\n\t    \"spu_mald.v\",\n\t    \"spu_mast.v\",\n\t    \"std-3.11.1-parameters.v\",\n\t    \"sync_pulse_synchronizer.v\",\n\t    \"synchronizer_asr.v\",\n\t    \"synchronizer_asr_dup.v\",\n\t    \"tlu_misctl.v\",\n\t    \"ucb_bus_in.v\",\n\t    \"ucb_bus_out.v\",\n\t    \"ucb_flow_jbi.v\",\n\t    \"ucb_flow_spi.v\"\n\t]\n}\n"
  },
  {
    "path": "conf/generators/meta-path/yosys-asicworld.json",
    "content": "{\n\t\"name\": \"asicworld\",\n\t\"project\": \"yosys\",\n\t\"paths\": [\n\t\t[\"tools\", \"yosys\", \"tests\", \"asicworld\"]\n\t],\n\t\"matches\": [\"*.v\"],\n\t\"blacklist\": [\"code_verilog_tutorial_counter_tb.v\", \"code_hdl_models_arbiter_tb.v\", \"code_verilog_tutorial_first_counter_tb.v\", \"code_verilog_tutorial_fsm_full_tb.v\", \"code_hdl_models_full_subtracter_gates.v\", \"simple_values.v\", \"svinterface_at_top.sv\"],\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/yosys-errors.json",
    "content": "{\n\t\"name\": \"errors\",\n\t\"project\": \"yosys\",\n\t\"should_fail_because\": \"this test imported from yosys repository contains intentional syntax error\",\n\t\"paths\": [\n\t\t[\"tools\", \"yosys\", \"tests\", \"errors\"]\n\t],\n\t\"matches\": [\"*.v\"],\n\t\"blacklist\": [\"syntax_err06.v\", \"syntax_err09.v\", \"syntax_err12.v\", \"syntax_err13.v\"],\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/yosys-memories.json",
    "content": "{\n\t\"name\": \"memories\",\n\t\"project\": \"yosys\",\n\t\"paths\": [\n\t\t[\"tools\", \"yosys\", \"tests\", \"memories\"]\n\t],\n\t\"matches\": [\"*.v\"],\n\t\"blacklist\": [\"issue00335.v\"],\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/yosys-simple.json",
    "content": "{\n\t\"name\": \"simple\",\n\t\"project\": \"yosys\",\n\t\"paths\": [\n\t\t[\"tools\", \"yosys\", \"tests\", \"simple\"]\n\t],\n\t\"matches\": [\"*.v\"],\n\t\"blacklist\": [\"hierdefparam.v\", \"memory.v\", \"values.v\", \"func_width_scope.v\", \"named_genblk.v\", \"mem2reg_bounds_tern.v\", \"module_scope_func.v\"],\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/yosys-sva.json",
    "content": "{\n\t\"name\": \"sva\",\n\t\"project\": \"yosys\",\n\t\"paths\": [\n\t\t[\"tools\", \"yosys\", \"tests\", \"sva\"]\n\t],\n\t\"matches\": [\"*.sv\"],\n\t\"blacklist\": [\"basic04.sv\", \"basic05.sv\"],\n\t\"results_group\": \"imported\"\n}\n"
  },
  {
    "path": "conf/generators/meta-path/yosys-svinterfaces.json",
    "content": "{\r\n\t\"name\": \"svinterfaces\",\r\n\t\"project\": \"yosys\",\r\n\t\"paths\": [\r\n\t\t[\"tools\", \"yosys\", \"tests\", \"svinterfaces\"]\r\n\t],\r\n\t\"matches\": [\"*.sv\"],\r\n\t\"blacklist\": [\"svinterface1.sv\", \"svinterface_at_top.sv\", \"load_and_derive.sv\", \"ondemand.sv\", \"resolve_types.sv\"],\r\n\t\"results_group\": \"imported\"\r\n}\r\n"
  },
  {
    "path": "conf/generators/templates/assignment-sim.json",
    "content": "{\n\t\"name\": \"assignment_sim\",\n\t\"filename\": \"11.4.1--{1}_assignment-sim-{4}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {1}_assignment_sim_{4}\",\n\t\t\":description: {0}= assignment simulation test\",\n        \":type: simulation elaboration parsing\",\n\t\t\":tags: 11.4.1\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"reg [31:0] a;\",\n\t\t\"wire [31:0] b;\",\n\t\t\"assign b = 32'd{3};\",\n\t\t\"final begin\",\n\t\t\"    a = 32'd{2};\",\n\t\t\"    a {0}= b;\",\n\t\t\"    $display(\\\":assert: (int(%s) == %d)\\\", \\\"{2}{0}{3}\\\", a);\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n    \"cartesian_product\": \"true\",\n\t\"values\": [[\n\t\t[\"+\", \"plus\"],\n\t\t[\"-\", \"minus\"],\n\t\t[\"*\", \"mul\"],\n\t\t[\"/\", \"div\"],\n\t\t[\"%\", \"mod\"],\n\t\t[\"&\", \"and\"],\n\t\t[\"|\", \"or\"],\n\t\t[\"^\", \"xor\"],\n\t\t[\"<<\", \"log_shl\"],\n\t\t[\">>\", \"log_shr\"]\n\t],\n    [\n        [\"4\", \"3\", \"0\"],\n        [\"4\", \"4\", \"1\"]\n    ]]\n}\n"
  },
  {
    "path": "conf/generators/templates/assignment.json",
    "content": "{\n\t\"name\": \"assignment_op\",\n\t\"filename\": \"11.4.1--{1}_assignment.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {1}_assignment\",\n\t\t\":description: {0} assignment test\",\n\t\t\":tags: 11.4.1\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"int a = 12;\",\n\t\t\"int b = 5;\",\n\t\t\"initial begin\",\n\t\t\"    a {0} b;\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"=\", \"normal\"],\n\t\t[\"+=\", \"plus\"],\n\t\t[\"-=\", \"minus\"],\n\t\t[\"*=\", \"mul\"],\n\t\t[\"/=\", \"div\"],\n\t\t[\"%=\", \"mod\"],\n\t\t[\"&=\", \"and\"],\n\t\t[\"|=\", \"or\"],\n\t\t[\"^=\", \"xor\"],\n\t\t[\"<<=\", \"log_shl\"],\n\t\t[\">>=\", \"log_shr\"],\n\t\t[\"<<<=\", \"arith_shl\"],\n\t\t[\">>>=\", \"arith_shr\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/binary.json",
    "content": "{\n\t\"name\": \"binary_op\",\n\t\"filename\": \"{2}--binary_op_{1}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: binary_op_{1}\",\n\t\t\":description: {0} operator test\",\n\t\t\":tags: {2}\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"int a = 12;\",\n\t\t\"int b = 5;\",\n\t\t\"int c;\",\n\t\t\"initial begin\",\n\t\t\"    c = a {0} b;\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"+\", \"plus\", \"11.4.3\"],\n\t\t[\"-\", \"minus\", \"11.4.3\"],\n\t\t[\"*\", \"mul\", \"11.4.3\"],\n\t\t[\"/\", \"div\", \"11.4.3\"],\n\t\t[\"%\", \"mod\", \"11.4.3\"],\n\t\t[\"==\", \"log_eq\", \"11.4.5\"],\n\t\t[\"!=\", \"log_neq\", \"11.4.5\"],\n\t\t[\"===\", \"case_eq\", \"11.4.5\"],\n\t\t[\"!==\", \"case_neq\", \"11.4.5\"],\n\t\t[\"==?\", \"wild_eq\", \"11.4.6\"],\n\t\t[\"!=?\", \"wild_neq\", \"11.4.6\"],\n\t\t[\"&&\", \"log_and\", \"11.4.7\"],\n\t\t[\"||\", \"log_or\", \"11.4.7\"],\n\t\t[\"**\", \"pow\", \"11.4.3\"],\n\t\t[\"<\", \"lt\", \"11.4.4\"],\n\t\t[\"<=\", \"le\", \"11.4.4\"],\n\t\t[\">\", \"gt\", \"11.4.4\"],\n\t\t[\">=\", \"ge\", \"11.4.4\"],\n\t\t[\"&\", \"bit_and\", \"11.4.8\"],\n\t\t[\"|\", \"bit_or\", \"11.4.8\"],\n\t\t[\"^\", \"bit_xor\", \"11.4.8\"],\n\t\t[\"^~\", \"bit_xnor\", \"11.4.8\"],\n\t\t[\"~^\", \"bit_xnor\", \"11.4.8\"],\n\t\t[\">>\", \"log_shr\", \"11.4.10\"],\n\t\t[\"<<\", \"log_shl\", \"11.4.10\"],\n\t\t[\">>>\", \"arith_shr\", \"11.4.10\"],\n\t\t[\"<<<\", \"arith_shl\", \"11.4.10\"],\n\t\t[\"->\", \"log_imp\", \"11.4.7\"],\n\t\t[\"<->\", \"log_equiv\", \"11.4.7\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/encapsulation-fail.json",
    "content": "{\n\t\"name\": \"encapsulation\",\n\t\"filename\": \"8.18--{0}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {0}\",\n\t\t\":description: encapsulation test\",\n\t\t\":should_fail_because: {1}\",\n\t\t\":tags: 8.18\",\n\t\t\":type: simulation elaboration\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"class a_cls;\",\n\t\t\"    local int a_loc = 21;\",\n\t\t\"    protected int a_prot = 22;\",\n\t\t\"    int a = 23;\",\n\t\t\"endclass\",\n\t\t\"class b_cls extends a_cls;\",\n\t\t\"    local int b_loc = 31;\",\n\t\t\"    protected int b_prot = 32;\",\n\t\t\"    int b = 33;\",\n\t\t\"    function void fun();\",\n\t\t\"        $display({2});\",\n\t\t\"    endfunction\",\n\t\t\"endclass\",\n\t\t\"b_cls b_obj;\",\n\t\t\"initial begin\",\n\t\t\"    b_obj = new;\",\n\t\t\"    $display(b_obj.{3});\",\n\t\t\"    b_obj.fun();\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"inherited_local_from_outside\", \"It is illegal to access inherited local variable from subclass instance.\", \"b\", \"a_loc\"],\n\t\t[\"local_from_outside\", \"It is illegal to access local variable from class instance.\", \"b\", \"b_loc\"],\n\t\t[\"inherited_prot_from_outside\", \"It is illegal to access inherited protected variable from subclass instance.\", \"b\", \"a_prot\"],\n\t\t[\"prot_from_outside\", \"It is illegal to access protected variable from class instance.\", \"b\", \"b_prot\"],\n\t\t[\"inherited_local_from_inside\", \"It is illegal to access inherited local variable inside subclass.\", \"a_loc\", \"b\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/encapsulation-success.json",
    "content": "{\n\t\"name\": \"encapsulation\",\n\t\"filename\": \"8.18--{0}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {0}\",\n\t\t\":description: encapsulation test\",\n\t\t\":tags: 8.18\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"class a_cls;\",\n\t\t\"    local int a_loc = 21;\",\n\t\t\"    protected int a_prot = 22;\",\n\t\t\"    int a = 23;\",\n\t\t\"endclass\",\n\t\t\"class b_cls extends a_cls;\",\n\t\t\"    local int b_loc = 31;\",\n\t\t\"    protected int b_prot = 32;\",\n\t\t\"    int b = 33;\",\n\t\t\"    function void fun();\",\n\t\t\"        $display({1});\",\n\t\t\"    endfunction\",\n\t\t\"endclass\",\n\t\t\"b_cls b_obj;\",\n\t\t\"initial begin\",\n\t\t\"    b_obj = new;\",\n\t\t\"    $display(b_obj.{2});\",\n\t\t\"    b_obj.fun();\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"local_from_inside\", \"b_loc\", \"b\"],\n\t\t[\"inherited_prot_from_inside\", \"a_prot\", \"b\"],\n\t\t[\"prot_from_inside\", \"b_prot\", \"b\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/equality.json",
    "content": "{\n\t\"name\": \"equality_operators_sim\",\n\t\"filename\": \"11.4.5--equality_operator_{4}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: equality_operator_sim_{4}\",\n\t\t\":description: equality operator test in simulation\",\n        \":type: simulation elaboration parsing\",\n\t\t\":tags: 11.4.5\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"wire [7:0] a = {0};\",\n\t\t\"wire [7:0] b = {1};\",\n\t\t\"wire c;\",\n\t\t\"assign a = {0};\",\n\t\t\"assign b = {1};\",\n\t\t\"assign c = a {2} b;\",\n\t\t\"final begin\",\n\t\t\"    $display(\\\":assert: ('%s' == '%d')\\\", \\\"{3}\\\", c);\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"8'b1101x001\", \"8'b1101x001\", \"==\" , \"x\"],\n\t\t[\"8'b1101x001\", \"8'b1101x000\", \"==\" , \"0\"],\n\t\t[\"8'b1101z001\", \"8'b1101z001\", \"==\" , \"x\"],\n\t\t[\"8'b1101z001\", \"8'b1101z000\", \"==\" , \"0\"],\n\t\t[\"8'b11011001\", \"8'b11011001\", \"==\" , \"1\"],\n\t\t[\"8'b11011001\", \"8'b11011000\", \"==\" , \"0\"],\n\t\t[\"8'b1101x001\", \"8'b1101x001\", \"!=\" , \"x\"],\n\t\t[\"8'b1101x001\", \"8'b1101x000\", \"!=\" , \"1\"],\n\t\t[\"8'b1101z001\", \"8'b1101z001\", \"!=\" , \"x\"],\n\t\t[\"8'b1101z001\", \"8'b1101z000\", \"!=\" , \"1\"],\n\t\t[\"8'b11011001\", \"8'b11011001\", \"!=\" , \"0\"],\n\t\t[\"8'b11011001\", \"8'b11011000\", \"!=\" , \"1\"],\n\t\t[\"8'b1101x001\", \"8'b1101x001\", \"===\", \"1\"],\n\t\t[\"8'b1101x001\", \"8'b1101x000\", \"===\", \"0\"],\n\t\t[\"8'b1101z001\", \"8'b1101z001\", \"===\", \"1\"],\n\t\t[\"8'b1101z001\", \"8'b1101z000\", \"===\", \"0\"],\n\t\t[\"8'b11011001\", \"8'b11011001\", \"===\", \"1\"],\n\t\t[\"8'b11011001\", \"8'b11011000\", \"===\", \"0\"],\n\t\t[\"8'b1101x001\", \"8'b1101x001\", \"!==\", \"0\"],\n\t\t[\"8'b1101x001\", \"8'b1101x000\", \"!==\", \"1\"],\n\t\t[\"8'b1101z001\", \"8'b1101z001\", \"!==\", \"0\"],\n\t\t[\"8'b1101z001\", \"8'b1101z000\", \"!==\", \"1\"],\n\t\t[\"8'b11011001\", \"8'b11011001\", \"!==\", \"0\"],\n\t\t[\"8'b11011001\", \"8'b11011000\", \"!==\", \"1\"],\n\t\t[\"8'b1101z001\", \"8'b1101x001\", \"===\", \"0\"],\n\t\t[\"8'b1101z001\", \"8'b1101x001\", \"==\" , \"x\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/force-assignments.json",
    "content": "{\n\t\"name\": \"assignment-strengths\",\n\t\"filename\": \"10.3.4--assignment_{0}_{1}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: cont_assignment_strength_{0}_{1}\",\n\t\t\":description: {0} {1} assignment test\",\n\t\t\":tags: 10.3.4\",\n\t\t\"*/\",\n\t\t\"module top(input a, input b);\",\n\t\t\"wire ({0}, {1}) w = a & b;\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"supply1\", \"supply0\"],\n\t\t[\"strong1\", \"supply0\"],\n\t\t[\"pull1\", \"supply0\"],\n\t\t[\"weak1\", \"supply0\"],\n\t\t[\"highz1\", \"supply0\"],\n\t\t[\"supply1\", \"strong0\"],\n\t\t[\"strong1\", \"strong0\"],\n\t\t[\"pull1\", \"strong0\"],\n\t\t[\"weak1\", \"strong0\"],\n\t\t[\"highz1\", \"strong0\"],\n\t\t[\"supply1\", \"pull0\"],\n\t\t[\"strong1\", \"pull0\"],\n\t\t[\"pull1\", \"pull0\"],\n\t\t[\"weak1\", \"pull0\"],\n\t\t[\"highz1\", \"pull0\"],\n\t\t[\"supply1\", \"weak0\"],\n\t\t[\"strong1\", \"weak0\"],\n\t\t[\"pull1\", \"weak0\"],\n\t\t[\"weak1\", \"weak0\"],\n\t\t[\"highz1\", \"weak0\"],\n\t\t[\"supply1\", \"highz0\"],\n\t\t[\"strong1\", \"highz0\"],\n\t\t[\"pull1\", \"highz0\"],\n\t\t[\"weak1\", \"highz0\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/integers.json",
    "content": "{\n\t\"name\": \"integers\",\n\t\"filename\": \"6.11--integer_{2}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: integer_{2}\",\n\t\t\":description: {1} {0}net test\",\n\t\t\":tags: 6.11\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"{1} {0}v;\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"\", \"shortint\", \"shortint\"],\n\t\t[\"\", \"int\", \"int\"],\n\t\t[\"\", \"longint\", \"longint\"],\n\t\t[\"\", \"byte\", \"byte\"],\n\t\t[\"\", \"bit\", \"bit\"],\n\t\t[\"\", \"logic\", \"logic\"],\n\t\t[\"\", \"reg\", \"reg\"],\n\t\t[\"\", \"integer\", \"integer\"],\n\t\t[\"\", \"time\", \"time\"],\n\t\t[\"signed \", \"shortint\", \"signed_shortint\"],\n\t\t[\"signed \", \"int\", \"signed_int\"],\n\t\t[\"signed \", \"longint\", \"signed_longint\"],\n\t\t[\"signed \", \"byte\", \"signed_byte\"],\n\t\t[\"signed \", \"bit\", \"signed_bit\"],\n\t\t[\"signed \", \"logic\", \"signed_logic\"],\n\t\t[\"signed \", \"reg\", \"signed_reg\"],\n\t\t[\"signed \", \"integer\", \"signed_integer\"],\n\t\t[\"signed \", \"time\", \"signed_time\"],\n\t\t[\"unsigned \", \"shortint\", \"unsigned_shortint\"],\n\t\t[\"unsigned \", \"int\", \"unsigned_int\"],\n\t\t[\"unsigned \", \"longint\", \"unsigned_longint\"],\n\t\t[\"unsigned \", \"byte\", \"unsigned_byte\"],\n\t\t[\"unsigned \", \"bit\", \"unsigned_bit\"],\n\t\t[\"unsigned \", \"logic\", \"unsigned_logic\"],\n\t\t[\"unsigned \", \"reg\", \"unsigned_reg\"],\n\t\t[\"unsigned \", \"integer\", \"unsigned_integer\"],\n\t\t[\"unsigned \", \"time\", \"unsigned_time\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/keywords.json",
    "content": "{\n\t\"name\": \"keywords\",\n\t\"filename\": \"5.6.2--keyword_{0}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: keyword_{0}\",\n\t\t\":description: The '{0}' keyword should be reserved\",\n\t\t\":should_fail_because: The '{0}' keyword should be reserved\",\n\t\t\":tags: 5.6.2\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"    bit {0};\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"accept_on\"],\n\t\t[\"alias\"],\n\t\t[\"always\"],\n\t\t[\"always_comb\"],\n\t\t[\"always_ff\"],\n\t\t[\"always_latch\"],\n\t\t[\"and\"],\n\t\t[\"assert\"],\n\t\t[\"assign\"],\n\t\t[\"assume\"],\n\t\t[\"automatic\"],\n\t\t[\"before\"],\n\t\t[\"begin\"],\n\t\t[\"bind\"],\n\t\t[\"bins\"],\n\t\t[\"binsof\"],\n\t\t[\"bit\"],\n\t\t[\"break\"],\n\t\t[\"buf\"],\n\t\t[\"bufif0\"],\n\t\t[\"bufif1\"],\n\t\t[\"byte\"],\n\t\t[\"case\"],\n\t\t[\"casex\"],\n\t\t[\"casez\"],\n\t\t[\"cell\"],\n\t\t[\"chandle\"],\n\t\t[\"checker\"],\n\t\t[\"class\"],\n\t\t[\"clocking\"],\n\t\t[\"cmos\"],\n\t\t[\"config\"],\n\t\t[\"const\"],\n\t\t[\"constraint\"],\n\t\t[\"context\"],\n\t\t[\"continue\"],\n\t\t[\"cover\"],\n\t\t[\"covergroup\"],\n\t\t[\"coverpoint\"],\n\t\t[\"cross\"],\n\t\t[\"deassign\"],\n\t\t[\"default\"],\n\t\t[\"defparam\"],\n\t\t[\"design\"],\n\t\t[\"disable\"],\n\t\t[\"dist\"],\n\t\t[\"do\"],\n\t\t[\"edge\"],\n\t\t[\"else\"],\n\t\t[\"end\"],\n\t\t[\"endcase\"],\n\t\t[\"endchecker\"],\n\t\t[\"endclass\"],\n\t\t[\"endclocking\"],\n\t\t[\"endconfig\"],\n\t\t[\"endfunction\"],\n\t\t[\"endgenerate\"],\n\t\t[\"endgroup\"],\n\t\t[\"endinterface\"],\n\t\t[\"endmodule\"],\n\t\t[\"endpackage\"],\n\t\t[\"endprimitive\"],\n\t\t[\"endprogram\"],\n\t\t[\"endproperty\"],\n\t\t[\"endspecify\"],\n\t\t[\"endsequence\"],\n\t\t[\"endtable\"],\n\t\t[\"endtask\"],\n\t\t[\"enum\"],\n\t\t[\"event\"],\n\t\t[\"eventually\"],\n\t\t[\"expect\"],\n\t\t[\"export\"],\n\t\t[\"extends\"],\n\t\t[\"extern\"],\n\t\t[\"final\"],\n\t\t[\"first_match\"],\n\t\t[\"for\"],\n\t\t[\"force\"],\n\t\t[\"foreach\"],\n\t\t[\"forever\"],\n\t\t[\"fork\"],\n\t\t[\"forkjoin\"],\n\t\t[\"function\"],\n\t\t[\"generate\"],\n\t\t[\"genvar\"],\n\t\t[\"global\"],\n\t\t[\"highz0\"],\n\t\t[\"highz1\"],\n\t\t[\"if\"],\n\t\t[\"iff\"],\n\t\t[\"ifnone\"],\n\t\t[\"ignore_bins\"],\n\t\t[\"illegal_bins\"],\n\t\t[\"implements\"],\n\t\t[\"implies\"],\n\t\t[\"import\"],\n\t\t[\"incdir\"],\n\t\t[\"include\"],\n\t\t[\"initial\"],\n\t\t[\"inout\"],\n\t\t[\"input\"],\n\t\t[\"inside\"],\n\t\t[\"instance\"],\n\t\t[\"int\"],\n\t\t[\"integer\"],\n\t\t[\"interconnect\"],\n\t\t[\"interface\"],\n\t\t[\"intersect\"],\n\t\t[\"join\"],\n\t\t[\"join_any\"],\n\t\t[\"join_none\"],\n\t\t[\"large\"],\n\t\t[\"let\"],\n\t\t[\"liblist\"],\n\t\t[\"library\"],\n\t\t[\"local\"],\n\t\t[\"localparam\"],\n\t\t[\"logic\"],\n\t\t[\"longint\"],\n\t\t[\"macromodule\"],\n\t\t[\"matches\"],\n\t\t[\"medium\"],\n\t\t[\"modport\"],\n\t\t[\"module\"],\n\t\t[\"nand\"],\n\t\t[\"negedge\"],\n\t\t[\"nettype\"],\n\t\t[\"new\"],\n\t\t[\"nexttime\"],\n\t\t[\"nmos\"],\n\t\t[\"nor\"],\n\t\t[\"noshowcancelled\"],\n\t\t[\"not\"],\n\t\t[\"notif0\"],\n\t\t[\"notif1\"],\n\t\t[\"null\"],\n\t\t[\"or\"],\n\t\t[\"output\"],\n\t\t[\"package\"],\n\t\t[\"packed\"],\n\t\t[\"parameter\"],\n\t\t[\"pmos\"],\n\t\t[\"posedge\"],\n\t\t[\"primitive\"],\n\t\t[\"priority\"],\n\t\t[\"program\"],\n\t\t[\"property\"],\n\t\t[\"protected\"],\n\t\t[\"pull0\"],\n\t\t[\"pull1\"],\n\t\t[\"pulldown\"],\n\t\t[\"pullup\"],\n\t\t[\"pulsestyle_ondetect\"],\n\t\t[\"pulsestyle_onevent\"],\n\t\t[\"pure\"],\n\t\t[\"rand\"],\n\t\t[\"randc\"],\n\t\t[\"randcase\"],\n\t\t[\"randsequence\"],\n\t\t[\"rcmos\"],\n\t\t[\"real\"],\n\t\t[\"realtime\"],\n\t\t[\"ref\"],\n\t\t[\"reg\"],\n\t\t[\"reject_on\"],\n\t\t[\"release\"],\n\t\t[\"repeat\"],\n\t\t[\"restrict\"],\n\t\t[\"return\"],\n\t\t[\"rnmos\"],\n\t\t[\"rpmos\"],\n\t\t[\"rtran\"],\n\t\t[\"rtranif0\"],\n\t\t[\"rtranif1\"],\n\t\t[\"s_always\"],\n\t\t[\"s_eventually\"],\n\t\t[\"s_nexttime\"],\n\t\t[\"s_until\"],\n\t\t[\"s_until_with\"],\n\t\t[\"scalared\"],\n\t\t[\"sequence\"],\n\t\t[\"shortint\"],\n\t\t[\"shortreal\"],\n\t\t[\"showcancelled\"],\n\t\t[\"signed\"],\n\t\t[\"small\"],\n\t\t[\"soft\"],\n\t\t[\"solve\"],\n\t\t[\"specify\"],\n\t\t[\"specparam\"],\n\t\t[\"static\"],\n\t\t[\"string\"],\n\t\t[\"strong\"],\n\t\t[\"strong0\"],\n\t\t[\"strong1\"],\n\t\t[\"struct\"],\n\t\t[\"super\"],\n\t\t[\"supply0\"],\n\t\t[\"supply1\"],\n\t\t[\"sync_accept_on\"],\n\t\t[\"sync_reject_on\"],\n\t\t[\"table\"],\n\t\t[\"tagged\"],\n\t\t[\"task\"],\n\t\t[\"this\"],\n\t\t[\"throughout\"],\n\t\t[\"time\"],\n\t\t[\"timeprecision\"],\n\t\t[\"timeunit\"],\n\t\t[\"tran\"],\n\t\t[\"tranif0\"],\n\t\t[\"tranif1\"],\n\t\t[\"tri\"],\n\t\t[\"tri0\"],\n\t\t[\"tri1\"],\n\t\t[\"triand\"],\n\t\t[\"trior\"],\n\t\t[\"trireg\"],\n\t\t[\"type\"],\n\t\t[\"typedef\"],\n\t\t[\"union\"],\n\t\t[\"unique\"],\n\t\t[\"unique0\"],\n\t\t[\"unsigned\"],\n\t\t[\"until\"],\n\t\t[\"until_with\"],\n\t\t[\"untyped\"],\n\t\t[\"use\"],\n\t\t[\"uwire\"],\n\t\t[\"var\"],\n\t\t[\"vectored\"],\n\t\t[\"virtual\"],\n\t\t[\"void\"],\n\t\t[\"wait\"],\n\t\t[\"wait_order\"],\n\t\t[\"wand\"],\n\t\t[\"weak\"],\n\t\t[\"weak0\"],\n\t\t[\"weak1\"],\n\t\t[\"while\"],\n\t\t[\"wildcard\"],\n\t\t[\"wire\"],\n\t\t[\"with\"],\n\t\t[\"within\"],\n\t\t[\"wor\"],\n\t\t[\"xnor\"],\n\t\t[\"xor\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/logical-equiv.json",
    "content": "{\n\t\"name\": \"logical_equivalence_operator_sim\",\n\t\"filename\": \"11.4.7--logical_equiv_operator_{2}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: logical_equiv_operator_sim_{2}\",\n\t\t\":description: logical equivalence operator test in simulation\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\":tags: 11.4.7\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"wire a;\",\n\t\t\"wire b;\",\n\t\t\"wire c;\",\n\t\t\"assign a = {0};\",\n\t\t\"assign b = {1};\",\n\t\t\"assign c = a <-> b;\",\n\t\t\"final begin\",\n\t\t\"    $display(\\\":assert: ((%s) == %d)\\\", \\\"(((not {0}) or {1}) and ((not {1}) or {0}))\\\", c);\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"0\", \"0\"],\n\t\t[\"0\", \"1\"],\n\t\t[\"1\", \"0\"],\n\t\t[\"1\", \"1\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/logical-impl.json",
    "content": "{\n\t\"name\": \"logical_implication_operator_sim\",\n\t\"filename\": \"11.4.7--logical_impl_operator_{2}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: logical_impl_operator_sim_{2}\",\n\t\t\":description: logical implication operator test in simulation\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\":tags: 11.4.7\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"wire a;\",\n\t\t\"wire b;\",\n\t\t\"wire c;\",\n\t\t\"assign a = {0};\",\n\t\t\"assign b = {1};\",\n\t\t\"assign c = a -> b;\",\n\t\t\"final begin\",\n\t\t\"    $display(\\\":assert: ((%s) == %d)\\\", \\\"((not {0}) or {1})\\\", c);\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"0\", \"0\"],\n\t\t[\"0\", \"1\"],\n\t\t[\"1\", \"0\"],\n\t\t[\"1\", \"1\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/logical.json",
    "content": "{\n\t\"name\": \"logical_operators_sim\",\n\t\"filename\": \"11.4.7--logical_operator_{4}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: logical_operator_sim_{4}\",\n\t\t\":description: logical operator test in simulation\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\":tags: 11.4.7\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"wire a;\",\n\t\t\"wire b;\",\n\t\t\"wire c;\",\n\t\t\"assign a = {0};\",\n\t\t\"assign b = {1};\",\n\t\t\"assign c = a {2} b;\",\n\t\t\"final begin\",\n\t\t\"    $display(\\\":assert: ((%s) == %d)\\\", \\\"{0} {3} {1}\\\", c);\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"cartesian_product\": \"true\",\n\t\"values\": [[\n\t\t[\"0\", \"0\"],\n\t\t[\"0\", \"1\"],\n\t\t[\"1\", \"0\"],\n\t\t[\"1\", \"1\"]\n\t],\n\t[\n\t\t[\"&&\", \"and\"],\n\t\t[\"||\", \"or\"]\n\t]]\n}\n"
  },
  {
    "path": "conf/generators/templates/nets.json",
    "content": "{\n\t\"name\": \"nets\",\n\t\"filename\": \"{1}--net_{0}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: net_{0}\",\n\t\t\":description: {0} net test\",\n\t\t\":tags: {1}\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"{0} v;\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"wire\", \"6.6.1\"],\n\t\t[\"tri\", \"6.6.1\"],\n\t\t[\"uwire\", \"6.6.2\"],\n\t\t[\"wor\", \"6.6.3\"],\n\t\t[\"wand\", \"6.6.3\"],\n\t\t[\"trior\", \"6.6.3\"],\n\t\t[\"triand\", \"6.6.3\"],\n\t\t[\"trireg\", \"6.6.4\"],\n\t\t[\"tri0\", \"6.6.5\"],\n\t\t[\"tri1\", \"6.6.5\"],\n\t\t[\"supply0\", \"6.6.6\"],\n\t\t[\"supply1\", \"6.6.6\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/operators-sim.json",
    "content": "{\n\t\"name\": \"operators_sim\",\n\t\"filename\": \"{2}--{1}_operator_sim_{5}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {1}_operator_sim_{5}\",\n\t\t\":description: {0} operator test in simulation\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\":tags: {2}\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"wire [31:0] a;\",\n\t\t\"wire [31:0] b;\",\n\t\t\"wire [31:0] c;\",\n\t\t\"assign a = 32'd{3};\",\n\t\t\"assign b = 32'd{4};\",\n\t\t\"assign c = a {0} b;\",\n\t\t\"final begin\",\n\t\t\"    $display(\\\":assert: (int(%s) == %d)\\\", \\\"{3}{0}{4}\\\", c);\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n    \"cartesian_product\": \"true\",\n\t\"values\": [[\n\t\t[\"+\", \"plus\", \"11.4.3\"],\n\t\t[\"-\", \"minus\", \"11.4.3\"],\n\t\t[\"*\", \"mul\", \"11.4.3\"],\n\t\t[\"/\", \"div\", \"11.4.3\"],\n\t\t[\"%\", \"mod\", \"11.4.3\"],\n\t\t[\"**\", \"exp\", \"11.4.3\"],\n\t\t[\"==\", \"log_eq\", \"11.4.5\"],\n\t\t[\"!=\", \"log_neq\", \"11.4.5\"],\n\t\t[\"<\", \"lt\", \"11.4.4\"],\n\t\t[\"<=\", \"le\", \"11.4.4\"],\n\t\t[\">\", \"gt\", \"11.4.4\"],\n\t\t[\">=\", \"ge\", \"11.4.4\"],\n\t\t[\"&\", \"bit_and\", \"11.4.8\"],\n\t\t[\"|\", \"bit_or\", \"11.4.8\"],\n\t\t[\"^\", \"bit_xor\", \"11.4.8\"],\n\t\t[\"<<\", \"log_shl\", \"11.4.10\"],\n\t\t[\">>\", \"log_shr\", \"11.4.10\"]\n\t],\n\t[\n\t\t[\"4\", \"3\", \"0\"],\n\t\t[\"4\", \"4\", \"1\"]\n\t]]\n}\n"
  },
  {
    "path": "conf/generators/templates/sampled-functions-gclk.json",
    "content": "{\n\t\"name\": \"sampled_functions\",\n\t\"filename\": \"20.13--{0}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {0}_function\",\n\t\t\":description: ${0} test\",\n\t\t\":tags: {1}\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"logic a, clk;\",\n\t\t\"global clocking @(posedge clk); endclocking\",\n\t\t\"assert property (@(posedge clk) ${0}(a)) else $info;\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"past_gclk\", \"20.13 16.9\"],\n\t\t[\"rose_gclk\", \"20.13 16.9\"],\n\t\t[\"fell_gclk\", \"20.13 16.9\"],\n\t\t[\"stable_gclk\", \"20.13 16.9\"],\n\t\t[\"changed_gclk\", \"20.13 16.9\"],\n\t\t[\"future_gclk\", \"20.13 16.9\"],\n\t\t[\"rising_gclk\", \"20.13 16.9\"],\n\t\t[\"falling_gclk\", \"20.13 16.9\"],\n\t\t[\"steady_gclk\", \"20.13 16.9\"],\n\t\t[\"changing_gclk\", \"20.13 16.9\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/sampled-functions.json",
    "content": "{\n\t\"name\": \"sampled_functions\",\n\t\"filename\": \"20.13--{0}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {0}_function\",\n\t\t\":description: ${0} test\",\n\t\t\":tags: {1}\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"logic a, clk;\",\n\t\t\"assert property (@(posedge clk) ${0}(a)) else $info;\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"sampled\", \"20.13 16.9\"],\n\t\t[\"rose\", \"20.13 16.9\"],\n\t\t[\"fell\", \"20.13 16.9\"],\n\t\t[\"stable\", \"20.13 16.9\"],\n\t\t[\"changed\", \"20.13 16.9\"],\n\t\t[\"past\", \"20.13 16.9\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/simple-logical.json",
    "content": "{\n\t\"name\": \"simple_logical_operators_sim\",\n\t\"filename\": \"11.4.7--simple_{1}_logical_operator.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: simple_{1}_logical_operator_sim\",\n\t\t\":description: minimal {0} operator simulation test (without result verification)\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\":tags: 11.4.7\",\n\t\t\"*/\",\n\t\t\"module top(input a, input b, output c);\",\n\t\t\"    assign c = a {0} b;\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"&&\", \"and\"],\n\t\t[\"||\", \"or\"],\n\t\t[\"<->\", \"equiv\"],\n\t\t[\"->\", \"impl\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/simple-operators-sim.json",
    "content": "{\n\t\"name\": \"operators_sim\",\n\t\"filename\": \"{2}--simple_{1}_operator_sim.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: simple_{1}_operator_sim\",\n\t\t\":description: minimal {0} operator simulation test (without result verification)\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\":tags: {2}\",\n\t\t\"*/\",\n\t\t\"module top(input [3:0] a, input [3:0] b, output [3:0] c);\",\n\t\t\"    assign c = a {0} b;\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"+\", \"plus\", \"11.4.3\"],\n\t\t[\"-\", \"minus\", \"11.4.3\"],\n\t\t[\"*\", \"mul\", \"11.4.3\"],\n\t\t[\"/\", \"div\", \"11.4.3\"],\n\t\t[\"%\", \"mod\", \"11.4.3\"],\n\t\t[\"**\", \"exp\", \"11.4.3\"],\n\t\t[\"==\", \"eq\", \"11.4.5\"],\n\t\t[\"!=\", \"neq\", \"11.4.5\"],\n\t\t[\"===\", \"eq_xz\", \"11.4.5\"],\n\t\t[\"!==\", \"neq_xz\", \"11.4.5\"],\n\t\t[\"<\", \"lt\", \"11.4.4\"],\n\t\t[\"<=\", \"le\", \"11.4.4\"],\n\t\t[\">\", \"gt\", \"11.4.4\"],\n\t\t[\">=\", \"ge\", \"11.4.4\"],\n\t\t[\"&\", \"bit_and\", \"11.4.8\"],\n\t\t[\"|\", \"bit_or\", \"11.4.8\"],\n\t\t[\"^\", \"bit_xor\", \"11.4.8\"],\n\t\t[\"<<\", \"log_shl\", \"11.4.10\"],\n\t\t[\">>\", \"log_shr\", \"11.4.10\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/simple-unary.json",
    "content": "{\n\t\"name\": \"unary_op\",\n\t\"filename\": \"{2}--simple_unary_op_{1}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: simple_unary_op_{1}\",\n\t\t\":description: minimal {0} operator simulation test (without result verification)\",\n\t\t\":tags: {2}\",\n\t\t\"*/\",\n\t\t\"module top(input [3:0] a, output [3:0] b);\",\n\t\t\"    assign b = {0}a;\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"+\", \"plus\", \"11.3\"],\n\t\t[\"-\", \"minus\", \"11.3\"],\n\t\t[\"!\", \"not_log\", \"11.3\"],\n\t\t[\"~\", \"not_bit\", \"11.4.8\"],\n\t\t[\"&\", \"and\", \"11.4.9\"],\n\t\t[\"~&\", \"nand\", \"11.4.9\"],\n\t\t[\"|\", \"or\", \"11.4.9\"],\n\t\t[\"~|\", \"nor\", \"11.4.9\"],\n\t\t[\"^\", \"xor\", \"11.4.9\"],\n\t\t[\"~^\", \"xnor_1\", \"11.4.9\"],\n\t\t[\"^~\", \"xnor_2\", \"11.4.9\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/trig-functions.json",
    "content": "{\n\t\"name\": \"trig_functions\",\n\t\"filename\": \"20.8--{0}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {0}_function\",\n\t\t\":description: ${0} test\",\n\t\t\":tags: 20.8\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"initial\",\n\t\t\"$display(\\\"%f\\\", ${0}(4));\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"sin\"],\n\t\t[\"cos\"],\n\t\t[\"tan\"],\n\t\t[\"asin\"],\n\t\t[\"acos\"],\n\t\t[\"atan\"],\n\t\t[\"sinh\"],\n\t\t[\"cosh\"],\n\t\t[\"tanh\"],\n\t\t[\"asinh\"],\n\t\t[\"acosh\"],\n\t\t[\"atanh\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/unary.json",
    "content": "{\n\t\"name\": \"unary_op\",\n\t\"filename\": \"{2}--unary_op_{1}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: unary_op_{1}\",\n\t\t\":description: {0} operator test\",\n\t\t\":tags: {2}\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"int a = 12;\",\n\t\t\"int b = 5;\",\n\t\t\"initial begin\",\n\t\t\"    a = {0}b;\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"+\", \"plus\", \"11.3\"],\n\t\t[\"-\", \"minus\", \"11.3\"],\n\t\t[\"!\", \"not_log\", \"11.3\"],\n\t\t[\"~\", \"not_bit\", \"11.4.8\"],\n\t\t[\"&\", \"and\", \"11.4.9\"],\n\t\t[\"~&\", \"nand\", \"11.4.9\"],\n\t\t[\"|\", \"or\", \"11.4.9\"],\n\t\t[\"~|\", \"nor\", \"11.4.9\"],\n\t\t[\"^\", \"xor\", \"11.4.9\"],\n\t\t[\"~^\", \"xnor_1\", \"11.4.9\"],\n\t\t[\"^~\", \"xnor_2\", \"11.4.9\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/uniquecase.json",
    "content": "{\n\t\"name\": \"uniquecase\",\n\t\"filename\": \"12.5.3--{2}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {1}_{0}\",\n\t\t\":description: {0} statement with {1}\",\n\t\t\":tags: 12.5.3\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"wire [3:0] a = 3;\",\n\t\t\"reg [3:0] b = 0;\",\n\t\t\"initial begin\",\n\t\t\"    {1} {0} (a)\",\n\t\t\"        0, 1: b = 1;\",\n\t\t\"        2: b = 2;\",\n\t\t\"        3: b = 3;\",\n\t\t\"    endcase\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"case\", \"unique\", \"unique_case\"],\n\t\t[\"case\", \"unique0\", \"unique0_case\"],\n\t\t[\"case\", \"priority\", \"priority_case\"],\n\t\t[\"casez\", \"unique\", \"unique_casez\"],\n\t\t[\"casez\", \"unique0\", \"unique0_casez\"],\n\t\t[\"casez\", \"priority\", \"priority_casez\"],\n\t\t[\"casex\", \"unique\", \"unique_casex\"],\n\t\t[\"casex\", \"unique0\", \"unique0_casex\"],\n\t\t[\"casex\", \"priority\", \"priority_casex\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/uvm-classes_0.json",
    "content": "{\n\t\"name\": \"uvm_classes_0\",\n\t\"filename\": \"{0}_class_0.sv\",\n\t\"template_file\": \"uvm-classes_0.sv\",\n\t\"values\": [\n\t\t[\"uvm_agent\"],\n\t\t[\"uvm_component\"],\n\t\t[\"uvm_driver\"],\n\t\t[\"uvm_env\"],\n\t\t[\"uvm_monitor\"],\n\t\t[\"uvm_sequencer\"],\n\t\t[\"uvm_scoreboard\"],\n\t\t[\"uvm_test\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/uvm-classes_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: {0}_0\n:description: {0} class test\n:tags: uvm uvm-classes\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass C extends {0};\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n        `uvm_info(\"RESULT\", \"new {0} created\", UVM_LOW);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        `uvm_info(\"RESULT\", \"build phase completed\", UVM_LOW);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        `uvm_info(\"RESULT\", \"connect phase completed\", UVM_LOW);\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n        `uvm_info(\"RESULT\", \"end of elaboration phase completed\", UVM_LOW);\n    endfunction\n\n    virtual function void start_of_simulation_phase(uvm_phase phase);\n        super.start_of_simulation_phase(phase);\n        `uvm_info(\"RESULT\", \"start of simulation phase completed\", UVM_LOW);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        `uvm_info(\"RESULT\", \"run phase phase completed\", UVM_LOW);\n    endtask\n\n    virtual function void extract_phase(uvm_phase phase);\n        super.extract_phase(phase);\n        `uvm_info(\"RESULT\", \"extract phase completed\", UVM_LOW);\n    endfunction\n\n    virtual function void check_phase(uvm_phase phase);\n        super.check_phase(phase);\n        `uvm_info(\"RESULT\", \"check phase completed\", UVM_LOW);\n    endfunction\n\n    virtual function void report_phase(uvm_phase phase);\n        super.report_phase(phase);\n        `uvm_info(\"RESULT\", \"report phase completed\", UVM_LOW);\n    endfunction\n\nendclass\n\nmodule top;\n    C obj;\n    initial begin\n        obj = new(\"C\");\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "conf/generators/templates/uvm-classes_1.json",
    "content": "{\n\t\"name\": \"uvm_classes_1\",\n\t\"filename\": \"{0}_class_1.sv\",\n\t\"template_file\": \"uvm-classes_1.sv\",\n\t\"values\": [\n\t\t[\"uvm_agent\"],\n\t\t[\"uvm_component\"],\n\t\t[\"uvm_driver\"],\n\t\t[\"uvm_env\"],\n\t\t[\"uvm_monitor\"],\n\t\t[\"uvm_sequencer\"],\n\t\t[\"uvm_scoreboard\"],\n\t\t[\"uvm_test\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/uvm-classes_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: {0}_1\n:description: {0} class test\n:tags: uvm uvm-classes\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`define PATTERN 2\n\ninterface input_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, data);\nendinterface\n\ninterface output_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, output data);\nendinterface\n\nmodule dut(input_if.port in, output_if.port out);\n    always @(posedge in.clk)\n        out.data <= in.data;\nendmodule\n\nclass C extends {0};\n    virtual output_if out_vif;\n    virtual input_if in_vif;\n\n    `uvm_component_utils(C)\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n            \"C\", \"input_if\", in_vif));\n        assert(uvm_resource_db#(virtual output_if)::read_by_name(\n            \"C\", \"output_if\", out_vif));\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(\"RESULT\", $sformatf(\"Writing %0d to input interface\", `PATTERN), UVM_LOW);\n        in_vif.data <= `PATTERN;\n        repeat(2) @(posedge out_vif.clk);\n        if(out_vif.data == `PATTERN) begin\n            `uvm_info(\"RESULT\", $sformatf(\"Match %d == %d\",\n                out_vif.data, `PATTERN), UVM_LOW);\n        end\n        else begin\n            `uvm_error(\"RESULT\", $sformatf(\"Mismatch %d != %d\",\n                out_vif.data, `PATTERN));\n        end\n        phase.drop_objection(this);\n    endtask\nendclass\n\nmodule top;\n    logic clk;\n    C obj;\n    input_if in(clk);\n    output_if out(clk);\n    dut d(in, out);\n\n    always #5 clk = !clk;\n\n    initial begin\n        obj = new(\"C\");\n        uvm_resource_db#(virtual input_if)::set(\"C\",\"input_if\", in);\n        uvm_resource_db#(virtual output_if)::set(\"C\", \"output_if\", out);\n        clk = 0;\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "conf/generators/templates/uvm-classes_2.json",
    "content": "{\n\t\"name\": \"uvm_classes_2\",\n\t\"filename\": \"{0}_class_2.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: {0}_2\",\n\t\t\":description: {0} class test\",\n\t\t\":tags: uvm uvm-classes\",\n\t\t\":type: parsing\",\n\t\t\":timeout: 300\",\n\t\t\"*/\",\n\t\t\"import uvm_pkg::*;\",\n\t\t\"`include \\\"uvm_macros.svh\\\"\\n\",\n\n\t\t\"class C extends {0}(\\\"\\\", null);\",\n\t\t\"endclass\"\n\t],\n\t\"values\": [\n\t\t[\"uvm_agent\"],\n\t\t[\"uvm_component\"],\n\t\t[\"uvm_driver\"],\n\t\t[\"uvm_env\"],\n\t\t[\"uvm_monitor\"],\n\t\t[\"uvm_sequencer\"],\n\t\t[\"uvm_scoreboard\"],\n\t\t[\"uvm_test\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/uvm-classes_3.json",
    "content": "{\n\t\"name\": \"uvm_classes_3\",\n\t\"filename\": \"{0}_class_3.sv\",\n\t\"template_file\": \"uvm-classes_3.sv\",\n\t\"values\": [\n\t\t[\"uvm_agent\"],\n\t\t[\"uvm_component\"],\n\t\t[\"uvm_driver\"],\n\t\t[\"uvm_env\"],\n\t\t[\"uvm_monitor\"],\n\t\t[\"uvm_sequencer\"],\n\t\t[\"uvm_scoreboard\"],\n\t\t[\"uvm_test\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/uvm-classes_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: {0}_3\n:description: {0} class test\n:tags: uvm uvm-classes\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass C extends {0};\n    `uvm_component_utils(C)\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n        `uvm_info(\"RESULT\", \"Created new {0}\", UVM_LOW);\n    endfunction\nendclass\n\nmodule top;\n    C obj;\n\n    initial begin\n        obj = new(\"C\");\n    end\nendmodule\n"
  },
  {
    "path": "conf/generators/templates/wildcard-const.json",
    "content": "{\n\t\"name\": \"wildcard_const_operators_sim\",\n\t\"filename\": \"11.4.6--wildcard_const_operator_{4}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: wildcard_const_operator_sim_{4}\",\n\t\t\":description: wildcard operator with constant test in simulation\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\":tags: 11.4.6\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"logic [3:0] a = {0};\",\n\t\t\"logic c;\",\n\t\t\"initial begin\",\n\t\t\"    c = a {2} {1};\",\n\t\t\"    $display(\\\":assert: ('%s' == '%d')\\\", \\\"{3}\\\", c);\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"4'b1001\", \"4'bx001\", \"==?\" , \"1\"],\n\t\t[\"4'b1001\", \"4'bz001\", \"==?\" , \"1\"],\n\t\t[\"4'bx001\", \"4'b1001\", \"==?\" , \"x\"],\n\t\t[\"4'bz001\", \"4'b1001\", \"==?\" , \"x\"],\n\t\t[\"4'bz001\", \"4'bx001\", \"==?\" , \"1\"],\n\t\t[\"4'b1001\", \"4'bx001\", \"!=?\" , \"0\"],\n\t\t[\"4'bz001\", \"4'bx001\", \"!=?\" , \"0\"],\n\t\t[\"4'bz001\", \"4'b1001\", \"!=?\" , \"x\"]\n\t]\n}\n"
  },
  {
    "path": "conf/generators/templates/wildcard.json",
    "content": "{\n\t\"name\": \"wildcard_operators_sim\",\n\t\"filename\": \"11.4.6--wildcard_operator_{4}.sv\",\n\t\"template\": [\n\t\t\"/*\",\n\t\t\":name: wildcard_operator_sim_{4}\",\n\t\t\":description: wildcard operator test in simulation\",\n\t\t\":type: simulation elaboration parsing\",\n\t\t\":tags: 11.4.6\",\n\t\t\"*/\",\n\t\t\"module top();\",\n\t\t\"logic [3:0] a = {0};\",\n\t\t\"logic [3:0] b = {1};\",\n\t\t\"logic c;\",\n\t\t\"initial begin\",\n\t\t\"    c = a {2} b;\",\n\t\t\"    $display(\\\":assert: ('%s' == '%d')\\\", \\\"{3}\\\", c);\",\n\t\t\"end\",\n\t\t\"endmodule\"\n\t],\n\t\"values\": [\n\t\t[\"4'b1001\", \"4'bx001\", \"==?\" , \"1\"],\n\t\t[\"4'b1001\", \"4'bz001\", \"==?\" , \"1\"],\n\t\t[\"4'bx001\", \"4'b1001\", \"==?\" , \"x\"],\n\t\t[\"4'bz001\", \"4'b1001\", \"==?\" , \"x\"],\n\t\t[\"4'bz001\", \"4'bx001\", \"==?\" , \"1\"],\n\t\t[\"4'b1001\", \"4'bx001\", \"!=?\" , \"0\"],\n\t\t[\"4'bz001\", \"4'bx001\", \"!=?\" , \"0\"],\n\t\t[\"4'bz001\", \"4'b1001\", \"!=?\" , \"x\"]\n\t]\n}\n"
  },
  {
    "path": "conf/lrm.conf",
    "content": "# vim: noet tabstop=64\n#\n# input database for the report generator\n# syntax:\n# <TAG NAME><tab><TAG DESCRIPTION>[<tab><TAG URL>]\n#\nsanity\tVarious sanity checks\nveer-eh1\tVeeR EH1 RISC-V core\thttps://github.com/chipsalliance/Cores-VeeR-EH1\nveer-el2\tVeeR EL2 RISC-V core\thttps://github.com/chipsalliance/Cores-VeeR-EL2\nibex\tIbex RISC-V core\thttps://github.com/lowRISC/ibex\nfx68k\tFX68K m68k core\thttps://github.com/ijor/fx68k\nyosys\tTests imported from Yosys\thttps://github.com/YosysHQ/yosys/tree/master/tests/hana\nhdlconv\tTests imported from hdlConvertor\thttps://github.com/Nic30/hdlConvertor/tree/master/tests\nhdlconv_std2012\tTests imported from hdlConvertor (std2012)\thttps://github.com/Nic30/hdlConvertor/tree/master/tests\nhdlconv_std2017\tTests imported from hdlConvertor (std2017)\thttps://github.com/Nic30/hdlConvertor/tree/master/tests\nutd-sv\tTests imported from utd-SystemVerilog\thttps://github.com/SymbiFlow/utd-sv\nuvm\tTests imported from UVM\thttps://github.com/SymbiFlow/uvm\nuvm-req\tUVM Prerequisites\nuvm-assertions\tUVM tests using assertions\nuvm-scoreboards\tuvm_scoreboard examples\nuvm-agents\tuvm_agent examples\nuvm-classes\tParticular UVM classes\nbasejump\tTests imported from Basejump STL\thttps://github.com/bespoke-silicon-group/basejump_stl\nariane\tAriane RISC-V core\thttps://github.com/openhwgroup/cva6\nscr1\tSCR1 RISC-V core\thttps://github.com/syntacore/scr1\ntaiga\tTaiga RISC-V core\thttps://gitlab.com/sfu-rcl/Taiga\nblack-parrot\tBlackParrot RISC-V core\thttps://github.com/black-parrot/black-parrot\nrsd\tRSD RISC-V core\thttps://github.com/rsd-devel/rsd\nivtest\tTests imported from ivtest\thttps://github.com/steveicarus/iverilog/tree/master/ivtest\nRgGen\tRgGen code generator for configuration and status registers\thttps://github.com/rggen/rggen\nTNoC\tNoC router and fabric\thttps://github.com/taichi-ishitani/tnoc\n5\tLexical conventions\n5.1\tGeneral\n5.2\tLexical tokens\n5.3\tWhite space\n5.4\tComments\n5.5\tOperators\n5.6\tIdentifiers, keywords, and system names\n5.6.1\tEscaped identifiers\n5.6.2\tKeywords\n5.6.3\tSystem tasks and system functions\n5.6.4\tCompiler directives\n5.7\tNumbers\n5.7.1\tInteger literal constants\n5.7.2\tReal literal constants\n5.8\tTime literals\n5.9\tString literals\n5.9.1\tSpecial characters in strings\n5.10\tStructure literals\n5.11\tArray literals\n5.12\tAttributes\n5.13\tBuilt-in methods\n6\tData types\n6.1\tGeneral\n6.2\tData types and data objects\n6.3\tValue set\n6.3.1\tLogic values\n6.3.2\tStrengths\n6.3.2.1\tCharge strength\n6.3.2.2\tDrive strength\n6.4\tSingular and aggregate types\n6.5\tNets and variables\n6.6\tNet types\n6.6.1\tWire and tri nets\n6.6.2\tUnresolved nets\n6.6.3\tWired nets\n6.6.4\tTrireg net\n6.6.4.1\tCapacitive networks\n6.6.4.2\tIdeal capacitive state and charge decay\n6.6.5\tTri0 and tri1 nets\n6.6.6\tSupply nets\n6.6.7\tUser-defined nettypes\n6.6.8\tGeneric interconnect\n6.7\tNet declarations\n6.7.1\tNet declarations with built-in net types\n6.7.2\tNet declarations with user-defined nettypes\n6.7.3\tInitialization of nets with user-defined nettypes\n6.8\tVariable declarations\n6.9\tVector declarations\n6.9.1\tSpecifying vectors\n6.9.2\tVector net accessibility\n6.10\tImplicit declarations\n6.11\tInteger data types\n6.11.1\tIntegral types\n6.11.2\t2-state (two-value) and 4-state (four-value) data types\n6.11.3\tSigned and unsigned integer types\n6.12\tReal, shortreal, and realtime data types\n6.12.1\tOperators and real numbers\n6.12.2\tConversion\n6.13\tVoid data type\n6.14\tChandle data type\n6.15\tClass\n6.16\tString data type\n6.16.1\tLen()\n6.16.2\tPutc()\n6.16.3\tGetc()\n6.16.4\tToupper()\n6.16.5\tTolower()\n6.16.6\tCompare()\n6.16.7\tIcompare()\n6.16.8\tSubstr()\n6.16.9\tAtoi(), atohex(), atooct(), atobin()\n6.16.10\tAtoreal()\n6.16.11\tItoa()\n6.16.12\tHextoa()\n6.16.13\tOcttoa()\n6.16.14\tBintoa()\n6.16.15\tRealtoa()\n6.17\tEvent data type\n6.18\tUser-defined types\n6.19\tEnumerations\n6.19.1\tDefining new data types as enumerated types\n6.19.2\tEnumerated type ranges\n6.19.3\tType checking\n6.19.4\tEnumerated types in numerical expressions\n6.19.5\tEnumerated type methods\n6.19.5.1\tFirst()\n6.19.5.2\tLast()\n6.19.5.3\tNext()\n6.19.5.4\tPrev()\n6.19.5.5\tNum()\n6.19.5.6\tName()\n6.19.5.7\tUsing enumerated type methods\n6.20\tConstants\n6.20.1\tParameter declaration syntax\n6.20.2\tValue parameters\n6.20.2.1\t$ as a parameter value\n6.20.3\tType parameters\n6.20.4\tLocal parameters (localparam)\n6.20.5\tSpecify parameters\n6.20.6\tConst constants\n6.21\tScope and lifetime\n6.22\tType compatibility\n6.22.1\tMatching types\n6.22.2\tEquivalent types\n6.22.3\tAssignment compatible\n6.22.4\tCast compatible\n6.22.5\tType incompatible\n6.22.6\tMatching nettypes\n6.23\tType operator\n6.24\tCasting\n6.24.1\tCast operator\n6.24.2\t$cast dynamic casting\n6.24.3\tBit-stream casting\n6.25\tParameterized data types\n7\tAggregate data types\n7.1\tGeneral\n7.2\tStructures\n7.2.1\tPacked structures\n7.2.2\tAssigning to structures\n7.3\tUnions\n7.3.1\tPacked unions\n7.3.2\tTagged unions\n7.4\tPacked and unpacked arrays\n7.4.1\tPacked arrays\n7.4.2\tUnpacked arrays\n7.4.3\tOperations on arrays\n7.4.4\tMemories\n7.4.5\tMultidimensional arrays\n7.4.6\tIndexing and slicing of arrays\n7.5\tDynamic arrays\n7.5.1\tNew[ ]\n7.5.2\tSize()\n7.5.3\tDelete()\n7.6\tArray assignments\n7.7\tArrays as arguments to subroutines\n7.8\tAssociative arrays\n7.8.1\tWildcard index type\n7.8.2\tString index\n7.8.3\tClass index\n7.8.4\tIntegral index\n7.8.5\tOther user-defined types\n7.8.6\tAccessing invalid indices\n7.8.7\tAllocating associative array elements\n7.9\tAssociative array methods\n7.9.1\tNum() and size()\n7.9.2\tDelete()\n7.9.3\tExists()\n7.9.4\tFirst()\n7.9.5\tLast()\n7.9.6\tNext()\n7.9.7\tPrev()\n7.9.8\tArguments to traversal methods\n7.9.9\tAssociative array assignment\n7.9.10\tAssociative array arguments\n7.9.11\tAssociative array literals\n7.10\tQueues\n7.10.1\tQueue operators\n7.10.2\tQueue methods\n7.10.2.1\tSize()\n7.10.2.2\tInsert()\n7.10.2.3\tDelete()\n7.10.2.4\tPop_front()\n7.10.2.5\tPop_back()\n7.10.2.6\tPush_front()\n7.10.2.7\tPush_back()\n7.10.3\tPersistence of references to elements of a queue\n7.10.4\tUpdating a queue using assignment and unpacked array concatenation\n7.10.5\tBounded queues\n7.11\tArray querying functions\n7.12\tArray manipulation methods\n7.12.1\tArray locator methods\n7.12.2\tArray ordering methods\n7.12.3\tArray reduction methods\n7.12.4\tIterator index querying\n8\tClasses\n8.1\tGeneral\n8.2\tOverview\n8.3\tSyntax\n8.4\tObjects (class instance)\n8.5\tObject properties and object parameter data\n8.6\tObject methods\n8.7\tConstructors\n8.8\tTyped constructor calls\n8.9\tStatic class properties\n8.10\tStatic methods\n8.11\tThis\n8.12\tAssignment, renaming, and copying\n8.13\tInheritance and subclasses\n8.14\tOverridden members\n8.15\tSuper\n8.16\tCasting\n8.17\tChaining constructors\n8.18\tData hiding and encapsulation\n8.19\tConstant class properties\n8.20\tVirtual methods\n8.21\tAbstract classes and pure virtual methods\n8.22\tPolymorphism: dynamic method lookup\n8.23\tClass scope resolution operator ::\n8.24\tOut-of-block declarations\n8.25\tParameterized classes\n8.25.1\tClass scope resolution operator for parameterized classes\n8.26\tInterface classes\n8.26.1\tInterface class syntax\n8.26.2\tExtends versus implements\n8.26.3\tType access\n8.26.4\tType usage restrictions\n8.26.5\tCasting and object reference assignment\n8.26.6\tName conflicts and resolution\n8.26.6.1\tMethod name conflict resolution\n8.26.6.2\tParameter and type declaration inheritance conflicts and resolution\n8.26.6.3\tDiamond relationship\n8.26.7\tPartial implementation\n8.26.8\tMethod default argument values\n8.26.9\tConstraint blocks, covergroups, and randomization\n8.27\tTypedef class\n8.28\tClasses and structures\n8.29\tMemory management\n9\tProcesses\n9.1\tGeneral\n9.2\tStructured procedures\n9.2.1\tInitial procedures\n9.2.2\tAlways procedures\n9.2.2.1\tGeneral purpose always procedure\n9.2.2.2\tCombinational logic always_comb procedure\n9.2.2.2.1\tImplicit always_comb sensitivities\n9.2.2.2.2\talways_comb compared to always @*\n9.2.2.3\tLatched logic always_latch procedure\n9.2.2.4\tSequential logic always_ff procedure\n9.2.3\tFinal procedures\n9.3\tBlock statements\n9.3.1\tSequential blocks\n9.3.2\tParallel blocks\n9.3.3\tStatement block start and finish times\n9.3.4\tBlock names\n9.3.5\tStatement labels\n9.4\tProcedural timing controls\n9.4.1\tDelay control\n9.4.2\tEvent control\n9.4.2.1\tEvent OR operator\n9.4.2.2\tImplicit event_expression list\n9.4.2.3\tConditional event controls\n9.4.2.4\tSequence events\n9.4.3\tLevel-sensitive event control\n9.4.4\tLevel-sensitive sequence controls\n9.4.5\tIntra-assignment timing controls\n9.5\tProcess execution threads\n9.6\tProcess control\n9.6.1\tWait fork statement\n9.6.2\tDisable statement\n9.6.3\tDisable fork statement\n9.7\tFine-grain process control\n10.3\tContinuous assignments\n10.3.1\tThe net declaration assignment\n10.3.2\tThe continuous assignment statement\n10.3.3\tContinuous assignment delays\n10.3.4\tContinuous assignment strengths\n10.4.1\tBlocking procedural assignments\n10.4.2\tNonblocking procedural assignments\n10.6.1\tThe assign and deassign procedural statements\n10.6.2\tThe force and release procedural statements\n11\tOperators and expressions\n11.1\tGeneral\n11.2\tOverview\n11.2.1\tConstant expressions\n11.2.2\tAggregate expressions\n11.3\tOperators\n11.3.1\tOperators with real operands\n11.3.2\tOperator precedence\n11.3.3\tUsing integer literals in expressions\n11.3.4\tOperations on logic (4-state) and bit (2-state) types\n11.3.5\tOperator expression short circuiting\n11.3.6\tAssignment within an expression\n11.4\tOperator descriptions\n11.4.1\tAssignment operators\n11.4.2\tIncrement and decrement operators\n11.4.3\tArithmetic operators\n11.4.3.1\tArithmetic expressions with unsigned and signed types\n11.4.4\tRelational operators\n11.4.5\tEquality operators\n11.4.6\tWildcard equality operators\n11.4.7\tLogical operators\n11.4.8\tBitwise operators\n11.4.9\tReduction operators\n11.4.10\tShift operators\n11.4.11\tConditional operator\n11.4.12\tConcatenation operators\n11.4.12.1\tReplication operator\n11.4.12.2\tString concatenation\n11.4.13\tSet membership operator\n11.4.14\tStreaming operators (pack/unpack)\n11.4.14.1\tConcatenation of stream_expressions\n11.4.14.2\tRe-ordering of the generic stream\n11.4.14.3\tStreaming concatenation as an assignment target (unpack)\n11.4.14.4\tStreaming dynamically sized data\n11.5\tOperands\n11.5.1\tVector bit-select and part-select addressing\n11.5.2\tArray and memory addressing\n11.5.3\tLongest static prefix\n11.6\tExpression bit lengths\n11.6.1\tRules for expression bit lengths\n11.6.2\tExample of expression bit-length problem\n11.6.3\tExample of self-determined expressions\n11.7\tSigned expressions\n11.8\tExpression evaluation rules\n11.8.1\tRules for expression types\n11.8.2\tSteps for evaluating an expression\n11.8.3\tSteps for evaluating an assignment\n11.8.4\tHandling X and Z in signed expressions\n11.9\tTagged union expressions and member access\n11.10\tString literal expressions\n11.10.1\tString literal operations\n11.10.2\tString literal value padding and potential problems\n11.10.3\tEmpty string literal handling\n11.11\tMinimum, typical, and maximum delay expressions\n11.12\tLet construct\n12\tProcedural programming statements\n12.1\tGeneral\n12.2\tOverview\n12.3\tSyntax\n12.4\tConditional if-else statement\n12.4.1\tif-else-if construct\n12.4.2\tunique-if, unique0-if, and priority-if\n12.4.2.1\tViolation reports generated by unique-if, unique0-if, and priority-if constructs\n12.4.2.2\tIf statement violation reports and multiple processes\n12.5\tCase statement\n12.5.1\tCase statement with do-not-cares\n12.5.2\tConstant expression in case statement\n12.5.3\tunique-case, unique0-case, and priority-case\n12.5.3.1\tViolation reports generated by unique-case, unique0-case, and priority-case constructs\n12.5.3.2\tCase statement violation reports and multiple processes\n12.5.4\tSet membership case statement\n12.6\tPattern matching conditional statements\n12.6.1\tPattern matching in case statements\n12.6.2\tPattern matching in if statements\n12.6.3\tPattern matching in conditional expressions\n12.7\tLoop statements\n12.7.1\tThe for-loop\n12.7.2\tThe repeat loop\n12.7.3\tThe foreach-loop\n12.7.4\tThe while-loop\n12.7.5\tThe do...while-loop\n12.7.6\tThe forever-loop\n12.8\tJump statements\n13.3\tTasks\n13.3.1\tStatic and automatic tasks\n13.4\tFunctions\n13.4.1\tReturn values and void functions\n13.4.2\tStatic and automatic functions\n13.4.3\tConstant functions\n13.4.4\tBackground processes spawned by function calls\n14.3\tClocking block declaration\n15.4\tMailboxes\n15.5\tNamed Events\n16.2\tOverview\n16.4\tDeferred assertions\n16.7\tSequences\n16.9\tSequence operations\n16.10\tLocal variables\n16.12\tDeclaring properties\n16.14\tConcurrent assertions\n16.15\tDisable iff resolution\n16.17\tExpect statement\n18.4\tRandom variables\n18.4.1\tRand modifier\n18.4.2\tRandc modifier\n18.5\tConstraint blocks\n18.5.1\tExternal constraint blocks\n18.5.2\tConstraint inheritance\n18.5.3\tSet membership\n18.5.4\tDistribution\n18.5.5\tUniqueness constraints\n18.5.6\tImplication\n18.5.7\tif–else constraints\n18.5.8\tIterative constraints\n18.5.8.1\tforeach iterative constraints\n18.5.8.2\tArray reduction iterative constraints\n18.5.9\tGlobal constraints\n18.5.10\tVariable ordering\n18.5.11\tStatic constraint blocks\n18.5.12\tFunctions in constraints\n18.5.13\tConstraint guards\n18.5.14\tSoft constraints\n18.5.14.1\tSoft constraint priorities\n18.5.14.2\tDiscarding soft constraints\n18.6\tRandomization methods\n18.6.1\tRandomize()\n18.6.2\tPre_randomize() and post_randomize()\n18.6.3\tBehavior of randomization methods\n18.7\tIn-line constraints—randomize() with\n18.7.1\tlocal:: scope resolution\n18.8\tDisabling random variables with rand_mode()\n18.9\tControlling constraints with constraint_mode()\n18.10\tDynamic constraint modification\n18.11\tIn-line random variable control\n18.11.1\tIn-line constraint checker\n18.12\tRandomization of scope variables—std::randomize()\n18.12.1\tAdding constraints to scope variables—std::randomize() with\n18.13\tRandom number system functions and methods\n18.13.1\t$urandom\n18.13.2\t$urandom_range()\n18.13.3\tsrandom()\n18.13.4\tget_randstate()\n18.13.5\tset_randstate()\n18.14\tRandom stability\n18.14.1\tRandom stability properties\n18.14.2\tThread stability\n18.14.3\tObject stability\n18.15\tManually seeding randomize\n18.16\tRandom weighted case—randcase\n18.17\tRandom sequence generation—randsequence\n18.17.1\tRandom production weights\n18.17.2\tif–else production statements\n18.17.3\tCase production statements\n18.17.4\tRepeat production statements\n18.17.5\tInterleaving productions—rand join\n18.17.6\tAborting productions—break and return\n18.17.7\tValue passing between productions\n20.2\tSimulation control system tasks\n20.3\tSimulation time system functions\n20.4\tTimescale system tasks\n20.5\tConversion functions\n20.6\tData query functions\n20.7\tArray query functions\n20.8\tMath functions\n20.9\tBit vector system functions\n20.10\tSeverity tasks\n20.11\tElaboration system tasks\n20.13\tSampled value system functions\n20.14\tCoverage system functions\n20.15\tProbabilistic distribution functions\n21.2\tDisplay system tasks\n21.3\tFile input/output system tasks and system functions\n21.4\tLoading memory array data from a file\n21.6\tCommand line input\n21.7\tValue change dump (VCD) files\n23.2\tModule definitions\n22\tCompiler directives\n22.1\tGeneral\n22.2\tOverview\n22.3\tresetall\n22.4\tinclude\n22.5\tdefine, undef and undefineall\n22.5.1\tdefine\n22.5.2\tundef\n22.5.3\tundefineall\n22.6\tifdef, else, elsif, endif, ifndef\n22.7\ttimescale\n22.8\tdefault_nettype\n22.9\tunconnected_drive and nounconnected_drive\n22.10\tcelldefine and endcelldefine\n22.11\tpragma\n22.12\tline\n22.13\t__FILE__ and __LINE__\n24.3\tThe program construct\n25.3\tInterface syntax\n26.2\tPackage declarations\n26.3\tReferencing data in packages\n"
  },
  {
    "path": "conf/meta-tags.conf",
    "content": "# vim: noet tabstop=16\n#\n# meta-tags configuration file\n# syntax:\n# <META TAG NAME><tab><SPACE SEPARATED DEPENDENCY TAGS>\n#\nuvm-req\t5.4 5.5 5.6 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.2 6.23 6.24 6.3 6.6 6.9 7.1 7.11 7.2 7.5 8.1 8.11 8.13 8.15 8.16 8.2 8.21 8.23 8.26 8.3 8.7 9.2 9.3 9.4 9.6 9.7 10.11 10.3 10.4 10.6 11.12 11.3 12.4 12.5 12.6 12.7 12.8 13.3 13.4 14.11 15.3 15.4 15.5 16.12 16.17 16.2 16.8 16.9 17.2 20.15 20.2 20.3 20.4 20.5 20.6 20.7 20.9 21.2 21.3 21.6 22.13 22.4 22.5 22.6 22.7 23.2 24.3 25.3 26.2 26.3\n"
  },
  {
    "path": "conf/report/code-template.html",
    "content": "<!DOCTYPE html>\n<html>\n  <head>\n    <meta charset=\"UTF-8\" />\n    <link rel=\"stylesheet\" type=\"text/css\" href=\"{{csspath}}\">\n  </head>\n  <body>  \n    <header id=\"header_code\"><h2>{{filename|e}}</h2></header>  \n    {{ code }}\n  </body>\n</html>\n"
  },
  {
    "path": "conf/report/code.css",
    "content": "@import 'details-view.css';\n\n:root {\n  font-family: \"Courier New\", Consolas, monospace;\n}\npre {\n  margin: 0; padding: 4px;\n}\n\n.highlight .hll { background-color: #ffffcc }\n.highlight .c { color: #228B22 } /* Comment */\n.highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */\n.highlight .k { color: #8B008B; font-weight: bold } /* Keyword */\n.highlight .cm { color: #228B22 } /* Comment.Multiline */\n.highlight .cp { color: #1e889b } /* Comment.Preproc */\n.highlight .c1 { color: #228B22 } /* Comment.Single */\n.highlight .cs { color: #8B008B; font-weight: bold } /* Comment.Special */\n.highlight .gd { color: #aa0000 } /* Generic.Deleted */\n.highlight .ge { font-style: italic } /* Generic.Emph */\n.highlight .gr { color: #aa0000 } /* Generic.Error */\n.highlight .gh { color: #000080; font-weight: bold } /* Generic.Heading */\n.highlight .gi { color: #00aa00 } /* Generic.Inserted */\n.highlight .go { color: #888888 } /* Generic.Output */\n.highlight .gp { color: #555555 } /* Generic.Prompt */\n.highlight .gs { font-weight: bold } /* Generic.Strong */\n.highlight .gu { color: #800080; font-weight: bold } /* Generic.Subheading */\n.highlight .gt { color: #aa0000 } /* Generic.Traceback */\n.highlight .kc { color: #8B008B; font-weight: bold } /* Keyword.Constant */\n.highlight .kd { color: #8B008B; font-weight: bold } /* Keyword.Declaration */\n.highlight .kn { color: #8B008B; font-weight: bold } /* Keyword.Namespace */\n.highlight .kp { color: #8B008B; font-weight: bold } /* Keyword.Pseudo */\n.highlight .kr { color: #8B008B; font-weight: bold } /* Keyword.Reserved */\n.highlight .kt { color: #a7a7a7; font-weight: bold } /* Keyword.Type */\n.highlight .m { color: #B452CD } /* Literal.Number */\n.highlight .s { color: #CD5555 } /* Literal.String */\n.highlight .na { color: #658b00 } /* Name.Attribute */\n.highlight .nb { color: #658b00 } /* Name.Builtin */\n.highlight .nc { color: #008b45; font-weight: bold } /* Name.Class */\n.highlight .no { color: #00688B } /* Name.Constant */\n.highlight .nd { color: #707a7c } /* Name.Decorator */\n.highlight .ne { color: #008b45; font-weight: bold } /* Name.Exception */\n.highlight .nf { color: #008b45 } /* Name.Function */\n.highlight .nn { color: #008b45; text-decoration: underline } /* Name.Namespace */\n.highlight .nt { color: #8B008B; font-weight: bold } /* Name.Tag */\n.highlight .nv { color: #00688B } /* Name.Variable */\n.highlight .ow { color: #8B008B } /* Operator.Word */\n.highlight .w { color: #bbbbbb } /* Text.Whitespace */\n.highlight .mf { color: #B452CD } /* Literal.Number.Float */\n.highlight .mh { color: #B452CD } /* Literal.Number.Hex */\n.highlight .mi { color: #B452CD } /* Literal.Number.Integer */\n.highlight .mo { color: #B452CD } /* Literal.Number.Oct */\n.highlight .sb { color: #CD5555 } /* Literal.String.Backtick */\n.highlight .sc { color: #CD5555 } /* Literal.String.Char */\n.highlight .sd { color: #CD5555 } /* Literal.String.Doc */\n.highlight .s2 { color: #CD5555 } /* Literal.String.Double */\n.highlight .se { color: #CD5555 } /* Literal.String.Escape */\n.highlight .sh { color: #1c7e71; font-style: italic } /* Literal.String.Heredoc */\n.highlight .si { color: #CD5555 } /* Literal.String.Interpol */\n.highlight .sx { color: #cb6c20 } /* Literal.String.Other */\n.highlight .sr { color: #1c7e71 } /* Literal.String.Regex */\n.highlight .s1 { color: #CD5555 } /* Literal.String.Single */\n.highlight .ss { color: #CD5555 } /* Literal.String.Symbol */\n.highlight .bp { color: #658b00 } /* Name.Builtin.Pseudo */\n.highlight .vc { color: #00688B } /* Name.Variable.Class */\n.highlight .vg { color: #00688B } /* Name.Variable.Global */\n.highlight .vi { color: #00688B } /* Name.Variable.Instance */\n.highlight .il { color: #B452CD } /* Literal.Number.Integer.Long */\n\n.highlight pre {\n  margin: 0;\n}\n\n#header_code {\n  position:sticky;\n  left: 0;\n  top: 0;\n  width: calc(100vw - 13px);\n}\n\n.linenodiv a {\n  color: #000000;\n  text-decoration: none;\n}\n\n.linenodiv a:hover {\n  text-decoration: underline;\n}\n"
  },
  {
    "path": "conf/report/details-view.css",
    "content": ":root {\n  font-family: sans-serif;\n  font-size: 0.8rem;\n}\n\n* {\n  box-sizing: border-box;\n}\n\nbody {\n  margin: 0;\n  padding: 0;\n  width: 100%;\n  min-width: min-content;\n}\n\nheader {\n  width: 100%;\n  height: 50px;\n  background-color: #666; color: #fff;\n  font-family: sans-serif;\n  line-height: 1.4rem;\n  padding-left: 20px;\n  margin: 0;\n  display: flex;\n  align-items: center;\n  gap: 0;\n  justify-content: stretch;\n  justify-items: stretch;\n}\n\nh1 {\n  font-size: 1em;\n  margin: 0;\n  padding: 4px;\n  text-decoration: inherit;\n  font-weight: bold;\n  text-transform: uppercase;\n}\n\nh2 {\n  font-size: inherit;\n  margin: 0;\n  padding: 4px;\n  color: inherit;\n  font-weight: normal;\n}\n\nheader a {\n  color: inherit;\n  text-decoration: underline;\n  text-underline-position: under;\n  text-decoration-color: #fff4;\n}\n\nheader a:hover {\n  background-color: #0004;\n}\n\npre, code {\n  font-family: \"Courier New\", Consolas, monospace;\n}"
  },
  {
    "path": "conf/report/filter.js",
    "content": "// NOTE: Code here uses classes and functions from report.js\n\nconst HEADER_COLUMNS_COUNT = 2\n\n/// Filter state manager ///////////////////////////////////////////////\n\nconst filter_state = new StateManager({\n  hidden_column_ids: {\n    initial: [],\n    validator: (v) => Array.isArray(v),\n  },\n  row_filter_func: {\n    initial: null,\n    validator: (v) => (typeof v === \"function\" || v === null)\n  },\n  cell_filter_func: {\n    initial: null,\n    validator: (v) => (typeof v === \"function\" || v === null)\n  },\n\n  tool_filter: {\n    initial: TOOL_NAMES.map((v) => v.toLowerCase()).sort(),\n    validator: (v) => (Array.isArray(v) && v.every((v) => is_string(v))),\n  },\n  applied_tool_filter: {\n    initial: TOOL_NAMES.map((v) => v.toLowerCase()).sort(),\n    validator: (v) => (Array.isArray(v) && v.every((v) => is_string(v))),\n  },\n\n  coverage_filter: {\n    initial: [\">=\", 0],\n    validator: (v) => Array.isArray(v),\n  },\n  applied_coverage_filter: {\n    initial: [\">=\", 0],\n    validator: (v) => Array.isArray(v),\n  },\n\n  type_filter: {\n    initial: [\"elaboration\", \"parsing\", \"simulation\"],\n    validator: (v) => (Array.isArray(v) && v.every((v) => is_string(v))),\n  },\n  applied_type_filter: {\n    initial: [\"elaboration\", \"parsing\", \"simulation\"],\n    validator: (v) => (Array.isArray(v) && v.every((v) => is_string(v))),\n  },\n})\n\n/// EntriesListController //////////////////////////////////////////////\n\nclass CoverageFilterEntriesController {\n  constructor(state_manager, element) {\n    this._state = state_manager\n\n    this._top = element\n    this._first_entry = this._top.querySelector(\".p_entry\")\n    this._first_operator = this._first_entry.querySelector(\".p_entry-operator\")\n    this._first_value = this._first_entry.querySelector(\".p_entry-value\");\n\n    [this._first_operator, this._first_value].forEach((element) => {\n      element.addEventListener(\"change\", this._update_state.bind(this))\n    })\n\n    this._entry_template = this._top.querySelector(\".p_entry-template\")\n    this._add_button = this._top.querySelector(\".p_add-entry-button\")\n\n    this._add_button.onclick = this._add_entry_button_clicked.bind(this)\n\n    this._state.subscribe(\n        [\"coverage_filter\"],\n        StateManager.debounce(this._state_changed.bind(this)))\n\n    this._update_state_handle = null\n  }\n\n  static _select_option(select_element, option_value) {\n    let i = 0\n    for (const child of select_element.options) {\n      if (child.value === option_value) {\n        select_element.selectedIndex = i\n        return\n      }\n      ++i\n    }\n    select_element.selectedIndex = -1\n  }\n\n  _state_changed(state, changed_values) {\n    let entries = [...this._top.querySelectorAll(\".p_entry.v_removable\")]\n    const values = state.coverage_filter\n    const expected_removable_entries_count = (values.length - 2) / 3\n\n    if (entries.length > expected_removable_entries_count) {\n      for (let i = expected_removable_entries_count; i < entries.length; ++i) {\n        entries[i].remove()\n      }\n      entries.splice(expected_removable_entries_count)\n    } else if (entries.length < expected_removable_entries_count) {\n      let last_entry = entries.length > 0 ? entries[entries.lenght-1] : this._first_entry\n      for (let i = entries.length; i < expected_removable_entries_count; ++i) {\n        const new_entry = this._create_entry()\n        last_entry.after(new_entry)\n        entries.push(new_entry)\n        last_entry = new_entry\n      }\n    }\n\n    CoverageFilterEntriesController._select_option(this._first_operator, values[0])\n    this._first_value.value = values[1]\n\n    let i = 2\n    for (const entry of entries) {\n      CoverageFilterEntriesController._select_option(entry.querySelector(\".p_entry-relation\"), values[i+0])\n      CoverageFilterEntriesController._select_option(entry.querySelector(\".p_entry-operator\"), values[i+1])\n      entry.querySelector(\".p_entry-value\").value = values[i + 2]\n      i += 3\n    }\n  }\n\n  _add_entry_button_clicked(event) {\n    const entries = this._top.querySelectorAll(\".p_entry\")\n    const last_entry = entries[entries.length - 1]\n    const new_entry = this._create_entry()\n    last_entry.after(new_entry)\n    new_entry.querySelector(\"select, input, button\").focus()\n    this._update_state()\n  }\n\n  _update_state() {\n    if (this._update_state_handle !== null)\n      clearTimeout(this._update_state_handle)\n\n    this._update_state_handle = setTimeout(() => {\n      this._update_state_handle = null\n\n      const entries = this._top.querySelectorAll(\".p_entry.v_removable\")\n      const new_state = new Array(2 + 3 * (entries.length))\n\n      new_state[0] = this._first_operator.value\n      if (this._first_value.validity.valid)\n        new_state[1] = this._first_value.valueAsNumber|0\n      else\n        new_state[1] = NaN\n\n      let i = 2\n      for (const entry of entries) {\n        new_state[i+0] = entry.querySelector(\".p_entry-relation\").value\n        new_state[i+1] = entry.querySelector(\".p_entry-operator\").value\n        const value_field = entry.querySelector(\".p_entry-value\")\n        if (value_field.validity.valid)\n          new_state[i + 2] = value_field.valueAsNumber|0\n        else\n          new_state[i + 2] = NaN\n        i += 3\n      }\n\n      this._state.state.coverage_filter = new_state\n    }, 100)\n  }\n\n  _create_entry() {\n    const entry = this._entry_template.content.firstElementChild.cloneNode(true)\n\n    entry.querySelectorAll(\"select, input\").forEach((element) => {\n      element.addEventListener(\"change\", this._update_state.bind(this))\n    })\n\n    const remove_button = entry.querySelector(\".p_remove-entry-button\")\n    remove_button.onclick = (event) => {\n      entry.remove()\n      this._update_state()\n    }\n\n    return entry\n  }\n}\n\n/// CheckboxGroupController ////////////////////////////////////////////\n\nclass CheckboxGroupController {\n  constructor(state_manager, state_key, checkbox_list) {\n    this._state = state_manager\n    this._key = state_key\n    this._checkboxes = new Map()\n    this._selections = new Set(this._state.state[this._key])\n\n    for (const checkbox of checkbox_list) {\n      this._checkboxes.set(checkbox.value, checkbox)\n      checkbox.checked = this._selections.has(checkbox.value)\n      checkbox.addEventListener(\"change\", this._checkbox_changed.bind(this))\n    }\n\n    this._state.subscribe(\n        [state_key],\n        StateManager.debounce(this._state_changed.bind(this)))\n\n    this._update_state_handle = null\n  }\n\n  _state_changed(state, changed_values) {\n    this._selections = new Set(state[this._key])\n    for (const [value, checkbox] of this._checkboxes) {\n      checkbox.checked = this._selections.has(value)\n    }\n  }\n\n  _checkbox_changed(event) {\n    const checkbox = event.target\n    if (checkbox.checked == this._selections.has(checkbox.value))\n      return\n\n    if (checkbox.checked) {\n      this._selections.add(checkbox.value)\n    } else {\n      this._selections.delete(checkbox.value)\n    }\n\n    if (this._update_state_handle === null) {\n      this._update_state_handle = setTimeout(() => {\n        this._update_state_handle = null\n        this._state.state[this._key] = [...this._selections].sort()\n      }, 0)\n    }\n  }\n}\n\n/// FilterController ///////////////////////////////////////////////////\n\nclass FilterController {\n  constructor(state_manager, elements) {\n    this._state = state_manager\n    this._apply_button = elements.apply_button\n    this._reset_button = elements.reset_button\n    this._error_label = elements.error_label\n\n    this._apply_button.onclick = this._apply_clicked.bind(this)\n    this._reset_button.onclick = this._reset_clicked.bind(this)\n\n    this._state.subscribe(\n        [\"tool_filter\", \"coverage_filter\", \"type_filter\", \"applied_tool_filter\", \"applied_coverage_filter\", \"applied_type_filter\"],\n        StateManager.debounce(this._state_changed.bind(this)))\n  }\n\n  static _is_filter_valid(key, value) {\n    const VALID_OPERATORS = new Set([\">=\", \"<=\", \">\", \"<\", \"==\"])\n    const VALID_RELATIONS = new Set([\"&&\", \"||\"])\n\n    switch (key) {\n      case \"tool_filter\":\n      case \"type_filter\":\n        return value.length > 0\n\n      case \"coverage_filter\": {\n        if (value.length < 2 || ((value.length - 2) % 3) !== 0)\n          return false\n        if (!VALID_OPERATORS.has(value[0]) || !isFinite(value[1]) || value[1] < 0 || value[1] > 100)\n          return false\n        for (let i = 2; i < value.length; i += 3) {\n          if (!VALID_RELATIONS.has(value[i+0])) return false\n          if (!VALID_OPERATORS.has(value[i+1])) return false\n          if (!isFinite(value[i+2]) || value[i+2] < 0 || value[i+2] > 100) return false\n        }\n        return true\n      }\n    }\n  }\n\n  _state_changed(state, changed_values) {\n    let apply_possible = false;\n    let reset_possible = false;\n    const ERROR_MSGS = {\n      tool_filter: \"No tool selected.\",\n      coverage_filter: \"Invalid coverage value(s).\",\n      type_filter: \"No type selected.\",\n    }\n    const ERROR_MSG_PREFIX = \"<strong>Error(s):</strong> \"\n    const errors = []\n\n    for (const key of [\"tool_filter\", \"coverage_filter\", \"type_filter\"]) {\n      if (!deep_eq(state[key], this._state.state_spec[key].initial))\n        reset_possible = true\n      if (!deep_eq(state[key], state[`applied_${key}`]))\n        apply_possible = true\n      if (!FilterController._is_filter_valid(key, state[key]))\n        errors.push(ERROR_MSGS[key])\n    }\n\n    if (errors.length > 0)\n      this._error_label.innerHTML = ERROR_MSG_PREFIX + errors.join(\" \")\n    else\n      this._error_label.innerText = \"\"\n\n    this._apply_button.disabled = (errors.length != 0) || !apply_possible;\n    this._reset_button.disabled = !reset_possible;\n  }\n\n  _apply_clicked(event) {\n    const tool_filter = this._state.state.tool_filter\n    const coverage_filter = this._state.state.coverage_filter\n    const type_filter = this._state.state.type_filter\n\n    this._state.state.applied_tool_filter = tool_filter\n    this._state.state.applied_coverage_filter = coverage_filter\n    this._state.state.applied_type_filter = type_filter\n\n    if (!(coverage_filter.length === 2 && (\n          (coverage_filter[0] === \">=\" && coverage_filter[1] === 0) ||\n          (coverage_filter[0] === \"<=\" && coverage_filter[1] === 100)\n        ))) {\n      const operator = coverage_filter[0]\n      const value = coverage_filter[1]\n      let coverage_filter_code = `(coverage ${operator} ${value})`\n      for (let i = 2; i < coverage_filter.length; i += 3) {\n        const relation = coverage_filter[i + 0]\n        const operator = coverage_filter[i + 1]\n        const value = coverage_filter[i + 2]\n        coverage_filter_code += ` ${relation} (coverage ${operator} ${value})`\n      }\n\n      const cell_filter_func_code = `(coverage) => { return (${coverage_filter_code}) }`\n      Log.dbg(\"filter\", \"Cell filter function: %o\", cell_filter_func_code)\n      const cell_filter_func = eval(cell_filter_func_code)\n      this._state.state.cell_filter_func = cell_filter_func\n    } else {\n      this._state.state.cell_filter_func = null\n    }\n\n    if (!deep_eq(type_filter, this._state.state_spec.type_filter.initial)) {\n      const type_filter_codes = []\n      for (const type of type_filter)\n        type_filter_codes.push(`(types.includes(\"${type}\"))`)\n      const type_filter_code = type_filter_codes.join(\" || \")\n\n      const row_filter_func_code = `(types) => { return (${type_filter_code}) }`\n      Log.dbg(\"filter\", \"Row filter function: %o\", row_filter_func_code)\n      const row_filter_func = eval(row_filter_func_code)\n      this._state.state.row_filter_func = row_filter_func\n    } else {\n      this._state.state.row_filter_func = null\n    }\n\n    const hidden_column_ids = []\n    let i = HEADER_COLUMNS_COUNT\n    for (const tool of TOOL_NAMES) {\n      if (!tool_filter.includes(tool.toLowerCase()))\n        hidden_column_ids.push(i)\n      ++i\n    }\n    this._state.state.hidden_column_ids = hidden_column_ids\n  }\n\n  _reset_clicked(event) {\n    for (const key of [\"tool_filter\", \"coverage_filter\", \"type_filter\"]) {\n      this._state.state[key] = this._state.state_spec[key].initial\n    }\n  }\n}\n\n/// DataTable filter function that does actual filtering ///////////////\n\n$.fn.dataTable.ext.search.push(function (settings, searchData, index, rowData, counter) {\n  if (filter_state.state.row_filter_func) {\n    const dt = settings.oInstance.DataTable();\n    const types = dt.row(index).node().dataset.types.split(\" \")\n    if (!filter_state.state.row_filter_func(types))\n      return false\n  }\n  if (filter_state.state.cell_filter_func) {\n    const hidden_column_ids = filter_state.state.hidden_column_ids\n    const cell_filter_func = filter_state.state.cell_filter_func\n    let i = 0\n    let has_matching_cell = false;\n    for (let col = HEADER_COLUMNS_COUNT; col < rowData.length; ++col) {\n      if (col === hidden_column_ids[i]) {\n        ++i\n        continue\n      }\n      const coverage = Math.round(parseSimpleFraction(rowData[col]) * 100)|0\n      if (cell_filter_func(coverage)) {\n        has_matching_cell = true\n        break\n      }\n    }\n    if (!has_matching_cell)\n      return false\n  }\n  return true\n})\n\n/// Main ///////////////////////////////////////////////////////////////\n\nwindow.addEventListener('DOMContentLoaded', function(event) {\n\n  // DataTable\n\n  $('table.dataTable').DataTable({\n    paging: false,\n    autoWidth: false,\n\n    order: [ [1, \"asc\"], ],\n    columns: [\n      { orderable: false },\n      { orderDataType: \"original-order\", type: \"num\" },\n      ...TOOL_NAMES.map(() => {\n        return {\n          orderDataType: \"simple-fraction\",\n          type: \"num\",\n        }\n      })\n    ],\n  })\n\n  // Update tables when a filter is applied\n\n  const tables = []\n  $('table.dataTable').each(function () {\n    const table = $(this).dataTable().api()\n    tables.push(table)\n\n    filter_state.subscribe(\n      [\"hidden_column_ids\", \"row_filter_func\", \"cell_filter_func\"],\n      StateManager.debounce((state, changed_values) => tables.forEach((table) => {\n        if (changed_values.has(\"hidden_column_ids\")) {\n          table.columns().visible(true)\n          table.columns(state.hidden_column_ids).visible(false)\n        }\n\n        setTimeout(()=>table.draw(), 0)\n    }), 0))\n  })\n\n  // Filter\n\n  const filter_section = document.querySelector(\"#filter-section\")\n\n  const filter_controller = new FilterController(filter_state, {\n    apply_button: document.getElementById(\"filter-apply-button\"),\n    reset_button: document.getElementById(\"filter-reset-button\"),\n    error_label: document.getElementById(\"filter-error-msg\"),\n  })\n\n  // Tool filter\n\n  const tool_filter = filter_section.querySelector(\".p_tool-filter\")\n  const tool_filter_checkboxes = tool_filter.querySelectorAll(\"input[type='checkbox']\")\n\n  tool_filter.querySelector(\".p_select-all-button\").onclick = (event) => {\n    tool_filter_checkboxes.forEach((element) => {\n      if (!element.checked) {\n        element.checked = true\n        element.dispatchEvent(new Event(\"change\"))\n      }\n    })\n  }\n  tool_filter.querySelector(\".p_invert-selection-button\").onclick = (event) => {\n    tool_filter_checkboxes.forEach((element) => {\n      element.checked = !(element.checked)\n      element.dispatchEvent(new Event(\"change\"))\n    })\n  }\n\n  const tool_filter_controls = new CheckboxGroupController(filter_state, \"tool_filter\", tool_filter_checkboxes)\n\n  // Coverage filter\n\n  const coverage_filter_controls = new CoverageFilterEntriesController(filter_state, filter_section.querySelector(\".p_coverage-filter\"));\n\n  // Type filter\n\n  const type_filter_checkboxes = document.querySelectorAll(\"#filter-section .p_type-filter input[type='checkbox']\")\n  const type_filter_controls = new CheckboxGroupController(filter_state, \"type_filter\", type_filter_checkboxes)\n})\n"
  },
  {
    "path": "conf/report/filter_ui_test.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2021 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom selenium import webdriver\nfrom selenium.webdriver.support.ui import Select\nimport sys\n\n\ndef setDriver(arg=None):\n    global driver\n    if arg is None:\n        driver = webdriver.Chrome()\n    else:\n        driver = arg\n\n\ndef openPage(URL):\n    driver.get(URL)\n    driver.implicitly_wait(10)\n    driver.find_element_by_tag_name('button').click()\n\n\ndef addEntries(iter):\n    for _ in range(iter):\n        driver.find_element_by_class_name('filter-add').click()\n\n\ndef fillEntryType(num, type):\n    entry_type = \"//*[@class='filter-entry-type']\"\n    select = Select(driver.find_elements_by_xpath(entry_type)[num])\n    select.select_by_value(type)\n\n\ndef fillSpan(entry_id, *args):\n    for i in range(len(args)):\n        entry_operator = f\"(//*[@id='filter']/ul/li[{entry_id+1}]/span/select)[{i+1}]\"\n        select = Select(driver.find_element_by_xpath(entry_operator))\n        select.select_by_value(args[i])\n\n\ndef applyFilters():\n    driver.find_element_by_class_name('filter-apply').click()\n\n\ndef removeIcon(num):\n    driver.find_elements_by_class_name('filter-clear')[num].click()\n\n\ndef removeAll():\n    driver.find_element_by_class_name('filter-remove').click()\n\n\nif __name__ == \"__main__\":\n    URL = sys.argv[1]\n    driver = setDriver(webdriver.Chrome())\n    openPage(URL)\n\n    addEntries(3)\n    fillEntryType(0, \"coverage\")\n    fillEntryType(1, \"type\")\n    fillEntryType(2, \"tool\")\n    fillSpan(0, \">\", \"50\", \"or\", \"<\", \"80\")\n    fillSpan(1, \"is\", \"preprocessing\")\n    fillSpan(2, \"is\", \"verible\", \"and\", \"is\", \"surelog\")\n    applyFilters()\n    removeIcon(2)\n    removeAll()\n"
  },
  {
    "path": "conf/report/footer.html",
    "content": "<footer>\n    <div>\n        <p>\n            Generated using <a href=\"https://github.com/chipsalliance/sv-tests\">sv-tests</a>,\n            revision: <a href=\"https://github.com/chipsalliance/sv-tests/commit/{{revision}}\">{{revision}}</a>,\n            {% if build_id != 'local' %}\n            build_id: <a href=\"{{'https://github.com/chipsalliance/sv-tests/actions/runs/' ~ build_id|string}}\">{{build_id}}</a>,\n            {% else %}\n            build_id: {{build_id}},\n            {% endif %}\n            date: {{datetime}}.\n        </p>\n    </div>\n      <div class=\"footer\">\n        <a href=\"https://www.linuxfoundation.org/\">\n            <svg width=\"219\" height=\"158\" viewBox=\"0 0 219 158\" fill=\"none\" xmlns=\"http://www.w3.org/2000/svg\">\n                <path d=\"M94.8842 57.0703H102.446V57.8342H99.1235V66.6183H98.2069V57.8342H94.8842V57.0703ZM103.363 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  },
  {
    "path": "conf/report/history-graph-template.html",
    "content": "<!DOCTYPE html>\n<html>\n<head>\n  <script src=\"https://cdn.jsdelivr.net/npm/chart.js@3.5.0/dist/chart.min.js\"></script>\n  <script src=\"https://cdn.jsdelivr.net/npm/chartjs-adapter-date-fns@2.0.0/dist/chartjs-adapter-date-fns.bundle.min.js\"></script>\n</head>\n\n<body>\n  <canvas id=\"line-chart\" width=300\" height=\"150\"></canvas>\n  <script>\n\n    function handleHover(evt, item, legend) {\n      legend.chart.data.datasets.forEach((line) => {\n        line.borderColorOrig = line.borderColor;\n        if (item.text != line.label) {\n          line.borderColor = line.borderColor + \"0c\";\n        }\n      });\n      legend.chart.update();\n    };\n    function handleLeave(evt, item, legend) {\n      legend.chart.data.datasets.forEach((line) => {\n          line.borderColor = line.borderColorOrig;\n      });\n      legend.chart.update();\n    };\n\n    new Chart(document.getElementById(\"line-chart\"), {\n      type: 'line',\n      data: {\n        labels: [ {{ labels }} ],\n        datasets: [\n          {% for tool in datasets | sort %}\n            {\n              data: [ {{ datasets[tool] }} ],\n              label: \"{{ tool }}\" ,\n              borderColor: \"{{ colors[tool] }}\",\n              stepped: true,\n              fill: false\n            },\n          {% endfor %}\n        ]\n      },\n      options: {\n        responsive: true,\n        plugins: {\n          title: {\n            display: true,\n            text: 'SV-Tests results history'\n          },\n          legend: {\n            onHover: handleHover,\n            onLeave: handleLeave\n          }\n        },\n        scales: {\n          x: {\n            display: true,\n            type: 'time',\n            title: {\n              display: true,\n              text: 'Date of the build'\n            }\n          },\n          y: {\n            display: true,\n            title: {\n              display: true,\n              text: 'Tests passed [%]'\n            },\n          }\n        }\n      },\n    });\n  </script>\n</body>\n</html>\n"
  },
  {
    "path": "conf/report/log-template.html",
    "content": "<!DOCTYPE html>\n<html>\n  <head>\n    <meta charset=\"UTF-8\" />\n    <link rel=\"stylesheet\" type=\"text/css\" href=\"{{csspath}}\">\n  </head>\n  <body>\n    <header class=\"{{result.status}}\">\n        <a href=\"{{log['runner_url']}}\" target=\"_blank\"><h1>{{log['runner']|e}}</h1></a>\n        <h2>{{result.name|e}}</h2>\n    </header>\n    <section class=\"property-list\">\n      <dl>\n        <div><dt>description</dt><dd>{{log['description']|e}}</dd></div>\n        <div><dt>rc</dt><dd>{{result.exit_code}} (means success: {{log['tool_success']|e}})</dd></div>\n        {% if should_fail_because|length %}\n        <div><dt>should_fail_because</dt><dd> {{log['should_fail_because']|e}}</dd></div>\n        {% endif %}\n        <div><dt>tags</dt><dd>{{result.tags|join(' ')|e}}</dd></div>\n        <div>\n          <dt>incdirs</dt>\n          <dd><ul>\n            {% for dir in log['incdirs'].split(' ') %}\n            <li>{{dir}}<li>\n            {% endfor %}\n          </ul></dd>\n        </div>\n        <div><dt>top module</dt><dd>{{log['top_module']|e}}</dd></div>\n        <div><dt>type</dt><dd>{{result.types|join(' ')|e}}</dd></div>\n        <div><dt>results group</dt><dd>{% if result.results_group|length %}{{result.results_group|e}}{% else %}<em></em>{% endif %}</dd></div>\n        <div><dt>mode</dt><dd>{{log['mode']|e}}</dd></div>\n        <div>\n          <dt>files</dt>\n          <dd><ul>\n            {% for f, f_html in input_files_map.items() %}\n            <li><a href=\"{{f_html}}\" target=\"file-frame\">{{f|e}}</a><li>\n            {% endfor %}\n          </ul></dd>\n        </div>\n        <div><dt>defines</dt><dd><code>{{log['defines']|e}}</code></dd></div>\n        <div><dt>completed</dt><dd>{{log['date_completed']|e}}</dd></div>\n        <div><dt>time elapsed</dt><dd>{{'%0.3f'| format(result.total_time|float)}}s</dd></div>\n        <div><dt>ram usage</dt><dd>{{'%d'| format(result.ram_usage|int)}} KB</dd></div>\n      </dl>\n    </section>\n    <section class=\"log\">\n      {% for line in content.split('\\n') %}\n      <pre>{{line}}</pre>\n      {% endfor %}\n    </section>\n  </body>\n</html>\n"
  },
  {
    "path": "conf/report/log.css",
    "content": "@import 'details-view.css';\n\n:root {\n  /* Colors */\n  --white: #FFFFFF;\n  --light-gray: #F9F9F9;\n  --gray: #E6E6E6;\n  --dark-gray: #8E8E93;\n  --black: #2C2C2E;\n  --red: #ED5545;\n  --green: #63C366;\n  --accent: #1226AA;\n  /* Padding */\n  --gap-l:30px;\n  --gap-m:20px;\n  --gap-s:10px;\n  /* Breakpoints */\n  --mobile:670px;\n  --tablet:1280px;\n  --desktop:1920px;\n}\n\nsection {\n  margin: 0;\n  padding: 4px;\n  overflow: hidden;\n  width: 100%;\n}\n\nsection.property-list.test-passed { background-color: #D7ECD4; }\nsection.property-list.test-failed { background-color: #F5CFCA; }\n\nsection.property-list a:link {\n  color: #00006f;\n}\n\nsection.property-list > dl {\n  margin: 0;\n}\n\nsection.property-list > dl > div {\n  display: block;\n  line-height: 1.2em;\n}\n\nheader.test-passed {\n  background-color: var(--green);\n  position: sticky;\n  left: 0;\n  top: 0;\n  width: calc(100vw - 15px);\n}\n\nheader.test-failed {\n  background-color: var(--red);\n  position: sticky;\n  left: 0;\n  top: 0;\n  width: calc(100vw - 15px);\n}\n\nsection.property-list > dl dt {\n  display: inline;\n  font-weight: bold;\n}\nsection.property-list > dl dt::after {\n  content: \":\";\n}\n\nsection.property-list > dl dd {\n  margin: 0 0 0 0.5em;\n  display: inline;\n}\n\nsection.property-list > dl dd ul {\n  margin: 0 0 0.5rem 1rem;\n  padding: 0;\n}\n\nsection.property-list > dl dd ul li {\n  list-style-type: none;\n}\n\nsection.log {\n  padding: 4px;\n  background-color: white;\n}\n\nsection.log > pre {\n  margin: 0;\n  padding: 0;\n  font-family: \"Courier New\", Consolas, monospace;\n}\n\n\n"
  },
  {
    "path": "conf/report/navbar.html",
    "content": "<section class=\"top-nav\">\n    <div class=\"nav-logo\">\n        <svg width=\"66\" height=\"62\" viewBox=\"0 0 66 62\" fill=\"none\" xmlns=\"http://www.w3.org/2000/svg\">\n            <path d=\"M65.3463 29.9323C65.2247 38.422 61.4477 46.7454 55.1771 52.53C48.9534 58.3713 40.3029 61.6235 31.7477 61.442C23.186 61.3222 14.8047 57.7789 8.97575 51.8959C3.09325 46.0559 -0.179302 37.9506 0.0075892 29.9323C0.138282 21.9065 3.7049 14.0621 9.63183 8.60273C15.513 3.09417 23.6735 0.0373689 31.7477 0.215105C39.8272 0.341159 47.7132 3.68411 53.2062 9.23552C58.7463 14.7567 61.8123 22.3779 61.6294 29.9323H65.3463ZM61.6294 29.9323C61.4987 22.3691 58.1333 15.005 52.5488 9.86957C46.9996 4.69254 39.3397 1.83364 31.7477 2.00759C24.1492 2.13364 16.7585 5.28499 11.604 10.5036C6.40763 15.6933 3.54545 22.8418 3.7245 29.9323C3.85519 37.0291 7.01927 43.9243 12.2601 48.7282C17.4734 53.5737 24.6367 56.2347 31.7477 56.0645C38.8639 55.9385 45.7593 52.9838 50.578 48.0941C55.4306 43.2297 58.0928 36.564 57.9125 29.9323H61.6294Z\" fill=\"#1226AA\"/>\n            <path d=\"M20.7043 26.7528C20.6095 26.9045 20.5084 27.0183 20.4009 27.0941C20.2998 27.17 20.167 27.2079 20.0027 27.2079C19.8573 27.2079 19.6992 27.1636 19.5286 27.0751C19.3642 26.9803 19.1746 26.876 18.9597 26.7622C18.7511 26.6485 18.5109 26.5473 18.239 26.4588C17.9672 26.364 17.6575 26.3166 17.3098 26.3166C16.7093 26.3166 16.2605 26.4462 15.9634 26.7054C15.6726 26.9582 15.5272 27.3027 15.5272 27.7389C15.5272 28.017 15.6157 28.2477 15.7927 28.431C15.9697 28.6144 16.2005 28.7724 16.4849 28.9051C16.7757 29.0379 17.1044 29.1612 17.471 29.2749C17.844 29.3824 18.2232 29.5057 18.6088 29.6447C18.9944 29.7775 19.3705 29.9355 19.7372 30.1188C20.1101 30.3021 20.4388 30.536 20.7233 30.8205C21.0141 31.1049 21.2479 31.4526 21.4249 31.8635C21.6019 32.268 21.6904 32.7579 21.6904 33.3332C21.6904 33.9716 21.5798 34.569 21.3586 35.1252C21.1373 35.6815 20.8149 36.1682 20.3914 36.5854C19.9742 36.9963 19.4559 37.3218 18.8364 37.5621C18.2232 37.7959 17.5247 37.9129 16.7409 37.9129C16.3111 37.9129 15.8717 37.8686 15.4229 37.7801C14.9805 37.6916 14.5506 37.5684 14.1334 37.4103C13.7162 37.246 13.3243 37.0532 12.9577 36.832C12.591 36.6107 12.2718 36.3642 12 36.0924L12.9482 34.5942C13.024 34.4868 13.122 34.3983 13.2421 34.3287C13.3685 34.2529 13.5045 34.215 13.6498 34.215C13.8395 34.215 14.0291 34.275 14.2187 34.3951C14.4147 34.5152 14.6328 34.648 14.873 34.7934C15.1195 34.9387 15.4008 35.0715 15.7169 35.1916C16.0329 35.3117 16.4059 35.3718 16.8357 35.3718C17.4173 35.3718 17.8693 35.2453 18.1916 34.9925C18.514 34.7333 18.6752 34.3256 18.6752 33.7693C18.6752 33.4469 18.5867 33.1846 18.4097 32.9823C18.2327 32.7801 17.9988 32.6125 17.7081 32.4798C17.4236 32.347 17.0981 32.2301 16.7314 32.129C16.3648 32.0278 15.9887 31.9172 15.6031 31.7971C15.2175 31.6707 14.8414 31.519 14.4748 31.342C14.1081 31.1587 13.7794 30.9216 13.4886 30.6308C13.2042 30.3337 12.9735 29.9671 12.7965 29.5309C12.6195 29.0885 12.531 28.5448 12.531 27.9001C12.531 27.3817 12.6353 26.876 12.8439 26.383C13.0525 25.8899 13.3591 25.4506 13.7636 25.065C14.1682 24.6794 14.6644 24.3728 15.2523 24.1453C15.8401 23.9114 16.5134 23.7944 17.2719 23.7944C17.6954 23.7944 18.1063 23.8292 18.5045 23.8987C18.9091 23.9619 19.2915 24.0599 19.6518 24.1927C20.0121 24.3191 20.3472 24.474 20.6569 24.6573C20.973 24.8343 21.2543 25.0366 21.5008 25.2641L20.7043 26.7528Z\" fill=\"#1226AA\"/>\n            <path d=\"M35.6498 23.9461L30.1124 37.7612H27.2109L21.6735 23.9461H24.2526C24.5307 23.9461 24.7551 24.0125 24.9258 24.1453C25.0965 24.2717 25.2261 24.436 25.3146 24.6383L27.9884 32.0341C28.1149 32.3565 28.2381 32.7105 28.3582 33.0961C28.4783 33.4754 28.5921 33.8736 28.6996 34.2908C28.7881 33.8736 28.8861 33.4754 28.9935 33.0961C29.1073 32.7105 29.2274 32.3565 29.3538 32.0341L32.0087 24.6383C32.0783 24.4613 32.2015 24.3033 32.3785 24.1642C32.5618 24.0188 32.7862 23.9461 33.0517 23.9461H35.6498Z\" fill=\"#1226AA\"/>\n            <path d=\"M35.777 30.811H40.8972V33.1814H35.777V30.811Z\" fill=\"#1226AA\"/>\n            <path d=\"M52 26.4873H48.1124V37.7612H44.9076V26.4873H41.02V23.9461H52V26.4873Z\" fill=\"#1226AA\"/>\n        </svg>     \n        <div class=\"logo-text\"><h1>SV Tests</h1></div>\n    </div>\n    <input id=\"menu-toggle\" type=\"checkbox\" />\n    <label class='menu-button-container' for=\"menu-toggle\">\n        <div class='menu-button'></div>\n    </label>\n    <ul class=\"menu\">\n        <li><a class=\"nav-link\" href=\"#report_table-\">main tests</a></li>\n        <li><a class=\"nav-link\" href=\"#report_table-cores\">cores</a></li>\n        <li><a class=\"nav-link\" href=\"#report_table-imported\">imported</a></li>\n        <li><a class=\"nav-link\" href=\"https://chipsalliance.github.io/sv-tests-results/history\">history</a></li>\n    </ul>\n</section>\n"
  },
  {
    "path": "conf/report/report-template.html",
    "content": "{# vim: set ts=2 sts=2 sw=2 et: #}\n<!DOCTYPE html>\n<html>\n   <head>\n      <meta charset=\"UTF-8\" />\n      <title>SystemVerilog Report</title>\n      <script src=\"https://ajax.googleapis.com/ajax/libs/jquery/3.4.1/jquery.min.js\"></script>\n      <script src=\"https://ajax.googleapis.com/ajax/libs/jqueryui/1.12.1/jquery-ui.min.js\"></script>\n      <link rel=\"stylesheet\" href=\"https://ajax.googleapis.com/ajax/libs/jqueryui/1.12.1/themes/smoothness/jquery-ui.css\">\n      <link rel=\"stylesheet\" type=\"text/css\" href=\"https://cdn.datatables.net/1.10.19/css/jquery.dataTables.css\">\n      <script type=\"text/javascript\" charset=\"utf8\" src=\"https://cdn.datatables.net/1.10.19/js/jquery.dataTables.min.js\"></script>\n      {# Global parameters for scripts and stylesheets #}\n      <script>\n         var TOOL_NAMES = [{{report.tools.keys()|numeric_sort|map('escape_js_str')|map('quote')|join(', ')}}];\n      </script>\n      <style>:root { --TOOLS_COUNT: {{report.tools|length}}; }</style>\n      <link rel=\"stylesheet\" type=\"text/css\" href=\"report.css\">\n      <script type=\"text/javascript\" charset=\"utf8\" src=\"report.js\"></script>\n      <script type=\"text/javascript\" charset=\"utf8\" src=\"filter.js\"></script>\n   </head>\n   <body>\n      {% include 'navbar.html' %}\n      <main>\n         <section id=\"filter-section\">\n            <details>\n               <summary>\n                  Advanced filters\n               </summary>\n               <button id=\"filter-apply-button\" class=\"v_link-button\" disabled>Apply</button>\n               <button id=\"filter-reset-button\" class=\"v_link-button\" disabled>Reset</button>\n               <span id=\"filter-error-msg\"></span>\n               <dl class=\"c_filter\">\n                  <dt>Tool</dt>\n                  <dd class=\"p_tool-filter\">\n                     <div class=\"p_checkboxes\">\n                        {% for tool, tool_info in report.tools|numeric_dictsort %}\n                        <label title=\"{{tool|escape_attr}}\"><input type=\"checkbox\" value=\"{{tool|lower|escape_attr}}\" checked>{{tool|e}}</label>\n                        {% endfor %}\n                     </div>\n                     <div class=\"p_buttons-bar\">\n                        <button class=\"p_select-all-button\">Select all</button>\n                        <button class=\"p_invert-selection-button\">Invert selection</button>\n                     </div>\n                  </dd>\n                  <dt>Coverage</dt>\n                  <dd class=\"p_coverage-filter\">\n                     <div class=\"p_entry\">\n                        <select class=\"p_entry-operator\">\n                           <option value=\"&gt;=\">&gt;=</option>\n                           <option value=\"&lt;=\">&lt;=</option>\n                           <option value=\"&gt;\">&gt;</option>\n                           <option value=\"&lt;\">&lt;</option>\n                           <option value=\"==\">==</option>\n                        </select>\n                        <input type=\"number\" min=\"0\" max=\"100\" class=\"p_entry-value\" value=\"0\"><span>%</span>\n                     </div>\n                     <template class=\"p_entry-template\">\n                        <div class=\"p_entry v_removable\">\n                           <select class=\"p_entry-relation\">\n                              <option value=\"&amp;&amp;\">and</option>\n                              <option value=\"||\">or</option>\n                           </select>\n                           <select class=\"p_entry-operator\">\n                              <option value=\"&gt;=\">&gt;=</option>\n                              <option value=\"&lt;=\">&lt;=</option>\n                              <option value=\"&gt;\">&gt;</option>\n                              <option value=\"&lt;\">&lt;</option>\n                              <option value=\"==\">==</option>\n                           </select>\n                           <input type=\"number\" min=\"0\" max=\"100\" class=\"p_entry-value\" value=\"0\"><span>%</span>\n                           <button class=\"v_link-button p_remove-entry-button\">(remove)</button>\n                        </div>\n                     </template>\n                     <button class=\"p_add-entry-button\">Add condition</button>\n                  </dd>\n                  <dt>Type</dt>\n                  <dd class=\"p_type-filter\">\n                     <div class=\"p_checkboxes\">\n                        {% for type in [\"Elaboration\", \"Parsing\", \"Simulation\"] %}\n                        <label title=\"{{type|escape_attr}}\"><input type=\"checkbox\" value=\"{{type|lower|escape_attr}}\" checked>{{type|e}}</label>\n                        {% endfor %}\n                     </div>\n                  </dd>\n               </dl>\n            </details>\n         </section>\n         {% for group, group_data in report.groups|numeric_dictsort %}\n         <table id=\"report_table-{{group}}\" class=\"dataTable\" data-group=\"{{group}}\">\n            <thead>\n               <tr>\n                  <th>\n                     <h2>{{group|e}}</h2>\n                  </th>\n                  <th></th>\n                  {% for tool, tool_info in report.tools|numeric_dictsort %}\n                  <th title=\"{{tool_info.version|escape_attr}}\" style=\"--z: {{loop.length - loop.index}}\">\n                     <a class=\"tool_link\" target=\"_blank\" href=\"{{tool_info.url}}\">{{tool|e}}</a>\n                  </th>\n                  {% endfor %}\n               </tr>\n            </thead>\n            <tbody>\n               {% for tag, tools in group_data.tags_tools|tag_dictsort %}\n               {%   set tag_info = report.tags[tag] %}\n               {%   set types_used_in_the_row = [] %}\n               {%   for tool, tool_data in tools.items() %}\n               {%     for type in tool_data.types %}\n               {%       if type not in types_used_in_the_row %}\n               {%         set _ = types_used_in_the_row.append(type) %}\n               {%       endif %}\n               {%     endfor %}\n               {%   endfor %}\n               <tr data-types=\"{{types_used_in_the_row|join(' ')}}\" data-tag=\"{{tag|lower|e}}\">\n                  <th title=\"{{tag_info.description|escape_attr}}\">\n                     {%- if tag_info.url -%}\n                     <a class=\"tag_link\" target=\"_blank\" href=\"{{tag_info.url}}\">{{tag_info.description|e}}</a>\n                     {%- else -%}\n                     {{tag_info.description|e}}\n                     {%- endif -%}\n                  </th>\n                  <th title=\"{{tag_info.description|escape_attr}}\">{{tag|e}}</th>\n                  {% for tool in report.tools|numeric_sort %}\n                  {%   set attrs = [] %}\n                  {%   if tool in tools %}\n                  {%     set tool_data = tools[tool] %}\n                  {%     set test_status = tool_data.status|string %}\n                  {%     if test_status != 'test-na' %}\n                  {%       set _ = attrs.append('class=' ~ (test_status|quote)) %}\n                  {%       set _ = attrs.append('data-tool=' ~ (tool|lower|escape_attr|quote)) %}\n                  {%       if test_status == 'test-varied' %}\n                  {%         set percentage = '%0.0f'|format(100.0 * tool_data.passed_tests / tool_data.total_tests) %}\n                  {%         set _ = attrs.append('style=\"--val: '~(percentage)~'%\"') %}\n                  {%       endif %}\n                  {%     endif %}\n                  {%   endif %}\n                  {%   if attrs|length %}\n                  <td {{attrs|join(' ')}}>{{tool_data.passed_tests}}/{{tool_data.total_tests}}</td>\n                  {%   else %}\n                  <td></td>\n                  {%   endif %}\n                  {% endfor %}\n               </tr>\n               {% endfor %}\n            </tbody>\n            <tfoot>\n               <tr>\n                  <th colspan=\"2\">Total tests passed</th>\n                  {% for tool in report.tools|numeric_sort %}\n                  {%   if tool in group_data.summaries %}\n                  {%     set tool_summary = group_data.summaries[tool] %}\n                  {%     set passed_tests = tool_summary.total_passed_tests %}\n                  {%     set total_tests = tool_summary.total_tests %}\n                  {%     set passed_tests_percentage = '%0.0f'|format(100.0 * passed_tests / total_tests) %}\n                  <td class=\"test-varied\" style=\"--val: {{passed_tests_percentage}}%\" title=\"{{tool|lower|e}} ({{passed_tests_percentage}}%)\">{{passed_tests}}/{{total_tests}}</td>\n                  {%   else %}\n                  <td></td>\n                  {%   endif %}\n                  {% endfor %}\n               </tr>\n               <tr>\n                  <th colspan=\"2\">Total tags passed</th>\n                  {% for tool in report.tools|numeric_sort %}\n                  {%   if tool in group_data.summaries %}\n                  {%     set tool_summary = group_data.summaries[tool] %}\n                  {%     set passed_tags = tool_summary.total_passed_tags %}\n                  {%     set tested_tags = tool_summary.total_tested_tags %}\n                  {%     set passed_tags_percentage = '%0.0f'|format(100.0 * passed_tags / tested_tags) %}\n                  <td class=\"test-varied\" style=\"--val: {{passed_tags_percentage}}%\" title=\"{{tool|lower|e}} ({{passed_tags_percentage}}%)\">{{passed_tags}}/{{tested_tags}}</td>\n                  {%   else %}\n                  <td></td>\n                  {%   endif %}\n                  {% endfor %}\n               </tr>\n               <tr>\n                  <th colspan=\"2\">Total time elapsed</th>\n                  {% for tool in report.tools|numeric_sort %}\n                  {%   if tool in group_data.summaries %}\n                  {%     set tool_summary = group_data.summaries[tool] %}\n                  <td title=\"{{tool|lower|e}}\">{{'%0.0f'|format(tool_summary.total_time)}}s</td>\n                  {%   else %}\n                  <td></td>\n                  {%   endif %}\n                  {% endfor %}\n               </tr>\n               <tr>\n                  <th colspan=\"2\">User time elapsed</th>\n                  {% for tool in report.tools|numeric_sort %}\n                  {%   if tool in group_data.summaries %}\n                  {%     set tool_summary = group_data.summaries[tool] %}\n                  <td title=\"{{tool|lower|e}}\">{{'%0.0f'|format(tool_summary.user_time)}}s</td>\n                  {%   else %}\n                  <td></td>\n                  {%   endif %}\n                  {% endfor %}\n               </tr>\n               <tr>\n                  <th colspan=\"2\">System time elapsed</th>\n                  {% for tool in report.tools|numeric_sort %}\n                  {%   if tool in group_data.summaries %}\n                  {%     set tool_summary = group_data.summaries[tool] %}\n                  <td title=\"{{tool|lower|e}}\">{{'%0.0f'|format(tool_summary.system_time)}}s</td>\n                  {%   else %}\n                  <td></td>\n                  {%   endif %}\n                  {% endfor %}\n               </tr>\n               <tr>\n                  <th colspan=\"2\">Maximum ram usage</th>\n                  {% for tool in report.tools|numeric_sort %}\n                  {%   if tool in group_data.summaries %}\n                  {%     set tool_summary = group_data.summaries[tool] %}\n                  <td title=\"{{tool|lower|e}}\">{{'%0.0f'|format(tool_summary.max_ram_usage)}} MB</td>\n                  {%   else %}\n                  <td></td>\n                  {%   endif %}\n                  {% endfor %}\n               </tr>\n               <tr>\n                  <th colspan=\"2\">Average throughput passed for inputs &gt; 1KiB</th>\n                  {% for tool in report.tools|numeric_sort %}\n                  {%   if tool in group_data.summaries %}\n                  {%     set tool_summary = group_data.summaries[tool] %}\n                  <td title=\"{{tool|lower|e}}\">{{'%0.0f'|format(tool_summary.passed_throughput|float)}} KiB/s</td>\n                  {%   else %}\n                  <td></td>\n                  {%   endif %}\n                  {% endfor %}\n               </tr>\n            </tfoot>\n         </table>\n         {% endfor %}\n         <section id=\"summary-section\">\n            <a href=\"report.csv\">Download a summary in csv</a>\n         </section>\n      </main>\n      {% include 'footer.html' %}\n      <div class=\"c_test-details-panel s_hidden\">\n         <div class=\"test-details\">\n            <div class=\"wrapper\"></div>\n            <h2>TEST DETAILS</h2>\n            <button class=\"p_close-button\">\n               <svg width=\"11\" height=\"11\" viewBox=\"0 0 11 11\" fill=\"none\" xmlns=\"http://www.w3.org/2000/svg\">\n               <path fill-rule=\"evenodd\" clip-rule=\"evenodd\" d=\"M3.83579 5.25L0.292893 8.79289L1.70711 10.2071L5.25 6.66421L8.79289 10.2071L10.2071 8.79289L6.66421 5.25L10.2071 1.70711L8.79289 0.292893L5.25 3.83579L1.70711 0.292893L0.292893 1.70711L3.83579 5.25Z\" fill=\"white\"/>\n               </svg>\n            </button>\n         </div> \n         <div class=\"grid-2\">\n            <iframe class=\"p_log\" name=\"log-frame\"></iframe>\n            <iframe class=\"p_file\" name=\"file-frame\"></iframe>\n         </div>\n         <div class=\"p_tests-list\">\n            <template class=\"p_item-template\">\n               <button class=\"p_item\">\n                  <slot name=\"test-name\"></slot>\n               </button>\n            </template>\n         </div>\n      </div>\n   </body>\n</html>"
  },
  {
    "path": "conf/report/report.css",
    "content": ":root {\n  /* Colors */\n  --white: #FFFFFF;\n  --light-gray: #F9F9F9;\n  --gray: #E6E6E6;\n  --dark-gray: #8E8E93;\n  --black: #2C2C2E;\n  --red: #ED5545;\n  --green: #63C366;\n  --accent: #1226AA;\n  /* Padding */\n  --gap-l:30px;\n  --gap-m:20px;\n  --gap-s:10px;\n  /* Breakpoints */\n  --mobile:670px;\n  --tablet:1280px;\n  --desktop:1920px;\n}\n\n/******** GENERAL ********/\n\n* {\n  box-sizing: border-box;\n  margin: 0px;\n}\nh1{\n  font-size: 24px;\n  font-family: 'Lato', sans-serif;\n  font-weight: 700\n}\n\nh2{\n  font-size: 15px;\n  font-family: 'Lato', sans-serif;\n  font-weight: 500;\n  padding-left: 10px;\n}\n\nh3{\n  font-size: 14px;\n  font-family: 'Roboto', sans-serif;\n  font-weight: 500;\n}\n\nh4{\n  font-size: 13px;\n  font-family: 'Roboto', sans-serif;\n}\nh5{\n  font-size: 12px;\n  font-family: 'Roboto', sans-serif;\n}\n\np{\n  font-size: 12px;\n  font-weight: 300;\n}\n\na {\n  font-size: 16px;\n  font-family: 'Roboto', sans-serif;\n  font-weight: 500;\n  color: var(--black);\n  text-decoration: underline;\n}\n\na:hover {\n  color: var(--accent);\n  transition: ease-in 0.2s;\n}\n\nbody {\n  background-color: var(--white);\n  margin: 0;\n  font-family: 'Roboto', sans-serif;\n  width: fit-content;\n  min-width: 100%;\n  font-family: sans-serif;\n  margin: 0;\n  padding: 0 0 var(--panel-height, 0) 0;\n}\n\nfooter {\n  display: flex;\n  position:sticky;\n  width: 100%;\n  margin-left: 0 !important;\n  margin-right: 0;\n  align-items: center;\n  justify-content: center;\n  font-size: 10px;\n  flex-direction: column;\n}\n\n/******** HEADER ********/\n\nheader {\n  margin-left: var(--gap-m);\n  margin-right: var(--gap-m);\n  z-index: 600;\n}\n@media only screen and (max-width: 670px) {\n  header {\n  margin-left: var(--gap-s);\n  margin-right: var(--gap-s);\n  }\n}\n\n.menu {\n  display: flex;\n  flex-direction: row;\n  list-style-type: none;\n  margin: 0;\n  padding: 0;\n}\n\n.menu > li {\n  margin: 0 1rem;\n  overflow: hidden;\n}\n\n.menu-button-container {\n  display: none;\n  height: 100%;\n  width: 30px;\n  cursor: pointer;\n  flex-direction: column;\n  justify-content: center;\n  align-items: center;\n}\n\n#menu-toggle {\n  display: none;\n}\n\n.menu-button,.menu-button::before,.menu-button::after {\n  display: block;\n  background-color: var(--black);\n  position: absolute;\n  height: 3px;\n  width: 20px;\n  transition: transform 400ms cubic-bezier(0.23, 1, 0.32, 1);\n  border-radius: 2px;\n}\n\n.menu-button::before {\n  content: '';\n  margin-top: -8px;\n}\n\n.menu-button::after {\n  content: '';\n  margin-top: 8px;\n}\n\n#menu-toggle:checked + .menu-button-container .menu-button::before {\n  margin-top: 0px;\n  transform: rotate(405deg);\n}\n\n#menu-toggle:checked + .menu-button-container .menu-button {\n  background: rgba(255, 255, 255, 0);\n}\n\n#menu-toggle:checked + .menu-button-container .menu-button::after {\n  margin-top: 0px;\n  transform: rotate(-405deg);\n}\n@media (max-width: 700px) {\n  .menu-button-container {\n  display: none;\n  }\n  .menu {\n  position: absolute;\n  top: 0;\n  margin-top: 100px;\n  left: 0;\n  flex-direction: column;\n  width: 100%;\n  justify-content: center;\n  align-items: center;\n  z-index:300;\n  }\n  #menu-toggle ~ .menu li {\n  height: 0;\n  margin: 0;\n  padding: 0;\n  border: 0;\n  transition: height 400ms cubic-bezier(0.23, 1, 0.32, 1);\n  }\n  #menu-toggle:checked ~ .menu li {\n  height: 3.5em;\n  padding: 0.5em;\n  transition: height 400ms cubic-bezier(0.23, 1, 0.32, 1);\n  }\n  .menu > li {\n  display: flex;\n  justify-content: center;\n  margin: 0;\n  padding: 0.5em 0;\n  width: 100%;\n  color: var(--black);\n  background-color: var(--white);\n  }\n  .menu > li:not(:last-child) {\n  border-bottom: 1px solid #444;\n  }\n}\n\n.top-nav {\n  display: flex;\n  position: sticky;\n  left: 0;\n  flex-direction: row;\n  align-items: center;\n  justify-content: space-between;\n  background-color: var(--white);\n  height: 100px;\n  width: calc(100vw - 30px);\n  padding: var(--gap-m);\n}\n\n.nav-logo{\n  display: flex;\n}\n\n.logo-description {\n  width: 300px;\n  font-family: 'Lato';\n  font-weight: 500;\n  font-size: 13px;\n  word-break: break-all;\n  text-decoration: none;\n}\n@media only screen and (max-width: 1200px) {\n  .logo-description {\n  display: none;\n  }\n}\n\n.logo-text {\n  margin-left: var(--gap-m);\n  display: flex;\n  flex-direction: row;\n  align-items: center;\n}\n\n.nav-link{\n  font-size: 15px;\n  font-family: 'Lato', sans-serif;\n  font-weight: 700;\n  color: var(--black);\n  text-decoration: none;\n}\n\n/******** FILTERS ********/\n\n.dataTables_filter {\n  float: none !important;\n  text-align: center;\n   display: flex;\n  justify-content: flex-end;\n  margin: var(--gap-m);\n}\n\n.dataTables_wrapper .dataTables_filter input {\n  margin-left: 0.5em;\n}\n\n#filter-section {\n  cursor:pointer;\n  color: var(--black);\n  text-decoration:none;\n  font-size: 15px;\n  font-family: \"Roboto\";\n}\n\n#filter-section > details > summary {\n  cursor:pointer;\n  color: var(--accent);\n  padding: var(--gap-m) 0;\n  font-size: 15px;\n  font-family: \"Roboto\";\n  font-weight: 600;\n  text-transform: uppercase;\n}\n\nmarker {\n  content: \"> \";\n}\n\nselect {\n  padding: var(--gap-s);\n  border-radius: 5px;\n  margin-right: 10px;\n  border: 1px solid var(--dark-gray);\n}\n\ninput[type=\"number\" i]{\n  padding: var(--gap-s);\n  border-radius: 5px;\n  border: 1px solid var(--dark-gray);\n  margin-right: 5px;\n}\n\nbutton {\n  background-color: var(--white);\n  border-radius: 5px;\n  border:1px solid var(--gray);\n  display:inline-block;\n  cursor:pointer;\n  color: var(--black);\n  padding: var(--gap-s) var(--gap-m);\n  text-decoration:none;\n  font-size: 15px;\n  font-family: \"Roboto\";\n}\n\nbutton:hover {\n  background-color: var(--accent);\n  transition: ease-in 0.2s;\n  color: var(--white);\n}\n\n.p_add-entry-button{\n  margin-top: 5px;\n}\n\ndt {\n  font-family: 'Roboto';\n  font-style: normal;\n  font-weight: 600;\n  text-transform: uppercase;\n  color: var(--dark-gray);\n  margin-bottom: 5px;\n  margin-top: 20px;\n}\n\nlabel {\n  margin-right: 10px;\n  display: block;\n}\n\n#filter-section {\n  padding: var(--gap-m);\n  border-bottom: 1px solid var(--gray);\n  border-top: 1px solid var(--gray);\n}\n\n#filter-apply-button {\n  background-color: var(--accent);\n  transition: ease-in 0.2s;\n  color: var(--white);\n}\n\n.controls{\n  display:flex;\n  margin-top: 10px;\n  justify-content:flex-end;\n}\n\n.p_checkboxes{\n  margin-bottom: 5px;\n}\n\ninput[type=\"checkbox\" i] {\n  margin-right: 5px;\n  width: 15px;\n  margin-top: 3px;\n  height: 15px;\n}\n\n#report_table-_filter > label {\n  color: var(--black);\n}\n\n#report_table-cores_filter > label {\n  color: var(--black);\n}\n\n#report_table-imported_filter > label {\n  color: var(--black);\n}\n\nform {\n  color: #555;\n  display: flex;\n  padding: 2px;\n  border: 1px solid currentColor;\n  border-radius: 5px;\n  margin: 0 0 30px;\n}\n\ninput[type=\"search\"] {\n  background: transparent;\n  height: 45px;\n  min-width: 300px;\n  max-width: 500px;\n  padding: var(--gap-s) var(--gap-s);\n  font-size: 16px;\n  border: 1px solid var(--dark-gray);\n  border-radius: 5px;\n  padding-left: 35px;\n  background: url(search.svg) no-repeat left;\n  background-size: 20px;\n  background-position: 7px;\n}\n\n/******** TABLE ********/\n\ntable.dataTable thead th, table.dataTable thead td {\n  border-bottom: none;\n}\n\ntable.dataTable {\n  width:100%;\n  overflow:auto;\n  border-collapse: collapse;\n}\n\n.dataTables_info {\n  font-size: 12px;\n  margin-top: 3px;\n  float: none !important;\n  text-align: left;\n}\n\ntable.dataTable td, table.dataTable th:nth-of-type(2) {\n  border: 1px solid var(--gray);\n}\n\ntr > th:nth-of-type(1){\n  font-family: 'Roboto', sans-serif;\n  font-weight: 500;\n  padding-left: 20px;\n  padding-right: 5px;\n  width: 260px;\n  min-width: 260px;\n  height: 60px;\n  border-bottom: 1px solid var(--gray);\n  background-color: var(--white);\n  text-align:left;\n  color: var(--black);\n}\n@media only screen and (max-width: 670px) {\n  tr > th:nth-of-type(1){\n  width: 160px;\n  min-width: 160px;\n  }\n}\n\ntr > th:nth-of-type(2){\n  font-family: 'Roboto', sans-serif;\n  font-weight: 500;\n  padding: var(--gap-s);\n  min-width:60px;\n  text-align:center;\n  color: var(--dark-gray);\n  word-break: break-word;\n  border-bottom: 1px solid var(--gray);\n}\n\ntd{\n   width:2000px; \n}\n\nth{\n   width:2000px;\n   word-break: break-word;\n}\n\nthead th {\n  height: 80px;\n   min-width: 90px;\n  background-color: var(--light-gray);\n  border-top: 1px solid var(--gray);\n  border-bottom: 1px solid var(--gray);\n}\n\ntable.dataTable > tbody > tr > td {\n  text-align: center;\n  min-width: 90px;\n  color: white;\n}\n\ntable.dataTable > tfoot > tr > td {\n  font-weight: normal !important;\n  text-align: center;\n  border: 1px solid var(--gray) !important;\n  overflow: hidden;\n  padding: 0;\n}\n\ntable.dataTable > tfoot > tr, tfoot > tr> th:nth-of-type(1) {\n  background-color: var(--light-gray);\n}\n\n@media only screen and (max-width: 670px){\n  tfoot > tr > th:nth-of-type(1) {\n  max-width: 330px;}\n}\n\ntable.dataTable, table.dataTable th, table.dataTable td {\n  box-sizing: border-box;\n}\n\n/******** TEST STATUS ********/\n\n.test-failed {\n  background-color: var(--red);\n}\n\n.test-passed {\n  background-color: var(--green);\n}\n\n.test-varied {\n  background-color: var(--red);\n  background-image:url('data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAEAAAABCAYAAAAfFcSJAAAACXBIWXMAAAsTAAALEwEAmpwYAAAAAXNSR0IArs4c6QAAAARnQU1BAACxjwv8YQUAAAAQSURBVHgBAQUA+v8AY8Nm/wWlAoycuazwAAAAAElFTkSuQmCC');\n  background-repeat:no-repeat;\n  background-size: var(--val, 100%) 100%;\n}\n\n/******** TABLE SORTING ********/\n\ntable.dataTable thead .sorting, table.dataTable thead .sorting_asc, table.dataTable thead .sorting_desc, table.dataTable thead .sorting_asc_disabled, table.dataTable thead .sorting_desc_disabled {\n  cursor: pointer;\n  background-repeat: no-repeat;\n  background-position: bottom right;\n}\n\ntable.dataTable thead .sorting {\n  background-image: url(\"sort_both.png\");\n}\ntable.dataTable thead .sorting_asc {\n  background-image: url(\"sort_asc.png\");\n}\ntable.dataTable thead .sorting_desc {\n  background-image: url(\"sort_desc.png\");\n}\n\n/******** STICKY COLUMNS ********/\n\ntable.dataTable > tbody > tr > th:nth-of-type(-n+2), table.dataTable > tfoot > tr > th:nth-of-type(-n+2) {\n  position: sticky;\n  z-index: 1;\n}\n\ntable.dataTable > * > tr > th:nth-of-type(1) {\n  left: 0;\n}\n\ntable.dataTable > * > tr > th:nth-of-type(2) {\n  left: 260px;\n  background-color: var(--white);\n  min-width: 120px;\n  width: 120px;\n  border-left: 0;\n}\n@media only screen and (max-width: 670px) {\n  table.dataTable > * > tr > th:nth-of-type(2) {\n  left: 160px;\n  min-width: 100px;\n  width: 100px;\n  }\n}\n\ntable.dataTable > thead > tr > th:nth-of-type(n+2) {\n  position: sticky;\n  z-index: calc(2 + var(--z, 0));\n  top: -1px;\n  min-width: 140px;\n}\n\ntable.dataTable thead th, table.dataTable thead td {\n  padding: 0px 5px;\n}\n\ntable.dataTable > thead > tr > th:nth-of-type(-n+2) {\n  position: sticky;\n  z-index: calc(3 + var(--TOOLS_COUNT, 100));\n  top: 0;\n  background-color: var(--light-gray);\n}\n\ntable.dataTable > tfoot > tr:nth-of-type(-n+2) > td {\n  color: white;\n  font-weight: bold;\n}\n\ntable.dataTable tbody th, table.dataTable tbody td {\n  padding: 0px 15px;\n}\n\ntable.dataTable tfoot th, table.dataTable tfoot td {\n  padding: 10px 18px 6px 15px;\n}\n\n/******** DETAILS ********/\n\n\n.c_test-details-panel .p_close-button {\n  background: var(--black);\n  float: top;\n  grid-area: \"options\";\n}\n\n\n.c_test-details-panel {\n  position: fixed;\n  bottom: 0;\n  z-index: 50;\n  width: 100%;\n  display: flex;\n  flex-direction: column;\n  align-items: stretch;\n  justify-items: stretch;\n  justify-content: stretch;\n  overflow-y: hidden;\n  overflow-x: hidden;\n  background-color: white;\n  font-family: \"Courier New\", Courier, monospace;\n  align-content: space-evenly;\n}\n@media only screen and (max-width: 1000px) {\n  .c_test-details-panel {\n  display: flex;\n  flex-direction: column;\n  }\n}\n\n.p_log {\n  width: 50vw;\n  min-height: 30vh;\n}\n@media only screen and (max-width: 1000px) {\n  .p_log {\n  width: 100vw;\n  }\n}\n\n.p_file {\n  width:50%;\n  min-height: 30vh;\n  background-color: white;\n}\n@media only screen and (max-width: 1000px) {\n  .p_file {\n  width: 100vw;\n  }\n}\n\n.test-details {\n  height: 60px;\n  background-color: var(--light-gray);\n  display: flex;\n  align-items: center;\n  flex-direction: row;\n  color: var(--dark-gray);\n  justify-content: space-between;\n  margin-left: 10px;\n  margin-right: 10px;\n}\n\n.wrapper {\n  width: 60px;\n}\n\n.grid-2{\n  display: flex;\n  flex-direction: row;\n}\n\nsection.log {\n  background-color: white;\n}\n@media only screen and (max-width: 1000px) {\n  .grid-2 {\n  display: flex;\n  flex-direction: column;\n  }\n}\n\n.c_test-details-panel.s_hidden {\n  display: none;\n}\n\n.c_test-details-panel > iframe {\n  background-color: #fff;\n  border: none;\n  height: 30vh;\n}\n\n.c_test-details-panel > .p_tests-list {\n  max-height: 20vh;\n  background-color: var(--white);\n  overflow-y: scroll;\n}\n\n.c_test-details-panel > .p_tests-list > button {\n  width: 20%;\n  height: 60px;\n  margin: 0px;\n  cursor: pointer;\n  border: 1px solid var(--white);\n  overflow:hidden;\n  text-overflow: ellipsis;\n  white-space: nowrap;\n  color: white;\n  box-sizing: border-box;\n}\n@media only screen and (max-width: 670px) {\n  .c_test-details-panel > .p_tests-list > button {\n  height: 50px;\n  width: 50%\n}\n}\n\n.c_test-details-panel > .p_tests-list > button:focus {\n  outline:0;\n}\n\n.c_test-details-panel .p_close-button {\n  background: var(--black);\n  border-radius: 25px;\n  float: top;\n  color: white;\n  padding: 12px;\n  width: 35px;\n  height: 35px;\n  display: flex;\n}\n\n.c_test-details-panel > .p_tests-list > .p_item {\n  float: left;\n  background-color: var(--red);\n}\n\n.c_test-details-panel > .p_tests-list > .p_item.s_passed {\n  background-color: var(--green);\n}\n\n.c_test-details-panel > .p_tests-list > .p_item.s_selected {\n  -webkit-box-shadow:inset 0px 0px 0px 5px var(--white);\n  -moz-box-shadow:inset 0px 0px 0px 5px var(--white);\n  box-shadow:inset 0px 0px 0px 5px var(--white);\n  filter: brightness(95%);\n  font-weight: bold;\n}\n\n.ui-widget-shadow {\n  -webkit-box-shadow: none;\n  box-shadow: none;\n}\n.ui-tooltip {\n  font-size: 13px;\n  white-space: pre-wrap;\n  max-width: 100%;\n}\n.ui-corner-all {\n  border-radius: 0px;\n}\ntable.dataTable > tbody > tr > td:not(:empty):hover {\n  cursor: pointer;\n}\ntable.dataTable > tbody > tr > td:not(:empty).s_selected {\n  -webkit-box-shadow:inset 0px 0px 0px 5px var(--gray);\n  -moz-box-shadow:inset 0px 0px 0px 5px var(--gray);\n  box-shadow:inset 0px 0px 0px 5px var(--gray);\n  filter: brightness(95%);\n  font-weight: bold;\n}\n\n/******** STICKY PAGE ********/\n\nheader, .dataTables_filter {\n  position: sticky;\n  width: calc(100vw - 30px);\n  left: 0;\n  margin-left: 0 !important;\n  margin-right: 0 !important;\n}\n\n#filter-section, .dataTables_info, #summary-section, footer {\n  position: sticky;\n  width: calc(100vw - 30px);\n  left: 10px;\n  margin-left: 0;\n  margin-right: 0;\n}\n\niframe[seamless] {\n    border: none;\n}"
  },
  {
    "path": "conf/report/report.js",
    "content": "/// Utils //////////////////////////////////////////////////////////////\n\nfunction is_string(o) { return (typeof o === \"string\" || o instanceof String) }\nfunction is_empty(str) { return str.length === 0 }\n\nfunction deep_eq(a, b) {\n  if (Array.isArray(a)) {\n    if (!Array.isArray(b) || a.length != b.length)\n      return false\n    return a.every((v, i) => deep_eq(v, b[i]))\n  } else {\n    return a === b\n  }\n}\n\nfunction parseSimpleFraction(s, for_sorting=false) {\n  try {\n    let [nom, denom] = s.split(\"/\").map((v) => parseInt(v))\n    if (for_sorting) {\n      // Add small offsets so that fractions with the same value will be\n      // sorted by denominator (e.g. 0/8 < 0/1, 1/1 < 20/20, etc).\n      nom   += 0.000001\n      denom += 0.000002\n    }\n    const value = nom / denom\n    return isFinite(value) ? value : NaN\n  } catch (e) {\n    return NaN\n  }\n}\n\nclass Log {\n  static dbg(tag, fmt, ...rest) {\n    console.debug(`%c[${tag}]%c ${fmt}`, \"text-transform:uppercase;font-weight:bold\", \"\", ...rest)\n  }\n\n  static err(tag, fmt, ...rest) {\n    console.error(`%c[${tag}]%c ${fmt}`, \"text-transform:uppercase;font-weight:bold\", \"\", ...rest)\n  }\n}\n\n/// Custom sorting for DataTable ///////////////////////////////////////\n\n// Sorts using original order of HTML table rows\n$.fn.dataTable.ext.order['original-order'] = function (settings, col) {\n  return [...Array(this.DataTable().data().length).keys()]\n}\n\n$.fn.dataTable.ext.order['simple-fraction'] = function (settings, col) {\n  return this.DataTable().data().map(function (row) {\n    const value = parseSimpleFraction(row[col], true)\n    return isFinite(value) ? value : -Infinity\n  })\n}\n\n/// ConfigLoader ///////////////////////////////////////////////////////\n\n// Global map where loaded configs put data under their individual keys.\n// The key is: \"${tool}/${tag}\", where both tool and tag are lowercase.\n// The variable is considered PRIVATE - do not use it outside of ConfigLoader.\nconfig_loader_data = {}\n\nclass ConfigLoader {\n  constructor() {\n    this._data = null\n    this._loaded_key = null\n  }\n\n  // Loads config for specified tool and tag.\n  // NOTE: do not call this concurrently multiple times.\n  async load(tool, tag) {\n    console.assert(is_string(tool) && !is_empty(tool), tool)\n    console.assert(is_string(tag) && !is_empty(tag), tag)\n\n    tool = tool.toLowerCase()\n    tag = tag.toLowerCase()\n\n    const key = `${tool}/${tag}`;\n\n    if (this._loaded_key === key) {\n      return this._data\n    }\n\n    const path = `results/${tool}/${tag}.config.js`\n\n    config_loader_data[key] = undefined\n\n    let script = document.createElement(\"script\")\n    const loading_done = new Promise((resolve, reject) => {\n      script.onload = resolve\n      script.onerror = reject\n    })\n    script.src = path\n    document.head.appendChild(script)\n    try {\n      await loading_done\n    } catch (e) {\n      Log.err(\"config\", \"Loading failed.\\n\"\n          + \"tool/tag: %o/%o\\nkey: %o\\npath: %o\\nexception: %o\", tool, tag, key, path, e)\n      return null\n    }\n    script.remove()\n\n    if (config_loader_data[key] === undefined) {\n      Log.err(\"config\", \"The loaded config script didn't assign anything to a dedicated global variable. The script probably has been generated incorrectly.\\n\"\n          + \"tool/tag: %o/%o\\nkey: %o\\npath: %o\", tool, tag, key, path)\n      return null\n    }\n\n    Log.dbg(\"config\", \"Loaded. key: %o; path: %o\", key, path)\n\n    this._loaded_key = key\n    this._data = config_loader_data[key]\n    delete config_loader_data[key]\n\n    return this._data\n  }\n\n  // Releases data. Note that The data still resides in memory if there\n  // are other references to it.\n  unload() {\n    if (this._loaded_key !== null) {\n      const key = this._loaded_key\n      this._data = null;\n      this._loaded_key = null;\n      Log.dbg(\"config\", \"Unloaded. key: %o\", key)\n    }\n  }\n\n  get data() { return this._data }\n}\n\n/// ReportViewerState //////////////////////////////////////////////////\n\nclass StateManager {\n  constructor(state_spec) {\n    this._spec = state_spec\n    Object.freeze(state_spec)\n\n    this._state = new Map()\n    this._subscribers = new Map()\n\n    for (const [key, spec] of Object.entries(state_spec)) {\n      Log.dbg(\"state/init\", \"%s: %o\", key, spec.initial)\n      this._state.set(key, spec.initial)\n      this._subscribers.set(key, new Set())\n    }\n\n    this._state_proxy = new Proxy(this._state, {\n      get: this._get_state_value.bind(this),\n      set: this._set_state_value.bind(this),\n    })\n  }\n\n  _get_state_value(state, key, proxy) {\n    console.assert(state.has(key), key)\n    return state.get(key)\n  }\n\n  _set_state_value(state, key, value, proxy) {\n    let previous_value = state.get(key)\n    if (deep_eq(value, previous_value))\n      return true\n\n    if (this._spec[key].validator) {\n      if (!this._spec[key].validator(value)) {\n        Log.err(\"state/set\", \"%s: invalid value: %o\", key, value)\n        return false\n      }\n    }\n    if (value instanceof Object)\n      Object.freeze(value)\n    state.set(key, value)\n    Log.dbg(\"state/change\", \"%s: %o → %o\", key, previous_value, value)\n    this._subscribers.get(key).forEach((callable) => callable(this._state_proxy, new Map([[key, previous_value]])))\n    return true\n  }\n\n  subscribe(keys, callable) {\n    if (callable === undefined) {\n      callable = keys\n      keys = this._subscribers.keys()\n    }\n    for (const key of keys) {\n      console.assert(this._subscribers.has(key), key)\n      this._subscribers.get(key).add(callable)\n    }\n  }\n\n  unsubscribe(keys, callable) {\n    if (callable === undefined) {\n      callable = keys\n      keys = this._subscribers.keys()\n    }\n    for (const key of keys) {\n      console.assert(this._subscribers.has(key), key)\n      this._subscribers.get(key).delete(callable)\n    }\n  }\n\n  get state() {\n    return this._state_proxy\n  }\n\n  get state_spec() {\n    return this._spec\n  }\n\n  static debounce(callable, timeout=0) {\n    function debounce_wrapper(state, changed_values) {\n      if (this.changed_values !== null) {\n        changed_values.forEach((v, k) => {\n          if (!this.changed_values.has(k)) {\n            this.changed_values.set(k, v)\n          } else if (this.changed_values.get(k) === state[k]) {\n            this.changed_values.delete(k)\n          }\n        })\n        if (this.changed_values.size === 0)\n          clearTimeout(this.handle)\n        return\n      }\n      this.changed_values = changed_values\n      this.handle = setTimeout(() => {\n        this.callable(state, this.changed_values)\n        this.changed_values = null\n      }, this.timeout)\n    }\n\n    return debounce_wrapper.bind({\n      callable: callable,\n      timeout: timeout,\n      handle: null,\n      changed_values: null,\n    })\n  }\n}\n\n/// TestDetailsPanel ///////////////////////////////////////////////////\n\nclass TestDetailsPanel {\n  constructor(state_manager, html_element) {\n    this._state = state_manager\n    this._panel = html_element\n\n    this._log = this._panel.querySelector(\".p_log\")\n    this._file = this._panel.querySelector(\".p_file\")\n    this._tests_list = this._panel.querySelector(\".p_tests-list\")\n    this._item_template = this._tests_list.querySelector(\".p_item-template\")\n    this._close_button = this._panel.querySelector(\".p_close-button\")\n\n    this._config = new ConfigLoader()\n\n    this._test_name_to_id = new Map()\n    this._items = []\n    this._selected_item = null\n    this._last_viewed_test = null\n\n    this._state.subscribe(\n        [\"tool_tag\", \"test\", \"group\"],\n        StateManager.debounce(this._state_changed.bind(this)))\n\n    this._close_button.onclick = () => this.close()\n  }\n\n  async _state_changed(state, changed_values) {\n    if (changed_values.has(\"tool_tag\") || changed_values.has(\"group\")) {\n      const [tool, tag] = state.tool_tag\n      if (tool === null || tag === null) {\n        this._unload_and_hide()\n        return\n      }\n\n      let group = state.group\n      if (group === null) {\n        console.assert(state.test !== null, state.test)\n        group = await this._find_group(tool, tag, state.test)\n        if (group !== null) {\n          state.group = group\n        } else {\n          state.tool_tag = [null, null]\n        }\n        return\n      }\n\n      await this._load_tests(tool, tag, group)\n      this._show_test(state.test)\n    } else if (changed_values.has(\"test\")) {\n      this._show_test(state.test)\n    }\n  }\n\n  async _find_group(tool, tag, test) {\n    console.assert(is_string(tool) && !is_empty(tool), tool)\n    console.assert(is_string(tag) && !is_empty(tag), tag)\n    console.assert(is_string(test) && !is_empty(test), test)\n\n    tool = tool.toLowerCase()\n    tag = tag.toLowerCase()\n\n    const config = await this._config.load(tool, tag)\n    if (config === null) {\n      Log.err(\"details panel\", \"Unknown tool/tag: %o/%o\", tool, tag)\n      return null\n    }\n\n    for (const [group, name] of config) {\n      if (name === test)\n        return group\n    }\n    return null\n  }\n\n  async _load_tests(tool, tag, group) {\n    console.assert(is_string(tool) && !is_empty(tool), tool)\n    console.assert(is_string(tag) && !is_empty(tag), tag)\n    console.assert(is_string(group), group)\n\n    tool = tool.toLowerCase()\n    tag = tag.toLowerCase()\n\n    await this._config.load(tool, tag)\n\n    this._set_selected_item(null)\n    for (const item of this._items)\n      item.remove()\n    this._items = []\n    this._test_name_to_id.clear()\n\n    let test_id = -1\n    for (const [test_group, name, status, log_url, first_input_url] of this._config.data) {\n      ++test_id\n      if (test_group !== group)\n        continue\n\n      this._test_name_to_id.set(name, test_id)\n\n      const item = this._item_template.content.firstElementChild.cloneNode(true)\n      if (status)\n        item.classList.add(\"s_passed\")\n      item.querySelector(\"slot[name='test-name']\").replaceWith(name)\n      item._test_id = test_id\n      item.onclick = this._item_clicked.bind(this)\n\n      this._tests_list.appendChild(item)\n      this._items.push(item)\n    }\n  }\n\n  _show_test(test) {\n    console.assert(this._current_tool !== null)\n    console.assert(test === null || is_string(test), test)\n\n    let test_id\n    if (!this._test_name_to_id.has(test)) {\n      if (this._test_name_to_id.has(this._last_viewed_test)) {\n        test = this._last_viewed_test\n        test_id = this._test_name_to_id.get(test)\n        Log.dbg(\"details panel\", \"Using last viewed test: %o\", test)\n      } else {\n        try {\n          // Use first available test\n          test_id = this._items[0]._test_id\n          test = this._config.data[test_id][1]\n          Log.dbg(\"details panel\", \"Using first available test: %o\", test)\n        } catch (e) {\n          Log.err(\"details panel\", \"Loaded tests list is empty.\\n\"\n            + \"tool/tag: %o/%o\", this._current_tool, this._current_test)\n          return\n        }\n      }\n      this._state.state.test = test\n    } else {\n      test_id = this._test_name_to_id.get(test)\n    }\n    const log_url = this._config.data[test_id][3]\n    const first_input_url = this._config.data[test_id][4]\n    const item = this._items.find((e) => e._test_id == test_id)\n\n    this._open_log(log_url)\n    this._open_file(first_input_url)\n    this._set_selected_item(item)\n    this._last_viewed_test = test\n\n    this._panel.classList.remove(\"s_hidden\")\n  }\n\n  _open_log(url) {\n    console.assert(is_string(url) && !is_empty(url), url)\n    this._log.contentWindow.location.replace(url);\n  }\n\n  _open_file(url) {\n    console.assert(is_string(url) && !is_empty(url), url)\n    this._file.contentWindow.location.replace(url);\n  }\n\n  _set_selected_item(item) {\n    if (this._selected_item === item)\n      return;\n\n    if (this._selected_item)\n      this._selected_item.classList.remove(\"s_selected\")\n    if (item) {\n      item.classList.add(\"s_selected\")\n      this._selected_item = item\n    } else {\n      this._selected_item = null\n    }\n  }\n\n  _item_clicked(event) {\n    const test_id = event.target._test_id\n    console.assert(test_id >= 0 || test_id < this._config.data.length, test_id)\n\n    const name = this._config.data[test_id][1]\n    const log_url = this._config.data[test_id][3]\n    const first_input_url = this._config.data[test_id][4]\n\n    this._open_log(log_url)\n    this._open_file(first_input_url)\n    this._set_selected_item(event.target)\n    this._last_viewed_test = name\n    this._state.state.test = name\n  }\n\n  _unload_and_hide() {\n    this._panel.classList.add(\"s_hidden\")\n\n    this._open_log(\"about:blank\")\n    this._open_file(\"about:blank\")\n\n    this._set_selected_item(null)\n    for (const item of this._items) {\n      item.remove()\n    }\n    this._items = []\n    this._test_name_to_id.clear()\n    this._config.unload()\n  }\n\n  close() {\n    this._unload_and_hide()\n    this._state.state.tool_tag = [null, null]\n    this._state.state.test = null\n    this._state.state.group = null\n  }\n}\n\n/// TestResultCellsSelectionController /////////////////////////////////\n\nclass TestResultCellsSelectionController {\n  constructor(state_manager, tables) {\n    this._state = state_manager\n    this._tables = tables\n\n    this._selected_cell = null;\n\n    this._state.subscribe(\n        [\"tool_tag\", \"group\"],\n        StateManager.debounce(this._state_changed.bind(this)))\n\n    for (const table of this._tables) {\n      const cells = table.querySelectorAll(\"tbody > tr > td:not(:empty)\")\n      for (const cell of cells) {\n        cell.onclick = this._cell_clicked.bind(this)\n      }\n    }\n  }\n\n  _state_changed(state, changed_values) {\n    if (changed_values.has(\"tool_tag\") || changed_values.has(\"group\")) {\n      const [tool, tag] = state.tool_tag\n      const group = state.group\n      if (this._set_selected_cell(tool, tag, group))\n        this._scroll_selected_cell_into_view()\n    }\n  }\n\n  _scroll_selected_cell_into_view() {\n    if (this._selected_cell === null)\n      return\n    const cell_to_scroll_to = this._selected_cell\n    setTimeout(() => {\n      if (cell_to_scroll_to === this._selected_cell) {\n        cell_to_scroll_to.scrollIntoView({block: \"center\", inline: \"end\"})\n      }\n    }, 250)\n  }\n\n  _set_selected_cell(tool, tag, group) {\n    if (tool === null || tag === null || group === null) {\n      this._set_selected_cell_element(null)\n      return false\n    }\n\n    tool = tool.toLowerCase()\n    tag = tag.toLowerCase()\n\n    let cell = null\n    for (const table of this._tables) {\n      if (table.dataset.group != group)\n        continue\n      cell = table.querySelector(`tbody > tr[data-tag=\"${tag}\"] > td[data-tool=\"${tool}\"]`);\n      if (cell)\n        break;\n    }\n    cell = cell ? cell : null\n    if (cell === this._selected_cell)\n      return false\n    this._set_selected_cell_element(cell)\n    return true\n  }\n\n  _set_selected_cell_element(element) {\n    if (element === this._selected_cell)\n      return;\n\n    if (this._selected_cell)\n      this._selected_cell.classList.remove(\"s_selected\")\n    if (element) {\n      Log.dbg(\"cell select\", \"%o\", element)\n      element.classList.add(\"s_selected\")\n      this._selected_cell = element\n    } else {\n      Log.dbg(\"cell select\", \"%o\", null)\n      this._selected_cell = null\n    }\n  }\n\n  _cell_clicked(event) {\n    const row_element = event.target.parentElement\n    const tbody_element = row_element.parentElement\n    const table_element = tbody_element.parentElement\n\n    const tool = event.target.dataset.tool\n    const tag = row_element.dataset.tag\n    const group = table_element.dataset.group\n\n    const [current_tool, current_tag] = this._state.state.tool_tag\n    const current_group = this._state.state.group\n\n    if (tool === current_tool && tag === current_tag && group == current_group) {\n      this._set_selected_cell_element(null)\n\n      this._state.state.tool_tag = [null, null]\n      this._state.state.test = null\n      this._state.state.group = null\n    } else {\n      this._set_selected_cell_element(event.target)\n\n      this._state.state.tool_tag = [tool, tag]\n      this._state.state.test = null\n      this._state.state.group = group\n    }\n  }\n}\n\n/// KeyboardControl ////////////////////////////////////////////////////\n\nclass KeyboardControl {\n  constructor(state_manager) {\n    this._state = state_manager\n\n    document.addEventListener(\"keydown\", this._key_pressed.bind(this))\n  }\n\n  _key_pressed(event) {\n    switch (event.key) {\n      case \"Escape\":\n      case \"Esc\":\n        this._state.state.tool_tag = [null, null]\n        this._state.state.test = null\n        this._state.state.group = null\n        break\n    }\n  }\n}\n\n/// UrlParametersController ////////////////////////////////////////////\n\nclass UrlParametersController {\n  constructor(state_manager) {\n    this._state = state_manager\n    this._update_state_from_parameters()\n    this._state.subscribe(\n        [\"tool_tag\", \"test\", \"group\"],\n        StateManager.debounce(this._state_changed.bind(this), 125))\n    window.addEventListener(\"popstate\", (event) => this._update_state_from_parameters())\n  }\n\n  _state_changed(state, changed_values) {\n    if (changed_values.has(\"tool_tag\") || changed_values.has(\"test\")) {\n      const [tool, tag] = state.tool_tag\n      const test = state.test\n\n      const url = UrlParametersController._make_url(tool, tag, test)\n      if (url.href === window.location.href)\n        return\n\n      history.pushState(null, \"\", url.href)\n      document.title = UrlParametersController._make_title(tool, tag, test)\n    }\n  }\n\n  static _make_url(tool, tag, test) {\n    const url = new URL(window.location)\n    if (tool === null || tag === null) {\n      url.hash = \"\"\n      url.searchParams.delete(\"v\")\n    } else if (test !== null) {\n      url.hash = \"\"\n      url.searchParams.set(\"v\", `${tool} ${tag} ${test}`)\n    }\n    return url\n  }\n\n  static _make_title(tool, tag, test) {\n    if (tool === null || tag === null) {\n      return `SystemVerilog Report`\n    } else if (test !== null) {\n      return `${tool}/${tag}/${test} - SystemVerilog Report`\n    }\n  }\n\n  _update_state_from_parameters() {\n    let url = new URL(window.location)\n\n    const set_state_if_valid = (tool, tag, test) => {\n      if (tool !== undefined && tool !== \"\"\n          && tag !== undefined && tag !== \"\"\n          && test !== undefined && test !== \"\") {\n        const url = UrlParametersController._make_url(tool, tag, test)\n        if (url.href !== window.location.href)\n          history.replaceState(null, \"\", url.href)\n\n        document.title = UrlParametersController._make_title(tool, tag, test)\n\n        this._state.state.tool_tag = [tool, tag]\n        this._state.state.test = test\n        this._state.state.group = null\n\n        return true\n      }\n      return false\n    }\n\n    // Try URL parameter \"v\" containing \"${TOOL} ${TAG} ${TEST}\"\n    const v = url.searchParams.get(\"v\")\n    if (is_string(v) && !is_empty(v)) {\n      const values = v.split(\" \")\n      let [tool, tag, test] = values\n      if (set_state_if_valid(tool, tag, test))\n        return\n    }\n\n    // Try URL hash containing \"#${TOOL}|${TAG}|${TEST}\" (legacy format)\n    if (is_string(url.hash) && !is_empty(url.hash)) {\n      const hash = decodeURIComponent(url.hash).substr(1)\n      const [tool, tag, test] = hash.split(\"|\")\n      if (set_state_if_valid(tool, tag, test))\n        return\n    }\n\n    // Set initial state (no selected test). Required for correct state\n    // restoration from history.\n    set_state_if_valid(null, null, null)\n  }\n}\n\n/// Main ///////////////////////////////////////////////////////////////\n\nconst state_manager = new StateManager({\n  tool_tag: {\n    initial: [null, null],\n    validator: (v) => (Array.isArray(v) && ((is_string(v[0]) && is_string(v[1])) || (v[0] === null && v[1] === null)))\n  },\n  test: {\n    initial: null,\n    validator: (v) => (is_string(v) || v === null)\n  },\n  group: {\n    initial: null,\n    validator: (v) => (is_string(v) || v === null)\n  },\n})\n\nvar test_details_panel = null;\nvar cells_selection_controller = null;\nvar keyboard_control = null;\nvar url_parameters_controller = null;\n\nwindow.addEventListener('DOMContentLoaded', function(event) {\n  const test_details_panel_element = document.querySelector(\n      \".c_test-details-panel\")\n  test_details_panel = new TestDetailsPanel(state_manager, test_details_panel_element)\n\n  const tables = document.querySelectorAll(\".dataTable\")\n  cells_selection_controller = new TestResultCellsSelectionController(state_manager, tables)\n\n  keyboard_control = new KeyboardControl(state_manager)\n  url_parameters_controller = new UrlParametersController(state_manager)\n\n  // Track panel height and store it in body's \"--panel-height\" CSS property\n  // TODO: move to a class, probably to TestDetailsPanel.\n  const panel_resize_observer = new ResizeObserver(entries => {\n    console.assert(entries.length === 1, entries)\n    const panel_entry = entries[0]\n    document.body.style.setProperty(\"--panel-height\", `${panel_entry.borderBoxSize[0].blockSize}px`)\n  })\n  state_manager.subscribe([\"tool_tag\"], StateManager.debounce((state, changed_values) => {\n    if (state.tool_tag[0] !== null) {\n      panel_resize_observer.observe(test_details_panel_element, { box: \"border-box\" })\n    } else {\n      panel_resize_observer.unobserve(test_details_panel_element)\n      document.body.style.removeProperty(\"--panel-height\")\n    }\n  }))\n  if (state_manager.state.tool_tag[0] !== null)\n    panel_resize_observer.observe(test_details_panel_element, { box: \"border-box\" })\n\n  // Install tooltip component\n  $(function() {\n    $(document).tooltip({ track: true, show: 0, hide: 0 });\n  });\n})\n"
  },
  {
    "path": "conf/requirements.txt",
    "content": "pyyaml\njinja2\ntree_sitter==0.20.4\npygments\nyapf==0.30.0\npsutil\nmako\nmake_var\nmarkupsafe\npytablewriter\nGitPython\nsimplesat==0.8.2\ngit+https://github.com/lowRISC/edalize.git@ot\ngit+https://github.com/lowRISC/fusesoc.git@ot\norderedmultidict\n"
  },
  {
    "path": "conf/runners/libs.json",
    "content": "{\n    \"uvm\": {\n        \"files\": [\"tests/uvm/src/uvm_pkg.sv\"],\n        \"incdirs\": [\"tests/uvm/src\"]\n    }\n}\n"
  },
  {
    "path": "generators/ariane",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport sys\nimport os\nimport re\nfrom make_var import *\n\ntempl = \"\"\"/*\n:name: {name}\n:description: {description}\n:files: {files}\n:incdirs: {incdirs}\n:defines: {defines}\n:tags: ariane cva6\n:results_group: cores\n:top_module: {top_module}\n:timeout: 360\n*/\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR and TESTS_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\nariane_path = os.path.abspath(os.path.join(third_party_dir, \"cores\", \"ariane\"))\nhpdcache_path = os.path.join(\n    ariane_path, \"core\", \"cache_subsystem\", \"hpdcache\")\n\n# Core-only configs use core/Flist.cva6 with target_cfg substitution.\n# The testbench config parses verilate_command from the Makefile via make -pn.\n\nlists = [\n    # 64-bit baseline — default config, std write-through cache, Sv39 MMU\n    {\n        'name': 'cva6_cv64a6_imafdc_sv39',\n        'description': 'CVA6 64-bit RV64GC, Sv39 MMU, write-through cache',\n        'target_cfg': 'cv64a6_imafdc_sv39',\n        'top_module': 'cva6',\n        'flist': ['core/Flist.cva6'],\n    },\n    # 64-bit HPDcache — exercises the entirely different HPDcache subsystem RTL\n    {\n        'name': 'cva6_cv64a6_imafdc_sv39_hpdcache',\n        'description': 'CVA6 64-bit RV64GC, Sv39, HPDcache',\n        'target_cfg': 'cv64a6_imafdc_sv39_hpdcache',\n        'top_module': 'cva6',\n        'flist': ['core/Flist.cva6'],\n    },\n    # 64-bit H-extension — hypervisor adds two-stage MMU, new CSRs\n    {\n        'name': 'cva6_cv64a6_imafdch_sv39',\n        'description': 'CVA6 64-bit RV64GC + H-extension, Sv39',\n        'target_cfg': 'cv64a6_imafdch_sv39',\n        'top_module': 'cva6',\n        'flist': ['core/Flist.cva6'],\n    },\n    # 32-bit — different XLEN, Sv32 MMU, no FPU\n    {\n        'name': 'cva6_cv32a6_imac_sv32',\n        'description': 'CVA6 32-bit RV32IMAC, Sv32 MMU',\n        'target_cfg': 'cv32a6_imac_sv32',\n        'top_module': 'cva6',\n        'flist': ['core/Flist.cva6'],\n    },\n    # Testbench — APU wrapper, AXI, peripherals, RVFI\n    {\n        'name': 'cva6_tb_cv64a6_imafdc_sv39',\n        'description': 'CVA6 64-bit testharness with SoC peripherals',\n        'top_module': 'ariane_testharness',\n        'use_makefile': True,\n    },\n]\n\nenv_vars = {\n    '${CVA6_REPO_DIR}': ariane_path,\n    '${HPDCACHE_DIR}': hpdcache_path,\n    '${CVA6_TB_DIR}': os.path.join(ariane_path, 'verif', 'tb', 'core'),\n}\n\n\ndef expand_vars(line, target_cfg):\n    for var, val in env_vars.items():\n        line = line.replace(var, val)\n    line = line.replace('${TARGET_CFG}', target_cfg)\n    return line\n\n\ndef process_filelist(flist_path, target_cfg, incdirs, defines, sources):\n    with open(flist_path) as f:\n        for line in f:\n            line = line.strip()\n            if not line or line.startswith('//'):\n                continue\n\n            line = expand_vars(line, target_cfg)\n\n            if line.startswith('+incdir+'):\n                incdirs.add(line.partition('+incdir+')[2])\n            elif line.startswith('+define+'):\n                defines.add(line.partition('+define+')[2])\n            elif line.startswith('-F'):\n                nested = line.split(None, 1)[1].strip()\n                if os.path.isfile(nested):\n                    process_filelist(\n                        nested, target_cfg, incdirs, defines, sources)\n            elif re.search(r'\\.(sv|v)$', line):\n                if os.path.isfile(line):\n                    sources.append(line)\n\n\ndef get_verilate_command_sources():\n    \"\"\"Use make -pn to get the expanded verilate_command, then extract\n    sources, incdirs, defines, and top_module from it.\"\"\"\n    main_path = os.path.abspath(os.getcwd())\n    os.chdir(ariane_path)\n    os.environ['RISCV'] = \"./\"\n\n    M = make_vars(origin=['makefile'])\n    os.chdir(main_path)\n\n    try:\n        ver_cmd = M['makefile']['verilate_command']\n    except KeyError:\n        print(\"Warning: verilate_command not found in Makefile\")\n        return [], set(), set(), 'ariane_testharness'\n\n    incdirs = set()\n    defines = set()\n    sources = []\n    top_module = 'ariane_testharness'\n    seen = set()\n\n    # Verilator auto-defines VERILATOR; add it for other tools (e.g. slang)\n    # that don't. This controls ifdef guards for UVM includes, mock UART, etc.\n    defines.add('VERILATOR')\n\n    tokens = iter(ver_cmd.split())\n    for tok in tokens:\n        tok = tok.strip()\n        if tok.startswith('+incdir+'):\n            incdirs.add(tok.partition('+incdir+')[2])\n        elif tok.startswith('+define+'):\n            d = tok.partition('+define+')[2]\n            if d:\n                defines.add(d)\n        elif tok == '-f':\n            flist = next(tokens, '').strip()\n            flist_path = os.path.join(ariane_path, flist)\n            if os.path.isfile(flist_path):\n                process_filelist(\n                    flist_path, 'cv64a6_imafdc_sv39', incdirs, defines,\n                    sources)\n                seen.update(sources)\n        elif tok == '--top-module':\n            top_module = next(tokens, top_module).strip()\n        elif re.search(r'\\.(sv|v)$', tok):\n            path = tok if os.path.isabs(tok) else os.path.join(\n                ariane_path, tok)\n            if os.path.isfile(path) and path not in seen:\n                sources.append(path)\n                seen.add(path)\n\n    return sources, incdirs, defines, top_module\n\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\nos.makedirs(test_dir, exist_ok=True)\n\nfor entry in lists:\n    incdirs = set()\n    defines = set()\n    sources = []\n\n    if entry.get('use_makefile'):\n        sources, incdirs, defines, top = get_verilate_command_sources()\n        entry['top_module'] = top\n    else:\n        for flist in entry['flist']:\n            flist_path = os.path.join(ariane_path, flist)\n            if not os.path.isfile(flist_path):\n                print(f\"Warning: flist not found: {flist_path}, skipping\")\n                continue\n            process_filelist(\n                flist_path, entry['target_cfg'], incdirs, defines, sources)\n\n    if not sources:\n        print(f\"Warning: no sources for {entry['name']}, skipping\")\n        continue\n\n    test_file = os.path.join(test_dir, entry['name'] + '.sv')\n\n    with open(test_file, 'w') as f:\n        f.write(\n            templ.format(\n                name=entry['name'],\n                description=entry['description'],\n                files=' '.join(sources),\n                incdirs=' '.join(sorted(incdirs)),\n                defines=' '.join(sorted(defines)),\n                top_module=entry['top_module'],\n            ))\n\n    print(f\"Generated: {test_file}\")\n"
  },
  {
    "path": "generators/black-parrot",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport re\nimport sys\n\ntempl = \"\"\"/*\n:name: {3}\n:description: black-parrot core test\n:files: {0}\n:incdirs: {1}\n:top_module: {2}\n:tags: black-parrot\n:results_group: cores\n:timeout: 1000\n*/\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\nbp_path = os.path.abspath(\n    os.path.join(third_party_dir, \"cores\", \"black-parrot\"))\n\n# BlackParrot has RTL in the main repo and in the BaseJump STL submodule\ncmd = f\"git submodule update --init --checkout {bp_path}\"\nprint(cmd)\nos.system(cmd)\ncmd = f\"cd {bp_path}; git submodule update --init --recursive external/basejump_stl\"\nprint(cmd)\nos.system(cmd)\ncmd = f\"cd {bp_path}; git submodule update --init --recursive external/HardFloat\"\nprint(cmd)\nos.system(cmd)\n\nlists = [\n    {\n        'name': 'bp_default',\n        'cfg': 'e_bp_default_cfg',\n        'flist': 'bp_top/syn/flist.vcs'\n    }, {\n        'name': 'bp_unicore',\n        'cfg': 'e_bp_unicore_cfg',\n        'flist': 'bp_top/syn/flist.vcs'\n    }, {\n        'name': 'bp_multicore_1',\n        'cfg': 'e_bp_multicore_1_cfg',\n        'flist': 'bp_top/syn/flist.vcs'\n    }, {\n        'name': 'bp_multicore_1_cce_ucode',\n        'cfg': 'e_bp_multicore_1_cce_ucode_cfg',\n        'flist': 'bp_top/syn/flist.vcs'\n    }, {\n        'name': 'bp_multicore_4',\n        'cfg': 'e_bp_multicore_4_cfg',\n        'flist': 'bp_top/syn/flist.vcs'\n    }, {\n        'name': 'bp_multicore_4_cce_ucode_cfg',\n        'cfg': 'e_bp_multicore_4_cce_ucode_cfg',\n        'flist': 'bp_top/syn/flist.vcs'\n    }\n]\n\ndirs = {\n    '$BP_COMMON_DIR': 'bp_common',\n    '$BP_FE_DIR': 'bp_fe',\n    '$BP_BE_DIR': 'bp_be',\n    '$BP_ME_DIR': 'bp_me',\n    '$BP_TOP_DIR': 'bp_top',\n    '$BP_EXTERNAL_DIR': 'external',\n    '$BASEJUMP_STL_DIR': 'external/basejump_stl',\n    '$HARDFLOAT_DIR': 'external/HardFloat',\n}\n\n\ndef expandPaths(p):\n    for d in dirs:\n        p = re.sub(re.escape(d), dirs[d], p)\n    return os.path.join(bp_path, p)\n\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\nif not os.path.isdir(test_dir):\n    os.makedirs(test_dir, exist_ok=True)\n\nfor l in lists:\n    sources = ''\n    incdirs = ''\n\n    with open(os.path.join(bp_path, l['flist'])) as f:\n        for line in f:\n            line = re.sub(r'^\\+define\\+.*?$', '', line)\n            line = re.sub(r'//.*?$', '', line)\n            line = re.sub(r'#.*?$', '', line)\n            res = re.match(r'^\\+incdir\\+(.*?)$', line)\n            if res is not None:\n                incdirs += expandPaths(res.group(1)) + ' '\n                continue\n            if len(line.strip()) > 0:\n                sources += expandPaths(line.strip()) + ' '\n    test_file = os.path.join(test_dir, l['name'] + '.sv')\n    cfg = l['cfg']\n    cmd = f\"sed 's/BP_CFG_FLOWVAR/{cfg}/g' {bp_path}/bp_top/test/tb/bp_tethered/wrapper.sv > {test_file}\"\n    print(cmd)\n    os.system(cmd)\n    sources += os.path.realpath(test_file)\n    with open(test_file, \"r+\") as f:\n        content = f.read()\n        f.seek(0, 0)\n        f.write(templ.format(sources, incdirs, \"wrapper\", l['name']) + content)\n"
  },
  {
    "path": "generators/easyUVM",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\nimport yaml\n\ntempl = \"\"\"/*\n:name: easyUVM\n:description: UVM testbench test\n:files: {0}\n:incdirs: {1}\n:tags: uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\nuvm_path = os.path.abspath(os.path.join(third_party_dir, \"tests\", \"easyUVM\"))\n\nsources = os.path.join(uvm_path, 'top.sv')\nincdirs = uvm_path\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\nif not os.path.isdir(test_dir):\n    os.makedirs(test_dir, exist_ok=True)\n\ntest_file = os.path.join(test_dir, \"top.sv\")\n\nwith open(test_file, \"w\") as f:\n    f.write(templ.format(sources, incdirs))\n"
  },
  {
    "path": "generators/fusesoc",
    "content": "#!/usr/bin/env python3\n\nimport os\nimport re\nimport sys\nimport yaml\nimport subprocess\nimport collections\nimport make_var\n\ntempl = \"\"\"/*\n:name: {0}\n:description: {1}\n:files: {2}\n:incdirs: {3}\n:defines: {4}\n:top_module: {5}\n:tags: {6}\n:timeout: {7}\n:results_group: cores\n:compatible-runners: {8}\n:type: {9}\n\"\"\"\n\ntry:\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\nfusesoc_conf_subdir = \"fusesoc-configs\"\nfusesoc_conf_files = os.listdir(\n    os.path.abspath(os.path.join(conf_dir, fusesoc_conf_subdir)))\n\nfor fusesoc_conf_file in fusesoc_conf_files:\n    fusesoc_conf_file = os.path.abspath(\n        os.path.join(conf_dir, fusesoc_conf_subdir, fusesoc_conf_file))\n\n    if not os.path.isfile(fusesoc_conf_file):\n        continue\n\n    with open(fusesoc_conf_file, 'r') as stream:\n        try:\n            yml_conf = yaml.safe_load(stream)\n        except yaml.YAMLError as err:\n            print(err)\n            sys.exit(1)\n\n    try:\n        yml_conf[\"name\"]\n        yml_conf[\"description\"]\n        yml_conf[\"top_module\"]\n        yml_conf[\"tags\"]\n        yml_conf[\"path\"]\n        yml_conf[\"command\"]\n        yml_conf[\"conf_file\"]\n        yml_conf[\"test_file\"]\n        yml_conf[\"timeout\"]\n        yml_conf[\"compatible-runners\"]\n        yml_conf[\"type\"]\n    except KeyError as err:\n        print(\"No key\", err, \"in file\", fusesoc_conf_file)\n        continue\n\n    test_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\n    if not os.path.isdir(test_dir):\n        os.makedirs(test_dir, exist_ok=True)\n\n    test_file = os.path.join(test_dir, yml_conf[\"test_file\"])\n\n    command_list = list(yml_conf[\"command\"].split(\" \"))\n\n    subprocess.call(\n        command_list, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL)\n\n    core_conf_path = os.path.abspath(yml_conf[\"conf_file\"])\n    sources_path = os.path.dirname(core_conf_path)\n\n    incdirs = ''\n    sources = ''\n    defines = ''\n    runner_flags = collections.defaultdict(str)\n\n    if core_conf_path.endswith(\".vc\") or core_conf_path.endswith(\".scr\"):\n        with open(core_conf_path, \"r\") as f:\n            for line in f:\n                line = line.strip()\n                if line.startswith(\"+incdir+\"):\n                    incdirs += os.path.join(\n                        sources_path,\n                        line.partition(\"+incdir+\")[2]) + ' '\n                elif (core_conf_path.endswith('.vc')\n                      and line.startswith(\"--top-module\")):\n                    top_module = line.partition(\"--top-module \")[2]\n                elif line.startswith(\"-D\"):\n                    defines += line[2:] + ' '\n                elif line.startswith(\"-CFLAGS\"):\n                    runner_flags[\"verilator\"] += \"-CFLAGS -I\" + os.path.join(\n                        sources_path,\n                        line.partition(\"-CFLAGS -I\")[2]) + ' '\n                elif line.startswith(\"-LDFLAGS\"):\n                    runner_flags[\"verilator\"] += line + ' '\n                elif not line.startswith(\"-\") and line:\n                    sources += os.path.join(sources_path, line) + ' '\n        try:\n            make_vars = make_var.make_vars(\n                cmd=\"make -pn -f \" + os.path.join(sources_path, \"config.mk\"))\n            runner_flags[\"verilator\"] += make_vars[\"makefile\"][\n                \"VERILATOR_OPTIONS\"]\n        except:\n            pass\n\n    elif core_conf_path.endswith(\".tcl\"):\n        with open(core_conf_path, \"r\") as f:\n            for line in f:\n                line = line.strip()\n                src_file_match = re.match(\n                    r\"read_verilog\\s+-sv\\s+{?(.+?)}?\\s*$\", line)\n                if src_file_match:\n                    src_file = src_file_match.group(1)\n                    sources += os.path.join(sources_path, src_file) + \" \"\n                elif line.startswith(\"set_property include_dirs \"):\n                    line.replace(\"set_property include_dirs \", \"\")\n                    # Skip unnecessary information here, leave only paths to include dirs\n                    split = line.split(\" \")[3:-3]\n                    for s in split:\n                        incdirs += os.path.join(sources_path, s) + \" \"\n    else:\n        print(\n            f\"Unsupported config file: {core_conf_path}, currently supports only .vc, .scr and .tcl files\"\n        )\n        sys.exit(1)\n\n    # Fusesoc files dedicated for Verilator contains top module\n    if not core_conf_path.endswith('.vc'):\n        top_module = yml_conf[\"top_module\"]\n\n    with open(test_file, \"w\") as f:\n        f.write(\n            templ.format(\n                yml_conf[\"name\"], yml_conf[\"description\"], sources, incdirs,\n                defines, top_module, yml_conf[\"tags\"], yml_conf[\"timeout\"],\n                yml_conf[\"compatible-runners\"], yml_conf[\"type\"]))\n        for runner, flags in runner_flags.items():\n            f.write(f\":runner_{runner}_flags: {flags}\\n\")\n        f.write(\"*/\")\n"
  },
  {
    "path": "generators/fx68k",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\n\ntempl = \"\"\"/*\n:name: fx68k\n:description: Full fx68k core test\n:files: {0}\n:tags: fx68k\n:results_group: cores\n:timeout: 100\n*/\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR and TESTS_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\nfx68k_path = os.path.abspath(os.path.join(third_party_dir, \"cores\", \"fx68k\"))\n\nfx68k_sources = ['fx68k.sv', 'fx68kAlu.sv', 'uaddrPla.sv']\n\nsources = ''\n\nfor src in fx68k_sources:\n    sources += os.path.join(fx68k_path, src) + ' '\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\nif not os.path.isdir(test_dir):\n    os.makedirs(test_dir, exist_ok=True)\n\ntest_file = os.path.join(test_dir, \"fx68k.sv\")\n\nwith open(test_file, \"w\") as f:\n    f.write(templ.format(sources))\n"
  },
  {
    "path": "generators/ivtest",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020-2021 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport re\nimport os\nimport sys\nimport glob\n\ntempl = \"\"\"/*\n:name: {0}\n:description: Test imported from ivtest\n:files: {1}\n:incdirs: {3}\n:tags: ivtest\n:results_group: imported\n:type: simulation elaboration parsing\n{2}\n{4}\n*/\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\ntype_should_fail = ['CE', 'RE']\n\n# FIXME: this all needs to be updated to properly load the ivtest *.list\n#        files like is done with the ivtest driver along with the correct\n#        override of the various tests.\nivtest_list_exclude = [\n    'blif.list',  # Skip the BLIF test list\n    'regress-ivl1.list',  # Skip the Icarus specific test list\n    'regress-ivl2.list',  # Skip the Icarus strict test list\n    'regress-msys2.list',  # Skip the msys2 override test list\n    'regress-v10.list',  # Skip the v10 override test list\n    'regress-v11.list',  # Skip the v11 override test list\n    'regress-v12.list',  # Skip the v12 override test list\n    'regress-vams.list',  # Skip the VAMS test list\n    'regress-vhdl.list',  # Skip the VHDL test list\n    'regress-vlog95.list',  # Skip the vlog95 override test list\n    'vhdl_regress.list',  # Skip the VHDL side test list\n    'vpi_regress.list'  # Skip the VPI test list\n]\n\nivtest_file_exclude = [\n    # The following are invalid per the latest standard, but are supported by\n    # commercial tools. For now exclude these tests in sv-tests.\n    # '{} (empty array)\n    'sv_array_assign_pattern2',\n    'sv_darray_args1',\n    'sv_darray_args2',\n    'sv_darray_args2b',\n    'sv_darray_args3',\n    'sv_darray_args4',\n    'sv_queue_real',\n    'sv_queue_string',\n    'sv_queue_vec',\n    # pullup/down with multiple terminals\n    'pr1787423',\n    'pr1787423b',\n    'pr2834340',\n    'pr2834340b',\n    # Parallel path '=>' with multiple input terminals\n    'pr1877743',\n    'specify_01',\n    # Parameter override without parens\n    'pr3194155',\n    'z1',\n    'z2',\n    # Empty parameter override\n    'pr1716276',\n    # Package scope event access\n    'sv_wildcard_import2',\n    'sv_wildcard_import3',\n    # Packed dims support [<dim>] for [0:<dim>-1] just like unpacked dims\n    'display_bug',\n    # `protect compiler directives\n    'pr478',\n    # `suppress_faults compiler directives\n    'pr1467825',\n    # generate begin/end was valid when generate was initially defined\n    'br988',\n    'pr2257003',\n    'pr2257003b',\n    # Using %v with a variable\n    'pr923',\n    # $itor(real) and $rtoi(self-determined integer)\n    'itor_rtoi',\n    # $printtimescale() can be passed more than a module identifier\n    'pr1701855b',\n    # Extra module instance parameters are a warning and then ignored\n    'param_test3',\n    # Initialization can be used with non-ANSI port definitions\n    'pr2790236',\n    # A foreach can have statement_or_null\n    'sf1289',\n    # These are optional system tasks and functions and may not be supported\n    'countdrivers1',\n    'countdrivers2',\n    'countdrivers3',\n    'countdrivers4',\n    'countdrivers5',\n    # Icarus checks that always blocks have delay constructs to prevent\n    # infinite loops. For now exclude these. I would ideally like to make\n    # these marked as fails for Icarus and and correctly parsed for others.\n    'always4A',\n    'always4B',\n    'always311A',\n    'always311B',\n    'always312A',\n    'always312B',\n    'always312C',\n    'always312D',\n    'always312E',\n    'always312F',\n    'always312G',\n    'always312H',\n    'always312I',\n    'always313A',\n    'always313B',\n    'always313C',\n    'always313D',\n    'always313E',\n    'always313F',\n    'always313G',\n    'always313H',\n    'always313J',\n    'always319A',\n    'always319B',\n    'always3110A',\n    'br991b',\n    'pr1862744b',\n    # Icarus checks that the always_* processes do not contain delay\n    # constructs and that the always_ff has a sensitivity list. These should\n    # should fail in Icarus, but should parse correctly.\n    'always_comb_fail3',\n    'always_comb_fail4',\n    'always_comb_fail',\n    'always_ff_fail2',\n    'always_ff_fail3',\n    'always_ff_fail4',\n    'always_ff_fail',\n    'always_ff_no_sens',\n    'always_latch_fail3',\n    'always_latch_fail4',\n    'always_latch_fail',\n    'always_latch_no_sens',\n    # '@ *' is valid and supported by commercial tools\n    'case3',\n    'wildsense',\n    # The following tests need to be looked at and verified\n    'pr1723367',  # scalar with vectored net\n    'undef',  # undefined macro behaviour is ambiguous\n    'sformatf',  # Too many arguments passed to $sformatf\n    'format',  # Missing argument to $display\n    # These tests use procedural continuous assigns with bit selects on the lhs,\n    # which is not allowed according to the LRM.\n    'array_lval_select3a',\n    'assign32E',\n    'assign_deassign_pv',\n    'force_lval_part',\n    'force_release_reg_pv',\n    'pr1832097b',\n    'pr2943394',\n    # These tests are marked 'designed to fail' but are actually valid.\n    'sv_port_default14',\n    'br995',\n    'br_gh306a',\n    'br_gh306b',\n    'case5synfail',\n    'casesynth8',\n    'dffsynth8',\n    'br1015a',\n    'br1027a',\n    'br1027c',\n    'br1027e',\n    'br_gh25a',\n    'br_gh25b',\n    'check_constant_3',\n    'function4',\n    'no_timescale_in_module',\n    'pr1704013',\n    'scope2b',\n    'event_array',\n    # $dumpvars with bit selects, doesn't appear to be legal and commercial tools disallow\n    'array_word_check',\n    'dump_memword',\n    # defparam targeting a localparam isn't allowed\n    'br_gh157',\n    'scoped_events',\n    # Module ANSI ports are redeclared in body\n    'br_ml20150606',\n    # This expects failure because of unsized literal in a concat, but pretty much\n    # all tools allow this (usually with a warning) as an extension because tons of code\n    # in the wild does it.\n    'indef_width_concat',\n    # Primitive port connections cannot use the '.name()' syntax\n    'pr938b',\n    'udp_dff',\n    # Icarus checks that final-blocks do not have non-blocking assignments but\n    # a strict reading of IEEE 1800-2017, $9.2.3 does not require this, even\n    # though the non-blocking assignment will have no effect.\n    'program3b',\n    # A wire with 'real' type is not allowed (commercial tools disallow)\n    'br_gh156',\n    'br_gh556',\n    # This test forgets to add parenthesis to a module instantiation.\n    'br_gh553',\n    # Expects pass or failure for out-of-bounds access but most tools warn instead of\n    # hard error and LRM specifies what the runtime behavior is.\n    'br_gh840a',\n    'br_gh840b',\n    'assign_op_oob',\n    'assign_op_real_array_oob',\n    # Provides connection for null port, LRM is unclear but all commercial tools disallow this\n    'pr1723367',\n    # Expects failure for using a slice in $readmemh but the LRM explicitly allows for this.\n    # VCS fails but other tools allow.\n    'readmemh5',\n    # Illegal; IEEE says parameters may be limited to 32 bits if no type is provided\n    'ilongint_test',\n    # Expects failure but IEEE does not disallow zero size arrays (parameters may cause this)\n    'br_ml20181012d',\n    # Test does not compile without __ICARUS__\n    'implicit_cast12',\n    'implicit_cast13',\n    # Illegal, f_ffffffff has too many digits for int\n    'sv_class8',\n    # output directory doesn't exist\n    'writememb1',\n    'writememb2',\n    'writememh1',\n    'writememh2',\n    # negative tests\n    'writememerror',\n    'uwire_fail',\n    # Null object dereferenced\n    'br_gh104a',\n    # Some tools error others warn, it's not clear in LRM what the requirements are\n    'br_gh230',\n    # Zero sized constant is illegal, but some tools warn and ignore\n    'br_gh60a',\n    # String type is not implicitly assignment compatible to a packed vector, but some allow\n    'br_ml20180227',\n    # Negative test wrong, what is tested appears legal on other simulators and by IEEE\n    'comment1',\n    # Checked values FAILED on multiple other simulators\n    'concat4',\n    # Illegal, but some tooks just warn\n    'enum_test3',\n    # Fails on others; does not appear to match IEEE's description of define identifiers\n    'escaped_macro_name',\n    # Checked values FAILED on multiple other simulators\n    'func_init_var3',\n    # Negative test that in some tools throws a warning rather than fatal error\n    'pr1938138',\n    # Unclear, most tools hard error but for some tools allow\n    'pr2794144',\n    # Modules ignored due to module ordering sv-test driver limitation\n    'br_gh104b',\n    'check_constant_2',\n    'def_nettype_none',\n    'implicitport2',\n    'implicitport3',\n    'implicitport6',\n    'mhead_task',\n    'pr1587634',\n    'pr1698659',\n    'pr2076425',\n    'pr2792883',\n    'shellho1',\n    # needs data text file that this test harness doesn't enable finding\n    'pr2800985a',\n    # primitive table rows are invalid, fails on multiple commercial tools\n    'pr3587570',\n    # Compilation errors with other simulators\n    'pr1520314',\n    # Synthesis one-hot assertion fails\n    'onehot',\n    # Primitive connect to real\n    'br_gh1182',\n    # Intentional assertion failures\n    'sv_deferred_assert1',\n    'sv_deferred_assert2',\n    'sv_deferred_assume1',\n    'sv_deferred_assume2',\n    'sv_immediate_assert',\n    'sv_immediate_assume',\n    'case_priority',\n    'case_unique',\n    # IEEE 22.2 directives must be on same line\n    'br_gh782b',\n    'br_gh782c',\n    'br_gh782e',\n    'br_gh782f',\n    # Requires iv-specific $abstime/$is_signed\n    'pr2590274a',\n    'pr2590274b',\n    'pr2590274c',\n    'struct_member_signed',\n    'struct_signed',\n    # '%d' with string argument\n    'sv_cast_typedef',\n    # IEEE does not disallow void' of a void function/task, 4 of 5 simulators take it\n    # (Useful in macros that void-call a passed func/task name without knowing dtype)\n    'sv_void_cast_fail1',\n    'sv_void_cast_fail2',\n    # Declares ports in the module body without declaring them in the header.\n    # The LRM does not allow this. All tools tried fail on this.\n    'module_output_port_sv_var2',\n    'module_output_port_var2',\n    # References a compilation unit-level item from within a package, which is not allowed\n    'sv_ps_type_class1',\n    # These need to be run in a Verilog-specific mode once sv-tests has one, since they expect\n    # failure even though SystemVerilog allows them.\n    'br_gh956a',\n    'module_inout_port_type',\n    'module_input_port_list_def',\n    'module_input_port_type',\n    'parameter_in_generate1',\n    'parameter_no_default',\n    'parameter_omit1',\n    'parameter_omit2',\n    'parameter_omit3',\n    'unnamed_block_var_decl',\n    'unnamed_fork_var_decl',\n    # References a non-existent module\n    'macro_args',\n    # Nested block comments are disallowed currently in SystemVerilog, however\n    # all simulators take this, so allowing it.\n    'macro_comment_multiline',\n    # It's not illegal to declare a range on a non-ANSI port declaration even\n    # if the 'direction' declaration for the port does not have it. LRM does not\n    # specify such a restriction, all tools support it.\n    'module_nonansi_vec_fail2',\n    'task_nonansi_vec_fail3',\n    # Wrapper script doesn't pass parameter to non-Icarus tools, so test fails\n    'parameter_no_default_toplvl',\n    # Wrapper script doean't give a top-module and fails as `celldefine's are\n    # assumed part of libraries and not automatically processed otherwise\n    'specify1',\n    # Declares \"x\" twice (Unlike modules, task/func 'dtype x'\n    # must be after 'input x'. All non-Icarus simulators agree.\n    'task_nonansi_enum2',\n    'task_nonansi_int2',\n    'task_nonansi_integer2',\n    'task_nonansi_parray2',\n    'task_nonansi_real2',\n    'task_nonansi_time2',\n    'task_nonansi_vec2',\n    # Test should expect fail: IEEE does not allow .* to connect to empty ports\n    'br_gh530',\n    # The LRM does not seem to support the idea of leaking enum members out of a surrounding\n    # struct scope, though some tools support it. VCS does not.\n    'enum_in_struct',\n    # All tools allow this. The LRM contains some conflicting wording on this, but shows\n    # an example that implies it should be allowed.\n    'sv_export_fail1',\n    # Redefining the same UDP is above what IEEE specifies; it's an error on some tools,\n    # warning on others (which pick first or last defined), and ignored on yet others.\n    'br_gh1175f',\n    # These appear to be mismarked, should be expect-fail, referencing an implicit\n    # net before it's declared. All commercial tools fail on this.\n    'pr1909940',\n    'pr1909940b',\n]\n\nivtest_extra_args = {\n    # Long running\n    'comp1000': ':timeout: 360',\n    'comp1001': ':timeout: 360',\n    # Promote warning to error to match iverilog\n    'porttest3': ':runner_verilator_flags: -Werror-ASSIGNIN',\n    'pow_ca_signed': ':runner_verilator_flags: --converge-limit 1000000',\n    'pow_ca_unsigned': ':runner_verilator_flags: --converge-limit 1000000',\n}\n\nivtest_dir = os.path.abspath(\n    os.path.join(third_party_dir, \"tools\", \"icarus\", \"ivtest\"))\nivtest_list_exclude = set(\n    map(lambda x: os.path.join(ivtest_dir, x), ivtest_list_exclude))\nivtest_lists = sorted(\n    list(\n        set(glob.glob(os.path.join(ivtest_dir, '*.list'))) -\n        ivtest_list_exclude))\n\ntests = []\n\nskip = False\n\nincdirs = [ivtest_dir, os.path.join(ivtest_dir, 'ivltests')]\n\nfor l in ivtest_lists:\n    list_filename = re.match(r'.*/([^/]*)\\.list', l).group(1)\n    with open(l, 'r') as f:\n        for line in f:\n            if skip:\n                skip = False\n                continue\n\n            # remove comments\n            line = re.sub(r'#.*?\\n', '', line)\n\n            # skip multiline definitions\n            if re.search(r'\\\\\\n', line):\n                skip = True\n                continue\n\n            line = line.split()\n\n            if len(line) < 3:\n                continue\n\n            # skip Not Implemented tests\n            if re.match('NI', line[1]):\n                continue\n\n            name = line[0]\n            path = os.path.join(ivtest_dir, line[2], line[0] + '.v')\n            should_fail_because = ''\n\n            # sanitize name\n            name = re.sub(r'\\W', '', name)\n\n            if name in ivtest_file_exclude:\n                continue\n\n            for t in type_should_fail:\n                if re.match(t, line[1]):\n                    should_fail_because = ':should_fail_because: this test was imported from ivtest and is designed to fail'\n\n            extra_args = ''\n            if name in ivtest_extra_args:\n                extra_args += ivtest_extra_args[name]\n\n            tests.append(\n                (\n                    list_filename + '_' + name + '_iv', path,\n                    should_fail_because, ' '.join(incdirs), extra_args))\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\nif not os.path.isdir(test_dir):\n    os.makedirs(test_dir, exist_ok=True)\n\nfor test in tests:\n    test_file = os.path.join(test_dir, test[0] + '.sv')\n    with open(test_file, \"w\") as f:\n        f.write(templ.format(*test))\n"
  },
  {
    "path": "generators/path_generator",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\nimport json\nimport glob\n\ntempl = \"\"\"/*\n:name: {name}\n:description: Tests imported from {project}\n:files: {files}\n:incdirs: {incdirs}\n:tags: {project}\n{extra_tags}\n*/\n{extra_code}\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\nname = ''\nproject = ''\npaths = [[]]\nmatches = []\n\nfor cfg in glob.glob(os.path.join(conf_dir, 'generators', 'meta-path',\n                                  '*.json')):\n    with open(cfg, 'r') as jf:\n        global_extra_tags = []\n        extra_code = \"\"\n        data = json.load(jf)\n        name = data['name']\n        project = data['project']\n        if 'should_fail_because' in data:\n            global_extra_tags.append(\n                f\":should_fail_because: {data['should_fail_because']}\")\n        paths = data['paths']\n        matches = data['matches']\n        blacklist = data.get('blacklist', [''])\n        commons = data.get('commons', [])\n        incdirs = data.get('incdirs', [])\n        timeouts = data.get('timeouts', {})\n        test_type = data.get('type', None)\n        results_group = data.get('results_group', None)\n\n        if test_type is not None:\n            global_extra_tags.append(f\":type: {test_type}\")\n\n        if results_group is not None:\n            global_extra_tags.append(f\":results_group: {results_group}\")\n\n        if 'fake_topmodule' in data:\n            global_extra_tags.append(\":top_module: top\")\n            extra_code = \"module top; endmodule\"\n\n    test_dir = os.path.join(tests_dir, 'generated', project)\n\n    if not os.path.isdir(test_dir):\n        os.makedirs(test_dir, exist_ok=True)\n\n    for path in paths:\n        for match in matches:\n            search_path = os.path.abspath(\n                os.path.join(third_party_dir, *path, match))\n            for f in glob.glob(search_path):\n\n                # make a copy of extra tags for a particular test\n                extra_tags = global_extra_tags[:]\n                basename = os.path.basename(f)\n                if blacklist.count(basename) > 0:\n                    print(\"Skipping blacklisted file: {}\".format(f))\n                    continue\n                fname = name + '_' + os.path.basename(os.path.splitext(f)[0])\n                # check if this file is in folder inside test directory\n                folder_path = f.replace(\n                    os.path.commonprefix([f, search_path]), \"\")\n                folder_path = os.path.dirname(folder_path)\n                folder_path = folder_path.replace(\"/\", \"_\")\n                if folder_path != \"\":\n                    fname = folder_path + \"_\" + fname\n                test_file = os.path.join(test_dir, fname + '.sv')\n\n                incs = os.path.dirname(f)\n\n                for common in commons:\n                    f = os.path.abspath(\n                        os.path.join(third_party_dir, common)) + \" \" + f\n\n                # add the test snippet do the beginning of the list\n                f = os.path.abspath(test_file) + \" \" + f\n\n                for incdir in incdirs:\n                    incs = os.path.abspath(\n                        os.path.join(third_party_dir, incdir)) + \" \" + incs\n\n                if basename in timeouts:\n                    extra_tags.append(f\":timeout: {timeouts[basename]}\")\n\n                extra_tags = \"\\n\".join(extra_tags)\n\n                with open(test_file, \"w\") as sv:\n                    sv.write(\n                        templ.format(\n                            project=project,\n                            files=f,\n                            name=fname,\n                            incdirs=incs,\n                            extra_tags=extra_tags,\n                            extra_code=extra_code))\n"
  },
  {
    "path": "generators/rggen",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\nimport glob\nimport re\n\ntempl = \"\"\"/*\n:name: RgGen\n:description: Full RgGen test\n:files: {0}\n:tags: RgGen\n:top_module: rggen\n:results_group: cores\n:timeout: 100\n*/\n\"\"\"\n\nwrapper_tmpl = \"\"\"\nmodule rggen;\n  import  rggen_rtl_pkg::*;\n\n  logic                       clk;\n  logic                       rst_n;\n  rggen_apb_if #(16, 32)      apb_if[2]();\n  logic [3:0]                 register_0_bit_field_0;\n  logic [3:0]                 register_0_bit_field_1;\n  logic                       register_0_bit_field_2;\n  logic [1:0]                 register_0_bit_field_3;\n  logic [1:0]                 register_0_bit_field_4;\n  logic [1:0]                 register_0_bit_field_5;\n  logic [1:0]                 register_0_bit_field_6;\n  logic                       register_1;\n  logic [3:0]                 register_2_bit_field_0;\n  logic                       register_2_bit_field_2_valid;\n  logic [1:0][3:0]            register_2_bit_field_2;\n  logic [1:0][3:0]            register_2_bit_field_3;\n  logic [3:0]                 register_3_bit_field_0;\n  logic [3:0]                 register_3_bit_field_1;\n  logic [3:0]                 register_3_bit_field_2_trigger;\n  logic [3:0]                 register_3_bit_field_3_trigger;\n  logic [3:0]                 register_4_bit_field_0_set;\n  logic [3:0]                 register_4_bit_field_0;\n  logic [3:0]                 register_4_bit_field_1_set;\n  logic [3:0]                 register_4_bit_field_1;\n  logic [3:0]                 register_4_bit_field_1_unmasked;\n  logic [3:0]                 register_4_bit_field_3_clear;\n  logic [3:0]                 register_4_bit_field_3;\n  logic                       register_5_bit_field_0_clear;\n  logic [1:0]                 register_5_bit_field_0;\n  logic [1:0]                 register_5_bit_field_1;\n  logic                       register_5_bit_field_2_set;\n  logic [1:0]                 register_5_bit_field_2;\n  logic [1:0]                 register_5_bit_field_3;\n  logic                       register_5_bit_field_4_valid;\n  logic [1:0]                 register_5_bit_field_4[2];\n  logic [1:0]                 register_5_bit_field_5[2];\n  logic                       register_5_bit_field_6_enable;\n  logic [1:0]                 register_5_bit_field_6;\n  logic [1:0]                 register_5_bit_field_7;\n  logic [1:0]                 register_5_bit_field_8;\n  logic                       register_5_bit_field_9_lock;\n  logic [1:0]                 register_5_bit_field_9;\n  logic [1:0]                 register_5_bit_field_10;\n  logic [1:0]                 register_5_bit_field_11;\n  logic [3:0]                 register_6_bit_field_0_set;\n  logic [3:0]                 register_6_bit_field_0;\n  logic [3:0]                 register_6_bit_field_1_set;\n  logic [3:0]                 register_6_bit_field_1;\n  logic [3:0]                 register_6_bit_field_1_unmasked;\n  logic [3:0]                 register_6_bit_field_3_set;\n  logic [3:0]                 register_6_bit_field_3;\n  logic [3:0]                 register_6_bit_field_4_set;\n  logic [3:0]                 register_6_bit_field_4;\n  logic [3:0]                 register_6_bit_field_4_unmasked;\n  logic [3:0]                 register_6_bit_field_6_clear;\n  logic [3:0]                 register_6_bit_field_6;\n  logic [3:0]                 register_6_bit_field_7_clear;\n  logic [3:0]                 register_6_bit_field_7;\n  logic [3:0]                 register_6_bit_field_8;\n  logic [3:0]                 register_6_bit_field_9;\n  logic [3:0]                 register_7_bit_field_0;\n  logic [3:0]                 register_7_bit_field_1;\n  logic [3:0]                 register_7_bit_field_2;\n  logic [3:0]                 register_7_bit_field_3;\n  logic [3:0]                 register_8_bit_field_0_set;\n  logic [3:0]                 register_8_bit_field_0;\n  logic [3:0]                 register_8_bit_field_1_clear;\n  logic [3:0]                 register_8_bit_field_1;\n  logic [3:0]                 register_8_bit_field_2_set;\n  logic [3:0]                 register_8_bit_field_2;\n  logic [3:0]                 register_8_bit_field_3_clear;\n  logic [3:0]                 register_8_bit_field_3;\n  logic [3:0]                 register_8_bit_field_4;\n  logic [3:0]                 register_8_bit_field_5;\n  logic [1:0]                 register_9_bit_field_0;\n  logic [1:0]                 register_9_bit_field_1;\n  logic [1:0]                 register_9_bit_field_2;\n  logic [1:0][1:0]            register_9_bit_field_3;\n  logic [1:0]                 register_9_bit_field_4;\n  logic [1:0]                 register_9_bit_field_5;\n  logic [3:0][3:0][1:0]       register_10_bit_field_0;\n  logic [3:0][3:0][1:0]       register_10_bit_field_1;\n  logic [3:0][3:0][1:0]       register_10_bit_field_2;\n  logic [1:0][3:0][3:0][7:0]  register_11_bit_field_0;\n  logic [1:0][3:0][3:0][7:0]  register_11_bit_field_1;\n  logic                       register_12_bit_field_0;\n  logic                       register_12_bit_field_1;\n  logic [1:0]                 register_13_bit_field_0;\n  logic [1:0]                 register_13_bit_field_1;\n  logic [1:0]                 register_13_bit_field_2;\n  logic [1:0]                 register_13_bit_field_3;\n  logic                       register_13_bit_field_3_write_trigger;\n  logic                       register_13_bit_field_3_read_trigger;\n  logic [1:0]                 register_13_bit_field_4;\n  logic [1:0]                 register_13_bit_field_5;\n  logic [1:0]                 register_13_bit_field_6;\n  logic [1:0]                 register_13_bit_field_6_hw_clear;\n  logic [1:0]                 register_13_bit_field_7;\n  logic [1:0]                 register_13_bit_field_7_hw_set;\n  logic [1:0]                 register_13_bit_field_8;\n  logic                       register_13_bit_field_8_hw_write_enable;\n  logic [1:0]                 register_13_bit_field_8_hw_write_data;\n  logic                       register_15_bit_field_0;\n  logic                       register_16_bit_field_0;\n  logic [15:0]                register_17_bit_field_0;\n  rggen_bus_if #(8, 32)       register_19_bus_if();\n\n  always_comb begin\n    register_2_bit_field_0                  = register_0_bit_field_0;\n    register_2_bit_field_2_valid            = register_3_bit_field_3_trigger[0];\n    register_2_bit_field_2[0]               = register_0_bit_field_0;\n    register_2_bit_field_3[0]               = register_0_bit_field_0;\n    register_4_bit_field_0_set              = register_3_bit_field_3_trigger;\n    register_4_bit_field_1_set              = register_3_bit_field_3_trigger;\n    register_4_bit_field_3_clear            = register_3_bit_field_2_trigger;\n    register_5_bit_field_0_clear            = register_3_bit_field_2_trigger[0];\n    register_5_bit_field_2_set              = register_3_bit_field_2_trigger[0];\n    register_5_bit_field_4_valid            = register_3_bit_field_3_trigger[0];\n    register_5_bit_field_4[0]               = register_0_bit_field_0[1:0];\n    register_5_bit_field_5[0]               = register_0_bit_field_0[1:0];\n    register_5_bit_field_6_enable           = register_0_bit_field_2;\n    register_5_bit_field_9_lock             = register_0_bit_field_2;\n    register_6_bit_field_0_set              = register_3_bit_field_3_trigger;\n    register_6_bit_field_1_set              = register_3_bit_field_3_trigger;\n    register_6_bit_field_3_set              = register_3_bit_field_3_trigger;\n    register_6_bit_field_4_set              = register_3_bit_field_3_trigger;\n    register_6_bit_field_6_clear            = register_3_bit_field_2_trigger;\n    register_6_bit_field_7_clear            = register_3_bit_field_2_trigger;\n    register_8_bit_field_0_set              = register_3_bit_field_3_trigger;\n    register_8_bit_field_1_clear            = register_3_bit_field_2_trigger;\n    register_8_bit_field_2_set              = register_3_bit_field_3_trigger;\n    register_8_bit_field_3_clear            = register_3_bit_field_2_trigger;\n    register_9_bit_field_1                  = register_0_bit_field_0[1:0];\n    register_9_bit_field_3[1]               = register_0_bit_field_0[1:0];\n    register_9_bit_field_4                  = register_0_bit_field_0[1:0];\n    register_9_bit_field_5                  = register_0_bit_field_0[1:0];\n    register_13_bit_field_1                 = register_13_bit_field_0;\n    register_13_bit_field_6_hw_clear        = register_13_bit_field_3_read_trigger;\n    register_13_bit_field_7_hw_set          = register_13_bit_field_3_read_trigger;\n    register_13_bit_field_8_hw_write_enable = register_13_bit_field_3_write_trigger;\n    register_13_bit_field_8_hw_write_data   = register_13_bit_field_3;\n    register_15_bit_field_0                 = register_0_bit_field_0[0];\n  end\n\n  block_0 #(\n    .ADDRESS_WIDTH                          (16                       ),\n    .PRE_DECODE                             (1'b1                     ),\n    .INSERT_SLICER                          (1'b1                     ),\n    .DEFAULT_READ_DATA                      (32'hDEAD_BEAF            ),\n    .REGISTER_10_BIT_FIELD_1_INITIAL_VALUE  ({2'h3, 2'h2, 2'h1, 2'h0} )\n  ) u_block_0 (\n    .i_clk                                      (clk                                      ),\n    .i_rst_n                                    (rst_n                                    ),\n    .apb_if                                     (apb_if[0]                                ),\n    .o_register_0_bit_field_0                   (register_0_bit_field_0                   ),\n    .o_register_0_bit_field_1                   (register_0_bit_field_1                   ),\n    .o_register_0_bit_field_2                   (register_0_bit_field_2                   ),\n    .o_register_0_bit_field_3                   (register_0_bit_field_3                   ),\n    .o_register_0_bit_field_4                   (register_0_bit_field_4                   ),\n    .o_register_0_bit_field_5                   (register_0_bit_field_5                   ),\n    .o_register_0_bit_field_6                   (register_0_bit_field_6                   ),\n    .i_register_0_bit_field_6                   (register_0_bit_field_6                   ),\n    .o_register_1                               (register_1                               ),\n    .i_register_2_bit_field_0                   (register_2_bit_field_0                   ),\n    .i_register_2_bit_field_2_valid             (register_2_bit_field_2_valid             ),\n    .i_register_2_bit_field_2                   (register_2_bit_field_2[0]                ),\n    .o_register_2_bit_field_2                   (register_2_bit_field_2[1]                ),\n    .i_register_2_bit_field_3                   (register_2_bit_field_3[0]                ),\n    .o_register_2_bit_field_3                   (register_2_bit_field_3[1]                ),\n    .o_register_3_bit_field_0                   (register_3_bit_field_0                   ),\n    .o_register_3_bit_field_1                   (register_3_bit_field_1                   ),\n    .o_register_3_bit_field_2_trigger           (register_3_bit_field_2_trigger           ),\n    .o_register_3_bit_field_3_trigger           (register_3_bit_field_3_trigger           ),\n    .i_register_4_bit_field_0_set               (register_4_bit_field_0_set               ),\n    .o_register_4_bit_field_0                   (register_4_bit_field_0                   ),\n    .i_register_4_bit_field_1_set               (register_4_bit_field_1_set               ),\n    .o_register_4_bit_field_1                   (register_4_bit_field_1                   ),\n    .o_register_4_bit_field_1_unmasked          (register_4_bit_field_1_unmasked          ),\n    .i_register_4_bit_field_3_clear             (register_4_bit_field_3_clear             ),\n    .o_register_4_bit_field_3                   (register_4_bit_field_3                   ),\n    .i_register_5_bit_field_0_clear             (register_5_bit_field_0_clear             ),\n    .o_register_5_bit_field_0                   (register_5_bit_field_0                   ),\n    .o_register_5_bit_field_1                   (register_5_bit_field_1                   ),\n    .i_register_5_bit_field_2_set               (register_5_bit_field_2_set               ),\n    .o_register_5_bit_field_2                   (register_5_bit_field_2                   ),\n    .o_register_5_bit_field_3                   (register_5_bit_field_3                   ),\n    .i_register_5_bit_field_4_valid             (register_5_bit_field_4_valid             ),\n    .i_register_5_bit_field_4                   (register_5_bit_field_4[0]                ),\n    .o_register_5_bit_field_4                   (register_5_bit_field_4[1]                ),\n    .i_register_5_bit_field_5                   (register_5_bit_field_5[0]                ),\n    .o_register_5_bit_field_5                   (register_5_bit_field_5[1]                ),\n    .i_register_5_bit_field_6_enable            (register_5_bit_field_6_enable            ),\n    .o_register_5_bit_field_6                   (register_5_bit_field_6                   ),\n    .o_register_5_bit_field_7                   (register_5_bit_field_7                   ),\n    .o_register_5_bit_field_8                   (register_5_bit_field_8                   ),\n    .i_register_5_bit_field_9_lock              (register_5_bit_field_9_lock              ),\n    .o_register_5_bit_field_9                   (register_5_bit_field_9                   ),\n    .o_register_5_bit_field_10                  (register_5_bit_field_10                  ),\n    .o_register_5_bit_field_11                  (register_5_bit_field_11                  ),\n    .i_register_6_bit_field_0_set               (register_6_bit_field_0_set               ),\n    .o_register_6_bit_field_0                   (register_6_bit_field_0                   ),\n    .i_register_6_bit_field_1_set               (register_6_bit_field_1_set               ),\n    .o_register_6_bit_field_1                   (register_6_bit_field_1                   ),\n    .o_register_6_bit_field_1_unmasked          (register_6_bit_field_1_unmasked          ),\n    .i_register_6_bit_field_3_set               (register_6_bit_field_3_set               ),\n    .o_register_6_bit_field_3                   (register_6_bit_field_3                   ),\n    .i_register_6_bit_field_4_set               (register_6_bit_field_4_set               ),\n    .o_register_6_bit_field_4                   (register_6_bit_field_4                   ),\n    .o_register_6_bit_field_4_unmasked          (register_6_bit_field_4_unmasked          ),\n    .i_register_6_bit_field_6_clear             (register_6_bit_field_6_clear             ),\n    .o_register_6_bit_field_6                   (register_6_bit_field_6                   ),\n    .i_register_6_bit_field_7_clear             (register_6_bit_field_7_clear             ),\n    .o_register_6_bit_field_7                   (register_6_bit_field_7                   ),\n    .o_register_6_bit_field_8                   (register_6_bit_field_8                   ),\n    .o_register_6_bit_field_9                   (register_6_bit_field_9                   ),\n    .o_register_7_bit_field_0                   (register_7_bit_field_0                   ),\n    .o_register_7_bit_field_1                   (register_7_bit_field_1                   ),\n    .o_register_7_bit_field_2                   (register_7_bit_field_2                   ),\n    .o_register_7_bit_field_3                   (register_7_bit_field_3                   ),\n    .i_register_8_bit_field_0_set               (register_8_bit_field_0_set               ),\n    .o_register_8_bit_field_0                   (register_8_bit_field_0                   ),\n    .i_register_8_bit_field_1_clear             (register_8_bit_field_1_clear             ),\n    .o_register_8_bit_field_1                   (register_8_bit_field_1                   ),\n    .i_register_8_bit_field_2_set               (register_8_bit_field_2_set               ),\n    .o_register_8_bit_field_2                   (register_8_bit_field_2                   ),\n    .i_register_8_bit_field_3_clear             (register_8_bit_field_3_clear             ),\n    .o_register_8_bit_field_3                   (register_8_bit_field_3                   ),\n    .o_register_8_bit_field_4                   (register_8_bit_field_4                   ),\n    .o_register_8_bit_field_5                   (register_8_bit_field_5                   ),\n    .o_register_9_bit_field_0                   (register_9_bit_field_0                   ),\n    .o_register_9_bit_field_0_write_trigger     (),\n    .o_register_9_bit_field_0_read_trigger      (),\n    .i_register_9_bit_field_1                   (register_9_bit_field_1                   ),\n    .o_register_9_bit_field_1_read_trigger      (),\n    .o_register_9_bit_field_2                   (register_9_bit_field_2                   ),\n    .o_register_9_bit_field_2_write_trigger     (),\n    .o_register_9_bit_field_3                   (register_9_bit_field_3[0]                ),\n    .i_register_9_bit_field_3                   (register_9_bit_field_3[1]                ),\n    .o_register_9_bit_field_3_write_trigger     (),\n    .o_register_9_bit_field_3_read_trigger      (),\n    .i_register_9_bit_field_4                   (register_9_bit_field_4                   ),\n    .o_register_9_bit_field_4_trigger           (),\n    .i_register_9_bit_field_5                   (register_9_bit_field_5                   ),\n    .o_register_9_bit_field_5_trigger           (),\n    .o_register_10_bit_field_0                  (register_10_bit_field_0                  ),\n    .o_register_10_bit_field_1                  (register_10_bit_field_1                  ),\n    .o_register_10_bit_field_2                  (register_10_bit_field_2                  ),\n    .o_register_11_bit_field_0                  (register_11_bit_field_0                  ),\n    .o_register_11_bit_field_1                  (register_11_bit_field_1                  ),\n    .o_register_12_bit_field_0                  (register_12_bit_field_0                  ),\n    .o_register_12_bit_field_1                  (register_12_bit_field_1                  ),\n    .o_register_13_bit_field_0                  (register_13_bit_field_0                  ),\n    .i_register_13_bit_field_1                  (register_13_bit_field_1                  ),\n    .o_register_13_bit_field_2                  (register_13_bit_field_2                  ),\n    .o_register_13_bit_field_3                  (register_13_bit_field_3                  ),\n    .o_register_13_bit_field_3_write_trigger    (register_13_bit_field_3_write_trigger    ),\n    .o_register_13_bit_field_3_read_trigger     (register_13_bit_field_3_read_trigger     ),\n    .o_register_13_bit_field_4                  (register_13_bit_field_4                  ),\n    .o_register_13_bit_field_5                  (register_13_bit_field_5                  ),\n    .o_register_13_bit_field_6                  (register_13_bit_field_6                  ),\n    .i_register_13_bit_field_6_hw_clear         (register_13_bit_field_6_hw_clear         ),\n    .o_register_13_bit_field_7                  (register_13_bit_field_7                  ),\n    .i_register_13_bit_field_7_hw_set           (register_13_bit_field_7_hw_set           ),\n    .o_register_13_bit_field_8                  (register_13_bit_field_8                  ),\n    .i_register_13_bit_field_8_hw_write_enable  (register_13_bit_field_8_hw_write_enable  ),\n    .i_register_13_bit_field_8_hw_write_data    (register_13_bit_field_8_hw_write_data    ),\n    .i_register_14_bit_field_0_up               (register_0_bit_field_0[0]                ),\n    .i_register_14_bit_field_0_down             (register_0_bit_field_1[0]                ),\n    .i_register_14_bit_field_0_clear            (register_3_bit_field_3_trigger[0]        ),\n    .o_register_14_bit_field_0                  (register_14_bit_field_0                  ),\n    .i_register_14_bit_field_1_up               (register_0_bit_field_0[0]                ),\n    .i_register_14_bit_field_1_down             (register_0_bit_field_1[0]                ),\n    .i_register_15_bit_field_0                  (register_15_bit_field_0                  ),\n    .o_register_16_bit_field_0                  (register_16_bit_field_0                  ),\n    .o_register_17_bit_field_0                  (register_17_bit_field_0                  ),\n    .register_19_bus_if                         (register_19_bus_if                       )\n  );\n\n  rggen_apb_bridge u_bridge (\n    .i_clk    (clk                ),\n    .i_rst_n  (rst_n              ),\n    .bus_if   (register_19_bus_if ),\n    .apb_if   (apb_if[1]          )\n  );\n\n  block_1 u_block_1 (\n    .i_clk                                                    (clk                  ),\n    .i_rst_n                                                  (rst_n                ),\n    .apb_if                                                   (apb_if[1]            ),\n    .o_register_file_0_register_0_bit_field_0                 (),\n    .o_register_file_0_register_1_bit_field_0                 (),\n    .o_register_file_1_register_0_bit_field_0                 (),\n    .o_register_file_1_register_1_bit_field_0                 (),\n    .o_register_file_2_register_file_0_register_0_bit_field_0 (),\n    .o_register_file_2_register_file_0_register_0_bit_field_1 (),\n    .o_register_file_2_register_file_0_register_0_bit_field_2 (),\n    .o_register_file_2_register_file_0_register_1_bit_field_0 ()\n  );\nendmodule\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\nif not os.path.isdir(test_dir):\n    os.makedirs(test_dir, exist_ok=True)\n\nrggen_sample_path = os.path.abspath(\n    os.path.join(third_party_dir, \"cores\", \"rggen-sample\"))\nrggen_sv_rtl_path = os.path.abspath(\n    os.path.join(third_party_dir, \"cores\", \"rggen-sv-rtl\"))\n\nsources = ''\n\n\ndef is_valid_rggen_file(line):\n    if line.startswith(\"-f\"):\n        return False\n    elif re.search(r'axi|wishbone', line) is not None:\n        return False\n    else:\n        return True\n\n\nwith open(os.path.join(rggen_sv_rtl_path, \"compile.f\"), \"r\") as f:\n    for line in f.readlines():\n        if is_valid_rggen_file(line):\n            line = line.strip()\n            line = line.replace(\"${RGGEN_SV_RTL_ROOT}\", rggen_sv_rtl_path)\n            sources += line + \" \"\n\nsources += os.path.join(rggen_sample_path, \"block_0.sv\") + \" \"\nsources += os.path.join(rggen_sample_path, \"block_1.sv\") + \" \"\n\ntest_file = os.path.abspath(os.path.join(test_dir, \"rggen.sv\"))\nsources += test_file\n\nwith open(test_file, \"w\") as f:\n    f.write(templ.format(sources))\n    f.write(wrapper_tmpl)\n"
  },
  {
    "path": "generators/rsd",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\nimport glob\nimport re\n\ntempl = \"\"\"/*\n:name: rsd\n:description: Full RSD core test\n:files: {0}\n:incdirs: {1}\n:tags: rsd\n:top_module: Core\n:results_group: cores\n:timeout: 100\n*/\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\nrsd_path = os.path.abspath(\n    os.path.join(third_party_dir, \"cores\", \"rsd\", \"Processor\", \"Src\"))\nrsd_core_make = os.path.join(rsd_path, \"Makefiles\", \"CoreSources.inc.mk\")\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\nif not os.path.isdir(test_dir):\n    os.makedirs(test_dir, exist_ok=True)\n\ntest_file = os.path.join(test_dir, \"rsd.sv\")\n\nsources = os.path.abspath(test_file) + ' '\nincdirs = os.path.join(rsd_path, \"\") + ' '\n\nwith open(rsd_core_make, \"r\") as f:\n    in_source_list = False\n    for line in f.readlines():\n        line = re.sub(r\"#.+[\\n\\r]$\", \"\", line)  # Remove comments\n\n        # Find lines starting with \"TYPES|CORE_MODULES=\" and not ending with \"\\\".\n        m = re.search(r\"^(TYPES|CORE_MODULES)[\\s]*=(.+)$\", line)\n        if m:\n            line = m.group(2)  # Remove TYPES|CORE_MODULES=\n            in_source_list = True\n\n        if in_source_list:\n            # Find the end of source list\n            m = re.search(r\"\\\\[\\n\\r]*$\", line)\n            if not m:\n                in_source_list = False\n            # Remove backslash and spaces\n            line = re.sub(r\"\\\\[\\n\\r]*$\", \"\", line)\n            line = line.strip()\n            if (line != \"\"):\n                for i in line.split(r\"\\s+\"):\n                    sources += os.path.join(rsd_path, i) + ' '\n\nwith open(test_file, \"w\") as f:\n    f.write(templ.format(sources, incdirs))\n    f.write(\"`define RSD_SYNTHESIS\\n\")\n    f.write(\"`define RSD_SYNTHESIS_DESIGN_COMPILER\\n\")\n    f.write(\"`define RSD_MARCH_FP_PIPE\\n\")\n"
  },
  {
    "path": "generators/scr1",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\n\ntempl = \"\"\"/*\n:name: scr1\n:description: Full scr1 core test\n:files: {0}\n:incdirs: {1}\n:tags: scr1\n:top_module: scr1_top_tb_axi\n:results_group: cores\n:timeout: 100\n*/\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\nscr1_path = os.path.abspath(\n    os.path.join(third_party_dir, \"cores\", \"scr1\", \"src\"))\n\nflist = ['core.files', 'axi_top.files', 'axi_tb.files']\n\nsources = ''\nincdirs = ''\n\nfiles = []\nincludes = ['includes', 'tb']\n\nfor fname in flist:\n    with open(os.path.join(scr1_path, fname)) as f:\n        for line in f:\n            files += [line.strip()]\n\nfor sv in files:\n    sources += os.path.join(scr1_path, sv) + ' '\nfor inc in includes:\n    incdirs += os.path.join(scr1_path, inc) + ' '\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\nif not os.path.isdir(test_dir):\n    os.makedirs(test_dir, exist_ok=True)\n\ntest_file = os.path.join(test_dir, \"scr1.sv\")\n\nwith open(test_file, \"w\") as f:\n    f.write(templ.format(sources, incdirs))\n"
  },
  {
    "path": "generators/template_generator",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\nimport json\nimport glob\nimport itertools\n\ntry:\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\nname = ''\nfname = ''\ntempl = ''\nvals = []\n\nfor cfg in glob.glob(os.path.join(conf_dir, 'generators', 'templates',\n                                  '*.json')):\n    with open(cfg, 'r') as jf:\n        data = json.load(jf)\n        name = data['name']\n        fname = data['filename']\n        if 'template' in data.keys():\n            templ = '\\n'.join(data['template'])\n        elif 'template_file' in data.keys():\n            try:\n                with open(os.path.join(conf_dir, 'generators', 'templates',\n                                       data['template_file']), 'r') as t:\n                    templ = t.read()\n            except FileNotFoundError:\n                print(\"Template file \" + data['template_file'] + \" not found\")\n                sys.exit(1)\n        else:\n            print(\"No template or template_file specified \")\n            sys.exit(1)\n\n        vals = data['values']\n\n        if data.get('cartesian_product', False):\n            prod = list(itertools.product(*vals))\n            vals = [x[0] + x[1] for x in prod]\n\n    test_dir = os.path.join(tests_dir, 'generated', name)\n\n    if not os.path.isdir(test_dir):\n        os.makedirs(test_dir, exist_ok=True)\n\n    for idx, val in enumerate(vals):\n        test_file = os.path.join(test_dir, fname.format(*val, idx))\n        with open(test_file, \"w\") as wf:\n            wf.write(templ.format(*val, idx))\n"
  },
  {
    "path": "generators/tnoc",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\nimport glob\n\ntempl = \"\"\"/*\n:name: TNoC\n:description: Full TNoC core test\n:files: {0}\n:tags: TNoC\n:top_module: tnoc\n:results_group: cores\n:timeout: 100\n*/\n\"\"\"\n\nwrapper_tmpl = \"\"\"\nmodule tnoc (\n  input var i_clk,\n  input var i_rst_n\n);\n  import  tnoc_pkg::*;\n\n  localparam  tnoc_packet_config  PACKET_CONFIG = '{\n    size_x:           3,\n    size_y:           3,\n    virtual_channels: 2,\n    tags:             32,\n    address_width:    64,\n    data_width:       64,\n    max_data_width:   64,\n    max_byte_length:  32 * (64 / 8)\n  };\n\n  tnoc_types #(PACKET_CONFIG)   types();\n  tnoc_flit_if #(PACKET_CONFIG) receiver_if[9](types);\n  tnoc_flit_if #(PACKET_CONFIG) sender_if[9](types);\n\n  tnoc_fabric #(PACKET_CONFIG) u_fabric (.*);\nendmodule\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\nif not os.path.isdir(test_dir):\n    os.makedirs(test_dir, exist_ok=True)\n\ntnoc_path = os.path.abspath(os.path.join(third_party_dir, \"cores\", \"tnoc\"))\ntbcm_path = os.path.join(tnoc_path, \"rtl\", \"bcm\")\ntnoc_file_lists = [\n    os.path.join(tbcm_path, \"compile.f\"),\n    os.path.join(tnoc_path, \"rtl\", \"common\", \"compile.f\"),\n    os.path.join(tnoc_path, \"rtl\", \"router\", \"compile.f\"),\n    os.path.join(tnoc_path, \"rtl\", \"fabric\", \"compile.f\")\n]\n\nsources = ''\n\nfor file_list in tnoc_file_lists:\n    with open(file_list, \"r\") as f:\n        for line in f.readlines():\n            sources += line.strip() + \" \"\n\nsources = sources.replace(\"${TBCM_HOME}\", tbcm_path)\nsources = sources.replace(\"${TNOC_HOME}\", tnoc_path)\n\ntest_file = os.path.abspath(os.path.join(test_dir, \"tnoc.sv\"))\nsources += test_file\n\nwith open(test_file, \"w\") as f:\n    f.write(templ.format(sources))\n    f.write(wrapper_tmpl)\n"
  },
  {
    "path": "generators/veer-config",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\nimport subprocess\n\nvariants = [\n    {\n        \"test_type\": \"sim\",\n        \"name\": \"veer-el2\",\n        \"description\": \"Full VeeR EL2 core test\",\n        \"top_module\": \"tb_top\",\n        \"tags\": \"veer-el2\",\n        \"compatible-runners\": \"verilator slang\",\n        \"type\": \"parsing elaboration simulation_without_run\",\n    },\n    {\n        \"test_type\": \"synth\",\n        \"name\": \"veer-el2\",\n        \"description\": \"Full VeeR EL2 core test\",\n        \"top_module\": \"veer-el2_wrapper\",\n        \"tags\": \"veer-el2\",\n        \"compatible-runners\":\n        \"yosys-synlig yosys yosys-sv zachjs-sv2v icarus moore moore-parse odin sv-parser tree-sitter-verilog verible verible_extractor Surelog slang-parse\",\n        \"type\": \"parsing elaboration\",\n    },\n]\n\ntempl = \"\"\"/*\n:name: {0}\n:description: {1}\n:files: {2}\n:incdirs: {3}\n:top_module: {4}\n:tags: {5}\n:timeout: 1000\n:results_group: cores\n:compatible-runners: {6}\n:type: {7}\n{8}\n*/\n\"\"\"\n\ntry:\n    tests_dir = os.environ['TESTS_DIR']\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\nexcept KeyError:\n    print(\"Export the TESTS_DIR and THIRD_PARTY_DIR variables first\")\n    print(os.environ)\n    sys.exit(1)\n\nfor v in variants:\n    test_type = v[\"test_type\"]\n    name = v[\"name\"]\n    description = v[\"description\"]\n    top_module = v[\"top_module\"]\n    tags = v[\"tags\"]\n    compatible_runners = v[\"compatible-runners\"]\n    type = v[\"type\"]\n    include_dir = os.path.abspath(\n        os.path.join(third_party_dir, \"cores\", name, \"design\", \"include\"))\n    testbench_dir = os.path.abspath(\n        os.path.join(third_party_dir, \"cores\", name, \"testbench\"))\n    build_dir = os.path.abspath(\n        os.path.join(\n            tests_dir, \"generated\", \"veer-config\", name + \"_\" + test_type))\n    os.environ[\"BUILD_PATH\"] = build_dir\n    os.makedirs(build_dir, exist_ok=True)\n\n    # Generate VeeR config headers\n    veer_config = os.path.join(\n        third_party_dir, \"cores\", name, \"configs\", \"veer.config\")\n    ret = subprocess.run([veer_config], capture_output=True)\n\n    if ret.returncode != 0:\n        print(ret.stderr)\n        print(\"VeeR configuration failed!\")\n        exit(ret.returncode)\n\n    sources = \"\"\n    # Insert common configuration headers before common VeeR sources\n    common_defines = os.path.abspath(\n        os.path.join(build_dir, \"common_defines.vh\"))\n    el2_pdef = os.path.abspath(os.path.join(build_dir, \"el2_pdef.vh\"))\n    sources += common_defines + \" \" + el2_pdef + \" \"\n\n    # Setup common VeeR sources\n    for (dirpath, dirnames, filenames) in os.walk(os.path.join(third_party_dir,\n                                                               \"cores\", name,\n                                                               \"design\")):\n        if dirpath.endswith(\"include\"):\n            continue\n        for f in filenames:\n            if f.endswith((\"sv\", \"v\")):\n                sources += os.path.abspath(os.path.join(dirpath, f)) + \" \"\n\n    # Setup simulation specific sources and verilator args\n    incdirs = build_dir + \" \" + include_dir\n    extra_args = \"\"\n    if test_type == \"sim\":\n        incdirs += \" \" + testbench_dir\n        for (dirpath, dirnames,\n             filenames) in os.walk(os.path.join(third_party_dir, \"cores\", name,\n                                                \"testbench\")):\n            if 'uvm' in dirnames:\n                # Skip uvm dir as it uses a custom Makefile\n                dirnames.remove('uvm')\n\n            for f in filenames:\n                if 'axi_crossbar_wrap_2x1' in f:\n                    # Skip this file as it's unused without a specific define\n                    # and contains invalid syntax that can cause tools to fail\n                    continue\n\n                if f.endswith((\"sv\", \"v\")):\n                    sources += os.path.abspath(os.path.join(dirpath, f)) + \" \"\n\n        extra_args += \":runner_verilator_flags:\"\n        extra_args += \" -CFLAGS -I\" + build_dir\n        extra_args += \" -CFLAGS -I\" + include_dir\n        extra_args += \" -CFLAGS -I\" + testbench_dir\n        extra_args += \" -Wno-WIDTH\"\n\n        with open(common_defines, 'a') as cdf:\n            cdf.write(\"`undef RV_ASSERT_ON\")\n\n    # Insert VeeR includes before other sources\n    for (dirpath, dirnames,\n         filenames) in os.walk(os.path.join(third_party_dir, \"cores\", name,\n                                            \"design\", \"include\")):\n        for f in filenames:\n            if f.endswith((\"sv\", \"v\")):\n                sources = os.path.abspath(\n                    os.path.join(dirpath, f)) + \" \" + sources\n\n    # Write generated test to a file\n    test_file = os.path.join(build_dir, name + \"_\" + test_type + \".sv\")\n    with open(test_file, \"w\") as tf:\n        tf.write(\n            templ.format(\n                name, description, sources, incdirs, top_module, tags,\n                compatible_runners, type, extra_args))\n"
  },
  {
    "path": "generators/yosys_hana",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\nimport glob\n\ntempl = \"\"\"/*\n:name: {1}\n:description: Tests imported from yosys\n:files: {0}\n:results_group: imported\n:tags: yosys\n*/\n\"\"\"\n\ntry:\n    third_party_dir = os.environ['THIRD_PARTY_DIR']\n    tests_dir = os.environ['TESTS_DIR']\n    conf_dir = os.environ['CONF_DIR']\nexcept KeyError:\n    print(\"Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first\")\n    sys.exit(1)\n\ntry:\n    tests_subdir = sys.argv[1]\nexcept IndexError:\n    print(\"Usage: ./generator <subdir>\")\n    sys.exit(1)\n\nyosys_path = os.path.abspath(os.path.join(third_party_dir, \"tools\", \"yosys\"))\nhana_vlib = os.path.join(yosys_path, 'tests', 'hana', 'hana_vlib.v')\n\ntest_dir = os.path.join(tests_dir, 'generated', tests_subdir)\n\nif not os.path.isdir(test_dir):\n    os.makedirs(test_dir, exist_ok=True)\n\nfor f in glob.glob(os.path.join(yosys_path, 'tests', 'hana', 'test*.v')):\n    # test_parser has invalid syntax\n    if 'test_parser.v' in f:\n        continue\n\n    fname = 'hana_' + os.path.basename(os.path.splitext(f)[0])\n    test_file = os.path.join(test_dir, fname + '.sv')\n\n    with open(test_file, \"w\") as sv:\n        sv.write(templ.format(f + ' ' + hana_vlib, fname))\n"
  },
  {
    "path": "tests/README.md",
    "content": "# Tests\n\nThis directory contains various tests.\nThe tests are divided into various directories.\n\n## Chapter tests\n\nThe purpose of these tests is to verify individual features of each LRM chapter (and subchapters).\nThey are minimal by design and when possible, test an isolated SystemVerilog construct.\n\n## Generated tests\n\nSome of the tests are not stored directly in the repositories, but dynamically generated using various scripts.\nThe `make generate` target runs all the generators.\nIt creates a `generated` directory alongside the directories for each chapter and puts the generated test cases inside it.\n\nThe generators are stored in the [generators](https://github.com/SymbiFlow/sv-tests/tree/master/generators) directory.\nThe configuration for generators is stored in the [conf/generators](https://github.com/SymbiFlow/sv-tests/tree/master/conf/generators) directory.\n\nThere are various types of generators.\nSome generate fairly simple tests, but does so in a bulk to generate multiple similar tests.\nAn example of this would be the [template generator](https://github.com/SymbiFlow/sv-tests/blob/master/generators/template_generator).\nIt has a multitude of various configs, one interesting example would be the [logical operators](https://github.com/SymbiFlow/sv-tests/blob/master/conf/generators/templates/logical.json) tests.\n\nSome generators generate more sophisticated test cases.\nThese can for example be tests of full blown soft cores.\nAn example of this would be the [BlackParrot](https://github.com/SymbiFlow/sv-tests/blob/master/generators/black-parrot) generator.\nIt generates a wrapper which makes it possible to use BlackParrot as a test.\n\n## UVM tests\n\nThe repository contains multiple tests dedicated to verifying UVM support of various tools.\n\nThe source code of UVM is stored in the [third party](https://github.com/SymbiFlow/sv-tests/tree/master/third_party/tests) directory.\nThe tests that want to include it need to include the `uvm` tag on the list of their tags.\n\nThe tests that use UVM are stored in various places, for example:\n\n* Multiple tests are stored in the [testbenches](https://github.com/SymbiFlow/sv-tests/tree/master/tests/testbenches) directory.\n* Some UVM tests are stored in the chapters directories, mostly chapter-16 and chapter-18.\n* There is a test generator for [EasyUVM](https://github.com/SymbiFlow/sv-tests/blob/master/generators/easyUVM).\n* There are multiple UVM tests that use the template generator (see the ``uvm*`` files in the [conf](https://github.com/SymbiFlow/sv-tests/blob/master/conf/generators/templates/) directory).\n"
  },
  {
    "path": "tests/chapter-10/10.3--proc-assignment--bad.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: proc_assignment__bad\n:description: continuous assignment with delay test\n:should_fail_because: Illegal to procedurally assign to wire, IEEE Table 10-1\n:tags: 10.3\n:type: simulation elaboration\n*/\nmodule top(input a, input b);\n\nwire w;\n\n// Illegal to procedurally assign to wire, IEEE Table 10-1\ninitial\n\tw = #10 a & b;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-10/10.3.1--net-decl-assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: net_decl_assignment\n:description: net declaration assignment test\n:tags: 10.3.1\n*/\nmodule top(input a, input b);\n\nwire w = a & b;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-10/10.3.1--one-net.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: one_net_assign\n:description: simple net declaration assignment test\n:tags: 10.3.1\n:type: simulation elaboration parsing\n*/\nmodule top(input a, output b);\n\nassign b = a;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-10/10.3.2--cont-assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cont_assignment\n:description: continuous assignment test\n:tags: 10.3.2\n*/\nmodule top(input a, input b);\n\nwire w;\nassign w = a & b;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-10/10.3.3--cont-assignment-delay.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cont_assignment_delay\n:description: continuous assignment with delay test\n:tags: 10.3.3\n*/\nmodule top(input a, input b);\n\nwire w;\n\nassign #10 w = a & b;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-10/10.3.3--cont-assignment-net-delay.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cont_assignment_net_delay\n:description: continuous assignment with net delay test\n:tags: 10.3.3\n*/\nmodule top(input a, input b);\n\nwire #10 w;\n\nassign w = a & b;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-10/10.4.1--blocking-assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: blocking_assignment\n:description: blocking assignment test\n:tags: 10.4.1\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nlogic a = 3;\nlogic b = 2;\n\ninitial begin\n\ta = 1;\n\tb = a;\n\t$display(\":assert: (%d == %d)\", a, b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-10/10.4.2--non-blocking-assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: non_blocking_assignment\n:description: non-blocking assignment test\n:tags: 10.4.2\n*/\nmodule top();\n\nlogic a;\n\ninitial begin\n\ta <= 2;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-10/10.6.1--assign-deassign.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assign_deassign\n:description: assign-deassign statements test\n:tags: 10.6.1\n*/\nmodule top(clk, q, d, clr, set);\n\ninput clk, d, clr, set;\noutput q;\nlogic q;\n\nalways @(clr or set)\n\tif (clr)\n\t\tassign q = 0;\n\telse if (set)\n\t\tassign q = 1;\n\telse\n\t\tdeassign q;\n\nalways @(posedge clk)\n\tq <= d;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-10/10.6.2--force-release.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: force_release\n:description: force-release statements test\n:tags: 10.6.2\n*/\nmodule flop(clk, q, d);\n\ninput clk, d;\noutput q;\nlogic q;\n\nalways @(posedge clk)\n  q <= d;\n\nendmodule\n\nmodule top(clk, q, d, f1, f0);\n\ninput clk, d, f1, f0;\noutput q;\nwire q;\n\nflop u_flop (.*);\n\nalways @(f1 or f0)\n  if (f0)\n    force u_flop.q = 0;\n  else if (f1)\n    force u_flop.q = 1;\n  else\n    release u_flop.q;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.10--string_bit_array-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_bit_array_sim\n:description: string stored in bit array simulation test\n:type: simulation elaboration parsing\n:tags: 11.10\n*/\nmodule top();\n\nbit [8*14:1] a;\n\ninitial begin\n\ta = \"Test\";\n    $display(\":assert: ('Test' == '%0s')\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.10--string_bit_array.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_bit_array\n:description: string stored in bit array test\n:tags: 11.10\n*/\nmodule top();\n\nbit [8*14:1] a;\n\ninitial begin\n\ta = \"Test\";\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.10.1--string_compare.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_compare\n:description: string comparison test\n:type: simulation elaboration parsing\n:tags: 11.10.1\n*/\nmodule top();\n\nbit [8*14:1] a;\nbit [8*14:1] b;\n\ninitial begin\n\ta = \"Test\";\n\tb = \"Test\";\n\t$display(\":assert:('%s' == '%s')\", a, b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.10.1--string_concat.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_concat\n:description: string concatenation test\n:type: simulation elaboration parsing\n:tags: 11.10.1\n*/\nmodule top();\n\nbit [8*14:1] a;\nbit [8*14:1] b;\n\ninitial begin\n\ta = \"Test\";\n\tb = \"TEST\";\n\t$display(\":assert: ('TEST' in '%s')\", {a, b});\n\t$display(\":assert: ('Test' in '%s')\", {a, b});\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.10.1--string_copy.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_copy\n:description: string copy test\n:type: simulation elaboration parsing\n:tags: 11.10.1\n*/\nmodule top();\n\nbit [8*14:1] a;\nbit [8*14:1] b;\n\ninitial begin\n\ta = \"Test\";\n\tb = a;\n\t$display(\":assert:('%s' == '%s')\", a, b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.10.3--empty_string-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: empty_string_sim\n:description: empty string simulation test\n:type: simulation elaboration parsing\n:tags: 11.10.3\n*/\nmodule top();\n\nbit [8*14:1] a;\n\ninitial begin\n\ta = \"\";\n    $display(\":assert: (1 == %d)\", a == 0);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.10.3--empty_string.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: empty_string\n:description: empty string test\n:tags: 11.10.3\n*/\nmodule top();\n\nbit [8*14:1] a;\n\ninitial begin\n\ta = \"\";\n\tassert(a == 0);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.11--min_max_avg_delay.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: min_max_avg_delay\n:description: minimum, typical and maximum delay expressions test\n:tags: 11.11\n*/\nmodule top();\n\ninitial begin\n\t#(100:200:300) $display(\"Done\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.12--let_construct.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: let_construct\n:description: let construct test\n:tags: 11.12\n*/\nmodule top();\n\nlogic [3:0] a = 12;\nlogic [3:0] b = 15;\nlogic [3:0] c = 7;\nlogic d;\n\nlet op(x, y, z) = |((x | y) & z);\n\ninitial begin\n\td = op(.x(a), .y(b), .z(c));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.3.5--expr_short_circuit.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: expr_short_circuit\n:description: expression short circuiting test\n:type: simulation elaboration parsing\n:tags: 11.3.5\n*/\nmodule top();\n\nlogic a = 1;\nlogic b = 1;\nlogic c = 0;\nlogic d;\n\nfunction int fun(logic a);\n    $display(\":assert: (False)\");\n\treturn a;\nendfunction\n\ninitial begin\n    d = a && (b || fun(c));\n    $display(\":assert: (1 == %d)\", d);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--assign_in_exp-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\r\n:name: assign_in_exp_sim\r\n:description: assignment in expression simulation test\r\n:type: simulation elaboration parsing\r\n:tags: 11.3.6\r\n*/\r\nmodule top();\r\n\r\nint a;\r\nint b;\r\nint c;\r\n\r\ninitial begin\r\n        c = a;\r\n        b = (a-=1);\r\n        $display(\":assert: (%d == %d)\", b, (c-1));\r\nend\r\n\r\nendmodule\r\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--assign_in_exp.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\r\n:name: assign_in_exp\r\n:description: assignment in expression test\r\n:tags: 11.3.6\r\n*/\r\nmodule top();\r\n\r\nint a;\r\nint b;\r\n\r\ninitial begin\r\n        b = (a-=1);\r\nend\r\n\r\nendmodule\r\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--assign_in_expr-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assign_in_expr_sim\n:description: assignment in expression simulation test\n:type: simulation elaboration parsing\n:tags: 11.3.6\n*/\nmodule top();\n\nint a;\nint b;\nint c;\n\ninitial begin\n\ta = (b = (c = 5));\t\n    $display(\":assert: (5 == %d)\", a);\n    $display(\":assert: (5 == %d)\", b);\n    $display(\":assert: (5 == %d)\", c);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--assign_in_expr.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assign_in_expr\n:description: assignment in expression test\n:tags: 11.3.6\n*/\nmodule top();\n\nint a;\nint b;\nint c;\n\ninitial begin\n\ta = (b = (c = 5));\t\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--assign_in_expr_inv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assign_in_expr_inv\n:description: invalid assignment in expression test\n:should_fail_because: blocking assignments within expression must be enclosed in parentheses\n:tags: 11.3.6\n*/\nmodule top();\n\nint a;\nint b;\nint c;\n\ninitial begin\n\ta = b = c = 5;\t\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--assign_in_expression-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\r\n:name: assign_in_expression_sim\r\n:description: assignment in expression simulation test\r\n:type: simulation elaboration parsing\r\n:tags: 11.3.6\r\n*/\r\nmodule top();\r\n\r\nint a;\r\nint b;\r\nint c;\r\n\r\ninitial begin\r\n        c = a;\r\n        b = (++a);\r\n        $display(\":assert: (%d == %d)\", b, (c+1));\r\nend\r\n\r\nendmodule\r\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--assign_in_expression.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\r\n:name: assign_in_expression\r\n:description: assignment in expression test\r\n:tags: 11.3.6\r\n*/\r\nmodule top();\r\n\r\nint a;\r\nint b;\r\n\r\ninitial begin\r\n        b = (++a);\r\nend\r\n\r\nendmodule\r\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--assignment_in_expression-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\r\n:name: assignment_in_expression_sim\r\n:description: assignment in expression simulation test\r\n:type: simulation elaboration parsing\r\n:tags: 11.3.6\r\n*/\r\nmodule top();\r\n\r\nint a;\r\nint b;\r\nint c;\r\n\r\ninitial begin\r\n        c = a;\r\n        b = (a+=1);\r\n        $display(\":assert: (%d == %d)\", b, (c+1));\r\nend\r\n\r\nendmodule\r\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--assignment_in_expression.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\r\n:name: assignment_in_expression\r\n:description: assignment in expression test\r\n:tags: 11.3.6\r\n*/\r\nmodule top();\r\n\r\nint a;\r\nint b;\r\n\r\ninitial begin\r\n        b = (a+=1);\r\nend\r\n\r\nendmodule\r\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--two_assign_in_expr-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\r\n:name: two_assignments_in_expression_sim\r\n:description: assignment in expression simulation test\r\n:type: simulation elaboration parsing\r\n:tags: 11.3.6\r\n*/\r\nmodule top();\r\n\r\nint a;\r\nint b;\r\nint c;\r\nint d;\r\nint e;\r\n\r\ninitial begin\r\n        c = a;\r\n        e = b;\r\n        d = ((b += (a+=1) + 1));\r\n        $display(\":assert: (%d == %d)\", b, (e+c+2));\r\n        $display(\":assert: (%d == %d)\", d, (e+c+2));\r\nend\r\n\r\nendmodule\r\n"
  },
  {
    "path": "tests/chapter-11/11.3.6--two_assign_in_expr.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\r\n:name: two_assignments_in_expression\r\n:description: assignment in expression test\r\n:tags: 11.3.6\r\n*/\r\nmodule top();\r\n\r\nint a;\r\nint b;\r\nint c;\r\nint d;\r\nint e;\r\n\r\ninitial begin\r\n        c = a;\r\n        e = b;\r\n        d = ((b += (a+=1) + 1));\r\nend\r\n\r\nendmodule\r\n"
  },
  {
    "path": "tests/chapter-11/11.4.1--assignment-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assignment_sim\n:description: assignment simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.1\n*/\nmodule top();\nreg [3:0] a;\nreg [3:0] b;\ninitial begin\n    a = 4'd12;\n    b = 4'd5;\n    $display(\":assert: (12 == %d)\", a);\n    a = b;\n    $display(\":assert: (5 == %d)\", a);\nend\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.10--arith-shift-assignment-signed.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arith_shift_assignment_signed\n:description: arithmetic shift assignment operator test\n:type: simulation elaboration parsing\n:tags: 11.4.10\n*/\nmodule top();\n\nlogic signed [7:0] a, b, c;\n\ninitial begin\n    a = -120; // 128 + 8\n    b = a;\n    c = a;\n    b <<<= 3;\n    c >>>= 3;\n\n    $display(\":assert: (  64 == %d)\", b);\n    $display(\":assert: ( -15 == %d)\", c);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.10--arith-shift-assignment-unsigned.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arith_shift_assignment_unsigned\n:description: arithmetic shift assignment operator test\n:type: simulation elaboration parsing\n:tags: 11.4.10\n*/\nmodule top();\n\nlogic [7:0] a, b, c;\n\ninitial begin\n    a = 8;\n    b = a;\n    c = a;\n    b <<<= 3;\n    c >>>= 3;\n\n    $display(\":assert: (64 == %d)\", b);\n    $display(\":assert: (1 == %d)\", c);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.10--arith-shift-signed.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arith_shift_signed\n:description: arithmetic shift operator test\n:type: simulation elaboration parsing\n:tags: 11.4.10\n*/\nmodule top();\n\nlogic signed [7:0] a, b, c;\n\ninitial begin\n    a = -120; // 128 + 8\n    b = (a <<< 3);\n    c = (a >>> 3);\n\n    $display(\":assert: (  64 == %d)\", b);\n    $display(\":assert: ( -15 == %d)\", c);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.10--arith-shift-unsigned.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arith_shift_unsigned\n:description: arithmetic shift operator test\n:type: simulation elaboration parsing\n:tags: 11.4.10\n*/\nmodule top();\n\nlogic [7:0] a, b, c;\n\ninitial begin\n    a = 8;\n    b = (a <<< 3);\n    c = (a >>> 3);\n\n    $display(\":assert: (64 == %d)\", b);\n    $display(\":assert: (1 == %d)\", c);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.11--cond_op-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cond_op_sim\n:description: ?: operator simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.11\n*/\nmodule top();\n\nint a = 12;\nint b = 5;\nint c;\n\ninitial begin\n\tc = (a > b) ? 11 : 13;\n    $display(\":assert: (11 == %d)\", c);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.11--cond_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cond_op\n:description: ?: operator test\n:tags: 11.4.11\n*/\nmodule top();\n\nint a = 12;\nint b = 5;\nint c;\n\ninitial begin\n\tc = (a > b) ? 11 : 13;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.12--concat_op-bit_select.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: concat_op-bit_select\n:description: concatenation operator w/ bit selection test\n:tags: 11.4.12\n*/\nmodule top();\n\n  bit [3:0] a;\n\n  bit [7:0] b = 8'b10101100;\n  bit [7:0] c = 8'b01010011;\n\n  initial begin\n\ta = {b, c}[9:6];\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.12--concat_op-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: concat_op_sim\n:description: concatenation operator simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.12\n*/\nmodule top();\n\nbit [15:0] a;\n\nbit [7:0] b = 8'h89;\nbit [7:0] c = 8'h12;\n\ninitial begin\n\ta = {b, c};\n    $display(\":assert: (0x8912 == %d)\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.12--concat_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: concat_op\n:description: concatenation operator test\n:tags: 11.4.12\n*/\nmodule top();\n\nbit [15:0] a;\n\nbit [7:0] b = 8'b10101100;\nbit [7:0] c = 8'b01010011;\n\ninitial begin\n\ta = {b, c};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.12.1--nested_repl_op-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: nested_repl_op_sim\n:description: nested replication operator simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.12.1\n*/\nmodule top();\n\nbit [15:0] a;\n\nbit [1:0] b = 2'b10;\nbit [1:0] c = 2'b01;\nbit [3:0] d = 4'b1111;\n\ninitial begin\n\ta = {{3{b, c}}, d};\n    $display(\":assert: (0b1001100110011111 == %d)\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.12.1--nested_repl_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: nested_repl_op\n:description: nested replication operator test\n:tags: 11.4.12.1\n*/\nmodule top();\n\nbit [15:0] a;\n\nbit [1:0] b = 2'b10;\nbit [1:0] c = 2'b01;\nbit [3:0] d = 4'b1111;\n\ninitial begin\n\ta = {{3{b, c}}, d};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.12.1--repl_op-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: repl_op_sim\n:description: replication operator simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.12.1\n*/\nmodule top();\n\nbit [15:0] a;\n\nbit [1:0] b = 2'b10;\n\ninitial begin\n\ta = {8{b}};\n    $display(\":assert: (0b1010101010101010 == %d)\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.12.1--repl_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: repl_op\n:description: replication operator test\n:tags: 11.4.12.1\n*/\nmodule top();\n\nbit [15:0] a;\n\nbit [1:0] b = 2'b10;\n\ninitial begin\n\ta = {8{b}};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.12.2--string_concat_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_concat_op\n:description: string concatenation operator test\n:tags: 11.4.12.2\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nstring str;\n\ninitial begin\n\tstr = {\"Hello\", \"_\", \"World\", \"!\"};\n\t$display(\":assert:('%s' == 'Hello_World!')\", str);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.12.2--string_repl_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_repl_op\n:description: string replication operator test\n:tags: 11.4.12.2\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nstring str;\n\ninitial begin\n\tstr = {4{\"test\"}};\n\t$display(\":assert:('%s' == 'testtesttesttest')\", str);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.13--set_member-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: set_member_sim\n:description: inside operator simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.13\n*/\nmodule top();\n\nint a = 12;\n\ninitial begin\n    $display(\":assert: (1 == %d)\", a inside {2, 4, 6, 8, 10, 12});\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.13--set_member.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: set_member\n:description: inside operator test\n:tags: 11.4.13\n*/\nmodule top();\n\nint a;\nint b = 12;\nlocalparam c = 5;\nlocalparam d = 7;\n\ninitial begin\n\ta = b inside {c, d};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.1--stream_concat-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: stream_concat_sim\n:description: stream concatenation simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.14.1\n*/\nmodule top();\n\nint a = {\"A\", \"B\", \"C\", \"D\"};\nint b = {\"E\", \"F\", \"G\", \"H\"};\nlogic [63:0] c;\n\ninitial begin\n\tc = {>> 8 {a, b}};\n    $display(\":assert: (((%d << 32) + %d) == %d) \", a, b, c);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.1--stream_concat.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: stream_concat\n:description: stream concatenation test\n:tags: 11.4.14.1\n*/\nmodule top();\n\nint a = {\"A\", \"B\", \"C\", \"D\"};\nint b = {\"E\", \"F\", \"G\", \"H\"};\nlogic [63:0] c;\n\ninitial begin\n\tc = {>> 8 {a, b}};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.2--reorder_stream-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: reorder_stream_sim\n:description: stream reordering simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.14.2\n*/\nmodule top();\n\nint a = {\"A\", \"B\", \"C\", \"D\"};\nint b;\n\ninitial begin\n\tb = {<< 8 {a}};\n    $display(\":assert: (0x44434241 == 0x%x)\", b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.2--reorder_stream.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: reorder_stream\n:description: stream reordering test\n:tags: 11.4.14.2\n*/\nmodule top();\n\nint a = {\"A\", \"B\", \"C\", \"D\"};\nint b;\n\ninitial begin\n\tb = {<< 8 {a}};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.2--reorder_stream_byte-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: reorder_stream_byte_sim\n:description: stream reordering simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.14.2\n*/\nmodule top();\n\nint a = {\"A\", \"B\", \"C\", \"D\"};\nint b;\n\ninitial begin\n\tb = {<< byte {a}};\n    $display(\":assert: (0x44434241 == 0x%x)\", b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.2--reorder_stream_byte.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: reorder_stream_byte\n:description: stream reordering test\n:tags: 11.4.14.2\n*/\nmodule top();\n\nint a = {\"A\", \"B\", \"C\", \"D\"};\nint b;\n\ninitial begin\n\tb = {<< byte {a}};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.3--unpack_stream-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpack_stream_sim\n:description: stream unpack simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.14.3\n*/\nmodule top();\n\nint a = 1;\nint b = 2;\nint c = 3;\n\ninitial begin\n\tbit [95:0] d = {<< 32 {a, b, c}};\n    $display(\":assert: (((%d << 64) + (%d << 32) + %d) == %d)\", c, b, a, d);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.3--unpack_stream.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpack_stream\n:description: stream unpack test\n:tags: 11.4.14.3\n*/\nmodule top();\n\nint a = 1;\nint b = 2;\nint c = 3;\n\ninitial begin\n\tbit [95:0] d = {<<{a, b, c}};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.3--unpack_stream_inv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpack_stream_inv\n:description: invalid stream unpack test\n:should_fail_because: stream is wider than assignment target\n:tags: 11.4.14.3\n:runner_verilator_flags: -Werror-WIDTH\n:type: simulation elaboration\n*/\nmodule top();\n\nint a = 1;\nint b = 2;\nint c = 3;\n\ninitial begin\n\tint d = {<<{a, b, c}};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.3--unpack_stream_pad-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpack_stream_pad_sim\n:description: padded stream unpack simulation test\n:type: simulation elaboration parsing\n:tags: 11.4.14.3\n*/\nmodule top();\n\nint a = 1;\nint b = 2;\nint c = 3;\n\nbit ok;\n\ninitial begin\n    bit [127:0] d = {<< 32 {a, b, c}};\n    ok = d == 128'h00000003_00000002_00000001_00000000;\n    $display(\":assert: (%0d == %0d)\", ok, 1);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.3--unpack_stream_pad.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpack_stream_pad\n:description: padded stream unpack test\n:tags: 11.4.14.3\n*/\nmodule top();\n\nint a = 1;\nint b = 2;\nint c = 3;\n\ninitial begin\n\tbit [127:0] d = {<<{a, b, c}};\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.4--dynamic_array_stream-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dynamic_array_unpack_stream_sim\n:description: stream unpack simulation test with dynamic array\n:type: simulation elaboration parsing\n:tags: 11.4.14.4\n:unsynthesizable: 1\n*/\nmodule top();\n\nint i_header;\nint i_len;\nbyte i_data[];\nint i_crc;\n\nint o_header;\nint o_len;\nbyte o_data[];\nint o_crc;\n\ninitial begin\n\tbyte pkt[$];\n\n\ti_header = 12;\n\ti_len = 5;\n\ti_crc = 42;\n\ti_data = new[5];\n\n    i_data[0] = 1;\n    i_data[1] = 2;\n    i_data[2] = 3;\n    i_data[3] = 4;\n    i_data[4] = 5;\n\n\tpkt = {<< 8 {i_header, i_len, i_crc, i_data}};\n\n\t{<< 8 {o_header, o_len, o_crc, o_data}} = pkt;\n\n    $display(\":assert: (12 == %d)\", o_header);\n    $display(\":assert: (5 == %d)\", o_len);\n    $display(\":assert: (42 == %d)\", o_crc);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.4--dynamic_array_stream.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dynamic_array_unpack_stream\n:description: stream unpack test with dynamic array\n:tags: 11.4.14.4\n:unsynthesizable: 1\n*/\nmodule top();\n\nint i_header;\nint i_len;\nbyte i_data[];\nint i_crc;\n\nint o_header;\nint o_len;\nbyte o_data[];\nint o_crc;\n\ninitial begin\n\tbyte pkt[$];\n\n\ti_header = 12;\n\ti_len = 5;\n\ti_data = new[5];\n\ti_crc = 42;\n\n\tpkt = {<< 8 {i_header, i_len, i_data, i_crc}};\n\n\t{<< 8 {o_header, o_len, o_data, o_crc}} = pkt;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.14.4--dynamic_array_stream_with.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dynamic_array_unpack_stream_with\n:description: stream unpack test with dynamic array using with\n:tags: 11.4.14.4\n:unsynthesizable: 1\n*/\nmodule top();\n\nint i_header;\nint i_len;\nbyte i_data[];\nint i_crc;\n\nint o_header;\nint o_len;\nbyte o_data[];\nint o_crc;\n\ninitial begin\n\tbyte pkt[$];\n\n\ti_header = 12;\n\ti_len = 5;\n\ti_data = new[5];\n\ti_crc = 42;\n\n\tpkt = {<< 8 {i_header, i_len, i_data, i_crc}};\n\n\t{<< 8 {o_header, o_len, o_data with [0 +: o_len], o_crc}} = pkt;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.2--unary_op_dec-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unary_op_dec_sim\n:description: -- operator simulation test\ntype: simulation elaboration parsing\n:tags: 11.4.2\n*/\nmodule top();\n\nint a = 12;\n\ninitial begin\n\ta--;\n    $display(\":assert: (11 == %d)\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.2--unary_op_dec.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unary_op_dec\n:description: -- operator test\n:tags: 11.4.2\n*/\nmodule top();\n\nint a = 12;\n\ninitial begin\n\ta--;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.2--unary_op_inc-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unary_op_inc_sim\n:description: ++ operator simulation test\ntype: simulation elaboration parsing\n:tags: 11.4.2\n*/\nmodule top();\n\nint a = 12;\n\ninitial begin\n\ta++;\n    $display(\":assert: (13 == %d)\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.2--unary_op_inc.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unary_op_inc\n:description: ++ operator test\n:tags: 11.4.2\n*/\nmodule top();\n\nint a = 12;\n\ninitial begin\n\ta++;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.4.5--equality-op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: equality_op\n:description: equality operator test\n:type: simulation elaboration parsing\n:tags: 11.4.5\n*/\nmodule top();\n\nreg [7:0] a, b, c, d, e, f;\n\ninitial begin\n    a = 8'b1101x001;\n    b = 8'b1101x000;\n    c = 8'b1101z001;\n    d = 8'b1101z000;\n    e = 8'b11011001;\n    f = 8'b11011000;\n\n    $display(\":assert: (0 == %d)\", a == b);\n    $display(\":assert: (0 == %d)\", c == d);\n    $display(\":assert: (0 == %d)\", e == f);\n\n    $display(\":assert: (0 == %d)\", a === b);\n    $display(\":assert: (0 == %d)\", c === d);\n    $display(\":assert: (0 == %d)\", e === f);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.1--idx_neg_part_select-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: idx_neg_part_select_sim\n:description: indexed negative part-select bit simulation test\n:type: simulation elaboration parsing\n:tags: 11.5.1\n*/\nmodule top();\nlogic [15:0] a = 16'h1234;\nlogic [7:0] b;\n\ninitial begin\n\tb = a[15-:8];\n    $display(\":assert: (0x12 == 0x%x)\", b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.1--idx_neg_part_select.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: idx_neg_part_select\n:description: indexed negative part-select bit test\n:tags: 11.5.1\n*/\nmodule top();\nlogic [15:0] a;\nlogic [3:0] b;\n\ninitial begin\n\tb = a[11-:4];\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.1--idx_pos_part_select-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: idx_pos_part_select_sim\n:description: indexed positive part-select bit simulation test\n:type: simulation elaboration parsing\n:tags: 11.5.1\n*/\nmodule top();\nlogic [15:0] a = 16'h1234;\nlogic [7:0] b;\n\ninitial begin\n\tb = a[0+:8];\n    $display(\":assert: (0x34 == 0x%x)\", b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.1--idx_pos_part_select.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: idx_pos_part_select\n:description: indexed positive part-select bit test\n:tags: 11.5.1\n*/\nmodule top();\nlogic [15:0] a;\nlogic [3:0] b;\n\ninitial begin\n\tb = a[11+:4];\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.1--idx_select-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: idx_select_sim\n:description: indexed select bit simulation test\n:type: simulation elaboration parsing\n:tags: 11.5.1\n*/\nmodule top();\nlogic [15:0] a = 16'h1000;\nlogic b;\nlogic c;\n\ninitial begin\n\tb = a[12];\n\tc = a[5];\n    $display(\":assert: (1 == %d)\", b);\n    $display(\":assert: (0 == %d)\", c);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.1--idx_select.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: idx_select\n:description: indexed select bit test\n:tags: 11.5.1\n*/\nmodule top();\nlogic [15:0] a;\nlogic b;\n\ninitial begin\n\tb = a[11];\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.1--non_idx_part_select-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: non_idx_part_select_sim\n:description: non-indexed part-select bit simulation test\n:type: simulation elaboration parsing\n:tags: 11.5.1\n*/\nmodule top();\nlogic [15:0] a = 16'h1234;\nlogic [3:0] b;\n\ninitial begin\n\tb = a[11:8];\n    $display(\":assert: (2 == %d)\", b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.1--non_idx_part_select.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: non_idx_part_select\n:description: non-indexed part-select bit test\n:tags: 11.5.1\n*/\nmodule top();\nlogic [15:0] a;\nlogic [3:0] b;\n\ninitial begin\n\tb = a[11:8];\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.2--array_addressing-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array_addressing_sim\n:description: array addressing simulation test\n:type: simulation elaboration parsing\n:tags: 11.5.2\n*/\nmodule top();\nlogic [7:0] mem [0:1023];\nlogic [7:0] a;\n\ninitial begin\n    mem[123] = 125;\n\ta = mem[123];\n    $display(\":assert: (125 == %d)\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.2--array_addressing.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array_addressing\n:description: array addressing test\n:tags: 11.5.2\n*/\nmodule top();\nlogic [7:0] mem [0:1023];\nlogic [7:0] a;\n\ninitial begin\n\ta = mem[123];\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.2--multi_dim_array_addressing-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: multi_dim_array_addressing_sim\n:description: multi-dimensional array addressing simulation test\n:type: simulation elaboration parsing\n:tags: 11.5.2\n*/\nmodule top();\nlogic [7:0] mem [0:1023][0:3];\nlogic [7:0] a;\n\ninitial begin\n    mem[123][2] = 125;\n\ta = mem[123][2];\n    $display(\":assert: (125 == %d)\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.5.2--multi_dim_array_addressing.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: multi_dim_array_addressing\n:description: multi-dimensional array addressing test\n:tags: 11.5.2\n*/\nmodule top();\nlogic [7:0] mem [0:1023][0:3];\nlogic [7:0] a;\n\ninitial begin\n\ta = mem[123][2];\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.7--signed_func-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: signed_func_sim\n:description: $signed() simulation test\n:type: simulation elaboration parsing\n:tags: 11.7\n*/\nmodule top();\n\nlogic signed [7:0] a;\n\ninitial begin\n\ta = $signed(4'b1000);\n    $display(\":assert: (-8 == %d)\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.7--signed_func.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: signed_func\n:description: $signed() test\n:tags: 11.7\n*/\nmodule top();\n\nlogic signed [7:0] a;\n\ninitial begin\n\ta = $signed(4'b1000);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.7--unsigned_func-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unsigned_func_sim\n:description: $unsigned() simulation test\n:type: simulation elaboration parsing\n:tags: 11.7\n*/\nmodule top();\n\nlogic [7:0] a;\n\ninitial begin\n\ta = $unsigned(-4);\n    $display(\":assert: (0b11111100 == %d)\", a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.7--unsigned_func.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unsigned_func\n:description: $unsigned() test\n:tags: 11.7\n*/\nmodule top();\n\nlogic [7:0] a;\n\ninitial begin\n\ta = $unsigned(-4);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.9--tagged_union.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: tagged_union\n:description: tagged union test\n:tags: 11.9\n*/\nmodule top();\n\ntypedef union tagged {\n\tvoid Invalid;\n\tint Valid;\n} u_int;\n\nu_int a, b;\n\ninitial begin\n\ta = tagged Invalid;\n\tb = tagged Valid(42);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.9--tagged_union_member_access-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: tagged_union_member_access_sim\n:description: tagged union member access simulation test\n:type: simulation elaboration parsing\n:tags: 11.9\n*/\nmodule top();\n\ntypedef union tagged {\n\tvoid Invalid;\n\tint Valid;\n} u_int;\n\nu_int a;\n\nint b;\n\ninitial begin\n\ta = tagged Valid(42);\n\tb = a.Valid;\n    $display(\":assert: (42 == %d)\", b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.9--tagged_union_member_access.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: tagged_union_member_access\n:description: tagged union member access test\n:tags: 11.9\n*/\nmodule top();\n\ntypedef union tagged {\n\tvoid Invalid;\n\tint Valid;\n} u_int;\n\nu_int a, b;\n\nint c;\n\ninitial begin\n\ta = tagged Invalid;\n\tb = tagged Valid(42);\n\tc = b.Valid;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/11.9--tagged_union_member_access_inv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: tagged_union_member_access_inv\n:description: invalid tagged union member access test\n:should_fail_because: accessing wrong member should result in run-time error\n:tags: 11.9\n:type: simulation\n*/\nmodule top();\n\ntypedef union tagged {\n\tvoid Invalid;\n\tint Valid;\n} u_int;\n\nu_int a, b;\n\nint c;\n\ninitial begin\n\ta = tagged Invalid;\n\tb = tagged Valid(42);\n\tc = a.Valid;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.4.11--simple_cond_op-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_cond_op_sim\n:description: minimal ?: operator simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.4.11\n*/\nmodule top(input a, output b);\n\nassign b = (a) ? 0 : 1;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.4.12--simple_concat_op-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_concat_op_sim\n:description: minimal concatenation operator simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.4.12\n*/\nmodule top(input [1:0] a, input [1:0] b, output [3:0] c);\n\nassign c = {a, b};\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.4.12.1--simple_repl_op-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_repl_op_sim\n:description: minimal replication operator simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.4.12.1\n*/\nmodule top(input [1:0] a, output [15:0] b);\n\nassign b = {8{a}};\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.4.13--simple_set_member-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_set_member_sim\n:description: minimal inside operator simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.4.13\n*/\nmodule top(input [3:0] a, output b);\n\nassign b = (a inside {2, 3, 4, 5});\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.4.14.3--simple_unpack_stream-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_unpack_stream_sim\n:description: minimal stream unpack simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.4.14.3\n*/\nmodule top(input [1:0] a, input [1:0] b, input [1:0] c, output [5:0] d);\n\n    assign d = {<<2 {a, b, c}};\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.5.1--simple_idx_neg_part_select-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_idx_neg_part_select_sim\n:description: minimal indexed negative part-select bit simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.5.1\n*/\nmodule top(input [15:0] a, output [3:0] b);\n\n    assign b = a[15-:4];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.5.1--simple_idx_pos_part_select-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_idx_pos_part_select_sim\n:description: minimal indexed positive part-select bit simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.5.1\n*/\nmodule top(input [15:0] a, output [3:0] b);\n\n    assign b = a[0+:4];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.5.1--simple_idx_select-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_idx_select_sim\n:description: minimal indexed select bit simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.5.1\n*/\nmodule top(input [3:0] a, output b);\n\n    assign b = a[2];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.5.1--simple_non_idx_part_select-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_non_idx_part_select_sim\n:description: minimal non-indexed part-select bit simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.5.1\n*/\nmodule top(input [7:0] a, output [1:0] b);\n\nassign b = a[7:6];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-11/simple/11.5.2--simple_array_addressing-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: simple_array_addressing_sim\n:description: minimal array addressing simulation test (without result verification)\n:type: simulation elaboration parsing\n:tags: 11.5.2\n*/\nmodule top(input [7:0] a, output [7:0] b);\n\nreg [7:0] mem [0:255];\n\nassign b = mem[a];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.4--if.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if\n:description: A module testing if statement\n:tags: 12.4\n*/\nmodule if_tb ();\n\twire a = 0;\n\treg b = 0;\n\talways @* begin\n\t\tif(a) b = 1;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.4--if_else.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else\n:description: A module testing if-else statement\n:tags: 12.4\n*/\nmodule if_tb ();\n\twire a = 0;\n\treg b = 0;\n\talways @* begin\n\t\tif(a) b = 1;\n\t\telse b = 0;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.4.1--if_else_if.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_if\n:description: A module testing if-else-if statement\n:tags: 12.4.1\n*/\nmodule if_tb ();\n\twire a = 0;\n\treg b = 0;\n\twire c = 0;\n\treg d = 0;\n\talways @* begin\n\t\tif(a) b = 1;\n\t\telse if(c) d = 1;\n\t\telse b = 0;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.4.2--priority_if.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: priority_if\n:description: A module testing priority-if statement\n:tags: 12.4.2\n*/\nmodule if_tb ();\n\twire [3:0] a = 0;\n\treg [1:0] b = 0;\n\talways @* begin\n\t\tpriority if(a[0] == 0) b = 1;\n\t\telse if(a[1] == 0) b = 2;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.4.2--unique0_if.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unique0_if\n:description: A module testing unique0-if statement\n:tags: 12.4.2\n*/\nmodule if_tb ();\n\twire [3:0] a = 0;\n\treg [1:0] b = 0;\n\talways @* begin\n\t\tunique0 if(a == 0) b = 1;\n\t\telse if(a == 1) b = 2;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.4.2--unique_if.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unique_if\n:description: A module testing unique-if statement\n:tags: 12.4.2\n*/\nmodule if_tb ();\n\twire [3:0] a = 0;\n\treg [1:0] b = 0;\n\talways @* begin\n\t\tunique if(a == 0) b = 1;\n\t\telse if(a == 1) b = 2;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.5--case.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: case\n:description: A module testing case statement\n:tags: 12.5\n*/\nmodule case_tb ();\n\twire [3:0] a = 0;\n\treg [3:0] b = 0;\n\talways @* begin\n\t\tcase(a)\n\t\t\t4'h0: b = 12;\n\t\t\t4'h3: b = 4;\n\t\t\t4'hf: b = 8;\n\t\t\tdefault b = 0;\n\t\tendcase\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.5.1--casex.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: casex\n:description: A module testing casex statement\n:tags: 12.5.1\n*/\nmodule case_tb ();\n\twire [3:0] a = 4'b10zx;\n\treg [3:0] b = 0;\n\talways @* begin\n\t\tcasex(a)\n\t\t\t4'b1xz?: b = 1;\n\t\t\t4'b01xx: b = 2;\n\t\t\t4'b001x: b = 3;\n\t\t\t4'b0001: b = 4;\n\t\t\tdefault b = 0;\n\t\tendcase\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.5.1--casez.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: casez\n:description: A module testing casez statement\n:tags: 12.5.1\n*/\nmodule case_tb ();\n\twire [3:0] a = 4'b1z11;\n\treg [3:0] b = 0;\n\talways @* begin\n\t\tcasez(a)\n\t\t\t4'b1zzz: b = 1;\n\t\t\t4'b01z?: b = 2;\n\t\t\t4'b001z: b = 3;\n\t\t\t4'b0001: b = 4;\n\t\t\tdefault b = 0;\n\t\tendcase\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.5.2--case_const.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: case_constant\n:description: A module testing case statement with constant expression\n:tags: 12.5.2\n*/\nmodule case_tb ();\n\twire [3:0] a = 0;\n\treg [3:0] b = 0;\n\talways @* begin\n\t\tcase(1)\n\t\t\ta[0] : b = 1;\n\t\t\ta[1] : b = 2;\n\t\t\ta[2] : b = 3;\n\t\t\ta[3] : b = 4;\n\t\t\tdefault b = 0;\n\t\tendcase\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.5.4--case_set.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: case_set\n:description: A module testing case set membership\n:tags: 12.5.4\n*/\nmodule case_tb ();\n\treg [3:0] a = 0;\n\treg [3:0] b = 0;\n\talways @* begin\n\t\tcase(a) inside\n\t\t\t1, 3: b = 1;\n\t\t\t4'b01??, [5:6]: b = 2;\n\t\t\tdefault b = 3;\n\t\tendcase\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.6.1--case_pattern.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: case_pattern\n:description: A module testing pattern matching in case statements\n:tags: 12.6.1\n*/\nmodule case_tb ();\n\n\ttypedef union tagged {\n\t\tstruct {\n\t\t\tbit [3:0] val1, val2;\n\t\t} a;\n\t\tstruct {\n\t\t\tbit [7:0] val1, val2;\n\t\t} b;\n\t\tstruct {\n\t\t\tbit [15:0] val1, val2;\n\t\t} c;\n\t} u;\n\n\tu tmp;\n\n\tinitial case (tmp) matches\n\t\ttagged a '{.v, 0} : $display(\"a %d\", v);\n\t\ttagged a '{.v1, .v2} : $display(\"a %d %d\", v1, v2);\n\t\ttagged b '{.v1, .v2} : $display(\"b %d %d\", v1, v2);\n\t\ttagged c '{0, .v} : $display(\"c %d\", v);\n\tendcase\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.6.1--casex_pattern.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: casex_pattern\n:description: A module testing pattern matching in casex statements\n:tags: 12.6.1\n*/\nmodule case_tb ();\n\n\ttypedef union tagged {\n\t\tstruct {\n\t\t\tbit [3:0] val1, val2;\n\t\t} a;\n\t\tstruct {\n\t\t\tbit [7:0] val1, val2;\n\t\t} b;\n\t\tstruct {\n\t\t\tbit [15:0] val1, val2;\n\t\t} c;\n\t} u;\n\n\tu tmp;\n\n\tinitial casex (tmp) matches\n\t\ttagged a '{.v, 4'b00?x} : $display(\"a %d\", v);\n\t\ttagged a '{.v1, .v2} : $display(\"a %d %d\", v1, v2);\n\t\ttagged b '{.v1, .v2} : $display(\"b %d %d\", v1, v2);\n\t\ttagged c '{4'h??0x, .v} : $display(\"c %d\", v);\n\tendcase\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.6.1--casez_pattern.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: casez_pattern\n:description: A module testing pattern matching in casez statements\n:tags: 12.6.1\n*/\nmodule case_tb ();\n\n\ttypedef union tagged {\n\t\tstruct {\n\t\t\tbit [3:0] val1, val2;\n\t\t} a;\n\t\tstruct {\n\t\t\tbit [7:0] val1, val2;\n\t\t} b;\n\t\tstruct {\n\t\t\tbit [15:0] val1, val2;\n\t\t} c;\n\t} u;\n\n\tu tmp;\n\n\tinitial casez (tmp) matches\n\t\ttagged a '{.v, 4'bzz0?} : $display(\"a %d\", v);\n\t\ttagged a '{.v1, .v2} : $display(\"a %d %d\", v1, v2);\n\t\ttagged b '{.v1, .v2} : $display(\"b %d %d\", v1, v2);\n\t\ttagged c '{4'hz00?, .v} : $display(\"c %d\", v);\n\tendcase\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.6.2--if_pattern.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_pattern\n:description: A module testing pattern matching in if statements\n:tags: 12.6.2\n*/\nmodule case_tb ();\n\n\ttypedef union tagged {\n\t\tstruct {\n\t\t\tbit [3:0] val1, val2;\n\t\t} a;\n\t\tstruct {\n\t\t\tbit [7:0] val1, val2;\n\t\t} b;\n\t\tstruct {\n\t\t\tbit [15:0] val1, val2;\n\t\t} c;\n\t} u;\n\n\tu tmp;\n\n\tinitial if (tmp matches tagged a '{4'b01zx, .v})\n\t\t$display(\"a %d\", v);\n\t\t\n\t\t\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.6.3--conditional_pattern.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: conditional_pattern\n:description: A module testing pattern matching in conditional expressions\n:tags: 12.6.3\n*/\nmodule case_tb ();\n\n\ttypedef union tagged {\n\t\tstruct {\n\t\t\tbit [3:0] val1, val2;\n\t\t} a;\n\t\tstruct {\n\t\t\tbit [7:0] val1, val2;\n\t\t} b;\n\t\tstruct {\n\t\t\tbit [15:0] val1, val2;\n\t\t} c;\n\t} u;\n\n\tu tmp;\n\n\tbit [3:0] val;\n\n\tinitial begin\n          val = tmp matches tagged a '{4'b01zx, .v} ? 1 : 2;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.7.1--for.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: for_loop\n:description: A module testing for loop\n:tags: 12.7.1\n*/\nmodule for_tb ();\n\tinitial begin\n\t\tfor (int i = 0; i < 256; i++)\n\t\t\t$display(\"%d\", i);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.7.2--repeat.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: repeat_loop\n:description: A module testing repeat loop\n:tags: 12.7.2\n*/\nmodule repeat_tb ();\n\tint a = 128;\n\tinitial begin\n\t\trepeat(a)\n\t\t\t$display(\"repeat\");\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.7.3--foreach-synth.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: foreach_loop_synth\n:description: A module testing foreach loop\n:tags: 12.7.3\n*/\nmodule test ();\n  logic [15:0] test [4] = '{16'h1111, 16'h2222, 16'h3333, 16'h4444};\n  logic [15:0] copy [4];\n  always_comb begin\n    foreach(test[i]) begin\n      copy[i] = test[i];\n    end\n  end\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.7.3--foreach.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: foreach_loop\n:description: A module testing foreach loop\n:tags: 12.7.3\n:unsynthesizable: 1\n*/\nmodule foreach_tb ();\n\tstring test [4] = '{\"111\", \"222\", \"333\", \"444\"};\n\tinitial begin\n\t\tforeach(test[i])\n\t\t\t$display(i, test[i]);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.7.4--while.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: while_loop\n:description: A module testing while loop\n:tags: 12.7.4\n*/\nmodule while_tb ();\n\tstring test [4] = '{\"111\", \"222\", \"333\", \"444\"};\n\tinitial begin\n\t\tint i = 0;\n\t\twhile(test[i] != \"222\")begin\n\t\t\t$display(i, test[i]);\n\t\t\ti++;\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.7.5--dowhile.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dowhile_loop\n:description: A module testing do..while loop\n:tags: 12.7.5\n*/\nmodule dowhile_tb ();\n\tstring test [4] = '{\"111\", \"222\", \"333\", \"444\"};\n\tinitial begin\n\t\tint i = 0;\n\t\tdo begin\n\t\t\t$display(i, test[i]);\n\t\t\ti++;\n\t\tend while(test[i] != \"222\"); \n\t   \n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.7.6--forever.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: forever_loop\n:description: A module testing forever loop\n:tags: 12.7.6\n:unsynthesizable: 1\n*/\nmodule forever_tb ();\n   initial begin\n      forever begin : loop\n\t disable loop;\n      end\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.8--break.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: jump_break\n:description: A module testing break statement\n:tags: 12.8\n:type: simulation elaboration parsing\n*/\nmodule jump_tb ();\n\tinitial begin\n\t\tint i;\n\t\tfor (i = 0; i < 256; i++)begin\n\t\t\tif(i > 100)\n\t\t\t\tbreak;\n\t\tend\n\t\t$display(\":assert:(%d == 101)\", i);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.8--continue.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: jump_continue\n:description: A module testing continue statement\n:tags: 12.8\n:type: simulation elaboration parsing\n*/\nmodule jump_tb ();\n\tinitial begin\n\t\tfor (int i = 0; i < 256; i++)begin\n\t\t\tif(i < 255)\n\t\t\t\tcontinue;\n\t\t\t$display(\":assert:(%d == 255)\", i);\n\t\tend\n\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.8--return.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: jump_return\n:description: A module testing return statement\n:tags: 12.8\n*/\nmodule jump_tb ();\n\tfunction void fun(input int a);\n\t\t$display(\"a\");\n\t\tif(a == 21)\n\t\t\treturn;\n\t\t$display(a);\n\t\treturn;\n\tendfunction\n\tinitial begin\n\t\tfor (int i = 0; i < 256; i++)begin\n\t\t\tfun(i);\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-12/12.8--return_val.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: jump_return_expr\n:description: A module testing return <expr> statement\n:tags: 12.8\n*/\nmodule jump_tb ();\n\tfunction int fun(input int a);\n\t\treturn a * 3;\n\tendfunction\n\tinitial begin\n\t\tfor (int i = 0; i < 256; i++)begin\n\t\t\t$display(fun(i));\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.3--task-label.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: task-label\n:description: test w/ named end test\n:tags: 13.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\n  task mytask;\n    $display(\":assert: True\");\n  endtask : mytask\n\n  initial\n    mytask;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.3--task.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: task\n:description: task test\n:tags: 13.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\ntask mytask;\n\t$display(\":assert: True\");\nendtask\n\ninitial \n\tmytask;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.3.1--task-automatic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: task_automatic\n:description: automatic task test\n:tags: 13.3.1\n:type: simulation elaboration parsing\n*/\nmodule top();\n\ntask automatic mytask;\n\tint a = 0;\n\ta++;\n\t$display(\":assert:(%d == 1)\", a);\nendtask\n\ninitial begin\n   mytask;\n   mytask;\n   mytask;\n   mytask;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.3.1--task-static.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: task_static\n:description: static task test\n:tags: 13.3.1\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\ntask static mytask(int test);\n\tint a = 0;\n\ta++;\n\tif (test)\n\t\t$display(\":assert:(%d != 1)\", a);\n\telse\n\t\t$display(\":assert:(%d == 1)\", a);\nendtask\n\ninitial\n\tbegin\n\t\tmytask(0);\n\t\tmytask(1);\n\t\tmytask(1);\n\t\tmytask(1);\n\tend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4--function-label.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: function\n:description: function w/ named end test\n:tags: 13.4\n:type: simulation elaboration parsing\n*/\nmodule top();\n\n  function int test(int val);\n    return val + 1;\n  endfunction : test\n\n  initial\n    $display(\":assert: (%d == 2)\", test(1));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4--function.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: function\n:description: function test\n:tags: 13.4\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nfunction int test(int val);\n\treturn val + 1;\nendfunction\n\ninitial\n\t$display(\":assert: (%d == 2)\", test(1));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4.1--function-return-assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: function_return_assignment\n:description: function return value assignment test\n:tags: 13.4.1\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nfunction int add(int a, int b);\n\tadd = a + b;\nendfunction\n\ninitial\n\t$display(\":assert: (%d == 90)\", add(30, 60));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4.1--function-return.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: function_return\n:description: function return value test\n:tags: 13.4.1\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nfunction int add(int a, int b);\n\treturn a + b;\nendfunction\n\ninitial\n\t$display(\":assert: (%d == 90)\", add(30, 60));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4.1--function-void-return.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: function_void_return\n:description: void function return value test\n:should_fail_because: void function returns value\n:tags: 13.4.1\n:type: simulation elaboration\n*/\nmodule top();\n\nfunction void add(int a, int b);\n\t$display(\"%d+%d=\", a, b);\n\treturn a + b;\nendfunction\n\ninitial\n\t$display(\"%d\", add(45, 90));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4.2--function-automatic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: function_automatic\n:description: automatic function test\n:tags: 13.4.2\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nfunction automatic int add(int val);\n\tint a = 0;\n\ta = a + val;\n\treturn a;\nendfunction\n\ninitial\n\tbegin\n\t\t$display(\":assert: (%d == 5)\", add(5));\n\t\t$display(\":assert: (%d == 5)\", add(5));\n\t\t$display(\":assert: (%d == 5)\", add(5));\n\t\t$display(\":assert: (%d == 5)\", add(5));\n\tend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4.2--function-recursive.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n// -*- coding: utf-8 -*-\n// SPDX-License-Identifier: ISC\n//\n// Copyright (C) 2020 The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n/*\n:name: function_recursive\n:description: recursive function test\n:tags: 13.4.2\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nfunction automatic int factorial(int val);\n\tif(val == 0) return 1;\n\treturn factorial(val-1) * val;\nendfunction\n\ninitial\n\tbegin\n\t\t$display(\":assert: (%d == 1)\", factorial(0));\n\t\t$display(\":assert: (%d == 1)\", factorial(1));\n\t\t$display(\":assert: (%d == 2)\", factorial(2));\n\t\t$display(\":assert: (%d == 120)\", factorial(5));\n\t\t$display(\":assert: (%d == 39916800)\", factorial(11));\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4.2--function-static.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: function_static\n:description: static function test\n:tags: 13.4.2\n:unsynthesizable: 1\n*/\nmodule top();\n\nfunction static int add(int val);\n\tint a = 0;\n\ta = a + val;\n\treturn a;\nendfunction\n\ninitial\n\tbegin\n\t\t$display(\":assert: (%d == 5)\", add(5));\n\t\t$display(\":assert: (%d == 10)\", add(5));\n\t\t$display(\":assert: (%d == 15)\", add(5));\n\t\t$display(\":assert: (%d == 20)\", add(5));\n\tend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4.3--const-function.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: const_function\n:description: const function test\n:tags: 13.4.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nlocalparam a = fun(3);\n\nfunction int fun(int val);\n\treturn val + 1;\nendfunction\n\ninitial\n\t$display(\":assert: (%d == 4)\", a);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4.4--fork-invalid.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: function_fork_invalid\n:description: function invalid fork test\n:should_fail_because: only fork-join_none is permitted inside a function\n:tags: 13.4.4\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule top();\n\nfunction int fun(int val);\n\tfork\n\t\t$display(\"abc\");\n\t\t$display(\"def\");\n\tjoin_any\n\treturn val + 2;\nendfunction\n\ninitial\n\t$display(\"$d\", fun(2));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-13/13.4.4--fork-valid.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: function_fork_valid\n:description: function valid fork test\n:tags: 13.4.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nfunction int fun(int val);\n\tfork\n\t\t$display(\"abc\");\n\t\t$display(\"def\");\n\tjoin_none\n\treturn val + 2;\nendfunction\n\ninitial\n\t$display(\"$d\", fun(2));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-14/14.3--clocking-block-signals-error.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: clocking_block_signals_fail\n:description: clocking block with signals test\n:should_fail_because: assigning to net from procedural context\n:type: simulation elaboration\n:tags: 14.3\n:unsynthesizable: 1\n*/\nmodule top(input clk, input a, output b, output c);\n\nclocking ck1 @(posedge clk);\n\tdefault input #10ns output #5ns;\n\tinput a;\n\toutput b;\n\toutput #3ns c;\nendclocking\n\nalways_ff @(posedge clk) begin\n\tb <= a;\n\tc <= a;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-14/14.3--clocking-block-signals.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: clocking_block_signals\n:description: clocking block with signals test\n:tags: 14.3\n:unsynthesizable: 1\n*/\nmodule top(input clk, input a, output logic b, output logic c);\n\nclocking ck1 @(posedge clk);\n\tdefault input #10ns output #5ns;\n\tinput a;\n\toutput b;\n\toutput #3ns c;\nendclocking\n\nalways_ff @(posedge clk) begin\n\tb <= a;\n\tc <= a;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-14/14.3--clocking-block.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: clocking_block\n:description: clocking block test\n:tags: 14.3\n:unsynthesizable: 1\n*/\nmodule top(input clk);\n\nclocking ck1 @(posedge clk);\n\tdefault input #10ns output #5ns;\nendclocking\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-14/14.3--default-clocking-block.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: default_clocking_block\n:description: default clocking block test\n:tags: 14.3\n:unsynthesizable: 1\n*/\nmodule top(input clk);\n\ndefault clocking @(posedge clk);\n\tdefault input #10ns output #5ns;\nendclocking\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-14/14.3--global-clocking-block.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: global_clocking_block\n:description: global clocking block test\n:tags: 14.3\n:unsynthesizable: 1\n*/\nmodule top(input clk);\n\nglobal clocking ck1 @(posedge clk); endclocking\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-15/15.4--mailbox-blocking.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: mailbox_blocking\n:description: blocking mailbox test\n:tags: 15.4\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nmailbox #(string) m;\n\ninitial begin\n\tstring msg = \"abc\";\n\tstring r;\n\tstring r_peek;\n\tm = new();\n\tm.put(msg);\n\tm.peek(r_peek);\n\t$display(\":assert: (%d == 1)\", m.num());\n\tm.get(r);\n\t$display(\":assert: ('%s' == '%s')\", r, r_peek);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-15/15.4--mailbox-non-blocking.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: mailbox_non_blocking\n:description: non-blocking mailbox test\n:tags: 15.4\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nmailbox #(string) m;\n\ninitial begin\n\tstring msg = \"abc\";\n\tstring r;\n\tstring r_peek;\n\tint i;\n\tm = new();\n\ti = m.try_put(msg);\n\tm.peek(r_peek);\n\t$display(\":assert: (%d == 1)\", m.num());\n\ti = m.try_get(r);\n\t$display(\":assert: ('%s' == '%s')\", r, r_peek);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-15/15.5.1--named-event-trigger-blocking.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: named_event_trigger_blocking\n:description: Trigger named event, blocking\n:tags: 15.5\n:top_module: top\n:unsynthesizable: 1\n*/\n\n\nmodule inner();\n\tinitial \n\t\t-> top.e;\nendmodule\n\nmodule top();\n\nevent e;\n\ninitial begin\n\t// Normal trigger\n\t-> e;\n\t// Nonblocking trigger\n\t->> e; \nend\n\nendmodule\n\nclass foo;\n\n\tevent e;\n\t\n\ttask wait_e();\n\t\t->e;\n\tendtask;\n\nendclass\n\n"
  },
  {
    "path": "tests/chapter-15/15.5.1--named-event-trigger-non-blocking.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: named_event_trigger_non_blocking\n:description: Trigger named event, non-blocking\n:tags: 15.5\n:top_module: top\n:unsynthesizable: 1\n*/\n\n\nmodule inner();\n\tinitial \n\t\t->> top.e;\nendmodule\n\nmodule top();\n\nevent e;\n\ninitial begin\n\t// Nonblocking trigger\n\t->> e; \nend\n\nendmodule\n\nclass foo;\n\n\tevent e;\n\t\n\ttask wait_e();\n\t\t->> e;\n\tendtask;\n\nendclass\n\n"
  },
  {
    "path": "tests/chapter-15/15.5.2--named-event-wait.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: named_event_wait\n:description: Wait for a named event\n:tags: 15.5\n:top_module: top\n:unsynthesizable: 1\n*/\n\n\n\nmodule inner();\n\tinitial \n\t\t@top.e;\nendmodule\n\n\nmodule top();\n\nevent e;\n\ninitial begin\n\t@ e;\nend\n\nendmodule\n\nclass foo;\n\n\tevent e;\n\t\n\ttask wait_e();\n\t\t@e;\n\tendtask;\n\nendclass\n\n"
  },
  {
    "path": "tests/chapter-16/16.10--property-local-var-fail.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_local_var_fail_test\n:description: failing property with local variables\n:should_fail_because: pipeline increments value by 4 but property expects incrementation by 3\n:type: simulation\n:tags: 16.10\n:unsynthesizable: 1\n*/\n\nmodule clk_gen(\n    input            valid,\n    input            clk,\n    output reg [7:0] out,\n    input      [7:0] in\n);\n\n    reg [7:0] data_reg_0;\n    reg [7:0] data_reg_1;\n    reg [7:0] data_reg_2;\n\n    initial begin\n        data_reg_0 = 0;\n        data_reg_1 = 0;\n        data_reg_2 = 0;\n        out        = 0;\n    end\n\n    always @(posedge clk) begin\n        if (valid) begin\n            data_reg_0 <= in + 1;\n            data_reg_1 <= data_reg_0 + 1;\n            data_reg_2 <= data_reg_1 + 1;\n            out        <= data_reg_2 + 1;\n        end\n    end\n\nendmodule: clk_gen\n\nmodule top();\n\n    int         cycle;\n    logic       valid;\n    logic       clk;\n    logic [7:0] out;\n    logic [7:0] in;\n\n    clk_gen dut(.valid(valid), .clk(clk), .out(out), .in(in));\n\n    initial begin\n        cycle = 0;\n        clk   = 0;\n        valid = 1;\n    end\n\n    property prop;\n        int x;\n        @(posedge clk) (valid, x = in) |-> ##4 (out == x + 3);\n    endproperty\n\n    assert property (prop) else $error($sformatf(\"property check failed :assert: (False)\"));\n\n    assign in = cycle;\n\n    always @(posedge clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) clk = ~clk;\n        end\n    end\n\n    initial #1000 $finish;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.10--property-local-var-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_local_var_test_uvm\n:description: property with local variables in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input            valid,\n    input            clk,\n    output reg [7:0] out,\n    input      [7:0] in\n);\n\n    reg [7:0] data_reg_0;\n    reg [7:0] data_reg_1;\n    reg [7:0] data_reg_2;\n\n    initial begin\n        data_reg_0 = 0;\n        data_reg_1 = 0;\n        data_reg_2 = 0;\n        out        = 0;\n    end\n\n    always @(posedge clk) begin\n        if (valid) begin\n            data_reg_0 <= in + 1;\n            data_reg_1 <= data_reg_0 + 1;\n            data_reg_2 <= data_reg_1 + 1;\n            out        <= data_reg_2 + 1;\n        end\n    end\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit       valid,\n    output bit       clk,\n    input      [7:0] out,\n    output bit [7:0] in\n);\n\nendinterface: clk_gen_if\n\nstring label = \"SEQUENCE_LOCAL_VAR_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    int cycle = 0;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.valid(dif.valid), .clk(dif.clk), .out(dif.out), .in(dif.in));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk   = 0;\n        dif.valid = 1;\n        run_test();\n    end\n\n    property prop;\n        int x;\n        @(posedge dif.clk) (dif.valid, x = dif.in) |-> ##4 (dif.out == x + 4);\n    endproperty\n\n    assert property (prop) else `uvm_info(label, $sformatf(\"property check failed :assert: (False)\"), UVM_LOW);\n\n    assign dif.in = cycle;\n\n    always @(posedge dif.clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.10--property-local-var.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_local_var_test\n:description: property with local variables\n:type: simulation elaboration parsing\n:tags: 16.10\n:unsynthesizable: 1\n*/\n\nmodule clk_gen(\n    input            valid,\n    input            clk,\n    output reg [7:0] out,\n    input      [7:0] in\n);\n\n    reg [7:0] data_reg_0;\n    reg [7:0] data_reg_1;\n    reg [7:0] data_reg_2;\n\n    initial begin\n        data_reg_0 = 0;\n        data_reg_1 = 0;\n        data_reg_2 = 0;\n        out        = 0;\n    end\n\n    always @(posedge clk) begin\n        if (valid) begin\n            data_reg_0 <= in + 1;\n            data_reg_1 <= data_reg_0 + 1;\n            data_reg_2 <= data_reg_1 + 1;\n            out        <= data_reg_2 + 1;\n        end\n    end\n\nendmodule: clk_gen\n\nmodule top();\n\n    int         cycle;\n    logic       valid;\n    logic       clk;\n    logic [7:0] out;\n    logic [7:0] in;\n\n    clk_gen dut(.valid(valid), .clk(clk), .out(out), .in(in));\n\n    initial begin\n        cycle = 0;\n        clk   = 0;\n        valid = 1;\n    end\n\n    property prop;\n        int x;\n        @(posedge clk) (valid, x = in) |-> ##4 (out == x + 4);\n    endproperty\n\n    assert property (prop) else $error($sformatf(\"property check failed :assert: (False)\"));\n\n    assign in = cycle;\n\n    always @(posedge clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) clk = ~clk;\n        end\n    end\n\n    initial #1000 $finish;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.10--sequence-local-var-fail.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_local_var_fail_test\n:description: failing sequence with local variables\n:should_fail_because: pipeline increments value by 4 but sequence expects incrementation by 3\n:type: simulation\n:tags: 16.10\n:unsynthesizable: 1\n*/\n\nmodule clk_gen(\n    input            valid,\n    input            clk,\n    output reg [7:0] out,\n    input      [7:0] in\n);\n\n    reg [7:0] data_reg_0;\n    reg [7:0] data_reg_1;\n    reg [7:0] data_reg_2;\n\n    initial begin\n        data_reg_0 = 0;\n        data_reg_1 = 0;\n        data_reg_2 = 0;\n        out        = 0;\n    end\n\n    always @(posedge clk) begin\n        if (valid) begin\n            data_reg_0 <= in + 1;\n            data_reg_1 <= data_reg_0 + 1;\n            data_reg_2 <= data_reg_1 + 1;\n            out        <= data_reg_2 + 1;\n        end\n    end\n\nendmodule: clk_gen\n\nmodule top();\n\n    int         cycle;\n    logic       valid;\n    logic       clk;\n    logic [7:0] out;\n    logic [7:0] in;\n\n    clk_gen dut(.valid(valid), .clk(clk), .out(out), .in(in));\n\n    initial begin\n        cycle = 0;\n        clk   = 0;\n        valid = 1;\n    end\n\n    sequence seq;\n        int x;\n        @(posedge clk) (valid, x = in) ##4 (out == x + 3);\n    endsequence\n\n    assert property (seq) else $error($sformatf(\"sequence check failed :assert: (False)\"));\n\n    assign in = cycle;\n\n    always @(posedge clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) clk = ~clk;\n        end\n    end\n\n    initial #1000 $finish;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.10--sequence-local-var-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_local_var_test_uvm\n:description: sequence with local variables in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input            valid,\n    input            clk,\n    output reg [7:0] out,\n    input      [7:0] in\n);\n\n    reg [7:0] data_reg_0;\n    reg [7:0] data_reg_1;\n    reg [7:0] data_reg_2;\n\n    initial begin\n        data_reg_0 = 0;\n        data_reg_1 = 0;\n        data_reg_2 = 0;\n        out        = 0;\n    end\n\n    always @(posedge clk) begin\n        if (valid) begin\n            data_reg_0 <= in + 1;\n            data_reg_1 <= data_reg_0 + 1;\n            data_reg_2 <= data_reg_1 + 1;\n            out        <= data_reg_2 + 1;\n        end\n    end\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit       valid,\n    output bit       clk,\n    input      [7:0] out,\n    output bit [7:0] in\n);\n\nendinterface: clk_gen_if\n\nstring label = \"SEQUENCE_LOCAL_VAR_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    int cycle = 0;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.valid(dif.valid), .clk(dif.clk), .out(dif.out), .in(dif.in));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk   = 0;\n        dif.valid = 1;\n        run_test();\n    end\n\n    sequence seq;\n        int x;\n        @(posedge dif.clk) (dif.valid, x = dif.in) ##4 (dif.out == x + 4);\n    endsequence\n\n    assert property (seq) else `uvm_error(label, $sformatf(\"sequence check failed :assert: (False)\"));\n\n    assign dif.in = cycle;\n\n    always @(posedge dif.clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.10--sequence-local-var.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_local_var_test\n:description: sequence with local variables\n:type: simulation elaboration parsing\n:tags: 16.10\n:unsynthesizable: 1\n*/\n\nmodule clk_gen(\n    input            valid,\n    input            clk,\n    output reg [7:0] out,\n    input      [7:0] in\n);\n\n    reg [7:0] data_reg_0;\n    reg [7:0] data_reg_1;\n    reg [7:0] data_reg_2;\n\n    initial begin\n        data_reg_0 = 0;\n        data_reg_1 = 0;\n        data_reg_2 = 0;\n        out        = 0;\n    end\n\n    always @(posedge clk) begin\n        if (valid) begin\n            data_reg_0 <= in + 1;\n            data_reg_1 <= data_reg_0 + 1;\n            data_reg_2 <= data_reg_1 + 1;\n            out        <= data_reg_2 + 1;\n        end\n    end\n\nendmodule: clk_gen\n\nmodule top();\n\n    int         cycle;\n    logic       valid;\n    logic       clk;\n    logic [7:0] out;\n    logic [7:0] in;\n\n    clk_gen dut(.valid(valid), .clk(clk), .out(out), .in(in));\n\n    initial begin\n        cycle = 0;\n        clk   = 0;\n        valid = 1;\n    end\n\n    sequence seq;\n        int x;\n        @(posedge clk) (valid, x = in) ##4 (out == x + 4);\n    endsequence\n\n    assert property (seq) else $error($sformatf(\"sequence check failed :assert: (False)\"));\n\n    assign in = cycle;\n\n    always @(posedge clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) clk = ~clk;\n        end\n    end\n\n    initial #1000 $finish;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.11--sequence-subroutine-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_subroutine_test_uvm\n:description: sequence with subroutine in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input            valid,\n    input            clk,\n    output reg [7:0] out,\n    input      [7:0] in\n);\n\n    reg [7:0] data_reg_0;\n    reg [7:0] data_reg_1;\n    reg [7:0] data_reg_2;\n\n    initial begin\n        data_reg_0 = 0;\n        data_reg_1 = 0;\n        data_reg_2 = 0;\n        out        = 0;\n    end\n\n    always @(posedge clk) begin\n        if (valid) begin\n            data_reg_0 <= in + 1;\n            data_reg_1 <= data_reg_0 + 1;\n            data_reg_2 <= data_reg_1 + 1;\n            out        <= data_reg_2 + 1;\n        end\n    end\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit       valid,\n    output bit       clk,\n    input      [7:0] out,\n    output bit [7:0] in\n);\n\nendinterface: clk_gen_if\n\nstring label = \"SEQUENCE_LOCAL_VAR_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    int cycle = 0;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.valid(dif.valid), .clk(dif.clk), .out(dif.out), .in(dif.in));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk   = 0;\n        dif.valid = 1;\n        run_test();\n    end\n\n    sequence seq;\n        int x;\n        @(posedge dif.clk) (dif.valid, x = dif.in) ##4 (dif.out == x + 4, $display(\"print in sequence\"));\n    endsequence\n\n    assert property (seq) else `uvm_info(label, $sformatf(\"sequence check failed\"), UVM_LOW);\n\n    assign dif.in = cycle;\n\n    always @(posedge dif.clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.12--property-disable-iff.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_disable_iff_min_test\n:description: minimal property disable iff test\n:tags: 16.12\n*/\nmodule top();\n\nlogic clk;\nlogic a;\nlogic b;\nlogic c;\n\nassert property ( @(posedge clk) disable iff (a) b |-> c );\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.12--property-disj.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_disj_test\n:description: property || test\n:tags: 16.12\n*/\nmodule top();\n\nlogic clk;\nlogic a;\nlogic b;\n\nassert property ( @(posedge clk) a || b );\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.12--property-iff.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_iff_test\n:description: property iff test\n:tags: 16.12\n*/\nmodule top();\n\nlogic clk;\nlogic a;\nlogic b;\n\nassert property ( @(posedge clk) a iff b );\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.12--property-interface-prec-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_interface_prec_test_uvm\n:description: interface property with precondition in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mem_ctrl (\n    input            clk,\n    output reg       read,\n    output reg       write,\n    output reg [7:0] addr,\n    output reg [7:0] dout,\n    input      [7:0] din\n);\n\n    reg       phase;\n    reg [7:0] addr_i;\n\n    initial begin\n        phase = 0;\n        read = 0;\n        write = 0;\n    end\n\n    always @(posedge clk) begin\n        read <= 0;\n        write <= 0;\n        addr <= addr_i;\n\n        if(phase) begin\n            read <= 1;\n        end else begin\n            write <= 1;\n        end\n\n        dout <= din;\n        addr_i <= addr_i + 1;\n        phase <= ~phase;\n    end\n\nendmodule: mem_ctrl\n\nstring label = \"PROPERTY_UVM\";\n\ninterface mem_ctrl_if(\n    output bit clk,\n    input read,\n    input write,\n    input [7:0] addr,\n    input [7:0] dout,\n    output reg [7:0] din\n);\n\n    assert property (@(posedge clk) read |=> write ) else `uvm_error(label, $sformatf(\"write after read :assert: (False)\"));\n\nendinterface: mem_ctrl_if\n\nclass env extends uvm_env;\n    virtual mem_ctrl_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name(\n            get_full_name(), \"mem_ctrl_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mem_ctrl_if dif();\n\n    mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mem_ctrl_if)::set(\"env\",\n            \"mem_ctrl_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.12--property-interface-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_interface_test_uvm\n:description: interface property test with UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mem_ctrl (\n    input            clk,\n    output reg       read,\n    output reg       write,\n    output reg [7:0] addr,\n    output reg [7:0] dout,\n    input      [7:0] din\n);\n\n    reg       phase;\n    reg [7:0] addr_i;\n\n    initial begin\n        phase = 0;\n        read = 0;\n        write = 0;\n    end\n\n    always @(posedge clk) begin\n        read <= 0;\n        write <= 0;\n        addr <= addr_i;\n\n        if(phase) begin\n            read <= 1;\n        end else begin\n            write <= 1;\n        end\n\n        dout <= din;\n        addr_i <= addr_i + 1;\n        phase <= ~phase;\n    end\n\nendmodule: mem_ctrl\n\nstring label = \"PROPERTY_INTERFACE_UVM\";\n\ninterface mem_ctrl_if(\n    output bit clk,\n    input read,\n    input write,\n    input [7:0] addr,\n    input [7:0] dout,\n    output reg [7:0] din\n);\n\n    assert property (@(posedge clk) !(read & write)) else `uvm_error(label, $sformatf(\"read and write both asserted :assert: (False)\"));\n\nendinterface: mem_ctrl_if\n\nclass env extends uvm_env;\n    virtual mem_ctrl_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name(\n            get_full_name(), \"mem_ctrl_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mem_ctrl_if dif();\n\n    mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mem_ctrl_if)::set(\"env\",\n            \"mem_ctrl_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.12--property-prec-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_prec_test_uvm\n:description: property with precondition in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mem_ctrl (\n    input            clk,\n    output reg       read,\n    output reg       write,\n    output reg [7:0] addr,\n    output reg [7:0] dout,\n    input      [7:0] din\n);\n\n    reg       phase;\n    reg [7:0] addr_i;\n\n    initial begin\n        phase = 0;\n        read = 0;\n        write = 0;\n    end\n\n    always @(posedge clk) begin\n        read <= 0;\n        write <= 0;\n        addr <= addr_i;\n\n        if(phase) begin\n            read <= 1;\n        end else begin\n            write <= 1;\n        end\n\n        dout <= din;\n        addr_i <= addr_i + 1;\n        phase <= ~phase;\n    end\n\nendmodule: mem_ctrl\n\ninterface mem_ctrl_if(\n    output bit clk,\n    input read,\n    input write,\n    input [7:0] addr,\n    input [7:0] dout,\n    output reg [7:0] din\n);\n\nendinterface: mem_ctrl_if\n\nstring label = \"PROPERTY_UVM\";\n\nclass env extends uvm_env;\n    virtual mem_ctrl_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name(\n            get_full_name(), \"mem_ctrl_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mem_ctrl_if dif();\n\n    mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mem_ctrl_if)::set(\"env\",\n            \"mem_ctrl_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    assert property (@(posedge dif.clk) dif.read |=> dif.write ) else `uvm_error(label, $sformatf(\"write after read :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.12--property-prec.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_prec_test\n:description: property with precondition test\n:tags: 16.12\n*/\nmodule top();\n\nlogic clk;\nlogic a;\nlogic b;\n\nassert property ( @(posedge clk) a |-> b);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.12--property-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_test_uvm\n:description: property test with UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mem_ctrl (\n    input            clk,\n    output reg       read,\n    output reg       write,\n    output reg [7:0] addr,\n    output reg [7:0] dout,\n    input      [7:0] din\n);\n\n    reg       phase;\n    reg [7:0] addr_i;\n\n    initial begin\n        phase = 0;\n        read = 0;\n        write = 0;\n    end\n\n    always @(posedge clk) begin\n        read <= 0;\n        write <= 0;\n        addr <= addr_i;\n\n        if(phase) begin\n            read <= 1;\n        end else begin\n            write <= 1;\n        end\n\n        dout <= din;\n        addr_i <= addr_i + 1;\n        phase <= ~phase;\n    end\n\nendmodule: mem_ctrl\n\ninterface mem_ctrl_if(\n    output bit clk,\n    input read,\n    input write,\n    input [7:0] addr,\n    input [7:0] dout,\n    output reg [7:0] din\n);\n\nendinterface: mem_ctrl_if\n\nstring label = \"PROPERTY_UVM\";\n\nclass env extends uvm_env;\n    virtual mem_ctrl_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name(\n            get_full_name(), \"mem_ctrl_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mem_ctrl_if dif();\n\n    mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mem_ctrl_if)::set(\"env\",\n            \"mem_ctrl_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    assert property (@(posedge dif.clk) !(dif.read & dif.write)) else `uvm_error(label, $sformatf(\"read and write both asserted :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.12--property.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_test\n:description: property test\n:tags: 16.12\n*/\nmodule top();\n\nlogic clk;\nlogic a;\n\nassert property ( @(posedge clk) (a == 1));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.13--sequence-multiclock-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_multiclock_test_uvm\n:description: sequence with local variables in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input      clk0,\n    input      clk1,\n    output reg out0,\n    output reg out1\n);\n\n    initial begin\n        out0 = 0;\n        out1 = 0;\n    end\n\n    always @(posedge clk0) begin\n        out0 <= 1;\n    end\n\n    always @(posedge clk1) begin\n        out1 <= 1;\n    end\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit clk0,\n    output bit clk1,\n    input      out0,\n    input      out1\n);\n\nendinterface: clk_gen_if\n\nstring label = \"SEQUENCE_MULTICLOCK_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk0);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.clk0(dif.clk0), .clk1(dif.clk1), .out0(dif.out0), .out1(dif.out1));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk0 = 0;\n        dif.clk1 = 0;\n        run_test();\n    end\n\n    sequence seq;\n        @(posedge dif.clk0) ##1 dif.out0 ##1 @(posedge dif.clk1) dif.out1;\n    endsequence\n\n    assert property (seq) else `uvm_error(label, $sformatf(\"sequence check failed :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk0 = ~dif.clk0;\n            #(150) dif.clk1 = ~dif.clk1;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.14--assume-property-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assume_property_test_uvm\n:description: assume property test with UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mem_ctrl (\n    input            clk,\n    output reg       read,\n    output reg       write,\n    output reg [7:0] addr,\n    output reg [7:0] dout,\n    input      [7:0] din\n);\n\n    reg       phase;\n    reg [7:0] addr_i;\n\n    initial begin\n        phase = 0;\n        read = 0;\n        write = 0;\n    end\n\n    always @(posedge clk) begin\n        read <= 0;\n        write <= 0;\n        addr <= addr_i;\n\n        if(phase) begin\n            read <= 1;\n        end else begin\n            write <= 1;\n        end\n\n        dout <= din;\n        addr_i <= addr_i + 1;\n        phase <= ~phase;\n    end\n\nendmodule: mem_ctrl\n\ninterface mem_ctrl_if(\n    output bit clk,\n    input read,\n    input write,\n    input [7:0] addr,\n    input [7:0] dout,\n    output reg [7:0] din\n);\n\nendinterface: mem_ctrl_if\n\nstring label = \"PROPERTY_UVM\";\n\nclass env extends uvm_env;\n    virtual mem_ctrl_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name(\n            get_full_name(), \"mem_ctrl_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mem_ctrl_if dif();\n\n    mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mem_ctrl_if)::set(\"env\",\n            \"mem_ctrl_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    assume property (@(posedge dif.clk) !(dif.read & dif.write)) else `uvm_error(label, $sformatf(\"read and write both asserted :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.14--assume-property.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assume_property_test\n:description: assume property test\n:tags: 16.14\n*/\nmodule top();\n\nlogic clk;\nlogic a;\n\nassume property ( @(posedge clk) (a == 1));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.15--property-disable-iff-fail.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_disable_iff_fail_test\n:description: failing property with disable iff\n:should_fail_because: disable iff uses wrong reset polarity\n:type: simulation\n:tags: 16.15\n:unsynthesizable: 1\n*/\n\nmodule clk_gen(\n    input      rst,\n    input      clk,\n    output reg out\n);\n\n    initial begin\n        out = 0;\n    end\n\n    always @(posedge clk or posedge rst) begin\n        if (rst)\n            out <= 0;\n        else\n            out <= 1;\n    end\n\nendmodule: clk_gen\n\nmodule top();\n\n    logic rst;\n    logic clk;\n    logic out;\n\n    clk_gen dut(.rst(rst), .clk(clk), .out(out));\n\n    initial begin\n        clk   = 0;\n        rst   = 1;\n    end\n\n    property prop;\n        @(posedge clk) disable iff (~rst) out;\n    endproperty\n\n    assert property (prop) else $error($sformatf(\"property check failed :assert: (True)\"));\n\n    initial begin\n        forever begin\n            #(50) clk = ~clk;\n        end\n    end\n\n    initial #1000 $finish;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.15--property-disable-iff.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_disable_iff_test\n:description: property with disable iff\n:type: simulation elaboration parsing\n:tags: 16.15\n:unsynthesizable: 1\n*/\n\nmodule clk_gen(\n    input      rst,\n    input      clk,\n    output reg out\n);\n\n    initial begin\n        out = 0;\n    end\n\n    always @(posedge clk or posedge rst) begin\n        if (rst)\n            out <= 0;\n        else\n            out <= 1;\n    end\n\nendmodule: clk_gen\n\nmodule top();\n\n    logic rst;\n    logic clk;\n    logic out;\n\n    clk_gen dut(.rst(rst), .clk(clk), .out(out));\n\n    initial begin\n        clk   = 0;\n        rst   = 1;\n    end\n\n    property prop;\n        @(posedge clk) disable iff (rst) out;\n    endproperty\n\n    assert property (prop) else $error($sformatf(\"property check failed :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) clk = ~clk;\n        end\n    end\n\n    initial #1000 $finish;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.15--property-iff-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: property_disable_iff_test_uvm\n:description: property with disable iff test with UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input      rst,\n    input      clk,\n    output reg out\n);\n\n    initial begin\n        out = 0;\n    end\n\n    always @(posedge clk or posedge rst) begin\n        if (rst)\n            out <= 0;\n        else\n            out <= 1;\n    end\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit rst,\n    output bit clk,\n    input out\n);\n\nendinterface: clk_gen_if\n\nstring label = \"IFF_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.clk(dif.clk), .rst(dif.rst), .out(dif.out));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk = 0;\n        dif.rst = 1;\n        run_test();\n    end\n\n    property prop;\n        @(posedge dif.clk) disable iff (dif.rst) dif.out;\n    endproperty\n\n    assert property (prop) else $error($sformatf(\"property check failed :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.17--expect-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: expect_test_uvm\n:description: expect in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mem_ctrl (\n    input            clk,\n    output reg       read,\n    output reg       write,\n    output reg [7:0] addr,\n    output reg [7:0] dout,\n    input      [7:0] din\n);\n\n    reg       phase;\n    reg [7:0] addr_i;\n\n    initial begin\n        phase = 0;\n        read = 1;\n        write = 0;\n    end\n\n    always @(posedge clk) begin\n        read <= 0;\n        write <= 0;\n        addr <= addr_i;\n\n        if(phase) begin\n            read <= 1;\n        end else begin\n            write <= 1;\n        end\n\n        dout <= din;\n        addr_i <= addr_i + 1;\n        phase <= ~phase;\n    end\n\nendmodule: mem_ctrl\n\ninterface mem_ctrl_if(\n    output bit clk,\n    input read,\n    input write,\n    input [7:0] addr,\n    input [7:0] dout,\n    output reg [7:0] din\n);\n\nendinterface: mem_ctrl_if\n\nstring label = \"EXPECT_UVM\";\n\nclass env extends uvm_env;\n    virtual mem_ctrl_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name(\n            get_full_name(), \"mem_ctrl_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(4) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mem_ctrl_if dif();\n\n    mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mem_ctrl_if)::set(\"env\",\n            \"mem_ctrl_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        expect (@(posedge dif.clk) dif.read ##1 dif.write) else `uvm_error(label, $sformatf(\"expect failed :assert: (False)\"));\n    end\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.17--expect.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: expect_test\n:description: expect test\n:tags: 16.17\n*/\n\nmodule top();\n\nlogic clk;\nlogic a;\nlogic b;\n\ninitial begin\n    expect (@(posedge clk) a ##1 b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assert-final-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assert_final_test_uvm\n:description: assert final test with UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule inverter (\n    input [7:0] a,\n    output [7:0] b\n);\n\n    assign b = !a;\n\nendmodule: inverter\n\ninterface inverter_if(\n    output reg [7:0] a,\n    input [7:0] b\n);\n\nendinterface: inverter_if\n\nstring label = \"ASSERT_FINAL_UVM\";\n\nclass env extends uvm_env;\n    virtual inverter_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual inverter_if)::read_by_name(\n            get_full_name(), \"inverter_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            int a = 8'h35;\n            m_if.a <= a;\n\n            assert final (m_if.a != m_if.b) else $error($sformatf(\"assert failed :assert: (False)\"));\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top;\n    env environment;\n\n    inverter_if dif();\n\n    inverter dut(.a(dif.a), .b(dif.b));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual inverter_if)::set(\"env\",\n            \"inverter_if\", dif);\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assert-final.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assert_final_test\n:description: assert final test\n:tags: 16.4\n*/\nmodule top();\n\nlogic a = 1;\n\nassert final (a != 0);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assert-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assert_test_uvm\n:description: assert test with UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule adder (\n    input clk,\n    input [7:0] a,\n    input [7:0] b,\n    output reg [8:0] c\n);\n\n    always @ (posedge clk) begin\n        c <= a + b;\n    end\n\nendmodule: adder\n\ninterface adder_if(\n    output bit clk,\n    output reg [7:0] a,\n    output reg [7:0] b,\n    input [8:0] c\n);\n\nendinterface: adder_if\n\nstring label = \"ASSERT_UVM\";\n\nclass env extends uvm_env;\n    virtual adder_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual adder_if)::read_by_name(\n            get_full_name(), \"adder_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            int a = 8'h35, b = 8'h79;\n            @(m_if.clk);\n            m_if.a <= a;\n            m_if.b <= b;\n\n            repeat(3) @(m_if.clk);\n                assert (m_if.c == (a + b)) else `uvm_error(label, $sformatf(\"c(%0d) != a + b(%0d) :assert: (False)\", m_if.c, a + b));\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top;\n    env environment;\n\n    adder_if dif();\n\n    adder dut(.clk(dif.clk), .a(dif.a), .b(dif.b), .c(dif.c));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual adder_if)::set(\"env\",\n            \"adder_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assert.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assert_test\n:description: assert test\n:tags: 16.2\n*/\nmodule top();\n\nlogic a = 1;\n\ninitial assert (a != 0);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assert0-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assert0_test_uvm\n:description: assert0 test with UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule inverter (\n    input [7:0] a,\n    output [7:0] b\n);\n\n    assign b = !a;\n\nendmodule: inverter\n\ninterface inverter_if(\n    output reg [7:0] a,\n    input [7:0] b\n);\n\nendinterface: inverter_if\n\nstring label = \"ASSERT0_UVM\";\n\nclass env extends uvm_env;\n    virtual inverter_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual inverter_if)::read_by_name(\n            get_full_name(), \"inverter_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            int a = 8'h35;\n            m_if.a <= a;\n\n            assert #0 (m_if.a != m_if.b) else $error($sformatf(\"assert failed :assert: (False)\"));\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top;\n    env environment;\n\n    inverter_if dif();\n\n    inverter dut(.a(dif.a), .b(dif.b));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual inverter_if)::set(\"env\",\n            \"inverter_if\", dif);\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assert0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assert0_test\n:description: assert #0 test\n:tags: 16.4\n*/\nmodule top();\n\nlogic a = 1;\n\nassert #0 (a != 0);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assume-final.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assume_final_test\n:description: assume final test\n:tags: 16.4\n*/\nmodule top(input logic a);\n\nassume final (a != 0);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assume-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assume_test_uvm\n:description: assert test with UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule adder (\n    input clk,\n    input [7:0] a,\n    input [7:0] b,\n    output reg [8:0] c\n);\n\n    always @ (posedge clk) begin\n        c <= a + b;\n    end\n\nendmodule: adder\n\ninterface adder_if(\n    output bit clk,\n    output reg [7:0] a,\n    output reg [7:0] b,\n    input [8:0] c\n);\n\nendinterface: adder_if\n\nstring label = \"ASSERT_UVM\";\n\nclass env extends uvm_env;\n    virtual adder_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual adder_if)::read_by_name(\n            get_full_name(), \"adder_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            int a = 8'h35, b = 8'h79;\n            @(m_if.clk);\n            m_if.a <= a;\n            m_if.b <= b;\n\n            repeat(3) @(m_if.clk);\n                assume (m_if.c == (a + b)) else `uvm_error(label, $sformatf(\"c(%0d) != a + b(%0d) :assert: (False)\", m_if.c, a + b));\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top;\n    env environment;\n\n    adder_if dif();\n\n    adder dut(.clk(dif.clk), .a(dif.a), .b(dif.b), .c(dif.c));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual adder_if)::set(\"env\",\n            \"adder_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assume.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assume_test\n:description: assume test\n:tags: 16.2\n*/\nmodule top(input logic a);\n\ninitial assume (a != 0);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--assume0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assume0_test\n:description: assume #0 test\n:tags: 16.4\n*/\nmodule top(input logic a);\n\nassume #0 (a != 0);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--cover-final.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cover_final_test\n:description: cover final test\n:tags: 16.4\n*/\nmodule top();\n\nlogic a = 1;\n\ncover final (a != 0);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--cover.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cover_test\n:description: cover test\n:tags: 16.2\n*/\nmodule top();\n\nlogic a = 1;\n\ninitial cover (a != 0);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.2--cover0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cover0_test\n:description: cover #0 test\n:tags: 16.4\n*/\nmodule top();\n\nlogic a = 1;\n\ncover #0 (a != 0);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.7--sequence-and-range-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_range_and_op_test_uvm\n:description: sequence with range and \"and\" operator in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mod (\n    input            clk,\n    input            req,\n    output reg       gnt0,\n    output reg       gnt1,\n    output reg       gnt2\n);\n\n    int cnt = 0;\n    bit req_old = 0;\n\n    initial begin\n        gnt0 = 0;\n        gnt1 = 0;\n        gnt2 = 0;\n    end\n\n    always @(posedge clk) begin\n        req_old <= req;\n        if (req & ~req_old) begin\n            cnt <= 0;\n            gnt0 <= 0;\n            gnt1 <= 0;\n            gnt2 <= 0;\n        end else begin\n            if (cnt < 16) begin\n                cnt <= cnt+1;\n            end\n            if (cnt == 3)\n                gnt0 <= 1;\n\n            if (cnt == 6)\n                gnt1 <= 1;\n\n            if (cnt == 7)\n                gnt2 <= 1;\n        end\n    end\n\nendmodule: mod\n\ninterface mod_if(\n    output bit clk,\n    output bit req,\n    input gnt0,\n    input gnt1,\n    input gnt2\n);\n\nendinterface: mod_if\n\nstring label = \"SEQUENCE_AND_UVM\";\n\nclass env extends uvm_env;\n    virtual mod_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mod_if)::read_by_name(\n            get_full_name(), \"mod_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mod_if dif();\n\n    mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mod_if)::set(\"env\",\n            \"mod_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        dif.req = 1;\n    end\n\n    sequence seq;\n        @(posedge dif.clk) ((dif.req ##[1:6] dif.gnt0) and (dif.req ##[1:9] dif.gnt1)) ##0 dif.gnt2;\n    endsequence\n\n    assert property (seq) else `uvm_error(label, $sformatf(\"seq failed :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.7--sequence-and-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_and_op_test_uvm\n:description: sequence with \"and\" operator in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mod (\n    input            clk,\n    input            req,\n    output reg       gnt0,\n    output reg       gnt1,\n    output reg       gnt2\n);\n\n    int cnt = 0;\n    bit req_old = 0;\n\n    initial begin\n        gnt0 = 0;\n        gnt1 = 0;\n        gnt2 = 0;\n    end\n\n    always @(posedge clk) begin\n        req_old <= req;\n        if (req & ~req_old) begin\n            cnt <= 0;\n            gnt0 <= 0;\n            gnt1 <= 0;\n            gnt2 <= 0;\n        end else begin\n            if (cnt < 16) begin\n                cnt <= cnt+1;\n            end\n            if (cnt == 3)\n                gnt0 <= 1;\n\n            if (cnt == 6)\n                gnt1 <= 1;\n\n            if (cnt == 7)\n                gnt2 <= 1;\n        end\n    end\n\nendmodule: mod\n\ninterface mod_if(\n    output bit clk,\n    output bit req,\n    input gnt0,\n    input gnt1,\n    input gnt2\n);\n\nendinterface: mod_if\n\nstring label = \"SEQUENCE_AND_UVM\";\n\nclass env extends uvm_env;\n    virtual mod_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mod_if)::read_by_name(\n            get_full_name(), \"mod_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mod_if dif();\n\n    mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mod_if)::set(\"env\",\n            \"mod_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        dif.req = 1;\n    end\n\n    sequence seq;\n        @(posedge dif.clk) ((dif.req ##5 dif.gnt0) and (dif.req ##8 dif.gnt1)) ##0 dif.gnt2;\n    endsequence\n\n    assert property (seq) else `uvm_error(label, $sformatf(\"seq failed :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.7--sequence-intersect-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_intersect_op_test_uvm\n:description: sequence with \"intersect\" operator in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mod (\n    input            clk,\n    input            req,\n    output reg       gnt0,\n    output reg       gnt1,\n    output reg       gnt2\n);\n\n    int cnt = 0;\n    bit req_old = 0;\n\n    initial begin\n        gnt0 = 0;\n        gnt1 = 0;\n        gnt2 = 0;\n    end\n\n    always @(posedge clk) begin\n        req_old <= req;\n        if (req & ~req_old) begin\n            cnt <= 0;\n            gnt0 <= 0;\n            gnt1 <= 0;\n            gnt2 <= 0;\n        end else begin\n            if (cnt < 16) begin\n                cnt <= cnt+1;\n            end\n            if (cnt == 3)\n                gnt0 <= 1;\n\n            if (cnt == 3)\n                gnt1 <= 1;\n\n            if (cnt == 7)\n                gnt2 <= 1;\n        end\n    end\n\nendmodule: mod\n\ninterface mod_if(\n    output bit clk,\n    output bit req,\n    input gnt0,\n    input gnt1,\n    input gnt2\n);\n\nendinterface: mod_if\n\nstring label = \"SEQUENCE_AND_UVM\";\n\nclass env extends uvm_env;\n    virtual mod_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mod_if)::read_by_name(\n            get_full_name(), \"mod_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mod_if dif();\n\n    mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mod_if)::set(\"env\",\n            \"mod_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        dif.req = 1;\n    end\n\n    sequence seq;\n        @(posedge dif.clk) (dif.req ##5 dif.gnt0) intersect (dif.req ##[1:9] dif.gnt1);\n    endsequence\n\n    assert property (seq) else `uvm_error(label, $sformatf(\"seq failed :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.7--sequence-or-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_or_op_test_uvm\n:description: sequence with \"or\" operator in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mod (\n    input            clk,\n    input            req,\n    output reg       gnt0,\n    output reg       gnt1,\n    output reg       gnt2\n);\n\n    int cnt = 0;\n    bit req_old = 0;\n\n    initial begin\n        gnt0 = 0;\n        gnt1 = 0;\n        gnt2 = 0;\n    end\n\n    always @(posedge clk) begin\n        req_old <= req;\n        if (req & ~req_old) begin\n            cnt <= 0;\n            gnt0 <= 0;\n            gnt1 <= 0;\n            gnt2 <= 0;\n        end else begin\n            if (cnt < 16) begin\n                cnt <= cnt+1;\n            end\n            if (cnt == 3)\n                gnt0 <= 1;\n\n            if (cnt == 6)\n                gnt1 <= 1;\n\n            if (cnt == 7)\n                gnt2 <= 1;\n        end\n    end\n\nendmodule: mod\n\ninterface mod_if(\n    output bit clk,\n    output bit req,\n    input gnt0,\n    input gnt1,\n    input gnt2\n);\n\nendinterface: mod_if\n\nstring label = \"SEQUENCE_AND_UVM\";\n\nclass env extends uvm_env;\n    virtual mod_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mod_if)::read_by_name(\n            get_full_name(), \"mod_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mod_if dif();\n\n    mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mod_if)::set(\"env\",\n            \"mod_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        dif.req = 1;\n    end\n\n    sequence seq;\n        @(posedge dif.clk) (dif.req ##5 dif.gnt0) or (dif.req ##3 dif.gnt1);\n    endsequence\n\n    assert property (seq) else `uvm_error(label, $sformatf(\"seq failed :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.7--sequence-throughout-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_throughout_op_test_uvm\n:description: sequence with \"throughout\" operator in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mod (\n    input            clk,\n    input            req,\n    output reg       gnt0,\n    output reg       gnt1,\n    output           gnt2\n);\n\n    int cnt = 0;\n    bit req_old = 0;\n\n    initial begin\n        gnt0 = 0;\n        gnt1 = 0;\n    end\n\n    assign gnt2 = req;\n\n    always @(posedge clk) begin\n        req_old <= req;\n        if (req & ~req_old) begin\n            cnt <= 0;\n            gnt0 <= 0;\n            gnt1 <= 0;\n        end else begin\n            if (cnt < 16) begin\n                cnt <= cnt+1;\n            end\n            if (cnt == 3)\n                gnt0 <= 1;\n\n            if (cnt == 3)\n                gnt1 <= 1;\n        end\n    end\n\nendmodule: mod\n\ninterface mod_if(\n    output bit clk,\n    output bit req,\n    input gnt0,\n    input gnt1,\n    input gnt2\n);\n\nendinterface: mod_if\n\nstring label = \"SEQUENCE_AND_UVM\";\n\nclass env extends uvm_env;\n    virtual mod_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mod_if)::read_by_name(\n            get_full_name(), \"mod_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mod_if dif();\n\n    mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mod_if)::set(\"env\",\n            \"mod_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    initial begin\n        dif.req = 1;\n    end\n\n    sequence seq;\n        @(posedge dif.clk) (dif.req ##5 dif.gnt0) intersect (dif.req ##[1:9] dif.gnt1);\n    endsequence\n\n    assert property (@(posedge dif.clk) dif.gnt2 throughout seq) else `uvm_error(label, $sformatf(\"seq failed :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.7--sequence-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_test_uvm\n:description: sequence in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule mem_ctrl (\n    input            clk,\n    output reg       read,\n    output reg       write,\n    output reg [7:0] addr,\n    output reg [7:0] dout,\n    input      [7:0] din\n);\n\n    reg       phase;\n    reg [7:0] addr_i;\n\n    initial begin\n        phase = 0;\n        read = 1;\n        write = 0;\n    end\n\n    always @(posedge clk) begin\n        read <= 0;\n        write <= 0;\n        addr <= addr_i;\n\n        if(phase) begin\n            read <= 1;\n        end else begin\n            write <= 1;\n        end\n\n        dout <= din;\n        addr_i <= addr_i + 1;\n        phase <= ~phase;\n    end\n\nendmodule: mem_ctrl\n\ninterface mem_ctrl_if(\n    output bit clk,\n    input read,\n    input write,\n    input [7:0] addr,\n    input [7:0] dout,\n    output reg [7:0] din\n);\n\nendinterface: mem_ctrl_if\n\nstring label = \"SEQUENCE_UVM\";\n\nclass env extends uvm_env;\n    virtual mem_ctrl_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name(\n            get_full_name(), \"mem_ctrl_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(1) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    mem_ctrl_if dif();\n\n    mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual mem_ctrl_if)::set(\"env\",\n            \"mem_ctrl_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    sequence seq;\n        @(posedge dif.clk) dif.read ##1 dif.write;\n    endsequence\n\n    assert property (seq) else `uvm_error(label, $sformatf(\"seq failed :assert: (False)\"));\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.7--sequence.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_test\n:description: sequence test\n:tags: 16.7\n:unsynthesizable: 1\n*/\n\nmodule top();\n\nlogic clk;\nlogic a;\nlogic b;\n\nsequence seq;\n    @(posedge clk) a ##1 b;\nendsequence\n\nassert property (seq);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.9--sequence-changed-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_changed_test_uvm\n:description: sequence with \"changed\" task in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input   clk,\n    output  out\n);\n\n    int cnt = 0;\n    bit clk_reg = 0;\n\n    assign out = clk_reg;\n\n    initial begin\n        cnt = 0;\n        clk_reg = 0;\n    end\n\n    always @(posedge clk) begin\n        cnt <= cnt + 1;\n\n        if (cnt > 5) begin\n            clk_reg = 1;\n            cnt = 5;\n        end\n    end\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit clk,\n    input out\n);\n\nendinterface: clk_gen_if\n\nstring label = \"SEQUENCE_FUNC_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    int cycle = 0;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.clk(dif.clk), .out(dif.out));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    sequence seq;\n        @(posedge dif.clk) $changed(dif.out);\n    endsequence\n\n    assert property (seq) else `uvm_info(label, $sformatf(\"$changed(dif.out) failed :assert: (%d != 8)\", cycle), UVM_LOW);\n\n    always @(posedge dif.clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.9--sequence-cons-repetition.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_consecutive_repetition_test\n:description: sequence with consecutive repetition operator test\n:tags: 16.9\n:unsynthesizable: 1\n*/\n\nmodule top();\n\nlogic clk;\nlogic a;\nlogic b;\n\nsequence seq;\n    @(posedge clk) b ##1 a [*2:10] ##1 b;\nendsequence\n\nassert property (seq);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.9--sequence-fell-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_fell_test_uvm\n:description: sequence with \"fell\" task in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input   clk,\n    output  out\n);\n\n    int cnt = 0;\n    bit clk_reg = 0;\n\n    assign out = clk_reg;\n\n    initial begin\n        cnt = 0;\n        clk_reg = 1;\n    end\n\n    always @(posedge clk) begin\n        cnt <= cnt + 1;\n\n        if (cnt > 5) begin\n            clk_reg = 0;\n            cnt = 5;\n        end\n    end\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit clk,\n    input out\n);\n\nendinterface: clk_gen_if\n\nstring label = \"SEQUENCE_FUNC_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    int cycle = 0;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.clk(dif.clk), .out(dif.out));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    sequence seq;\n        @(posedge dif.clk) $fell(dif.out);\n    endsequence\n\n    assert property (seq) else `uvm_info(label, $sformatf(\"$fell(dif.out) failed :assert: (%d != 8)\", cycle), UVM_LOW);\n\n    always @(posedge dif.clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.9--sequence-goto-repetition.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_goto_repetition_test\n:description: sequence with goto repetition operator test\n:tags: 16.9\n:unsynthesizable: 1\n*/\n\nmodule top();\n\nlogic clk;\nlogic a;\nlogic b;\n\nsequence seq;\n    @(posedge clk) b ##1 a [->2:10] ##1 b;\nendsequence\n\nassert property (seq);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.9--sequence-noncons-repetition.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_nonconsecutive_repetition_test\n:description: sequence with nonconsecutive repetition operator test\n:tags: 16.9\n:unsynthesizable: 1\n*/\n\nmodule top();\n\nlogic clk;\nlogic a;\nlogic b;\n\nsequence seq;\n    @(posedge clk) b ##1 a [=2:10] ##1 b; //should be equal to: b ##1 a ##1 a ##1 a ##1 b\nendsequence\n\nassert property (seq);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.9--sequence-past-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_past_test_uvm\n:description: sequence with \"past\" task in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input   clk,\n    output  out\n);\n\n    int cnt = 0;\n    bit clk_reg = 0;\n\n    assign out = clk_reg;\n\n    initial begin\n        cnt = 0;\n        clk_reg = 0;\n    end\n\n    always @(posedge clk) begin\n        cnt <= cnt + 1;\n\n        if (cnt > 5) begin\n            clk_reg = 1;\n            cnt = 5;\n        end\n    end\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit clk,\n    input out\n);\n\nendinterface: clk_gen_if\n\nstring label = \"SEQUENCE_FUNC_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    int cycle = 0;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.clk(dif.clk), .out(dif.out));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    sequence seq;\n        @(posedge dif.clk) ~$past(dif.out) & dif.out;\n    endsequence\n\n    assert property (seq) else `uvm_info(label, $sformatf(\"$past(dif.out) failed :assert: (%d != 8)\", cycle), UVM_LOW);\n\n    always @(posedge dif.clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.9--sequence-rose-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_rose_test_uvm\n:description: sequence with \"rose\" task in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input   clk,\n    output  out\n);\n\n    int cnt = 0;\n    bit clk_reg = 0;\n\n    assign out = clk_reg;\n\n    initial begin\n        cnt = 0;\n        clk_reg = 0;\n    end\n\n    always @(posedge clk) begin\n        cnt <= cnt + 1;\n\n        if (cnt > 5) begin\n            clk_reg = 1;\n            cnt = 5;\n        end\n    end\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit clk,\n    input out\n);\n\nendinterface: clk_gen_if\n\nstring label = \"SEQUENCE_FUNC_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    int cycle = 0;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.clk(dif.clk), .out(dif.out));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    sequence seq;\n        @(posedge dif.clk) $rose(dif.out);\n    endsequence\n\n    assert property (seq) else `uvm_info(label, $sformatf(\"$rose(dif.out) failed :assert: (%d != 8)\", cycle), UVM_LOW);\n\n    always @(posedge dif.clk)\n        cycle <= cycle + 1;\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-16/16.9--sequence-stable-uvm.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequence_stable_test_uvm\n:description: sequence with \"stable\" task in UVM\n:type: simulation elaboration parsing\n:tags: uvm uvm-assertions\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nmodule clk_gen(\n    input   clk,\n    output  out\n);\n\n    assign out = 0;\n\nendmodule: clk_gen\n\ninterface clk_gen_if(\n    output bit clk,\n    input out\n);\n\nendinterface: clk_gen_if\n\nstring label = \"SEQUENCE_FUNC_UVM\";\n\nclass env extends uvm_env;\n    virtual clk_gen_if m_if;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    function void connect_phase(uvm_phase phase);\n        `uvm_info(label, \"Started connect phase\", UVM_LOW);\n        assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name(\n            get_full_name(), \"clk_gen_if\", m_if));\n        `uvm_info(label, \"Finished connect phase\", UVM_LOW);\n    endfunction: connect_phase\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(label, \"Started run phase\", UVM_LOW);\n        begin\n            repeat(10) @(posedge m_if.clk);\n        end\n        `uvm_info(label, \"Finished run phase\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask: run_phase\nendclass\n\nmodule top();\n    env environment;\n\n    int cycle = 0;\n\n    clk_gen_if dif();\n\n    clk_gen dut(.clk(dif.clk), .out(dif.out));\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual clk_gen_if)::set(\"env\",\n            \"clk_gen_if\", dif);\n        dif.clk = 0;\n        run_test();\n    end\n\n    sequence seq;\n        @(posedge dif.clk) $stable(dif.out);\n    endsequence\n\n    assert property (seq) else `uvm_info(label, $sformatf(\"$stable(dif.out) returned false :assert: (%d == 1)\", cycle), UVM_LOW);\n\n    initial begin\n        forever begin\n            #(50) dif.clk = ~dif.clk;\n            cycle = cycle + 1;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.10--dynamic-constraint-modification_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dynamic_constraint_modification_0\n:description: dynamic constraint modification test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    constraint c { b dist { 3 := 0, 10 := 1}; }\nendclass\n\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize() with { b dist { 3 := 1, 10 := 0}; };\n\n      if(obj.b == 3) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.11--in-line-random-variable-control_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_random_variable-control_0\n:description: in-line random variable control test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x = 0, y = 0;\n    int v = 0, w = 0;\n    constraint c { x < v && y > w; };\nendclass\n\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      /* random variables: v, w state variables: x, y */\n      obj.randomize(v, w);\n\n      if(obj.x == 0 && obj.y == 0) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d obj.v = %0d obj.y = %0d obj.w = %0d SUCCESS\", obj.x, obj.v, obj.y, obj.w), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d obj.v = %0d obj.y = %0d obj.w = %0d FAILED\", obj.x, obj.v, obj.y, obj.w));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.11--in-line-random-variable-control_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_random_variable-control_1\n:description: in-line random variable control test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    randc bit [7:0] x = 0, y = 0;\n    bit [7:0] v = 0, w = 0;\n    constraint c { x < v && y > w; };\nendclass\n\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      /* random variables: v, w state variables: x, y */\n      obj.randomize(v, w);\n\n      if(obj.x == 0 && obj.y == 0) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d obj.v = %0d obj.y = %0d obj.w = %0d SUCCESS\", obj.x, obj.v, obj.y, obj.w), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d obj.v = %0d obj.y = %0d obj.w = %0d FAILED\", obj.x, obj.v, obj.y, obj.w));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.11.1--in-line-constraint-checker_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_constraint_checker_0\n:description: in-line constraint checker test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\n    int v;\n\n    constraint c1 { x < v; };\nendclass\n\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.x = 2;\n      obj.v = 1;\n      ret = obj.randomize(null);\n\n      if(ret == 0 && obj.x == 2 && obj.v == 1) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d obj.v = %0d SUCCESS\", obj.x, obj.v), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d obj.v = %0d FAILED\", obj.x, obj.v));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.11.1--in-line-constraint-checker_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_constraint_checker_1\n:description: in-line constraint checker test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    randc bit [7:0] x;\n    bit [7:0] v;\n\n    constraint c1 { x < v; };\nendclass\n\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.x = 2;\n      obj.v = 1;\n      ret = obj.randomize(null);\n\n      if(ret == 0 && obj.x == 2 && obj.v == 1) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d obj.v = %0d SUCCESS\", obj.x, obj.v), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d obj.v = %0d FAILED\", obj.x, obj.v));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.12--randomization-of-scope-variables_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: randomization_of_scope_variables_0\n:description: Randomization of scope variables - std::randomize() test\n:tags: 18.12\n*/\n\nclass a;\n    function int do_randomize();\n        int x, success;\n        success = std::randomize(x);\n        return success;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.12--randomization-of-scope-variables_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: randomization_of_scope_variables_1\n:description: Randomization of scope variables - std::randomize() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    function int do_randomize();\n        int x, success;\n        success = std::randomize(x);\n        return success;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      ret = obj.do_randomize();\n      if(ret == 1) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret = %0d SUCCESS\", ret), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret = %0d FAILED\", ret));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.12.1--adding-constraints-to-scope-variables_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: adding_constraints_to_scope_variables_0\n:description: Adding constraints to scope variables—std::randomize() with - test\n:tags: 18.12.1\n*/\n\nclass a;\n    function int do_randomize(int y);\n        int x, success;\n        success = std::randomize(x) with {x > 0; x < y;};\n        return success;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.12.1--adding-constraints-to-scope-variables_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: adding_constraints_to_scope_variables_1\n:description: Adding constraints to scope variables—std::randomize() with - test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    function int do_randomize(int y);\n        int x, success;\n        success = std::randomize(x) with {x > 0; x < y;};\n        return success;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret, y = 20;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      ret = obj.do_randomize(y);\n      if(ret == 1) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret = %0d SUCCESS\", ret), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret = %0d FAILED\", ret));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.13.1--urandom_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: urandom_0\n:description: urandom() test\n:tags: 18.13.1\n*/\n\nclass a;\n    function int unsigned do_urandom();\n        int unsigned x;\n        x = $urandom();\n        return x;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.13.1--urandom_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: urandom_1\n:description: urandom() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    function int unsigned do_urandom();\n        int unsigned x;\n        x = $urandom();\n        return x;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int unsigned ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      ret = obj.do_urandom();\n      if(ret >= 0) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret = %0d SUCCESS\", ret), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret = %0d FAILED\", ret));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.13.1--urandom_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: urandom_2\n:description: urandom() test\n:tags: 18.13.1\n*/\n\nclass a;\n    function int unsigned do_urandom(int seed);\n        int unsigned x;\n        x = $urandom(seed);\n        return x;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.13.1--urandom_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: urandom_3\n:description: urandom() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    function int unsigned do_urandom(int seed);\n        int unsigned x;\n        x = $urandom(seed);\n        return x;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int unsigned ret1, ret2;\n  int seed = 254;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      ret1 = obj.do_urandom(seed);\n      ret2 = obj.do_urandom(seed);\n      if(ret1 == ret2) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d SUCCESS\", ret1, ret2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d FAILED\", ret1, ret2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.13.2--urandom_range_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: urandom_range_0\n:description: urandom_range() test\n:tags: 18.13.2\n*/\n\nclass a;\n    function int do_urandom_range(int unsigned maxval, int unsigned minval);\n        int unsigned val;\n        val = $urandom_range(maxval, minval);\n        return val;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.13.2--urandom_range_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: urandom_range_1\n:description: urandom_range() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    function int unsigned do_urandom_range(int unsigned maxval, int unsigned minval);\n        int unsigned val;\n        val = $urandom_range(maxval, minval);\n        return val;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int unsigned max = 10, min = 1, ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      ret = obj.do_urandom_range(max, min);\n      if(ret >= min && ret <= max) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret = %0d SUCCESS\", ret), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret = %0d FAILED\", ret));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.13.2--urandom_range_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: urandom_range_2\n:description: urandom_range() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    function int unsigned do_urandom_range(int unsigned maxval, int unsigned minval);\n        int unsigned val;\n        val = $urandom_range(maxval, minval);\n        return val;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int unsigned max = 10, min = 1, ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      /* If max is less than min, then arguments should be automatically reversed */\n      ret = obj.do_urandom_range(min, max);\n      if(ret >= min && ret <= max) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret = %0d SUCCESS\", ret), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret = %0d FAILED\", ret));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.13.2--urandom_range_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: urandom_range_3\n:description: urandom_range() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    function int unsigned do_urandom_range(int unsigned maxval);\n        int unsigned val;\n        val = $urandom_range(maxval);\n        return val;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int unsigned max = 10, ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      ret = obj.do_urandom_range(max);\n      if(ret >= 0 && ret <= max) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret = %0d SUCCESS\", ret), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret = %0d FAILED\", ret));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.13.3--srandom_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: srandom_0\n:description: srandom() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\n    constraint c {x > 0 && x < 30;};\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret1, ret2, prev_x, seed = 20;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.srandom(seed);\n      ret1 = obj.randomize();\n      prev_x = obj.x;\n      obj.srandom(seed);\n      ret2 = obj.randomize();\n      if(ret1 == 1 && ret2 == 1 && obj.x > 0 && obj.x < 30 && prev_x == obj.x) begin\n        `uvm_info(\"RESULT\", $sformatf(\"prev_x = %0d obj.x = %0d SUCCESS\", prev_x, obj.x), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"prev_x = %0d obj.x = %0d FAILED\", prev_x, obj.x));\n      end\n\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.13.4--get_randstate_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: get_randstate_0\n:description: get_randstate() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  string randstate;\n  int ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n\n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      ret = obj.randomize();\n      randstate = obj.get_randstate();\n\n      if(ret == 1 && randstate != \"\") begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret = %0d randstate = %s SUCCESS\", ret, randstate), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret = %0d randstate = %s FAILED\", ret, randstate));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n\nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.13.5--set_randstate_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: set_randstate_0\n:description: set_randstate() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  string randstate;\n  int prev_x;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      randstate = obj.get_randstate();\n      obj.randomize();\n      prev_x = obj.x;\n      obj.set_randstate(randstate);\n      obj.randomize();\n\n      if(obj.x == prev_x) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d prev_x = %0d SUCCESS\", obj.x, prev_x), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d prev_x = %0d FAILED\", obj.x, prev_x));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.14--random-stability_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_stability_0\n:description: random stability - urandom_range test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass env extends uvm_env;\n  int unsigned val1, val2;\n  process p;\n  string randstate;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      p = process::self();\n      randstate = p.get_randstate();\n      val1 = $urandom_range(0, 1000);\n      p.set_randstate(randstate);\n      val2 = $urandom_range(0, 1000);\n\n      if(val1 == val2) begin\n        `uvm_info(\"RESULT\", $sformatf(\"val1 = %0d val2 = %0d SUCCESS\", val1, val2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"val1 = %0d val2 = %0d FAILED\", val1, val2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.14--random-stability_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_stability_1\n:description: random stability - shuffle test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass env extends uvm_env;\n  int tab1[5] = { 1, 2, 3, 4, 5 };\n  int tab2[5] = { 1, 2, 3, 4, 5 };\n  process p;\n  string randstate;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      p = process::self();\n      randstate = p.get_randstate();\n      tab1.shuffle;\n      p.set_randstate(randstate);\n      tab2.shuffle;\n\n      if(tab1 == tab2) begin\n        `uvm_info(\"RESULT\", $sformatf(\"tab1 = %p tab2 = %p SUCCESS\", tab1, tab2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"tab1 = %p tab2 = %p FAILED\", tab1, tab2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.14--random-stability_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_stability_2\n:description: random stability - randcase test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass env extends uvm_env;\n  int x, y;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      for (int i = 0; i < 10; i++)\n        randcase\n            0   :   x = x + 1;\n            1   :   y = y + 1;\n        endcase\n\n      if(x == 0 && y == 10) begin\n        `uvm_info(\"RESULT\", $sformatf(\"x = %0d y = %0d SUCCESS\", x, y), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"x = %0d y = %0d FAILED\", x, y));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.14--random-stability_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_stability_3\n:description: random stability - randcase test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass env extends uvm_env;\n  process p;\n  string randstate;\n  int x, y;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      p = process::self();\n      randstate = p.get_randstate();\n      randcase\n          2 : x = 1;\n          2 : x = 2;\n          2 : x = 3;\n          2 : x = 4;\n          2 : x = 5;\n      endcase\n\n      p.set_randstate(randstate);\n      randcase\n          2 : y = 1;\n          2 : y = 2;\n          2 : y = 3;\n          2 : y = 4;\n          2 : y = 5;\n      endcase\n\n      if(x == y) begin\n        `uvm_info(\"RESULT\", $sformatf(\"x = %0d y = %0d SUCCESS\", x, y), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"x = %0d y = %0d FAILED\", x, y));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.14.2--thread-stability_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: thread_stability_0\n:description: thread stability test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass env extends uvm_env;\n  int unsigned val1, val2;\n  process p1, p2;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n\n      fork\n        begin\n            p1 = process::self();\n            p1.srandom(100);\n            val1 = $urandom;\n        end\n        begin\n            p2 = process::self();\n            p2.srandom(100);\n            val2 = $urandom;\n        end\n      join\n\n      if(val1 == val2) begin\n        `uvm_info(\"RESULT\", $sformatf(\"val1 = %0d val2 = %0d SUCCESS\", val1, val2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"val1 = %0d val2 = %0d FAILED\", val1, val2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.14.2--thread-stability_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: thread_stability_1\n:description: thread stability test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass env extends uvm_env;\n  int unsigned val1, val2;\n  process p1, p2;\n  string randstate1, randstate2;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n\n      fork\n        begin\n            p1 = process::self();\n            randstate1 = p1.get_randstate();\n            val1 = $urandom;\n        end\n        begin\n            p2 = process::self();\n            randstate2 = p2.get_randstate();\n            val2 = $urandom;\n        end\n      join\n\n      if(val1 != val2 && randstate1 != randstate2) begin\n        `uvm_info(\"RESULT\", $sformatf(\"val1 = %0d val2 = %0d SUCCESS\", val1, val2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"val1 = %0d val2 = %0d FAILED\", val1, val2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.14.3--object-stability_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: object_stability_0\n:description: object stability test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a1;\n    rand int x;\nendclass\n\nclass a2;\n    rand int y;\nendclass\n\nclass env extends uvm_env;\n  a1 obj1 = new();\n  a2 obj2 = new();\n  string randstate1, randstate2;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      randstate1 = obj1.get_randstate();\n      randstate2 = obj2.get_randstate();\n      obj1.randomize();\n      obj2.randomize();\n\n      if(obj1.x != obj2.y && randstate1 != randstate2) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj1.x = %0d obj2.y = %0d SUCCESS\", obj1.x, obj2.y), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj1.x = %0d obj2.y = %0d FAILED\", obj1.x, obj2.y));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.14.3--object-stability_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: object_stability_1\n:description: object stability test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a1;\n    rand int x;\n    function new (int seed);\n        this.srandom(seed);\n    endfunction\nendclass\n\nclass a2;\n    rand int y;\n    function new (int seed);\n        this.srandom(seed);\n    endfunction\nendclass\n\nclass env extends uvm_env;\n  a1 obj1 = new(200);\n  a2 obj2 = new(200);\n  string randstate1, randstate2;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      randstate1 = obj1.get_randstate();\n      randstate2 = obj2.get_randstate();\n      obj1.randomize();\n      obj2.randomize();\n\n      if(obj1.x == obj2.y && randstate1 == randstate2) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj1.x = %0d obj2.y = %0d SUCCESS\", obj1.x, obj2.y), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj1.x = %0d obj2.y = %0d FAILED\", obj1.x, obj2.y));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.15--manually-seeding-randomize_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: manually_seeding_randomize_0\n:description: manually seeding randomize test\n:tags: 18.15\n:unsynthesizable: 1\n*/\n\nclass a;\n    rand int x;\n    function new (int seed);\n        this.srandom(seed);\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.15--manually-seeding-randomize_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: manually_seeding_randomize_1\n:description: manually seeding randomize test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\n    function new (int seed);\n        this.srandom(seed);\n    endfunction\nendclass\n\nclass env extends uvm_env;\n  a obj = new(100);\n  int prev_x;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      prev_x = obj.x;\n      obj.srandom(100);\n      obj.randomize();\n\n      if(obj.x == prev_x) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d prev_x = %0d SUCCESS\", obj.x, prev_x), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d prev_x = %0d FAILED\", obj.x, prev_x));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.16--random-weighted-case-randcase_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_weighted_case_randcase_0\n:description: randcase test\n:tags: 18.16\n:type: simulation elaboration parsing\n*/\n\nfunction int F();\n    int a;\n    randcase\n        0 : a = 5;\n        1 : a = 10;\n    endcase\n    return a;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (10 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.16--random-weighted-case-randcase_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_weighted_case_randcase_2\n:description: randcase test\n:tags: 18.16\n:type: simulation elaboration parsing\n*/\n\nfunction int F(int y);\n    int a;\n    randcase\n        y - y : a = 5;\n        y + y : a = 10;\n    endcase\n    return a;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F(6);\n      $display(\":assert: (10 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17--random-sequence-generation-randsequence_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_sequence_generation_randsequence_0\n:description: randsequence test\n:type: simulation elaboration parsing\n:tags: 18.17\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n        main : first second done;\n        first : { x = x + 1; };\n        second : { x = x + 2; };\n        done : { x = x + 3; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (6 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17--random-sequence-generation-randsequence_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_sequence_generation_randsequence_2\n:description: randsequence test\n:type: simulation elaboration parsing\n:tags: 18.17\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n        main : first | second;\n        first : { x = -2; };\n        second : { x = 2; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      if (x != 2 && x != -2) $stop;\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.1--random-production-weights_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_production_weights_0\n:description: randsequence weights test\n:type: simulation elaboration parsing\n:tags: 18.17.1\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n        main : first := 1 | second := 0;\n        first : { x = 2; };\n        second : { x = -2; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (2 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.2--if-else-production-statements_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_production_statements_0\n:description: randcase if-else test\n:type: simulation elaboration parsing\n:tags: 18.17.2\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    int switch = 1;\n    randsequence( main )\n      main : first;\n      first : { if(switch) x = 10; else x = 5; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      if (x != 10) $stop;\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.2--if-else-production-statements_0_fail.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_production_statements_0_fail\n:description: randcase if-else test\n:should_fail_because: switch variable not declared\n:type: elaboration\n:tags: 18.17.2\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n      main : first;\n      first : { if(switch ) x = 10; else x = 5; };\n    endsequence\n    return x;\nendfunction\n"
  },
  {
    "path": "tests/chapter-18/18.17.2--if-else-production-statements_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_production_statements_2\n:description: randcase if-else test\n:type: simulation elaboration parsing\n:tags: 18.17.2\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    int switch = 1;\n    randsequence( main )\n      main : first;\n      first : if(switch) second else third;\n      second : { x = 10; };\n      third : { x = 5; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (10 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.2--if-else-production-statements_2_fail.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_production_statements_2_fail\n:description: randcase if-else test\n:should_fail_because: switch variable not declared\n:type: elaboration\n:tags: 18.17.2\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n      main : first;\n      first : if(switch) second else third;\n      second : { x = 10; };\n      third : { x = 5; };\n    endsequence\n    return x;\nendfunction\n"
  },
  {
    "path": "tests/chapter-18/18.17.3--case-production-statements_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: case_production_statements_0\n:description: randcase case statement test\n:type: simulation elaboration parsing\n:tags: 18.17.3\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    int switch = 1;\n    randsequence( main )\n      main : case (switch)\n          0 : zero;\n          1 : first;\n          2 : second;\n          default : third;\n      endcase;\n      zero : { x = 0; };\n      first : { x = 10; };\n      second : { x = 2; };\n      third : { x = 3; };\n    endsequence\n\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (10 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.3--case-production-statements_0_fail.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: case_production_statements_0_fail\n:description: randcase case statement test\n:should_fail_because: switch variable not declared\n:type: elaboration\n:tags: 18.17.3\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n      main : case (switch)\n          0 : zero;\n          1 : first;\n          2 : second;\n          default : third;\n      endcase;\n      zero2 : { x = 0; };\n      first : { x = 10; };\n      second : { x = 2; };\n      third : { x = 3; };\n    endsequence\n\n    return x;\nendfunction\n"
  },
  {
    "path": "tests/chapter-18/18.17.4--repeat-production-statements_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: repeat_production_statements_0\n:description: repeat statement test\n:type: simulation elaboration parsing\n:tags: 18.17.4\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n      main : first;\n      first : repeat(10) second;\n      second : { x = x + 1; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (10 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.5--interleaving-productions-rand-join_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: interleaving_productions_rand_join_0\n:description: rand join statement test\n:type: simulation elaboration parsing\n:tags: 18.17.5\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n      main : rand join first second;\n      first : { x = x + 20; };\n      second : { x = x - 10; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (10 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.5--interleaving-productions-rand-join_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: interleaving_productions_rand_join_2\n:description: rand join statement test\n:type: simulation elaboration parsing\n:tags: 18.17.5\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n      main : rand join (0.5) first second;\n      first : { x = x + 20; };\n      second : { x = x - 10; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (10 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.6--aborting-productions-break-and-return_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: aborting_productions_break_and_return_0\n:description: break statement test\n:type: simulation elaboration parsing\n:tags: 18.17.6\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    int break_on = 1;\n\n    randsequence( main )\n      main : first second third;\n      first : { x = x + 10; };\n      second : { if(break_on == 1) break; } fourth;\n      third : { x = x + 10; };\n      fourth : { x = x + 15; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (10 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.6--aborting-productions-break-and-return_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: aborting_productions_break_and_return_2\n:description: return statement test\n:type: simulation elaboration parsing\n:tags: 18.17.6\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    static int return_on = 1;\n    randsequence( main )\n      main : first second third;\n      first : { x = x + 20; };\n      second : { if(return_on == 1) return; x = x + 10; };\n      third : { x = x + 5;};\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (25 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.17.6--aborting-productions-break-and-return_2_fail.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: aborting_productions_break_and_return_2_fail\n:description: return statement test\n:should_fail_because: typo in production name\n:type: elaboration\n:tags: 18.17.6\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    static int return_on = 1;\n    randsequence( main )\n      main : first secondi third;\n      first : { x = x + 20; };\n      second : { if(return_on == 1) return; x = x + 10; };\n      third : { x = x + 5;};\n    endsequence\n    return x;\nendfunction\n"
  },
  {
    "path": "tests/chapter-18/18.17.7--value-passing-between-productions_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: value_passing_between_productions_0\n:description: value passing in randsequence test\n:type: simulation elaboration parsing\n:tags: 18.17.7\n:unsynthesizable: 1\n*/\n\nfunction int F();\n    int x;\n    randsequence( main )\n      main : first second third;\n      first : add(10);\n      second : add(5);\n      third : add(2);\n      void add(int y) : { x = x + y; };\n    endsequence\n    return x;\nendfunction\n\nmodule top;\n   int x;\n   initial begin\n      x = F();\n      $display(\":assert: (17 == %d)\", x);\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.4.1--rand-modifier.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: rand_modifier\n:description: rand modifier test\n:tags: 18.4.1\n*/\n\nclass a;\n    rand int b;\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.4.2--randc-modifier.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: randc_modifier\n:description: randc modifier test\n:tags: 18.4.2\n*/\n\nclass a;\n    randc int b;\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5--constraint-blocks_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constraint_blocks_0\n:description: constraint blocks test\n:tags: 18.5\n*/\n\nclass a;\n    rand int b;\n    constraint c { b == 0; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5--constraint-blocks_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constraint_blocks_1\n:description: constraint blocks test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    constraint c { b == 5; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 5) begin\n        `uvm_info(\"RESULT\", $sformatf(\"b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.1--explicit-external-constraint_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: explicit_external_constraint_0\n:description: explicit external constraint test\n:tags: 18.5.1\n*/\n\nclass a;\n    rand int b;\n    extern constraint c;\nendclass\n\nconstraint a::c { b == 0; }\n"
  },
  {
    "path": "tests/chapter-18/18.5.1--explicit-external-constraint_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: explicit_external_constraint_1\n:description: explicit external constraint test\n:should_fail_because: explicit contraint needs to be defined\n:tags: 18.5.1\n:type: simulation elaboration\n*/\n\nclass a;\n    rand int b;\n    extern constraint c;\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.1--explicit-external-constraint_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: explicit_external_constraint_2\n:description: explicit external constraint test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    extern constraint c;\nendclass\n\nconstraint a::c { b == 5; }\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 5) begin\n        `uvm_info(\"RESULT\", $sformatf(\"b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.1--implicit-external-constraint_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implicit_external_constraint_0\n:description: implicit external constraint test\n:tags: 18.5.1\n*/\n\nclass a;\n    rand int b;\n    constraint c;\nendclass\n\nconstraint a::c { b == 0; }\n"
  },
  {
    "path": "tests/chapter-18/18.5.1--implicit-external-constraint_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implicit_external_constraint_1\n:description: implicit external constraint test\n:tags: 18.5.1\n*/\n\nclass a;\n    rand int b;\n    constraint c;\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.1--implicit-external-constraint_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implicit_external_constraint_2\n:description: implicit external constraint test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    constraint c;\nendclass\n\nconstraint a::c { b == 5; }\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 5) begin\n        `uvm_info(\"RESULT\", $sformatf(\"b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.10--variable-ordering_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: variable_ordering_0\n:description: variable ordering test\n:tags: 18.5.10\n*/\n\nclass a;\n    rand bit b1;\n    rand int b2;\n\n    constraint c1 { b1 -> b2 == 0; }\n    constraint c2 { solve b1 before b2; }\nendclass\n\n"
  },
  {
    "path": "tests/chapter-18/18.5.10--variable-ordering_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: variable_ordering_1\n:description: variable ordering test\n:should_fail_because: randc vars are not allowed, they are always solved before any other\n:tags: 18.5.10\n:type: simulation elaboration\n*/\n\nclass a;\n    rand bit b1;\n    randc int b2;\n\n    constraint c1 { b1 -> b2 == 0; }\n    constraint c2 { solve b1 before b2; }\nendclass\n\n"
  },
  {
    "path": "tests/chapter-18/18.5.11--static-constraint-blocks_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: static_constraint_blocks_0\n:description: static constraint blocks test\n:tags: 18.5.11\n:unsynthesizable: 1\n*/\n\nclass a;\n    rand int b;\n\n    static constraint c1 { b == 5; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.11--static-constraint-blocks_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: static_constraint_blocks_1\n:description: static constraint blocks test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n\n    static constraint c1 { b == 5; }\n    static constraint c2 { b == 2; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj1 = new;\n  a obj2 = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n    /* shall affect all instances of constraint c2 */\n    obj1.c1.constraint_mode(0);\n  endfunction\n\n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj1.randomize();\n      obj2.randomize();\n      if(obj1.b == 2 && obj2.b == 2) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj1.b = %0d obj2.b = %0d SUCCESS\", obj1.b, obj2.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj1.b = %0d obj2.b = %0d FAILED\", obj1.b, obj2.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n\nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.12--functions-in-constraint_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: functions_in_constraints_0\n:description: functions in constraints test\n:tags: 18.5.12\n*/\n\nclass a;\n    rand int b1, b2;\n    function int F (input int d);\n        F=d;\n    endfunction\n\n    constraint c1 { b1 == 5; }\n    constraint c2 { b2 == F(b1); }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.12--functions-in-constraint_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: functions_in_constraint_1\n:description: functions in constraint test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b1, b2;\n    function int F (input int d);\n        F=d;\n    endfunction\n\n    constraint c1 { b1 == 5; }\n    constraint c2 { b2 == F(b1); }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b2 == 5) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b2 = %0d SUCCESS\", obj.b2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b2 = %0d FAILED\", obj.b2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.13--constraint-guards_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constraint_guards_0\n:description: constraint guards test\n:tags: 18.5.13\n*/\n\nclass b;\n    int d1;\nendclass\n\nclass a;\n    rand int b1;\n    b next;\n\n    constraint c1 { if (next == null) b1 == 5; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.13--constraint-guards_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constraint_guards_1\n:description: constraint guards test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass b;\n    int d1;\nendclass\n\nclass a;\n    rand int b1;\n    b next;\n\n    constraint c1 { if (next == null) b1 == 5; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj1 = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj1.randomize();\n      if(obj1.b1 == 5) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj1.b1 = %0d SUCCESS\", obj1.b1), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj1.b1 = %0d FAILED\", obj1.b1));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.14--soft-constraints_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: soft_constraints_0\n:description: soft constraints test\n:tags: 18.5.14\n*/\n\n\nclass a;\n    rand int b;\n\n    constraint c {\n        soft b > 4;\n        soft b < 12; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.14--soft-constraints_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: soft_constraints_1\n:description: soft constraints test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n\n    constraint c {\n        soft b > 4;\n        soft b < 12;\n    }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b > 4 && obj.b < 12) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.14--soft-constraints_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: soft_constraints_2\n:description: soft constraints test\n:should_fail_because: Soft constraints can only be specified on random variables; they may not be specified for randc variables.\n:tags: 18.5.14\n:type: simulation elaboration\n*/\n\n\nclass a;\n    randc int b;\n\n    constraint c {\n        soft b > 4;\n        soft b < 12; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.1--soft-constraint-priorities_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: soft_constraint_priorities_0\n:description: soft constraint priorities test\n:tags: 18.5.14.1\n*/\n\n\nclass a1;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\nendclass\n\nclass a2 extends a1;\n    constraint c2 { soft b == 20; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.1--soft-constraint-priorities_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: soft_constraint_priorities_1\n:description: soft constraint priorities test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a1;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\nendclass\n\nclass a2 extends a1;\n    constraint c2 { soft b == 20; }\nendclass\n\nclass env extends uvm_env;\n\n  a2 obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 20) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.1--soft-constraint-priorities_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: soft_constraint_priorities_2\n:description: soft constraint priorities test\n:tags: 18.5.14.1\n*/\n\n\nclass a1;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\nendclass\n\nclass a2 extends a1;\n    constraint c2 { soft b == 20; }\n    constraint c3;\nendclass\n\nconstraint a2::c3 { soft b > 100; };\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.1--soft-constraint-priorities_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: soft_constraint_priorities_3\n:description: soft constraint priorities test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a1;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\nendclass\n\nclass a2 extends a1;\n    constraint c2 { soft b == 20; }\n    constraint c3;\nendclass\n\nconstraint a2::c3 { soft b > 100; };\n\nclass env extends uvm_env;\n\n  a2 obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b > 100) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.1--soft-constraint-priorities_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: soft_constraint_priorities_4\n:description: soft constraint priorities test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a1;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\nendclass\n\nclass a2 extends a1;\n\n    constraint c2 {soft b == 20; }\n    constraint c3;\nendclass\n\nconstraint a2::c3 { soft b > 100; };\n\nclass env extends uvm_env;\n\n  a2 obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize() with { soft b == 90; };\n      if(obj.b == 90) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.2--discarding-soft-constraints_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: discarding_soft_constraints_0\n:description: discarding soft constraints test\n:tags: 18.5.14.2\n*/\n\n\nclass a;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\n\n    constraint c2 { disable soft b; }\n    constraint c3 { soft b == 20; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.2--discarding-soft-constraints_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: discarding_soft_constraints_1\n:description: discarding soft constraints test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\n\n    constraint c2 { disable soft b; }\n    constraint c3 { soft b == 20; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 20) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.2--discarding-soft-constraints_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: discarding_soft_constraints_2\n:description: discarding soft constraints test\n:tags: 18.5.14.2\n*/\n\n\nclass a;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\n\n    constraint c2 { disable soft b; soft b == 20; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.2--discarding-soft-constraints_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: discarding_soft_constraints_3\n:description: discarding soft constraints test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\n\n    constraint c2 { disable soft b; }\n    constraint c3 { soft b == 20; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 20) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.14.2--discarding-soft-constraints_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: discarding_soft_constraints_5\n:description: discarding soft constraints test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n\n    constraint c1 {\n        soft b > 4;\n        soft b < 12; }\n\n    constraint c2 { disable soft b; }\n    constraint c3 { soft b == 20; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 20) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.2--constraint-inheritance_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constraint_inheritance_0\n:description: contraint inheritance test\n:tags: 18.5.2\n*/\n\nclass a;\n    rand int b;\n    constraint c { b == 5; };\nendclass\n\nclass a2 extends a;\n    rand int b2;\n    constraint c2 { b2 == b; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.2--constraint-inheritance_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constraint_inheritance_1\n:description: contraint inheritance test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    constraint c { b == 5; };\nendclass\n\nclass a2 extends a;\n    rand int b2;\n    constraint c2 { b2 == b; }\nendclass\n\nclass env extends uvm_env;\n\n  a2 obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b2 == 5) begin\n        `uvm_info(\"RESULT\", $sformatf(\"b2 = %0d SUCCESS\", obj.b2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b2 = %0d FAILED\", obj.b2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.2--pure-constraint_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pure_constraint_0\n:description: pure constraint test\n:tags: 18.5.2\n:unsynthesizable: 1\n*/\n\nvirtual class a;\n    pure constraint c;\nendclass\n\nclass a2 extends a;\n    rand int b2;\n    constraint c { b2 == 5; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.2--pure-constraint_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pure_constraint_1\n:description: pure constraint test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nvirtual class a;\n    pure constraint c;\nendclass\n\nclass a2 extends a;\n    rand int b2;\n    constraint c { b2 == 5; }\nendclass\n\nclass env extends uvm_env;\n\n  a2 obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b2 == 5) begin\n        `uvm_info(\"RESULT\", $sformatf(\"b2 = %0d SUCCESS\", obj.b2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b2 = %0d FAILED\", obj.b2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.2--pure-constraint_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pure_constraint_2\n:description: pure constraint test\n:should_fail_because: pure constraint must be implemented by non-virtual class\n:tags: 18.5.2\n:type: simulation elaboration\n*/\n\nvirtual class a;\n    pure constraint c;\nendclass\n\nclass a2 extends a;\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.2--pure-constraint_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pure_constraint_3\n:description: pure constraint test\n:tags: 18.5.2\n*/\n\nvirtual class a;\n    pure constraint c;\nendclass\n\nvirtual class a2 extends a;\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.3--set-membership_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: set_membership_0\n:description: set membership test\n:tags: 18.5.3\n*/\n\nclass a;\n    rand int b;\n    constraint c { b inside {3, 10}; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.3--set-membership_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: set_membership_1\n:description: set membership test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    constraint c { b inside {3, 10}; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b inside {3, 10}) begin\n        `uvm_info(\"RESULT\", $sformatf(\"b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.4--distribution_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: distribution_0\n:description: distribution test\n:tags: 18.5.4\n*/\n\nclass a;\n    rand int b;\n    constraint c { b dist {3 := 1, 10 := 2}; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.4--distribution_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: distribution_1\n:description: distribution test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    constraint c { b dist {3 := 0, 10 := 5}; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 10) begin\n        `uvm_info(\"RESULT\", $sformatf(\"b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.4--distribution_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: distribution_2\n:description: distribution test\n:should_fail_because: distribution shall not be applied to randc variables\n:tags: 18.5.4\n:type: simulation elaboration\n*/\n\nclass a;\n    randc int b;\n    constraint c { b dist {3 := 0, 10 := 5}; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.5--uniqueness-constraints_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uniqueness_constraints_0\n:description: uniqueness constraints test\n:tags: 18.5.5\n*/\n\nclass a;\n    rand int b1, b2;\n    constraint c1 { b1 inside {3, 10}; }\n    constraint c2 { b2 inside {3, 10}; }\n    constraint c3 { unique {b1, b2}; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.5--uniqueness-constraints_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uniqueness_constraints_1\n:description: uniqueness constraints test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b1, b2;\n    constraint c1 { b1 inside {3, 10}; }\n    constraint c2 { b2 inside {3, 10}; }\n    constraint c3 { unique {b1, b2}; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if((obj.b1 == 3 && obj.b2 == 10) ||\n         (obj.b2 == 3 && obj.b1 == 10))\n      begin\n        `uvm_info(\"RESULT\", $sformatf(\"b1 = %0d b2 = %0d SUCCESS\", obj.b1, obj.b2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b1 = %0d b2 = %0d FAILED\", obj.b1, obj.b2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.6--implication_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implication_0\n:description: implication test\n:tags: 18.5.6\n*/\n\nclass a;\n    rand int b1, b2;\n    constraint c1 { b1 == 5; }\n    constraint c2 { b1 == 5 -> b2 == 10; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.6--implication_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implication_1\n:description: implication test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b1, b2;\n    constraint c1 { b1 == 5; }\n    constraint c2 { b1 == 5 -> b2 == 10; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b1 == 5 && obj.b2 == 10) begin\n        `uvm_info(\"RESULT\", $sformatf(\"b1 = %0d b2 = %0d SUCCESS\", obj.b1, obj.b2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b1 = %0d b2 = %0d FAILED\", obj.b1, obj.b2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.7--if-else-constraints_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_constraints_0\n:description: if-else constraints test\n:tags: 18.5.7\n*/\n\nclass a;\n    rand int b1, b2;\n    constraint c1 { b1 == 5; }\n    constraint c2 { if(b1 == 5) b2 == 10; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.7--if-else-constraints_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_constraints_1\n:description: if-else constraints test\n:tags: 18.5.7\n*/\n\nclass a;\n    rand int b1, b2;\n    constraint c1 { b1 == 5; }\n    constraint c2 { if (b1 == 0) b2 == 10;\n                    else b2 == 15;}\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.7--if-else-constraints_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_constraints_2\n:description: if-else constraints test\n:tags: 18.5.7\n*/\n\nclass a;\n    rand int b1, b2;\n    constraint c1 { b1 == 5; }\n    constraint c2 { if (b1 == 0) b2 == 10;\n                    else if (b1 == 5) b2 == 3; \n                    else b2 == 15;}\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.7--if-else-constraints_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_constraints_3\n:description: if-else constraints test\n:tags: 18.5.7\n*/\n\nclass a;\n    rand int b1, b2, b3;\n    constraint c1 { b1 == 5; }\n    constraint c2 { b2 == 3; }\n    constraint c3 { if (b1 == 0)\n                      if (b2 == 2) b3 == 4; \n                      else b3 == 10;}\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.7--if-else-constraints_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: if_else_constraints_4\n:description: if-else constraints test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b1, b2, b3;\n    constraint c1 { b1 == 5; }\n    constraint c2 { b2 == 3; }\n    constraint c3 { if (b1 == 5)\n                      if (b2 == 2) b3 == 4; \n                      else b3 == 10;}\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b3 == 10) begin\n        `uvm_info(\"RESULT\", $sformatf(\"b3 = %0d SUCCESS\", obj.b3), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"b3 = %0d FAILED\", obj.b3));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.8.1--foreach-iterative-constraints_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: foreach_iterative_constraints_0\n:description: foreach iterative constraints test\n:tags: 18.5.8.1\n:unsynthesizable: 1\n*/\n\nclass a;\n    rand int B[5];\n    constraint c { foreach ( B [ i ] ) B[i] == 5; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.8.1--foreach-iterative-constraints_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: foreach_iterative_constraints_1\n:description: foreach iterative constraints test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int B[5];\n    constraint c { foreach ( B [ i ] ) B[i] == 5; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.B.sum() == 25) begin\n        `uvm_info(\"RESULT\", $sformatf(\"sum = %0d SUCCESS\", obj.B.sum()), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"sum = %0d FAILED\", obj.B.sum()));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.8.2--array-reduction-iterative-constraints_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array_reduction_iterative_constraints_0\n:description: array reduction iterative constraints test\n:tags: 18.5.8.2\n*/\n\nclass a;\n    rand int B[5];\n    constraint c { B.sum() == 5; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.8.2--array-reduction-iterative-constraints_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array_reduction_iterative_constraints_1\n:description: array reduction iterative constraints test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int B[5];\n    constraint c { B.sum() == 5; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.B.sum() == 5) begin\n        `uvm_info(\"RESULT\", $sformatf(\"sum = %0d SUCCESS\", obj.B.sum()), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"sum = %0d FAILED\", obj.B.sum()));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.5.9--global-constraints_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: global_constraints_0\n:description: global constraints test\n:tags: 18.5.9\n*/\n\nclass a;\n    rand int v;\nendclass\n\nclass b;\n    rand a aObj;\n    rand int v;\n\n    constraint c { aObj.v < v; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.5.9--global-constraints_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: global_constraints_1\n:description: global constraints test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int v;\nendclass\n\nclass b extends a;\n    rand a aObj;\n\n    constraint c { aObj.v < v; }\nendclass\n\nclass env extends uvm_env;\n\n  b bObj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      bObj.randomize();\n      if(bObj.aObj.v < bObj.v) begin\n        `uvm_info(\"RESULT\", $sformatf(\"%0d < %0d SUCCESS\", bObj.aObj.v, bObj.v), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"%0d !< %0d FAILED\", bObj.aObj.v, bObj.v));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.6.1--randomize-method_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: randomize_method_0\n:description: randomize() method test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    constraint c { b == 20; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      int success = obj.randomize();\n      if(success == 1) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.6.2--post-randomize_method_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: post_randomize_method_0\n:description: post_randomize() method test\n:tags: 18.6.2\n*/\n\nclass a;\n    rand int b;\n    int d;\n\n    constraint c { b == 5; }\n    function void post_randomize();\n        d = 20;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.6.2--post-randomize_method_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: post_randomize_method_1\n:description: post_randomize() method test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    int d;\n\n    constraint c { b == 5; }\n    function void post_randomize();\n        d = 20;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 5 && obj.d == 20) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d obj.d = %0d SUCCESS\", obj.b, obj.d), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d obj.d = %0d FAILED\", obj.b, obj.d));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.6.2--pre-randomize-method_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pre_randomize_method_0\n:description: pre_randomize() method test\n:tags: 18.6.2\n*/\n\nclass a;\n    rand int b;\n    int d;\n\n    constraint c { b == 5; }\n    function void pre_randomize();\n        d = 20;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.6.2--pre-randomize-method_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pre_randomize_method_1\n:description: pre_randomize() method test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    int d;\n\n    constraint c { b == 5; }\n    function void pre_randomize();\n        d = 20;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n      if(obj.b == 5 && obj.d == 20) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d obj.d = %0d SUCCESS\", obj.b, obj.d), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d obj.d = %0d FAILED\", obj.b, obj.d));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.6.3--behavior-of-randomization-methods_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: behavior_of_randomization_methods_0\n:description: static random variables test\n:tags: 18.6.3\n:unsynthesizable: 1\n*/\n\nclass a;\n    static rand int b;\n    constraint c { b > 5; b < 12; }\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.6.3--behavior-of-randomization-methods_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: behavior_of_randomization_methods_1\n:description: static random variables test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    static rand int b;\n    constraint c { b > 5; b < 12; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj1 = new;\n  a obj2 = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj1.randomize();\n      if(obj1.b == obj2.b) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj1.b = %0d obj2.b = %0d SUCCESS\", obj1.b, obj2.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj1.b = %0d obj2.b = %0d FAILED\", obj1.b, obj2.b));\n      end\n\n      obj2.randomize();\n      if(obj1.b == obj2.b) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj1.b = %0d obj2.b = %0d SUCCESS\", obj1.b, obj2.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj1.b = %0d obj2.b = %0d FAILED\", obj1.b, obj2.b));\n      end\n\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.6.3--behavior-of-randomization-methods_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: behavior_of_randomization_methods_2\n:description: If randomize() fails, the constraints are infeasible, and the random variables retain their previous values.\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b = 1;\n\n    /* Create infeasible constraint */\n    constraint c { b == 0 && b > 0; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int prev_value, status;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      prev_value = obj.b;\n      status = obj.randomize();\n\n      if(status == 0 && prev_value == obj.b) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d prev_value = %0d SUCCESS\", obj.b, prev_value), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d prev_value = %0d FAILED\", obj.b, prev_value));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.6.3--behavior-of-randomization-methods_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: behavior_of_randomization_methods_3\n:description: If randomize() fails, post_randomize() is not called.\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    int d = 1;\n\n    constraint c { b == 0 && b > 0; }\n\n    function void post_randomize();\n        d = 20;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int status;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      status = obj.randomize();\n\n      if(status == 0 && obj.d == 1) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.d = %0d SUCCESS\", obj.d), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.d = %0d FAILED\", obj.d));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.6.3--behavior-of-randomization-methods_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: behavior_of_randomization_methods_4\n:description: behavior of randomization methods test\n:should_fail_because: The randomize() method is built-in and cannot be overridden.\n:tags: 18.6.3\n:type: simulation elaboration\n*/\n\nclass a;\n    rand int b;\n    constraint c { b > 5 && b < 12; }\n\n    function void randomize();\n        b = 7;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.6.3--behavior-of-randomization-methods_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: behavior_of_randomization_methods_5\n:description:  behavior of randomization methods test\n:should_fail_because: The randomize() method is built-in and cannot be overridden.\n:tags: uvm-random uvm\n:type: simulation elaboration\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int b;\n    constraint c { b > 5 && b < 12; }\n\n    function void randomize();\n        b = 7;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize();\n\n      if(b > 5 && b < 12) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.b = %0d SUCCESS\", obj.b), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.b = %0d FAILED\", obj.b));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.7--in-line-constraints--randomize_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_constraints--randomize_0\n:description: in-line constraints test - randomize()\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand bit [7:0] x, y, z;\n    constraint c { z == x + y; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.randomize() with { x < y; };\n      if(obj.z == obj.x + obj.y && obj.x < obj.y) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d obj.y = %0d obj.z = %0d SUCCESS\", obj.x, obj.y, obj.z), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d obj.y = %0d obj.z = %0d FAILED\", obj.x, obj.y, obj.z));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.7--in-line-constraints--randomize_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_constraints--randomize_1\n:description: in-line constraints test - randomize()\n:tags: 18.7\n:unsynthesizable: 1\n*/\n\nclass a1;\n    rand int x;\nendclass\n\nclass a2;\n    int x, y;\n\n    task do_randomize(a1 obj, int x, int z);\n        int result;\n        result = obj.randomize() with {x > 0; x < y + z;};\n    endtask\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.7--in-line-constraints--randomize_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_constraints--randomize_2\n:description: in-line constraints test - randomize()\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a1;\n    rand int x;\nendclass\n\nclass a2;\n    int x, y;\n\n    task do_randomize(a1 obj, int x, int z);\n        int result;\n        /* In the line below x should be a member of class a1 */\n        result = obj.randomize() with {x > 0; x < y + z;};\n    endtask\nendclass\n\nclass env extends uvm_env;\n\n  a1 obj1 = new;\n  a2 obj2 = new;\n  int z;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj2.x = -20;\n      obj2.y = 5;\n      z = 10;\n      obj2.do_randomize(obj1, -20, z);\n      if(obj1.x > 0 && obj1.x < obj2.y + z) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj1.x = %0d obj2.x = %0d obj2.y = %0d SUCCESS\", obj1.x, obj2.x, obj2.y), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj1.x = %0d obj2.x = %0d obj2.y = %0d FAILED\", obj1.x, obj2.x, obj2.y));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.7--in-line-constraints--randomize_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_constraints--randomize_3\n:description: in-line constraints test - randomize()\n:tags: 18.7\n*/\n\nclass a;\n    rand int x;\nendclass\n\nfunction int F(a obj, int y);\n    F = obj.randomize() with (x) { x > 0; x < y; };\nendfunction\n"
  },
  {
    "path": "tests/chapter-18/18.7--in-line-constraints--randomize_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_constraints--randomize_4\n:description: in-line constraints test - randomize()\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\nendclass\n\nfunction int F(a obj, int y);\n    F = obj.randomize() with (x) { x > 0; x < y; };\nendfunction\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int y;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      y = 10;\n      F(obj, y);\n      if(obj.x > 0 && obj.x < y) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d y = %0d SUCCESS\", obj.x, y), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d y = %0d FAILED\", obj.x, y));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.7--in-line-constraints--randomize_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_constraints--randomize_5\n:description: in-line constraints test - randomize()\n:tags: 18.7\n*/\n\nclass a;\n    rand int x;\n    int y = -1;\nendclass\n\nfunction int F(a obj, int y);\n    F = obj.randomize() with (x) { x > 0; x < y; };\nendfunction\n"
  },
  {
    "path": "tests/chapter-18/18.7--in-line-constraints--randomize_6.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: in-line_constraints--randomize_6\n:description: in-line constraints test - randomize()\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\n    int y = -1;\nendclass\n\nfunction int F(a obj, int y);\n    F = obj.randomize() with (x) { x > 0; x < y; };\nendfunction\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int y;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      y = 10;\n      F(obj, y);\n      if(obj.x > 0 && obj.x < y) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d y = %0d SUCCESS\", obj.x, y), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d y = %0d FAILED\", obj.x, y));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.7.1--local-scope-resolution_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: local_scope_resolution_0\n:description: local:: scope resolution test\n:tags: 18.7.1\n*/\n\nclass a;\n    rand int x;\nendclass\n\nfunction int F(a obj, int x);\n    F = obj.randomize() with {x < local::x; };\nendfunction\n"
  },
  {
    "path": "tests/chapter-18/18.7.1--local-scope-resolution_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: local_scope_resolution_1\n:description: local:: scope resolution test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\nendclass\n\nfunction int F(a obj, int x);\n    F = obj.randomize() with {x > 0; x < local::x; };\nendfunction\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int x;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      x = 10;\n      F(obj, x);\n      if(obj.x < x) begin\n        `uvm_info(\"RESULT\", $sformatf(\"obj.x = %0d x = %0d SUCCESS\", obj.x, x), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"obj.x = %0d x = %0d FAILED\", obj.x, x));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: disabling-random-variables-with-rand_mode_0\n:description: rand_mode() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\n    constraint c {x > 0; x < 12; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret1, ret2;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.x.rand_mode(0);\n      ret1 = obj.x.rand_mode();\n      ret2 = obj.randomize();\n      if(ret1 == 0 && ret2 == 0) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d SUCCESS\", ret1, ret2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d FAILED\", ret1, ret2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: disabling-random-variables-with-rand_mode_1\n:description: rand_mode() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    randc bit [7:0] x;\n    constraint c {x > 0; x < 12; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret1, ret2;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.x.rand_mode(0);\n      ret1 = obj.x.rand_mode();\n      ret2 = obj.randomize();\n      if(ret1 == 0 && ret2 == 0) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d SUCCESS\", ret1, ret2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d FAILED\", ret1, ret2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: disabling-random-variables-with-rand_mode_2\n:description: rand_mode() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x, y;\n    constraint c {x > 0; x < 12; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret1, ret2;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.rand_mode(0);\n      obj.x.rand_mode(1);\n      ret1 = obj.x.rand_mode();\n      ret2 = obj.randomize();\n      if(ret1 == 1 && ret2 == 1 && obj.x > 0 && obj.x < 12) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d obj.x = %0d SUCCESS\", ret1, ret2, obj.x), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d obj.x = %0d FAILED\", ret1, ret2, obj.x));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: disabling-random-variables-with-rand_mode_3\n:description: rand_mode() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    static rand int x;\n    constraint c {x > 0; x < 12; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj1 = new;\n  a obj2 = new;\n  int ret1, ret2;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj1.x.rand_mode(0);\n      ret1 = obj1.x.rand_mode();\n      ret2 = obj2.x.rand_mode();\n\n      if(ret1 == 0 && ret2 == 0) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d SUCCESS\", ret1, ret2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d FAILED\", ret1, ret2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: disabling-random-variables-with-rand_mode_4\n:description: rand_mode() test\n:should_fail_because: The rand_mode() method is built-in and cannot be overridden.\n:tags: 18.8\n:type: simulation elaboration\n*/\n\nclass a1;\n    rand int x;\n    function int rand_mode();\n        return 1;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: disabling-random-variables-with-rand_mode_5\n:description: rand_mode() test\n:should_fail_because: The rand_mode() method is built-in and cannot be overridden.\n:tags: uvm-random uvm\n:type: simulation elaboration\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\n    function int rand_mode();\n        return 1;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      ret = obj.x.rand_mode();\n\n      if(ret == 1) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret = %0d SUCCESS\", ret), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret = %0d FAILED\", ret));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.9--controlling-constraints-with-constraint_mode_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: controlling-constraints-with-constraint_mode_0\n:description: constraint_mode() test\n:tags: uvm-random uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\n    constraint c1 { x < 0; }\n    constraint c2 { x > 0; }\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret1, ret2;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      obj.c1.constraint_mode(0);\n      ret1 = obj.c1.constraint_mode();\n      ret2 = obj.c2.constraint_mode();\n      obj.randomize();\n      if(obj.x > 0 && ret1 == 0 && ret2 == 1) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d SUCCESS\", ret1, ret2), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret1 = %0d ret2 = %0d FAILED\", ret1, ret2));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-18/18.9--controlling-constraints-with-constraint_mode_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: controlling_constraints_with_constraint_mode_1\n:description: constraint_mode() test\n:should_fail_because: The constraint_mode() method is built-in and cannot be overridden.\n:tags: 18.8\n:type: simulation elaboration\n*/\n\nclass a;\n    rand int x;\n    function int constraint_mode();\n        return 1;\n    endfunction\nendclass\n"
  },
  {
    "path": "tests/chapter-18/18.9--controlling-constraints-with-constraint_mode_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: controlling-constraints-with-constraint_mode_2\n:description: constraint_mode() test\n:should_fail_because: The constraint_mode() method is built-in and cannot be overridden.\n:tags: uvm-random uvm\n:type: simulation elaboration\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass a;\n    rand int x;\n    function int constraint_mode();\n        return 1;\n    endfunction\nendclass\n\nclass env extends uvm_env;\n\n  a obj = new;\n  int ret;\n\n  function new(string name, uvm_component parent = null);\n    super.new(name, parent);\n  endfunction\n  \n  task run_phase(uvm_phase phase);\n    phase.raise_objection(this);\n    begin\n      ret = obj.constraint_mode();\n\n      if(ret == 1) begin\n        `uvm_info(\"RESULT\", $sformatf(\"ret = %0d SUCCESS\", ret), UVM_LOW);\n      end else begin\n        `uvm_error(\"RESULT\", $sformatf(\"ret = %0d FAILED\", ret));\n      end\n    end\n    phase.drop_objection(this);\n  endtask: run_phase\n  \nendclass\n\nmodule top;\n\n  env environment;\n\n  initial begin\n    environment = new(\"env\");\n    run_test();\n  end\n  \nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.10--error.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: error_task\n:description: $error test\n:tags: 20.10\n:type: parsing\n  Note this is not a simulation test, as the $warning may result in some\n  simulators returning bad exit status.\n:unsynthesizable: 1\n*/\n\nmodule top();\n\ninitial begin\n\t$error(\"error\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.10--fatal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fatal_task\n:description: $fatal test\n:tags: 20.10\n:type: parsing\n  Note this is not a simulation test, as the $warning may result in some\n  simulators returning bad exit status.\n:unsynthesizable: 1\n*/\n\nmodule top();\n\ninitial begin\n\t$fatal(2, \"fatal\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.10--info.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: info_task\n:description: $info test\n:tags: 20.10\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\n\nmodule top();\n\ninitial begin\n\t$info(\"info\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.10--warning.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: warning_task\n:description: $warning test\n:tags: 20.10\n:type: parsing\n  Note this is not a simulation test, as the $warning may result in some\n  simulators returning bad exit status.\n:unsynthesizable: 1\n*/\n\nmodule top();\n\ninitial begin\n\t$warning(\"warning\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.14--coverage.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: coverage_routines\n:description: coverage routine test\n:tags: 20.14\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\n\nmodule DUT;\nendmodule\n\nmodule top();\n    int unsigned i;\n    real r;\n    DUT unit1();\n    DUT unit2();\n\n    initial begin\n        i = $coverage_control(`SV_COV_CHECK, `SV_COV_TOGGLE, `SV_COV_HIER, $root);\n        i = $coverage_control(`SV_COV_RESET, `SV_COV_TOGGLE, `SV_COV_MODULE, \"DUT\");\n        i = $coverage_control(`SV_COV_RESET, `SV_COV_TOGGLE, `SV_COV_MODULE, $root.top.unit1);\n        i = $coverage_control(`SV_COV_STOP,  `SV_COV_TOGGLE, `SV_COV_HIER, $root.top.unit2);\n        i = $coverage_control(`SV_COV_START, `SV_COV_TOGGLE, `SV_COV_HIER, \"DUT\");\n        i = $coverage_get_max(`SV_COV_TOGGLE, `SV_COV_HIER, \"DUT\");\n        r = $coverage_get(`SV_COV_STATEMENT, `SV_COV_HIER, $root.top.unit1);\n        i = $coverage_merge(`SV_COV_ASSERTION, \"some_name\");\n        i = $coverage_save(`SV_COV_FSM_STATE, \"some_name\");\n        $set_coverage_db_name(\"coverage.db\");\n        $load_coverage_db(\"coverage.db\");\n        r = $get_coverage();\n    end\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.15--dist_chi_square.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dist_chi_square_function\n:description: $dist_chi_square test\n:tags: 20.15\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tinteger seed = 1234;\n\t$display(\"%d\", $dist_chi_square(seed, 3));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.15--dist_erlang.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dist_erlang_function\n:description: $dist_erlang test\n:tags: 20.15\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tinteger seed = 1234;\n\t$display(\"%d\", $dist_erlang(seed,  3, 100));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.15--dist_exponential.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dist_exponential_function\n:description: $dist_exponential test\n:tags: 20.15\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tinteger seed = 1234;\n\t$display(\"%d\", $dist_exponential(seed, 100));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.15--dist_normal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dist_normal_function\n:description: $dist_normal test\n:tags: 20.15\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tinteger seed = 1234;\n\t$display(\"%d\", $dist_normal(seed, 0, 100));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.15--dist_poisson.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dist_poisson_function\n:description: $dist_poisson test\n:tags: 20.15\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tinteger seed = 1234;\n\t$display(\"%d\", $dist_poisson(seed, 100));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.15--dist_t.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dist_t_function\n:description: $dist_t test\n:tags: 20.15\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tinteger seed = 1234;\n\t$display(\"%d\", $dist_t(seed, 3));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.15--dist_uniform.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dist_uniform_function\n:description: $dist_uniform test\n:tags: 20.15\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tinteger seed = 1234;\n\t$display(\"%d\", $dist_uniform(seed, 0, 100));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.15--random.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: random_function\n:description: $random test\n:tags: 20.15\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\"%d\", $random);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.2--exit.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: exit_task\n:description: $exit test\n:tags: 20.2\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial\n\t$exit;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.2--finish.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: finish_task\n:description: $finish test\n:tags: 20.2\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial\n\t$finish;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.2--stop.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: stop_task\n:description: $stop test\n:tags: 20.2\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial\n\t$stop;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.3--realtime.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: realtime_task\n:description: $realtime test\n:tags: 20.3\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial\n\t$display($realtime);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.3--stime.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: stime_task\n:description: $stime test\n:tags: 20.3\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial\n\t$display($stime);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.3--time.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: time_task\n:description: $time test\n:tags: 20.3\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial\n\t$display($time);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.4--printtimescale-hier.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: printtimescale_hier_task\n:description: $printtimescale hierarchy test\n:tags: 20.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\n\n`timescale 1 ms / 1 us\n\nmodule top();\n\ninitial\n\t$printtimescale(mod0.m);\n\nendmodule\n\n`timescale 1 us / 1 ns\n\nmodule mod0();\n\tmod1 m();\nendmodule\n\n`timescale 1 ns / 1 ps\n\nmodule mod1();\ninitial\n\t$display(\"mod1\");\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.4--printtimescale.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: printtimescale_task\n:description: $printtimescale test\n:tags: 20.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\n\n`timescale 1 ms / 1 us\n\nmodule top();\n\ninitial\n\t$printtimescale;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.4--timeformat.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: timeformat_task\n:description: $timeformat test\n:tags: 20.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\n\n`timescale 1 fs / 1 fs\n\nmodule top();\n\ninitial begin\n\t$timeformat(-9, 5, \"ns\", 10);\n\t$display(\"%t\", $realtime);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.5--itor.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: itor_function\n:description: $itor test\n:tags: 20.5\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%f == 20.0)\", $itor(20));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.5--real-bits-conv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: realtobits_bitstoreal_functions\n:description: $realtobits and $bitstoreal test\n:tags: 20.5\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%f == 12.45)\", $bitstoreal($realtobits(12.45)));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.5--rtoi.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: rtoi_function\n:description: $rtoi test\n:tags: 20.5\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%d == 21)\", $rtoi(21.37));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.5--shortreal-bits-conv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: shortrealtobits_bitstoshortreal_functions\n:description: $shortrealtobits and $bitstoshortreal test\n:tags: 20.5\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\n\nmodule top();\n\n\tshortreal s;\n\ninitial begin\n\ts = $bitstoshortreal($shortrealtobits(12.45));\n\t$display(\":assert: (%0d == 1)\", (s > 12.449 && s < 12.451));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.6--bits.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: bits_function\n:description: $bits test\n:tags: 20.6\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tlogic [31:0] val;\n\t$display(\":assert: (%d == 32)\", $bits(val));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.6--bits_type.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: bits_type_function\n:description: $bits with type argument\n:tags: 20.6\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ntypedef struct packed {\n\tlogic val1;\n\tbit [7:0] val2;\n} mystruct;\n\ninitial begin\n\t$display(\":assert: (%d == 9)\", $bits(mystruct));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.6--isunbounded.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: isunbounded_function\n:description: $isunbounded test\n:tags: 20.6\n:type: simulation elaboration parsing\n*/\n\nmodule top();\nparameter int i = $;\n\ninitial begin\n\t$display(\":assert: (%d == 0)\", $isunbounded(1));\n\t$display(\":assert: (%d == 1)\", $isunbounded(i));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.6--typename.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typename_function\n:description: $typename test\n:tags: 20.6\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tlogic val;\n\t$display(\":assert: ('%s' == 'logic')\", $typename(val));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.6--typename_type.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typename_type_function\n:description: $typename with type as an argument\n:tags: 20.6\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: ('%s' == 'logic')\", $typename(logic));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.7--array-queries-multi-dim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array_queries_multi_dim\n:description: multi-dimensional array query function tests\n:tags: 20.7\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\nlogic [31:0] arr [15:0];\n\ninitial begin\n\t$display(\":assert: (%d == 2)\", $dimensions(arr));\n\t$display(\":assert: (%d == 1)\", $increment(arr, 2));\n\t$display(\":assert: (%d == 0)\", $right(arr, 2));\n\t$display(\":assert: (%d == 31)\", $left(arr, 2));\n\t$display(\":assert: (%d == 0)\", $right(arr, 1));\n\t$display(\":assert: (%d == 15)\", $left(arr, 1));\n\t$display(\":assert: (%d == 0)\", $low(arr, 2));\n\t$display(\":assert: (%d == 31)\", $high(arr, 2));\n\t$display(\":assert: (%d == 32)\", $size(arr, 2));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.7--array-queries.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array_queries\n:description: array query function tests\n:tags: 20.7\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\nlogic [31:0] arr;\n\ninitial begin\n\t$display(\":assert: (%d == 0)\", $unpacked_dimensions(arr));\n\t$display(\":assert: (%d == 1)\", $dimensions(arr));\n\t$display(\":assert: (%d == 1)\", $increment(arr));\n\t$display(\":assert: (%d == 0)\", $right(arr));\n\t$display(\":assert: (%d == 31)\", $left(arr));\n\t$display(\":assert: (%d == 0)\", $low(arr));\n\t$display(\":assert: (%d == 31)\", $high(arr));\n\t$display(\":assert: (%d == 32)\", $size(arr));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--atan2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: atan2_function\n:description: $atan2 test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\"%f\", $atan2(2.1, 3.7));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--ceil.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: ceil_function\n:description: $ceil test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%f == 4)\", $ceil(3.7));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--clog2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: clog2_function\n:description: $clog2 test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%d == 5)\", $clog2(32));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--exp.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: exp_function\n:description: $exp test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%f > 2.718) and (%f < 2.719)\", $exp(1), $exp(1));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--floor.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: floor_function\n:description: $floor test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%f == 2)\", $floor(2.1));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--hypot.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: hypot_function\n:description: $hypot test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\"%f\", $hypot(2.1, 3.7));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--ln.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: ln_function\n:description: $ln test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%d == 0)\", $ln(1));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--log10.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: log10_function\n:description: $log10 test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%d == 2)\", $log10(100));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--pow.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pow_function\n:description: $pow test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%f == 5.0625)\", $pow(2.25, 2));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.8--sqrt.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sqrt_function\n:description: $sqrt test\n:tags: 20.8\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\t$display(\":assert: (%d == 3)\", $sqrt(9));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.9--countbits.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: countbits_function\n:description: $countbits test\n:tags: 20.9\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tlogic [31:0] val = 32'h70008421;\n\t$display(\":assert: (%d == 7)\", $countbits(val, '1));\n\t$display(\":assert: (%d == 7)\", $countones(val));\n\t$display(\":assert: (%d == 25)\", $countbits(val, '0));\n\t$display(\":assert: (%d == 32)\", $countbits(val, '0, '1));\n\t$display(\":assert: (%d == 0)\", $countbits(val, 'x, 'z));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.9--isunknown.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: isunknown_function\n:description: $isunknown test\n:tags: 20.9\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tparameter [3:0] val0 = 4'b000x;\n\tparameter [3:0] val1 = 4'b000z;\n\tparameter [3:0] val2 = 4'b00xz;\n\tparameter [3:0] val3 = 4'b0000;\n\t$display(\":assert: (%d == 1)\", $isunknown(val0));\n\t$display(\":assert: (%d == 1)\", $isunknown(val1));\n\t$display(\":assert: (%d == 1)\", $isunknown(val2));\n\t$display(\":assert: (%d == 0)\", $isunknown(val3));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.9--onehot.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: onehot_function\n:description: $onehot test\n:tags: 20.9\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tlogic [31:0] val0 = 32'h00010000;\n\tlogic [31:0] val1 = 32'h00010100;\n\tlogic [31:0] val2 = 32'h00000000;\n\t$display(\":assert: (%d == 1)\", $onehot(val0));\n\t$display(\":assert: (%d == 0)\", $onehot(val1));\n\t$display(\":assert: (%d == 0)\", $onehot(val2));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-20/20.9--onehot0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: onehot0_function\n:description: $onehot0 test\n:tags: 20.9\n:type: simulation elaboration parsing\n*/\n\nmodule top();\n\ninitial begin\n\tlogic [31:0] val0 = 32'h00010000;\n\tlogic [31:0] val1 = 32'h00030000;\n\tlogic [31:0] val2 = 32'h00000000;\n\t$display(\":assert: (%d == 1)\", $onehot0(val0));\n\t$display(\":assert: (%d == 0)\", $onehot0(val1));\n\t$display(\":assert: (%d == 1)\", $onehot0(val2));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.2--display-boh.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: display_boh\n:description: $display test\n:tags: 21.2\n:type: simulation elaboration parsing\n*/\nmodule top();\n\ninitial begin\n\tint val = 1234;\n\t$displayb(val);\n\t$displayo(val);\n\t$displayh(val);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.2--display.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: display_task\n:description: $display test\n:tags: 21.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial begin\n\tint val = 1234;\n\t$display(val);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.2--monitor.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: monitor_task\n:description: $monitor test\n:tags: 21.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nint a;\n\ninitial begin\n\t$monitoron;\n\t$monitor(a);\n\t$monitorb(a);\n\t$monitoro(a);\n\t$monitorh(a);\n\t$monitoroff;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.2--strobe.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: strobe_task\n:description: $strobe test\n:tags: 21.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nlogic clk;\nint a;\n\nalways @(posedge clk) begin\n\t$strobe(a);\n\t$strobeb(a);\n\t$strobeo(a);\n\t$strobeh(a);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.2--write-boh.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: write_boh\n:description: $write test\n:tags: 21.2\n:type: simulation elaboration parsing\n*/\nmodule top();\n\ninitial begin\n\tint val = 1234;\n\t$writeb(val);\n\t$writeo(val);\n\t$writeh(val);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.2--write.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: write_task\n:description: $write test\n:tags: 21.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial begin\n\tint val = 1234;\n\t$write(val);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fdisplay-boh.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fdisplay_boh\n:description: $fdisplay test\n:tags: 21.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nint fd;\nstring str = \"abc\";\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fdisplayb(fd, str);\n\t$fdisplayo(fd, str);\n\t$fdisplayh(fd, str);\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fdisplay.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fdisplay_task\n:description: $fdisplay test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nint fd;\nstring str = \"abc\";\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fdisplay(fd, str);\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--feof.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: feof_function\n:description: $feof test\n:tags: 21.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\ninitial begin\n\tint fd;\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$display($feof(fd));\n\t$fclose(fd);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--ferror.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: ferror_function\n:description: $ferror test\n:tags: 21.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\ninitial begin\n\tint fd;\n\tstring str;\n\tinteger errno;\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\terrno = $ferror(fd, str);\n\t$display(errno);\n\t$display(str);\n\t$fclose(fd);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fflush.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fflush_task\n:description: $fflush test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial begin\n\tint fd;\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fflush();\n\t$fclose(fd);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fgetc.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fgetc_function\n:description: $fgetc test\n:tags: 21.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nint fd;\nint c;\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\tc = $fgetc(fd);\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fgets.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fgets_function\n:description: $fgets test\n:tags: 21.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nint fd;\nstring tmp;\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fgets(tmp, fd);\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--file.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: file_tasks\n:description: $fopen and $fclose test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial begin\n\tint fd;\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fclose(fd);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fmonitor.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fmonitor_task\n:description: $fmonitor test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nlogic a;\n\nint fd;\nstring str = \"abc\";\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fmonitor(fd, a);\n\t$fmonitorb(fd, a);\n\t$fmonitoro(fd, a);\n\t$fmonitorh(fd, a);\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fpos.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: file_pos_tasks\n:description: $fseek, $ftell and $rewind test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\ninitial begin\n\tint fd;\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$display(\":assert: (%d == 0)\", $ftell(fd));\n\t$fseek(fd, 12, 0);\n\t$display(\":assert: (%d == 12)\", $ftell(fd));\n\t$rewind(fd);\n\t$display(\":assert: (%d == 0)\", $ftell(fd));\n\t$fclose(fd);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fread.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fread_task\n:description: $fread test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nint fd;\nint c;\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fread(c, fd);\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fscanf.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fscanf_task\n:description: $fscanf test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nint fd;\nint c;\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fscanf(fd, \"%d\", c);\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fstrobe.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fstrobe_task\n:description: $fstrobe test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nlogic clk;\nlogic a;\n\nint fd;\n\nalways @(posedge clk) begin\n\t$fstrobe(fd, a);\n\t$fstrobe(fd, a);\n\t$fstrobe(fd, a);\n\t$fstrobe(fd, a);\nend\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fwrite-boh.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fwrite_boh\n:description: $fwrite test\n:tags: 21.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nint fd;\nstring str = \"abc\";\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fwriteb(fd, str);\n\t$fwriteo(fd, str);\n\t$fwriteh(fd, str);\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--fwrite.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fwrite_task\n:description: $fwrite test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nint fd;\nstring str = \"abc\";\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$fwrite(fd, str);\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--sscanf.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sscanf_task\n:description: $sscanf test\n:tags: 21.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\nstring str = \"1234\";\nint c;\n\ninitial begin\n\t$sscanf(str, \"%d\", c);\n\t$display(\":assert: (%d == %s)\", c, str);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.3--ungetc.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: ungetc_function\n:description: $ungetc test\n:tags: 21.3\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nint fd;\n\ninitial begin\n\tfd = $fopen(\"tmp.txt\", \"w\");\n\t$ungetc(123, fd);\n\t$display(\":assert: (%d == %d)\", 123, $fgetc(fd));\nend\n\nfinal\n\t$fclose(fd);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.4--readmemb.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: readmemb_task\n:description: $readmemb test\n:tags: 21.4\n:type: parsing\n*/\nmodule top();\n\nlogic [31:0] mem0 [1023:0];\nstring fname0 = \"test0.mem\";\n\ninitial begin\n\t$readmemb(fname0, mem0);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.4--readmemh.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: readmemh_task\n:description: $readmemh test\n:tags: 21.4\n:type: parsing\n*/\nmodule top();\n\nlogic [31:0] mem1 [1023:0];\nstring fname1 = \"test1.mem\";\n\ninitial begin\n\t$readmemh(fname1, mem1);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.6--test.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: test_plusargs\n:description: $test$plusargs test\n:tags: 21.6\n:type: simulation elaboration parsing\n*/\nmodule top();\n\ninitial begin\n\tif ($test$plusargs(\"TEST\")) $display(\"TEST argument found\");\n\telse $display(\"TEST argument not found\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.6--value.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: value_plusargs\n:description: $value$plusargs test\n:tags: 21.6\n:type: simulation elaboration parsing\n*/\nmodule top();\n\ninteger i;\n\ninitial begin\n\tif ($value$plusargs(\"TEST=%d\", i)) $display(\"i=%d\", i);\n\telse\n\t\t$display(\"TEST not found\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.7--dumpfile.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: vcd_dump_test\n:description: vcd dump tests\n:tags: 21.7\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\ninteger i;\n\ninitial begin\n\t$dumpfile(\"out.vcd\");\n\t$dumpvars;\n\t$dumplimit(1024*1024);\n\n\ti = 1;\n\t#100 i = 2;\n\t#200 $dumpoff;\n\ti = 3;\n\t#800 $dumpon;\n\ti = 4;\n\t#100 $dumpflush;\n\ti = 5;\n\t#300 $dumpall;\n\ti = 6;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-21/21.7--dumpports.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: vcd_dumpports_test\n:description: vcd dump ports tests\n:tags: 21.7\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top();\n\ninteger i;\nstring fname = \"out.vcd\";\n\ninitial begin\n\t$dumpports(top, fname);\n\t$dumpportslimit(1024*1024, fname);\n\n\ti = 1;\n\t#100 i = 2;\n\t#200 $dumpportsoff(fname);\n\ti = 3;\n\t#800 $dumpportson(fname);\n\ti = 4;\n\t#100 $dumpportsflush(fname);\n\ti = 5;\n\t#300 $dumpportsall(fname);\n\ti = 6;\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.10--celldefine-basic-1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.10--celldefine-basic-1\n:description: Test\n:tags: 22.10\n:type: preprocessing\n*/\n`celldefine\n`endcelldefine\n"
  },
  {
    "path": "tests/chapter-22/22.10--celldefine-basic-2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.10--celldefine-basic-2\n:description: Test\n:tags: 22.10\n:type: preprocessing\n*/\n`celldefine\n"
  },
  {
    "path": "tests/chapter-22/22.11--pragma-basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.11--pragma-basic\n:description: Test\n:tags: 22.11\n:type: preprocessing\n*/\n`pragma pragma_name \"pragma_value\"\n"
  },
  {
    "path": "tests/chapter-22/22.11--pragma-complex.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.11--pragma-complex\n:description: Test\n:tags: 22.11\n:type: preprocessing\n*/\n`pragma foo something, somethingelse = 7, \"abcdef\"\n"
  },
  {
    "path": "tests/chapter-22/22.11--pragma-invalid.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.11--pragma-invalid\n:description: Test\n:should_fail_because: The pragma specification is identified by the pragma_name, which follows the `pragma directive.\n:tags: 22.11\n:type: preprocessing\n*/\n`pragma\n"
  },
  {
    "path": "tests/chapter-22/22.11--pragma-nested.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.11--pragma-nested\n:description: Test\n:tags: 22.11\n:type: preprocessing\n*/\n`pragma foo something, somethingelse = 7, \"abcdef\", ( hello, ( \"world\", pr = 4, \"gm\" ) ), a\n"
  },
  {
    "path": "tests/chapter-22/22.11--pragma-number-multi.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.11--pragma-number-multi\n:description: Test\n:tags: 22.11\n:type: preprocessing\n*/\n`pragma pragma_number_other a = 123, b = 4\n"
  },
  {
    "path": "tests/chapter-22/22.11--pragma-number.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.11--pragma-number\n:description: Test\n:tags: 22.11\n:type: preprocessing\n*/\n`pragma pragma_number 123\n"
  },
  {
    "path": "tests/chapter-22/22.12--line-basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.12--line-basic\n:description: Test\n:tags: 22.12\n:type: preprocessing\n*/\n`line 1 \"somefile\" 2\n"
  },
  {
    "path": "tests/chapter-22/22.12--line-complex.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.12--line-complex\n:description: Test\n:tags: 22.12\n:type: preprocessing\n*/\n`line 1 \"somefile\" 2\n`line 123 \"someother\" 1\n`line 8273 \"somefile\" 0\n`resetall\n`line 5 \"foo\" 2\n"
  },
  {
    "path": "tests/chapter-22/22.12--line-illegal-1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.12--line-illegal-1\n:description: The level parameter shall be 0, 1, or 2\n:should_fail_because: The level parameter shall be 0, 1, or 2\n:tags: 22.12\n:type: preprocessing\n*/\n`line 1 \"somefile\" 3\n"
  },
  {
    "path": "tests/chapter-22/22.12--line-illegal-2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.12--line-illegal-2\n:description: The filename parameter shall be a string literal\n:should_fail_because: The filename parameter shall be a string literal\n:tags: 22.12\n:type: preprocessing\n*/\n`line 1 somefile 2\n"
  },
  {
    "path": "tests/chapter-22/22.12--line-illegal-3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.12--line-illegal-3\n:description: The number parameter shall be a positive integer that specifies the new line number\n:should_fail_because: The number parameter shall be a positive integer that specifies the new line number\n:tags: 22.12\n:type: preprocessing\n*/\n`line -12 \"somefile\" 3\n"
  },
  {
    "path": "tests/chapter-22/22.12--line-illegal-4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.12--line-illegal-4\n:description: The level parameter shall be 0, 1, or 2\n:should_fail_because: The level parameter shall be 0, 1, or 2\n:tags: 22.12\n:type: preprocessing\n*/\n`line 1 \"somefile\"\n"
  },
  {
    "path": "tests/chapter-22/22.12--line-illegal-5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.12--line-illegal-5\n:description: Missing filename \n:should_fail_because: Missing filename \n:tags: 22.12\n:type: preprocessing\n*/\n`line 1\n"
  },
  {
    "path": "tests/chapter-22/22.3--resetall_basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.3--resetall_basic\n:description: Test\n:tags: 22.3\n:type: preprocessing parsing\n*/\n`resetall\nmodule top ();\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.3--resetall_illegal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.3--resetall_illegal\n:description: It shall be illegal for the `resetall directive to be specified within a design element.\n:should_fail_because: It shall be illegal for the `resetall directive to be specified within a design element.\n:tags: 22.3\n:type: preprocessing parsing\n*/\n`resetall\nmodule top ();\n`resetall\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.3--resetall_multiple.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.3--resetall_multiple\n:description: Test\n:tags: 22.3\n:type: preprocessing parsing\n*/\n`resetall\n`resetall\n`resetall\n\nmodule top ();\nendmodule\n\n"
  },
  {
    "path": "tests/chapter-22/22.4--check_included_definitions.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.4--check_included_definitions\n:description: Test\n:tags: 22.4\n:type: preprocessing parsing\n*/\n`include \"include_directory/defs.sv\"\nmodule top ();\ninitial begin\n        $display(\":assert:(`TWO_PLUS_TWO == 5)\");\n\t$display(\":assert:('%s' == '%s')\", `define_var, \"define_var\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.4--include_basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.4--include_basic\n:description: Test\n:tags: 22.4\n:type: preprocessing parsing\n*/\n`include \"dummy_include.sv\"\nmodule top ();\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.4--include_basic_rpath.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.4--include_basic_rpath\n:description: Test\n:tags: 22.4\n:type: preprocessing parsing\n*/\n`include \"dummy_include.sv\"\nmodule top ();\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.4--include_from_other_directory.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.4--include_from_other_directory\n:description: Test\n:tags: 22.4\n:type: preprocessing parsing\n*/\n`include \"include_directory/defs.sv\"\nmodule top ();\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.4--include_via_define.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.4--include_via_define\n:description: Though not well documented, real world code does `defines that cause includes\n:tags: 22.4\n:type: preprocessing parsing\n*/\n`define DO_INCLUDE(FN) `include FN\n\n// Check that multiple define references don't throw a multiple `include-on-line error\n`DO_INCLUDE(\"dummy_include.sv\") `DO_INCLUDE(\"dummy_include.sv\")\n\n// Check that ifdefs\n`ifdef NEVER\n `DO_INCLUDE(\"SHOULD_NOT_BE_INCLUDED\")\n`endif\n\nmodule top ();\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.4--include_with_comment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.4--include_with_comment\n:description: Test\n:tags: 22.4\n:type: preprocessing parsing\n*/\n`include \"dummy_include.sv\" // comments after `include are perfectly legal\nmodule top ();\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_1\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define D(x,y) initial $display(\"start\", x , y, \"end\");\nmodule top ();\n`D( \"msg1\" , \"msg2\" )\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_10.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_10\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO1(a=5,b=\"B\",c) initial $display(a,,b,,c);\nmodule top ();\n`MACRO1 ( 1 , , 3 )\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_11.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_11\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO1(a=5,b=\"B\",c) initial $display(a,,b,,c);\nmodule top ();\n`MACRO1 ( , 2, )\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_12.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_12\n:description: Test\n:should_fail_because: If fewer actual arguments are specified than the number of formal arguments and all the remaining formal arguments have defaults, then the defaults are substituted for the additional formal arguments. It shall be an error if any of the remaining formal arguments does not have a default specified.\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO1(a=5,b=\"B\",c) initial $display(a,,b,,c);\nmodule top ();\n`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_13.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_13\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO2(a=5, b, c=\"C\") initial $display(a,,b,,c);\nmodule top ();\n`MACRO2 (1, , 3)\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_14.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_14\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO2(a=5, b, c=\"C\") initial $display(a,,b,,c);\nmodule top ();\n`MACRO2 (, 2, )\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_15.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_15\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO2(a=5, b, c=\"C\") initial $display(a,,b,,c);\nmodule top ();\n`MACRO2 (, 2)\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_16.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_16\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO3(a=5, b=0, c=\"C\") initial $display(a,,b,,c);\nmodule top ();\n`MACRO3 ( 1 )\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_17.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_17\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO3(a=5, b=0, c=\"C\") initial $display(a,,b,,c);\nmodule top ();\n`MACRO3 ( )\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_18.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_18\n:description: Test\n:should_fail_because: For a macro with arguments, the parentheses are always required in the macro call, even if all the arguments have defaults. \n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO3(a=5, b=0, c=\"C\") initial $display(a,,b,,c);\nmodule top ();\n`MACRO3\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_19.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_19\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define wordsize 8\nmodule top ();\nlogic [1:`wordsize] data;\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_2\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define D(x,y) initial $display(\"start\", x , y, \"end\");\nmodule top ();\n`D( \" msg1\", )\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_20.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_20\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define var_nand(dly) nand #dly\nmodule top ();\n`var_nand(2) g121 (q21, n10, n11);\n`var_nand(5) g122 (q22, n10, n11); \nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_21.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_21\n:description: Test\n:should_fail_because: text specified for macro text shall not be split across string literals\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define first_half \"start of string\nmodule top ();\ninitial $display(`first_half end of string\");\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_22.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_22\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define max(a,b)((a) > (b) ? (a) : (b))\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_23.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_23\n:description: Test\n:should_fail_because:  All compiler directives shall be considered predefined macro names; it shall be illegal to redefine a compiler directive as a macro name.\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define define \"illegal\"\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_24.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_24\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\nmodule top ();\n`define HI Hello\n`define LO \"`HI, world\"\n`define H(x) \"Hello, x\"\ninitial begin\n\t$display(\"`HI, world\");\n\t$display(`LO);\n\t$display(`H(world));\nend\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_25.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_25\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define msg(x,y) `\"x: `\\`\"y`\\`\"`\"\nmodule top ();\ninitial $display(`msg(left side,right side));\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_26.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_26\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define append(f) f``_master\nmodule top ();\ninitial $display(`append(clock));\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_3\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define D(x,y) initial $display(\"start\", x , y, \"end\");\nmodule top ();\n`D(, \"msg2 \")\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_4\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define D(x,y) initial $display(\"start\", x , y, \"end\");\nmodule top ();\n`D(,)\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_5\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define D(x,y) initial $display(\"start\", x , y, \"end\");\nmodule top ();\n`D(  ,  )\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_6.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_6\n:description: Test\n:should_fail_because: If fewer actual arguments are specified than the number of formal arguments and all the remaining formal arguments have defaults, then the defaults are substituted for the additional formal arguments. It shall be an error if any of the remaining formal arguments does not have a default specified.\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define D(x,y) initial $display(\"start\", x , y, \"end\");\nmodule top ();\n`D(\"msg1\")\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_7.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_7\n:description: Test\n:should_fail_because: To use a macro defined with arguments, the name of the text macro shall be followed by a list of actual arguments in parentheses, separated by commas.\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define D(x,y) initial $display(\"start\", x , y, \"end\");\n`D()\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_8.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_8\n:description: Test\n:should_fail_because: It shall be an error to specify more actual arguments than the number of formal arguments.\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define D(x,y) initial $display(\"start\", x , y, \"end\");\n`D(,,)\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define-expansion_9.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_expansion_9\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define MACRO1(a=5,b=\"B\",c) initial $display(a,,b,,c);\nmodule top ();\n`MACRO1 ( , 2, 3 )\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define FOUR 5\n`define SOMESTRING \"somestring\"\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--define_and_resetall.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--define_and_resetall\n:description: The text macro facility is not affected by the compiler directive `resetall\n:tags: 22.5.1\n:type: simulation elaboration preprocessing\n*/\n`define SOMESTRING \"somestring\"\n`resetall\n\nmodule top ();\ninitial begin\n       \t$display(\":assert:('%s' == '%s')\", `SOMESTRING, \"somestring\");\nend\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.5.1--include-define-expansion.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.1--include-define-expansion\n:description: Test\n:tags: 22.5.1\n:type: preprocessing\n*/\n`define foo(the_file) `\"the_file`\"\n`include `foo(dummy_include.sv)\n"
  },
  {
    "path": "tests/chapter-22/22.5.2--undef-basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.2--undef-basic\n:description: Test\n:tags: 22.5.2\n:type: preprocessing\n*/\n`define FOO \"foo\"\n`undef FOO\n"
  },
  {
    "path": "tests/chapter-22/22.5.2--undef-nonexisting.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.2--undef-nonexisting\n:description: Test\n:tags: 22.5.2\n:type: preprocessing\n*/\n`undef FOO\n`undef BAR\n"
  },
  {
    "path": "tests/chapter-22/22.5.3--undefineall-and-redefine.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.3--undefineall-and-redefine\n:description: Test\n:tags: 22.5.3\n:type: preprocessing\n*/\n`define FOO \"foo\"\n`undefineall\n`define FOO 5\n`undefineall\n`define FOO(x,y) (x + y)\n"
  },
  {
    "path": "tests/chapter-22/22.5.3--undefineall-basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.5.3--undefineall-basic\n:description: Test\n:tags: 22.5.3\n:type: preprocessing\n*/\n`undefineall\n"
  },
  {
    "path": "tests/chapter-22/22.6--ifdef-behavioral.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.6--ifdef-behavioral\n:description: Test\n:tags: 22.6\n:type: preprocessing\n*/\nmodule and_op (a, b, c);\n\toutput a;\n\tinput b, c;\n\t`ifdef behavioral\n\t\twire a = b & c;\n\t`else\n\t\tand a1 (a,b,c);\n\t`endif\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.6--ifdef-chained-nested.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.6--ifdef-chained-nested\n:description: Test\n:tags: 22.6\n:type: preprocessing\n*/\nmodule test;\n`ifdef first_block\n\t`ifndef second_nest\n\t\tinitial $display(\"first_block is defined\");\n\t`else\n\t\tinitial $display(\"first_block and second_nest defined\");\n\t`endif\n`elsif second_block\n\tinitial $display(\"second_block defined, first_block is not\");\n`else\n\t`ifndef last_result\n\t\tinitial $display(\"first_block, second_block,\", \" last_result not defined.\");\n\t`elsif real_last\n\t\tinitial $display(\"first_block, second_block not defined,\", \" last_result and real_last defined.\");\n\t`else\n\t\tinitial $display(\"Only last_result defined!\");\n\t`endif\n`endif\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.6--ifdef-nested.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.6--ifdef-nested\n:description: Test\n:tags: 22.6\n:type: preprocessing\n*/\nmodule test(out);\noutput out;\n`define wow\n`define nest_one\n`define second_nest\n`define nest_two\n`ifdef wow\n\tinitial $display(\"wow is defined\");\n\t`ifdef nest_one\n\t\tinitial $display(\"nest_one is defined\");\n\t\t`ifdef nest_two\n\t\t\tinitial $display(\"nest_two is defined\");\n\t\t`else\n\t\t\tinitial $display(\"nest_two is not defined\");\n\t\t`endif\n\t`else\n\t\tinitial $display(\"nest_one is not defined\");\n\t`endif\n`else\n\tinitial $display(\"wow is not defined\");\n\t`ifdef second_nest\n\t\tinitial $display(\"second_nest is defined\");\n\t`else\n\t\tinitial $display(\"second_nest is not defined\");\n\t`endif\n`endif\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.7--timescale-basic-1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.7--timescale-basic-1\n:description: Test\n:tags: 22.7\n:type: preprocessing\n*/\n`timescale 1 ns / 1 ps\n"
  },
  {
    "path": "tests/chapter-22/22.7--timescale-basic-2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.7--timescale-basic-2\n:description: Test\n:tags: 22.7\n:type: preprocessing\n*/\n`timescale 10 us / 100 ns\n"
  },
  {
    "path": "tests/chapter-22/22.7--timescale-basic-3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.7--timescale-basic-3\n:description: Test\n:should_fail_because: The integers in `timescale arguments specify an order of magnitude for the size of the value; the valid integers are 1, 10, and 100\n:tags: 22.7\n:type: simulation elaboration\n*/\n`timescale 9 ns / 1 ps\n"
  },
  {
    "path": "tests/chapter-22/22.7--timescale-basic-4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.7--timescale-basic-4\n:description: Test\n:should_fail_because: The time_precision argument shall be at least as precise as the time_unit argument; it cannot specify a longerunit of time than time_unit.\n:tags: 22.7\n:type: simulation elaboration\n*/\n`timescale 1 ns / 10 ns\n"
  },
  {
    "path": "tests/chapter-22/22.7--timescale-module.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.7--timescale-module\n:description: Test\n:tags: 22.7\n:type: preprocessing\n:unsynthesizable: 1\n*/\n`timescale 10 ns / 1 ns\nmodule test;\n\tlogic set;\n\tparameter d = 1.55;\n\tinitial begin\n\t\t#d set = 0;\n\t\t#d set = 1;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-22/22.7--timescale-reset.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.7--timescale-reset\n:description: Test\n:tags: 22.7\n:type: preprocessing\n*/\n`timescale 1 ns / 1 ps\n`resetall\n`timescale 10 us / 100 ns\n"
  },
  {
    "path": "tests/chapter-22/22.8--default_nettype-redefinition.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.8--default_nettype-redefinition\n:description: Test\n:tags: 22.8\n:type: preprocessing\n*/\n`default_nettype wire\n`default_nettype tri\n`default_nettype tri0\n`default_nettype tri1\n`default_nettype wand\n`default_nettype triand\n`default_nettype wor\n`default_nettype trior\n`default_nettype trireg\n`default_nettype uwire\n`default_nettype none\n"
  },
  {
    "path": "tests/chapter-22/22.8--default_nettype.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.8--default_nettype\n:description: Test\n:tags: 22.8\n:type: preprocessing\n*/\n`default_nettype wire\n"
  },
  {
    "path": "tests/chapter-22/22.9--unconnected_drive-basic-2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.9--unconnected_drive-basic-2\n:description: Test\n:tags: 22.9\n:type: preprocessing\n*/\n`unconnected_drive pull1\n"
  },
  {
    "path": "tests/chapter-22/22.9--unconnected_drive-basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.9--unconnected_drive-basic\n:description: Test\n:tags: 22.9\n:type: preprocessing\n*/\n`unconnected_drive pull1\n`nounconnected_drive\n"
  },
  {
    "path": "tests/chapter-22/22.9--unconnected_drive-invalid-1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.9--unconnected_drive-invalid-1\n:description: Test\n:should_fail_because: The directive `unconnected_drive takes one of two arguments - pull1 or pull0.\n:tags: 22.9\n:type: simulation elaboration\n*/\n`unconnected_drive\n`nounconnected_drive\n"
  },
  {
    "path": "tests/chapter-22/22.9--unconnected_drive-invalid-2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.9--unconnected_drive-invalid-2\n:description: Test unconnected drive macro with argument other than pull0 and pull1\n:should_fail_because: The directive `unconnected_drive takes one of two arguments - pull1 or pull0 \n:tags: 22.9\n:type: simulation elaboration\n*/\n`unconnected_drive pull2\n`nounconnected_drive\n"
  },
  {
    "path": "tests/chapter-22/22.9--unconnected_drive-invalid-3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: 22.9--unconnected_drive-invalid-3\n:description: Test\n:should_fail_because: use a strength keyword with `nounconnected_drive macro\n:tags: 22.9\n:type: simulation elaboration\n*/\n`unconnected_drive pull0 \n`nounconnected_drive pull0\n"
  },
  {
    "path": "tests/chapter-22/dummy_include.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dummy_include\n:description: Utility for testing `include directive\n:type: preprocessing\n:tags: 22.4\n*/\n"
  },
  {
    "path": "tests/chapter-22/include_directory/defs.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: defs \n:description: Utility for testing `include directive\n:type: preprocessing\n:tags: 22.4\n*/\n\n`define define_var \"define_var\"\n`define TWO_PLUS_TWO 5\n"
  },
  {
    "path": "tests/chapter-23/23.2--macromodule-definition.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: macromodule_definition\n:description: macromodule definition test\n:tags: 23.2\n*/\nmacromodule top();\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-23/23.2--module-definition.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: module_definition\n:description: module definition test\n:tags: 23.2\n*/\nmodule top();\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-23/23.2--module-label.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: module_definition\n:description: module w/ named end test\n:tags: 23.2\n:type: simulation elaboration parsing\n*/\nmodule top();\n\nendmodule : top\n"
  },
  {
    "path": "tests/chapter-24/24.3--program.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: program_construct\n:description: program construct test\n:tags: 24.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nprogram prog(input wire a, input wire b);\n\tinitial $display(\":assert: (%d == %d)\", a, b);\nendprogram\n\nmodule top();\n\n   wire a = 1;\n   wire b = 1;\n\n   prog p(a, b);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-25/25.3-interface.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: interface\n:description: interface test\n:tags: 25.3\n:top_module: top\n*/\n\ninterface test_bus;\n  logic test_pad;\nendinterface: test_bus\n\nmodule sub(test_bus iface);\nendmodule\n\nmodule top;\n   test_bus iface();\n   sub sub (.iface);\nendmodule\n"
  },
  {
    "path": "tests/chapter-26/26.2--package-decl.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: package_decl\n:description: package declaration test\n:tags: 26.2\n*/\nmodule top();\n\nendmodule\n\npackage mypkg;\n\nfunction int add(int a, b);\n\treturn a + b;\nendfunction\n\nendpackage : mypkg\n"
  },
  {
    "path": "tests/chapter-26/26.3--package-ref.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: package_ref\n:description: package reference test\n:tags: 26.3\n:type: simulation elaboration parsing\n*/\n\npackage mypkg;\n\nfunction int add(int a, b);\n\treturn a + b;\nendfunction\n\nendpackage : mypkg\n\nmodule top();\n\ninitial $display(\":assert: (%d == 4)\", mypkg::add(1, 3));\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.10-structure-arrays-illegal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: structure-arrays-illegal\n:description: Structure array assignment tests\n:should_fail_because: C-like assignment is illegal\n:tags: 5.10\n:type: simulation elaboration\n*/\nmodule top();\n  typedef struct {\n    int a;\n    int b;\n  } ms_t;\n\n  /* C-like assignment is illegal */\n  ms_t ms[1:0] = '{0, 0, 1, 1};\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.10-structure-arrays.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: structure-arrays\n:description: Structure array assignment tests\n:tags: 5.10\n*/\nmodule top();\n  typedef struct {\n    int a;\n    int b;\n  } ms_t;\n\n  ms_t ms[1:0] = '{'{0, 0}, '{1, 1}};\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.10-structure-replication.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: structure-replication\n:description: Structure replication assignment tests\n:tags: 5.10\n*/\nmodule top();\n  struct {int X,Y,Z;} XYZ = '{3{1}};\n  typedef struct {int a,b[4];} ab_t;\n  int a,b,c;\n\n  initial begin\n    ab_t v1[1:0] [2:0];\n    v1 = '{2{'{3{'{a,'{2{b,c}}}}}}};\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.10-structures.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: structure\n:description: Structure assignment tests\n:tags: 5.10\n*/\nmodule top();\n  typedef struct {\n    int a;\n    int b;\n  } ms_t;\n\n  ms_t ms;\n\n  initial begin\n    ms = '{ 0, 1};\n\n    ms = '{ default:1, int:1};\n\n    ms = '{ int:0, int:1};\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.11-arrays-key-index.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-key-index\n:description: Basic arrays test\n:tags: 5.11\n*/\nmodule top();\n  typedef int triple [1:3];\n  triple b = '{1:1, default:0};\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.11-arrays-replication.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-replication\n:description: Basic arrays test\n:tags: 5.11\n*/\nmodule top();\n  int n[1:2][1:6] = '{2{'{3{4, 5}}}};\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.11-arrays.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays\n:description: Basic arrays test\n:tags: 5.11\n*/\nmodule top();\n  int n[1:2][1:3] = '{'{0,1,2},'{3{4}}};\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.12-attributes-case.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: attributes-case\n:description: Assing attributes to a case statement\n:tags: 5.12\n*/\n\nmodule top();\n  reg [1:0] a;\n\n  bit b;\n\n  initial begin\n\n    (* full_case, parallel_case *)\n    case (a)\n      2'b00 :\n        b = 0;\n      2'b01, 2'b10 :\n        b = 1;\n      default :\n        b = 0;\n    endcase\n\n    (* full_case = 1 *)\n    (* parallel_case = 1 *)\n    case (a)\n      2'b00 :\n        b = 0;\n      2'b01, 2'b10 :\n        b = 1;\n      default :\n        b = 0;\n    endcase\n\n    (* full_case, parallel_case = 0 *)\n    case (a)\n      2'b00 :\n        b = 0;\n      2'b01, 2'b10 :\n        b = 1;\n      default :\n        b = 0;\n    endcase\n\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.12-attributes-conditional.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: attributes-conditional\n:description: Assing attributes to a conditional operator\n:tags: 5.12\n*/\n\nmodule top();\n  bit a, b, c, d;\n\n  initial begin\n    a = b ? (* no_glitch *) c : d;\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.12-attributes-module.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: attributes-module\n:description: Assing attributes to a module\n:tags: 5.12\n*/\n\n(* optimize_power *)\nmodule topa();\nendmodule\n\n(* optimize_power=0 *)\nmodule topb();\nendmodule\n\n(* optimize_power=1 *)\nmodule topc();\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.12-attributes-operator.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: attributes-operator\n:description: Assing attributes to an operator\n:tags: 5.12\n*/\n\nmodule top();\n  logic [7:0] a;\n  logic [7:0] b;\n  logic [7:0] c;\n\n  initial begin\n    a = b + (* mode = \"cla\" *) c;\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.12-attributes-variable.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: attributes-variable\n:description: Assing attributes to a variable\n:tags: 5.12\n*/\n\nmodule top();\n  (* fsm_state *)   logic [7:0] a;\n  (* fsm_state=1 *) logic [7:0] b;\n  (* fsm_state=0 *) logic [7:0] c;\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.13-builtin-methods-strings.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: builtin-methods-string\n:description: Check if built-in methods can be called\n:tags: 5.13\n*/\nmodule top();\n  string a = \"test\";\n\n  initial begin\n    $display(\"length check: %d\\n\", a.len());\n  end\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.4--coments.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: comments\n:description: A module testing system verilog comments\n:tags: 5.4\n*/\nmodule empty (\n);\n  /* multi\n     line\n     comment\n   */\n\n  // single line comment\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6--identifiers.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: identifiers\n:description: Identifiers that should be accepted\n:tags: 5.6\n*/\nmodule identifiers();\n  reg shiftreg_a;\n  reg busa_index;\n  reg error_condition;\n  reg merge_ab;\n  reg _bus3;\n  reg n$657;\n\n  /* Should also be case sensitive,\n   * should not cause a conflict here\n   */\n  reg sensitive;\n  reg Sensitive;\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6--wrong-identifiers.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: wrong-identifiers\n:description: Identifiers that should not be accepted\n:should_fail_because: The first character of a simple identifier shall not be a digit or $\n:tags: 5.6\n*/\nmodule identifiers();\n  reg $dollar;\n  reg 0number;\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.1--escaped-identifiers.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: escaped-identifiers\n:description: Escaped identifiers that should be accepted\n:tags: 5.6.1\n*/\nmodule identifiers();\n\n  reg \\busa+index ;\n  reg \\-clock ;\n  reg \\***error-condition*** ;\n  reg \\net1/\\net2 ;\n  reg \\{a,b} ;\n  reg \\a*(b+c) ;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.1--nonescaped-access.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: nonescaped-access\n:description: Escaped identifiers can be referenced by nonescaped name\n:tags: 5.6.1\n*/\n`default_nettype none\nmodule identifiers();\n\n  reg \\cpu3 ;\n  wire reference_test;\n\n  assign reference_test = cpu3;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.3--system-functions.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: system-functions\n:description: Calling system functions\n:tags: 5.6.3\n*/\nmodule systemfn();\n  /* Note:\n   * This does not test all the individual system calls.\n   * It just verifies if the concept exists using one of the\n   * calls.\n   */\n\n  initial $display(\"hello world\");\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-begin-keywords.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: begin-keywords\n:description: Begin keywords check\n:tags: 5.6.4\n*/\n\n`begin_keywords \"1364-2001\" // use IEEE Std 1364-2001 Verilog keywords\nmodule b_kw();\n  reg logic; // OK: \"logic\" is not a keyword in 1364-2001\nendmodule\n`end_keywords\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-celldefine.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: celldefine\n:description: Celldefine check\n:tags: 5.6.4\n*/\n\n`celldefine\nmodule cd();\nendmodule\n`endcelldefine\n\nmodule ncd();\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-debug-line.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: debug-line\n:description: Debugging compiler directives\n:tags: 5.6.4\n*/\n\nmodule directives();\n  `line 1 \"5.6.4--compiler-directives-debug-line.sv\" 1\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-debug.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: debug-directives\n:description: Debugging compiler directives\n:tags: 5.6.4\n*/\n\nmodule directives();\n  initial $display(\"At %s @ %d\\n\", `__FILE__, `__LINE__);\nendmodule;\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-default-nettype.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: default-nettype\n:description: Default nettype check\n:tags: 5.6.4\n*/\n\n`default_nettype wire\n`default_nettype none\nmodule dn();\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-define.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: define-directive\n:description: Define and undef checks\n:tags: 5.6.4\n*/\n\n`define XXX 1\n\n`ifdef XXX\n`undef XXX\n`elsif YYY \n`define XXX 0\n`endif\n\n`ifndef YYY\n`define YYY 0\n`else\n`define XXX 0\n`endif\n\n`undefineall\n\nmodule d();\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-include.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: include-directive\n:description: Include empty file\n:tags: 5.6.4\n*/\n\n`include \"/dev/null\"\n\nmodule empty();\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-pragma.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pragma-directive\n:description: Try to set a pragma\n:tags: 5.6.4\n*/\n\nmodule ts();\n`pragma protect\n  wire protected_wire;\n`pragma protect end\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-preprocessor-macro_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: compiler_directives_preprocessor_macro_0\n:description: Read preprocessing macro from template (:defines: marker)\n:tags: 5.6.4\n:type: preprocessing\n:defines: TEST_VAR\n*/\n\n`ifdef TEST_VAR\n`else\nTEST_VAR parsed not correctly from template\n`endif\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: compiler_directives_preprocessor_macro_1\n:description: Read preprocessing macro from template (:defines: marker)\n:tags: 5.6.4\n:defines: VAR_1=2 VAR_2=5\n*/\n\nmodule top();\nint a = `VAR_1 + `VAR_2;\n\ninitial begin\n    if (a == 7)\n\t$display(\":assert:(True)\");\n    else\n\t$display(\":assert:(False)\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-resetall.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: resetall-directive\n:description: Check for the resetall directive\n:tags: 5.6.4\n*/\n\n`resetall\n\nmodule ts();\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-timescale.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: timescale-directive\n:description: Set timescale\n:tags: 5.6.4\n*/\n\n`timescale 1 ns / 1 ps\n\nmodule ts();\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.6.4--compiler-directives-unconnected-drive.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unconnected-drive\n:description: Unconnected drive keywords\n:tags: 5.6.4\n:type: preprocessing\n*/\n\n\n`unconnected_drive pull1\n\nmodule ts();\nendmodule\n\n`nounconnected_drive\n"
  },
  {
    "path": "tests/chapter-5/5.7.1--integers-left-padding-bit.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: integers-left-padding-bit\n:description: Automatic left padding of literal numbers using single-bit value\n:tags: 5.7.1\n*/\nmodule top();\n  logic [15:0] a, b, c, d;\n\n  initial begin\n    a = '0; // sets all 16 bits to 0\n    b = '1; // sets all 16 bits to 1\n    c = 'x; // sets all 16 bits to x\n    d = 'z; // sets all 16 bits to z\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.1--integers-left-padding.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: integers-left-padding\n:description: Automatic left padding of literal constant numbers\n:tags: 5.7.1\n*/\nmodule top();\n  logic [11:0] a, b, c, d;\n  logic [84:0] e, f, g;\n\n  initial begin\n    a = 'h x;   // yields xxx\n    b = 'h 3x;  // yields 03x\n    c = 'h z3;  // yields zz3\n    d = 'h 0z3; // yields 0z3\n    e = 'h5;    // yields {82{1'b0},3'b101}\n    f = 'hx;    // yields {85{1'hx}}\n    g = 'hz;    // yields {85{1'hz}}\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.1--integers-signed-illegal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: integers-sized-illegal\n:description: Integer literal constants\n:should_fail_because: illegal negative decimal syntax, proper one is -8'd6\n:tags: 5.7.1\n*/\nmodule top();\n  logic  [7:0] a;\n\n  initial begin\n    a = 8'd-6;\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.1--integers-signed.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: integers-signed\n:description: Integer literal constants\n:tags: 5.7.1\n*/\nmodule top();\n  logic  [7:0] a;\n  logic  [3:0] b;\n  logic  [3:0] c;\n  logic [15:0] d;\n\n  initial begin\n    a = -8'd 6;  // this defines the two's-complement of 6,\n                 // held in 8 bits—equivalent to -(8'd 6)\n    b = 4'shf;   // this denotes the 4-bit number '1111', to\n                 // be interpreted as a two's-complement number,\n                 // or '-1'. This is equivalent to -4'h 1\n    c = -4'sd15; // this is equivalent to -(-4'd 1), or '0001'\n    d = 16'sd?;  // the same as 16'sbz\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.1--integers-sized.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: integers-sized\n:description: Integer literal constants\n:tags: 5.7.1\n*/\nmodule top();\n  logic  [3:0] a;\n  logic  [4:0] b;\n  logic [ 2:0] c;\n  logic [11:0] d;\n  logic [15:0] e;\n\n  initial begin\n    a = 4'b1001; // is a 4-bit binary number\n    b = 5'D3;    // is a 5-bit decimal number\n    c = 3'b01x;  // is a 3-bit number with the least\n                 // significant bit unknown\n    d = 12'hx;   // is a 12-bit unknown number\n    e = 16'hz;   // is a 16-bit high-impedance number\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.1--integers-token.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: integers-token\n:description: Testing the integer variable type\n:tags: 5.7.1\n*/\nmodule top();\n  integer a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.1--integers-underscores.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: integers-underscores\n:description: Automatic left padding of literal numbers using single-bit value\n:tags: 5.7.1\n*/\nmodule top();\n  logic [31:0] a;\n  logic [15:0] b;\n  logic [31:0] c;\n\n  initial begin\n    a = 27_195_000;              // unsized decimal 27195000\n    b = 16'b0011_0101_0001_1111; // 16-bit binary number\n    c = 32 'h 12ab_f001;         // 32-bit hexadecimal number\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.1--integers-unsized-illegal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: integers-unsized-illegal\n:description: Integer literal constants\n:should_fail_because: hexadecimal format requires 'h\n:tags: 5.7.1\n*/\nmodule top();\n  logic [31:0] a;\n\n  initial begin\n    a = 4af; // is illegal (hexadecimal format requires 'h)\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.1--integers-unsized.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: integers-unsized\n:description: Integer literal constantsa\n:tags: 5.7.1\n*/\nmodule top();\n  logic [31:0] a;\n\n  initial begin\n    a = 659;      // is a decimal number\n    a = 'h 837FF; // is a hexadecimal number\n    a = 'o7460;   // is an octal number\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.2-real-constants-illegal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: real-constants-illegal\n:description: Examples of real literal constants\n:should_fail_because: Real literal constants must have at least one digit on each side of the decimal point\n:tags: 5.7.2\n*/\nmodule top();\n  logic [31:0] a;\n\n  initial begin\n    a = .12;\n    a = 9.;\n    a = 4.E3;\n    a = .2e-7;\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.2-real-constants.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: real-constants\n:description: Examples of real literal constants\n:tags: 5.7.2\n*/\nmodule top();\n  logic [31:0] a;\n\n  initial begin\n    a = 1.2;\n    a = 0.1;\n    a = 2394.26331;\n    a = 1.2E12;           // the exponent symbol can be e or E\n    a = 1.30e-2;\n    a = 0.1e-0;\n    a = 23E10;\n    a = 29E-2;\n    a = 236.123_763_e-12; // underscores are ignored\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.7.2-real-token.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: real-token\n:description: Testing the real variable type\n:tags: 5.7.2\n:unsynthesizable: 1\n*/\nmodule top();\n  real a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.8-time-literals.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: time-literals\n:description: Examples of time literals\n:tags: 5.8\n:unsynthesizable: 1\n*/\n\n`timescale 100ps/10ps\n\nmodule top();\n  time a;\n\n  initial begin\n    a = 1fs;\n    a = 1ps;\n    a = 1ns;\n    a = 1us;\n    a = 1ms;\n    a = 1s;\n\n    /* real */\n    a = 2.1ms;\n\n  end;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.9-string-assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string-assignment\n:description: String assignment tests\n:tags: 5.9\n*/\nmodule top();\n  byte        a;\n  bit   [7:0] b;\n  logic [7:0] c;\n\n  initial begin\n    a = \"a\";\n    b = \"b\";\n    c = \"c\";\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.9-string-basics.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string-basic\n:description: Basic string example\n:tags: 5.9 5.3\n*/\nmodule top();\n\n  initial begin\n    $display(\"one line\");\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.9-string-broken-line.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string-broken-line\n:description: Basic broken line string example\n:tags: 5.9\n*/\nmodule top();\n\n  initial begin\n    $display(\"broken \\\n              line\");\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.9-string-word-assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string-word-assignment\n:description: String assignment tests\n:tags: 5.9\n*/\nmodule top();\n  bit [8 * 3 - 1 : 0] a = \"hi0\";\n  // Note as of January 2020 several commercial simulators do not support unpacked byte\n  // assignment from strings:\n  byte      b[3 : 0] = \"hi2\";\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-5/5.9.1-string-special-chars.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string-special-chars\n:description: Special characters in strings\n:tags: 5.9.1\n*/\nmodule top();\n\n  initial begin\n    $display(\"newline \\n\");\n    $display(\"tab \\t\");\n    $display(\"backslash \\\\\");\n    $display(\"quote \\\"\");\n    $display(\"vertical tab \\v\");\n    $display(\"form feed \\f\");\n    $display(\"bell \\a\");\n    $display(\"octal \\123\");\n    $display(\"hex \\x12\");\n  end\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.10--implicit_continuous_assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implicit_continuous_assignment\n:description: implicit declaration in continuous assignment tests\n:tags: 6.10\n*/\nmodule top();\n\twire [3:0] a = 8;\n\twire [3:0] b = 5;\n\n\tassign c = | (a | b);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.10--implicit_port.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implicit_port\n:description: implicit port signal tests\n:tags: 6.10\n*/\nmodule top(input [3:0] a, input [3:0] b);\n\twire [3:0] c;\n\tassign c = a | b;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.10--implicit_port_connection.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implicit_port_connection\n:description: implicit port connection tests\n:tags: 6.10\n*/\nmodule top();\n\twire a = 1;\n\twire b = 0;\n\twire d;\n\n\ttest mod(a, b, c);\n\n\tassign d = c;\nendmodule\n\nmodule test(input a, input b, output c);\n\tassign c = a | b;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.12--real.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: real\n:description: real type tests\n:tags: 6.12\n:unsynthesizable: 1\n*/\nmodule top();\n\treal a = 0.5;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.12--real_bit_select.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: real_idx\n:description: real indexing tests\n:should_fail_because: it is illegal to do bit select on real data type\n:tags: 6.12\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule top();\n\treal a = 0.5;\n\twire b;\n\n\tassign b = a[2];\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.12--real_bit_select_idx.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: real_bit_select\n:description: real bit select tests\n:should_fail_because: it is illegal to do bit select on real data type\n:tags: 6.12\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule top();\n\treal a = 0.5;\n\twire [3:0] b;\n\twire c;\n\n\tassign c = b[a];\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.12--real_edge.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: real_edge\n:description: real edge event tests\n:should_fail_because: it is illegal to use edge event controls on real type\n:tags: 6.12\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule top();\n\treal a = 0.5;\n\talways @(posedge a)\n\t\t$display(\"posedge\");\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.12--realtime.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: realtime\n:description: realtime type tests\n:tags: 6.12\n:unsynthesizable: 1\n*/\nmodule top();\n\trealtime a = 0.5;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.12--shortreal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: shortreal\n:description: shortreal type tests\n:tags: 6.12\n:unsynthesizable: 1\n*/\nmodule top();\n\tshortreal a = 0.5;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.13--void.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: void\n:description: void type tests\n:tags: 6.13\n:type: simulation elaboration parsing\n*/\nmodule top();\n\tfunction void fun();\n\t\t$display(\":assert:(True)\");\n\tendfunction\n\n\tinitial\n\t\tfun();\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.14--chandle.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: chandle\n:description: chandle type tests\n:tags: 6.14\n:unsynthesizable: 1\n*/\nmodule top();\n\tchandle a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16--string.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string\n:description: string type tests\n:tags: 6.16\n*/\nmodule top();\n\tstring a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.1--string_len.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_len\n:description: string.len()  tests\n:tags: 6.16.1\n*/\nmodule top();\n\tstring a = \"Test\";\n\tint b = a.len();\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.10--string_atoreal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_atoreal\n:description: string.atoreal()  tests\n:tags: 6.16.10\n:unsynthesizable: 1\n*/\nmodule top();\n\tstring a = \"4.76\";\n\treal b = a.atoreal();\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.11--string_itoa.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_itoa\n:description: string.itoa()  tests\n:tags: 6.16.11\n*/\nmodule top();\n\tstring a;\n\tinitial\n\t\ta.itoa(12);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.12--string_hextoa.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_hextoa\n:description: string.hextoa()  tests\n:tags: 6.16.12\n*/\nmodule top();\n\tstring a;\n\tinitial\n\t\ta.hextoa(12);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.13--string_octtoa.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_octtoa\n:description: string.octtoa()  tests\n:tags: 6.16.13\n*/\nmodule top();\n\tstring a;\n\tinitial\n\t\ta.octtoa(12);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.14--string_bintoa.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_bintoa\n:description: string.bintoa()  tests\n:tags: 6.16.14\n*/\nmodule top();\n\tstring a;\n\tinitial\n\t\ta.bintoa(12);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.15--string_realtoa.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_realtoa\n:description: string.realtoa()  tests\n:tags: 6.16.15\n*/\nmodule top();\n\tstring a;\n\tinitial\n\t\ta.realtoa(4.76);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.2--string_putc.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_putc\n:description: string.putc()  tests\n:tags: 6.16.2\n*/\nmodule top();\n\tstring a = \"Test\";\n\tinitial\n\t\ta.putc(2, \"B\");\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.3--string_getc.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_getc\n:description: string.getc()  tests\n:tags: 6.16.3\n*/\nmodule top();\n\tstring a = \"Test\";\n\tbyte b = a.getc(2);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.4--string_toupper.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_toupper\n:description: string.toupper()  tests\n:tags: 6.16.4\n*/\nmodule top();\n\tstring a = \"Test\";\n\tstring b = a.toupper();\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.5--string_tolower.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_tolower\n:description: string.tolower()  tests\n:tags: 6.16.5\n*/\nmodule top();\n\tstring a = \"Test\";\n\tstring b = a.tolower();\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.6--string_compare.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_compare_fn\n:description: string.compare()  tests\n:tags: 6.16.6\n*/\nmodule top();\n\tstring a = \"Test\";\n\tstring b = \"TEST\";\n\tint c = a.compare(b);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.7--string_icompare.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_icompare\n:description: string.icompare()  tests\n:tags: 6.16.7\n*/\nmodule top();\n\tstring a = \"Test\";\n\tstring b = \"TEST\";\n\tint c = a.icompare(b);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.8--string_substr.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_substr\n:description: string.substr()  tests\n:tags: 6.16.8\n*/\nmodule top();\n\tstring a = \"Test\";\n\tstring b = a.substr(1, 2);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.9--string_atobin.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_atobin\n:description: string.atobin()  tests\n:tags: 6.16.9\n*/\nmodule top();\n\tstring a = \"10101\";\n\tint b = a.atobin();\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.9--string_atohex.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_atohex\n:description: string.atohex()  tests\n:tags: 6.16.9\n*/\nmodule top();\n\tstring a = \"0xff\";\n\tint b = a.atohex();\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.9--string_atoi.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_atoi\n:description: string.atoi()  tests\n:tags: 6.16.9\n*/\nmodule top();\n\tstring a = \"1234\";\n\tint b = a.atoi();\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.16.9--string_atooct.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: string_atooct\n:description: string.atooct()  tests\n:tags: 6.16.9\n*/\nmodule top();\n\tstring a = \"777\";\n\tint b = a.atooct();\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.17--event.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event\n:description: event type tests\n:tags: 6.17\n:unsynthesizable: 1\n*/\nmodule top();\n\tevent a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.18--typedef.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef\n:description: user types tests\n:tags: 6.18\n*/\nmodule top();\n\ttypedef logic logic_t;\n\n\tlogic_t a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19--enum_anon.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_anon\n:description: anonymous enum tests\n:tags: 6.19\n*/\nmodule top();\n\tenum {a, b, c} val;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19--enum_value_inv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_value_inv\n:description: Tests that tools diagnose invalid enum value assignments\n:should_fail_because: If the integer value expression is a sized literal constant, it shall be an error if the size is different from the enum base type, even if the value is within the representable range.\n:tags: 6.19\n:runner_verilator_flags: -Werror-WIDTH\n:type: simulation elaboration\n*/\nmodule top();\n\t// 6.19 says:\n\t// If the integer value expression is a sized literal constant, it shall\n\t// be an error if the size is different from the enum base type, even if\n\t// the value is within the representable range.\n\tenum logic [2:0] {\n\t  Global = 4'h2,\n\t  Local = 4'h3\n\t} myenum;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19--enum_xx.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_xx\n:description: enum with x tests\n:tags: 6.19\n*/\nmodule top();\n\tenum integer {a=0, b={32{1'bx}}, c=1} val;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19--enum_xx_inv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_xx_inv\n:description: invalid enum with x tests\n:should_fail_because: An enumerated name with x or z assignments assigned to an enum with no explicit data type or an explicit2-state declaration shall be a syntax error\n:tags: 6.19\n:type: simulation elaboration\n*/\nmodule top();\n\tenum bit [1:0] {a=0, b=2'bxx, c=1} val;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19--enum_xx_inv_order.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_xx_inv_order\n:description: unassigned name following enum with x tests\n:should_fail_because: An unassigned enumerated name that follows an enum name with x or z assignments shall be a syntax error.\n:tags: 6.19\n:type: simulation elaboration\n*/\nmodule top();\n\tenum integer {a=0, b={32{1'bx}}, c} val;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.1--enum_typedef.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_typedef\n:description: typedef enum tests\n:tags: 6.19.1\n*/\nmodule top();\n\ttypedef enum {a, b, c} e;\n\te val;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.2--enum_sequence.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_sequence\n:description: enum sequence tests\n:tags: 6.19.2\n*/\nmodule top();\n\tenum {start=10, step[10]} e;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.2--enum_sequence_range.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_sequence_range\n:description: enum sequence range tests\n:tags: 6.19.2\n*/\nmodule top();\n\tenum {start=10, stop[11:13]} e;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.3--enum_type_checking.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_type_checking\n:description: enum type checking tests\n:tags: 6.19.3\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val;\n\t\tval = a;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.3--enum_type_checking_inv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_type_checking_inv\n:description: invalid enum assignment tests\n:should_fail_because: enum enforces strict type checking rules\n:tags: 6.19.3\n:type: simulation elaboration\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val;\n\t\tval = 1;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.4--enum_numerical_expr.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_numerical_expr\n:description: enum numerical expression tests\n:tags: 6.19.4\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\tinteger i;\n\t\te val;\n\t\tval = a;\n\t\ti = val * 4;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.4--enum_numerical_expr_cast.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_numerical_expr_cast\n:description: enum numerical expression with casting\n:tags: 6.19.4\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val;\n\t\tval = a;\n\t\tval = e'(val+1);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.4--enum_numerical_expr_no_cast.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_numerical_expr_no_cast\n:description: enum numerical expression without casting\n:should_fail_because: enum numerical expression without casting\n:tags: 6.19.4\n:type: simulation elaboration\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val;\n\t\tval = a;\n\t\tval += 1;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.5.1--enum_first.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_first\n:description: enum first method tests\n:tags: 6.19.5.1\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val = a;\n\t\tval = val.first();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.5.2--enum_last.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_last\n:description: enum last method tests\n:tags: 6.19.5.2\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val = a;\n\t\tval = val.last();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.5.3--enum_next.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_next\n:description: enum next method tests\n:tags: 6.19.5.3\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val = a;\n\t\tval = val.next();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.5.4--enum_prev.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_prev\n:description: enum prev method tests\n:tags: 6.19.5.4\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val = b;\n\t\tval = val.prev();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.5.5--enum_num.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_num\n:description: enum num method tests\n:tags: 6.19.5.5\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val = a;\n\t\tint n = val.num();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.19.5.6--enum_name.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: enum_name\n:description: enum name method tests\n:tags: 6.19.5.6\n*/\nmodule top();\n\ttypedef enum {a, b, c, d} e;\n\n\tinitial begin\n\t\te val = a;\n\t\tstring s = val.name();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.2--parameter.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameter\n:description: parameter tests\n:tags: 6.20.2\n*/\nmodule top();\n\tparameter p = 123;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.2--parameter_aggregate.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameter_aggregate\n:description: parameter aggregate type tests\n:tags: 6.20.2\n*/\nmodule top();\n\tparameter logic [31:0] p [3:0] = '{1, 2, 3, 4};\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.2--parameter_dep.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameter_dep\n:description: parameter depending on another parameter tests\n:tags: 6.20.2\n*/\nmodule top();\n\tparameter p1 = 123;\n\tparameter p2 = p1 * 3;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.2--parameter_port_list.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameter_port_list\n:description: parameter port list tests\n:tags: 6.20.2\n*/\nmodule top #(p = 12);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.2--parameter_range.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameter_range\n:description: parameter with implied range tests\n:tags: 6.20.2\n*/\nmodule top();\n\tparameter p = 16'h1234;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.2--parameter_real.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameter_real\n:description: parameter with real value test\n:tags: 6.20.2\n*/\nmodule top();\n\tparameter p = 4.76;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.3--parameter_type.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameter_type\n:description: parameter type tests\n:tags: 6.20.3\n:unsynthesizable: 1\n*/\nmodule top #(type T = real);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.4--localparam.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: localparam\n:description: localparam without type specifier\n:tags: 6.20.4\n*/\nmodule top();\n\tlocalparam p = 123;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.4--localparam_int.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: localparam_int\n:description: localparam integer type\n:tags: 6.20.4\n*/\nmodule top();\n\tlocalparam int p = 123;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.4--localparam_logic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: localparam_logic\n:description: localparam with logic type\n:tags: 6.20.4\n*/\nmodule top();\n\tlocalparam [10:0] p = 1 << 5;\n\tlocalparam logic [10:0] q = 1 << 5;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.4--localparam_string.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: localparam_string\n:description: localparam string typed\n:tags: 6.20.4\n*/\nmodule top();\n\tlocalparam s1 = \"foo\";\n\tlocalparam string s2 = \"bar\";\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.4--localparam_unsigned_int.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: localparam_uint\n:description: localparam unsigned typed\n:tags: 6.20.4\n*/\nmodule top();\n\tlocalparam int unsigned q = 123;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.5--specparam.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: specparam\n:description: specparam tests\n:tags: 6.20.5\n*/\nmodule top();\n\tspecparam delay = 50;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.5--specparam_inv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: specparam_inv\n:description: specparam assignment to param should be invalid\n:should_fail_because: specparam assignment to param should be invalid\n:tags: 6.20.5\n:type: simulation elaboration\n*/\nmodule top();\n\tspecparam delay = 50;\n\tparameter p = delay + 2;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.20.6--const.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: const\n:description: const test\n:tags: 6.20.6\n:unsynthesizable: 1\n*/\nmodule top();\n\tclass test_cls;\n\t\tint a;\n\t\ttask test_method(int val);\n\t\t\t$display(\"test_method\");\n\t\t\ta += val;\n\t\tendtask\n\tendclass\n\n\tconst test_cls test_obj = new;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.23--localparam_type_decl.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: localparam_type_decl\n:description: Declare a type with a localparam\n:tags: 6.23\n*/\nmodule top ;\n\nlocalparam type testtype = logic;\n\ntesttype t;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.23--type_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: type_op\n:description: type operator tests\n:tags: 6.23\n:unsynthesizable: 1\n*/\nmodule top();\n\treal a = 4.76;\n\treal b = 0.74;\n\tvar type(a+b) c;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.23--type_op_compare.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: type_op_compare\n:description: type comparison tests\n:tags: 6.23\n*/\nmodule top #( parameter type T = type(logic[11:0]) )\n   ();\n   initial begin\n      case (type(T))\n        type(logic[11:0]) : ;\n        default           : $stop;\n      endcase\n      if (type(T) == type(logic[12:0])) $stop;\n      if (type(T) != type(logic[11:0])) $stop;\n      if (type(T) === type(logic[12:0])) $stop;\n      if (type(T) !== type(logic[11:0])) $stop;\n      $finish;\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.24.1--cast_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cast_op\n:description: cast operator\n:tags: 6.24.1\n*/\nmodule top();\n\tint a = int'(2.1 * 3.7);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.24.2--cast_fn.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cast_fn\n:description: $cast function\n:tags: 6.24.2\n*/\nmodule top();\n\tint a;\n\tinitial\n\t\tif (! $cast(a, 2.1 * 3.7))\n\t\t\t$display(\"cast failed\");\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.24.2--cast_task.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cast_task\n:description: $cast task\n:tags: 6.24.2 8.16\n*/\nmodule top();\n\tint a;\n\tinitial\n\t\t$cast(a, 2.1 * 3.7);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.24.3--bitstream_cast.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: bitstream_cast\n:description: bitstream cast function\n:tags: 6.24.3\n*/\nmodule top();\n\tstruct packed {logic [7:0] a; logic [7:0] b; logic [15:0] c;} s;\n\tinteger a = integer'(s);\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.5--variable_assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: variable_assignment\n:description: Variable assignment tests\n:tags: 6.5\n*/\nmodule top();\n\tint v;\n\n\tassign v = 12;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.5--variable_mixed_assignments.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: variable_mixed_assignments\n:description: Variable mixed assignments tests\n:should_fail_because: mixing procedural and continuous assignments is illegal\n:tags: 6.5\n:type: simulation elaboration\n*/\nmodule top();\n\twire clk = 0;\n\tint v;\n\n\tassign v = 12;\n\talways @(posedge clk) v <= ~v;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.5--variable_multiple_assignments.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: variable_multiple_assignments\n:description: Variable multiple assignments tests\n:should_fail_because: it shall be an error to have multiple continuous assignments\n:tags: 6.5\n:type: simulation elaboration\n*/\nmodule top();\n\tint v;\n\n\tassign v = 12;\n\tassign v = 13;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.5--variable_redeclare.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: variable_redeclare\n:description: Variable redeclaration tests\n:should_fail_because: Variable redeclaration\n:tags: 6.5\n:type: simulation elaboration\n*/\nmodule top();\n\treg v;\n\twire v;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.6.7--nettype.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: nettype\n:description: user-defined nettype tests\n:tags: 6.6.7\n*/\nmodule top();\n\tnettype real real_net;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.6.7--nettype_resolution_fn.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: nettype_resolution_fn\n:description: user-defined nettype with resolution function tests\n:tags: 6.6.7\n:unsynthesizable: 1\n*/\nmodule top();\n\tfunction automatic real real_sum (input real driver[]);\n\t\treal_sum = 0.0;\n\t\tforeach (driver[i])\n\t\t\treal_sum += driver[i];\n\tendfunction\n\n\tnettype real real_net with real_sum;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.6.8--interconnect.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: interconnect\n:description: generic interconnect tests\n:tags: 6.6.8\n*/\nmodule top();\n\tinterconnect bus;\n\n\tmod_i m1(bus);\n\tmod_o m2(bus);\nendmodule\n\nmodule mod_i(input in);\n\nendmodule\n\nmodule mod_o(output out);\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.9.1--logic_vector.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: logic_vector\n:description: logic vector tests\n:tags: 6.9.1\n*/\nmodule top();\n\tlogic [15:0] a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.9.2--vector_scalared.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: vector_scalared\n:description: scalared vector tests\n:tags: 6.9.2\n*/\nmodule top();\n\ttri1 scalared [15:0] a = 0;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.9.2--vector_vectored.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: vector_vectored\n:description: vectored vector tests\n:tags: 6.9.2\n*/\nmodule top();\n\ttri1 vectored [15:0] a;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-6/6.9.2--vector_vectored_inv.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: vector_vectored_inv\n:description: vectored vector invalid access tests\n:should_fail_because: bit selects are not permitted on vectored vector nets\n:tags: 6.9.2\n*/\nmodule top();\n\tlogic vectored [15:0] a = 0;\n\n\tassign a[1] = 1;\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/alloc.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-allocating-elements\n:description: Test associative arrays elements allocation\n:tags: 7.8.7 7.8 7.9.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint arr [ int ];\n\ninitial begin\n\t$display(\":assert: (%d == 0)\", arr.size);\n\tarr[10] = 10;\n\t$display(\":assert: (%d == 1)\", arr.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/arguments.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-as-arguments\n:description: Test passing associative array as arugments support\n:tags: 7.9.10 7.8\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nstring arraya[int];\n\ntask fun (string arrayb[int]);\n\tarrayb[ 1 ] = \"d\";\n\t$display(\":assert: (('%s' == 'a') and ('%s' == 'd') and ('%s' == 'c'))\",\n\t\tarrayb[0], arrayb[1], arrayb[2]);\nendtask\n\ninitial begin\n\tarraya[ 0 ] = \"a\";\n\tarraya[ 1 ] = \"b\";\n\tarraya[ 2 ] = \"c\";\n\n\t$display(\":assert: (('%s' == 'a') and ('%s' == 'b') and ('%s' == 'c'))\",\n\t\tarraya[0], arraya[1], arraya[2]);\n\n\tfun(arraya);\n\n\t$display(\":assert: (('%s' == 'a') and ('%s' == 'b') and ('%s' == 'c'))\",\n\t\tarraya[0], arraya[1], arraya[2]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-assignment\n:description: Test associative arrays assignment support\n:tags: 7.9.9 7.8\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nstring words [ int ];\nstring w [ int ];\n\ninitial begin\n\twords[0] = \"hello\";\n\twords[1] = \"happy\";\n\twords[2] = \"world\";\n\t$display(\":assert: (('%s' == 'hello') and ('%s' == 'happy') and ('%s' == 'world'))\",\n\t\twords[0], words[1], words[2]);\n\n\tw = words;\n\tw[1] = \"sad\";\n\n\t$display(\":assert: (('%s' == 'hello') and ('%s' == 'happy') and ('%s' == 'world'))\",\n\t\twords[0], words[1], words[2]);\n\t$display(\":assert: (('%s' == 'hello') and ('%s' == 'sad') and ('%s' == 'world'))\",\n\t\tw[0], w[1], w[2]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/class.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-class\n:description: Test associative arrays support\n:tags: 7.8.3 7.8\n*/\nmodule top ();\n\nclass C;\n    int x;\nendclass\n\nint arr [ C ];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/integral.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-integral\n:description: Test associative arrays support\n:tags: 7.8.4 7.8\n*/\nmodule top ();\n\nint arr [ integer ];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/literals.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-literals\n:description: Test associative arrays literals support\n:tags: 7.9.11 7.8\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nstring words [int] = '{default: \"hello\"};\n\ninitial begin\n\t$display(\":assert: ('%s' == 'hello')\", words[1]);\n\twords[1] = \"world\";\n\t$display(\":assert: (('%s' == 'hello') and ('%s' == 'world'))\",\n\t\twords[0], words[1]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-find-first-index\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nstring s[] = { \"hello\", \"sad\", \"hello\", \"world\" };\nint qi[$];\n\ninitial begin\n\tqi = s.find_first_index with ( item == \"hello\" );\n    $display(\":assert: (%d == 1)\", qi.size);\n    $display(\":assert: (%d == 0)\", qi[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/find-first.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-find-first\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nstring s[] = { \"hello\", \"sad\", \"hello\", \"world\" };\nstring qs[$];\n\ninitial begin\n\tqs = s.find_first with ( item == \"hello\" );\n    $display(\":assert: (%d == 1)\", qs.size);\n    $display(\":assert: ('%s' == 'hello')\", qs[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/find-index.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-find-index\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nstring s[] = { \"hello\", \"sad\", \"world\" };\nint qi[$];\n\ninitial begin\n\tqi = s.find_index with ( item == \"world\" );\n    $display(\":assert: (%d == 1)\", qi.size);\n    $display(\":assert: (%d == 2)\", qi[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-find-last-index\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nstring s[] = { \"hello\", \"sad\", \"hello\", \"world\" };\nint qi[$];\n\ninitial begin\n\tqi = s.find_last_index with ( item == \"hello\" );\n    $display(\":assert: (%d == 1)\", qi.size);\n    $display(\":assert: (%d == 2)\", qi[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/find-last.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-find-last\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nstring s[] = { \"hello\", \"sad\", \"hello\", \"world\" };\nstring qs[$];\n\ninitial begin\n\tqs = s.find_last with ( item == \"hello\" );\n    $display(\":assert: (%d == 1)\", qs.size);\n    $display(\":assert: ('%s' == 'hello')\", qs[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/find.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-find\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nstring s[] = { \"hello\", \"sad\", \"world\" };\nstring qs[$];\n\ninitial begin\n\tqs = s.find with ( item == \"sad\" );\n    $display(\":assert: (%d == 1)\", qs.size);\n    $display(\":assert: ('%s' == 'sad')\", qs[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/max.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-max\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint s[] = { 10, 20, 2, 11, 5 };\nint qi[$];\n\ninitial begin\n\tqi = s.max;\n    $display(\":assert: (%d == 1)\", qi.size);\n    $display(\":assert: (%d == 20)\", qi[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/min.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-min\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint s[] = { 10, 20, 2, 11, 5 };\nint qi[$];\n\ninitial begin\n\tqi = s.min;\n    $display(\":assert: (%d == 1)\", qi.size);\n    $display(\":assert: (%d == 2)\", qi[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/unique-index.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-unique-index\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10 7.12.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint s[] = { 10, 10, 3, 20, 20, 10 };\nint qi[$];\n\ninitial begin\n\tqi = s.unique_index;\n    $display(\":assert: (%d == 3)\", qi.size);\n\tqi.sort;\n    $display(\":assert: ((%d == 0) and (%d == 2) and (%d == 3))\",\n\t\tqi[0], qi[1], qi[2]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/locator-methods/unique.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-locator-methods-unique\n:description: Test support of array locator methods\n:tags: 7.12.1 7.12 7.10 7.12.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint s[] = { 10, 10, 3, 20, 20, 10 };\nint qi[$];\n\ninitial begin\n\tqi = s.unique;\n    $display(\":assert: (%d == 3)\", qi.size);\n\tqi.sort;\n    $display(\":assert: ((%d == 3) and (%d == 10) and (%d == 20))\",\n\t\tqi[0], qi[1], qi[2]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/methods/delete.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-delete\n:description: Test support of associative arrays methods (delete)\n:tags: 7.9.2 7.9\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint map [ string ];\n\ninitial begin\n    map[ \"hello\" ] = 1;\n    map[ \"sad\" ] = 2;\n    map[ \"world\" ] = 3;\n    $display(\":assert: (%d == 3)\", map.size);\n    map.delete( \"sad\" );\n    $display(\":assert: (%d == 2)\", map.size);\n    map.delete;\n    $display(\":assert: (%d == 0)\", map.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/methods/exists.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-exists\n:description: Test support of associative arrays methods (exists)\n:tags: 7.9.3 7.9\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint map [ string ];\n\ninitial begin\n    map[ \"hello\" ] = 1;\n    map[ \"sad\" ] = 2;\n    map[ \"world\" ] = 3;\n    $display(\":assert: (%d == 1)\", map.exists( \"sad\" ));\n    $display(\":assert: (%d == 0)\", map.exists( \"happy\" ));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/methods/first.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-first\n:description: Test support of associative arrays methods (first)\n:tags: 7.9.4 7.9\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint map [ string ];\nstring s;\nint rc;\n\ninitial begin\n    // empty, should return zero\n    rc = map.first( s );\n    $display(\":assert: (%d == 0)\", rc);\n\n    map[ \"hello\" ] = 1;\n    map[ \"sad\" ] = 2;\n    map[ \"world\" ] = 3;\n    rc = map.first( s );\n    $display(\":assert: ((%d == 1) and ('%s' == 'hello'))\", rc, s);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/methods/last.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-last\n:description: Test support of associative arrays methods (last)\n:tags: 7.9.5 7.9\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint map [ string ];\nstring s;\nint rc;\n\ninitial begin\n    // empty, should return zero\n    rc = map.last( s );\n    $display(\":assert: (%d == 0)\", rc);\n\n    map[ \"hello\" ] = 1;\n    map[ \"sad\" ] = 2;\n    map[ \"world\" ] = 3;\n    rc = map.last( s );\n    $display(\":assert: ((%d == 1) and ('%s' == 'world'))\", rc, s);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/methods/next.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-next\n:description: Test support of associative arrays methods (next)\n:tags: 7.9.6 7.9\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint map [ string ];\nstring s;\nint rc;\n\ninitial begin\n    map[ \"hello\" ] = 1;\n    map[ \"sad\" ] = 2;\n    map[ \"world\" ] = 3;\n\n    rc = map.first( s );\n    $display(\":assert: ((%d == 1) and ('%s' == 'hello'))\", rc, s);\n    rc = map.next( s );\n    $display(\":assert: ((%d == 1) and ('%s' == 'sad'))\", rc, s);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/methods/num.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-num\n:description: Test support of associative arrays methods (num)\n:tags: 7.9.1 7.9\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint arr [ int ];\n\ninitial begin\n    $display(\":assert: (%d == 0)\", arr.num);\n    arr[ 3 ] = 1;\n    $display(\":assert: (%d == 1)\", arr.num);\n    arr[ 16'hffff ] = 2;\n    $display(\":assert: (%d == 2)\", arr.num);\n    arr[ 4'b1000 ] = 3;\n    $display(\":assert: (%d == 3)\", arr.num);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/methods/prev.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-prev\n:description: Test support of associative arrays methods (prev)\n:tags: 7.9.7 7.9\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint map [ string ];\nstring s;\nint rc;\n\ninitial begin\n    map[ \"hello\" ] = 1;\n    map[ \"sad\" ] = 2;\n    map[ \"world\" ] = 3;\n\n    rc = map.last( s );\n    $display(\":assert: ((%d == 1) and ('%s' == 'world'))\", rc, s);\n    rc = map.prev( s );\n    $display(\":assert: ((%d == 1) and ('%s' == 'sad'))\", rc, s);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/methods/size.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-size\n:description: Test support of associative arrays methods (size)\n:tags: 7.9.1 7.9\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint arr [ int ];\n\ninitial begin\n    $display(\":assert: (%d == 0)\", arr.size);\n    arr[ 3 ] = 1;\n    $display(\":assert: (%d == 1)\", arr.size);\n    arr[ 16'hffff ] = 2;\n    $display(\":assert: (%d == 2)\", arr.size);\n    arr[ 4'b1000 ] = 3;\n    $display(\":assert: (%d == 3)\", arr.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/methods/traversal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-arg-traversal\n:description: Test support of associative arrays methods\n:tags: 7.9.8 7.9\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nstring map[ byte ];\nbyte ix;\nint rc;\n\ninitial begin\n    map[ 1000 ] = \"a\";\n    rc = map.first( ix );\n    $display(\":assert: ( ('%0d' == '1') and ('%b' == '11101000') )\", rc, ix);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/nonexistent.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-access-nonexistent\n:description: Test access to nonexistent associative array element\n:tags: 7.8.6 7.9.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint arr [ int ];\nint r;\n\ninitial begin\n\tarr[10] = 10;\n\t$display(\":assert: (%d == 1)\", arr.size);\n\n\t// access nonexistent element\n\t$display(\":re: BEGIN:ARRAY_NONEXISTENT\");\n\tr = arr[9];\n\t$display(\":re: END\");\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/other.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-other-types\n:description: Test associative arrays support\n:tags: 7.8.1\n:unsynthesizable: 1\n*/\nmodule top ();\n\ntypedef struct {\n    byte B;\n    int I[*];\n} Unpkt;\n\nint arr [ Unpkt ];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/string.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-string\n:description: Test associative arrays support\n:tags: 7.8.2 7.8\n*/\nmodule top ();\n\nint arr [ string ];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/associative/wildcard.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: associative-arrays-wildcard\n:description: Test associative arrays support\n:tags: 7.8.1\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint arr [*];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/dynamic/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dyn-arr-basic\n:description: Test dynamic arrays support\n:tags: 7.5\n*/\nmodule top ();\n\nbit [7:0] arr[];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/dynamic/op-delete.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dynamic-arrays-op-delete\n:description: Test dynamic arrays operator delete support\n:tags: 7.5.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr[];\n\ninitial begin\n    arr = new [ 16 ];\n    $display(\":assert: (%d == 16)\", arr.size);\n    arr.delete;\n    $display(\":assert: (%d == 0)\", arr.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/dynamic/op-new.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dynamic-arrays-op-new\n:description: Test dynamic arrays operator new support\n:tags: 7.5.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr[];\n\ninitial begin\n    arr = new [ 4 ];\n    arr[ 0 ] = 5;\n    arr[ 1 ] = 6;\n    arr[ 2 ] = 7;\n    arr[ 3 ] = 8;\n    $display(\":assert: ((%d == 5) and (%d == 6) and (%d == 7) and (%d == 8))\",\n        arr[ 0 ], arr[ 1 ], arr[ 2 ], arr[ 3 ]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/dynamic/op-size.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dynamic-arrays-op-size\n:description: Test dynamic arrays operator size support\n:tags: 7.5.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr[];\n\ninitial begin\n    arr = new [ 16 ];\n    $display(\":assert: (%d == 16)\", arr.size);\n    arr = new [ 8 ];\n    $display(\":assert: (%d == 8)\", arr.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/multidimensional/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: multi-dim-basic\n:description: Test multidimensional arrays\n:tags: 7.4.5\n*/\n\nmodule top ();\n\n// 10 elements of 4 8-bit bytes\n// (each element packed into 32 bits)\nbit [3:0] [7:0] arr [1:10];\n\n// compatible with memory array\nbit [7:0] mem [0:255];\n\n// Varies most rapidly:\n// 1 to 6\n// 1 to 5\n// 1 to 8\n// 1 to 7\n//    2     1          4     3\nbit [1:5] [1:6] arr2 [1:7] [1:8];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/multidimensional/copy.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: copy\n:description: Test multidimensional word copy\n:tags: 7.4.5\n:type: simulation elaboration parsing\n*/\n\nmodule top ();\n\nbit [3:0] [7:0] arr_a [1:10];\nbit [3:0] [7:0] arr_b [1:10];\n\ninitial begin\n\tarr_a[1] = 32'hdeadbeef;\n\t$display(\":assert: ('%h' == 'deadbeef')\", arr_a[1]);\n\n\tarr_b[2] = arr_a[1];\n\t$display(\":assert: ('%h' == 'deadbeef')\", arr_b[2]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/multidimensional/multi.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: multi-declaration\n:description: Test multidimensional arrays\n:tags: 7.4.5\n*/\n\nmodule top ();\n\n// Same packed dimensions\nbit [7:0] [31:0] arr_a [1:5] [1:10], arr_b [0:255];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/multidimensional/subarrays.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: subarrays\n:description: Test multidimensional subarrays assignments\n:tags: 7.4.5\n:type: simulation elaboration parsing\n*/\n\nmodule top ();\n\nint A[2][3][4], B[2][3][4];\n\ninitial begin\n\tA[0][2][0] = 5;\n\tA[0][2][1] = 6;\n\tA[0][2][2] = 7;\n\tA[0][2][3] = 8;\n\n\tB[1][1] = A[0][2];\n\t$display(\":assert: ((%d == 5) and (%d == 6) and (%d == 7) and (%d == 8))\",\n\t\tB[1][1][0], B[1][1][1], B[1][1][2], B[1][1][3]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: basic-packed\n:description: Test packed arrays support\n:tags: 7.4.1 7.4\n*/\nmodule top ();\n\nbit [7:0] _bit;\nlogic [7:0] _logic;\nreg [7:0] _reg;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/equality.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-packed-arrays-equality\n:description: Test packed arrays operations support (equality)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr_a;\nbit [7:0] arr_b;\n\ninitial begin\n\tarr_a = 8'hff;\n\tarr_b = 8'hff;\n\t$display(\":assert: (('%h' == 'ff') and ('%h' == 'ff'))\", arr_a, arr_b);\n\n\t$display(\":assert: (%d == 1)\", (arr_a == arr_b));\n\t$display(\":assert: (%d == 0)\", (arr_a != arr_b));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/onebit.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-packed-arrays-one-bit\n:description: Test packed arrays operations support (one bit)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr_a;\nbit [7:0] arr_b;\n\ninitial begin\n\tarr_a = 8'hff;\n\tarr_b = 8'h00;\n\t$display(\":assert: (('%h' == 'ff') and ('%h' == '00'))\", arr_a, arr_b);\n\n\tarr_b[5] = arr_a[2];\n\t$display(\":assert: ('%b' == '00100000')\", arr_b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/operations.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-packed-arrays-rw\n:description: Test packed arrays operations support (R & W)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr;\n\ninitial begin\n\tarr = 8'h00;\n\t$display(\":assert: ('%h' == '00')\", arr);\n\n\tarr = 8'hde;\n\t$display(\":assert: ('%h' == 'de')\", arr);\n\n\tarr = 8'had;\n\t$display(\":assert: ('%h' == 'ad')\", arr);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/querying-functions/dimensions.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-packed-quering-functions-dimensions\n:description: Test quering functions support on packed arrays\n:tags: 7.11 7.4.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr;\n\ninitial begin\n\t$display(\":assert: (%d == 1)\", $dimensions(arr));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/querying-functions/high.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-packed-quering-functions-high\n:description: Test quering functions support on packed arrays\n:tags: 7.11 7.4.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr;\n\ninitial begin\n\t$display(\":assert: (%d == 7)\", $high(arr));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/querying-functions/increment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-packed-quering-functions-increment\n:description: Test quering functions support on packed arrays\n:tags: 7.11 7.4.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr;\n\ninitial begin\n\t$display(\":assert: (%d == 1)\", $increment(arr));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/querying-functions/left.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-packed-quering-functions-left\n:description: Test quering functions support on packed arrays\n:tags: 7.11 7.4.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr;\n\ninitial begin\n\t$display(\":assert: (%d == 7)\", $left(arr));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/querying-functions/low.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-packed-quering-functions-low\n:description: Test quering functions support on packed arrays\n:tags: 7.11 7.4.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr;\n\ninitial begin\n\t$display(\":assert: (%d == 0)\", $low(arr));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/querying-functions/right.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-packed-quering-functions-right\n:description: Test quering functions support on packed arrays\n:tags: 7.11 7.4.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr;\n\ninitial begin\n\t$display(\":assert: (%d == 0)\", $right(arr));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/querying-functions/size.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-packed-quering-functions-size\n:description: Test quering functions support on packed arrays\n:tags: 7.11 7.4.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr;\n\ninitial begin\n\t$display(\":assert: (%d == 8)\", $size(arr));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: arrays-packed-quering-functions-unpacked-dimensions\n:description: Test quering functions support on packed arrays\n:tags: 7.11 7.4.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr;\n\ninitial begin\n\t$display(\":assert: (%d == 0)\", $unpacked_dimensions(arr));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/slice-equality.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-packed-arrays-slice-equality\n:description: Test packed arrays operations support (slice equality)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr_a;\nbit [7:0] arr_b;\n\ninitial begin\n\tarr_a = 8'hf0;\n\tarr_b = 8'h0f;\n\t$display(\":assert: (('%h' == 'f0') and ('%h' == '0f'))\", arr_a, arr_b);\n\n\t$display(\":assert: (%d == 1)\", (arr_a[7:4] == arr_b[3:0]));\n\t$display(\":assert: (%d == 0)\", (arr_a[7:4] != arr_b[3:0]));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/slice.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-packed-arrays-slice-rw\n:description: Test packed arrays operations support (R&W slice)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr_a;\nbit [7:0] arr_b;\n\ninitial begin\n\tarr_a = 8'hff;\n\tarr_b = 8'h00;\n\t$display(\":assert: (('%h' == 'ff') and ('%h' == '00'))\", arr_a, arr_b);\n\n\tarr_b[5:3] = arr_a[2:0];\n\t$display(\":assert: ('%b' == '00111000')\", arr_b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/treat-as-integer.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-arrays-treat-as-integer\n:description: Test packed arrays operations support (treat array as integer)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr_a;\nbit [7:0] arr_b;\n\ninitial begin\n\tarr_a = 8'd17;\n\tarr_b = (arr_a + 29);\n\t$display(\":assert: (%d == 46)\", arr_b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/variable-slice-zero.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-arrays-variable-slice-zero-rw\n:description: Test packed arrays operations support (Variable slice)\n:should_fail_because: slicing array with zero part width\n:tags: 7.4.3\n:type: simulation elaboration\n*/\nmodule top ();\n\nbit [7:0] arr_a;\nbit [7:0] arr_b;\n\n// TODO: Not sure if that should fail.\n// TODO: Icarus fails with:\n// TODO: \"error: Indexed part widths must be constant and greater than zero.\"\n// TODO: Info in queue section: \"Unlike arrays, the empty queue, {}, is a valid queue\"\n//\n// Found:\n//  The term slice refers to a selection of one or more contiguous elements of an array\n//  so it should fail\nparameter integer c = 0;\n\ninitial begin\n\tarr_a = 8'hff;\n\tarr_b = 8'h00;\n\t$display(\":assert: (('%h' == 'ff') and ('%h' == '00'))\", arr_a, arr_b);\n\n\tarr_b[4+:c] = arr_a[1+:c];\n\t$display(\":assert: ('%b' == '00000000')\", arr_b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/packed/variable-slice.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-packed-arrays-variable-slice-rw\n:description: Test packed arrays operations support (Variable slice)\n:tags: 7.4.3 7.4.6\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit [7:0] arr_a;\nbit [7:0] arr_b;\n\nparameter integer c = 3;\n\ninitial begin\n\tarr_a = 8'hff;\n\tarr_b = 8'h00;\n\t$display(\":assert: (('%h' == 'ff') and ('%h' == '00'))\", arr_a, arr_b);\n\n\tarr_b[4+:c] = arr_a[1+:c];\n\t$display(\":assert: ('%b' == '01110000')\", arr_b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/assignments.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: array-unpacked-assignments\n:description: Test unpacked arrays assignments\n:tags: 7.6 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint A [3:0];\nint B [0:3];\n\ninitial begin\n\tA[0] = 0;\n\tA[1] = 1;\n\tA[2] = 2;\n\tA[3] = 3;\n\n\tB = A;\n\n\t$display(\":assert: ((%d == 0) and (%d == 1) and (%d == 2) and (%d == 3))\",\n\t\tB[3], B[2], B[1], B[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: basic-unpacked\n:description: Test unpacked arrays support\n:tags: 7.4.2 7.4\n*/\nmodule top ();\n\nbit _bit [7:0];\nlogic _logic [7:0];\nreg _reg [7:0];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/equality.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-unpacked-arrays-equality\n:description: Test unpacked arrays operations support (equality)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit arr_a [7:0];\nbit arr_b [7:0];\n\ninitial begin\n\tarr_a = '{1, 1, 1, 0, 0, 1, 1, 1};\n\tarr_b = '{1, 1, 1, 0, 0, 1, 1, 1};\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '1110_0111')\",\n\t\tarr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]);\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '1110_0111')\",\n\t\tarr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]);\n\n\t$display(\":assert: (%d == 1)\", (arr_a == arr_b));\n\t$display(\":assert: (%d == 0)\", (arr_a != arr_b));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/index.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpacked-array-iterator-index-querying\n:description: Test support of unpacked arrays index querying method\n:tags: 7.12.4 7.4.2 7.10 7.12.1\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint arr[] = { 0, 1, 3, 3 };\nint q[$];\n\ninitial begin\n\tq = arr.find with ( item == item.index );\n\t$display(\":assert: ((%d == 3) and (%d == 0) and (%d == 1) and (%d == 3))\",\n\t\tq.size, q[0], q[1], q[2]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/onebit.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-unpacked-arrays-one-bit\n:description: Test unpacked arrays operations support (one bit)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit arr_a [7:0];\nbit arr_b [7:0];\n\ninitial begin\n\tarr_a = '{1, 1, 1, 1, 1, 1, 1, 1};\n\tarr_b = '{0, 0, 0, 0, 0, 0, 0, 0};\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '1111_1111')\",\n\t\tarr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]);\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '0000_0000')\",\n\t\tarr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]);\n\n\tarr_b[5] = arr_a[2];\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '0010_0000')\",\n\t\tarr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/operations.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-unpacked-arrays-rw\n:description: Test unpacked arrays operations support (R & W)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit arr [7:0];\n\ninitial begin\n\tarr = '{0, 0, 0, 0, 0, 0, 0, 0};\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '0000_0000')\",\n\t\tarr[7], arr[6], arr[5], arr[4], arr[3], arr[2], arr[1], arr[0]);\n\n\tarr = '{1, 1, 0, 1, 1, 1, 1, 0 };\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '1101_1110')\",\n\t\tarr[7], arr[6], arr[5], arr[4], arr[3], arr[2], arr[1], arr[0]);\n\n\tarr = '{1, 0, 1, 0, 1, 1, 0, 1 };\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '1010_1101')\",\n\t\tarr[7], arr[6], arr[5], arr[4], arr[3], arr[2], arr[1], arr[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: ordering-methods-reverse\n:description: Test support of reverse method on unpacked arrays\n:tags: 7.12.2 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nstring s[] = { \"hello\", \"sad\", \"world\" };\n\ninitial begin\n\t$display(\":assert: (('%s' == 'hello') and ('%s' == 'sad') and ('%s' == 'world'))\",\n\t\ts[0], s[1], s[2]);\n\ts.reverse;\n\t$display(\":assert: (('%s' == 'world') and ('%s' == 'sad') and ('%s' == 'hello'))\",\n\t\ts[0], s[1], s[2]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: ordering-methods-rsort\n:description: Test support of rsort method on unpacked arrays\n:tags: 7.12.2 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint ia[] = { 4, 5, 3, 1 };\n\ninitial begin\n\t$display(\":assert: ((%d == 4) and (%d == 5) and (%d == 3) and (%d == 1))\",\n\t\tia[0], ia[1], ia[2], ia[3]);\n\tia.rsort;\n\t$display(\":assert: ((%d == 5) and (%d == 4) and (%d == 3) and (%d == 1))\",\n\t\tia[0], ia[1], ia[2], ia[3]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: ordering-methods-shuffle\n:description: Test support of shuffle method on unpacked arrays\n:tags: 7.12.2 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint ia[] = { 1, 2, 3, 4, 5 };\n\ninitial begin\n\t$display(\":info: { %d, %d, %d, %d, %d }\",\n\t\tia[0], ia[1], ia[2], ia[3], ia[4]);\n\tia.shuffle;\n\t$display(\":info: { %d, %d, %d, %d, %d }\",\n\t\tia[0], ia[1], ia[2], ia[3], ia[4]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: ordering-methods-sort\n:description: Test support of sort method on unpacked arrays\n:tags: 7.12.2 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint ia[] = { 4, 5, 3, 1 };\n\ninitial begin\n\t$display(\":assert: ((%d == 4) and (%d == 5) and (%d == 3) and (%d == 1))\",\n\t\tia[0], ia[1], ia[2], ia[3]);\n\tia.sort;\n\t$display(\":assert: ((%d == 1) and (%d == 3) and (%d == 4) and (%d == 5))\",\n\t\tia[0], ia[1], ia[2], ia[3]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/reduction-methods/and.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpacked-array-reduction-method-and\n:description: Test support of unpacked arrays reduction method and\n:tags: 7.12.3 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbyte b[] = { 1, 3, 5, 7 };\nint y;\n\ninitial begin\n\t$display(\":assert: ((%d == 1) and (%d == 3) and (%d == 5) and (%d == 7))\",\n\t\tb[0], b[1], b[2], b[3]);\n\ty = b.and;\n\t$display(\":assert: (%d == 1)\", y);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/reduction-methods/or.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpacked-array-reduction-method-or\n:description: Test support of unpacked arrays reduction method or\n:tags: 7.12.3 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbyte b[] = { 1, 2, 3, 4 };\nint y;\n\ninitial begin\n\t$display(\":assert: ((%d == 1) and (%d == 2) and (%d == 3) and (%d == 4))\",\n\t\tb[0], b[1], b[2], b[3]);\n\ty = b.or;\n\t$display(\":assert: (%d == 7)\", y);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/reduction-methods/product.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpacked-array-reduction-method-product\n:description: Test support of unpacked arrays reduction method product\n:tags: 7.12.3 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbyte b[] = { 1, 2, 3, 4 };\nint y;\n\ninitial begin\n\t$display(\":assert: ((%d == 1) and (%d == 2) and (%d == 3) and (%d == 4))\",\n\t\tb[0], b[1], b[2], b[3]);\n\ty = b.product;\n\t$display(\":assert: (%d == 24)\", y);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpacked-array-reduction-method-sum\n:description: Test support of unpacked arrays reduction method sum\n:tags: 7.12.3 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbyte b[] = { 1, 2, 3, 4 };\nint y;\n\ninitial begin\n\t$display(\":assert: ((%d == 1) and (%d == 2) and (%d == 3) and (%d == 4))\",\n\t\tb[0], b[1], b[2], b[3]);\n\ty = b.sum;\n\t$display(\":assert: (%d == 10)\", y);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpacked-array-reduction-method-xor\n:description: Test support of unpacked arrays reduction method xor\n:tags: 7.12.3 7.4.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbyte b[] = { 1, 2, 3, 4 };\nint y;\n\ninitial begin\n\t$display(\":assert: ((%d == 1) and (%d == 2) and (%d == 3) and (%d == 4))\",\n\t\tb[0], b[1], b[2], b[3]);\n\ty = b.xor;\n\t$display(\":assert: (%d == 4)\", y);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/slice-equality.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-unpacked-arrays-slice-equality\n:description: Test unpacked arrays operations support (slice equality)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit arr_a [7:0];\nbit arr_b [7:0];\n\ninitial begin\n\tarr_a = '{1, 1, 1, 1, 0, 0, 0, 0};\n\tarr_b = '{0, 0, 0, 0, 1, 1, 1, 1};\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '1111_0000')\",\n\t\tarr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]);\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '0000_1111')\",\n\t\tarr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]);\n\n\t$display(\":assert: (%d == 1)\", (arr_a[7:4] == arr_b[3:0]));\n\t$display(\":assert: (%d == 0)\", (arr_a[7:4] != arr_b[3:0]));\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/slice.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-unpacked-arrays-slice-rw\n:description: Test unpacked arrays operations support (R&W slice)\n:tags: 7.4.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit arr_a [7:0];\nbit arr_b [7:0];\n\ninitial begin\n\tarr_a = '{1, 1, 1, 1, 1, 1, 1, 1};\n\tarr_b = '{0, 0, 0, 0, 0, 0, 0, 0};\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '1111_1111')\",\n\t\tarr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]);\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '0000_0000')\",\n\t\tarr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]);\n\n\tarr_b[5:3] = arr_a[2:0];\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '0011_1000')\",\n\t\tarr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/subroutines.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpacked-arrays-as-arguments-to-subroutines\n:description: Test support of arrays as arugments to subroutines\n:tags: 7.7 7.4.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\ntask fun(int a [2:0]);\n\t$display(\":assert: ((%d == 0) and (%d == 1) and (%d == 2))\",\n\t\ta[0], a[1], a[2]);\nendtask;\n\ninitial begin\n\tint b [2:0];\n\tb[0] = 0;\n\tb[1] = 1;\n\tb[2] = 2;\n\t$display(\":assert: ((%d == 0) and (%d == 1) and (%d == 2))\",\n\t\tb[0], b[1], b[2]);\n\tfun(b);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/arrays/unpacked/variable-slice.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: operations-on-unpacked-arrays-variable-slice-rw\n:description: Test packed arrays operations support (Variable slice)\n:tags: 7.4.3 7.4.6\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nbit arr_a [7:0];\nbit arr_b [7:0];\n\nparameter integer c = 3;\n\ninitial begin\n\tarr_a = '{1, 1, 1, 1, 1, 1, 1, 1};\n\tarr_b = '{0, 0, 0, 0, 0, 0, 0, 0};\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '1111_1111')\",\n\t\tarr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]);\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '0000_0000')\",\n\t\tarr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]);\n\n\tarr_b[4+:c] = arr_a[1+:c];\n\t$display(\":assert: ('%b%b%b%b_%b%b%b%b' == '0111_0000')\",\n\t\tarr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/memories/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: memories-basic\n:description: Test memories support\n:tags: 7.4.4\n*/\nmodule top ();\n\n// one-dimensinal array with elements of types\n// reg, logic, bit\nlogic [7:0] mem [0:255];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/memories/read-write.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: memories-read-write\n:description: Test memories read-write support\n:tags: 7.4.4\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\n// one-dimensinal array with elements of types\n// reg, logic, bit\nlogic [7:0] mem [0:255];\n\ninitial begin\n\tmem[5] = 0;\n\t$display(\":assert: (%d == 0)\", mem[5]);\n\n\tmem[5] = 5;\n\t$display(\":assert: (%d == 5)\", mem[5]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: queues-basic\n:description: Test queues support\n:tags: 7.10\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/bounded.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: bounded-queues\n:description: Test bounded queues support\n:tags: 7.10.5 7.10 7.10.2.7 7.10.2.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint q[$:2]; // 3 elements\n\ninitial begin\n\tq.push_back(1);\n\tq.push_back(2);\n\tq.push_back(3);\n\t$display(\":assert: ((%d == 1) and (%d == 2) and (%d == 3))\",\n\t\tq[0], q[1], q[2]);\n\n\t$display(\":re: BEGIN:QUEUE_FULL\"); // expect warning\n\tq.push_back(4);\n\t$display(\":re: END\");\n\t$display(\":assert: (%d==3)\", q.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/delete.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: delete\n:description: Test queues delete function support\n:tags: 7.10.2.3 7.10.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\nint r;\n\ninitial begin\n\tq.push_back(2);\n\tq.push_back(3);\n\tq.push_back(4);\n\t$display(\":assert: (%d == 3)\", q.size);\n\tq.delete(0);\n\t$display(\":assert: (%d == 2)\", q.size);\n\tq.delete;\n\t$display(\":assert: (%d == 0)\", q.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/delete_assign.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: delete-assign\n:description: Update queue by assignment (delete)\n:tags: 7.10.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\nint r;\n\ninitial begin\n\tq.push_back(2);\n\tq.push_back(3);\n\tq.push_back(4);\n\t$display(\":assert: (%d == 3)\", q.size);\n\tq = q[1:$]; // q.delete(0)\n\t$display(\":assert: (%d == 2)\", q.size);\n\tq = {}; // q.delete\n\t$display(\":assert: (%d == 0)\", q.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/insert.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: insert\n:description: Test queues insert function support\n:tags: 7.10.2.2 7.10.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\n\ninitial begin\n\tq.insert(0, 1);\n\t$display(\":assert: (%d == 1)\", q.size);\n\t$display(\":assert: (%d == 1)\", q[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/insert_assign.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: insert-assign\n:description: Update queue by assignment (insert)\n:tags: 7.10.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\n\ninitial begin\n\tq = { 1, 2, 3, 4 };\n\tq = { q[0:1], 10, q[2:$] }; // q.insert(2, 10)\n\t$display(\":assert: (%d == 5)\", q.size);\n\t$display(\":assert: (%d == 10)\", q[2]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/max-size.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: max-size\n:description: Test queues size support\n:tags: 7.10.1 7.10.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nint q[$:5];\n\ninitial begin\n\tq.push_back(0);\n\tq.push_back(1);\n\tq.push_back(2);\n\tq.push_back(3);\n\tq.push_back(4);\n\tq.push_back(5);\n\t$display(\":assert: (%d == 6)\", q.size);\n\n\t// should issue warning\n\tq.push_back(6);\n\t$display(\":assert: (%d == 6)\", q.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/persistence.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: queues-elements-persistence\n:description: Test status of persistence of references to elements of queue\n:tags: 7.10.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\n\ntask automatic fun(ref int e);\n\t$display(\":assert: (%d == 2)\", e);\n\t#100\n\te = 10;\n\t$display(\":assert: (%d == 10)\", e);\nendtask\n\ninitial begin\n\tq.push_back(1);\n\tq.push_back(2);\n\tq.push_back(3);\n\t$display(\":assert: ((%d == 1) and (%d == 2) and (%d == 3))\",\n\t\tq[0], q[1], q[2]);\n\tfun(q[1]);\nend\n\ninitial begin\n\t#50\n\t$display(\":assert: (%d == 2)\", q[1]);\n\tq.delete();\n\t#100;\n\t$display(\":assert: (%d == 0)\", q.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/pop_back.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pop_back\n:description: Test queues pop_back function support\n:tags: 7.10.2.5 7.10.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\nint r;\n\ninitial begin\n\tq.push_back(2);\n\tq.push_back(3);\n\tq.push_back(4);\n\tr = q.pop_back;\n\t$display(\":assert: (%d == 2)\", q.size);\n\t$display(\":assert: (%d == 4)\", r);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/pop_back_assing.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pop_back-assign\n:description: Update queue by assignment (pop_back)\n:tags: 7.10.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\nint r;\n\ninitial begin\n\tq = { 2, 3, 4 };\n\tr = q[$];\n\tq = q[0:$-1]; // void'(q.pop_back()) or q.delete(q.size-1)\n\t$display(\":assert: (%d == 2)\", q.size);\n\t$display(\":assert: (%d == 4)\", r);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/pop_front.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pop_front\n:description: Test queues pop_front function support\n:tags: 7.10.2.4 7.10.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\nint r;\n\ninitial begin\n\tq.push_back(2);\n\tq.push_back(3);\n\tq.push_back(4);\n\tr = q.pop_front;\n\t$display(\":assert: (%d == 2)\", q.size);\n\t$display(\":assert: (%d == 2)\", r);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/pop_front_assign.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: pop_front-assign\n:description: Update queue by assignment (pop_front)\n:tags: 7.10.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\nint r;\n\ninitial begin\n\tq.push_back(2);\n\tq.push_back(3);\n\tq.push_back(4);\n\tr = q[0];\n\tq = q[1:$];\n\t$display(\":assert: (%d == 2)\", q.size);\n\t$display(\":assert: (%d == 2)\", r);\n\t$display(\":assert: (%d == 3)\", q[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/push_back.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: push_back\n:description: Test queues push_back function support\n:tags: 7.10.2.7 7.10.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\n\ninitial begin\n\tq.push_back(4);\n\tq.push_back(3);\n\tq.push_back(2);\n\t$display(\":assert: (%d == 3)\", q.size);\n\t$display(\":assert: (%d == 4)\", q[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/push_back_assign.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: push_back_assign\n:description: Update queue by assignment (push_back)\n:tags: 7.10.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\n\ninitial begin\n\tq = { q, 4 };\n\tq = { q, 3 };\n\tq = { q, 2 };\n\t$display(\":assert: (%d == 3)\", q.size);\n\t$display(\":assert: (%d == 4)\", q[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/push_front.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: push_front\n:description: Test queues push_front function support\n:tags: 7.10.2.6 7.10.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\n\ninitial begin\n\tq.push_front(2);\n\tq.push_front(3);\n\tq.push_front(4);\n\t$display(\":assert: (%d == 3)\", q.size);\n\t$display(\":assert: (%d == 4)\", q[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/push_front_assign.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: push_front_assign\n:description: Update queue by assignment (push_front)\n:tags: 7.10.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\n\ninitial begin\n\tq = { 2, q };\n\tq = { 3, q };\n\tq = { 4, q };\n\t$display(\":assert: (%d == 3)\", q.size);\n\t$display(\":assert: (%d == 4)\", q[0]);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/size.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: size\n:description: Test queues size support\n:tags: 7.10.2.1 7.10.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$];\n\ninitial begin\n\t$display(\":assert: (%d == 0)\", q.size);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/queues/slice.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: slice\n:description: Test queues slice support\n:tags: 7.10.1 7.10.2\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule top ();\n\nint q[$:5];\nint r[$];\n\ninitial begin\n\tq.push_back(0);\n\tq.push_back(1);\n\tq.push_back(2);\n\tq.push_back(3);\n\tq.push_back(4);\n\tq.push_back(5);\n\t$display(\":assert: (%d == 6)\", q.size);\n\n\tr = q[ 2 : 4 ];\n\t$display(\":assert: (%d == 3)\", r.size); // 4 - 2 + 1 elements\n\n\t// a > b gives empty queue\n\tr = q[ 4 : 2 ];\n\t$display(\":assert: (%d == 0)\", r.size);\n\n\t// a == b gives one element queue\n\tr = q[ 2 : 2 ];\n\t$display(\":assert: (%d == 1)\", r.size);\n\n\t// a < 0 is same as [ 0 : b ]\n\tr = q[ -2 : 2 ]; // 2 - 0 + 1 = 3\n\t$display(\":assert: (%d == 3)\", r.size);\n\n\t// b > $ is same as [ a : $ ]\n\tr = q[ 2 : 10 ]; // 5 - 2 + 1 = 4\n\t$display(\":assert: (%d == 4)\", r.size);\n\n\t// TODO: More invalid index values\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/structures/packed/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: basic-packed-structures\n:description: Test packed structures support\n:tags: 7.2.1 7.2 7.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nstruct packed {\n\tbit [3:0] lo;\n\tbit [3:0] hi;\n} p1;\n\ninitial begin\n\tp1 = 8'h5a;\n\t$display(\":assert: ('%h' == '5a')\", p1);\n\t$display(\":assert: (('%h' == 'a') and ('%h' == '5'))\", p1.hi, p1.lo);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/structures/packed/default-value.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: packed-structures-default-members-value\n:description: Test packed structures default value support\n:should_fail_because: members of packed structures shall not be assigned individual default member values.\n:tags: 7.2.2\n:type: simulation elaboration\n*/\nmodule top ();\n\n// Members of unpacked structures containing a union\n// as well as members of packed structures shall not be\n// assigned individual default member values.\n\nparameter c = 4'h5;\n\nstruct packed {\n\tbit [3:0] lo = c;\n\tbit [3:0] hi;\n} p1;\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/structures/packed/signed.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: packed-and-signed-structures\n:description: Test packed and signed structures support\n:tags: 7.2.1 7.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nstruct packed signed {\n\tbit [3:0] lo;\n\tbit [3:0] hi;\n} p1;\n\ninitial begin\n\tp1 = 8'd200;\n\t$display(\":assert: ('%h' == 'c8')\", p1);\n\t$display(\":assert: (%d == -56)\", p1);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/structures/packed/unsigned.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: packed-and-unsigned-structures\n:description: Test packed and unsigned structures support\n:tags: 7.2.1 7.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nstruct packed unsigned {\n\tbit [3:0] lo;\n\tbit [3:0] hi;\n} p1;\n\ninitial begin\n\tp1 = 8'd200;\n\t$display(\":assert: ('%h' == 'c8')\", p1);\n\t$display(\":assert: (%d == 200)\", p1);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/structures/unpacked/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: basic-unpacked-structures\n:description: Test unpacked structures support\n:tags: 7.2 7.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nstruct {\n\tbit [3:0] lo;\n\tbit [3:0] hi;\n} p1;\n\ninitial begin\n\tp1.lo = 4'h5;\n\tp1.hi = 4'ha;\n\t$display(\":assert: (('%h' == 'a') and ('%h' == '5'))\", p1.hi, p1.lo);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/structures/unpacked/default-value.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: unpacked-structures-members-default-value\n:description: Test unpacked structures members default value support\n:tags: 7.2.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nparameter c = 4'h5;\n\nstruct {\n\tbit [3:0] lo = c;\n\tbit [3:0] hi;\n} p1;\n\ninitial begin\n\tp1.hi = 4'ha;\n\t$display(\":assert: (('%h' == 'a') and ('%h' == '5'))\", p1.hi, p1.lo);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/unions/packed/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: basic-packed-unions\n:description: Test basic union support\n:tags: 7.3.1\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nunion packed {\n\tbit [7:0] v1;\n\tbit [7:0] v2;\n} un;\n\ninitial begin\n\tun.v1 = 8'd140;\n\t$display(\":assert: (%d == 140)\", un.v1);\n\t$display(\":assert: (%d == 140)\", un.v2);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/unions/tagged/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: basic-tagged-union\n:description: Test basic tagged union support\n:tags: 7.3.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nunion tagged {\n\tvoid invalid;\n\tbit [3:0] valid;\n} un;\n\ninitial begin\n\tun = tagged valid (10);\n\t$display(\":assert: ('%p' == ''{valid:10}')\", un);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/unions/tagged/packed.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: basic-tagged-packed-union\n:description: Test tagged packed union support\n:tags: 7.3.2\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nunion tagged packed {\n\tbit [6:0] v1;\n\tbit [6:0] v2;\n} un;\n\ninitial begin\n    un = tagged v2 (10);\n\tun = tagged v1 (85); // 101_0101\n\t$display(\":assert: ('%b' == '01010101')\", un);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-7/unions/unpacked/basic.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: basic-union\n:description: Test basic union support\n:tags: 7.3\n:type: simulation elaboration parsing\n*/\nmodule top ();\n\nunion {\n\tbit [7:0] v1;\n\tbit [3:0] v2;\n} un;\n\ninitial begin\n\tun.v1 = 8'd140;\n\t$display(\":assert: (%d == 140)\", un.v1);\n\t$display(\":assert: (%d == 12)\", un.v2);\nend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.10--static_methods.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: static_methods\n:description: static class methods test\n:tags: 8.10\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tstatic int id = 0;\n\t\tstatic function int next_id();\n\t\t\t++id;\n\t\t\tnext_id = id;\n\t\tendfunction\n\tendclass\n\n\ttest_cls test_obj0;\n\ttest_cls test_obj1;\n\n\tinitial begin\n\t\ttest_obj0 = new;\n\t\ttest_obj1 = new;\n\n\t\t$display(test_obj0.next_id());\n\t\t$display(test_obj1.next_id());\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.11--this.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: this\n:description: this keyword test\n:tags: 8.11\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tint a;\n\t\ttask test_method(int a);\n\t\t\t$display(\"test_method\");\n\t\t\tthis.a += a;\n\t\tendtask\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.12--assignment.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: assignment\n:description: object assignment\n:tags: 8.12\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tint a;\n\t\ttask test_method(int val);\n\t\t\t$display(\"test_method\");\n\t\t\ta += val;\n\t\tendtask\n\tendclass\n\n\ttest_cls test_obj0;\n\ttest_cls test_obj1;\n\n\tinitial begin\n\t\ttest_obj0 = new;\n\t\ttest_obj1 = test_obj0;\n\n\t\ttest_obj0.a = 12;\n\n\t\t$display(test_obj0.a);\n\n\t\ttest_obj0.test_method(9);\n\n\t\t$display(test_obj1.a);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.12--shallow_copy.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: shallow_copy\n:description: object shallow copy\n:tags: 8.12\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tint a;\n\t\ttask test_method(int val);\n\t\t\t$display(\"test_method\");\n\t\t\ta += val;\n\t\tendtask\n\tendclass\n\n\ttest_cls test_obj0;\n\ttest_cls test_obj1;\n\n\tinitial begin\n\t\ttest_obj0 = new;\n\n\t\ttest_obj0.a = 12;\n\n\t\t$display(test_obj0.a);\n\n\t\ttest_obj1 = new test_obj0;\n\n\t\ttest_obj0.test_method(9);\n\n\t\t$display(test_obj1.a);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.13--inheritance.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: inheritance\n:description: class inheritance test\n:tags: 8.13\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass super_cls;\n\t\tint s = 2;\n\t\tfunction int incs();\n\t\t\t++s;\n\t\t\tincs = s;\n\t\tendfunction\n\t\tfunction new(int def = 3);\n\t\t\ts = def;\n\t\tendfunction\n\tendclass\n\n\tclass test_cls extends super_cls;\n\t\tint a;\n\t\tfunction new(int def = 42);\n\t\t\tsuper.new(def + 3);\n\t\t\ta = def;\n\t\tendfunction\n\tendclass\n\n\ttest_cls test_obj;\n\n\tinitial begin\n\t\ttest_obj = new(37);\n\n\t\t$display(test_obj.incs());\n\t\t$display(test_obj.s);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.14--override_member.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: override_member\n:description: class member override test\n:tags: 8.14\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass super_cls;\n\t\tint s = 2;\n\t\tfunction int incs();\n\t\t\t++s;\n\t\t\tincs = s;\n\t\tendfunction\n\t\tfunction new(int def = 3);\n\t\t\ts = def;\n\t\tendfunction\n\tendclass\n\n\tclass test_cls extends super_cls;\n\t\tint a;\n\t\tfunction int incs();\n\t\t\ts += 2;\n\t\t\tincs = s;\n\t\tendfunction\n\t\tfunction new(int def = 42);\n\t\t\tsuper.new(def + 3);\n\t\t\ta = def;\n\t\tendfunction\n\tendclass\n\n\ttest_cls test_obj;\n\tsuper_cls super_obj;\n\n\tinitial begin\n\t\ttest_obj = new(37);\n\t\tsuper_obj = test_obj;\n\n\t\t$display(test_obj.s);\n\t\t$display(test_obj.incs());\n\t\t$display(test_obj.s);\n\t\t$display(super_obj.incs());\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.15--super-default-new.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: super-def-new\n:description: Base class has no user-defined constructor, derived class accesses superclass new()\n:tags: 8.15\n:unsynthesizable: 1\n*/\npackage test_pkg;\n\n  virtual class uvm_void;\n  endclass : uvm_void\n\n  class uvm_object extends uvm_void;\n    virtual function void print ();\n      $display (\"Print\");\n    endfunction : print \n  endclass : uvm_object\n\n  class uvm_report_object extends uvm_object;\n    function new ();\n      super.new ();\n    endfunction : new \n  endclass : uvm_report_object \n\nendpackage : test_pkg\n\nmodule m;\n  import test_pkg::*;\n  uvm_object u0;\n  \n   initial begin : test\n     #100;\n     $display (\"Hello World\");\n     u0 = new ();\n     u0.print();\n\n   end : test\n\nendmodule : m\n\n"
  },
  {
    "path": "tests/chapter-8/8.15--super.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: super\n:description: accessing superclass methods via super\n:tags: 8.15\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass super_cls;\n\t\tint s = 2;\n\t\tfunction int incs();\n\t\t\t++s;\n\t\t\tincs = s;\n\t\tendfunction\n\t\tfunction new(int def = 3);\n\t\t\ts = def;\n\t\tendfunction\n\tendclass\n\n\tclass test_cls extends super_cls;\n\t\tint a;\n\t\tfunction int incs();\n\t\t\ts += 2;\n\t\t\tincs = super.incs();\n\t\tendfunction\n\t\tfunction new(int def = 42);\n\t\t\tsuper.new(def + 3);\n\t\t\ta = def;\n\t\tendfunction\n\tendclass\n\n\ttest_cls test_obj;\n\tsuper_cls super_obj;\n\n\tinitial begin\n\t\ttest_obj = new(37);\n\t\tsuper_obj = test_obj;\n\n\t\t$display(test_obj.s);\n\t\t$display(test_obj.incs());\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.16--cast_func.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cast_func\n:description: $cast function test\n:tags: 8.16\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\ttypedef enum { aaa, bbb, ccc, ddd, eee } values;\n\tinitial begin\n\t\tvalues val;\n\t\tif(!$cast(val, 5))\n\t\t\t$display(\"$cast failed\");\n\t\t$display(val);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.17--constructor_const_arg.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constructor_const_arg\n:description: class inheritance with a constant constructor argument\n:tags: 8.17\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass super_cls;\n\t\tint s = 2;\n\t\tfunction new(int def = 3);\n\t\t\ts = def;\n\t\tendfunction\n\tendclass\n\tclass test_cls extends super_cls(5);\n\t\tint a;\n\t\tfunction new(int def = 42);\n\t\t\ta = def;\n\t\tendfunction\n\tendclass\n\n\ttest_cls test_obj;\n\n\tinitial begin\n\t\ttest_obj = new(37);\n\n\t\t$display(test_obj.a);\n\t\t$display(test_obj.s);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.18--var_local.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: var_local\n:description: class with local variable\n:tags: 8.18\n*/\nmodule class_tb ();\n\tclass a_cls;\n\t\tlocal int a_loc = 2;\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.18--var_protected.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: var_protected\n:description: class with protected variable\n:tags: 8.18\n*/\nmodule class_tb ();\n\tclass a_cls;\n\t\tprotected int a_prot = 2;\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.19--global_constant.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: global_constant\n:description: class with global constant variable\n:tags: 8.19\n*/\nmodule class_tb ();\n\tclass a_cls;\n\t\tconst int c = 12;\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.19--instance_constant.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: instance_constant\n:description: class with instance constant variable\n:tags: 8.19\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass a_cls;\n\t\tconst int c;\n\t\tfunction new(int val);\n\t\t\tc = 20 * val;\n\t\tendfunction\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.20--virtual_method.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: virtual_method\n:description: class with virtual methods\n:tags: 8.20\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass super_cls;\n\t\tint a = 1;\n\t\tvirtual function void print();\n\t\t\t$display(\"super_cls::a: %d\", a);\n\t\tendfunction\n\tendclass\n\n\tclass test_cls extends super_cls;\n\t\tint a = 2;\n\t\tvirtual function void print();\n\t\t\t$display(\"test_cls::a: %d\", a);\n\t\tendfunction\n\tendclass\n\n\ttest_cls test_obj;\n\tsuper_cls super_obj;\n\n\tinitial begin\n\t\ttest_obj = new;\n\t\tsuper_obj = new;\n\n\t\ttest_obj.print();\n\t\tsuper_obj.print();\n\n\t\tsuper_obj = test_obj;\n\n\t\ttest_obj.print();\n\t\tsuper_obj.print();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.21--abstract_class.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: abstract_class\n:description: class extending abstract class\n:tags: 8.21\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tvirtual class base_cls;\n\t\tpure virtual function void print();\n\tendclass\n\n\tclass test_cls extends base_cls;\n\t\tint a = 2;\n\t\tvirtual function void print();\n\t\t\t$display(a);\n\t\tendfunction\n\tendclass\n\n\ttest_cls test_obj;\n\n\tinitial begin\n\t\ttest_obj = new;\n\n\t\ttest_obj.print();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.21--abstract_class_inst.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: abstract_class_inst\n:description: instantiating abstract class\n:should_fail_because: instantiating abstract class\n:tags: 8.21\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tvirtual class base_cls;\n\t\tpure virtual function void print();\n\tendclass\n\n\tclass test_cls extends base_cls;\n\t\tint a = 2;\n\t\tvirtual function void print();\n\t\t\t$display(a);\n\t\tendfunction\n\tendclass\n\n\tbase_cls test_obj;\n\n\tinitial begin\n\t\ttest_obj = new;\n\n\t\ttest_obj.print();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.22--dynamic_method_lookup.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: dynamic_method_lookup\n:description: dynamic method selection with abstract base class\n:tags: 8.22\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tvirtual class base_cls;\n\t\tpure virtual function void print();\n\tendclass\n\n\tclass a_cls extends base_cls;\n\t\tvirtual function void print();\n\t\t\t$display(\"a\");\n\t\tendfunction\n\tendclass\n\n\tclass b_cls extends base_cls;\n\t\tvirtual function void print();\n\t\t\t$display(\"b\");\n\t\tendfunction\n\tendclass\n\n\tclass c_cls extends base_cls;\n\t\tvirtual function void print();\n\t\t\t$display(\"c\");\n\t\tendfunction\n\tendclass\n\n\tbase_cls arr[3];\n\ta_cls a;\n\tb_cls b;\n\tc_cls c;\n\n\tinitial begin\n\t\ta = new;\n\t\tb = new;\n\t\tc = new;\n\t\tarr[0] = a;\n\t\tarr[1] = b;\n\t\tarr[2] = c;\n\n\t\tarr[0].print();\n\t\tarr[1].print();\n\t\tarr[2].print();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.23--scope_resolution.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: scope_resolution\n:description: access static method using scope resolution operator\n:tags: 8.23\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tstatic int id = 0;\n\t\tstatic function int next_id();\n\t\t\t++id;\n\t\t\tnext_id = id;\n\t\tendfunction\n\tendclass\n\n\tinitial begin\n\t\t$display(test_cls::next_id());\n\t\t$display(test_cls::next_id());\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.24--out_of_block_methods.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: out_of_block_methods\n:description: out-of-body method declaration\n:tags: 8.24\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tint a;\n\t\textern function void test_method(int val);\n\tendclass\n\n\tfunction void test_cls::test_method(int val);\n\t\t$display(\"test_method\");\n\t\ta += val;\n\tendfunction\n\n\ttest_cls test_obj;\n\n\tinitial begin\n\t\ttest_obj = new;\n\n\t\ttest_obj.a = 12;\n\n\t\t$display(test_obj.a);\n\n\t\ttest_obj.test_method(9);\n\n\t\t$display(test_obj.a);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.25--parametrized_class_extend.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parametrized_class_extend\n:description: parametrized class extending another parametrized class\n:tags: 8.25\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass base_cls #(int b = 20);\n\t\tint a;\n\tendclass\n\n\tclass ext_cls #(int e = 25) extends base_cls #(5);\n\t\tint c;\n\tendclass\n\n\text_cls #(15) inst;\n\n\tinitial begin\n\t\tinst = new;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parametrized_class_invalid_scope_resolution\n:description: parametrized class invalid scope resolution\n:should_fail_because: parametrized class invalid scope resolution\n:tags: 8.25.1\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\n\tclass par_cls #(int a = 25);\n\t\tparameter int b = 23;\n\tendclass\n\n\tpar_cls #(15) inst;\n\n\tinitial begin\n\t\tinst = new;\n\n\t\t$display(par_cls::b);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parametrized_class_scope_resolution\n:description: parametrized class scope resolution\n:tags: 8.25.1\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\n\tclass par_cls #(int a = 25);\n\t\tparameter int b = 23;\n\tendclass\n\n\tpar_cls #(15) inst;\n\n\tinitial begin\n\t\tinst = new;\n\n\t\t$display(par_cls#()::b);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.2--implements.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implements\n:description: implements keyword test\n:tags: 8.26.2\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\tpure virtual function void hello();\n\tendclass\n\t\n\tclass Hello implements ihello;\n\t\tvirtual function void hello();\n\t\t\t$display(\"hello world\");\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tobj.hello();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.2--implements_extends.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implements_extends\n:description: class both implementing and extending\n:tags: 8.26.2\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\tpure virtual function void hello();\n\tendclass\n\n\tinterface class itest;\n\t\tpure virtual function void test();\n\tendclass\n\n\tclass base;\n\t\tfunction method();\n\t\t\t$display(\"method\");\n\t\tendfunction\n\tendclass\n\t\n\tclass Hello extends base implements ihello, itest;\n\t\tvirtual function void hello();\n\t\t\t$display(\"hello world\");\n\t\tendfunction\n\t\tvirtual function void test();\n\t\t\t$display(\"test\");\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tobj.method();\n\t\tobj.hello();\n\t\tobj.test();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.2--implements_multiple.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implements_multiple\n:description: class implementing multiple interfaces\n:tags: 8.26.2\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\tpure virtual function void hello();\n\tendclass\n\n\tinterface class itest;\n\t\tpure virtual function void test();\n\tendclass\n\t\n\tclass Hello implements ihello, itest;\n\t\tvirtual function void hello();\n\t\t\t$display(\"hello world\");\n\t\tendfunction\n\t\tvirtual function void test();\n\t\t\t$display(\"test\");\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tobj.hello();\n\t\tobj.test();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.3--type_access_extends.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: type_access_extends\n:description: accessing types from extended interface class\n:tags: 8.26.3\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\ttypedef int int_t;\n\t\tpure virtual function void hello(int_t val);\n\tendclass\n\n\tinterface class ihello_ex extends ihello;\n\t\tpure virtual function void hello_ex(int_t v1, int_t v2);\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.3--type_access_implements.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: type_access_implements\n:description: access interface class type with scope resolution operator\n:tags: 8.26.3\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\ttypedef int int_t;\n\t\tpure virtual function void hello(int_t val);\n\tendclass\n\t\n\tclass Hello implements ihello;\n\t\tvirtual function void hello(ihello::int_t val);\n\t\t\t$display(\":assert:(%d == 12)\", val);\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tobj.hello(12);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.3--type_access_implements_invalid.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: type_access_implements_invalid\n:description: access types from implemented class\n:should_fail_because: typedefs are not inherited by implements operator\n:tags: 8.26.3\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\ttypedef int int_t;\n\t\tpure virtual function void hello(int_t val);\n\tendclass\n\t\n\tclass Hello implements ihello;\n\t\tvirtual function void hello(int_t val);\n\t\t\t$display(\"hello world %d\", val);\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tobj.hello();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.4--illegal_forward_def_implements.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: illegal_forward_def_implements\n:description: implementing forward typedef for an interface class should fail\n:should_fail_because: implementing forward typedef for an interface class should fail\n:tags: 8.26.4\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\ttypedef interface class ihello;\n\n\tclass Hello implements ihello;\n\t\tvirtual function void hello(ihello::int_t val);\n\t\t\t$display(\"hello world %d\", val);\n\t\tendfunction\n\tendclass\n\n\tinterface class ihello;\n\t\ttypedef int int_t;\n\t\tpure virtual function void hello(int_t val);\n\tendclass\n\n\tHello obj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tobj.hello();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.4--illegal_implements_parameter.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: illegal_implements_parameter\n:description: implementing parameter that resolves to an interface class is not allowed\n:should_fail_because: implementing parameter that resolves to an interface class is not allowed\n:tags: 8.26.4\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\ttypedef int int_t;\n\t\tpure virtual function void hello(int_t val);\n\tendclass\n\n\tclass Hello #(type T = ihello) implements T;\n\t\tvirtual function void hello(ihello::int_t val);\n\t\t\t$display(\"hello world %d\", val);\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tobj.hello();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.5--cast_between_interface_classes.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: cast_between_interface_classes\n:description: it should be possible to cast between implemented interface classes\n:tags: 8.26.2\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\tpure virtual function void hello();\n\tendclass\n\n\tinterface class itest;\n\t\tpure virtual function void test();\n\tendclass\n\n\tclass Hello implements ihello, itest;\n\t\tvirtual function void hello();\n\t\t\t$display(\"hello world\");\n\t\tendfunction\n\t\tvirtual function void test();\n\t\t\t$display(\"test\");\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\tihello ih_ref;\n\titest it_ref;\n\n\tinitial begin\n\t\tobj = new;\n\t\tih_ref = obj;\n\t\t$cast(it_ref, ih_ref);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.5--implemented_class_handle.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: implemented_class_handle\n:description: it should be possible to assign object handle to a variable of an implemented class type\n:tags: 8.26.5\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\tpure virtual function void hello();\n\tendclass\n\t\n\tclass Hello implements ihello;\n\t\tvirtual function void hello();\n\t\t\t$display(\"hello world\");\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\tihello iobj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tiobj = obj;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.5--invalid_interface_instantiation.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: interface_instantiation\n:description: instantiating an interface class\n:should_fail_because: instantiating an interface class\n:tags: 8.26.5\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\tpure virtual function void hello();\n\tendclass\n\t\n\tihello obj;\n\n\tinitial begin\n\t\tobj = new;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.6.1--name_conflict_resolved.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: name_conflict_resolved\n:description: resolved interface class method name conflict\n:tags: 8.26.6.1\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\tpure virtual function void hello();\n\tendclass\n\n\tinterface class itest;\n\t\tpure virtual function void hello();\n\tendclass\n\t\n\tclass Hello implements ihello, itest;\n\t\tvirtual function void hello();\n\t\t\t$display(\":assert:(True)\");\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tobj.hello();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: name_conflict_unresolved\n:description: unresolved interface class method name conflict\n:should_fail_because: unresolved interface class method name conflict\n:tags: 8.26.6.1\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\tpure virtual function void hello();\n\tendclass\n\n\tinterface class itest;\n\t\tpure virtual function int hello();\n\tendclass\n\t\n\tclass Hello implements ihello, itest;\n\t\tvirtual function void hello();\n\t\t\t$display(\"hello world\");\n\t\tendfunction\n\tendclass\n\n\tHello obj;\n\n\tinitial begin\n\t\tobj = new;\n\t\tobj.hello();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.6.2--parameter_type_conflict.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameter_type_conflict\n:description: superclass type declaration conflicts must be resolved in subclass\n:tags: 8.26.6.2\n*/\nmodule class_tb ();\n\tinterface class ic1#(type T = logic);\n\t\tpure virtual function void fn1(T a);\n\tendclass\n\n\tinterface class ic2#(type T = logic);\n\t\tpure virtual function void fn2(T a);\n\tendclass\n\t\n\tinterface class ic3#(type TYPE = logic) extends ic1#(TYPE), ic2#(TYPE);\n\t\ttypedef TYPE T;\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameter_type_conflict_unresolved\n:description: superclass type declaration conflicts must be resolved in subclass\n:should_fail_because: superclass type declaration conflicts must be resolved in subclass\n:tags: 8.26.6.2\n:type: simulation elaboration\n*/\nmodule class_tb ();\n\tinterface class ic1#(type T = logic);\n\t\tpure virtual function void fn1(T a);\n\tendclass\n\n\tinterface class ic2#(type T = logic);\n\t\tpure virtual function void fn2(T a);\n\tendclass\n\t\n\tinterface class ic3#(type TYPE = logic) extends ic1#(TYPE), ic2#(TYPE);\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.6.3--diamond_relationship.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: diamond_relationship\n:description: interface class inherited from multiple sources shouldn't create symbol conflicts\n:tags: 8.26.6.3\n*/\nmodule class_tb ();\n\tinterface class ibase;\n\t\tpure virtual function void fn();\n\tendclass\n\n\tinterface class ic1 extends ibase;\n\t\tpure virtual function void fn1();\n\tendclass\n\n\tinterface class ic2 extends ibase;\n\t\tpure virtual function void fn2();\n\tendclass\n\t\n\tinterface class ic3 extends ic1, ic2;\n\t\tpure virtual function void fn3();\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: diamond_relationship_parametrized\n:description: different specializations of an interface class are treated as unique interface class types\n:should_fail_because: different specializations of an interface class are treated as unique interface class types\n:tags: 8.26.6.3\n:type: simulation elaboration\n*/\nmodule class_tb ();\n\tinterface class ibase#(type T = logic);\n\t\tpure virtual function void fn(T val);\n\tendclass\n\n\tinterface class ic1 extends ibase#(bit);\n\t\tpure virtual function void fn1();\n\tendclass\n\n\tinterface class ic2 extends ibase#(string);\n\t\tpure virtual function void fn2();\n\tendclass\n\t\n\tinterface class ic3 extends ic1, ic2;\n\t\tpure virtual function void fn3();\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.26.7--partial_implementation.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: partial_implementation\n:description: virtual classes can implement their interfaces partially\n:tags: 8.26.7\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tinterface class ihello;\n\t\tpure virtual function void hello();\n\t\tpure virtual function void world();\n\tendclass\n\n\tvirtual class vhello implements ihello;\n\t\tvirtual function void hello();\n\t\t\t$display(\"hello\");\n\t\tendfunction\n\t\tpure virtual function void world();\n\tendclass\n\n\tclass helloworld extends vhello;\n\t\tvirtual function void world();\n\t\t\t$display(\"world\");\n\t\tendfunction\n\tendclass\n\n\thelloworld obj;\n\n\tinitial begin\n\t\tobj = new;\n\n\t\tobj.hello();\n\t\tobj.world();\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.27--forward_declaration.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: forward_declaration\n:description: class forward declaration test\n:tags: 8.27\n*/\nmodule class_tb ();\n\ttypedef class C2;\n\n\tclass C1;\n\t\tC2 c;\n\tendclass\n\n\tclass C2;\n\t\tC1 c;\n\tendclass\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.4--instantiation.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: instantiation\n:description: simple class instantiation test\n:tags: 8.4\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tint a;\n\tendclass\n\n\ttest_cls test_obj;\n\n\tinitial begin\n\t\tif(test_obj == null) test_obj = new;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.5--parameters.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parameters\n:description: parametrized class test\n:tags: 8.5 8.25\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls #(parameter a = 12);\n\tendclass\n\n\ttest_cls #(34) test_obj;\n\n\tinitial begin\n\t\ttest_obj = new;\n\t\t$display(\":assert:(%d == 34)\", test_obj.a);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.5--properties.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: properties\n:description: class properties test\n:tags: 8.5\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tint a;\n\tendclass\n\n\ttest_cls test_obj;\n\n\tinitial begin\n\t\ttest_obj = new;\n\n\t\ttest_obj.a = 12;\n\n\t\t$display(\":assert:(%d == 12)\", test_obj.a);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.5--properties_enum.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: properties_enum\n:description: enum defined inside class\n:tags: 8.5\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\ttypedef enum {A = 10, B = 20, C = 30, D = 1} e_type;\n\tendclass\n\n\ttest_cls test_obj;\n\n\tinitial begin\n\t\ttest_obj = new;\n\t\t$display(test_obj.C);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.6--methods.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: methods\n:description: class method test\n:tags: 8.6\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tint a;\n\t\ttask test_method(int val);\n\t\t\t$display(\"test_method\");\n\t\t\ta += val;\n\t\tendtask\n\tendclass\n\n\ttest_cls test_obj;\n\n\tinitial begin\n\t\ttest_obj = new;\n\n\t\ttest_obj.a = 12;\n\n\t\t$display(test_obj.a);\n\n\t\ttest_obj.test_method(9);\n\n\t\t$display(test_obj.a);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.7--constructor.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constructor\n:description: class constructor test\n:tags: 8.7\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tint a;\n\t\tfunction new();\n\t\t\ta = 42;\n\t\tendfunction\n\tendclass\n\n\tinitial begin\n\t\ttest_cls test_obj = new;\n\n\t\t$display(\":assert:(%d == 42)\", test_obj.a);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.7--constructor_param.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constructor_param\n:description: class constructor with arguments test\n:tags: 8.7\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tint a;\n\t\tfunction new(int def = 42);\n\t\t\ta = def;\n\t\tendfunction\n\tendclass\n\n\tinitial begin\n\t\ttest_cls test_obj = new(37);\n\n\t\t$display(\":assert:(%d == 37)\", test_obj.a);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.7--constructor_super.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: constructor_super\n:description: class constructor super test\n:tags: 8.7 8.17\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass super_cls;\n\t\tint s = 2;\n\t\tfunction new(int def = 3);\n\t\t\ts = def;\n\t\tendfunction\n\tendclass\n\tclass test_cls extends super_cls;\n\t\tint a;\n\t\tfunction new(int def = 42);\n\t\t\tsuper.new(def + 3);\n\t\t\ta = def;\n\t\tendfunction\n\tendclass\n\n\ttest_cls test_obj;\n\n\tinitial begin\n\t\ttest_obj = new(37);\n\n\t\t$display(test_obj.a);\n\t\t$display(test_obj.s);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.8--typed_constructor.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typed_constructor\n:description: class typed constructor test\n:tags: 8.8\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass super_cls;\n\t\tint s = 2;\n\t\tfunction new(int def = 3);\n\t\t\ts = def;\n\t\tendfunction\n\tendclass\n\n\tclass test_cls extends super_cls;\n\t\tint a;\n\t\tfunction new(int def = 42);\n\t\t\tsuper.new(def + 3);\n\t\t\ta = def;\n\t\tendfunction\n\tendclass\n\n\ttest_cls super_obj;\n\n\tinitial begin\n\t\tsuper_obj = test_cls::new;\n\n\t\t$display(super_obj.s);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.8--typed_constructor_param.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typed_constructor_param\n:description: typed class constructor with parameters test\n:tags: 8.8\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass super_cls;\n\t\tint s = 2;\n\t\tfunction new(int def = 3);\n\t\t\ts = def;\n\t\tendfunction\n\tendclass\n\n\tclass test_cls #(int t = 12) extends super_cls;\n\t\tint a;\n\t\tfunction new(int def = 42);\n\t\t\tsuper.new(def + 3);\n\t\t\ta = def - t;\n\t\tendfunction\n\tendclass\n\n\tsuper_cls super_obj;\n\n\tinitial begin\n\t        super_obj = test_cls#(.t(23))::new(.def(41));\n\n\t\t$display(super_obj.s);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-8/8.9--static_properties.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: static_properties\n:description: static class properties test\n:tags: 8.9\n:unsynthesizable: 1\n*/\nmodule class_tb ();\n\tclass test_cls;\n\t\tstatic int s = 24;\n\tendclass\n\n\ttest_cls test_obj0;\n\ttest_cls test_obj1;\n\n\tinitial begin\n\t\ttest_obj0 = new;\n\t\ttest_obj1 = new;\n\n\t\ttest_obj0.s = 12;\n\t\t$display(test_obj0.s);\n\t\ttest_obj0.s = 13;\n\t\t$display(test_obj1.s);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.2.1--initial.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: initial\n:description: initial check\n:tags: 9.2.1\n*/\nmodule initial_tb ();\n\treg a = 0;\n\tinitial\n\t\ta = 1;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.2.2.1--always.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: always\n:description: always check\n:tags: 9.2.2.1 9.4.1\n*/\nmodule always_tb ();\n\tlogic a = 0;\n\talways #5 a = ~a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.2.2.2--always_comb.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: always_comb\n:description: always_comb check\n:tags: 9.2.2.2\n*/\nmodule always_tb ();\n\twire a = 0;\n\treg b = 0;\n\talways_comb\n\t\tb = ~a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.2.2.3--always_latch.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: always_latch_expr\n:description: always_latch check\n:tags: 9.2.2.3\n*/\nmodule always_tb ();\n\twire a = 0;\n\twire b = 0;\n\treg q = 0;\n\talways_latch\n\t\tif(a) q <= b;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.2.2.4--always_ff.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: always_ff\n:description: always_ff check\n:tags: 9.2.2.4\n*/\nmodule always_tb ();\n\twire a = 0;\n\twire b = 0;\n\treg q = 0;\n\talways_ff @(posedge a)\n\t\tq <= b;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.2.3--final.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: final\n:description: final check\n:tags: 9.2.3\n*/\nmodule initial_tb ();\n\treg a = 0;\n\tfinal\n\t\ta = 1;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.1--sequential_block.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sequential_block\n:description: sequential block check\n:tags: 9.3.1\n*/\nmodule sequential_tb ();\n\treg a = 0;\n\treg b = 0;\n\treg c = 0;\n\tinitial begin\n\t\ta = 1;\n\t\tb = a;\n\t\tc = b;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.2--parallel_block_join.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parallel_block_join\n:description: parallel block check\n:tags: 9.3.2\n:unsynthesizable: 1\n*/\nmodule parallel_tb ();\n\treg a = 0;\n\treg b = 0;\n\treg c = 0;\n\tinitial\n\t\tfork\n\t\t\ta = 1;\n\t\t\tb = 0;\n\t\t\tc = 1;\n\t\tjoin\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.2--parallel_block_join_any.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parallel_block_join_any\n:description: parallel block check\n:tags: 9.3.2\n:unsynthesizable: 1\n*/\nmodule parallel_tb ();\n\treg a = 0;\n\treg b = 0;\n\treg c = 0;\n\tinitial\n\t\tfork\n\t\t\ta = 1;\n\t\t\tb = 0;\n\t\t\tc = 1;\n\t\tjoin_any\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.2--parallel_block_join_none.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: parallel_block_join_none\n:description: parallel block check\n:tags: 9.3.2\n:unsynthesizable: 1\n*/\nmodule parallel_tb ();\n\treg a = 0;\n\treg b = 0;\n\treg c = 0;\n\tinitial\n\t\tfork\n\t\t\ta = 1;\n\t\t\tb = 0;\n\t\t\tc = 1;\n\t\tjoin_none\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.3--block_start_finish.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: block_start_finish\n:description: block start finish check\n:tags: 9.3.3\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg [3:0] a = 0;\n\tinitial begin\n\t\tfork\n\t\t\t#200 a = 'h1;\n\t\t\t#150 a = 'h2;\n\t\t\t#100 a = 'h3;\n\t\t\t#50  a = 'h4;\n\t\tjoin\n\n\t\tfork\n\t\t\t#200 a = 'h5;\n\t\t\t#150 a = 'h6;\n\t\t\t#100 a = 'h7;\n\t\t\t#50  a = 'h8;\n\t\tjoin\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.3--event.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_order\n:description: event order test\n:tags: 9.3.3\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\tevent ev;\n\treg [3:0] a = 0;\n\tinitial fork\n\t\tbegin\n\t\t\ta = 'h3;\n\t\t\t#20;\n\t\t\t->ev;\n\t\tend\n\t\tbegin\n\t\t\t@ev\n\t\t\ta = 'h4;\n\t\tend\n\tjoin\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.3--fork_return.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: fork_return\n:description: illegal return from fork\n:should_fail_because: illegal return from fork\n:tags: 9.3.3\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\ttask fork_test;\n\t\tfork\n\t\t\t#20;\n\t\t\treturn;\n\t\tjoin_none\n\tendtask\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.4--block_names_par.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: block_names_par\n:description: parallel block names check\n:tags: 9.3.4\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg a = 0;\n\tinitial\n\t\tfork: name\n\t\t\ta = 1;\n\t\tjoin: name\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.4--block_names_seq.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: block_names_seq\n:description: sequential block names check\n:tags: 9.3.4\n*/\nmodule block_tb ();\n\treg a = 0;\n\treg b = 0;\n\treg c = 0;\n\tinitial\n\t\tbegin: name\n\t\t\ta = 1;\n\t\t\tb = a;\n\t\t\tc = b;\n\t\tend: name\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.5--statement_labels_par.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: statement_labels_par\n:description: parallel block labels check\n:tags: 9.3.5\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg a = 0;\n\tinitial\n\t\tname: fork\n\t\t\ta = 1;\n\t\tjoin: name\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.3.5--statement_labels_seq.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: statement_labels_seq\n:description: sequential block labels check\n:tags: 9.3.5\n*/\nmodule block_tb ();\n\treg a = 0;\n\treg b = 0;\n\treg c = 0;\n\tinitial\n\t\tname: begin\n\t\t\ta = 1;\n\t\t\tb = a;\n\t\t\tc = b;\n\t\tend: name\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.1--delay_control-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: delay_control_sim\n:description: delay control simulation\n:tags: 9.4.1\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule top();\n\n   initial begin\n      $display(\":assert: (0 == %d)\", $time);\n\n      #10;\n      $display(\":assert: (10 == %d)\", $time);\n\n      #10;\n      $display(\":assert: (20 == %d)\", $time);\n\n      #10;\n      $display(\":assert: (30 == %d)\", $time);\n\n      $finish;\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.1--delay_control-two-blocks-sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: delay_control_two_blocks_sim\n:description: delay control simulation with two blocks\n:tags: 9.4.1\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule top();\n\n   initial begin\n      $display(\":assert: (0 == %d)\", $time);\n\n      #10;\n      $display(\":assert: (10 == %d)\", $time);\n\n      #10;\n      $display(\":assert: (20 == %d)\", $time);\n\n      #10;\n      $display(\":assert: (30 == %d)\", $time);\n\n      $finish;\n   end\n\n   initial begin\n      #5;\n      #10;\n      #10;\n   end\nendmodule\n\n"
  },
  {
    "path": "tests/chapter-9/9.4.1--delay_control.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: delay_control\n:description: delay control\n:tags: 9.4.1\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg [3:0] a = 0;\n\tinitial begin\n\t\t#10 a = 'h1;\n\t\t#10 a = 'h2;\n\t\t#10 a = 'h3;\n\t\t#10 a = 'h4;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2--event_control_edge.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_control_edge\n:description: event control\n:tags: 9.4.2\n*/\nmodule block_tb ();\n\treg [3:0] a = 0;\n\twire clk = 0;\n\talways @(edge clk) a = ~a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2--event_control_negedge.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_control_negedge\n:description: event control\n:tags: 9.4.2\n*/\nmodule block_tb ();\n\treg [3:0] a = 0;\n\twire clk = 0;\n\talways @(negedge clk) a = ~a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2--event_control_posedge.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_control_posedge\n:description: event control\n:tags: 9.4.2\n*/\nmodule block_tb ();\n\treg [3:0] a = 0;\n\twire clk = 0;\n\talways @(posedge clk) a = ~a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2--event_control_sim.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_control_simulation\n:description: Test event invocation\n:tags: 9.4.2\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule top();\n   event e;\n\n   int i = 0;\n\n   initial begin\n      // For now increment time and order locally only, do some simple checks\n      #5;\n      i++;\n      $display(\":assert: (1 == %d)\", i);\n      $display(\":assert: (5 == %d)\", $time);\n\n      #5;\n      i++;\n      $display(\":assert: (2 == %d)\", i);\n      $display(\":assert: (10 == %d)\", $time);\n\n      // Run event a, i should be incremented inside that event\n      #2;\n      ->e;\n\n      // i is not incremented until the next delay\n      $display(\":assert: (2 == %d)\", i);\n      // but time already is\n      $display(\":assert: (12 == %d)\", $time);\n      #3;\n\n      $display(\":assert: (3 == %d)\", i);\n      $display(\":assert: (15 == %d)\", $time);\n\n      $finish;\n   end\n\n   always @ (e) begin\n      i++;\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2--event_control_sim_minimal.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_control_simulation_minimal\n:description: Test event invocation\n:tags: 9.4.2\n:type: simulation elaboration\n:unsynthesizable: 1\n*/\nmodule top();\n   event e;\n\n   int i = 0;\n\n   initial begin\n      $display(\":assert: (0 == %d)\", i);\n      $display(\":assert: (0 == %d)\", $time);\n\n      ->e;\n\n      #5;\n\n      $display(\":assert: (1 == %d)\", i);\n      $display(\":assert: (5 == %d)\", $time);\n\n      $finish;\n   end\n\n   always @ (e) begin\n      i++;\n   end\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2.1--event_comma_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_comma_op\n:description: event comma operator\n:tags: 9.4.2.1\n*/\nmodule block_tb ();\n\twire a = 0;\n\twire b = 0;\n\twire c = 0;\n\twire d = 0;\n\treg out;\n\talways @(a, b, c, d)\n\t\tout = (a | b) & (c | d);\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2.1--event_or_op.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_or_op\n:description: event or operator\n:tags: 9.4.2.1\n*/\nmodule block_tb ();\n\twire a = 0;\n\twire b = 0;\n\twire c = 0;\n\twire d = 0;\n\treg out;\n\talways @(a or b or c or d)\n\t\tout = (a | b) & (c | d);\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2.2--event_implicit.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_implicit\n:description: event implicit list\n:tags: 9.4.2.2\n*/\nmodule block_tb ();\n\twire a = 0;\n\twire b = 0;\n\twire c = 0;\n\twire d = 0;\n\treg out;\n\talways @(*)\n\t\tout = (a | b) & (c | d);\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2.3--event_conditional.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_conditional\n:description: event conditional\n:tags: 9.4.2.3\n*/\nmodule block_tb ();\n\twire clk = 0;\n\twire en = 0;\n\twire a = 0;\n\treg y;\n\talways @(posedge clk iff en == 1)\n\t\ty <= a;\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.2.4--event_sequence.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_sequence\n:description: sequence event test\n:tags: 9.4.2.4\n:type: simulation elaboration parsing\n:unsynthesizable: 1\n*/\nmodule seq_tb ();\n\tlogic a = 0;\n\tlogic b = 0;\n\tlogic c = 0;\n\tlogic y = 0;\n\tlogic clk = 0;\n\n\tsequence seq;\n\t\t@(posedge clk) a ##1 b ##1 c;\n\tendsequence\n\n\tinitial begin\n\t\tfork\n\t\t\tbegin\n\t\t\t\t@seq y = 1;\n\t\t\t\t$display(\":assert:(True)\");\n\t\t\tend\n\t\t\tbegin\n\t\t\t\ta = 1;\n\t\t\t\t#10 clk = 1;\n\t\t\t\t#10 clk = 0;\n\t\t\t\tb = 1;\n\t\t\t\t#10 clk = 1;\n\t\t\t\t#10 clk = 0;\n\t\t\t\tc = 1;\n\t\t\t\t#10 clk = 1;\n\t\t\t\t#10 clk = 0;\n\t\t\tend\n\t\tjoin\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.3--event_sequence_controls.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_sequence_controls\n:description: event sequence\n:tags: 9.4.3\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg a = 0;\n\twire b = 1;\n\treg enable = 0;\n\n\tinitial begin\n\t\t#10 enable = 1;\n\tend\n\n\tinitial begin\n\t\twait (enable) #10 a = b;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.5--event_blocking_assignment_delay.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_blocking_assignment_delay\n:description: event blk assignment delay\n:tags: 9.4.5\n*/\nmodule block_tb ();\n\treg a = 0;\n\treg b = 1;\n\n\tinitial begin\n\t\ta = #10 b;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.5--event_nonblocking_assignment_delay.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_nonblocking_assignment_delay\n:description: event non blk assignment delay\n:tags: 9.4.5\n*/\nmodule block_tb ();\n\treg a = 0;\n\treg b = 1;\n\n\tinitial begin\n\t\ta <= #10 b;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.5--event_nonblocking_assignment_event.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_nonblocking_assignment_event\n:description: event non blk assignment event\n:tags: 9.4.5\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg a = 0;\n\treg b = 1;\n\twire clk = 0;\n\n\tinitial begin\n\t\ta = @(posedge clk) b;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_nonblocking_assignment_repeat\n:description: event non blk assignment repeat\n:tags: 9.4.5\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg a = 0;\n\treg b = 1;\n\twire clk = 0;\n\n\tinitial begin\n\t\ta = repeat(3) @(posedge clk) b;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_nonblocking_assignment_repeat_int\n:description: event non blk assignment repeat\n:tags: 9.4.5\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg a = 0;\n\treg b = 1;\n\twire clk = 0;\n\n\tint i = 3;\n\n\tinitial begin\n\t\ta = repeat(i) @(posedge clk) b;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int_neg.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_nonblocking_assignment_repeat_int_neg\n:description: event non blk assignment repeat\n:tags: 9.4.5\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg a = 0;\n\treg b = 1;\n\twire clk = 0;\n\n\tint i = -3;\n\n\tinitial begin\n\t\ta = repeat(i) @(posedge clk) b;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_neg.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: event_nonblocking_assignment_repeat_neg\n:description: event non blk assignment repeat\n:tags: 9.4.5\n:unsynthesizable: 1\n*/\nmodule block_tb ();\n\treg a = 0;\n\treg b = 1;\n\twire clk = 0;\n\n\tinitial begin\n\t\ta = repeat(-3) @(posedge clk) b;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.6.1--wait_fork.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: wait_fork\n:description: wait fork test\n:tags: 9.6.1\n:unsynthesizable: 1\n*/\nmodule fork_tb ();\n\treg a = 0;\n\treg b = 0;\n\tinitial begin\n\t\tfork\n\t\t\tbegin\n\t\t\t\t#50 a = 1;\n\t\t\t\t#50 a = 0;\n\t\t\t\t#50 a = 1;\n\t\t\tend\n\t\t\tbegin\n\t\t\t\t#50 b = 1;\n\t\t\t\t#50 b = 0;\n\t\t\t\t#50 b = 1;\n\t\t\tend\n\t\tjoin_none\n\t\twait fork;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.6.2--disable.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: disable\n:description: disable block\n:tags: 9.6.2\n*/\nmodule fork_tb ();\n\treg a = 0;\n\treg b = 0;\n\tinitial begin: block\n\t\ta = 1;\n\t\tdisable block;\n\t\tb = 1;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.6.2--disable_other.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: disable_other\n:description: disable other task\n:tags: 9.6.2\n:unsynthesizable: 1\n*/\nmodule fork_tb ();\n\treg a = 0;\n\treg b = 0;\n\treg c = 0;\n\tinitial fork\n\t\tbegin: block\n\t\t\t#10 a = 1;\n\t\t\t#10 b = 1;\n\t\tend\n\t\t#15 disable block;\n\tjoin\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.6.3--disable_fork.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: disable_fork\n:description: disable fork\n:tags: 9.6.3\n:unsynthesizable: 1\n*/\nmodule fork_tb ();\n\treg a = 0;\n\treg b = 0;\n\treg c = 0;\n\tinitial begin\n\t\tfork\n\t\t\t#50 a = 1;\n\t\t\t#100 b = 1;\n\t\t\t#150 c = 1;\n\t\tjoin_any\n\t\tdisable fork;\n\tend\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.7--process_cls_await.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: process_cls_await\n:description: process class await method\n:tags: 9.7\n:unsynthesizable: 1\n*/\nmodule process_tb ();\n\ttask automatic test (int N);\n\t\tprocess job[] = new [N];\n\n\t\tforeach(job[i])\n\t\t\tfork\n\t\t\t\tautomatic int k = i;\n\t\t\t\tbegin\n\t\t\t\t\tjob[k] = process::self();\n\t\t\t\t\t$display(\"process %d\", k);\n\t\t\t\tend\n\t\t\tjoin_none\n\n\t\tforeach(job[i])\n\t\t\twait(job[i] != null);\n\n\t\tjob[1].await();\n\tendtask\n\n\tinitial begin\n\t\ttest(8);\n\tend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.7--process_cls_kill.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: process_cls_kill\n:description: process class kill method\n:tags: 9.7\n:unsynthesizable: 1\n*/\nmodule process_tb ();\n\ttask automatic test (int N);\n\t\tprocess job[] = new [N];\n\n\t\tforeach(job[i])\n\t\t\tfork\n\t\t\t\tautomatic int k = i;\n\t\t\t\tbegin\n\t\t\t\t\tjob[k] = process::self();\n\t\t\t\t\t$display(\"process %d\", k);\n\t\t\t\tend\n\t\t\tjoin_none\n\n\t\tforeach(job[i])\n\t\t\twait(job[i] != null);\n\n\t\tjob[1].await();\n\n\t\tforeach(job[i])\n\t\t\tif(job[i].status != process::FINISHED)\n\t\t\t\tjob[i].kill();\n\tendtask\n\n\tinitial begin\n\t\ttest(8);\n\tend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.7--process_cls_self.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: process_cls_self\n:description: process class self method\n:tags: 9.7\n:unsynthesizable: 1\n*/\nmodule process_tb ();\n\ttask automatic test (int N);\n\t\tprocess job[] = new [N];\n\n\t\tforeach(job[i])\n\t\t\tfork\n\t\t\t\tautomatic int k = i;\n\t\t\t\tbegin\n\t\t\t\t\tjob[k] = process::self();\n\t\t\t\t\t$display(\"process %d\", k);\n\t\t\t\tend\n\t\t\tjoin_none\n\tendtask\n\n\tinitial begin\n\t\ttest(8);\n\tend\n\nendmodule\n"
  },
  {
    "path": "tests/chapter-9/9.7--process_cls_suspend_resume.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: process_control\n:description: process control\n:tags: 9.7\n:unsynthesizable: 1\n*/\nmodule process_tb ();\n\ttask automatic test (int N);\n\t\tprocess job[] = new [N];\n\n\t\tforeach(job[i])\n\t\t\tfork\n\t\t\t\tautomatic int k = i;\n\t\t\t\tbegin\n\t\t\t\t\tjob[k] = process::self();\n\t\t\t\t\tjob[k].suspend();\n\t\t\t\t\t$display(\"process %d\", k);\n\t\t\t\tend\n\t\t\tjoin_none\n\n\t\tforeach(job[i])\n\t\t\twait(job[i] != null);\n\n\t\tforeach(job[i])\n\t\t\tjob[i].resume();\n\n\t\tjob[1].await();\n\n\t\tforeach(job[i])\n\t\t\tif(job[i].status != process::FINISHED)\n\t\t\t\tjob[i].kill();\n\tendtask\n\n\tinitial begin\n\t\ttest(8);\n\tend\n\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_0\n:description: Test\n:tags: 6.15 8.3\n*/\nclass semicolon_classy; ; ;;; ; ; ;endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_1\n:description: Test\n:tags: 6.15 8.3\n*/\nclass Foo; endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_11.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_11\n:description: Test\n:tags: 6.15 8.3\n*/\nclass Foo #(int N, int P);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_12.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_12\n:description: Test\n:tags: 6.15 8.3\n*/\nclass Bar #(int X=0, int Y=1, int Z=2); endclass\nlocalparam x=3, y=4, z=5;\n\nclass Foo #(int N=1, int P=2) extends Bar #(x,y,z);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_13.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_13\n:description: Test\n:tags: 6.15 8.3\n*/\nclass Bar #(int X=0, int Y=1, int Z=2); endclass\nlocalparam x=3, y=4, z=5;\n\nclass Foo #(int W=8, type Int=int) extends Bar #(x,y,z);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_17.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_17\n:description: Test\n:tags: 6.15 8.3\n*/\nclass Foo #(type IFType=virtual x_if);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_18.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_18\n:description: Test\n:tags: 6.15 8.3\n*/\nclass Foo #(type IFType=virtual interface x_if);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_19.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_19\n:description: Test\n:tags: 6.15 8.3\n*/\npackage Package;\nclass Bar #(int X=0, int Y=1, int Z=2); endclass\nendpackage\nlocalparam x=3, y=4, z=5;\n\nclass Foo extends Package::Bar #(x,y,z); endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_21.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_21\n:description: Test\n:tags: 6.15 8.3\n*/\npackage Package;\nclass Bar #(int X=0, int Y=1, int Z=2); endclass\nendpackage\nlocalparam x=3, y=4, z=5;\n\nclass Foo extends Package::Bar #(x,y,z); endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_25.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_25\n:description: Test\n:tags: 6.15 8.3\n*/\npackage Package;\n\tinterface class Bar; endclass\nendpackage\n\nclass Foo implements Package::Bar; endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_26.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_26\n:description: Test\n:tags: 6.15 8.3\n*/\ninterface class Bar #(parameter N); endclass\n\nparameter int N = 1;\nclass Foo implements Bar#(N); endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_27.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_27\n:description: Test\n:tags: 6.15 8.3\n*/\n\npackage Package;\n  interface class Bar #(parameter A, B); endclass\nendpackage\n\nclass Foo implements Package::Bar#(1, 2); endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_28.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_28\n:description: Test\n:tags: 6.15 8.3\n*/\n\nclass Base; endclass\ninterface class Bar; endclass\n\nclass Foo extends Base implements Bar; endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_29.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_29\n:description: Test\n:tags: 6.15 8.3\n*/\n\npackage Pkg;\n  interface class Bar; endclass\nendpackage\n\nclass Base; endclass\ninterface class Baz; endclass\n\nclass Foo extends Base implements Pkg::Bar, Baz; endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_30.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_30\n:description: Test\n:tags: 6.15 8.3\n:unsynthesizable: 1\n*/\nclass Foo;\ninteger size;\nfunction new (integer size);\n  begin\n    this.size = size;\n  end\nendfunction\ntask print();\n  begin\n    $write(\"Hello, world!\");\n  end\nendtask\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_4\n:description: Test\n:tags: 6.15 8.3\n*/\nvirtual class Foo; endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_48.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_48\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_as_class_item;\n `undef EVIL_MACRO\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_49.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_49\n:description: Test\n:tags: 6.15 8.3\n*/\n\npackage glb;\n  localparam int arr[3] = '{1,2,3};\nendpackage\n\nfunction int f(int a);\n  return a;\nendfunction\n\nclass params_as_class_item;\n  parameter N = 2;\n  parameter reg P = '1;\n  localparam M = f(glb::arr[N]) + 1;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_51.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_51\n:description: Test\n:tags: 6.15 8.3\n*/\nclass how_wide;\n  localparam Max_int = {$bits(int) - 1{1'b1}};\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_52.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_52\n:description: Test\n:tags: 6.15 8.3\n:unsynthesizable: 1\n*/\nclass uvm_sequence_item;\nendclass\nclass how_wide #(type DT=int) extends uvm_sequence_item;\n  localparam Max_int = {$bits(DT) - 1{1'b1}};\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_53.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_53\n:description: Test\n:tags: 6.15 8.3\n*/\npackage mypkg;\n  typedef int GlueType;\n  class ModuleType #(parameter A); endclass\nendpackage\n\ntypedef int BrickType;\ntypedef int Ctype1;\ntypedef int Ctype2;\n\nparameter int N = 1;\nparameter int M = 2;\n\nclass param_types_as_class_item;\n  parameter type AT = int;\n  parameter type BT = BrickType;\n  parameter type CT1 = Ctype1, CT2 = Ctype2;\n  localparam type GT = mypkg::GlueType, GT2 = int;\n  localparam type HT1 = int, HT2 = mypkg::ModuleType#(N+M);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_54.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_54\n:description: Test\n:tags: 6.15 8.3\n:unsynthesizable: 1\n*/\nclass event_calendar;\n  event birthday;\n  event first_date, anniversary;\n  event revolution[4:0], independence[2:0];\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_55.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_55\n:description: Test\n:tags: 6.15 8.3\n:unsynthesizable: 1\n*/\nclass Packet;\nendclass\n\nclass Driver;\n  Packet pNP [*];\n  Packet pNP1 [* ];\n  Packet pNP2 [ *];\n  Packet pNP3 [ * ];\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_56.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_56\n:description: Test\n:tags: 6.15 8.3\n*/\ntypedef int data_type_or_module_type;\n\nclass Driver;\n  data_type_or_module_type foo1;\n  data_type_or_module_type foo2 = 1'b1;\n  data_type_or_module_type foo3, foo4;\n  data_type_or_module_type foo5 = 5, foo6 = 6;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_57.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_57\n:description: Test\n:tags: 6.15 8.3\n*/\ntypedef int data_type_or_module_type;\n\nclass fields_with_modifiers;\n  const data_type_or_module_type foo1 = 4'hf;\n  static data_type_or_module_type foo3, foo4;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_58.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_58\n:description: Test\n:tags: 6.15 8.3\n*/\ntypedef int data_type_or_module_type;\n\nclass fields_with_modifiers;\n  const static data_type_or_module_type foo1 = 4'hf;\n  static const data_type_or_module_type foo3 = 1, foo4 = 2;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_59.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_59\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n`ifdef DEBUGGER\n`endif\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_6.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_6\n:description: Test\n:tags: 6.15 8.3\n*/\nclass Bar; endclass\nclass Foo extends Bar; endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_60.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_60\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n`ifdef DEBUGGER\n`ifdef VERBOSE\n`endif\n`endif\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_61.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_61\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n`ifndef DEBUGGER\n`endif\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_62.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_62\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n  int num_packets;\n`ifdef DEBUGGER\n`endif\n  int router_size;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_63.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_63\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n  int num_packets;\n`ifdef DEBUGGER\n  string source_name;\n`endif\n  int router_size;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_64.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_64\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n  int num_packets;\n`ifdef DEBUGGER\n  string source_name;\n  string dest_name;\n`endif\n  int router_size;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_65.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_65\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n  int num_packets;\n`ifdef DEBUGGER\n  string source_name;\n  string dest_name;\n`else\n`endif\n  int router_size;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_66.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_66\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n  int num_packets;\n`ifdef DEBUGGER\n  string source_name;\n  string dest_name;\n`elsif LAZY\n`endif\n  int router_size;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_67.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_67\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n  int num_packets;\n`ifdef DEBUGGER\n`elsif LAZY\n  string source_name;\n  string dest_name;\n`endif\n  int router_size;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_68.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_68\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n  int num_packets;\n`ifdef DEBUGGER\n`elsif BORED\n  string source_name;\n  string dest_name;\n`elsif LAZY\n`endif\n  int router_size;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_69.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_69\n:description: Test\n:tags: 6.15 8.3\n*/\nclass pp_class;\n  int num_packets;\n`ifdef DEBUGGER\n`elsif BORED\n`else\n  string source_name;\n  string dest_name;\n`endif\n  int router_size;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_7.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_7\n:description: Test\n:tags: 6.15 8.3\n*/\npackage Package;\n  class Bar; endclass\nendpackage\n\nclass Foo extends Package::Bar; endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_8.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_8\n:description: Test\n:tags: 6.15 8.3\n*/\nclass Bar #(int X=0, int Y=1, int Z=2); endclass\nlocalparam x=3, y=4, z=5;\n\nclass Foo extends Bar #(x,y,z); endclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/class/class_test_9.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_test_9\n:description: Test\n:tags: 6.15 8.3\n*/\nclass Foo #(int N);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/desc/desc_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_0\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef DEBUGGER\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_1\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef DEBUGGER\n`ifdef VERBOSE\n`else\n`endif\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_10.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_10\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef FPGA\n`ifndef DEBUGGER\ninterface myinterface;\nendinterface\n`endif\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_15.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_15\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef ASIC\nmodule module_asic;\nendmodule\n`else  // ASIC\nmodule module_fpga;\nendmodule\n`endif  // ASIC\n"
  },
  {
    "path": "tests/generic/desc/desc_test_16.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_16\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef ASIC\nmodule module_asic;\nendmodule\n`elsif FPGA  // ASIC\nmodule module_fpga;\nendmodule\n`endif  // ASIC\n"
  },
  {
    "path": "tests/generic/desc/desc_test_17.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_17\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef ASIC_OR_FPGA\nmodule module_asic;\nendmodule\nmodule module_fpga;\nendmodule\n`else\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_18.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_18\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifndef ASIC_OR_FPGA\n`else\nmodule module_asic;\nendmodule\nmodule module_fpga;\nendmodule\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_2\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifndef DEBUGGER\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_3\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef DEBUGGER\n`else\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_4\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef DEBUGGER\n`elsif BORED\n`else\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_5\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef DEBUGGER\n`elsif BORED\n`elsif MORE_BORED\n`else\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_6.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_6\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef DEBUGGER\nmodule mymod;\nendmodule\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_7.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_7\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef DEBUGGER\nmodule mymod;\nendmodule\nmodule mymod_different;\nendmodule\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_8.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_8\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef DEBUGGER\npackage mypkg;\nendpackage\n`endif\n"
  },
  {
    "path": "tests/generic/desc/desc_test_9.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: desc_test_9\n:description: Test\n:type: preprocessing\n:tags: 5.6.4\n*/\n`ifdef FPGA\n`ifdef DEBUGGER\nmodule mymod;\nendmodule\n`endif\n`endif\n"
  },
  {
    "path": "tests/generic/empty/empty_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: empty_test_0\n:description: Test\n:type: preprocessing\n:tags: 5.3 5.4\n*/\n"
  },
  {
    "path": "tests/generic/empty/empty_test_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: empty_test_1\n:description: Test\n:type: preprocessing\n:tags: 5.3 5.4\n*/\n    "
  },
  {
    "path": "tests/generic/empty/empty_test_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: empty_test_2\n:description: Test\n:type: preprocessing\n:tags: 5.3 5.4\n*/\n\t\t\t"
  },
  {
    "path": "tests/generic/empty/empty_test_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: empty_test_3\n:description: Test\n:type: preprocessing\n:tags: 5.3 5.4\n*/\n\n\n"
  },
  {
    "path": "tests/generic/empty/empty_test_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: empty_test_4\n:description: Test\n:type: preprocessing\n:tags: 5.3 5.4\n*/\n// comment\n"
  },
  {
    "path": "tests/generic/empty/empty_test_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: empty_test_5\n:description: Test\n:type: preprocessing\n:tags: 5.3 5.4\n*/\n/* comment */\n"
  },
  {
    "path": "tests/generic/iface/iface_class_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: iface_class_test_0\n:description: Test\n:tags: 8.3 8.26\n*/\ninterface class base_ic;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/iface/iface_class_test_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: iface_class_test_1\n:description: Test\n:tags: 8.3 8.26\n*/\ninterface class base_ic;\nendclass : base_ic\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/iface/iface_class_test_10.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: iface_class_test_10\n:description: Test\n:tags: 8.3 8.26\n*/\ninterface class base_ic;\npure virtual function void pure_task1;\npure virtual function string concatenator(string arg);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/iface/iface_class_test_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: iface_class_test_2\n:description: Test\n:tags: 8.3 8.26\n*/\ninterface class base_ic #(int N = 8, type T = string);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/iface/iface_class_test_9.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: iface_class_test_9\n:description: Test\n:tags: 8.3 8.26\n*/\ntypedef int arg_type;\n\ninterface class base_ic;\npure virtual task pure_task1;\npure virtual task pure_task2(arg_type arg);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_0\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\ntask subtask;\nendtask\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_10.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_10\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass outerclass;\n  class innerclass;\n    class reallyinnerclass;\n      task subtask;\n      endtask\n    endclass\n  endclass\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_11.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_11\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\n  int buzz_count;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_12.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_12\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass semaphore;\n  local chandle p_handle;\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_14.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_14\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\nfunction integer subroutine;\n  input a;\n  subroutine = a+42;\nendfunction\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_15.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_15\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\nextern function void subroutine;\nendclass\n\nfunction void myclass::subroutine; endfunction\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_18.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_18\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\ntypedef logic bool;\nextern function void subroutine(input bool x);\nendclass\n\nfunction void myclass::subroutine(input bool x); endfunction\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_19.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_19\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\ntypedef logic bool;\nlocalparam int N = 2;\nextern function void subr(bool x[N]);\nendclass\n\nfunction void myclass::subr(bool x[N]); endfunction\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_2\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\nextern task subtask(int arg);\nendclass\n\ntask myclass::subtask(int arg); endtask\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_25.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_25\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\nextern virtual function integer subroutine;\nendclass\n\nfunction integer myclass::subroutine; endfunction\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_26.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_26\n:description: Test\n:tags: 8.3\n*/\nvirtual class myclass;\npure virtual function integer subroutine;\npure virtual function integer compute(int a, bit b);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_27.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_27\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass report_server; endclass\ntypedef int uvm_phase;\n\nclass myclass;\nvirtual function void starter(uvm_phase phase);\n  report_server new_server = new;\nendfunction : starter\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_3\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass myclass;\nextern task subtask(int arg);\nendclass\n\ntask myclass::subtask(int arg); endtask\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_31.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_31\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\nint dout;\nint n_bits;\n\nfunction void shifter;\n  for (int shft_idx=0, bit c=1'b1; shft_idx < n_bits;\n       shft_idx++) begin\n    dout = {dout} << 1;\n  end\nendfunction\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_32.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_32\n:description: Test\n:tags: 8.3\n*/\nclass myclass;\nint dout;\nint n_bits;\n\nfunction void shifter;\n  for (var int shft_idx=1, bit c=1'b0; shft_idx < n_bits;\n       shft_idx++) begin\n    dout = {dout} << 1;\n  end\nendfunction\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_39.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_39\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass constructible;\nfunction new;\nendfunction\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_4\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass myclass;\nextern virtual task subtask(int arg);\nendclass\n\ntask myclass::subtask(int arg); endtask\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_40.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_40\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass constructible;\nfunction new ();\nendfunction\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_41.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_41\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass constructible;\nfunction new ();\nendfunction : new\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_5\n:description: Test\n:should_fail_because: pure virtual methods can only be declared in virtual classes\n:tags: 8.3\n:type: elaboration\n:unsynthesizable: 1\n*/\nclass myclass;\npure virtual task pure_task1;\npure virtual task pure_task2(int arg);\nendclass\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_6.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_6\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass myclass;\nextern protected task subtask(int arg);\nendclass\n\ntask myclass::subtask(int arg); endtask\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_7.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_7\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass myclass;\nextern virtual protected task subtask(int arg);\nendclass\n\ntask myclass::subtask(int arg); endtask\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_8.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_8\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass myclass;\nextern protected virtual task subtask(int arg);\nendclass\n\ntask myclass::subtask(int arg); endtask\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/member/class_member_test_9.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: class_member_test_9\n:description: Test\n:tags: 8.3\n:unsynthesizable: 1\n*/\nclass myclass;\ntypedef int arg_type;\nextern local static task subtask(arg_type arg);\nendclass\n\ntask myclass::subtask(arg_type arg); endtask\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_0\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter foo = 0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_1\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_10.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_10\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 1'bx;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_11.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_11\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 1 'b x;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_12.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_12\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 1'bz;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_13.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_13\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 4'bxxxx;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_14.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_14\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 4'bzzzz;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_15.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_15\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 4'sb1111;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_16.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_16\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 4'Sb0000;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_2\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = '0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_24.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_24\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 'd0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_25.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_25\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 'd 0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_26.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_26\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'd1;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_27.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_27\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'D1;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_28.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_28\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32 'd 1;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_29.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_29\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'sd1;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_3\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = '1;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_30.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_30\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'Sd1;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_31.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_31\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'dx;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_32.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_32\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'dx_;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_33.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_33\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'dx__;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_34.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_34\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'dX;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_35.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_35\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'dz;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_36.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_36\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'dZ;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_4\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 'b0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_42.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_42\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 'o0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_43.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_43\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 'o 0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_44.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_44\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'o7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_45.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_45\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'o7_7_7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_46.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_46\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'O7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_47.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_47\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32 'o 7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_48.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_48\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'so7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_49.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_49\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'So7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_5\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 'b 0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_50.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_50\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'oxxx;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_51.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_51\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'oXX;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_52.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_52\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'ozz;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_53.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_53\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'oZZ;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_59.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_59\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 'h0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_6.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_6\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 1'b0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_60.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_60\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 'h 0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_61.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_61\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'h7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_62.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_62\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'H7fFF;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_64.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_64\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'hdeadbeef;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_65.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_65\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'hFEEDFACE;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_66.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_66\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32 'h 7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_67.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_67\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'sh7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_68.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_68\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'Sh7;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_69.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_69\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'hxxx;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_7.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_7\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 1'B0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_70.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_70\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'hXX;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_71.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_71\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'hzz;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_72.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_72\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 32'hZZ;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_8.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_8\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 1 'b 0;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/number/number_test_9.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: number_test_9\n:description: Test\n:tags: 5.6.4 5.7.1 5.7.2\n*/\nparameter int foo = 1'b1;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/preproc/preproc_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: preproc_test_0\n:description: Test\n:tags: 5.6.4\n:type: preprocessing\n*/\n`define TRUTH\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/preproc/preproc_test_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: preproc_test_2\n:description: Test\n:tags: 5.6.4\n:type: preprocessing\n*/\n`include \"preproc_test_2.svh\"\n`ifndef SUCCESS\n\"Didn't successfully include preproc_test_2.svh!\"\n`endif\n`ifndef SANITY\n`define SANITY\n`endif\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/preproc/preproc_test_2.svh",
    "content": "// This file exists for preproc_test_2.sv\n`define SUCCESS\n"
  },
  {
    "path": "tests/generic/preproc/preproc_test_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: preproc_test_4\n:description: Test\n:tags: 5.6.4\n:type: preprocessing\n*/\n`ifdef INSANITY\n`define INSANITY // comment\n`else\n`define SANITY 1\n`endif\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/preproc/preproc_test_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: preproc_test_5\n:description: Test\n:tags: 5.6.4\n:type: preprocessing\n*/\n`define INCEPTION(a, b, c)\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/preproc/preproc_test_6.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: preproc_test_6\n:description: Test\n:tags: 5.6.4\n:type: preprocessing\n*/\n`define INCEPTION(a, b, c) (a*b-c)\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/preproc/preproc_test_7.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: preproc_test_7\n:description: Test\n:tags: 5.6.4\n:type: preprocessing\n*/\n`define INCEPTION(a, b, c) \\\n  (a*b-c)\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/preproc/preproc_test_8.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: preproc_test_8\n:description: Test\n:tags: 5.6.4\n:type: preprocessing\n*/\n`define INCEPTION(xyz) \\\n  `define DEEPER (xyz)\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/struct/struct_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: struct_test_0\n:description: Test\n:tags: 7.2\n*/\ntypedef struct mystruct_fwd;\n\ntypedef struct { logic a; logic b; } mystruct_fwd;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_0\n:description: Test\n:tags: 6.18\n*/\ntypedef i_am_a_type_really;\n\ntypedef int i_am_a_type_really;\n\n// Multiple forward typedefs are allowed.\ntypedef i_am_a_type_really;\ntypedef i_am_a_type_really;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_1.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_1\n:description: Test\n:tags: 6.18\n*/\ntypedef reg[3:0] quartet;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_10.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_10\n:description: Test\n:tags: 6.18\n*/\ntypedef bit data_t;\n\ntypedef data_t my_array_t [ * ];\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_11.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_11\n:description: Test\n:tags: 6.18\n*/\ntypedef bit data_t;\n\ntypedef data_t my_array_t [bit];\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_12.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_12\n:description: Test\n:tags: 6.18\n*/\ntypedef bit data_t;\n\ntypedef data_t my_array_t [bit[31:0]];\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_13.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_13\n:description: Test\n:tags: 6.18\n*/\ntypedef bit data_t;\nparameter k = 6;\nparameter j = 5;\nparameter l = 2;\n\ntypedef data_t my_ar_t [bit[31:0][k:0]][bit[j:0][l:0]];\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_14.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_14\n:description: Test\n:tags: 6.18\n*/\npackage some_package;\n   typedef bit some_type;\nendpackage\n\ntypedef some_package::some_type myalias;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_16.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_16\n:description: Test\n:tags: 6.18\n*/\ntypedef struct packed {\n  logic [4:0] some_member;\n} mystruct_t;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_18.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_18\n:description: Test\n:tags: 6.18\n*/\nparameter K = 9;\n\ntypedef struct {\n  rand bit i;\n  randc integer b[K:0];\n} randstruct;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_19.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_19\n:description: Test\n:tags: 6.18\n*/\ntypedef enum {\n  Global = 2,\n  Local = 3\n} myenum_fwd;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_2.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_2\n:description: Test\n:tags: 6.18\n*/\ntypedef reg quartet[3:0];\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_20.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_20\n:description: Test\n:tags: 6.18\n*/\ntypedef enum logic[3:0] {\n  Global = 4'h2,\n  Local = 4'h3\n} myenum_fwd;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_21.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_21\n:description: Test\n:tags: 6.18\n*/\ntypedef enum bit[3:0] {\n  Global = 4'h2,\n  Local = 4'h3\n} myenum_fwd;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_22.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_22\n:description: Test\n:tags: 6.18\n*/\ntypedef enum uvec8_t;\ntypedef enum {\n  Global = 2,\n  Local = 3\n} uvec8_t;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_23.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_23\n:description: Test\n:tags: 6.18\n*/\ntypedef bit[3:0] num_t;\ntypedef enum num_t {\n  Global = 4'h2,\n  Local = 4'h3\n} myenum_fwd;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_24.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_24\n:description: Test\n:tags: 6.18\n*/\ntypedef struct {\n  int sample;\n  int tile;\n} tuple_t;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_25.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_25\n:description: Test\n:tags: 6.18\n*/\nparameter A = 5;\nparameter D = 32;\nparameter E = 7;\nparameter M = 4;\n\ntypedef struct packed {\n  reg  [A-1:0] addr;\n  reg [D-1:0] data;\n`ifndef FOO\n  reg  [E-1:0] ecc;\n`endif //  `ifndef FOO\n  reg   [M-1:0] mask;\n  reg         parity;\n} req_t;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_25__bad.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_25__bad\n:description: Test\n:should_fail_because: Using undefined parameters\n:tags: 6.18\n:type: simulation elaboration\n*/\n\n// A/D/E/M are not defined, so bad test.\n\ntypedef struct packed {\n  reg  [A-1:0] addr;\n  reg [D-1:0] data;\n`ifndef FOO\n  reg  [E-1:0] ecc;\n`endif //  `ifndef FOO\n  reg   [M-1:0] mask;\n  reg         parity;\n} req_t;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_26.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_26\n:description: Test\n:tags: 6.18\n*/\ntypedef enum {\n`ifdef TWO\n  Global = 2,\n`else\n  Global = 1,\n`endif\n  Local = 3\n} myenum_fwd;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_27.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_27\n:description: Test\n:tags: 6.18\n*/\ntypedef enum {\n  Global = 2,\n`ifdef TWO\n  Local = 2\n`else\n  Local = 1\n`endif\n} myenum_fwd;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_28__bad.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_28__bad\n:description: Test\n:should_fail_because: missing forward typedef declaration, type_identifier does not resolve to a data type.\n:tags: 6.18\n:type: simulation elaboration\n*/\n\n// 6.18 says:\n// The actual data type definition of a forward typedef declaration shall\n// be resolved within the same localscope or generate block. It shall be an\n// error if the type_identifier does not resolve to a data type.\n\ntypedef missing_forward_typedef;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_3.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_3\n:description: Test\n:tags: 6.18\n*/\ntypedef reg[1:0] quartet[1:0];\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_4.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_4\n:description: Test\n:tags: 6.18\n*/\ntypedef enum { RED, GREEN, BLUE } colors;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_5.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_5\n:description: Test\n:tags: 6.18\n*/\ntypedef union { int i; bit b; } bint;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_6.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_6\n:description: Test\n:tags: 6.18\n*/\ntypedef struct { int i; bit b; } mystruct;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_7.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_7\n:description: Test\n:tags: 6.18\n*/\ntypedef struct { int i, j, k; bit b, c, d; } mystruct;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_8.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_8\n:description: Test\n:tags: 6.18\n*/\ntypedef bit some_other_type;\ntypedef some_other_type myalias;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_8__bad.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_8__bad\n:description: Test\n:should_fail_because: defining a type using an undefined type\n:tags: 6.18\n:type: simulation elaboration\n*/\n// some_other_type is not defined\ntypedef some_other_type myalias;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/typedef/typedef_test_9.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: typedef_test_9\n:description: Test\n:tags: 6.18\n*/\nparameter j = 3;\nparameter k = 2;\ntypedef bit data_t;\n\ntypedef data_t my_array_t [k:0][j:0];\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/generic/union/union_test_0.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: union_test_0\n:description: Test\n:tags: 7.3\n*/\ntypedef union myunion_fwd;\n\ntypedef union { logic a; logic b; } myunion_fwd;\n\nmodule test;\nendmodule\n"
  },
  {
    "path": "tests/sanity.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: sanity\n:description: A simple module that should fail during parsing\n:should_fail_because: syntax error, fails during parsing\n:tags: sanity\n*/\nmodule sanity_tb (\n\tclk,\n\tout\n);\n\tinput clk;\n\toutput out;\nsyntaxerror\n\twire clk;\n\treg out;\n\n\treg [31:0] sum = 0;\n\n\talways @(posedge clk) begin\n\t\tif(sum >= 21) begin\n\t\t\tout <= 1;\n\t\t\tsum <= 0;\n\t\tend else begin\n\t\t\tout <= 0;\n\t\t\tsum <= sum + 1;\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_agent_active.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_agent_active\n:description: uvm active agent (agent + monitor + driver + sequencer) test\n:tags: uvm uvm-agents\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`define PATTERN 2\n\ninterface input_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, data);\nendinterface\n\ninterface output_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, output data);\nendinterface\n\nmodule dut(input_if.port in, output_if.port out);\n    always @(posedge in.clk)\n        out.data <= in.data;\nendmodule\n\nclass packet_in extends uvm_sequence_item;\n    logic [7:0] data;\n\n    `uvm_object_utils_begin(packet_in)\n        `uvm_field_int(data, UVM_ALL_ON|UVM_HEX)\n    `uvm_object_utils_end\n\n    function new(string name=\"packet_in\");\n        super.new(name);\n    endfunction: new\nendclass\n\nclass monitor extends uvm_monitor;\n    `uvm_component_utils(monitor)\n    virtual input_if  vif;\n    packet_in packet;\n\n    uvm_analysis_port #(packet_in) item_collected_port;\n\n    function new(string name, uvm_component parent);\n        super.new(name, parent);\n        item_collected_port = new (\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        packet = packet_in::type_id::create(\"packet\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n          \"env\", \"input_if\", vif));\n    endfunction\n\n    virtual task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        fork\n            collect_transactions(phase);\n        join\n        phase.drop_objection(this);\n    endtask\n\n    virtual task collect_transactions(uvm_phase phase);\n        packet.data = vif.data;\n        item_collected_port.write(packet);\n    endtask\nendclass\n\nclass sequence_in extends uvm_sequence #(packet_in);\n    `uvm_object_utils(sequence_in)\n\n    function new(string name=\"sequence_in\");\n        super.new(name);\n    endfunction: new\n\n    task body;\n        packet_in packet;\n\n        packet = packet_in::type_id::create(\"packet\");\n        start_item(packet);\n        packet.data = `PATTERN;\n        finish_item(packet);\n    endtask: body\nendclass\n\nclass sequencer extends uvm_sequencer #(packet_in);\n    `uvm_component_utils(sequencer)\n\n    function new (string name = \"sequencer\", uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\nendclass\n\nclass driver extends uvm_driver #(packet_in);\n    `uvm_component_utils(driver)\n    virtual input_if vif;\n\n    function new(string name = \"driver\", uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n          \"env\", \"input_if\", vif));\n    endfunction\n\n    virtual task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        fork\n            get_and_drive(phase);\n        join\n        phase.drop_objection(this);\n    endtask\n\n    virtual protected task get_and_drive(uvm_phase phase);\n        seq_item_port.get(req);\n        drive_transfer(req);\n    endtask\n\n    virtual protected task drive_transfer(packet_in packet);\n        vif.data <= packet.data;\n        @(posedge vif.clk);\n    endtask\n\nendclass\n\nclass agent_active extends uvm_agent;\n    sequencer sqr;\n    driver  drv;\n    monitor mon;\n\n    uvm_analysis_port #(packet_in) item_collected_port;\n    `uvm_component_utils(agent_active)\n\n    function new(string name = \"agent_active\", uvm_component parent = null);\n        super.new(name, parent);\n        item_collected_port = new(\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        mon = monitor::type_id::create(\"mon\", this);\n        sqr = sequencer::type_id::create(\"sqr\", this);\n        drv = driver::type_id::create(\"drv\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        mon.item_collected_port.connect(item_collected_port);\n        drv.seq_item_port.connect(sqr.seq_item_export);\n    endfunction\nendclass\n\nclass env extends uvm_env;\n    agent_active   agent;\n    virtual output_if vif;\n    static int data;\n    sequence_in seq;\n\n    `uvm_component_utils(env)\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        agent = agent_active::type_id::create(\"agent\", this);\n        seq = sequence_in::type_id::create(\"seq\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual output_if)::read_by_name(\n          get_full_name(), \"output_if\", vif));\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        seq.start(agent.sqr);\n        repeat(3) @(posedge vif.clk);\n        phase.drop_objection(this);\n    endtask\n  \n    virtual function void report_phase(uvm_phase phase);\n        super.report_phase(phase);\n        data <= vif.data;\n        if(data == `PATTERN) begin\n            `uvm_info(\"RESULT\", $sformatf(\"Match %d == %d\",\n               data, `PATTERN), UVM_LOW);\n        end\n        else begin\n            `uvm_error(\"RESULT\", $sformatf(\"Mismatch %d != %d\",\n               data, `PATTERN));\n        end\n    endfunction\nendclass\n\nmodule top;\n    logic clk;\n    env environment;\n\n    input_if in(clk);\n    output_if out(clk);\n    dut d(in, out);\n\n    always #5 clk = !clk;\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual input_if)::set(\"env\", \"input_if\", in);\n        uvm_resource_db#(virtual output_if)::set(\"env\",  \"output_if\", out);\n        clk = 0;\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_agent_env.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_agent_env\n:description: uvm agent + env test\n:tags: uvm uvm-agents\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`define PATTERN 2\n\ninterface input_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, data);\nendinterface\n\ninterface output_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, output data);\nendinterface\n\nmodule dut(input_if.port in, output_if.port out);\n    always @(posedge in.clk)\n        out.data <= in.data;\nendmodule\n\nclass agent extends uvm_agent;\n\n    virtual output_if out_vif;\n    virtual input_if in_vif;\n    `uvm_component_utils(agent)\n\n    function new(string name = \"agent\", uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n          \"env\", \"input_if\", in_vif));\n        assert(uvm_resource_db#(virtual output_if)::read_by_name(\n          \"env\", \"output_if\", out_vif));\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(\"RESULT\", $sformatf(\"Writing %0d to input interface\", `PATTERN), UVM_LOW);\n        in_vif.data <= `PATTERN;\n        repeat(2) @(posedge out_vif.clk);\n        if(out_vif.data == `PATTERN) begin\n            `uvm_info(\"RESULT\", $sformatf(\"Match %d == %d\",\n                out_vif.data, `PATTERN), UVM_LOW);\n        end\n        else begin\n            `uvm_error(\"RESULT\", $sformatf(\"Mismatch %d != %d\",\n                out_vif.data, `PATTERN));\n        end\n\n        phase.drop_objection(this);\n    endtask\n\nendclass\n\nclass env extends uvm_env;\n    agent   ag;\n\n    `uvm_component_utils(env)\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        ag = agent::type_id::create(\"ag\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n    endfunction\n  \n    virtual function void report_phase(uvm_phase phase);\n        super.report_phase(phase);\n    endfunction\nendclass\n\nmodule top;\n    logic clk;\n    env environment;\n\n    input_if in(clk);\n    output_if out(clk);\n    dut d(in, out);\n\n    always #5 clk = !clk;\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual input_if)::set(\"env\", \"input_if\", in);\n        uvm_resource_db#(virtual output_if)::set(\"env\",  \"output_if\", out);\n        clk = 0;\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_agent_passive.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_agent_passive\n:description: passive uvm_agent (agent + monitor + env) test\n:tags: uvm uvm-agents\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`define PATTERN 2\n\ninterface input_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, data);\nendinterface\n\ninterface output_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, output data);\nendinterface\n\nmodule dut(input_if.port in, output_if.port out);\n    always @(posedge in.clk)\n        out.data <= in.data;\nendmodule\n\nclass packet_out extends uvm_sequence_item;\n    logic [7:0] data;\n\n    `uvm_object_utils_begin(packet_out)\n        `uvm_field_int(data, UVM_ALL_ON|UVM_HEX)\n    `uvm_object_utils_end\n\n    function new(string name=\"packet_out\");\n        super.new(name);\n    endfunction: new\nendclass\n\nclass monitor extends uvm_monitor;\n    `uvm_component_utils(monitor)\n    virtual output_if  vif;\n    packet_out packet;\n\n    uvm_analysis_port #(packet_out) item_collected_port;\n\n    function new(string name, uvm_component parent);\n        super.new(name, parent);\n        item_collected_port = new (\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        packet = packet_out::type_id::create(\"packet\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual output_if)::read_by_name(\n          \"env\", \"output_if\", vif));\n    endfunction\n\n    virtual task run_phase(uvm_phase phase);\n        super.run_phase(phase);\n        fork\n            collect_transactions(phase);\n        join\n    endtask\n\n    virtual task collect_transactions(uvm_phase phase);\n        forever begin\n            repeat(2) @(posedge vif.clk);\n            packet.data = vif.data;\n            item_collected_port.write(packet);\n            if(packet.data == `PATTERN) begin\n                `uvm_info(\"RESULT\", $sformatf(\"Match %d == %d\",\n                    packet.data, `PATTERN), UVM_LOW);\n            end\n            else begin\n                `uvm_error(\"RESULT\", $sformatf(\"Mismatch %d != %d\",\n                    packet.data, `PATTERN));\n            end\n        end\n    endtask\nendclass\n\nclass agent_passive extends uvm_agent;\n    monitor mon;\n\n    uvm_analysis_port #(packet_out) item_collected_port;\n    `uvm_component_utils(agent_passive)\n\n    function new(string name = \"agent_passive\", uvm_component parent = null);\n        super.new(name, parent);\n        item_collected_port = new(\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        mon = monitor::type_id::create(\"mon\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        mon.item_collected_port.connect(item_collected_port);\n    endfunction\nendclass\n\nclass env extends uvm_env;\n    agent_passive   agent;\n    virtual input_if vif;\n\n    `uvm_component_utils(env)\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        agent = agent_passive::type_id::create(\"agent\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n          get_full_name(), \"input_if\", vif));\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(\"RESULT\", $sformatf(\"Writing %0d to input interface\", `PATTERN), UVM_LOW);\n        vif.data <= `PATTERN;\n        repeat(2) @(posedge vif.clk);\n        phase.drop_objection(this);\n    endtask\n  \n    virtual function void report_phase(uvm_phase phase);\n        super.report_phase(phase);\n    endfunction\nendclass\n\nmodule top;\n    logic clk;\n    env environment;\n\n    input_if in(clk);\n    output_if out(clk);\n    dut d(in, out);\n\n    always #5 clk = !clk;\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual input_if)::set(\"env\", \"input_if\", in);\n        uvm_resource_db#(virtual output_if)::set(\"env\",  \"output_if\", out);\n        clk = 0;\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_driver_sequencer_env.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_driver_sequencer_env\n:description: uvm driver + sequencer + env test\n:tags: uvm uvm-classes\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`define PATTERN 2\n\ninterface input_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, data);\nendinterface\n\ninterface output_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, output data);\nendinterface\n\nmodule dut(input_if.port in, output_if.port out);\n    always @(posedge in.clk)\n        out.data <= in.data;\nendmodule\n\nclass packet_in extends uvm_sequence_item;\n    logic [7:0] data;\n\n    `uvm_object_utils_begin(packet_in)\n        `uvm_field_int(data, UVM_ALL_ON|UVM_HEX)\n    `uvm_object_utils_end\n\n    function new(string name=\"packet_in\");\n        super.new(name);\n    endfunction: new\nendclass\n\nclass sequence_in extends uvm_sequence #(packet_in);\n    `uvm_object_utils(sequence_in)\n\n    function new(string name=\"sequence_in\");\n        super.new(name);\n    endfunction: new\n\n    task body;\n        packet_in packet;\n\n        packet = packet_in::type_id::create(\"packet\");\n        start_item(packet);\n        packet.data = `PATTERN;\n        finish_item(packet);\n    endtask: body\nendclass\n\nclass sequencer extends uvm_sequencer #(packet_in);\n    `uvm_component_utils(sequencer)\n\n    function new (string name = \"sequencer\", uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\nendclass\n\nclass driver extends uvm_driver #(packet_in);\n    `uvm_component_utils(driver)\n    virtual input_if vif;\n\n    function new(string name = \"driver\", uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n          \"env\", \"input_if\", vif));\n    endfunction\n\n    virtual task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        fork\n            get_and_drive(phase);\n        join\n        phase.drop_objection(this);\n    endtask\n\n    virtual protected task get_and_drive(uvm_phase phase);\n        seq_item_port.get(req);\n        drive_transfer(req);\n    endtask\n\n    virtual protected task drive_transfer(packet_in packet);\n        vif.data <= packet.data;\n    endtask\n\nendclass\n\nclass env extends uvm_env;\n    virtual output_if vif;\n    static int data;\n    sequence_in seq;\n    sequencer sqr;\n    driver  drv;\n\n    `uvm_component_utils(env)\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        seq = sequence_in::type_id::create(\"seq\", this);\n        sqr = sequencer::type_id::create(\"sqr\", this);\n        drv = driver::type_id::create(\"drv\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual output_if)::read_by_name(\n          get_full_name(), \"output_if\", vif));\n        drv.seq_item_port.connect(sqr.seq_item_export);\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        seq.start(sqr);\n        repeat(3) @(posedge vif.clk);\n        phase.drop_objection(this);\n    endtask\n  \n    virtual function void report_phase(uvm_phase phase);\n        super.report_phase(phase);\n        data <= vif.data;\n        if(data == `PATTERN) begin\n            `uvm_info(\"RESULT\", $sformatf(\"Match %d == %d\",\n               data, `PATTERN), UVM_LOW);\n        end\n        else begin\n            `uvm_error(\"RESULT\", $sformatf(\"Mismatch %d != %d\",\n               data, `PATTERN));\n        end\n    endfunction\nendclass\n\nmodule top;\n    logic clk;\n    env environment;\n\n    input_if in(clk);\n    output_if out(clk);\n    dut d(in, out);\n\n    always #5 clk = !clk;\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual input_if)::set(\"env\", \"input_if\", in);\n        uvm_resource_db#(virtual output_if)::set(\"env\",  \"output_if\", out);\n        clk = 0;\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_monitor_env.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_monitor_env\n:description: uvm monitor + env test\n:tags: uvm uvm-classes\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`define PATTERN 2\n\ninterface input_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, data);\nendinterface\n\ninterface output_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, output data);\nendinterface\n\nmodule dut(input_if.port in, output_if.port out);\n    always @(posedge in.clk)\n        out.data <= in.data;\nendmodule\n\nclass packet_out extends uvm_sequence_item;\n    logic [7:0] data;\n\n    `uvm_object_utils_begin(packet_out)\n        `uvm_field_int(data, UVM_ALL_ON|UVM_HEX)\n    `uvm_object_utils_end\n\n    function new(string name=\"packet_out\");\n        super.new(name);\n    endfunction: new\nendclass\n\nclass monitor extends uvm_monitor;\n    `uvm_component_utils(monitor)\n    virtual output_if  vif;\n    packet_out packet;\n\n    uvm_analysis_port #(packet_out) item_collected_port;\n\n    function new(string name, uvm_component parent);\n        super.new(name, parent);\n        item_collected_port = new (\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        packet = packet_out::type_id::create(\"packet\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual output_if)::read_by_name(\n          \"env\", \"output_if\", vif));\n    endfunction\n\n    virtual task run_phase(uvm_phase phase);\n        super.run_phase(phase);\n        fork\n            collect_transactions(phase);\n        join\n    endtask\n\n    virtual task collect_transactions(uvm_phase phase);\n        forever begin\n            repeat(2) @(posedge vif.clk);\n            packet.data = vif.data;\n            item_collected_port.write(packet);\n            if(packet.data == `PATTERN) begin\n                `uvm_info(\"RESULT\", $sformatf(\"Match %d == %d\",\n                    packet.data, `PATTERN), UVM_LOW);\n            end\n            else begin\n                `uvm_error(\"RESULT\", $sformatf(\"Mismatch %d != %d\",\n                    packet.data, `PATTERN));\n            end\n        end\n    endtask\nendclass\n\nclass env extends uvm_env;\n    virtual input_if vif;\n    monitor mon;\n\n    `uvm_component_utils(env)\n\n    uvm_analysis_port #(packet_out) item_collected_port;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n        item_collected_port = new(\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        mon = monitor::type_id::create(\"mon\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n          get_full_name(), \"input_if\", vif));\n        mon.item_collected_port.connect(item_collected_port);\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(\"RESULT\", $sformatf(\"Writing %0d to input interface\", `PATTERN), UVM_LOW);\n        vif.data <= `PATTERN;\n        repeat(2) @(posedge vif.clk);\n        phase.drop_objection(this);\n    endtask\n  \n    virtual function void report_phase(uvm_phase phase);\n        super.report_phase(phase);\n    endfunction\nendclass\n\nmodule top;\n    logic clk;\n    env environment;\n\n    input_if in(clk);\n    output_if out(clk);\n    dut d(in, out);\n\n    always #5 clk = !clk;\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual input_if)::set(\"env\", \"input_if\", in);\n        uvm_resource_db#(virtual output_if)::set(\"env\",  \"output_if\", out);\n        clk = 0;\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_resource_db_read_by_name.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_resource_db_read_by_name\n:description: uvm resource_db::read_by_name test\n:tags: uvm\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass C;\nendclass\n\nclass env extends uvm_env;\n    C obj;\n\n    `uvm_component_utils(env)\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        if(uvm_resource_db#(C)::read_by_name(\n            get_full_name(), \"obj\", obj)) begin\n            `uvm_info(\"RESULT\", \"read_by_name successful\", UVM_LOW);\n        end\n        else begin\n            `uvm_error(\"RESULT\", \"read_by_name failed\");\n        end\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        phase.drop_objection(this);\n    endtask\n  \nendclass\n\nmodule top;\n    env environment;\n    C obj;\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(C)::set(\"env\", \"obj\", obj);\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_scoreboard_env.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_scoreboard_env\n:description: uvm scoreboard + env test\n:tags: uvm uvm-scoreboards\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`define PATTERN 2\n\ninterface input_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, data);\nendinterface\n\ninterface output_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, output data);\nendinterface\n\nmodule dut(input_if.port in, output_if.port out);\n    always @(posedge in.clk)\n        out.data <= in.data;\nendmodule\n\nclass packet_out extends uvm_sequence_item;\n    logic [7:0] data;\n\n    `uvm_object_utils_begin(packet_out)\n        `uvm_field_int(data, UVM_ALL_ON|UVM_HEX)\n    `uvm_object_utils_end\n\n    function new(string name=\"packet_out\");\n        super.new(name);\n    endfunction: new\nendclass\n\nclass comparator #(type T = packet_out) extends uvm_scoreboard;\n    typedef comparator #(T) this_type;\n    `uvm_component_param_utils(this_type)\n    int match, mismatch;\n\n    const static string type_name = \"comparator #(T)\";\n\n    uvm_analysis_imp #(T, this_type) from_dut;\n\n    typedef uvm_built_in_converter #( T ) convert;\n\n    event end_of_simulation;\n\n    function new(string name, uvm_component parent);\n        super.new(name, parent);\n        from_dut = new(\"from_dut\", this);\n        match = 0;\n        mismatch = 0;\n    endfunction\n\n    virtual function string get_type_name();\n        return type_name;\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        @(end_of_simulation);\n        phase.drop_objection(this);\n    endtask\n\n    virtual function void write(T rec);\n        if(rec.data == `PATTERN) begin\n          `uvm_info(\"RESULT\", $sformatf(\"Comparator match %d == %d\", rec.data, `PATTERN), UVM_LOW);\n          match++;\n        end\n        else begin\n          `uvm_error(\"RESULT\", $sformatf(\"Comparator mismatch %d != %d\", rec.data, `PATTERN));\n          mismatch++;\n        end\n        -> end_of_simulation;\n  endfunction\nendclass\n\nclass env extends uvm_env;\n    comparator #(packet_out) comp;  \n    virtual input_if in_vif;\n    virtual output_if out_vif;\n    packet_out packet;\n\n    `uvm_component_utils(env)\n\n    uvm_analysis_port #(packet_out) item_collected_port;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n        item_collected_port = new(\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        comp = comparator#(packet_out)::type_id::create(\"comp\", this);\n        packet = packet_out::type_id::create(\"packet\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n          get_full_name(), \"input_if\", in_vif));\n        assert(uvm_resource_db#(virtual output_if)::read_by_name(\n          get_full_name(), \"output_if\", out_vif));\n        item_collected_port.connect(comp.from_dut);\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        `uvm_info(\"RESULT\", $sformatf(\"Writing %0d to input interface\", `PATTERN), UVM_LOW);\n        in_vif.data <= `PATTERN;\n        repeat(2) @(posedge out_vif.clk);\n        packet.data = out_vif.data;\n        item_collected_port.write(packet);\n    endtask\n\n    virtual function void report_phase(uvm_phase phase);\n        super.report_phase(phase);\n    endfunction\nendclass\n\nmodule top;\n    logic clk;\n    env environment;\n\n    input_if in(clk);\n    output_if out(clk);\n    dut d(in, out);\n\n    always #5 clk = !clk;\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual input_if)::set(\"env\", \"input_if\", in);\n        uvm_resource_db#(virtual output_if)::set(\"env\",  \"output_if\", out);\n        clk = 0;\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_scoreboard_monitor_agent_env.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_scoreboard_monitor_agent_env\n:description: uvm scoreboard + monitor + agent + env test\n:tags: uvm uvm-scoreboards\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`define PATTERN 2\n\ninterface input_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, data);\nendinterface\n\ninterface output_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, output data);\nendinterface\n\nmodule dut(input_if.port in, output_if.port out);\n    always @(posedge in.clk)\n        out.data <= in.data;\nendmodule\n\nclass packet_out extends uvm_sequence_item;\n    logic [7:0] data;\n\n    `uvm_object_utils_begin(packet_out)\n        `uvm_field_int(data, UVM_ALL_ON|UVM_HEX)\n    `uvm_object_utils_end\n\n    function new(string name=\"packet_out\");\n        super.new(name);\n    endfunction: new\nendclass\n\nclass monitor extends uvm_monitor;\n    `uvm_component_utils(monitor)\n    virtual output_if  vif;\n    packet_out packet;\n\n    uvm_analysis_port #(packet_out) item_collected_port;\n\n    function new(string name, uvm_component parent);\n        super.new(name, parent);\n        item_collected_port = new (\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        packet = packet_out::type_id::create(\"packet\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual output_if)::read_by_name(\n          \"env\", \"output_if\", vif));\n    endfunction\n\n    virtual task run_phase(uvm_phase phase);\n        super.run_phase(phase);\n        fork\n            collect_transactions(phase);\n        join\n    endtask\n\n    virtual task collect_transactions(uvm_phase phase);\n        forever begin\n            repeat(2) @(posedge vif.clk);\n            packet.data = vif.data;\n            item_collected_port.write(packet);\n        end\n    endtask\nendclass\n\nclass agent_passive extends uvm_agent;\n    monitor mon;\n\n    uvm_analysis_port #(packet_out) item_collected_port;\n    `uvm_component_utils(agent_passive)\n\n    function new(string name = \"agent_passive\", uvm_component parent = null);\n        super.new(name, parent);\n        item_collected_port = new(\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        mon = monitor::type_id::create(\"mon_out\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        mon.item_collected_port.connect(item_collected_port);\n    endfunction\nendclass\n\nclass comparator #(type T = packet_out) extends uvm_scoreboard;\n    typedef comparator #(T) this_type;\n    `uvm_component_param_utils(this_type)\n    int match, mismatch;\n\n    const static string type_name = \"comparator #(T)\";\n\n    uvm_analysis_imp #(T, this_type) from_dut;\n\n    typedef uvm_built_in_converter #( T ) convert;\n\n    event end_of_simulation;\n\n    function new(string name, uvm_component parent);\n        super.new(name, parent);\n        from_dut = new(\"from_dut\", this);\n        match = 0;\n        mismatch = 0;\n    endfunction\n\n    virtual function string get_type_name();\n        return type_name;\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        @(end_of_simulation);\n        phase.drop_objection(this);\n    endtask\n\n    virtual function void write(T rec);\n        if(rec.data == `PATTERN) begin\n          `uvm_info(\"RESULT\", $sformatf(\"Comparator match %d == %d\", rec.data, `PATTERN), UVM_LOW);\n          match++;\n        end\n        else begin\n          `uvm_error(\"RESULT\", $sformatf(\"Comparator mismatch %d != %d\", rec.data, `PATTERN));\n          mismatch++;\n        end\n        -> end_of_simulation;\n  endfunction\nendclass\n\nclass env extends uvm_env;\n    agent_passive   agent;\n    comparator #(packet_out) comp;  \n    virtual input_if vif;\n\n    `uvm_component_utils(env)\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        agent = agent_passive::type_id::create(\"agent\", this);\n        comp = comparator#(packet_out)::type_id::create(\"comp\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n          get_full_name(), \"input_if\", vif));\n        agent.item_collected_port.connect(comp.from_dut);\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        `uvm_info(\"RESULT\", $sformatf(\"Writing %0d to input interface\", `PATTERN), UVM_LOW);\n        vif.data <= `PATTERN;\n    endtask\n\n    virtual function void report_phase(uvm_phase phase);\n        super.report_phase(phase);\n    endfunction\nendclass\n\nmodule top;\n    logic clk;\n    env environment;\n\n    input_if in(clk);\n    output_if out(clk);\n    dut d(in, out);\n\n    always #5 clk = !clk;\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual input_if)::set(\"env\", \"input_if\", in);\n        uvm_resource_db#(virtual output_if)::set(\"env\",  \"output_if\", out);\n        clk = 0;\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_scoreboard_monitor_env.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_scoreboard_monitor_env\n:description: uvm scoreboard + monitor + env test\n:tags: uvm uvm-scoreboards\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\n`define PATTERN 2\n\ninterface input_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, data);\nendinterface\n\ninterface output_if(input clk);\n    logic [7:0] data;\n    modport port(input clk, output data);\nendinterface\n\nmodule dut(input_if.port in, output_if.port out);\n    always @(posedge in.clk)\n        out.data <= in.data;\nendmodule\n\nclass packet_out extends uvm_sequence_item;\n    logic [7:0] data;\n\n    `uvm_object_utils_begin(packet_out)\n        `uvm_field_int(data, UVM_ALL_ON|UVM_HEX)\n    `uvm_object_utils_end\n\n    function new(string name=\"packet_out\");\n        super.new(name);\n    endfunction: new\nendclass\n\nclass monitor extends uvm_monitor;\n    `uvm_component_utils(monitor)\n    virtual output_if  vif;\n    packet_out packet;\n\n    uvm_analysis_port #(packet_out) item_collected_port;\n\n    function new(string name, uvm_component parent);\n        super.new(name, parent);\n        item_collected_port = new (\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        packet = packet_out::type_id::create(\"packet\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual output_if)::read_by_name(\n          \"env\", \"output_if\", vif));\n    endfunction\n\n    virtual task run_phase(uvm_phase phase);\n        super.run_phase(phase);\n        fork\n            collect_transactions(phase);\n        join\n    endtask\n\n    virtual task collect_transactions(uvm_phase phase);\n        forever begin\n            repeat(2) @(posedge vif.clk);\n            packet.data = vif.data;\n            item_collected_port.write(packet);\n        end\n    endtask\nendclass\n\nclass comparator #(type T = packet_out) extends uvm_scoreboard;\n    typedef comparator #(T) this_type;\n    `uvm_component_param_utils(this_type)\n    int match, mismatch;\n\n    const static string type_name = \"comparator #(T)\";\n\n    uvm_analysis_imp #(T, this_type) from_dut;\n\n    typedef uvm_built_in_converter #( T ) convert;\n\n    event end_of_simulation;\n\n    function new(string name, uvm_component parent);\n        super.new(name, parent);\n        from_dut = new(\"from_dut\", this);\n        match = 0;\n        mismatch = 0;\n    endfunction\n\n    virtual function string get_type_name();\n        return type_name;\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        @(end_of_simulation);\n        phase.drop_objection(this);\n    endtask\n\n    virtual function void write(T rec);\n        if(rec.data == `PATTERN) begin\n          `uvm_info(\"RESULT\", $sformatf(\"Comparator match %d == %d\", rec.data, `PATTERN), UVM_LOW);\n          match++;\n        end\n        else begin\n          `uvm_error(\"RESULT\", $sformatf(\"Comparator mismatch %d != %d\", rec.data, `PATTERN));\n          mismatch++;\n        end\n        -> end_of_simulation;\n  endfunction\nendclass\n\nclass env extends uvm_env;\n    monitor mon;\n    comparator #(packet_out) comp;  \n    virtual input_if vif;\n\n    `uvm_component_utils(env)\n\n    uvm_analysis_port #(packet_out) item_collected_port;\n\n    function new(string name, uvm_component parent = null);\n        super.new(name, parent);\n        item_collected_port = new(\"item_collected_port\", this);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n        comp = comparator#(packet_out)::type_id::create(\"comp\", this);\n        mon = monitor::type_id::create(\"mon_out\", this);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert(uvm_resource_db#(virtual input_if)::read_by_name(\n          get_full_name(), \"input_if\", vif));\n        item_collected_port.connect(comp.from_dut);\n        mon.item_collected_port.connect(item_collected_port);\n    endfunction\n\n    virtual function void end_of_elaboration_phase(uvm_phase phase);\n        super.end_of_elaboration_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        `uvm_info(\"RESULT\", $sformatf(\"Writing %0d to input interface\", `PATTERN), UVM_LOW);\n        vif.data <= `PATTERN;\n    endtask\n\n    virtual function void report_phase(uvm_phase phase);\n        super.report_phase(phase);\n    endfunction\nendclass\n\nmodule top;\n    logic clk;\n    env environment;\n\n    input_if in(clk);\n    output_if out(clk);\n    dut d(in, out);\n\n    always #5 clk = !clk;\n\n    initial begin\n        environment = new(\"env\");\n        uvm_resource_db#(virtual input_if)::set(\"env\", \"input_if\", in);\n        uvm_resource_db#(virtual output_if)::set(\"env\",  \"output_if\", out);\n        clk = 0;\n        run_test();\n    end\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_sequence.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_sequence\n:description: uvm_sequence test\n:tags: uvm uvm-classes\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass C extends uvm_sequence;\n    function new(string name);\n        super.new(name);\n    endfunction\n\n    virtual task pre_body();\n        `uvm_info (get_type_name(), \"pre_body()\", UVM_LOW)\n    endtask\n   \n    virtual task pre_do(bit is_item);\n        `uvm_info (get_type_name(), \"pre_do()\", UVM_LOW)\n    endtask\n   \n    virtual function void mid_do(uvm_sequence_item this_item);\n        `uvm_info (get_type_name(), \"mid_do()\", UVM_LOW)\n    endfunction\n   \n    virtual task body();\n        `uvm_info (get_type_name(), \"body()\", UVM_LOW)\n    endtask\n   \n    virtual function void post_do(uvm_sequence_item this_item);\n        `uvm_info (get_type_name(), \"post_do()\", UVM_LOW)\n    endfunction\n   \n    virtual task post_body();\n        `uvm_info (get_type_name(), \"post_body()\", UVM_LOW)\n    endtask\nendclass\n\nmodule top;\n\tC obj;\n\tinitial begin\n\t\tobj = new(\"C\");\n\tend\nendmodule\n"
  },
  {
    "path": "tests/testbenches/uvm_test_run_test.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_test_run_test\n:description: test if uvm_test instance can be called by name\n:tags: uvm uvm-classes\n:type: simulation elaboration parsing\n:timeout: 300\n:unsynthesizable: 1\n*/\n\nimport uvm_pkg::*;\n`include \"uvm_macros.svh\"\n\nclass simple_test extends uvm_test;\n    `uvm_component_utils(simple_test)\n\n    function new(string name, uvm_component parent = null);\n      super.new(name, parent);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n    endfunction\n\n    virtual function void build_phase(uvm_phase phase);\n        super.build_phase(phase);\n    endfunction\n\n    task run_phase(uvm_phase phase);\n        phase.raise_objection(this);\n        `uvm_info(\"RESULT\", \"SUCCESS, simple_test called\", UVM_LOW);\n        phase.drop_objection(this);\n    endtask\nendclass\n\nmodule top;\n    initial begin\n        run_test(\"simple_test\");\n    end\nendmodule\n"
  },
  {
    "path": "tests/uvm/uvm_files.sv",
    "content": "// Copyright (C) 2019-2021  The SymbiFlow Authors.\n//\n// Use of this source code is governed by a ISC-style\n// license that can be found in the LICENSE file or at\n// https://opensource.org/licenses/ISC\n//\n// SPDX-License-Identifier: ISC\n\n\n/*\n:name: uvm_files\n:description: basic UVM test\n:tags: uvm\n:timeout: 300\n:unsynthesizable: 1\n*/\n\n"
  },
  {
    "path": "tools/BaseRunner.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport psutil\nimport resource\nimport shutil\nimport signal\nimport subprocess\nimport os\nimport re\n\n\ndef kill_child_processes(parent_pid, sig=signal.SIGKILL):\n    try:\n        parent = psutil.Process(parent_pid)\n    except psutil.NoSuchProcess:\n        return\n    children = parent.children(recursive=True)\n    for process in children:\n        process.send_signal(sig)\n\n\nclass BaseRunner:\n    \"\"\"Common base class shared by all runners\n    Each runner must either implement prepare_run_cb\n    or override the run method.\n\n    prepare_run_cb is responsible for generating command to run\n    and preparing the command working directory if required by the tool.\n\n    Runners must be located in tools/runners subdirectory\n    to be detected and launched by the Makefile.\n    \"\"\"\n    def __init__(\n            self,\n            name,\n            executable=None,\n            supported_features={'preprocessing', 'parsing', 'elaboration'}):\n        \"\"\"Base runner class constructor\n        Arguments:\n        name -- runner name.\n        executable -- name of an executable used by the particular runner\n        can be omitted if default can_run method isn't used.\n        supported_features -- list of supported test types\n        \"\"\"\n        self.name = name\n        self.executable = executable\n        self.supported_features = supported_features\n        self.allowed_extensions = ['.v', '.sv', '.vh', '.svh']\n\n        self.url = \"https://github.com/symbiflow/sv-tests\"\n        self.submodule = \"\"\n\n    def get_mode(self, params):\n        \"\"\"Determine correct run mode or return None when incompatible\n        \"\"\"\n        test_features = params['type'].split()\n        compatible_runners = params['compatible-runners'].split()\n\n        if \"all\" not in compatible_runners:\n            if self.name not in compatible_runners:\n                return None\n\n        # select the first mode from the list that matches both the runner and\n        # the test\n        modes_sorted = [\n            'simulation', 'simulation_without_run', 'elaboration', 'parsing',\n            'preprocessing'\n        ]\n\n        for m in modes_sorted:\n            if m in test_features and m in self.supported_features:\n                return m\n\n        return None\n\n    def run(self, tmp_dir, params):\n        \"\"\"Run the provided test case\n        This method is called by the main runner script (tools/runner).\n\n        Arguments:\n        tmp_dir -- temporary directory created for this test run.\n        params -- dictionary with all metadata from the test file.\n                  All keys are used without colons, ie. :tags: becomes tags.\n\n        Returns a tuple containing command execution log, return code,\n        user time, system time and ram usage\n        \"\"\"\n        result = self.run_subprocess(tmp_dir, params)\n\n        usage = resource.getrusage(resource.RUSAGE_CHILDREN)\n        profiling_data = (usage.ru_utime, usage.ru_stime, usage.ru_maxrss)\n\n        return result + profiling_data\n\n    def run_subprocess(self, tmp_dir, params):\n        \"\"\" Run the test case's subprocess\n\n        This method is called by the run method and is expected to execute the\n        command prepared in `self.cmd`. Subclasses may choose to override this\n        in order to intercept the execution of the subprocess or inject custom\n        return codes.\n\n        Arguments are the same as for the run method.\n\n        Returns a tuple containing command execution log and return code.\n        \"\"\"\n        self.prepare_run_cb(tmp_dir, params)\n\n        proc = subprocess.Popen(\n            self.cmd,\n            cwd=tmp_dir,\n            stdout=subprocess.PIPE,\n            stderr=subprocess.STDOUT)\n\n        timeout = int(params['timeout'])\n        if 'DISABLE_TEST_TIMEOUTS' in os.environ:\n            timeout = None\n        else:\n            try:\n                timeout = int(os.environ['OVERRIDE_TEST_TIMEOUTS'])\n            except KeyError:\n                # continue with timeout from params\n                pass\n            except ValueError:\n                return (\"Invalid OVERRIDE_TEST_TIMEOUTS value\", 1)\n\n        try:\n            log, _ = proc.communicate(timeout=timeout)\n            returncode = proc.returncode\n        except subprocess.TimeoutExpired:\n            kill_child_processes(proc.pid)\n            proc.kill()\n            proc.communicate()\n            log = (\"Timeout: > \" + str(timeout) + \"s\\n\").encode('utf-8')\n            returncode = 71  # 71meout :) - something easy to grep for\n\n        invocation_log = \" \".join(self.cmd) + \"\\n\"\n\n        return (\n            invocation_log + self.transform_log(log.decode('utf-8', 'ignore')),\n            returncode)\n\n    def is_success_returncode(self, rc, params):\n        \"\"\" Returns a boolean if the given returncode is considered a success.\n\n        This function determines if the tool was running successfully. Tools\n        might return more rich return codes, so not all non-zero codes might\n        mean failure.\n        \"\"\"\n        return rc == 0\n\n    def transform_log(self, output):\n        \"\"\" Post-process the output log\n\n        Subclasses may choose to override this in order to transform the output\n        of the command.\n        \"\"\"\n        return output\n\n    def can_run(self):\n        \"\"\"Check if runner can be used\n        This method is called by the main runner script (tools/runner) as\n        a sanity check to verify that tool used by the runner is properly\n        installed.\n\n        Returns True when tool is installed and can be used, False otherwise.\n        \"\"\"\n        return shutil.which(self.executable) is not None\n\n    def get_version_cmd(self):\n        \"\"\" Get version command\n\n        Returns a list containing the command and arguments needed to get the\n                version.\n        \"\"\"\n\n        # assume sane defaults\n        return [self.executable, \"--version\"]\n\n    def get_version(self):\n        \"\"\"Attempt to get the version of the tool\n\n        Returns a version string\n        \"\"\"\n\n        try:\n            cmd = self.get_version_cmd()\n\n            proc = subprocess.Popen(\n                cmd, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)\n\n            log, _ = proc.communicate()\n\n            if proc.returncode != 0:\n                return self.name\n\n            return log.decode('utf-8')\n        except (TypeError, NameError, OSError):\n            return self.name\n\n    def get_commit(self):\n        \"\"\"Attempt to get the commit hash of the tool. The result is based on\n        the latest commit of its corresponding sumbodule.\n\n        Returns a hash string\n        \"\"\"\n\n        try:\n            path = \"HEAD\"\n            if self.submodule:\n                path += \":\" + self.submodule\n\n            cmd = [\"git\", \"rev-parse\", path]\n\n            proc = subprocess.Popen(\n                cmd, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)\n\n            log, _ = proc.communicate()\n\n            if proc.returncode != 0:\n                return \"HEAD\"\n\n            return log.decode('utf-8').strip()\n        except (TypeError, NameError, OSError):\n            return \"HEAD\"\n\n    def get_url(self):\n        \"\"\"Get the URL to the homepage of the runner\n\n        Returns a string with the URL\n        \"\"\"\n\n        return self.url\n\n    def get_top_module_or_guess(self, params):\n        \"\"\" Get the top-level module from the params, or guess it\n        \"\"\"\n        return params['top_module'] or self.guess_top_module(params)\n\n    def guess_top_module(self, params):\n        \"\"\" Guess the top-level module\n\n        If the params do not contain a top-level module, check if there is a\n        module called \"top\". If not, guess the top-level module by grepping\n        for the first module in the first file. This works for most tests since\n        most follow the implied naming convention.\n        \"\"\"\n        regex = re.compile(r'module\\s+(\\w+)\\s*[#(;]')\n        for fn in params['files']:\n            with open(fn) as f:\n                try:\n                    modules = regex.findall(f.read())\n                except UnicodeDecodeError:\n                    continue\n                if modules:\n                    if \"top\" in modules:\n                        return \"top\"\n                    else:\n                        modules[0]\n        return None\n"
  },
  {
    "path": "tools/check-runners",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\nimport argparse\nimport logging\n\nfrom importlib import import_module\n\nparser = argparse.ArgumentParser()\n\nparser.add_argument(\"runners\", metavar='runner', type=str, nargs='+')\nparser.add_argument(\"--filter\", type=str, nargs='*')\n\nargs = parser.parse_args()\nlogger = logging.getLogger()\n\nrunner_obj = None\n\nrunners_ok = []\n\nif 'RUNNERS_DIR' in os.environ:\n    sys.path.insert(1, os.path.abspath(os.environ['RUNNERS_DIR']))\n\nif args.filter is not None:\n    runners = set(args.runners) & set(args.filter)\nelse:\n    runners = set(args.runners)\n\nrunners = list(sorted(runners))\n\nfor runner in runners:\n    module = import_module(runner)\n    runner_cls = getattr(module, runner)\n    runner_obj = runner_cls()\n\n    new_path = [\n        os.path.abspath(os.environ['OUT_DIR'] + \"/runners/bin/\"),\n        os.environ['PATH']\n    ]\n\n    os.environ['PATH'] = \":\".join(new_path)\n\n    if runner_obj.can_run():\n        print(runner)\n    else:\n        logger.debug('Runner {} not found'.format(runner))\n"
  },
  {
    "path": "tools/feature-analyzer",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport re\nimport os\nimport yaml\nimport glob\nimport argparse\n\nparser = argparse.ArgumentParser()\n\nparser.add_argument(\"-c\", \"--confdir\")\nparser.add_argument(\"-d\", \"--srcdir\")\nparser.add_argument(\"-f\", \"--files\", nargs=\"+\")\nparser.add_argument(\"-v\", \"--verbose\", action=\"store_true\")\n\nargs = parser.parse_args()\n\nfiles_using_tags = {}\nfound_keywords = {}\n\nkeywords = {}\n\nexts = ['*.v', '*.sv', '*.vh']\n\nfor f in glob.glob(os.path.join(args.confdir, '**', '*.yml'), recursive=True):\n    with open(f) as tag_file:\n        data = yaml.safe_load(tag_file)['tags']\n        for key in data:\n            try:\n                keywords[key].extend(data[key])\n            except KeyError:\n                keywords[key] = data[key]\n\nif args.files is not None:\n    files = args.files\nelse:\n    files = []\n    for ext in exts:\n        files.extend(\n            glob.glob(os.path.join(args.srcdir, '**', ext), recursive=True))\n\nfor f in files:\n    for tag in keywords:\n        try:\n            with open(os.path.realpath(f)) as src:\n                for line in src:\n                    for keyword in keywords[tag]:\n                        if re.search(re.escape(keyword), line) is not None:\n                            try:\n                                found_keywords[tag].add(keyword)\n                            except KeyError:\n                                found_keywords[tag] = {keyword}\n                            try:\n                                files_using_tags[tag].add(f)\n                            except KeyError:\n                                files_using_tags[tag] = {f}\n        except FileNotFoundError:\n            pass\n\nprint('Detected tags: {}'.format(files_using_tags.keys()))\n\nif args.verbose:\n    print('Found keywords:')\n    for tag in found_keywords:\n        print('{}: {}'.format(tag, found_keywords[tag]))\n    for tag in files_using_tags:\n        print(\n            'Keywords from \"{}\" were found in the following files:'.format(\n                tag))\n        for f in files_using_tags[tag]:\n            print(f)\n"
  },
  {
    "path": "tools/history-graph",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport io\nimport os\nimport csv\nimport sys\nimport jinja2\nimport datetime\nimport argparse\nimport binascii\n\nfrom git import Repo\nfrom random import randint\nfrom collections import defaultdict\n\nparser = argparse.ArgumentParser()\n\ndata = defaultdict(lambda: defaultdict(lambda: defaultdict(int)))\n\nparser.add_argument(\n    '-r',\n    '--results-dir',\n    help='Directory with the test results repository',\n    required=True)\n\nparser.add_argument(\n    '-n',\n    '--number-of-commits',\n    help='Number of commits in the history to process',\n    type=int,\n    default=120)\n\nparser.add_argument(\n    '--template',\n    help='Path to the html template',\n    default='conf/report/history-graph-template.html')\n\nparser.add_argument(\n    '-o',\n    '--out',\n    help='Path to the html file with the history graph',\n    default='out/report/history.html')\n\n# parse args\nargs = parser.parse_args()\n\n\ndef process_csv_reader(index, reader, data):\n    for r in reader:\n        key = 'pass' if r['Pass'] == 'True' else 'fail'\n        data[r['Tool']][index][key] += 1\n\n\ndef process_csv_from_file(index, csv_file_path, data):\n    with open(csv_file_path) as f:\n        reader = csv.DictReader(f)\n        process_csv_reader(index, reader, data)\n\n\ndef process_csv_from_commit(index, csv_file, data):\n    with io.BytesIO(csv_file.data_stream.read()) as f:\n        reader = csv.DictReader(io.StringIO(f.read().decode('utf-8')))\n        process_csv_reader(index, reader, data)\n\n\nrepo = Repo(args.results_dir)\nmain_hash = repo.head.object.hexsha\n\n# check if there is new (not yet committed) results file available\nchanged_files = [i.a_path for i in repo.index.diff(None)]\nappend_changed = 'report.csv' in changed_files\n\nif append_changed:\n    # process fewer history commits\n    args.number_of_commits -= 1\n\nfor i in range(args.number_of_commits - 1, -1, -1):\n    current_hash = f'{main_hash}~{i}'\n    commit = repo.commit(current_hash)\n    print(f'Processing {commit}')\n\n    date = datetime.datetime.fromtimestamp(commit.committed_date)\n\n    targetfile = commit.tree / 'report.csv'\n    process_csv_from_commit(date, targetfile, data)\n\nif append_changed:\n    date = datetime.datetime.now()\n    print('Processing locally modified results')\n    csv_path = os.path.join(args.results_dir, 'report.csv')\n    process_csv_from_file(date, csv_path, data)\n\ndatasets = defaultdict(list)\n\n# generate a set with all keys in case not all tools contain all keys\nall_keys = set()\nfor tool in data:\n    all_keys.update(set(data[tool].keys()))\n\nfor tool in data:\n    for index in sorted(list(all_keys)):\n        if index not in data[tool]:\n            # append 0% if the tool didn't run\n            datasets[tool].append(0)\n        else:\n            bad = data[tool][index]['fail']\n            good = data[tool][index]['pass']\n            percent = round(good * 100 / (good + bad), 2)\n            datasets[tool].append(percent)\n\n# convert lists to strings\nlabels = ', '.join(f'\"{x}\"' for x in sorted(list(all_keys)))\n\nfor tool in datasets:\n    datasets[tool] = ', '.join(str(x) for x in datasets[tool])\n\n# randomize colors\ncolors = dict()\nfor tool in datasets:\n    color = hex(binascii.crc32(tool.encode('utf-8')))[-6:]\n    colors[tool] = f'#{color:0<6.6}'\n\ntry:\n    with open(args.template) as f:\n        template = jinja2.Template(\n            f.read(), trim_blocks=True, lstrip_blocks=True)\nexcept Exception as e:\n    print(f'Unable to read template: {e}')\n\ntry:\n    with open(args.out, 'w') as f:\n        f.write(\n            template.render(labels=labels, datasets=datasets, colors=colors))\nexcept Exception as e:\n    print(f'Unable to generate history graph: {e}')\n"
  },
  {
    "path": "tools/logparser.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport re\n\n\ndef parseLog(log):\n    res = True\n    for line in log.split('\\n'):\n        pat = re.search(r':([a-z]+):(.*)', line.strip())\n        if pat:\n            if pat.group(1) == 'assert':\n                expr = pat.group(2)\n                try:\n                    if not eval(expr):\n                        res = False\n                except Exception:\n                    res = False\n    return res\n"
  },
  {
    "path": "tools/report_analyzer.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2021 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport argparse\nimport csv\nimport json\nimport sys\nimport pytablewriter\n\nrelevant_headers = [\"Tool\", \"TestName\", \"Pass\"]\n\n\ndef get_data(csv_path):\n    with open(csv_path, newline=\"\") as csv_file:\n        report = list(csv.DictReader(csv_file))\n        header = report[0].keys()\n\n        assert set(relevant_headers).issubset(\n            header), \"Lack of crucial headers in CSV report \" + csv_path\n\n        tools = set(row[\"Tool\"] for row in report)\n\n        sorted_report = {}\n        for tool in tools:\n            sorted_report[tool] = {}\n\n        for row in report:\n            sorted_report[row[\"Tool\"]][row[\"TestName\"]] = row[\"Pass\"]\n\n    return sorted_report\n\n\ndef check_tool(tool_reportA, tool_reportB, tool_name):\n    results = {\n        \"new_passes\": [],\n        \"new_failures\": [],\n        \"added\": [],\n        \"removed\": [],\n        \"summary\": {},\n    }\n\n    testsA = set(tool_reportA.keys())\n    testsB = set(tool_reportB.keys())\n\n    tests_added = testsA.difference(testsB)\n    tests_removed = testsB.difference(testsA)\n\n    tests_comparable = testsA.intersection(testsB)\n\n    added_cnt = len(tests_added)\n    removed_cnt = len(tests_removed)\n    no_change_cnt = 0\n\n    for test in tests_comparable:\n        res = check_test(tool_reportA[test], tool_reportB[test])\n        if (res == -1):\n            results[\"new_failures\"].append(test)\n        elif (res == 1):\n            results[\"new_passes\"].append(test)\n        else:\n            no_change_cnt += 1\n\n    fail_cnt = len(results[\"new_failures\"])\n    pass_cnt = len(results[\"new_passes\"])\n\n    for added_test in tests_added:\n        results[\"added\"].append(added_test)\n\n    for removed_test in tests_removed:\n        results[\"removed\"].append(removed_test)\n\n    results[\"summary\"][\"new_failures\"] = fail_cnt\n    results[\"summary\"][\"new_passes\"] = pass_cnt\n    results[\"summary\"][\"added\"] = added_cnt\n    results[\"summary\"][\"removed\"] = removed_cnt\n    results[\"summary\"][\"not_affected\"] = no_change_cnt\n\n    return results\n\n\ndef check_test(test_reportA, test_reportB):\n    if (test_reportA == test_reportB):\n        return 0\n    elif (test_reportA == \"True\" and test_reportB == \"False\"):\n        return 1\n    elif (test_reportA == \"False\" and test_reportB == \"True\"):\n        return -1\n    else:\n        raise ValueError(\n            \"unknown test result occured: A -> \" + test_reportA + \" B -> \" +\n            test_reportB)\n\n\ndef check_reports(reportA, reportB):\n    summary = {\n        \"comparable_tools\": {},\n        \"added_tools\": [],\n        \"removed_tools\": [],\n    }\n\n    toolsA = set(reportA.keys())\n    toolsB = set(reportB.keys())\n    tools = toolsA.intersection(toolsB)\n\n    if (toolsA != toolsB):\n        tools_added = toolsA.difference(toolsB)\n        tools_removed = toolsB.difference(toolsA)\n        summary[\"added_tools\"] = list(tools_added)\n        summary[\"removed_tools\"] = list(tools_removed)\n\n    for tool in tools:\n        tool_results = check_tool(reportA[tool], reportB[tool], tool)\n        summary[\"comparable_tools\"][tool] = tool_results\n\n    return summary\n\n\ndef prepare_comment(summary, table_path):\n    tools = list(summary[\"comparable_tools\"].keys())\n    cols = list(summary[\"comparable_tools\"][tools[0]][\"summary\"].keys())\n    cols.insert(0, \"tool\")\n\n    matrix = []\n    for tool in tools:\n        vals = list(summary[\"comparable_tools\"][tool][\"summary\"].values())\n        vals.insert(0, tool)\n        matrix.append(vals)\n\n    writer = pytablewriter.MarkdownTableWriter()\n    writer.table_name = \"Changes In Tests\"\n    pretty_cols = [c.replace(\"_\", \" \").title() for c in cols]\n    writer.headers = pretty_cols\n    writer.value_matrix = matrix\n    writer.write_table()\n    with open(table_path, \"w\") as f:\n        writer.stream = f\n        writer.write_table()\n\n\ndef main():\n    parser = argparse.ArgumentParser()\n    parser.add_argument(\n        \"report_compare\",\n        help=\"csv report that will be compared with base report\")\n    parser.add_argument(\n        \"report_base\", help=\"csv report that will be a base of comparison\")\n    parser.add_argument(\n        \"-o\",\n        \"--output\",\n        dest=\"output_path\",\n        default=\"report_summary.json\",\n        help=\"path to output json file, defaults to \\\"report_summary.json\\\"\")\n    parser.add_argument(\n        \"-t\",\n        \"--table\",\n        dest=\"table_path\",\n        default=\"report_summary.md\",\n        help=\n        \"path to output md file with summary, defaults to \\\"report_summary.md\\\"\"\n    )\n    parser.add_argument(\n        \"-c\",\n        \"--changes\",\n        dest=\"changes_path\",\n        default=\"./out/report\",\n        help=\n        \"path to output csv file with names of test that changed status, defaults to \\\"./out/report\\\"\"\n    )\n    args = parser.parse_args()\n\n    reportA = get_data(args.report_compare)\n    reportB = get_data(args.report_base)\n\n    summary = check_reports(reportA, reportB)\n\n    with open(args.changes_path + \"/new_failures.csv\", \"w\") as csv_file:\n        writer = csv.writer(csv_file)\n        for tool in summary[\"comparable_tools\"]:\n            for test in summary[\"comparable_tools\"][tool][\"new_failures\"]:\n                writer.writerow([tool, test])\n    with open(args.changes_path + \"/new_passes.csv\", \"w\") as csv_file:\n        writer = csv.writer(csv_file)\n        for tool in summary[\"comparable_tools\"]:\n            for test in summary[\"comparable_tools\"][tool][\"new_passes\"]:\n                writer.writerow([tool, test])\n\n    prepare_comment(summary, args.table_path)\n\n    with open(args.output_path, \"w\") as json_file:\n        json.dump(summary, json_file, indent=4)\n\n\nif __name__ == \"__main__\":\n    main()\n"
  },
  {
    "path": "tools/runner",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport re\nimport sys\nimport json\nimport shutil\nimport time\nimport logging\nimport argparse\nimport tempfile\nfrom datetime import datetime\nfrom importlib import import_module\nfrom logparser import parseLog\n\nparser = argparse.ArgumentParser()\n\nparser.add_argument(\"-r\", \"--runner\", required=True)\n\naction = parser.add_mutually_exclusive_group(required=True)\naction.add_argument(\"-t\", \"--test\")\naction.add_argument(\"-v\", \"--version\", action=\"store_true\")\naction.add_argument(\"-u\", \"--url\", action=\"store_true\")\n\nparser.add_argument(\"-o\", \"--out\", required=True)\nparser.add_argument(\"-k\", \"--keep-tmp\", action=\"store_true\")\n\nparser.add_argument(\n    \"-q\",\n    \"--quiet\",\n    dest='verbosity',\n    action='store_const',\n    const=logging.ERROR,\n    default=logging.DEBUG)\n\nargs = parser.parse_args()\n\n# setup logger\nlogger = logging.getLogger()\nlogger.setLevel(args.verbosity)\n\nch = logging.StreamHandler()\nch.setFormatter(logging.Formatter('%(levelname)-8s| %(message)s'))\nlogger.addHandler(ch)\n\nrunner_obj = None\n\nif 'RUNNERS_DIR' in os.environ:\n    sys.path.insert(1, os.path.abspath(os.environ['RUNNERS_DIR']))\n\ntry:\n    module = import_module(args.runner)\n    runner_cls = getattr(module, args.runner)\n    runner_obj = runner_cls()\nexcept Exception as e:\n    logger.error(\"Unable to load runner module: {}\".format(str(e)))\n    sys.exit(1)\n\ndirs = {}\n\ntry:\n    dirs['out'] = os.environ['OUT_DIR']\n    dirs['conf'] = os.environ['CONF_DIR']\n    dirs['tests'] = os.environ['TESTS_DIR']\n    dirs['runners'] = os.environ['RUNNERS_DIR']\n    dirs['third_party'] = os.environ['THIRD_PARTY_DIR']\nexcept KeyError as e:\n    logger.error(\"Required environment variables missing: {}\".format(str(e)))\n    sys.exit(1)\n\nnew_path = [os.path.abspath(dirs['out'] + \"/runners/bin/\"), os.environ['PATH']]\n\nos.environ['PATH'] = \":\".join(new_path)\n\nrunner = os.path.abspath(os.path.join(dirs['runners'], args.runner))\nout = os.path.abspath(args.out)\n\nos.makedirs(os.path.dirname(out), exist_ok=True)\n\nif args.version:\n    version = runner_obj.get_version()\n    with open(out, \"w\") as f:\n        f.write(version)\n\n    sys.exit(0)\n\nif args.url:\n    url = runner_obj.get_url()\n    with open(out, \"w\") as f:\n        f.write(url)\n\n    sys.exit(0)\n\nlibs_json = os.path.join(dirs['conf'], 'runners', 'libs.json')\n\nwith open(libs_json, 'r') as jf:\n    try:\n        libs = json.load(jf)\n    except JSONDecodeError as e:\n        libs = {}\n\ntest = os.path.abspath(os.path.join(dirs['tests'], args.test))\n\n# In addition to these fixed names, \"runner_<tool>_flags\" is allowed\nsupported_test_params = [\n    \"name\", \"tags\", \"description\", \"files\", \"incdirs\", \"top_module\", \"timeout\",\n    \"type\", \"should_fail\", \"should_fail_because\", \"defines\",\n    \"compatible-runners\", \"unsynthesizable\", \"results_group\"\n]\n\ntest_params = {}\n\n# look for all supported params\ntry:\n    with open(test) as f:\n        for l in f:\n            param = re.search(r\"^:([a-zA-Z_-]+):\\s*(.+)\", l)\n\n            if param is None:\n                continue\n\n            param_name = param.group(1).lower()\n            param_value = param.group(2)\n\n            if param_name not in supported_test_params:\n                if not re.match(r'runner_.*_flags$', param_name):\n                    logger.warning(\n                        \"Unsupported test param found: {} - ignoring\".format(\n                            param_name))\n                    continue\n\n            test_params[param_name] = param_value\n\n            # check all items in the supported_test_params exists in the test_params.\n            if len(set(supported_test_params) - set(test_params.keys())) == 0:\n                # all supported parameters found\n                break\n\n        else:\n            # set default values for optional metadata entries\n            test_params.setdefault('name', test)\n            test_params.setdefault('files', test)\n            test_params.setdefault('incdirs', os.path.dirname(test))\n            test_params.setdefault('top_module', '')\n            test_params.setdefault('timeout', \"30\")\n            test_params.setdefault('type', 'parsing elaboration')\n            test_params.setdefault(\n                'should_fail',\n                (\"0\", \"1\")[\"should_fail_because\" in test_params.keys()])\n            test_params.setdefault('should_fail_because', \"\")\n            test_params.setdefault('defines', \"\")\n            test_params.setdefault('compatible-runners', \"all\")\n            test_params.setdefault('unsynthesizable', '0')\n            test_params.setdefault('results_group', \"\")\n\n            if len(set(supported_test_params) - set(test_params.keys())) != 0:\n                missing = list(\n                    set(supported_test_params) - set(test_params.keys()))\n                logger.error(\n                    \"Required parameters missing ({}) in {}\".format(\n                        \", \".join(missing), args.test))\n                sys.exit(1)\nexcept Exception as e:\n    logger.error(\"Unable to parse test file: {}\".format(str(e)))\n    sys.exit(1)\n\n# if the string is not empty and should_fail is 0\n# then set it to 1 and issue a warning\nif test_params[\"should_fail\"] == \"0\" and test_params[\"should_fail_because\"]:\n    test_params[\"should_fail\"] = \"1\"\n    logger.warning(\"contradictory params should_fail, should_fail_because.\")\n# if string is empty and should_fail is 1\nelif test_params[\n        \"should_fail\"] == \"1\" and not test_params[\"should_fail_because\"]:\n    logger.warning(\n        \"should_fail tag should be replaced with should_fail_because.\")\n\ntest_params['files'] = test_params['files'].split()\ntest_params['incdirs'] = list(\n    map(\n        lambda x: os.path.abspath(os.path.join(dirs['tests'], x)),\n        test_params['incdirs'].split()))\n\ntest_params['mode'] = runner_obj.get_mode(test_params)\nif test_params['mode'] is None:\n    logger.info(\"Skipping {}/{}\".format(args.runner, args.test))\n    with open(out, \"w\") as f:\n        f.write(\"\")  # runner does not support mode; just mark file as handled.\n\n    sys.exit(0)\n\nfor key in libs.keys():\n    if key in test_params['tags']:\n        test_params['files'] = [\n            os.path.abspath(os.path.join(dirs['third_party'], p))\n            for p in libs[key]['files']\n        ] + test_params['files']\n        test_params['incdirs'] = [\n            os.path.abspath(os.path.join(dirs['third_party'], p))\n            for p in libs[key]['incdirs']\n        ] + test_params['incdirs']\n\ntest_params['defines'] = test_params['defines'].split()\n\n# Filter test files based on what the runner claims to support.\nfiltered_files = []\nfor f in test_params['files']:\n    if os.path.splitext(f)[1] in runner_obj.allowed_extensions:\n        filtered_files.append(f)\n    else:\n        logger.info(\n            \"Skipping '{}' with '{}' due to unsupported extension\".format(\n                f, args.runner))\n\ntest_params['files'] = filtered_files\n\n# Keep it simple to avoid problems with escaping.\nRESULTS_GROUP_PARAM_VALIDATOR_RE = re.compile(r\"[a-z0-9_]*\")\nif not RESULTS_GROUP_PARAM_VALIDATOR_RE.fullmatch(\n        test_params[\"results_group\"]):\n    group = test_params[\"results_group\"]\n    fixed_group = re.sub(\"[^a-z0-9_]\", \"_\", group.lower())\n    logger.warning(\n        f\"results_group '{group}' does not match pattern '[a-z0-9_]*'. Replacing with '{fixed_group}'.\"\n    )\n    test_params['results_group'] = fixed_group\n\ntry:\n    tmp_parent = os.path.join(os.path.abspath(dirs['out']), \"tmp\")\n    os.makedirs(tmp_parent, exist_ok=True)\n\n    tmp_dir = tempfile.mkdtemp(dir=tmp_parent)\nexcept (PermissionError, FileExistsError) as e:\n    logger.error(\n        \"Unable to create a temporary directory for test: {}\".format(str(e)))\n    sys.exit(1)\n\ntry:\n    logger.info(\"Running {}/{}\".format(args.runner, args.test))\n\n    start_time = time.time()\n    output, rc, user_time, system_time, ram_usage = runner_obj.run(\n        tmp_dir, test_params)\n    end_time = time.time()\n\n    tool_success = runner_obj.is_success_returncode(rc, test_params)\n    test_params['rc'] = rc\n    test_params['tool_success'] = \"1\" if tool_success else \"0\"\n    test_params['runner'] = runner_obj.name\n    test_params['runner_url'] = runner_obj.url\n    test_params['time_elapsed'] = end_time - start_time\n    test_params['user_time'] = user_time\n    test_params['system_time'] = system_time\n    test_params['ram_usage'] = ram_usage\n    test_params['date_completed'] = datetime.now().strftime(\n        \"%Y-%m-%d %H:%M:%S\")\n\n    tool_should_fail = test_params[\"should_fail\"] == \"1\"\n    tool_failed = not tool_success\n    tool_crashed = rc >= 126\n\n    test_passed = not tool_crashed and tool_should_fail == tool_failed\n\n    if test_passed and test_params['mode'] == 'simulation':\n        test_passed = parseLog(output)\n\n    if test_passed:\n        logger.info(\"PASS: {}/{}\".format(args.runner, args.test))\n    else:\n        logger.warning(\"FAIL: {}/{}\".format(args.runner, args.test))\n\n    os.makedirs(os.path.dirname(out), exist_ok=True)\n\n    test_params['files'] = ' '.join(test_params['files'])\n    test_params['incdirs'] = ' '.join(test_params['incdirs'])\n    test_params['defines'] = ' '.join(test_params['defines'])\n\n    with open(out, \"w\") as log:\n        # start by writing params\n        for p in test_params:\n            log.write(\"{}: {}\\n\".format(p, test_params[p]))\n        log.write(\"\\n\")\n        log.write(output)\nexcept Exception as e:\n    logger.error(\n        \"Unable to test {} using {}: {}\".format(\n            args.runner, args.test, str(e)))\n    sys.exit(1)\nfinally:\n    if args.keep_tmp:\n        logger.info(\n            \"{}/{} work directory was left for inspection {}\".format(\n                args.runner, args.test, tmp_dir))\n    else:\n        shutil.rmtree(tmp_dir)\n"
  },
  {
    "path": "tools/runners/Icarus.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020-2021 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom BaseRunner import BaseRunner\nimport os\n\n\nclass Icarus(BaseRunner):\n    def __init__(self):\n        super().__init__(\n            'icarus', 'iverilog', {\n                'preprocessing', 'parsing', 'elaboration', 'simulation',\n                'simulation_without_run'\n            })\n\n        self.submodule = \"third_party/tools/icarus\"\n        self.url = f\"https://github.com/steveicarus/iverilog/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        ofile = 'iverilog.out'\n\n        self.cmd = [self.executable, '-g2012']\n\n        self.cmd += ['-o', ofile]\n\n        if params['mode'] == 'preprocessing':\n            self.cmd.append('-E')\n        elif params['mode'] == 'parsing':\n            self.cmd += ['-t', 'null']\n\n        if params['top_module'] != '':\n            self.cmd += ['-s', params['top_module']]\n\n        for incdir in params['incdirs']:\n            self.cmd.append('-I' + incdir)\n\n        for define in params['defines']:\n            self.cmd.append('-D' + define)\n\n        self.cmd += params['files']\n\n        if params['mode'] != 'simulation':\n            return\n\n        # For simulation a wrapper script is created\n        scr = os.path.join(tmp_dir, 'scr.sh')\n        with open(scr, 'w') as f:\n            f.write('set -x\\n')\n            f.write('{0} \"$@\" || exit $?\\n'.format(self.cmd[0]))\n            f.write(f'./iverilog.out\\n')\n        self.cmd = ['sh', 'scr.sh'] + self.cmd[1:]\n\n    def get_version_cmd(self):\n        return [self.executable, \"-V\"]\n\n    def get_version(self):\n        version = super().get_version()\n\n        # The full version is the 4th word to the end of 1st line\n        version = version.splitlines()[0].split()[3:]\n\n        version.insert(0, self.name)\n\n        return \" \".join(version)\n"
  },
  {
    "path": "tools/runners/Odin.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom BaseRunner import BaseRunner\n\n\nclass Odin(BaseRunner):\n    def __init__(self):\n        super().__init__(\"odin\", \"odin_II\", {\"preprocessing\", \"parsing\"})\n\n        self.submodule = \"third_party/tools/odin_ii\"\n        self.url = f\"https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n\n        self.cmd = [self.executable, '--permissive', '-o odin.blif', '-V']\n\n        # odin doesn't seem to support include directories\n        # and thus only list of files is provided to it\n\n        if params['top_module'] != '':\n            self.cmd.append('--top_module ' + params['top_module'])\n\n        self.cmd += params['files']\n\n    def get_version_cmd(self):\n        # get it from the help\n        return [self.executable, \"-h\"]\n\n    def get_version(self):\n        version = super().get_version()\n\n        # The version is the 6th word in the 2nd line\n        version = version.splitlines()[1].split()[5]\n\n        return \" \".join([self.name, version])\n"
  },
  {
    "path": "tools/runners/Slang.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom BaseRunner import BaseRunner\n\n\nclass Slang(BaseRunner):\n    def __init__(\n            self,\n            name=\"slang\",\n            supported_features={'preprocessing', 'parsing', 'elaboration'}):\n        super().__init__(\n            name,\n            executable=\"slang-driver\",\n            supported_features=supported_features)\n\n        self.submodule = \"third_party/tools/slang\"\n        self.url = f\"https://github.com/MikePopoloski/slang/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        mode = params['mode']\n\n        self.cmd = [self.executable]\n        if mode == 'preprocessing':\n            self.cmd += ['-E']\n        elif mode == \"parsing\":\n            self.cmd.append(\"--parse-only\")\n\n        # Some tests expect that all input files will be concatenated into\n        # a single compilation unit, so ask slang to do that.\n        self.cmd += ['--single-unit']\n\n        # Set a default timescale so we don't get errors about some\n        # modules not having one.\n        self.cmd += ['--timescale=1ns/1ns']\n\n        top = params['top_module'].strip()\n        if top:\n            self.cmd.append('--top=' + top)\n\n        for incdir in params['incdirs']:\n            self.cmd.extend(['-I', incdir])\n\n        for define in params['defines']:\n            self.cmd.extend(['-D', define])\n\n        # Some tests access array elements out of bounds. Make that not an error.\n        self.cmd.append(\"-Wno-error=index-oob\")\n        self.cmd.append(\"-Wno-error=range-oob\")\n        self.cmd.append(\"-Wno-error=range-width-oob\")\n\n        tags = params[\"tags\"]\n\n        # The Ariane and Ibex cores have duplicate definitions.\n        if \"ariane\" in tags or \"ibex\" in tags:\n            self.cmd.append(\"-Wno-duplicate-definition\")\n\n        # Ibex includes files that try to instantiate Xilinx-specific modules\n        if \"ibex\" in tags:\n            self.cmd.append(\"--ignore-unknown-modules\")\n\n        # The Ariane core has syntax errors with stream concat operators.\n        if \"ariane\" in tags:\n            self.cmd.append(\"--allow-self-determined-stream-concat\")\n\n        # black-parrot has syntax errors where variables are used before they are declared.\n        # This is being fixed upstream, but it might take a long time to make it to master\n        # so this works around the problem in the meantime.\n        if \"black-parrot\" in tags and mode != \"parsing\":\n            self.cmd.append(\"--allow-use-before-declare\")\n\n            # These tests simply cannot be elaborated because they target\n            # modules that have invalid parameter values for a top-level module,\n            # or have an invalid configuration that results in $fatal calls.\n            name = params[\"name\"]\n            if 'bp_lce' in name or 'bp_uce' or 'bp_multicore' in name:\n                self.cmd.append(\"--parse-only\")\n\n        # These cores use a non-standard extension to write to the same variable\n        # from multiple procedures.\n        if \"fx68k\" in tags:\n            self.cmd.append(\"--allow-dup-initial-drivers\")\n\n        self.cmd += params['files']\n\n    def get_version(self):\n        version = super().get_version()\n\n        return \" \".join([self.name, version.split()[2]])\n"
  },
  {
    "path": "tools/runners/Slang_parse.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom runners.Slang import Slang\n\n\nclass Slang_parse(Slang):\n    def __init__(self):\n        super().__init__(\n            \"slang-parse\", supported_features={'preprocessing', 'parsing'})\n"
  },
  {
    "path": "tools/runners/Surelog.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom BaseRunner import BaseRunner\nfrom distutils.util import strtobool\n\n\nclass Surelog(BaseRunner):\n    def __init__(self):\n        super().__init__(\"Surelog\", \"surelog\")\n\n        self.submodule = \"third_party/tools/Surelog\"\n        self.url = f\"https://github.com/chipsalliance/Surelog/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        self.cmd = [self.executable, '-nopython', '-parse']\n\n        if params['mode'] in [\"parsing\", \"preprocessing\"]:\n            self.cmd.append('-noelab')\n\n        # silence surelog\n        self.cmd.append(\"-nonote\")\n        self.cmd.append(\"-noinfo\")\n        self.cmd.append(\"-nowarning\")\n\n        # force sverilog mode for .v files\n        if \"black-parrot\" in params[\"tags\"]:\n            self.cmd.append('-sverilog')\n\n        if \"basejump\" in params[\"tags\"]:\n            self.cmd.append('-sverilog')\n\n        if \"ivtest\" in params[\"tags\"]:\n            self.cmd.append('-sverilog')\n\n        top = params['top_module'].strip()\n        if top:\n            self.cmd.append('--top-module ' + top)\n\n        # lowmem option\n        if \"black-parrot\" in params[\"tags\"]:\n            self.cmd.append('-lowmem')\n\n        for define in params['defines']:\n            self.cmd.append('-D' + define)\n\n        # regular options\n        for incdir in params['incdirs']:\n            self.cmd.append('-I' + incdir)\n\n        self.cmd += params['files']\n\n    def is_success_returncode(self, rc, params):\n        # We're only interested in\n        # syntax, fatal and errors.\n        return rc & 0x07 == 0\n"
  },
  {
    "path": "tools/runners/Sv2v_zachjs.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom BaseRunner import BaseRunner\n\n\nclass Sv2v_zachjs(BaseRunner):\n    def __init__(self):\n        super().__init__(\n            \"zachjs-sv2v\", \"zachjs-sv2v\",\n            {\"preprocessing\", \"parsing\", \"elaboration\"})\n\n        self.submodule = \"third_party/tools/zachjs-sv2v\"\n        self.url = f\"https://github.com/zachjs/sv2v/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        self.cmd = [self.executable]\n\n        for incdir in params['incdirs']:\n            self.cmd.append('-I' + incdir)\n\n        for define in params['defines']:\n            self.cmd.append('-D' + define)\n\n        self.cmd += params['files']\n\n    def get_version(self):\n        version = super().get_version()\n\n        # return it with our custom prefix and without the trailing newline\n        return \"zachjs-\" + version.rstrip()\n"
  },
  {
    "path": "tools/runners/SynligYosys.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\n\nfrom BaseRunner import BaseRunner\n\n\nclass SynligYosys(BaseRunner):\n    def __init__(self):\n        super().__init__(\n            \"yosys-synlig\", \"yosys-synlig\",\n            {\"preprocessing\", \"parsing\", \"elaboration\"})\n\n        self.submodule = \"third_party/tools/synlig\"\n        self.url = f\"https://github.com/chipsalliance/synlig/tree/{self.get_commit()}\"\n\n    def get_mode(self, params):\n        unsynthesizable = int(params['unsynthesizable'])\n        if unsynthesizable:\n            return None\n        return super().get_mode(params)\n\n    def prepare_run_cb(self, tmp_dir, params):\n        runner_scr = os.path.join(tmp_dir, \"scr.sh\")\n        yosys_scr = os.path.join(tmp_dir, \"yosys-script\")\n        mode = params['mode']\n\n        top = params['top_module'] or None\n\n        # generate yosys script\n        with open(yosys_scr, \"w\") as f:\n            f.write(\"plugin -i systemverilog\\n\")\n            f.write(\n                \"read_systemverilog -nopython -parse -sverilog -nonote -noinfo -nowarning -DSYNTHESIS\"\n            )\n\n            if mode != \"elaboration\":\n                f.write(\" -parse-only\")\n\n            if top is not None:\n                f.write(f' --top-module {top}')\n\n            if mode in [\"parsing\", \"preprocessing\"]:\n                f.write(' -noelab')\n\n            for i in params[\"incdirs\"]:\n                f.write(f\" -I{i}\")\n\n            for d in params[\"defines\"]:\n                f.write(f\" -D{d}\")\n\n            for fn in params[\"files\"]:\n                f.write(f\" {fn}\")\n\n            f.write(\"\\n\")\n\n            if mode == \"elaboration\":\n                # prep (without optimizations)\n                if top is not None:\n                    f.write(f\"hierarchy -top \\\\{top}\\n\")\n                else:\n                    f.write(\"hierarchy -auto-top\\n\")\n\n                f.write(\n                    \"proc\\n\"\n                    \"check\\n\"\n                    \"memory_dff\\n\"\n                    \"memory_collect\\n\"\n                    \"stat\\n\"\n                    \"check\\n\")\n\n        # generate runner script\n        with open(runner_scr, \"w\") as f:\n            f.write(\"set -e\\n\")\n            f.write(\"set -x\\n\")\n            f.write(f\"cat {yosys_scr}\\n\")\n            f.write(f\"{self.executable} -s {yosys_scr}\\n\")\n\n        self.cmd = [\"sh\", runner_scr]\n"
  },
  {
    "path": "tools/runners/Verible.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom BaseRunner import BaseRunner\n\n\nclass Verible(BaseRunner):\n    def __init__(self):\n        super().__init__(\"verible\", \"verible-verilog-syntax\", {\"parsing\"})\n\n        self.submodule = \"third_party/tools/verible\"\n        self.url = f\"https://github.com/chipsalliance/verible/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        self.cmd = [self.executable]\n\n        self.cmd += params['files']\n"
  },
  {
    "path": "tools/runners/VeribleExtractor.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom BaseRunner import BaseRunner\n\nimport os\nimport shlex\n\n\nclass VeribleExtractor(BaseRunner):\n    def __init__(self):\n        super().__init__(\n            \"verible_extractor\", \"verible-verilog-kythe-extractor\",\n            {\"parsing\"})\n\n        self.submodule = \"third_party/tools/verible\"\n        self.url = f\"https://github.com/google/verible/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        src_list_path = os.path.join(tmp_dir, \"src_list\")\n        script_path = os.path.join(tmp_dir, \"run.sh\")\n\n        with open(src_list_path, \"w\") as src_list:\n            files = [os.path.abspath(f) for f in params.get(\"files\", [])]\n            print(\"\\n\".join(files), file=src_list)\n\n        inc_dirs = \",\".join(params.get(\"incdirs\", []))\n\n        with open(script_path, \"w\") as script:\n            command = (\n                '{executable}'\n                ' --file_list_root \"/\"'\n                ' --include_dir_paths {inc_dirs}'\n                ' --file_list_path {src_list_path}').format(\n                    executable=self.executable,\n                    inc_dirs=shlex.quote(inc_dirs),\n                    src_list_path=shlex.quote(src_list_path))\n            s = (\n                'echo \"#\" {command_str}\\n'\n                'log=\"$( {command} 2>&1 1>/dev/null )\"\\n'\n                'rc=$?\\n'\n                'echo \"stderr:\"\\n'\n                'echo \"$log\"\\n'\n                'if [ $rc -eq 0 ]; then\\n'\n                # Use the log output as an information that something failed.\n                # Ignore warnings about re-defining macros, and empty lines.\n                '    ! echo \"$log\" | grep -v -e \"^I .*] Re-defining macro.*\" -e \"^$\" -q\\n'\n                '    rc=$?\\n'\n                'fi\\n'\n                'exit $rc\\n').format(\n                    command_str=shlex.quote(command), command=command)\n            script.write(s)\n\n        self.cmd = ['sh', script_path]\n"
  },
  {
    "path": "tools/runners/Verilator.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport shutil\nimport shlex\n\nfrom BaseRunner import BaseRunner\n\n\nclass Verilator(BaseRunner):\n    def __init__(self):\n        super().__init__(\n            \"verilator\", \"verilator\", {\n                \"preprocessing\", \"parsing\", \"elaboration\", \"simulation\",\n                \"simulation_without_run\"\n            })\n\n        self.c_extensions = ['.cc', '.c', '.cpp', '.h', '.hpp']\n        self.allowed_extensions.extend(['.vlt'] + self.c_extensions)\n        self.submodule = \"third_party/tools/verilator\"\n        self.url = f\"https://github.com/verilator/verilator/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        mode = params['mode']\n        conf = os.environ['CONF_DIR']\n        scr = os.path.join(tmp_dir, 'scr.sh')\n\n        # verilator executable is a script but it doesn't\n        # have shell shebang on the first line\n        self.cmd = ['sh', 'scr.sh']\n\n        # Enable timing control support:\n        self.cmd.append('--timing')\n\n        if mode in ['simulation', 'simulation_without_run']:\n            self.cmd += ['--binary']\n        elif mode == 'preprocessing':\n            self.cmd += ['-P', '-E']\n        else:  # parsing and elaboration\n            self.cmd += ['--lint-only']\n\n        # Allow UVM builds within reasonable timeout\n        self.cmd += ['--build-jobs', '0']\n        # Disable compiler optimization as build time exceeds test runtime\n        self.cmd += ['-CFLAGS', '-O0']\n\n        self.cmd += ['-Wno-fatal', '-Wno-UNOPTFLAT', '-Wno-BLKANDNBLK']\n        # Flags for compliance testing:\n        self.cmd += ['-Wpedantic', '-Wno-context']\n\n        if params['top_module'] != '':\n            self.cmd += ['--top-module', params['top_module']]\n            top = params['top_module']\n        else:\n            top = 'top'\n\n        # top is None only if the test contains no module\n        # if that test would be run with simulation related options\n        # Verilator throws error on that test before the build stage\n        build_name = f'V{top}'\n        build_dir = 'vbuild'\n\n        for incdir in params['incdirs']:\n            self.cmd.append('-I' + incdir)\n\n        # No tests require UVM DPI, and we don't currently have a nice\n        # way of knowing when it is needed to put it on the command line.\n        # Also avoids compile time of the DPI C code.\n        self.cmd.append('-DUVM_NO_DPI')\n\n        if mode in ['simulation', 'simulation_without_run']:\n            self.cmd += [\n                '--Mdir', build_dir, '--prefix', build_name, '-o', build_name\n            ]\n\n        if 'runner_verilator_flags' in params:\n            self.cmd += shlex.split(params['runner_verilator_flags'])\n\n        for define in params['defines']:\n            self.cmd.append('-D' + define)\n\n        self.cmd += params['files']\n\n        with open(scr, 'w') as f:\n            f.write('set -x\\n')\n            f.write('{0} \"$@\" || exit $?\\n'.format(self.executable))\n            if mode == 'simulation':\n                f.write(f'./{build_dir}/{build_name}\\n')\n"
  },
  {
    "path": "tools/runners/Yosys.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\n\nfrom BaseRunner import BaseRunner\n\n\nclass Yosys(BaseRunner):\n    def __init__(self):\n        super().__init__(\n            \"yosys\", \"yosys\", {\n                \"preprocessing\", \"parsing\", \"elaboration\", \"simulation\",\n                \"simulation_without_run\"\n            })\n\n        self.submodule = \"third_party/tools/yosys\"\n        self.url = f\"https://github.com/YosysHQ/yosys/tree/{self.get_commit()}\"\n\n    def get_mode(self, params):\n        unsynthesizable = int(params['unsynthesizable'])\n        if unsynthesizable:\n            return None\n        return super().get_mode(params)\n\n    def prepare_run_cb(self, tmp_dir, params):\n        run = os.path.join(tmp_dir, \"run.sh\")\n        scr = os.path.join(tmp_dir, 'scr.ys')\n        mode = params['mode']\n        defer = \"\"\n        if mode in [\"preprocessing\", \"parsing\"]:\n            defer = \"-defer\"\n\n        nodisplay = \"\"\n        if mode in [\"simulation\", \"simulation_without_run\"]:\n            nodisplay = \"-nodisplay\"\n\n        top = params['top_module'] or None\n        if (top is not None):\n            top_opt = \"-top \\\\{top}\"\n        else:\n            top_opt = \"-auto-top\"\n\n        inc = \"\"\n        for incdir in params['incdirs']:\n            inc += f' -I {incdir}'\n\n        defs = \"\"\n        for define in params['defines']:\n            defs += f' -D {define}'\n\n        # prepare yosys script\n        with open(scr, 'w') as f:\n            for svf in params['files']:\n                f.write(\n                    f'read_verilog {defer} -sv {nodisplay} {inc} {defs} {svf}\\n'\n                )\n\n            if mode not in [\"preprocessing\", \"parsing\"]:\n                # prep (without optimizations)\n                f.write(\n                    f\"hierarchy {top_opt}\\n\"\n                    \"proc\\n\"\n                    \"check\\n\"\n                    \"clean\\n\"\n                    \"memory_dff\\n\"\n                    \"memory_collect\\n\"\n                    \"stat\\n\"\n                    \"check\\n\")\n            if mode in ['simulation', 'simulation_without_run']:\n                f.write(\"sim -assert\\n\")\n\n        # prepare wrapper script\n        with open(run, 'w') as f:\n            f.write('set -x\\n')\n            f.write(f'cat {scr}\\n')\n            f.write(f'{self.executable} -Q -T {scr}\\n')\n\n        self.cmd = ['sh', run]\n\n    def get_version_cmd(self):\n        return [self.executable, \"-V\"]\n\n    def get_version(self):\n        version = super().get_version()\n\n        return \" \".join([self.name, version.split()[1]])\n"
  },
  {
    "path": "tools/runners/circt_verilog.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom BaseRunner import BaseRunner\n\n\nclass circt_verilog(BaseRunner):\n    def __init__(\n        self,\n        name=\"circt-verilog\",\n        supported_features={\"preprocessing\", \"parsing\", \"elaboration\"},\n    ):\n        super().__init__(\n            name,\n            executable=\"circt-verilog\",\n            supported_features=supported_features)\n\n        self.submodule = \"third_party/tools/circt-verilog\"\n        self.url = f\"https://github.com/llvm/circt/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        self.cmd = [self.executable]\n        mode = params[\"mode\"]\n\n        # To process the input: The preprocessor indicates only run and print preprocessed files;\n        # parsing means only lint the input, without elaboration and mapping to CIRCT IR.\n        if mode == \"preprocessing\":\n            self.cmd += [\"-E\"]\n        elif mode == \"parsing\":\n            self.cmd += [\"--parse-only\"]\n\n        # The following options are mostly borrowed from the Slang runner, since circt-verilog\n        # uses Slang as its Verilog frontend.\n\n        # Setting for additional include search paths.\n        for incdir in params[\"incdirs\"]:\n            self.cmd.extend([\"-I\", incdir])\n\n        # Setting for macro or value defines in all source files.\n        for define in params[\"defines\"]:\n            self.cmd.extend([\"-D\", define])\n\n        # Borrow from slang config for some modules which get errors without a default timescale.\n        self.cmd += [\"--timescale=1ns/1ns\"]\n\n        # Combine all input files for the tests that need a single compilation unit.\n        self.cmd += [\"--single-unit\"]\n\n        # Disable certain warnings to make the output less noisy.\n        self.cmd += [\"-Wno-implicit-conv\"]\n\n        # Some tests access array elements out of bounds. Make that not an error.\n        self.cmd += [\n            \"-Wno-error=index-oob\",\n            \"-Wno-error=range-oob\",\n            \"-Wno-error=range-width-oob\",\n        ]\n\n        top = self.get_top_module_or_guess(params)\n        if top is not None:\n            self.cmd += [\"--top=\" + top]\n\n        tags = params[\"tags\"]\n\n        # The Ariane and Ibex cores have duplicate definitions.\n        if \"ariane\" in tags or \"ibex\" in tags:\n            self.cmd += [\"-Wno-duplicate-definition\"]\n\n        # The Ariane core has syntax errors with stream concat operators.\n        if \"ariane\" in tags:\n            self.cmd += [\"-Xslang=--allow-self-determined-stream-concat\"]\n\n        # black-parrot has syntax errors where variables are used before they are declared.\n        # This is being fixed upstream, but it might take a long time to make it to master\n        # so this works around the problem in the meantime.\n        if \"black-parrot\" in tags and mode != \"parsing\":\n            self.cmd += [\"--allow-use-before-declare\"]\n\n            # These tests simply cannot be elaborated because they target\n            # modules that have invalid parameter values for a top-level module,\n            # or have an invalid configuration that results in $fatal calls.\n            name = params[\"name\"]\n            if 'bp_lce' in name or 'bp_uce' or 'bp_multicore' in name:\n                self.cmd += [\"--parse-only\"]\n\n        # These cores use a non-standard extension to write to the same variable\n        # from multiple procedures.\n        if \"fx68k\" in tags:\n            self.cmd += [\"--allow-dup-initial-drivers\"]\n\n        self.cmd += params[\"files\"]\n"
  },
  {
    "path": "tools/runners/moore.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport re\nfrom BaseRunner import BaseRunner\n\n\nclass moore(BaseRunner):\n    def __init__(\n            self,\n            name=\"moore\",\n            supported_features={'preprocessing', 'parsing'}):\n        super().__init__(\n            name, executable=\"moore\", supported_features=supported_features)\n\n        self.submodule = \"third_party/tools/moore\"\n        self.url = f\"https://github.com/fabianschuiki/moore/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        self.cmd = [self.executable]\n\n        for incdir in params['incdirs']:\n            self.cmd.append('-I')\n            self.cmd.append(incdir)\n\n        tl = self.get_top_module_or_guess(params)\n        if tl:\n            self.cmd.append('-e')\n            self.cmd.append(tl)\n\n        self.cmd += params['files']\n\n    def run_subprocess(self, tmp_dir, params):\n        # Immediately fail some tests which otherwise completely break the\n        # compiler.\n        # TODO: Remove once #378 lands.\n        blacklist = [\n            \"std2017/p220.sv\",\n            \"std2017/p221.sv\",\n            \"std2017/p745.sv\",\n            \"std2017/p341.sv\",\n            \"std2017/p371.sv\",\n            \"std2017/p759.sv\",\n            \"std2017/p773.sv\",\n        ]\n        for arg in params['files']:\n            for bl in blacklist:\n                if bl in arg:\n                    return (\"Skipping blacklisted \" + arg, 1)\n        return super().run_subprocess(tmp_dir, params)\n\n    def transform_log(self, log):\n        # Strip away terminal escape codes. Moore does not yet check if the\n        # stdout is a tty that supports colorization.\n        log = re.sub(r'\\x1B\\[[0-?]*[ -/]*[@-~]', '', log)\n        return log\n"
  },
  {
    "path": "tools/runners/moore_parse.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom runners.moore import moore\n\n\nclass moore_parse(moore):\n    def __init__(self):\n        super().__init__(\"moore-parse\", supported_features={'parsing'})\n\n    def prepare_run_cb(self, tmp_dir, params):\n        self.cmd = [self.executable, '--syntax']\n\n        for incdir in params['incdirs']:\n            self.cmd.append('-I')\n            self.cmd.append(incdir)\n\n        self.cmd += params['files']\n"
  },
  {
    "path": "tools/runners/sv_parser.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom BaseRunner import BaseRunner\n\n\nclass sv_parser(BaseRunner):\n    def __init__(self):\n        super().__init__(\"sv-parser\", \"parse_sv\", {\"preprocessing\", \"parsing\"})\n\n        self.submodule = \"third_party/tools/sv-parser\"\n        self.url = f\"https://github.com/dalance/sv-parser/tree/{self.get_commit()}\"\n\n    def prepare_run_cb(self, tmp_dir, params):\n        self.cmd = [self.executable]\n\n        for incdir in params['incdirs']:\n            self.cmd.append('--include')\n            self.cmd.append(incdir)\n\n        for define in params['defines']:\n            self.cmd.append('--define')\n            self.cmd.append(define)\n\n        self.cmd += params['files']\n"
  },
  {
    "path": "tools/runners/tree_sitter_systemverilog.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport shutil\n\nfrom BaseRunner import BaseRunner\n\n\nclass tree_sitter_systemverilog(BaseRunner):\n    def __init__(self):\n        super().__init__(\n            \"tree-sitter-systemverilog\", \"tree-sitter\", {\"parsing\"})\n\n        self.submodule = \"third_party/tools/tree-sitter-systemverilog\"\n        self.url = f\"https://github.com/gmlarumbe/tree-sitter-systemverilog/tree/{self.get_commit()}\"\n        self.parser_dir = os.path.abspath(\n            os.environ['TREE_SITTER_SVERILOG_PARSER_DIR'])\n\n    def prepare_run_cb(self, tmp_dir, params):\n        # Tree‑sitter expects the grammar.json in $CWD/src/grammar.json,\n        # so we symlink the parser directory.\n        symlink_path = os.path.join(tmp_dir, 'src')\n        if os.path.exists(symlink_path) is False:\n            os.symlink(self.parser_dir, symlink_path, True)\n\n        self.cmd = [self.executable, 'parse', '--quiet']\n        self.cmd += params['files']\n\n    def can_run(self):\n        parser_c_path = os.path.join(self.parser_dir, 'parser.c')\n        return os.path.exists(parser_c_path) and super().can_run()\n"
  },
  {
    "path": "tools/runners/tree_sitter_verilog.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport shutil\n\nfrom BaseRunner import BaseRunner\n\n\nclass tree_sitter_verilog(BaseRunner):\n    def __init__(self):\n        super().__init__(\"tree-sitter-verilog\", \"tree-sitter\", {\"parsing\"})\n\n        self.submodule = \"third_party/tools/tree-sitter-verilog\"\n        self.url = f\"https://github.com/tree-sitter/tree-sitter-verilog/tree/{self.get_commit()}\"\n        self.parser_dir = os.path.abspath(\n            os.environ['TREE_SITTER_VERILOG_PARSER_DIR'])\n\n    def prepare_run_cb(self, tmp_dir, params):\n        # Tree‑sitter expects the grammar.json in $CWD/src/grammar.json,\n        # so we symlink the parser directory.\n        symlink_path = os.path.join(tmp_dir, 'src')\n        if os.path.exists(symlink_path) is False:\n            os.symlink(self.parser_dir, symlink_path, True)\n\n        self.cmd = [self.executable, 'parse', '--quiet']\n        self.cmd += params['files']\n\n    def can_run(self):\n        parser_c_path = os.path.join(self.parser_dir, 'parser.c')\n        return os.path.exists(parser_c_path) and super().can_run()\n"
  },
  {
    "path": "tools/runners/yosys_slang.py",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nimport os\nimport sys\n\nfrom BaseRunner import BaseRunner\n\n\nclass yosys_slang(BaseRunner):\n    def __init__(self):\n        super().__init__(\"yosys-slang\", \"yosys-slang\", {\"elaboration\"})\n\n        self.submodule = \"third_party/tools/yosys-slang\"\n        self.url = f\"https://github.com/povik/yosys-slang/tree/{self.get_commit()}\"\n\n    def get_mode(self, params):\n        unsynthesizable = int(params['unsynthesizable'])\n        if unsynthesizable:\n            return None\n\n        # These tests simply cannot be elaborated because they target\n        # modules that have invalid parameter values for a top-level module,\n        # or have an invalid configuration that results in $fatal calls.\n        name = params[\"name\"]\n        tags = params[\"tags\"]\n        if \"black-parrot\" in tags and ('bp_lce' in name or 'bp_uce'\n                                       or 'bp_multicore' in name):\n            return None\n\n        return super().get_mode(params)\n\n    def prepare_run_cb(self, tmp_dir, params):\n        yosys_scr = os.path.join(tmp_dir, \"yosys-script\")\n        mode = params['mode']\n\n        slang_cmd = ['-DSYNTHESIS']\n\n        # Ignore content which is unsynthesizable or likely irrelevant for synthesis. The inclusion\n        # of `--ignore-initial` is objectionable as it means the frontend won't pick up memory\n        # initialization.\n        slang_cmd += [\n            '--ignore-timing', '--ignore-initial', '--ignore-assertions'\n        ]\n\n        # Some tests expect that all input files will be concatenated into\n        # a single compilation unit, so ask slang to do that.\n        slang_cmd += ['--single-unit']\n\n        # Set a default timescale so we don't get errors about some\n        # modules not having one.\n        slang_cmd += ['--timescale=1ns/1ns']\n\n        top = params['top_module'].strip() or None\n        if top:\n            slang_cmd.append('--top=' + top)\n\n        for incdir in params['incdirs']:\n            slang_cmd.extend(['-I', incdir])\n\n        for define in params['defines']:\n            slang_cmd.extend(['-D', define])\n\n        # Some tests access array elements out of bounds. Make that not an error.\n        slang_cmd.append(\"-Wno-error=index-oob\")\n        slang_cmd.append(\"-Wno-error=range-oob\")\n        slang_cmd.append(\"-Wno-error=range-width-oob\")\n\n        tags = params[\"tags\"]\n\n        # The Ariane core does not build correctly if VERILATOR is not defined -- it will attempt\n        # to reference nonexistent modules, for example.\n        if \"ariane\" in tags:\n            slang_cmd.append(\"-DVERILATOR\")\n\n        # black-parrot has syntax errors where variables are used before they are declared.\n        # This is being fixed upstream, but it might take a long time to make it to master\n        # so this works around the problem in the meantime.\n        if \"black-parrot\" in tags:\n            slang_cmd.append(\"--allow-use-before-declare\")\n\n        # These cores use a non-standard extension to write to the same variable\n        # from multiple procedures.\n        if \"fx68k\" in tags:\n            slang_cmd.append(\"--allow-dup-initial-drivers\")\n\n        slang_cmd += params['files']\n\n        # generate yosys script\n        with open(yosys_scr, \"w\") as f:\n            f.write(\"plugin -i slang\\n\")\n            f.write(f\"read_slang {' '.join(slang_cmd)}\\n\")\n\n            # prep (without optimizations)\n            if top is not None:\n                f.write(f\"hierarchy -top \\\\{top}\\n\")\n            else:\n                f.write(\"hierarchy -auto-top\\n\")\n            f.write(\n                \"proc\\n\"\n                \"check\\n\"\n                \"memory_dff\\n\"\n                \"memory_collect\\n\"\n                \"stat\\n\"\n                \"check\\n\")\n\n        self.cmd = [self.executable, \"-s\", yosys_scr]\n"
  },
  {
    "path": "tools/runners.mk",
    "content": "# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nINSTALL_DIR := $(abspath $(OUT_DIR)/runners/)\n\nRDIR := $(abspath third_party/tools)\nTDIR := $(abspath tools)\nCDIR := $(abspath conf)\n\nTREE_SITTER_SVERILOG_PARSER_DIR := $(abspath $(OUT_DIR)/tmp/tree-sitter-systemverilog/parser)\nTREE_SITTER_VERILOG_PARSER_DIR := $(abspath $(OUT_DIR)/tmp/tree-sitter-verilog/parser)\n\nexport TREE_SITTER_SVERILOG_PARSER_DIR\nexport TREE_SITTER_VERILOG_PARSER_DIR\n\n.PHONY: runners\n\nrunners:\n\n# odin\nodin: $(INSTALL_DIR)/bin/odin_II\n\n$(INSTALL_DIR)/bin/odin_II:\n\t$(MAKE) -C $(RDIR)/odin_ii/ODIN_II/ build\n\tinstall -D $(RDIR)/odin_ii/ODIN_II/odin_II $@\n\n# yosys\nyosys: $(INSTALL_DIR)/bin/yosys\n\n$(INSTALL_DIR)/bin/yosys:\n\t$(MAKE) -C $(RDIR)/yosys CONFIG=gcc PREFIX=$(INSTALL_DIR) install\n\n# icarus\nicarus: $(INSTALL_DIR)/bin/iverilog\n\n$(INSTALL_DIR)/bin/iverilog:\n\tcd $(RDIR)/icarus && autoconf\n\tcd $(RDIR)/icarus && ./configure --prefix=$(abspath $(INSTALL_DIR))/\n\t$(MAKE) -C $(RDIR)/icarus\n\t$(MAKE) -C $(RDIR)/icarus installdirs\n\t$(MAKE) -C $(RDIR)/icarus install\n\n# verilator\nverilator: $(INSTALL_DIR)/bin/verilator\n\n$(INSTALL_DIR)/bin/verilator:\n\tcd $(RDIR)/verilator && autoconf\n\tcd $(RDIR)/verilator && ./configure --prefix=$(abspath $(INSTALL_DIR))/\n\t$(MAKE) -C $(RDIR)/verilator\n\t$(MAKE) -C $(RDIR)/verilator install\n\n# slang\nslang: $(INSTALL_DIR)/bin/slang-driver\n\n$(INSTALL_DIR)/bin/slang-driver:\n\tmkdir -p $(RDIR)/slang/build\n\tcd $(RDIR)/slang/build && cmake .. -DSLANG_INCLUDE_TESTS=OFF -DCMAKE_BUILD_TYPE=Release\n\t$(MAKE) -C $(RDIR)/slang/build\n\tinstall -D $(RDIR)/slang/build/bin/slang $@\n\n# Surelog\nsurelog: $(INSTALL_DIR)/bin/surelog\n\n$(INSTALL_DIR)/bin/surelog:\n\tcd $(RDIR)/Surelog ; mkdir -p build/tests dist\n\tcd $(RDIR)/Surelog/build && cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$(INSTALL_DIR) ../\n\t$(MAKE) -C $(RDIR)/Surelog/build install\n\n# zachjs-sv2v\nzachjs-sv2v: $(INSTALL_DIR)/bin/zachjs-sv2v\n\n$(INSTALL_DIR)/bin/zachjs-sv2v:\n\t$(MAKE) -C $(RDIR)/zachjs-sv2v\n\tinstall -D $(RDIR)/zachjs-sv2v/bin/sv2v $@\n\n# tree-sitter-verilog & tree-sitter-systemverilog\ntree-sitter-systemverilog: $(INSTALL_DIR)/bin/tree-sitter\n\t(export PATH=$(INSTALL_DIR)/bin/:${PATH} && \\\n\t\tcd $(RDIR)/tree-sitter-systemverilog && tree-sitter generate)\n\tmkdir -p $(abspath $(OUT_DIR)/tmp/tree-sitter-systemverilog)\n\tmv $(RDIR)/tree-sitter-systemverilog/src $(TREE_SITTER_SVERILOG_PARSER_DIR)\n\ntree-sitter-verilog: $(INSTALL_DIR)/bin/tree-sitter\n\t(export PATH=$(INSTALL_DIR)/bin/:${PATH} && \\\n\t\tcd $(RDIR)/tree-sitter-verilog && tree-sitter generate)\n\tmkdir -p $(abspath $(OUT_DIR)/tmp/tree-sitter-verilog)\n\tmv $(RDIR)/tree-sitter-verilog/src $(TREE_SITTER_VERILOG_PARSER_DIR)\n\n$(INSTALL_DIR)/bin/tree-sitter:\n\twget https://github.com/tree-sitter/tree-sitter/releases/download/v0.25.3/tree-sitter-linux-x64.gz\n\tgunzip tree-sitter-linux-x64.gz\n\tinstall -D tree-sitter-linux-x64 $@\n\trm tree-sitter-linux-x64\n\n# yosys-synlig\nyosys-synlig: $(INSTALL_DIR)/bin/yosys-synlig\n\n$(INSTALL_DIR)/bin/yosys-synlig:\n\tmkdir -p $(INSTALL_DIR)\n\t(export PATH=$(INSTALL_DIR)/bin/:${PATH} && \\\n\t\tcd $(RDIR)/synlig && \\\n\t\t$(MAKE) -rR -Oline install CFG_OUT_DIR=$(INSTALL_DIR)/)\n\tmv $(INSTALL_DIR)/bin/yosys $(INSTALL_DIR)/bin/yosys-synlig\n\n# sv-parser\nsv-parser: $(INSTALL_DIR)/bin/parse_sv\n\n$(INSTALL_DIR)/bin/parse_sv:\n\tcd $(RDIR)/sv-parser && cargo build --release --example parse_sv\n\tinstall -D $(RDIR)/sv-parser/target/release/examples/parse_sv $@\n\n# moore\nmoore: $(INSTALL_DIR)/bin/moore\n\n$(INSTALL_DIR)/bin/moore: $(RDIR)/moore/Cargo.lock\n\t(export CARGO_NET_GIT_FETCH_WITH_CLI=true && \\\n        cargo install --locked --path $(RDIR)/moore --root $(INSTALL_DIR) --bin moore)\n\n$(RDIR)/moore/Cargo.lock: $(CDIR)/runners/Cargo.lock\n\tcp -f $(CDIR)/runners/Cargo.lock $(RDIR)/moore/Cargo.lock\n\n# verible\nverible:\n\tcd $(RDIR)/verible/ && bazel build :install-binaries --noshow_progress --//bazel:use_local_flex_bison -c opt\n\tcd $(RDIR)/verible/ && .github/bin/simple-install.sh $(INSTALL_DIR)/bin\n\tcd $(RDIR)/verible/ && bazel shutdown\n\n$(INSTALL_DIR)/bin/verible-verilog-kythe-extractor: verible\n\n$(INSTALL_DIR)/bin/verilog_syntax: verible\n\n# yosys-slang\nyosys-slang: $(INSTALL_DIR)/bin/yosys-slang\n\n$(INSTALL_DIR)/bin/slang-yosys $(INSTALL_DIR)/bin/slang-yosys-config:\n\t$(MAKE) -C $(RDIR)/yosys CONFIG=gcc CXXSTD=c++20 ENABLE_ABC=0 \\\n\t\t\t\tPROGRAM_PREFIX=slang- PREFIX=$(INSTALL_DIR) install\n\n$(INSTALL_DIR)/bin/yosys-slang: $(INSTALL_DIR)/bin/slang-yosys-config\n\tmkdir -p $(INSTALL_DIR)\n\t(export PATH=$(INSTALL_DIR)/bin/:${PATH} && \\\n\t\tcd $(RDIR)/yosys-slang && \\\n\t\tTARGET=$(INSTALL_DIR)/share/slang-yosys/plugins/slang.so YOSYS_PREFIX=slang- ./build.sh)\n\t# copy slang-yosys, which was the result of compiling yosys with PROGRAM_PREFIX=slang-,\n\t# to yosys-slang, which is the executable registered in tools/runners/yosys_slang.py\n\tcp $(INSTALL_DIR)/bin/slang-yosys $(INSTALL_DIR)/bin/yosys-slang\n\n# circt-verilog\ncirct-verilog: $(INSTALL_DIR)/bin/circt-verilog\n\n$(INSTALL_DIR)/bin/circt-verilog:\n\tcd $(RDIR)/circt-verilog && cmake llvm/llvm -B build \\\n\t\t-DCMAKE_INSTALL_PREFIX=$(INSTALL_DIR) \\\n\t\t-DCMAKE_BUILD_TYPE=Release \\\n\t\t-DLLVM_TARGETS_TO_BUILD=host \\\n\t\t-DLLVM_ENABLE_PROJECTS=mlir \\\n\t\t-DLLVM_EXTERNAL_PROJECTS=circt \\\n\t\t-DLLVM_EXTERNAL_CIRCT_SOURCE_DIR=$(RDIR)/circt-verilog \\\n\t\t-DCIRCT_SLANG_FRONTEND_ENABLED=ON\n\t$(MAKE) -C $(RDIR)/circt-verilog/build install-circt-verilog\n\n# setup the dependencies\nRUNNERS_TARGETS := odin yosys icarus verilator slang zachjs-sv2v tree-sitter-systemverilog tree-sitter-verilog sv-parser moore verible surelog yosys-synlig circt-verilog\n.PHONY: $(RUNNERS_TARGETS)\nrunners: $(RUNNERS_TARGETS)\n"
  },
  {
    "path": "tools/sv-report",
    "content": "#!/usr/bin/env python3\n# -*- coding: utf-8 -*-\n#\n# Copyright (C) 2020 The SymbiFlow Authors.\n#\n# Use of this source code is governed by a ISC-style\n# license that can be found in the LICENSE file or at\n# https://opensource.org/licenses/ISC\n#\n# SPDX-License-Identifier: ISC\n\nfrom pygments.formatters import HtmlFormatter\nfrom pygments import lexers, highlight\nimport multiprocessing\nfrom glob import glob\nfrom logparser import parseLog\nimport argparse\nimport logging\nimport jinja2\nimport markupsafe\nimport csv\nimport datetime\nimport sys\nimport os\nimport re\nimport html\nimport urllib.parse\nimport dataclasses\nimport enum\nfrom typing import Dict, Any, List, Set, Iterable\nimport json\nimport itertools\n\nfrom typing import Match  # portable type alias\n\n# We only consider tests with minimum this size for the throughput\n# calculation, so that we skip the super-tiny few-line tests that are\n# not a true reflection of a common usage.\n_minimum_throughput_file_size = 1024\n\n# Regexp for matching file paths with optional line and column number\n# separated with \":\".\n# The patch must contain at least one \"/\". Designed for finding references to\n# input files in tools' output.\n# Captures 3 groups:\n#   1: file path\n#   2: matched text following file path (i.e. \":row:column\")\n#   3: row number\n# Example inputs:\n#   /some/file.sv\n#   relative/file/name.v:12       <- group(2): \":12\",    group(3): \"12\"\n#   /some/file.svh:12:35          <- group(2): \":12:35\", group(3): \"12\"\n_PATH_WITH_LINE_NO_MATCHER = re.compile(\n    r\"([^\\s:\\\"'`/]*/[^\\s:\\\"'`]+\\.\\w+)(:(\\d+)(?::\\d+)?)?\")\n\n# CamelCase or undscore_separator csv headers ?\n# We use CamelCase so that gnuplot getting header from CSV displays them\n# as-is and doesn't print the post-underscore letter a subscript.\n_csv_header = [\n    'TestName',\n    'Tool',  # Parser/Compiler/Tool processing it\n    'Group',\n    'Pass',  # result. True if we got expected result.\n    'ExitCode',  # Actual tool exit code\n    'Tags',\n    'InputBytes',  # test facts\n    'AllowedTimeout',  # Some measurements\n    'TimeUser',\n    'TimeSystem',\n    'TimeWall',\n    'RamUsageMiB'\n]\n\n# Global state for worker threads. Initialized once per process using\n# init_globals.\n\n_logger = None\n_log_template_file = None\n_log_template = None\n_logs_dir = None\n_out_dir = None\n_top_dir = None\n_logs_out_dir = None\n_src_template = None\n_src_template_file = None\n_meta_tags = None\n\n\ndef init_logger(quiet: bool, verbose: bool):\n    global _logger\n\n    if _logger is not None:\n        return\n\n    _logger = logging.getLogger()\n    _logger.setLevel(logging.DEBUG)\n\n    ch = logging.StreamHandler()\n    ch.setFormatter(logging.Formatter('%(levelname)-8s| %(message)s'))\n    _logger.addHandler(ch)\n\n    if quiet:\n        _logger.setLevel(logging.ERROR)\n    elif verbose:\n        _logger.setLevel(logging.DEBUG)\n    else:\n        _logger.setLevel(logging.INFO)\n\n    return _logger\n\n\ndef init_templates(log_template_file, src_template_file):\n    global _log_template\n    global _log_template_file\n    global _src_template\n    global _src_template_file\n\n    template_dir = os.path.dirname(log_template_file)\n    jinja2env = ReportJinja2Env(template_dir)\n    if _log_template_file is None:\n        _log_template_file = log_template_file\n        with open(_log_template_file, \"r\") as templ:\n            _log_template = jinja2env.from_string(templ.read())\n\n    if _src_template_file is None:\n        _src_template_file = src_template_file\n        with open(_src_template_file, \"r\") as templ:\n            _src_template = jinja2env.from_string(templ.read())\n\n\ndef init_dirs(logs_dir, out_dir, top_dir, logs_out_dir):\n    global _logs_dir\n    global _out_dir\n    global _top_dir\n    global _logs_out_dir\n    if _logs_dir is None:\n        _logs_dir = logs_dir\n    if _out_dir is None:\n        _out_dir = out_dir\n    if _top_dir is None:\n        _top_dir = top_dir\n    if _logs_out_dir is None:\n        _logs_out_dir = logs_out_dir\n\n\ndef init_meta_tags(meta_tags):\n    global _meta_tags\n    if _meta_tags is None:\n        _meta_tags = meta_tags\n\n\ndef init_globals(\n        log_template_file, src_template_file, logs_dir: str, out_dir, top_dir,\n        logs_out_dir, quiet: bool, verbose: bool, meta_tags):\n    init_logger(quiet, verbose)\n    init_templates(log_template_file, src_template_file)\n    init_dirs(logs_dir, out_dir, top_dir, logs_out_dir)\n    init_meta_tags(meta_tags)\n\n\n# NOTE: this works correctly only with numbers shorter than 10 digits\ndef numericSortKey(s: str):\n    # prepend all number occurences with the length of the number\n    r = re.sub(r\"\\d+\", lambda m: str(len(m.group(0))) + m.group(0), s).lower()\n    return r\n\n\nclass ReportJinja2Env(jinja2.Environment):\n    def __init__(self, include_dir: str):\n        super().__init__(\n            trim_blocks=True,\n            lstrip_blocks=True,\n            loader=jinja2.FileSystemLoader(include_dir))\n        self.filters[\"escape_attr\"] = ReportJinja2Env.escapeXmlAttribute\n        self.filters[\"escape_js_str\"] = ReportJinja2Env.escapeJsString\n        self.filters[\"quote\"] = ReportJinja2Env.surroundWithQuotes\n        self.filters[\"numeric_sort\"] = ReportJinja2Env.numericSort\n        self.filters[\"numeric_dictsort\"] = ReportJinja2Env.numericDictSort\n        self.filters[\"tag_dictsort\"] = ReportJinja2Env.tagDictSort\n\n    @staticmethod\n    def escapeXmlAttribute(value: str):\n        return str(markupsafe.escape(value)).replace(\"\\n\", \"&#10;\")\n\n    @staticmethod\n    def escapeJsString(value: str):\n        def esc(match: Match):\n            return rf\"\\x{ord(match.group(0)):02x}\"\n\n        return re.sub(r\"[\\x00-\\x1F\\x7F'\\\"]\", esc, value)\n\n    @staticmethod\n    def surroundWithQuotes(value: str, quot='\"'):\n        return quot + str(value) + quot\n\n    @staticmethod\n    def numericSort(l: List[str]):\n        return sorted(l, key=numericSortKey)\n\n    @staticmethod\n    def numericDictSort(d: Dict[str, Any]):\n        return sorted(d.items(), key=lambda kv: numericSortKey(kv[0]))\n\n    # Like numericDictSort, but entries starting with a letter are placed before\n    # entries starting with a digit.\n    @staticmethod\n    def tagDictSort(d: Dict[str, Any]):\n        def tagSortKey(s: str):\n            if len(s) > 0 and s[0].isdigit():\n                return numericSortKey(s)\n            else:\n                return \" \" + numericSortKey(s)\n\n        return sorted(d.items(), key=lambda kv: tagSortKey(kv[0]))\n\n\ndef exists_and_is_newer_than(target: str, sources: List[str]):\n    if not os.path.exists(target):\n        return False\n\n    for s in sources:\n        if (not os.path.exists(s)\n                or os.path.getctime(s) > os.path.getctime(target)):\n            return False\n\n    return True\n\n\ndef totalSize(files):\n    size = 0\n    for f in files:\n        try:\n            size += os.path.getsize(f)\n        except FileNotFoundError:\n            pass\n    return size\n\n\ndef criticalError(msg):\n    _logger.critical(msg)\n    sys.exit(1)\n\n\ndef readConfig(filename):\n    config = {}\n    urls = {}\n    try:\n        with open(filename) as f:\n            for l in f:\n                ls = l.strip()\n                # skip lines with comments\n                if re.search(r\"^\\s*#.*\", ls) is not None:\n                    continue\n\n                entry = ls.split(\"\\t\")\n\n                if not 2 <= len(entry) <= 3:\n                    raise KeyError(\"Invalid entry: \" + ls)\n\n                config[entry[0]] = entry[1]\n\n                # check if we\n                if len(entry) == 3:\n                    urls[entry[0]] = entry[2]\n    except (OSError, FileNotFoundError, KeyError) as e:\n        criticalError(f\"Unable to parse {config} file - {str(e)}\")\n    return config, urls\n\n\n@enum.unique\nclass TestStatus(enum.Enum):\n    NA = \"test-na\"\n    PASSED = \"test-passed\"\n    FAILED = \"test-failed\"\n    VARIED = \"test-varied\"\n\n    def __str__(self):\n        return self.value\n\n\n@dataclasses.dataclass\nclass TestResult:\n    log_html_file: str = \"\"\n\n    name: str = \"\"\n    tags: Set[str] = dataclasses.field(default_factory=set)\n    types: Set[str] = dataclasses.field(default_factory=set)\n    results_group: str = \"\"\n    unsynthesizable: str = \"\"\n    input_files: List[str] = dataclasses.field(default_factory=list)\n    # Unit: bytes\n    total_input_files_size: int = 0\n    status: TestStatus = TestStatus.NA\n    exit_code: int = 0\n\n    # Unit: seconds\n    timeout: int = 0\n\n    # Unit: seconds\n    total_time: float = 0\n    user_time: float = 0\n    system_time: float = 0\n\n    # Unit: KB\n    ram_usage: float = 0\n\n\n@dataclasses.dataclass\nclass TagInfo:\n    description: str = \"\"\n    url: str = \"\"\n\n\n@dataclasses.dataclass\nclass ToolInfo:\n    # Tool name should be used only for display purposes. Always use a key\n    # from `tools` in `ReportResults` (or another dict where tool ID is\n    # the key) as a runner/tool ID.\n    name: str = \"\"\n    version: str = \"\"\n    url: str = \"\"\n\n\n@dataclasses.dataclass\nclass TagToolResult:\n    tests: List[TestResult] = dataclasses.field(default_factory=list)\n    types: Set[str] = dataclasses.field(default_factory=set)\n\n    passed_tests: int = 0\n\n    @property\n    def total_tests(self):\n        return len(self.tests)\n\n    @property\n    def status(self) -> TestStatus:\n        if (self.total_tests == 0):\n            return TestStatus.NA\n        elif (self.passed_tests == 0):\n            return TestStatus.FAILED\n        elif (self.passed_tests == self.total_tests):\n            return TestStatus.PASSED\n        return TestStatus.VARIED\n\n\n@dataclasses.dataclass\nclass ToolSummary:\n    # Unit: seconds\n    total_time: float = 0\n    user_time: float = 0\n    system_time: float = 0\n\n    # Unit: MB\n    max_ram_usage: float = 0\n\n    # Unit: KiB/s\n    passed_throughput: float = 0\n\n    total_passed_tests: int = 0\n    total_tests: int = 0\n    total_passed_tags: int = 0\n    total_tested_tags: int = 0\n\n\n@dataclasses.dataclass\nclass GroupData:\n    # key 1 = tag id; key 2 = runner name = runner class name\n    tags_tools: Dict[str, Dict[str, TagToolResult]] = dataclasses.field(\n        default_factory=dict)\n    # key = runner name = runner class name\n    summaries: Dict[str, ToolSummary] = dataclasses.field(default_factory=dict)\n    # key = runner name = runner class name\n    tests: Dict[str,\n                List[TestResult]] = dataclasses.field(default_factory=dict)\n\n\n# GroupData equivalent for data from a single tool\n@dataclasses.dataclass\nclass PartialGroupData:\n    # key 1 = tag id\n    tags: Dict[str, TagToolResult] = dataclasses.field(default_factory=dict)\n    summary: ToolSummary = dataclasses.field(default_factory=ToolSummary)\n    tests: List[TestResult] = dataclasses.field(default_factory=list)\n\n\n@dataclasses.dataclass\nclass ReportResults:\n    # Results groups (key = results group id)\n    groups: Dict[str, GroupData] = dataclasses.field(default_factory=dict)\n    # key = runner name = runner class name\n    tools: Dict[str, ToolInfo] = dataclasses.field(default_factory=dict)\n\n    # Tags used in the report. Keys are tag IDs.\n    tags: Dict[str, TagInfo] = dataclasses.field(default_factory=dict)\n\n\ndef convertPathsToRelativeLinks(text: str, relative_to: str):\n    \"\"\"Replaces paths to existing files in \"text\" with HTML links to them.\n\n    The matched paths can optionally contain row and column number separated\n    with \":\". The generated links are relative to \"relative_to\" and their\n    target (frame in which they open) is \"file-frame\".\n\n    Designed for finding references to input files in tools' output.\n\n    Args:\n      text: Escaped (for use in HTML) text.\n      relative_to: Directory to which the generated urls will be relative.\n\n    Returns:\n      Text in which paths are replaced with HTML links.\n    \"\"\"\n    def convertPath(match: Match):\n        path: str = html.unescape(match.group(1))\n        if not os.path.exists(path):\n            return match.group(0)\n\n        if path.startswith(_top_dir):\n            path = path[len(_top_dir) + 1:]\n        elif path.startswith(\"/\"):\n            return match.group(0)\n\n        url = os.path.join(_out_dir, path + \".html\")\n        url = os.path.relpath(url, relative_to)\n        url = urllib.parse.quote(url)\n        esc_match = str(markupsafe.escape(path))\n        line_no = match.group(3)\n        if line_no is not None:\n            url = f\"{url}#l-{line_no}\"\n            esc_match = esc_match + (match.group(2) or \"\")\n        return f'<a href=\"{url}\" target=\"file-frame\">{esc_match}</a>'\n\n    return _PATH_WITH_LINE_NO_MATCHER.sub(convertPath, text)\n\n\ndef renderLogToHTMLFile(\n        log_template, out_dir: str, log_html_path: str,\n        test_result: TestResult, test_log: Dict[str, str], log_content: str):\n    files_map: Dict[str, str] = {}\n    log_html_dir = os.path.dirname(log_html_path)\n    for input_file in test_result.input_files:\n        # Absolute path:\n        input_file_html = os.path.join(_out_dir, input_file + \".html\")\n        # Path relative to rendered log:\n        input_file_html = os.path.relpath(input_file_html, log_html_dir)\n\n        files_map[input_file] = urllib.parse.quote(input_file_html)\n\n    log_content = convertPathsToRelativeLinks(\n        str(markupsafe.escape(log_content)), log_html_dir)\n\n    csspath = os.path.join(_out_dir, \"log.css\")\n    csspath = os.path.relpath(csspath, os.path.dirname(log_html_path))\n    os.makedirs(os.path.dirname(log_html_path), exist_ok=True)\n    with open(log_html_path, 'w') as f:\n        f.write(\n            log_template.render(\n                input_files_map=files_map,\n                result=test_result,\n                log=test_log,\n                content=log_content,\n                csspath=csspath))\n\n\ndef renderInputFileToHTMLFile(\n        out_dir: str, html_path: str, input_file_path: str, lex):\n    formatter = HtmlFormatter(\n        full=False, linenos=True, anchorlinenos=True, lineanchors='l')\n\n    os.makedirs(os.path.dirname(html_path), exist_ok=True)\n\n    raw_code = \"\"\n    try:\n        with open(input_file_path, 'rb') as f:\n            raw_code = f.read()\n    except IOError:\n        _logger.warning(f\"Error when opening file {input_file_path}\")\n        try:\n            with open(html_path, 'w') as out:\n                out.write('Error when opening file ' + input_file_path)\n        except IOError:\n            pass\n        return\n\n    code = highlight(raw_code, lex, formatter)\n    csspath = os.path.join(_out_dir, \"code.css\")\n    csspath = os.path.relpath(csspath, os.path.dirname(html_path))\n    with open(html_path, 'w') as out:\n        out.write(\n            _src_template.render(\n                csspath=csspath, filename=input_file_path, code=code))\n\n\ndef renderTagResultsConfig(\n        js_path: str, tool: str, tag: str, test_results: Iterable[TestResult]):\n    tool = tool.lower()\n    tag = tag.lower()\n    js_global_variable_name = f\"config_loader_data['{tool}/{tag}']\"\n\n    # Order of values in each entry:\n    # [group, name, status, log_html_path, first_input_file_html_path]\n    config = []\n    for test_result in test_results:\n        name = test_result.name\n        status = int(test_result.status == TestStatus.PASSED)\n        log_html_file = test_result.log_html_file\n        first_input_html = test_result.input_files[0] + \".html\"\n        first_input_html = urllib.parse.quote(first_input_html)\n        group = test_result.results_group\n        config.append([group, name, status, log_html_file, first_input_html])\n\n    js_data = json.dumps(config, separators=(\",\", \":\"))\n    code = f\"{js_global_variable_name} = {js_data}\"\n\n    os.makedirs(os.path.dirname(js_path), exist_ok=True)\n    with open(js_path, \"w\") as f:\n        f.write(code)\n\n\ndef collect_logs(runner_name: str):\n    @dataclasses.dataclass\n    class LocalPartialGroupData:\n        group: PartialGroupData = dataclasses.field(\n            default_factory=PartialGroupData)\n\n        # Values used to calculate throughput. Totals are collected only for\n        # files with size > _minimum_throughput_file_size\n        passed_tests_time: float = 0.0\n        passed_tests_input_files_size: float = 0.0\n\n    local_groups: Dict[str, LocalPartialGroupData] = {}\n    tool_info: ToolInfo = ToolInfo()\n\n    rendered_count = 0\n    tests_count = 0\n\n    for log_file in glob(os.path.join(_logs_dir, runner_name, \"**/*.log\"),\n                         recursive=True):\n        # Strip f\"{_logs_dir}/\" prefix from log file path\n        t_id = log_file[len(_logs_dir) + 1:]\n        _logger.debug(\"Found log: \" + t_id)\n\n        # Tests that have not run will have an existing, but empty logfile.\n        if os.path.getsize(log_file) == 0:\n            continue\n\n        test_result = TestResult()\n\n        remaining_parameters = {\n            \"name\", \"tags\", \"should_fail\", \"rc\", \"date_completed\",\n            \"description\", \"files\", \"incdirs\", \"top_module\", \"runner\",\n            \"runner_url\", \"time_elapsed\", \"type\", \"mode\", \"timeout\",\n            \"user_time\", \"system_time\", \"ram_usage\", \"tool_success\",\n            \"should_fail_because\", \"defines\", \"compatible-runners\",\n            \"unsynthesizable\", \"results_group\"\n        }\n        test_log_data: Dict[str, Any] = {}\n        log_content = \"\"\n\n        with open(log_file, \"r\") as f:\n            try:\n                for l in f:\n                    attr = re.search(r\"^([a-zA-Z_-]+):(.+)\", l)\n\n                    if attr is None:\n                        raise KeyError(\n                            \"Could not find parameters: {}\".format(\n                                \", \".join(remaining_parameters)))\n\n                    param = attr.group(1).lower()\n                    value = attr.group(2).strip()\n\n                    if param not in remaining_parameters:\n                        _logger.warning(\n                            \"Skipping unknown parameter: {} in {}\".format(\n                                param, log_file))\n                        continue\n                    if param in test_log_data:\n                        _logger.warning(\n                            \"Skipping duplicated parameter: {} in {}\".format(\n                                param, log_file))\n                        continue\n\n                    test_log_data[param] = value\n\n                    remaining_parameters.remove(param)\n                    if len(remaining_parameters) == 0:\n                        # found all tags\n                        break\n\n            except Exception as e:\n                _logger.warning(\n                    \"Skipping {} on {}: {}\".format(\n                        log_file, runner_name, str(e)))\n                continue\n\n            log_content = f.read()\n\n        # Test Result\n\n        test_result.name = test_log_data[\"name\"]\n        test_result.unsynthesizable = test_log_data[\"unsynthesizable\"]\n        test_result.results_group = test_log_data[\"results_group\"]\n\n        # Convert splitted \"tags\" to set() and append all meta-tags\n        test_result.tags = set(test_log_data[\"tags\"].split())\n        for meta_tag, dependency_tags in _meta_tags.items():\n            dependency_tags = set(dependency_tags.split())\n            if not dependency_tags.isdisjoint(test_result.tags):\n                test_result.tags.add(meta_tag)\n\n        test_result.input_files = [\n            os.path.relpath(f, _top_dir)\n            for f in test_log_data[\"files\"].split()\n        ]\n\n        test_result.types = test_log_data[\"type\"].split()\n        test_result.total_input_files_size = totalSize(test_result.input_files)\n        test_result.exit_code = int(test_log_data[\"rc\"])\n\n        # Determine test status\n        tool_should_fail = test_log_data[\"should_fail\"] == \"1\"\n        tool_crashed = test_result.exit_code >= 126\n        tool_failed = test_log_data[\"tool_success\"] == \"0\"\n        if tool_crashed or tool_should_fail != tool_failed:\n            test_result.status = TestStatus.FAILED\n        elif (test_log_data[\"mode\"] == \"simulation\"\n              and not parseLog(log_content)):\n            test_result.status = TestStatus.FAILED\n        else:\n            test_result.status = TestStatus.PASSED\n\n        test_result.timeout = int(test_log_data[\"timeout\"])\n\n        test_result.total_time = float(test_log_data[\"time_elapsed\"])\n        test_result.user_time = float(test_log_data[\"user_time\"])\n        test_result.system_time = float(test_log_data[\"system_time\"])\n\n        test_result.ram_usage = float(test_log_data[\"ram_usage\"])  # KB\n\n        log_html = os.path.join(_logs_out_dir, t_id + \".html\")\n        test_result.log_html_file = os.path.relpath(log_html, _out_dir)\n\n        # Render the log if needed\n        if not exists_and_is_newer_than(\n                log_html, [log_file, _log_template_file, __file__]):\n            rendered_count += 1\n            renderLogToHTMLFile(\n                _log_template, _out_dir, log_html, test_result, test_log_data,\n                log_content)\n        tests_count += 1\n\n        # Group\n\n        local_group = local_groups.setdefault(\n            test_result.results_group, LocalPartialGroupData())\n        group = local_group.group\n        group.tests.append(test_result)\n\n        # (tag, tool) results\n\n        for tag in test_result.tags:\n            tag_data = group.tags.setdefault(tag, TagToolResult())\n            tag_data.tests.append(test_result)\n            tag_data.types.update(test_result.types)\n            if test_result.status == TestStatus.PASSED:\n                tag_data.passed_tests += 1\n\n        # Summary\n\n        if test_result.status == TestStatus.PASSED:\n            input_files_size = test_result.total_input_files_size\n            if input_files_size > _minimum_throughput_file_size:\n                local_group.passed_tests_input_files_size += input_files_size\n                local_group.passed_tests_time += test_result.total_time\n\n        summary = group.summary\n\n        summary.total_time += test_result.total_time\n        summary.user_time += test_result.user_time\n        summary.system_time += test_result.system_time\n\n        ram_usage_mb = test_result.ram_usage / 1000\n        if summary.max_ram_usage < ram_usage_mb:\n            summary.max_ram_usage = ram_usage_mb\n\n        summary.total_tests += 1\n        if test_result.status == TestStatus.PASSED:\n            summary.total_passed_tests += 1\n\n        if tool_info.name == \"\":\n            tool_info.name = test_log_data[\"runner\"]\n\n    _logger.info(\n        f\"{runner_name}: (Re)generated {rendered_count}/{tests_count} rendered log files.\"\n    )\n\n    all_used_tags: Set[str] = set()\n\n    for group_id, local_group in local_groups.items():\n        group = local_group.group\n        all_used_tags.update(group.tags.keys())\n        for tag_id, tag_tool_result in group.tags.items():\n            if tag_tool_result.status != TestStatus.NA:\n                group.summary.total_tested_tags += 1\n                if tag_tool_result.status == TestStatus.PASSED:\n                    group.summary.total_passed_tags += 1\n\n            tag_tool_result.tests.sort(key=lambda t: numericSortKey(t.name))\n\n        time = local_group.passed_tests_time\n        size = local_group.passed_tests_input_files_size\n        if time == 0:\n            group.summary.passed_throughput = 0\n        else:\n            group.summary.passed_throughput = size / time / 1024\n\n    for tag_id in all_used_tags:\n        # List of tag's test lists from all groups\n        tests_lists = [\n            lg.group.tags[tag_id].tests\n            for lg in local_groups.values()\n            if tag_id in lg.group.tags\n        ]\n        config_js = os.path.join(\n            _out_dir, \"results\", runner_name.lower(),\n            tag_id.lower() + \".config.js\")\n\n        # Render the config\n        renderTagResultsConfig(\n            config_js, runner_name, tag_id,\n            itertools.chain.from_iterable(tests_lists))\n\n    try:\n        with open(os.path.join(_logs_dir, runner_name, \"version\")) as f:\n            tool_info.version = f.read().strip()\n    except IOError:\n        pass\n\n    try:\n        with open(os.path.join(_logs_dir, runner_name, \"url\")) as f:\n            tool_info.url = f.read().strip()\n    except IOError:\n        pass\n\n    groups: Dict[str, PartialGroupData] = {\n        id: lg.group\n        for id, lg in local_groups.items()\n    }\n\n    return {\n        \"tool_info\": tool_info,\n        \"partial_groups\": groups,\n    }\n\n\ndef render_batch(input_files):\n    lex = lexers.get_lexer_by_name(\"systemverilog\")\n    batch_rendered_count = 0\n    for input_file in input_files:\n        input_file_html = os.path.join(_out_dir, input_file + \".html\")\n        if exists_and_is_newer_than(\n                input_file_html, [input_file, _src_template_file, __file__]):\n            continue\n        batch_rendered_count += 1\n        renderInputFileToHTMLFile(_out_dir, input_file_html, input_file, lex)\n    return batch_rendered_count\n\n\ndef main():\n    parser = argparse.ArgumentParser()\n\n    logger_args = parser.add_mutually_exclusive_group()\n\n    logger_args.add_argument(\n        \"-q\", \"--quiet\", action=\"store_true\", help=\"Disable all logs\")\n\n    logger_args.add_argument(\n        \"-v\", \"--verbose\", action=\"store_true\", help=\"Verbose logging\")\n\n    parser.add_argument(\n        \"-i\", \"--input\", help=\"Input database/LRM\", default=\"conf/lrm.conf\")\n\n    parser.add_argument(\n        \"-m\",\n        \"--meta-tags\",\n        help=\"Meta-tags config file\",\n        default=\"conf/meta-tags.conf\")\n\n    parser.add_argument(\n        \"-l\",\n        \"--logs\",\n        help=\"Directory with all the individual test results\",\n        default=\"out/logs\")\n\n    parser.add_argument(\n        \"--template\",\n        help=\"Path to the html report template\",\n        default=\"conf/report/report-template.html\")\n\n    parser.add_argument(\n        \"--navbar\",\n        help=\"Path to the html navbar template\",\n        default=\"conf/report/navbar-template.html\")\n\n    parser.add_argument(\n        \"--code-template\",\n        help=\"Path to the html code preview template\",\n        default=\"conf/report/code-template.html\")\n\n    parser.add_argument(\n        \"--log-template\",\n        help=\"Path to the html log template\",\n        default=\"conf/report/log-template.html\")\n\n    parser.add_argument(\n        \"-o\",\n        \"--out\",\n        help=\"Path to the html file with the report\",\n        default=\"out/report/index.html\")\n\n    parser.add_argument(\n        \"-c\",\n        \"--csv\",\n        help=\"Path to the csv file with the report\",\n        default=\"out/report/report.csv\")\n\n    parser.add_argument(\n        \"-r\", \"--revision\", help=\"Report revision\", default=\"unknown\")\n\n    # parse args\n    args = parser.parse_args()\n\n    init_logger(args.quiet, args.verbose)\n\n    # Common paths\n    out_dir = os.path.dirname(os.path.abspath(args.out))\n    top_dir = os.path.abspath(os.curdir)\n    logs_out_dir = os.path.join(out_dir, \"logs\")\n\n    # read meta-tags configuration\n    meta_tags, meta_urls = readConfig(args.meta_tags)\n\n    # generate input database first\n    database, urls = readConfig(args.input)\n    urls = {**urls, **meta_urls}\n\n    runner_names = []\n    for r in [os.path.dirname(r) for r in glob(args.logs + \"/*/\")]:\n        runner_name = os.path.basename(r)\n        _logger.debug(\"Found Runner: \" + runner_name)\n        runner_names.append(runner_name)\n\n    _logger.info(\n        \"Generating {} from log files in '{}'\".format(args.out, args.logs))\n\n    process_initargs = [\n        args.log_template,\n        args.code_template,\n        args.logs,\n        out_dir,\n        top_dir,\n        logs_out_dir,\n        args.quiet,\n        args.verbose,\n        meta_tags,\n    ]\n    results = None\n    with multiprocessing.Pool(initializer=init_globals,\n                              initargs=process_initargs) as pool:\n        results = pool.map(collect_logs, runner_names)\n\n    # Input files (.sv) path relative to repository's toplevel directory\n    all_input_files: Set[str] = set()\n    csv_output = {}\n    # Data passed to report template\n    report_data = ReportResults()\n    for tool_name, tool_results in zip(runner_names, results):\n        report_data.tools[tool_name] = tool_results[\"tool_info\"]\n        partial_groups: Dict[str,\n                             PartialGroupData] = tool_results[\"partial_groups\"]\n\n        for group_id, partial_group in partial_groups.items():\n            group = report_data.groups.setdefault(group_id, GroupData())\n            group.tests[tool_name] = partial_group.tests\n            group.summaries[tool_name] = partial_group.summary\n\n            for tag_id, tool_data in partial_group.tags.items():\n                tools = group.tags_tools.setdefault(tag_id, {})\n                tools[tool_name] = tool_data\n\n                if tag_id not in database and tag_id not in report_data.tags:\n                    _logger.warning(\n                        \"Tag not present in the database: \" + tag_id)\n                report_data.tags.setdefault(\n                    tag_id,\n                    TagInfo(\n                        description=database.get(tag_id, \"\"),\n                        url=urls.get(tag_id, \"\")))\n\n            for test_result in partial_group.tests:\n                all_input_files.update(test_result.input_files)\n\n                unique_row = test_result.name + \":\" + tool_name\n\n                csv_output[unique_row] = {\n                    \"TestName\": test_result.name,\n                    \"Tool\": tool_name,\n                    \"Group\": test_result.results_group,\n                    \"Pass\": test_result.status == TestStatus.PASSED,\n                    \"ExitCode\": test_result.exit_code,\n                    \"Tags\": \" \".join(test_result.tags),\n                    \"InputBytes\": test_result.total_input_files_size,\n                    \"AllowedTimeout\": test_result.timeout,\n                    \"TimeUser\": round(test_result.user_time, 6),\n                    \"TimeSystem\": round(test_result.system_time, 6),\n                    \"TimeWall\": round(test_result.total_time, 6),\n                    \"RamUsageMiB\": round(test_result.ram_usage / 1024, 3),\n                }\n\n    ncpu = multiprocessing.cpu_count()\n    batch_size = int(len(all_input_files) / ncpu) + 1\n    file_batches = []\n    for i in range(0, len(all_input_files), batch_size):\n        file_batches.append(list(all_input_files)[i:i + batch_size])\n\n    # Render input files\n    rendered_count = 0\n    with multiprocessing.Pool(initializer=init_globals,\n                              initargs=process_initargs) as pool:\n        rendered_count = sum(pool.map(render_batch, file_batches))\n\n    _logger.info(\n        f\"(Re)generated {rendered_count}/{len(all_input_files)} rendered input files.\"\n    )\n\n    try:\n        template_dir = os.path.dirname(args.log_template)\n        jinja2env = ReportJinja2Env(template_dir)\n        with open(args.template, \"r\") as f:\n            report = jinja2env.from_string(f.read())\n\n        build_id = os.environ.get('GITHUB_RUN_ID', 'local')\n        build_datetime = datetime.datetime.now().strftime(\"%Y-%m-%d %H:%M:%S\")\n\n        with open(args.out, 'w') as f:\n            f.write(\n                report.render(\n                    report=report_data,\n                    revision=args.revision,\n                    build_id=build_id,\n                    datetime=build_datetime))\n\n        with open(args.csv, 'w', newline='') as csvfile:\n            writer = csv.DictWriter(csvfile, fieldnames=_csv_header)\n            writer.writeheader()\n            for test in csv_output:\n                writer.writerow(csv_output[test])\n    except KeyError:\n        _logger.critical(\"Unable to generate report, not enough logs\")\n    except Exception as e:\n        _logger.critical(\"Unable to generate report: \" + str(e))\n\n\nif __name__ == \"__main__\":\n    main()\n"
  }
]