Repository: chipsalliance/sv-tests Branch: master Commit: 69ec9d1f8a77 Files: 1153 Total size: 1.0 MB Directory structure: gitextract_v_hu2ggc/ ├── .editorconfig ├── .github/ │ ├── dependabot.yml │ └── workflows/ │ ├── comment-pr.yml │ ├── lint-review.yml │ ├── report.sh │ ├── summary.sh │ ├── sv-tests-ci.yml │ ├── sv-tests-code-quality.yml │ └── update_report.sh ├── .gitignore ├── .gitmodules ├── .style.yapf ├── AUTHORS ├── LICENSE ├── Makefile ├── README.md ├── conf/ │ ├── environment.yml │ ├── feature-analyzer/ │ │ ├── keywords.yml │ │ ├── operators.yml │ │ └── tags.yml │ ├── fusesoc-configs/ │ │ ├── ibex-sim.yml │ │ ├── veer-eh1-sim.yml │ │ └── veer-eh1-synth.yml │ ├── generators/ │ │ ├── meta-path/ │ │ │ ├── basejump.json │ │ │ ├── hdlconvertor.json │ │ │ ├── hdlconvertor_std2012.json │ │ │ ├── hdlconvertor_std2017.json │ │ │ ├── projf-explore.json │ │ │ ├── utd-systemverilog.json │ │ │ ├── yosys-asicworld.json │ │ │ ├── yosys-errors.json │ │ │ ├── yosys-memories.json │ │ │ ├── yosys-simple.json │ │ │ ├── yosys-sva.json │ │ │ └── yosys-svinterfaces.json │ │ └── templates/ │ │ ├── assignment-sim.json │ │ ├── assignment.json │ │ ├── binary.json │ │ ├── encapsulation-fail.json │ │ ├── encapsulation-success.json │ │ ├── equality.json │ │ ├── force-assignments.json │ │ ├── integers.json │ │ ├── keywords.json │ │ ├── logical-equiv.json │ │ ├── logical-impl.json │ │ ├── logical.json │ │ ├── nets.json │ │ ├── operators-sim.json │ │ ├── sampled-functions-gclk.json │ │ ├── sampled-functions.json │ │ ├── simple-logical.json │ │ ├── simple-operators-sim.json │ │ ├── simple-unary.json │ │ ├── trig-functions.json │ │ ├── unary.json │ │ ├── uniquecase.json │ │ ├── uvm-classes_0.json │ │ ├── uvm-classes_0.sv │ │ ├── uvm-classes_1.json │ │ ├── uvm-classes_1.sv │ │ ├── uvm-classes_2.json │ │ ├── uvm-classes_3.json │ │ ├── uvm-classes_3.sv │ │ ├── wildcard-const.json │ │ └── wildcard.json │ ├── lrm.conf │ ├── meta-tags.conf │ ├── report/ │ │ ├── code-template.html │ │ ├── code.css │ │ ├── details-view.css │ │ ├── filter.js │ │ ├── filter_ui_test.py │ │ ├── footer.html │ │ ├── history-graph-template.html │ │ ├── log-template.html │ │ ├── log.css │ │ ├── navbar.html │ │ ├── report-template.html │ │ ├── report.css │ │ └── report.js │ ├── requirements.txt │ └── runners/ │ └── libs.json ├── generators/ │ ├── ariane │ ├── black-parrot │ ├── easyUVM │ ├── fusesoc │ ├── fx68k │ ├── ivtest │ ├── path_generator │ ├── rggen │ ├── rsd │ ├── scr1 │ ├── template_generator │ ├── tnoc │ ├── veer-config │ └── yosys_hana ├── tests/ │ ├── README.md │ ├── chapter-10/ │ │ ├── 10.3--proc-assignment--bad.sv │ │ ├── 10.3.1--net-decl-assignment.sv │ │ ├── 10.3.1--one-net.sv │ │ ├── 10.3.2--cont-assignment.sv │ │ ├── 10.3.3--cont-assignment-delay.sv │ │ ├── 10.3.3--cont-assignment-net-delay.sv │ │ ├── 10.4.1--blocking-assignment.sv │ │ ├── 10.4.2--non-blocking-assignment.sv │ │ ├── 10.6.1--assign-deassign.sv │ │ └── 10.6.2--force-release.sv │ ├── chapter-11/ │ │ ├── 11.10--string_bit_array-sim.sv │ │ ├── 11.10--string_bit_array.sv │ │ ├── 11.10.1--string_compare.sv │ │ ├── 11.10.1--string_concat.sv │ │ ├── 11.10.1--string_copy.sv │ │ ├── 11.10.3--empty_string-sim.sv │ │ ├── 11.10.3--empty_string.sv │ │ ├── 11.11--min_max_avg_delay.sv │ │ ├── 11.12--let_construct.sv │ │ ├── 11.3.5--expr_short_circuit.sv │ │ ├── 11.3.6--assign_in_exp-sim.sv │ │ ├── 11.3.6--assign_in_exp.sv │ │ ├── 11.3.6--assign_in_expr-sim.sv │ │ ├── 11.3.6--assign_in_expr.sv │ │ ├── 11.3.6--assign_in_expr_inv.sv │ │ ├── 11.3.6--assign_in_expression-sim.sv │ │ ├── 11.3.6--assign_in_expression.sv │ │ ├── 11.3.6--assignment_in_expression-sim.sv │ │ ├── 11.3.6--assignment_in_expression.sv │ │ ├── 11.3.6--two_assign_in_expr-sim.sv │ │ ├── 11.3.6--two_assign_in_expr.sv │ │ ├── 11.4.1--assignment-sim.sv │ │ ├── 11.4.10--arith-shift-assignment-signed.sv │ │ ├── 11.4.10--arith-shift-assignment-unsigned.sv │ │ ├── 11.4.10--arith-shift-signed.sv │ │ ├── 11.4.10--arith-shift-unsigned.sv │ │ ├── 11.4.11--cond_op-sim.sv │ │ ├── 11.4.11--cond_op.sv │ │ ├── 11.4.12--concat_op-bit_select.sv │ │ ├── 11.4.12--concat_op-sim.sv │ │ ├── 11.4.12--concat_op.sv │ │ ├── 11.4.12.1--nested_repl_op-sim.sv │ │ ├── 11.4.12.1--nested_repl_op.sv │ │ ├── 11.4.12.1--repl_op-sim.sv │ │ ├── 11.4.12.1--repl_op.sv │ │ ├── 11.4.12.2--string_concat_op.sv │ │ ├── 11.4.12.2--string_repl_op.sv │ │ ├── 11.4.13--set_member-sim.sv │ │ ├── 11.4.13--set_member.sv │ │ ├── 11.4.14.1--stream_concat-sim.sv │ │ ├── 11.4.14.1--stream_concat.sv │ │ ├── 11.4.14.2--reorder_stream-sim.sv │ │ ├── 11.4.14.2--reorder_stream.sv │ │ ├── 11.4.14.2--reorder_stream_byte-sim.sv │ │ ├── 11.4.14.2--reorder_stream_byte.sv │ │ ├── 11.4.14.3--unpack_stream-sim.sv │ │ ├── 11.4.14.3--unpack_stream.sv │ │ ├── 11.4.14.3--unpack_stream_inv.sv │ │ ├── 11.4.14.3--unpack_stream_pad-sim.sv │ │ ├── 11.4.14.3--unpack_stream_pad.sv │ │ ├── 11.4.14.4--dynamic_array_stream-sim.sv │ │ ├── 11.4.14.4--dynamic_array_stream.sv │ │ ├── 11.4.14.4--dynamic_array_stream_with.sv │ │ ├── 11.4.2--unary_op_dec-sim.sv │ │ ├── 11.4.2--unary_op_dec.sv │ │ ├── 11.4.2--unary_op_inc-sim.sv │ │ ├── 11.4.2--unary_op_inc.sv │ │ ├── 11.4.5--equality-op.sv │ │ ├── 11.5.1--idx_neg_part_select-sim.sv │ │ ├── 11.5.1--idx_neg_part_select.sv │ │ ├── 11.5.1--idx_pos_part_select-sim.sv │ │ ├── 11.5.1--idx_pos_part_select.sv │ │ ├── 11.5.1--idx_select-sim.sv │ │ ├── 11.5.1--idx_select.sv │ │ ├── 11.5.1--non_idx_part_select-sim.sv │ │ ├── 11.5.1--non_idx_part_select.sv │ │ ├── 11.5.2--array_addressing-sim.sv │ │ ├── 11.5.2--array_addressing.sv │ │ ├── 11.5.2--multi_dim_array_addressing-sim.sv │ │ ├── 11.5.2--multi_dim_array_addressing.sv │ │ ├── 11.7--signed_func-sim.sv │ │ ├── 11.7--signed_func.sv │ │ ├── 11.7--unsigned_func-sim.sv │ │ ├── 11.7--unsigned_func.sv │ │ ├── 11.9--tagged_union.sv │ │ ├── 11.9--tagged_union_member_access-sim.sv │ │ ├── 11.9--tagged_union_member_access.sv │ │ ├── 11.9--tagged_union_member_access_inv.sv │ │ └── simple/ │ │ ├── 11.4.11--simple_cond_op-sim.sv │ │ ├── 11.4.12--simple_concat_op-sim.sv │ │ ├── 11.4.12.1--simple_repl_op-sim.sv │ │ ├── 11.4.13--simple_set_member-sim.sv │ │ ├── 11.4.14.3--simple_unpack_stream-sim.sv │ │ ├── 11.5.1--simple_idx_neg_part_select-sim.sv │ │ ├── 11.5.1--simple_idx_pos_part_select-sim.sv │ │ ├── 11.5.1--simple_idx_select-sim.sv │ │ ├── 11.5.1--simple_non_idx_part_select-sim.sv │ │ └── 11.5.2--simple_array_addressing-sim.sv │ ├── chapter-12/ │ │ ├── 12.4--if.sv │ │ ├── 12.4--if_else.sv │ │ ├── 12.4.1--if_else_if.sv │ │ ├── 12.4.2--priority_if.sv │ │ ├── 12.4.2--unique0_if.sv │ │ ├── 12.4.2--unique_if.sv │ │ ├── 12.5--case.sv │ │ ├── 12.5.1--casex.sv │ │ ├── 12.5.1--casez.sv │ │ ├── 12.5.2--case_const.sv │ │ ├── 12.5.4--case_set.sv │ │ ├── 12.6.1--case_pattern.sv │ │ ├── 12.6.1--casex_pattern.sv │ │ ├── 12.6.1--casez_pattern.sv │ │ ├── 12.6.2--if_pattern.sv │ │ ├── 12.6.3--conditional_pattern.sv │ │ ├── 12.7.1--for.sv │ │ ├── 12.7.2--repeat.sv │ │ ├── 12.7.3--foreach-synth.sv │ │ ├── 12.7.3--foreach.sv │ │ ├── 12.7.4--while.sv │ │ ├── 12.7.5--dowhile.sv │ │ ├── 12.7.6--forever.sv │ │ ├── 12.8--break.sv │ │ ├── 12.8--continue.sv │ │ ├── 12.8--return.sv │ │ └── 12.8--return_val.sv │ ├── chapter-13/ │ │ ├── 13.3--task-label.sv │ │ ├── 13.3--task.sv │ │ ├── 13.3.1--task-automatic.sv │ │ ├── 13.3.1--task-static.sv │ │ ├── 13.4--function-label.sv │ │ ├── 13.4--function.sv │ │ ├── 13.4.1--function-return-assignment.sv │ │ ├── 13.4.1--function-return.sv │ │ ├── 13.4.1--function-void-return.sv │ │ ├── 13.4.2--function-automatic.sv │ │ ├── 13.4.2--function-recursive.sv │ │ ├── 13.4.2--function-static.sv │ │ ├── 13.4.3--const-function.sv │ │ ├── 13.4.4--fork-invalid.sv │ │ └── 13.4.4--fork-valid.sv │ ├── chapter-14/ │ │ ├── 14.3--clocking-block-signals-error.sv │ │ ├── 14.3--clocking-block-signals.sv │ │ ├── 14.3--clocking-block.sv │ │ ├── 14.3--default-clocking-block.sv │ │ └── 14.3--global-clocking-block.sv │ ├── chapter-15/ │ │ ├── 15.4--mailbox-blocking.sv │ │ ├── 15.4--mailbox-non-blocking.sv │ │ ├── 15.5.1--named-event-trigger-blocking.sv │ │ ├── 15.5.1--named-event-trigger-non-blocking.sv │ │ └── 15.5.2--named-event-wait.sv │ ├── chapter-16/ │ │ ├── 16.10--property-local-var-fail.sv │ │ ├── 16.10--property-local-var-uvm.sv │ │ ├── 16.10--property-local-var.sv │ │ ├── 16.10--sequence-local-var-fail.sv │ │ ├── 16.10--sequence-local-var-uvm.sv │ │ ├── 16.10--sequence-local-var.sv │ │ ├── 16.11--sequence-subroutine-uvm.sv │ │ ├── 16.12--property-disable-iff.sv │ │ ├── 16.12--property-disj.sv │ │ ├── 16.12--property-iff.sv │ │ ├── 16.12--property-interface-prec-uvm.sv │ │ ├── 16.12--property-interface-uvm.sv │ │ ├── 16.12--property-prec-uvm.sv │ │ ├── 16.12--property-prec.sv │ │ ├── 16.12--property-uvm.sv │ │ ├── 16.12--property.sv │ │ ├── 16.13--sequence-multiclock-uvm.sv │ │ ├── 16.14--assume-property-uvm.sv │ │ ├── 16.14--assume-property.sv │ │ ├── 16.15--property-disable-iff-fail.sv │ │ ├── 16.15--property-disable-iff.sv │ │ ├── 16.15--property-iff-uvm.sv │ │ ├── 16.17--expect-uvm.sv │ │ ├── 16.17--expect.sv │ │ ├── 16.2--assert-final-uvm.sv │ │ ├── 16.2--assert-final.sv │ │ ├── 16.2--assert-uvm.sv │ │ ├── 16.2--assert.sv │ │ ├── 16.2--assert0-uvm.sv │ │ ├── 16.2--assert0.sv │ │ ├── 16.2--assume-final.sv │ │ ├── 16.2--assume-uvm.sv │ │ ├── 16.2--assume.sv │ │ ├── 16.2--assume0.sv │ │ ├── 16.2--cover-final.sv │ │ ├── 16.2--cover.sv │ │ ├── 16.2--cover0.sv │ │ ├── 16.7--sequence-and-range-uvm.sv │ │ ├── 16.7--sequence-and-uvm.sv │ │ ├── 16.7--sequence-intersect-uvm.sv │ │ ├── 16.7--sequence-or-uvm.sv │ │ ├── 16.7--sequence-throughout-uvm.sv │ │ ├── 16.7--sequence-uvm.sv │ │ ├── 16.7--sequence.sv │ │ ├── 16.9--sequence-changed-uvm.sv │ │ ├── 16.9--sequence-cons-repetition.sv │ │ ├── 16.9--sequence-fell-uvm.sv │ │ ├── 16.9--sequence-goto-repetition.sv │ │ ├── 16.9--sequence-noncons-repetition.sv │ │ ├── 16.9--sequence-past-uvm.sv │ │ ├── 16.9--sequence-rose-uvm.sv │ │ └── 16.9--sequence-stable-uvm.sv │ ├── chapter-18/ │ │ ├── 18.10--dynamic-constraint-modification_0.sv │ │ ├── 18.11--in-line-random-variable-control_0.sv │ │ ├── 18.11--in-line-random-variable-control_1.sv │ │ ├── 18.11.1--in-line-constraint-checker_0.sv │ │ ├── 18.11.1--in-line-constraint-checker_1.sv │ │ ├── 18.12--randomization-of-scope-variables_0.sv │ │ ├── 18.12--randomization-of-scope-variables_1.sv │ │ ├── 18.12.1--adding-constraints-to-scope-variables_0.sv │ │ ├── 18.12.1--adding-constraints-to-scope-variables_1.sv │ │ ├── 18.13.1--urandom_0.sv │ │ ├── 18.13.1--urandom_1.sv │ │ ├── 18.13.1--urandom_2.sv │ │ ├── 18.13.1--urandom_3.sv │ │ ├── 18.13.2--urandom_range_0.sv │ │ ├── 18.13.2--urandom_range_1.sv │ │ ├── 18.13.2--urandom_range_2.sv │ │ ├── 18.13.2--urandom_range_3.sv │ │ ├── 18.13.3--srandom_0.sv │ │ ├── 18.13.4--get_randstate_0.sv │ │ ├── 18.13.5--set_randstate_0.sv │ │ ├── 18.14--random-stability_0.sv │ │ ├── 18.14--random-stability_1.sv │ │ ├── 18.14--random-stability_2.sv │ │ ├── 18.14--random-stability_3.sv │ │ ├── 18.14.2--thread-stability_0.sv │ │ ├── 18.14.2--thread-stability_1.sv │ │ ├── 18.14.3--object-stability_0.sv │ │ ├── 18.14.3--object-stability_1.sv │ │ ├── 18.15--manually-seeding-randomize_0.sv │ │ ├── 18.15--manually-seeding-randomize_1.sv │ │ ├── 18.16--random-weighted-case-randcase_0.sv │ │ ├── 18.16--random-weighted-case-randcase_2.sv │ │ ├── 18.17--random-sequence-generation-randsequence_0.sv │ │ ├── 18.17--random-sequence-generation-randsequence_2.sv │ │ ├── 18.17.1--random-production-weights_0.sv │ │ ├── 18.17.2--if-else-production-statements_0.sv │ │ ├── 18.17.2--if-else-production-statements_0_fail.sv │ │ ├── 18.17.2--if-else-production-statements_2.sv │ │ ├── 18.17.2--if-else-production-statements_2_fail.sv │ │ ├── 18.17.3--case-production-statements_0.sv │ │ ├── 18.17.3--case-production-statements_0_fail.sv │ │ ├── 18.17.4--repeat-production-statements_0.sv │ │ ├── 18.17.5--interleaving-productions-rand-join_0.sv │ │ ├── 18.17.5--interleaving-productions-rand-join_2.sv │ │ ├── 18.17.6--aborting-productions-break-and-return_0.sv │ │ ├── 18.17.6--aborting-productions-break-and-return_2.sv │ │ ├── 18.17.6--aborting-productions-break-and-return_2_fail.sv │ │ ├── 18.17.7--value-passing-between-productions_0.sv │ │ ├── 18.4.1--rand-modifier.sv │ │ ├── 18.4.2--randc-modifier.sv │ │ ├── 18.5--constraint-blocks_0.sv │ │ ├── 18.5--constraint-blocks_1.sv │ │ ├── 18.5.1--explicit-external-constraint_0.sv │ │ ├── 18.5.1--explicit-external-constraint_1.sv │ │ ├── 18.5.1--explicit-external-constraint_2.sv │ │ ├── 18.5.1--implicit-external-constraint_0.sv │ │ ├── 18.5.1--implicit-external-constraint_1.sv │ │ ├── 18.5.1--implicit-external-constraint_2.sv │ │ ├── 18.5.10--variable-ordering_0.sv │ │ ├── 18.5.10--variable-ordering_1.sv │ │ ├── 18.5.11--static-constraint-blocks_0.sv │ │ ├── 18.5.11--static-constraint-blocks_1.sv │ │ ├── 18.5.12--functions-in-constraint_0.sv │ │ ├── 18.5.12--functions-in-constraint_1.sv │ │ ├── 18.5.13--constraint-guards_0.sv │ │ ├── 18.5.13--constraint-guards_1.sv │ │ ├── 18.5.14--soft-constraints_0.sv │ │ ├── 18.5.14--soft-constraints_1.sv │ │ ├── 18.5.14--soft-constraints_2.sv │ │ ├── 18.5.14.1--soft-constraint-priorities_0.sv │ │ ├── 18.5.14.1--soft-constraint-priorities_1.sv │ │ ├── 18.5.14.1--soft-constraint-priorities_2.sv │ │ ├── 18.5.14.1--soft-constraint-priorities_3.sv │ │ ├── 18.5.14.1--soft-constraint-priorities_4.sv │ │ ├── 18.5.14.2--discarding-soft-constraints_0.sv │ │ ├── 18.5.14.2--discarding-soft-constraints_1.sv │ │ ├── 18.5.14.2--discarding-soft-constraints_2.sv │ │ ├── 18.5.14.2--discarding-soft-constraints_3.sv │ │ ├── 18.5.14.2--discarding-soft-constraints_5.sv │ │ ├── 18.5.2--constraint-inheritance_0.sv │ │ ├── 18.5.2--constraint-inheritance_1.sv │ │ ├── 18.5.2--pure-constraint_0.sv │ │ ├── 18.5.2--pure-constraint_1.sv │ │ ├── 18.5.2--pure-constraint_2.sv │ │ ├── 18.5.2--pure-constraint_3.sv │ │ ├── 18.5.3--set-membership_0.sv │ │ ├── 18.5.3--set-membership_1.sv │ │ ├── 18.5.4--distribution_0.sv │ │ ├── 18.5.4--distribution_1.sv │ │ ├── 18.5.4--distribution_2.sv │ │ ├── 18.5.5--uniqueness-constraints_0.sv │ │ ├── 18.5.5--uniqueness-constraints_1.sv │ │ ├── 18.5.6--implication_0.sv │ │ ├── 18.5.6--implication_1.sv │ │ ├── 18.5.7--if-else-constraints_0.sv │ │ ├── 18.5.7--if-else-constraints_1.sv │ │ ├── 18.5.7--if-else-constraints_2.sv │ │ ├── 18.5.7--if-else-constraints_3.sv │ │ ├── 18.5.7--if-else-constraints_4.sv │ │ ├── 18.5.8.1--foreach-iterative-constraints_0.sv │ │ ├── 18.5.8.1--foreach-iterative-constraints_1.sv │ │ ├── 18.5.8.2--array-reduction-iterative-constraints_0.sv │ │ ├── 18.5.8.2--array-reduction-iterative-constraints_1.sv │ │ ├── 18.5.9--global-constraints_0.sv │ │ ├── 18.5.9--global-constraints_1.sv │ │ ├── 18.6.1--randomize-method_0.sv │ │ ├── 18.6.2--post-randomize_method_0.sv │ │ ├── 18.6.2--post-randomize_method_1.sv │ │ ├── 18.6.2--pre-randomize-method_0.sv │ │ ├── 18.6.2--pre-randomize-method_1.sv │ │ ├── 18.6.3--behavior-of-randomization-methods_0.sv │ │ ├── 18.6.3--behavior-of-randomization-methods_1.sv │ │ ├── 18.6.3--behavior-of-randomization-methods_2.sv │ │ ├── 18.6.3--behavior-of-randomization-methods_3.sv │ │ ├── 18.6.3--behavior-of-randomization-methods_4.sv │ │ ├── 18.6.3--behavior-of-randomization-methods_5.sv │ │ ├── 18.7--in-line-constraints--randomize_0.sv │ │ ├── 18.7--in-line-constraints--randomize_1.sv │ │ ├── 18.7--in-line-constraints--randomize_2.sv │ │ ├── 18.7--in-line-constraints--randomize_3.sv │ │ ├── 18.7--in-line-constraints--randomize_4.sv │ │ ├── 18.7--in-line-constraints--randomize_5.sv │ │ ├── 18.7--in-line-constraints--randomize_6.sv │ │ ├── 18.7.1--local-scope-resolution_0.sv │ │ ├── 18.7.1--local-scope-resolution_1.sv │ │ ├── 18.8--disabling-random-variables-with-rand_mode_0.sv │ │ ├── 18.8--disabling-random-variables-with-rand_mode_1.sv │ │ ├── 18.8--disabling-random-variables-with-rand_mode_2.sv │ │ ├── 18.8--disabling-random-variables-with-rand_mode_3.sv │ │ ├── 18.8--disabling-random-variables-with-rand_mode_4.sv │ │ ├── 18.8--disabling-random-variables-with-rand_mode_5.sv │ │ ├── 18.9--controlling-constraints-with-constraint_mode_0.sv │ │ ├── 18.9--controlling-constraints-with-constraint_mode_1.sv │ │ └── 18.9--controlling-constraints-with-constraint_mode_2.sv │ ├── chapter-20/ │ │ ├── 20.10--error.sv │ │ ├── 20.10--fatal.sv │ │ ├── 20.10--info.sv │ │ ├── 20.10--warning.sv │ │ ├── 20.14--coverage.sv │ │ ├── 20.15--dist_chi_square.sv │ │ ├── 20.15--dist_erlang.sv │ │ ├── 20.15--dist_exponential.sv │ │ ├── 20.15--dist_normal.sv │ │ ├── 20.15--dist_poisson.sv │ │ ├── 20.15--dist_t.sv │ │ ├── 20.15--dist_uniform.sv │ │ ├── 20.15--random.sv │ │ ├── 20.2--exit.sv │ │ ├── 20.2--finish.sv │ │ ├── 20.2--stop.sv │ │ ├── 20.3--realtime.sv │ │ ├── 20.3--stime.sv │ │ ├── 20.3--time.sv │ │ ├── 20.4--printtimescale-hier.sv │ │ ├── 20.4--printtimescale.sv │ │ ├── 20.4--timeformat.sv │ │ ├── 20.5--itor.sv │ │ ├── 20.5--real-bits-conv.sv │ │ ├── 20.5--rtoi.sv │ │ ├── 20.5--shortreal-bits-conv.sv │ │ ├── 20.6--bits.sv │ │ ├── 20.6--bits_type.sv │ │ ├── 20.6--isunbounded.sv │ │ ├── 20.6--typename.sv │ │ ├── 20.6--typename_type.sv │ │ ├── 20.7--array-queries-multi-dim.sv │ │ ├── 20.7--array-queries.sv │ │ ├── 20.8--atan2.sv │ │ ├── 20.8--ceil.sv │ │ ├── 20.8--clog2.sv │ │ ├── 20.8--exp.sv │ │ ├── 20.8--floor.sv │ │ ├── 20.8--hypot.sv │ │ ├── 20.8--ln.sv │ │ ├── 20.8--log10.sv │ │ ├── 20.8--pow.sv │ │ ├── 20.8--sqrt.sv │ │ ├── 20.9--countbits.sv │ │ ├── 20.9--isunknown.sv │ │ ├── 20.9--onehot.sv │ │ └── 20.9--onehot0.sv │ ├── chapter-21/ │ │ ├── 21.2--display-boh.sv │ │ ├── 21.2--display.sv │ │ ├── 21.2--monitor.sv │ │ ├── 21.2--strobe.sv │ │ ├── 21.2--write-boh.sv │ │ ├── 21.2--write.sv │ │ ├── 21.3--fdisplay-boh.sv │ │ ├── 21.3--fdisplay.sv │ │ ├── 21.3--feof.sv │ │ ├── 21.3--ferror.sv │ │ ├── 21.3--fflush.sv │ │ ├── 21.3--fgetc.sv │ │ ├── 21.3--fgets.sv │ │ ├── 21.3--file.sv │ │ ├── 21.3--fmonitor.sv │ │ ├── 21.3--fpos.sv │ │ ├── 21.3--fread.sv │ │ ├── 21.3--fscanf.sv │ │ ├── 21.3--fstrobe.sv │ │ ├── 21.3--fwrite-boh.sv │ │ ├── 21.3--fwrite.sv │ │ ├── 21.3--sscanf.sv │ │ ├── 21.3--ungetc.sv │ │ ├── 21.4--readmemb.sv │ │ ├── 21.4--readmemh.sv │ │ ├── 21.6--test.sv │ │ ├── 21.6--value.sv │ │ ├── 21.7--dumpfile.sv │ │ └── 21.7--dumpports.sv │ ├── chapter-22/ │ │ ├── 22.10--celldefine-basic-1.sv │ │ ├── 22.10--celldefine-basic-2.sv │ │ ├── 22.11--pragma-basic.sv │ │ ├── 22.11--pragma-complex.sv │ │ ├── 22.11--pragma-invalid.sv │ │ ├── 22.11--pragma-nested.sv │ │ ├── 22.11--pragma-number-multi.sv │ │ ├── 22.11--pragma-number.sv │ │ ├── 22.12--line-basic.sv │ │ ├── 22.12--line-complex.sv │ │ ├── 22.12--line-illegal-1.sv │ │ ├── 22.12--line-illegal-2.sv │ │ ├── 22.12--line-illegal-3.sv │ │ ├── 22.12--line-illegal-4.sv │ │ ├── 22.12--line-illegal-5.sv │ │ ├── 22.3--resetall_basic.sv │ │ ├── 22.3--resetall_illegal.sv │ │ ├── 22.3--resetall_multiple.sv │ │ ├── 22.4--check_included_definitions.sv │ │ ├── 22.4--include_basic.sv │ │ ├── 22.4--include_basic_rpath.sv │ │ ├── 22.4--include_from_other_directory.sv │ │ ├── 22.4--include_via_define.sv │ │ ├── 22.4--include_with_comment.sv │ │ ├── 22.5.1--define-expansion_1.sv │ │ ├── 22.5.1--define-expansion_10.sv │ │ ├── 22.5.1--define-expansion_11.sv │ │ ├── 22.5.1--define-expansion_12.sv │ │ ├── 22.5.1--define-expansion_13.sv │ │ ├── 22.5.1--define-expansion_14.sv │ │ ├── 22.5.1--define-expansion_15.sv │ │ ├── 22.5.1--define-expansion_16.sv │ │ ├── 22.5.1--define-expansion_17.sv │ │ ├── 22.5.1--define-expansion_18.sv │ │ ├── 22.5.1--define-expansion_19.sv │ │ ├── 22.5.1--define-expansion_2.sv │ │ ├── 22.5.1--define-expansion_20.sv │ │ ├── 22.5.1--define-expansion_21.sv │ │ ├── 22.5.1--define-expansion_22.sv │ │ ├── 22.5.1--define-expansion_23.sv │ │ ├── 22.5.1--define-expansion_24.sv │ │ ├── 22.5.1--define-expansion_25.sv │ │ ├── 22.5.1--define-expansion_26.sv │ │ ├── 22.5.1--define-expansion_3.sv │ │ ├── 22.5.1--define-expansion_4.sv │ │ ├── 22.5.1--define-expansion_5.sv │ │ ├── 22.5.1--define-expansion_6.sv │ │ ├── 22.5.1--define-expansion_7.sv │ │ ├── 22.5.1--define-expansion_8.sv │ │ ├── 22.5.1--define-expansion_9.sv │ │ ├── 22.5.1--define.sv │ │ ├── 22.5.1--define_and_resetall.sv │ │ ├── 22.5.1--include-define-expansion.sv │ │ ├── 22.5.2--undef-basic.sv │ │ ├── 22.5.2--undef-nonexisting.sv │ │ ├── 22.5.3--undefineall-and-redefine.sv │ │ ├── 22.5.3--undefineall-basic.sv │ │ ├── 22.6--ifdef-behavioral.sv │ │ ├── 22.6--ifdef-chained-nested.sv │ │ ├── 22.6--ifdef-nested.sv │ │ ├── 22.7--timescale-basic-1.sv │ │ ├── 22.7--timescale-basic-2.sv │ │ ├── 22.7--timescale-basic-3.sv │ │ ├── 22.7--timescale-basic-4.sv │ │ ├── 22.7--timescale-module.sv │ │ ├── 22.7--timescale-reset.sv │ │ ├── 22.8--default_nettype-redefinition.sv │ │ ├── 22.8--default_nettype.sv │ │ ├── 22.9--unconnected_drive-basic-2.sv │ │ ├── 22.9--unconnected_drive-basic.sv │ │ ├── 22.9--unconnected_drive-invalid-1.sv │ │ ├── 22.9--unconnected_drive-invalid-2.sv │ │ ├── 22.9--unconnected_drive-invalid-3.sv │ │ ├── dummy_include.sv │ │ └── include_directory/ │ │ └── defs.sv │ ├── chapter-23/ │ │ ├── 23.2--macromodule-definition.sv │ │ ├── 23.2--module-definition.sv │ │ └── 23.2--module-label.sv │ ├── chapter-24/ │ │ └── 24.3--program.sv │ ├── chapter-25/ │ │ └── 25.3-interface.sv │ ├── chapter-26/ │ │ ├── 26.2--package-decl.sv │ │ └── 26.3--package-ref.sv │ ├── chapter-5/ │ │ ├── 5.10-structure-arrays-illegal.sv │ │ ├── 5.10-structure-arrays.sv │ │ ├── 5.10-structure-replication.sv │ │ ├── 5.10-structures.sv │ │ ├── 5.11-arrays-key-index.sv │ │ ├── 5.11-arrays-replication.sv │ │ ├── 5.11-arrays.sv │ │ ├── 5.12-attributes-case.sv │ │ ├── 5.12-attributes-conditional.sv │ │ ├── 5.12-attributes-module.sv │ │ ├── 5.12-attributes-operator.sv │ │ ├── 5.12-attributes-variable.sv │ │ ├── 5.13-builtin-methods-strings.sv │ │ ├── 5.4--coments.sv │ │ ├── 5.6--identifiers.sv │ │ ├── 5.6--wrong-identifiers.sv │ │ ├── 5.6.1--escaped-identifiers.sv │ │ ├── 5.6.1--nonescaped-access.sv │ │ ├── 5.6.3--system-functions.sv │ │ ├── 5.6.4--compiler-directives-begin-keywords.sv │ │ ├── 5.6.4--compiler-directives-celldefine.sv │ │ ├── 5.6.4--compiler-directives-debug-line.sv │ │ ├── 5.6.4--compiler-directives-debug.sv │ │ ├── 5.6.4--compiler-directives-default-nettype.sv │ │ ├── 5.6.4--compiler-directives-define.sv │ │ ├── 5.6.4--compiler-directives-include.sv │ │ ├── 5.6.4--compiler-directives-pragma.sv │ │ ├── 5.6.4--compiler-directives-preprocessor-macro_0.sv │ │ ├── 5.6.4--compiler-directives-preprocessor-macro_1.sv │ │ ├── 5.6.4--compiler-directives-resetall.sv │ │ ├── 5.6.4--compiler-directives-timescale.sv │ │ ├── 5.6.4--compiler-directives-unconnected-drive.sv │ │ ├── 5.7.1--integers-left-padding-bit.sv │ │ ├── 5.7.1--integers-left-padding.sv │ │ ├── 5.7.1--integers-signed-illegal.sv │ │ ├── 5.7.1--integers-signed.sv │ │ ├── 5.7.1--integers-sized.sv │ │ ├── 5.7.1--integers-token.sv │ │ ├── 5.7.1--integers-underscores.sv │ │ ├── 5.7.1--integers-unsized-illegal.sv │ │ ├── 5.7.1--integers-unsized.sv │ │ ├── 5.7.2-real-constants-illegal.sv │ │ ├── 5.7.2-real-constants.sv │ │ ├── 5.7.2-real-token.sv │ │ ├── 5.8-time-literals.sv │ │ ├── 5.9-string-assignment.sv │ │ ├── 5.9-string-basics.sv │ │ ├── 5.9-string-broken-line.sv │ │ ├── 5.9-string-word-assignment.sv │ │ └── 5.9.1-string-special-chars.sv │ ├── chapter-6/ │ │ ├── 6.10--implicit_continuous_assignment.sv │ │ ├── 6.10--implicit_port.sv │ │ ├── 6.10--implicit_port_connection.sv │ │ ├── 6.12--real.sv │ │ ├── 6.12--real_bit_select.sv │ │ ├── 6.12--real_bit_select_idx.sv │ │ ├── 6.12--real_edge.sv │ │ ├── 6.12--realtime.sv │ │ ├── 6.12--shortreal.sv │ │ ├── 6.13--void.sv │ │ ├── 6.14--chandle.sv │ │ ├── 6.16--string.sv │ │ ├── 6.16.1--string_len.sv │ │ ├── 6.16.10--string_atoreal.sv │ │ ├── 6.16.11--string_itoa.sv │ │ ├── 6.16.12--string_hextoa.sv │ │ ├── 6.16.13--string_octtoa.sv │ │ ├── 6.16.14--string_bintoa.sv │ │ ├── 6.16.15--string_realtoa.sv │ │ ├── 6.16.2--string_putc.sv │ │ ├── 6.16.3--string_getc.sv │ │ ├── 6.16.4--string_toupper.sv │ │ ├── 6.16.5--string_tolower.sv │ │ ├── 6.16.6--string_compare.sv │ │ ├── 6.16.7--string_icompare.sv │ │ ├── 6.16.8--string_substr.sv │ │ ├── 6.16.9--string_atobin.sv │ │ ├── 6.16.9--string_atohex.sv │ │ ├── 6.16.9--string_atoi.sv │ │ ├── 6.16.9--string_atooct.sv │ │ ├── 6.17--event.sv │ │ ├── 6.18--typedef.sv │ │ ├── 6.19--enum_anon.sv │ │ ├── 6.19--enum_value_inv.sv │ │ ├── 6.19--enum_xx.sv │ │ ├── 6.19--enum_xx_inv.sv │ │ ├── 6.19--enum_xx_inv_order.sv │ │ ├── 6.19.1--enum_typedef.sv │ │ ├── 6.19.2--enum_sequence.sv │ │ ├── 6.19.2--enum_sequence_range.sv │ │ ├── 6.19.3--enum_type_checking.sv │ │ ├── 6.19.3--enum_type_checking_inv.sv │ │ ├── 6.19.4--enum_numerical_expr.sv │ │ ├── 6.19.4--enum_numerical_expr_cast.sv │ │ ├── 6.19.4--enum_numerical_expr_no_cast.sv │ │ ├── 6.19.5.1--enum_first.sv │ │ ├── 6.19.5.2--enum_last.sv │ │ ├── 6.19.5.3--enum_next.sv │ │ ├── 6.19.5.4--enum_prev.sv │ │ ├── 6.19.5.5--enum_num.sv │ │ ├── 6.19.5.6--enum_name.sv │ │ ├── 6.20.2--parameter.sv │ │ ├── 6.20.2--parameter_aggregate.sv │ │ ├── 6.20.2--parameter_dep.sv │ │ ├── 6.20.2--parameter_port_list.sv │ │ ├── 6.20.2--parameter_range.sv │ │ ├── 6.20.2--parameter_real.sv │ │ ├── 6.20.3--parameter_type.sv │ │ ├── 6.20.4--localparam.sv │ │ ├── 6.20.4--localparam_int.sv │ │ ├── 6.20.4--localparam_logic.sv │ │ ├── 6.20.4--localparam_string.sv │ │ ├── 6.20.4--localparam_unsigned_int.sv │ │ ├── 6.20.5--specparam.sv │ │ ├── 6.20.5--specparam_inv.sv │ │ ├── 6.20.6--const.sv │ │ ├── 6.23--localparam_type_decl.sv │ │ ├── 6.23--type_op.sv │ │ ├── 6.23--type_op_compare.sv │ │ ├── 6.24.1--cast_op.sv │ │ ├── 6.24.2--cast_fn.sv │ │ ├── 6.24.2--cast_task.sv │ │ ├── 6.24.3--bitstream_cast.sv │ │ ├── 6.5--variable_assignment.sv │ │ ├── 6.5--variable_mixed_assignments.sv │ │ ├── 6.5--variable_multiple_assignments.sv │ │ ├── 6.5--variable_redeclare.sv │ │ ├── 6.6.7--nettype.sv │ │ ├── 6.6.7--nettype_resolution_fn.sv │ │ ├── 6.6.8--interconnect.sv │ │ ├── 6.9.1--logic_vector.sv │ │ ├── 6.9.2--vector_scalared.sv │ │ ├── 6.9.2--vector_vectored.sv │ │ └── 6.9.2--vector_vectored_inv.sv │ ├── chapter-7/ │ │ ├── arrays/ │ │ │ ├── associative/ │ │ │ │ ├── alloc.sv │ │ │ │ ├── arguments.sv │ │ │ │ ├── assignment.sv │ │ │ │ ├── class.sv │ │ │ │ ├── integral.sv │ │ │ │ ├── literals.sv │ │ │ │ ├── locator-methods/ │ │ │ │ │ ├── find-first-index.sv │ │ │ │ │ ├── find-first.sv │ │ │ │ │ ├── find-index.sv │ │ │ │ │ ├── find-last-index.sv │ │ │ │ │ ├── find-last.sv │ │ │ │ │ ├── find.sv │ │ │ │ │ ├── max.sv │ │ │ │ │ ├── min.sv │ │ │ │ │ ├── unique-index.sv │ │ │ │ │ └── unique.sv │ │ │ │ ├── methods/ │ │ │ │ │ ├── delete.sv │ │ │ │ │ ├── exists.sv │ │ │ │ │ ├── first.sv │ │ │ │ │ ├── last.sv │ │ │ │ │ ├── next.sv │ │ │ │ │ ├── num.sv │ │ │ │ │ ├── prev.sv │ │ │ │ │ ├── size.sv │ │ │ │ │ └── traversal.sv │ │ │ │ ├── nonexistent.sv │ │ │ │ ├── other.sv │ │ │ │ ├── string.sv │ │ │ │ └── wildcard.sv │ │ │ ├── dynamic/ │ │ │ │ ├── basic.sv │ │ │ │ ├── op-delete.sv │ │ │ │ ├── op-new.sv │ │ │ │ └── op-size.sv │ │ │ ├── multidimensional/ │ │ │ │ ├── basic.sv │ │ │ │ ├── copy.sv │ │ │ │ ├── multi.sv │ │ │ │ └── subarrays.sv │ │ │ ├── packed/ │ │ │ │ ├── basic.sv │ │ │ │ ├── equality.sv │ │ │ │ ├── onebit.sv │ │ │ │ ├── operations.sv │ │ │ │ ├── querying-functions/ │ │ │ │ │ ├── dimensions.sv │ │ │ │ │ ├── high.sv │ │ │ │ │ ├── increment.sv │ │ │ │ │ ├── left.sv │ │ │ │ │ ├── low.sv │ │ │ │ │ ├── right.sv │ │ │ │ │ ├── size.sv │ │ │ │ │ └── unpacked-dimensions.sv │ │ │ │ ├── slice-equality.sv │ │ │ │ ├── slice.sv │ │ │ │ ├── treat-as-integer.sv │ │ │ │ ├── variable-slice-zero.sv │ │ │ │ └── variable-slice.sv │ │ │ └── unpacked/ │ │ │ ├── assignments.sv │ │ │ ├── basic.sv │ │ │ ├── equality.sv │ │ │ ├── index.sv │ │ │ ├── onebit.sv │ │ │ ├── operations.sv │ │ │ ├── ordering-methods/ │ │ │ │ ├── reverse.sv │ │ │ │ ├── rsort.sv │ │ │ │ ├── shuffle.sv │ │ │ │ └── sort.sv │ │ │ ├── reduction-methods/ │ │ │ │ ├── and.sv │ │ │ │ ├── or.sv │ │ │ │ ├── product.sv │ │ │ │ ├── sum.sv │ │ │ │ └── xor.sv │ │ │ ├── slice-equality.sv │ │ │ ├── slice.sv │ │ │ ├── subroutines.sv │ │ │ └── variable-slice.sv │ │ ├── memories/ │ │ │ ├── basic.sv │ │ │ └── read-write.sv │ │ ├── queues/ │ │ │ ├── basic.sv │ │ │ ├── bounded.sv │ │ │ ├── delete.sv │ │ │ ├── delete_assign.sv │ │ │ ├── insert.sv │ │ │ ├── insert_assign.sv │ │ │ ├── max-size.sv │ │ │ ├── persistence.sv │ │ │ ├── pop_back.sv │ │ │ ├── pop_back_assing.sv │ │ │ ├── pop_front.sv │ │ │ ├── pop_front_assign.sv │ │ │ ├── push_back.sv │ │ │ ├── push_back_assign.sv │ │ │ ├── push_front.sv │ │ │ ├── push_front_assign.sv │ │ │ ├── size.sv │ │ │ └── slice.sv │ │ ├── structures/ │ │ │ ├── packed/ │ │ │ │ ├── basic.sv │ │ │ │ ├── default-value.sv │ │ │ │ ├── signed.sv │ │ │ │ └── unsigned.sv │ │ │ └── unpacked/ │ │ │ ├── basic.sv │ │ │ └── default-value.sv │ │ └── unions/ │ │ ├── packed/ │ │ │ └── basic.sv │ │ ├── tagged/ │ │ │ ├── basic.sv │ │ │ └── packed.sv │ │ └── unpacked/ │ │ └── basic.sv │ ├── chapter-8/ │ │ ├── 8.10--static_methods.sv │ │ ├── 8.11--this.sv │ │ ├── 8.12--assignment.sv │ │ ├── 8.12--shallow_copy.sv │ │ ├── 8.13--inheritance.sv │ │ ├── 8.14--override_member.sv │ │ ├── 8.15--super-default-new.sv │ │ ├── 8.15--super.sv │ │ ├── 8.16--cast_func.sv │ │ ├── 8.17--constructor_const_arg.sv │ │ ├── 8.18--var_local.sv │ │ ├── 8.18--var_protected.sv │ │ ├── 8.19--global_constant.sv │ │ ├── 8.19--instance_constant.sv │ │ ├── 8.20--virtual_method.sv │ │ ├── 8.21--abstract_class.sv │ │ ├── 8.21--abstract_class_inst.sv │ │ ├── 8.22--dynamic_method_lookup.sv │ │ ├── 8.23--scope_resolution.sv │ │ ├── 8.24--out_of_block_methods.sv │ │ ├── 8.25--parametrized_class_extend.sv │ │ ├── 8.25.1--parametrized_class_invalid_scope_resolution.sv │ │ ├── 8.25.1--parametrized_class_scope_resolution.sv │ │ ├── 8.26.2--implements.sv │ │ ├── 8.26.2--implements_extends.sv │ │ ├── 8.26.2--implements_multiple.sv │ │ ├── 8.26.3--type_access_extends.sv │ │ ├── 8.26.3--type_access_implements.sv │ │ ├── 8.26.3--type_access_implements_invalid.sv │ │ ├── 8.26.4--illegal_forward_def_implements.sv │ │ ├── 8.26.4--illegal_implements_parameter.sv │ │ ├── 8.26.5--cast_between_interface_classes.sv │ │ ├── 8.26.5--implemented_class_handle.sv │ │ ├── 8.26.5--invalid_interface_instantiation.sv │ │ ├── 8.26.6.1--name_conflict_resolved.sv │ │ ├── 8.26.6.1--name_conflict_unresolved.sv │ │ ├── 8.26.6.2--parameter_type_conflict.sv │ │ ├── 8.26.6.2--parameter_type_conflict_unresolved.sv │ │ ├── 8.26.6.3--diamond_relationship.sv │ │ ├── 8.26.6.3--diamond_relationship_parametrized.sv │ │ ├── 8.26.7--partial_implementation.sv │ │ ├── 8.27--forward_declaration.sv │ │ ├── 8.4--instantiation.sv │ │ ├── 8.5--parameters.sv │ │ ├── 8.5--properties.sv │ │ ├── 8.5--properties_enum.sv │ │ ├── 8.6--methods.sv │ │ ├── 8.7--constructor.sv │ │ ├── 8.7--constructor_param.sv │ │ ├── 8.7--constructor_super.sv │ │ ├── 8.8--typed_constructor.sv │ │ ├── 8.8--typed_constructor_param.sv │ │ └── 8.9--static_properties.sv │ ├── chapter-9/ │ │ ├── 9.2.1--initial.sv │ │ ├── 9.2.2.1--always.sv │ │ ├── 9.2.2.2--always_comb.sv │ │ ├── 9.2.2.3--always_latch.sv │ │ ├── 9.2.2.4--always_ff.sv │ │ ├── 9.2.3--final.sv │ │ ├── 9.3.1--sequential_block.sv │ │ ├── 9.3.2--parallel_block_join.sv │ │ ├── 9.3.2--parallel_block_join_any.sv │ │ ├── 9.3.2--parallel_block_join_none.sv │ │ ├── 9.3.3--block_start_finish.sv │ │ ├── 9.3.3--event.sv │ │ ├── 9.3.3--fork_return.sv │ │ ├── 9.3.4--block_names_par.sv │ │ ├── 9.3.4--block_names_seq.sv │ │ ├── 9.3.5--statement_labels_par.sv │ │ ├── 9.3.5--statement_labels_seq.sv │ │ ├── 9.4.1--delay_control-sim.sv │ │ ├── 9.4.1--delay_control-two-blocks-sim.sv │ │ ├── 9.4.1--delay_control.sv │ │ ├── 9.4.2--event_control_edge.sv │ │ ├── 9.4.2--event_control_negedge.sv │ │ ├── 9.4.2--event_control_posedge.sv │ │ ├── 9.4.2--event_control_sim.sv │ │ ├── 9.4.2--event_control_sim_minimal.sv │ │ ├── 9.4.2.1--event_comma_op.sv │ │ ├── 9.4.2.1--event_or_op.sv │ │ ├── 9.4.2.2--event_implicit.sv │ │ ├── 9.4.2.3--event_conditional.sv │ │ ├── 9.4.2.4--event_sequence.sv │ │ ├── 9.4.3--event_sequence_controls.sv │ │ ├── 9.4.5--event_blocking_assignment_delay.sv │ │ ├── 9.4.5--event_nonblocking_assignment_delay.sv │ │ ├── 9.4.5--event_nonblocking_assignment_event.sv │ │ ├── 9.4.5--event_nonblocking_assignment_repeat.sv │ │ ├── 9.4.5--event_nonblocking_assignment_repeat_int.sv │ │ ├── 9.4.5--event_nonblocking_assignment_repeat_int_neg.sv │ │ ├── 9.4.5--event_nonblocking_assignment_repeat_neg.sv │ │ ├── 9.6.1--wait_fork.sv │ │ ├── 9.6.2--disable.sv │ │ ├── 9.6.2--disable_other.sv │ │ ├── 9.6.3--disable_fork.sv │ │ ├── 9.7--process_cls_await.sv │ │ ├── 9.7--process_cls_kill.sv │ │ ├── 9.7--process_cls_self.sv │ │ └── 9.7--process_cls_suspend_resume.sv │ ├── generic/ │ │ ├── class/ │ │ │ ├── class_test_0.sv │ │ │ ├── class_test_1.sv │ │ │ ├── class_test_11.sv │ │ │ ├── class_test_12.sv │ │ │ ├── class_test_13.sv │ │ │ ├── class_test_17.sv │ │ │ ├── class_test_18.sv │ │ │ ├── class_test_19.sv │ │ │ ├── class_test_21.sv │ │ │ ├── class_test_25.sv │ │ │ ├── class_test_26.sv │ │ │ ├── class_test_27.sv │ │ │ ├── class_test_28.sv │ │ │ ├── class_test_29.sv │ │ │ ├── class_test_30.sv │ │ │ ├── class_test_4.sv │ │ │ ├── class_test_48.sv │ │ │ ├── class_test_49.sv │ │ │ ├── class_test_51.sv │ │ │ ├── class_test_52.sv │ │ │ ├── class_test_53.sv │ │ │ ├── class_test_54.sv │ │ │ ├── class_test_55.sv │ │ │ ├── class_test_56.sv │ │ │ ├── class_test_57.sv │ │ │ ├── class_test_58.sv │ │ │ ├── class_test_59.sv │ │ │ ├── class_test_6.sv │ │ │ ├── class_test_60.sv │ │ │ ├── class_test_61.sv │ │ │ ├── class_test_62.sv │ │ │ ├── class_test_63.sv │ │ │ ├── class_test_64.sv │ │ │ ├── class_test_65.sv │ │ │ ├── class_test_66.sv │ │ │ ├── class_test_67.sv │ │ │ ├── class_test_68.sv │ │ │ ├── class_test_69.sv │ │ │ ├── class_test_7.sv │ │ │ ├── class_test_8.sv │ │ │ └── class_test_9.sv │ │ ├── desc/ │ │ │ ├── desc_test_0.sv │ │ │ ├── desc_test_1.sv │ │ │ ├── desc_test_10.sv │ │ │ ├── desc_test_15.sv │ │ │ ├── desc_test_16.sv │ │ │ ├── desc_test_17.sv │ │ │ ├── desc_test_18.sv │ │ │ ├── desc_test_2.sv │ │ │ ├── desc_test_3.sv │ │ │ ├── desc_test_4.sv │ │ │ ├── desc_test_5.sv │ │ │ ├── desc_test_6.sv │ │ │ ├── desc_test_7.sv │ │ │ ├── desc_test_8.sv │ │ │ └── desc_test_9.sv │ │ ├── empty/ │ │ │ ├── empty_test_0.sv │ │ │ ├── empty_test_1.sv │ │ │ ├── empty_test_2.sv │ │ │ ├── empty_test_3.sv │ │ │ ├── empty_test_4.sv │ │ │ └── empty_test_5.sv │ │ ├── iface/ │ │ │ ├── iface_class_test_0.sv │ │ │ ├── iface_class_test_1.sv │ │ │ ├── iface_class_test_10.sv │ │ │ ├── iface_class_test_2.sv │ │ │ └── iface_class_test_9.sv │ │ ├── member/ │ │ │ ├── class_member_test_0.sv │ │ │ ├── class_member_test_10.sv │ │ │ ├── class_member_test_11.sv │ │ │ ├── class_member_test_12.sv │ │ │ ├── class_member_test_14.sv │ │ │ ├── class_member_test_15.sv │ │ │ ├── class_member_test_18.sv │ │ │ ├── class_member_test_19.sv │ │ │ ├── class_member_test_2.sv │ │ │ ├── class_member_test_25.sv │ │ │ ├── class_member_test_26.sv │ │ │ ├── class_member_test_27.sv │ │ │ ├── class_member_test_3.sv │ │ │ ├── class_member_test_31.sv │ │ │ ├── class_member_test_32.sv │ │ │ ├── class_member_test_39.sv │ │ │ ├── class_member_test_4.sv │ │ │ ├── class_member_test_40.sv │ │ │ ├── class_member_test_41.sv │ │ │ ├── class_member_test_5.sv │ │ │ ├── class_member_test_6.sv │ │ │ ├── class_member_test_7.sv │ │ │ ├── class_member_test_8.sv │ │ │ └── class_member_test_9.sv │ │ ├── number/ │ │ │ ├── number_test_0.sv │ │ │ ├── number_test_1.sv │ │ │ ├── number_test_10.sv │ │ │ ├── number_test_11.sv │ │ │ ├── number_test_12.sv │ │ │ ├── number_test_13.sv │ │ │ ├── number_test_14.sv │ │ │ ├── number_test_15.sv │ │ │ ├── number_test_16.sv │ │ │ ├── number_test_2.sv │ │ │ ├── number_test_24.sv │ │ │ ├── number_test_25.sv │ │ │ ├── number_test_26.sv │ │ │ ├── number_test_27.sv │ │ │ ├── number_test_28.sv │ │ │ ├── number_test_29.sv │ │ │ ├── number_test_3.sv │ │ │ ├── number_test_30.sv │ │ │ ├── number_test_31.sv │ │ │ ├── number_test_32.sv │ │ │ ├── number_test_33.sv │ │ │ ├── number_test_34.sv │ │ │ ├── number_test_35.sv │ │ │ ├── number_test_36.sv │ │ │ ├── number_test_4.sv │ │ │ ├── number_test_42.sv │ │ │ ├── number_test_43.sv │ │ │ ├── number_test_44.sv │ │ │ ├── number_test_45.sv │ │ │ ├── number_test_46.sv │ │ │ ├── number_test_47.sv │ │ │ ├── number_test_48.sv │ │ │ ├── number_test_49.sv │ │ │ ├── number_test_5.sv │ │ │ ├── number_test_50.sv │ │ │ ├── number_test_51.sv │ │ │ ├── number_test_52.sv │ │ │ ├── number_test_53.sv │ │ │ ├── number_test_59.sv │ │ │ ├── number_test_6.sv │ │ │ ├── number_test_60.sv │ │ │ ├── number_test_61.sv │ │ │ ├── number_test_62.sv │ │ │ ├── number_test_64.sv │ │ │ ├── number_test_65.sv │ │ │ ├── number_test_66.sv │ │ │ ├── number_test_67.sv │ │ │ ├── number_test_68.sv │ │ │ ├── number_test_69.sv │ │ │ ├── number_test_7.sv │ │ │ ├── number_test_70.sv │ │ │ ├── number_test_71.sv │ │ │ ├── number_test_72.sv │ │ │ ├── number_test_8.sv │ │ │ └── number_test_9.sv │ │ ├── preproc/ │ │ │ ├── preproc_test_0.sv │ │ │ ├── preproc_test_2.sv │ │ │ ├── preproc_test_2.svh │ │ │ ├── preproc_test_4.sv │ │ │ ├── preproc_test_5.sv │ │ │ ├── preproc_test_6.sv │ │ │ ├── preproc_test_7.sv │ │ │ └── preproc_test_8.sv │ │ ├── struct/ │ │ │ └── struct_test_0.sv │ │ ├── typedef/ │ │ │ ├── typedef_test_0.sv │ │ │ ├── typedef_test_1.sv │ │ │ ├── typedef_test_10.sv │ │ │ ├── typedef_test_11.sv │ │ │ ├── typedef_test_12.sv │ │ │ ├── typedef_test_13.sv │ │ │ ├── typedef_test_14.sv │ │ │ ├── typedef_test_16.sv │ │ │ ├── typedef_test_18.sv │ │ │ ├── typedef_test_19.sv │ │ │ ├── typedef_test_2.sv │ │ │ ├── typedef_test_20.sv │ │ │ ├── typedef_test_21.sv │ │ │ ├── typedef_test_22.sv │ │ │ ├── typedef_test_23.sv │ │ │ ├── typedef_test_24.sv │ │ │ ├── typedef_test_25.sv │ │ │ ├── typedef_test_25__bad.sv │ │ │ ├── typedef_test_26.sv │ │ │ ├── typedef_test_27.sv │ │ │ ├── typedef_test_28__bad.sv │ │ │ ├── typedef_test_3.sv │ │ │ ├── typedef_test_4.sv │ │ │ ├── typedef_test_5.sv │ │ │ ├── typedef_test_6.sv │ │ │ ├── typedef_test_7.sv │ │ │ ├── typedef_test_8.sv │ │ │ ├── typedef_test_8__bad.sv │ │ │ └── typedef_test_9.sv │ │ └── union/ │ │ └── union_test_0.sv │ ├── sanity.sv │ ├── testbenches/ │ │ ├── uvm_agent_active.sv │ │ ├── uvm_agent_env.sv │ │ ├── uvm_agent_passive.sv │ │ ├── uvm_driver_sequencer_env.sv │ │ ├── uvm_monitor_env.sv │ │ ├── uvm_resource_db_read_by_name.sv │ │ ├── uvm_scoreboard_env.sv │ │ ├── uvm_scoreboard_monitor_agent_env.sv │ │ ├── uvm_scoreboard_monitor_env.sv │ │ ├── uvm_sequence.sv │ │ └── uvm_test_run_test.sv │ └── uvm/ │ └── uvm_files.sv └── tools/ ├── BaseRunner.py ├── check-runners ├── feature-analyzer ├── history-graph ├── logparser.py ├── report_analyzer.py ├── runner ├── runners/ │ ├── Icarus.py │ ├── Odin.py │ ├── Slang.py │ ├── Slang_parse.py │ ├── Surelog.py │ ├── Sv2v_zachjs.py │ ├── SynligYosys.py │ ├── Verible.py │ ├── VeribleExtractor.py │ ├── Verilator.py │ ├── Yosys.py │ ├── circt_verilog.py │ ├── moore.py │ ├── moore_parse.py │ ├── sv_parser.py │ ├── tree_sitter_systemverilog.py │ ├── tree_sitter_verilog.py │ └── yosys_slang.py ├── runners.mk └── sv-report ================================================ FILE CONTENTS ================================================ ================================================ FILE: .editorconfig ================================================ # Editor config file, see http://editorconfig.org/ root = true [*] charset = utf-8 indent_style = space end_of_line = lf insert_final_newline = true trim_trailing_whitespace = true [*.{h,cpp}] indent_size = 2 [*.py] indent_size = 4 [*.html] indent_size = 2 [Makefile] indent_style = tab [*.mk] indent_style = tab ================================================ FILE: .github/dependabot.yml ================================================ version: 2 updates: - package-ecosystem: gitsubmodule directory: "/" schedule: interval: daily # UTC time: "22:00" open-pull-requests-limit: 100 ================================================ FILE: .github/workflows/comment-pr.yml ================================================ name: comment-pr on: workflow_run: workflows: ["sv-tests-ci"] types: - completed jobs: Comment: permissions: pull-requests: write name: Comment runs-on: [ubuntu-latest] if: ${{ github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success' }} steps: - name: Download artifacts id: get-artifacts uses: actions/github-script@v7 with: script: | var artifacts = await github.rest.actions.listWorkflowRunArtifacts({ owner: context.repo.owner, repo: context.repo.repo, run_id: ${{ github.event.workflow_run.id }}, }); var matchArtifact = artifacts.data.artifacts.filter((artifact) => { return artifact.name == "tests_summary" })[0]; var download = await github.rest.actions.downloadArtifact({ owner: context.repo.owner, repo: context.repo.repo, artifact_id: matchArtifact.id, archive_format: 'zip', }); core.setOutput('artifact_id', matchArtifact.id); var fs = require('fs'); fs.writeFileSync('${{github.workspace}}/tests_summary.zip', Buffer.from(download.data)); - name: Unpack artifacts run: | unzip tests_summary.zip cat ./tests_summary.md - name: Generate and append artifacts link run: | ARTIFACT_ID=${{ steps.get-artifacts.outputs.artifact_id}} ARTIFACT_URL="https://github.com/${{ github.repository }}/actions/runs/${{ github.event.workflow_run.id }}/artifacts/$ARTIFACT_ID" MD_URL="[Download an archive containing all the details]($ARTIFACT_URL)" echo -e "\n\n$MD_URL" >> tests_summary.md - name: Show summary run: | cat tests_summary.md > $GITHUB_STEP_SUMMARY - name: Prepare comment id: get-comment-body run: | { echo "body<> $GITHUB_OUTPUT - name: Get PR number id: get-pr-number run: | num=$(cat ./issue_num) echo "num=$num" >> $GITHUB_OUTPUT - name: Post comment uses: KeisukeYamashita/create-comment@v1 with: number: ${{ steps.get-pr-number.outputs.num }} check-only-first-line: "true" unique: "true" token: ${{ secrets.GITHUB_TOKEN }} comment: ${{ steps.get-comment-body.outputs.body }} ================================================ FILE: .github/workflows/lint-review.yml ================================================ name: lint-review on: pull_request: workflow_dispatch: jobs: lint_review: runs-on: ubuntu-latest permissions: checks: write contents: read pull-requests: write steps: - uses: actions/checkout@v2 - name: Run Verible action uses: chipsalliance/verible-linter-action@main with: paths: ./tests github_token: ${{ secrets.GITHUB_TOKEN }} suggest_fixes: 'false' ================================================ FILE: .github/workflows/report.sh ================================================ #!/bin/bash set -euxo pipefail make $@ generate-tests cp -ar ./out/report_*/logs ./out/ make $@ report ================================================ FILE: .github/workflows/summary.sh ================================================ #!/bin/bash set -euxo pipefail set -x set -e #environment variables for this file are set in sv-tests-ci.yml # Get base report from sv-tests master run git clone https://github.com/chipsalliance/sv-tests-results.git --depth 120 $REPORTS_HISTORY # Delete headers from all report.csv for file in $(find ./out/report_* -name "*.csv" -print); do sed -i.backup 1,1d $file done # concatenate test reports cat $(find ./out/report_* -name "*.csv" -print) >> $COMPARE_REPORT # Insert header at the first line of concatenated report sed -i 1i\ $(head -1 $(find ./out/report_* -name "*.csv.backup" -print -quit)) $COMPARE_REPORT python $ANALYZER $COMPARE_REPORT $BASE_REPORT -o $CHANGES_SUMMARY_JSON -t $CHANGES_SUMMARY_MD # generate history graph python $GRAPHER -n 120 -r $REPORTS_HISTORY set +e set +x ================================================ FILE: .github/workflows/sv-tests-ci.yml ================================================ name: sv-tests-ci on: push: branches: - master pull_request: workflow_dispatch: schedule: - cron: '0 1 * * *' # run daily at 01:00 am (UTC) jobs: Run: strategy: fail-fast: false matrix: tool: - name: icarus deps: autoconf autotools-dev bison flex libfl-dev gperf - name: moore rust_ver: "1.61" - name: odin repo: odin_ii deps: autoconf autotools-dev bison flex libfl-dev cmake pkg-config - name: slang deps: cmake pkg-config - name: surelog repo: Surelog submodules: third_party/UHDM third_party/antlr4 third_party/googletest deps: cmake default-jre pkg-config tclsh uuid-dev - name: sv-parser deps: cargo rust_ver: "1.94" - name: tree-sitter-systemverilog deps: gcc - name: tree-sitter-verilog deps: gcc - name: verible deps: bazel=7.6.1 bison flex libfl-dev skip-ccache: 1 - name: verilator deps: autoconf autotools-dev bison flex help2man libfl-dev libelf-dev make_jobs_max: 4 - name: yosys deps: bison clang tcl-dev flex libfl-dev pkg-config libreadline-dev - name: yosys-synlig repo: synlig submodules: third_party/yosys third_party/surelog deps: cmake clang tcl-dev bison default-jre flex libfl-dev libreadline-dev pkg-config tclsh uuid-dev runners_filter: SynligYosys - name: zachjs-sv2v deps: haskell-stack - name: yosys-slang deps: bison clang tcl-dev flex libfl-dev pkg-config libreadline-dev cmake pkg-config submodules: third_party/slang - name: circt-verilog deps: cmake clang ninja-build lld submodules: llvm env: RUNNERS_FILTER: ${{ matrix.tool.runners_filter }} CCACHE_DIR: "/root/sv-tests/sv-tests/.cache/" # those generators can use a lot of RAM/cpu and starve other tests # tests from those generators are run without "-j" flag BIG_GENERATORS: "fusesoc black-parrot" DEBIAN_FRONTEND: "noninteractive" GHA_MACHINE_TYPE: "n2-highmem-16" name: ${{ matrix.tool.name }} runs-on: [self-hosted, Linux, X64, gcp-custom-runners] container: ubuntu:jammy-20221130 steps: - name: Cancel previous uses: styfle/cancel-workflow-action@0.8.0 with: access_token: ${{ github.token }} - name: Show shell run: | echo "$SHELL" - name: Checkout code uses: actions/checkout@v2 - name: Update apt repos run: | apt-get update -qq - name: Setup Node run: | apt -qq -y install curl touch "$HOME/.bash_profile" # From https://nodejs.org/en/download curl -o- https://raw.githubusercontent.com/nvm-sh/nvm/v0.40.2/install.sh | bash . "$HOME/.nvm/nvm.sh" nvm install 22 - name: Add bazel repo (if needed) if: ${{ contains(matrix.tool.deps, 'bazel') }} run: | apt -qq -y install apt-transport-https curl gnupg curl -fsSL https://bazel.build/bazel-release.pub.gpg | gpg --dearmor > bazel.gpg chmod a+r bazel.gpg mv bazel.gpg /etc/apt/trusted.gpg.d/ echo "deb [arch=amd64] https://storage.googleapis.com/bazel-apt stable jdk1.8" | tee /etc/apt/sources.list.d/bazel.list apt-get update -qq - name: Install common dependencies run: | apt install -y python3 python3-pip git wget file update-alternatives --install /usr/bin/python python /usr/bin/python3 1 update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1 pip install --use-pep517 --upgrade setuptools pip install --use-pep517 -r conf/requirements.txt - name: Install VeeR dependencies run: | apt install -y cpanminus cpanm Bit::Vector JSON - name: Install ccache if: ${{ !matrix.tool.skip-ccache }} run: | apt install -y ccache - name: Install tool-specific dependencies if: ${{ matrix.tool.deps }} run: | apt -qq -y install ${{ matrix.tool.deps }} - name: Setup Rust (if needed) if: ${{ matrix.tool.rust_ver }} run: | apt -y install curl curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs > setup.sh sh setup.sh -y source $HOME/.cargo/env rustup install ${{ matrix.tool.rust_ver }} rustup default ${{ matrix.tool.rust_ver }} - name: Update haskell (if needed) if: ${{ contains(matrix.tool.deps, 'haskell') }} run: | stack upgrade - name: Checkout the tool submodule run: | # Github dropped support for unauthorized git: https://github.blog/2021-09-01-improving-git-protocol-security-github/ # Make sure we always use https:// instead of git:// git config --global url.https://github.com/.insteadOf git://github.com/ # take verilator from github (some tested tools still use a submodule # from veripool) git config --global url."https://github.com/verilator/verilator".insteadOf http://git.veripool.org/git/verilator REPOSITORY_NAME=${{ matrix.tool.name }} if [[ ! -z "${{ matrix.tool.repo }}" ]]; then REPOSITORY_NAME=${{ matrix.tool.repo }} fi git submodule update --init --depth 1 third_party/tools/${REPOSITORY_NAME} if [[ ! -z "${{ matrix.tool.submodules }}" ]]; then pushd third_party/tools/${REPOSITORY_NAME} git submodule update --init --recursive --depth 1 ${{ matrix.tool.submodules }} popd fi # yosys tool contains tests, is a dependency of other tools git submodule update --init --recursive --depth 1 third_party/tools/yosys # icarus contains tests git submodule update --init --depth 1 third_party/tools/icarus - name: Create Cache Timestamp id: cache_timestamp uses: nanzm/get-time-action@v1.1 with: format: 'YYYY-MM-DD-HH-mm-ss' - name: Setup cache uses: actions/cache@v4 timeout-minutes: 3 continue-on-error: true with: path: "/root/sv-tests/sv-tests/.cache/" key: cache_${{ matrix.tool.name }}_${{ steps.cache_timestamp.outputs.time }} restore-keys: cache_${{ matrix.tool.name }}_ - name: Build run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" [[ -f $HOME/.cargo/env ]] && source $HOME/.cargo/env . "$HOME/.bash_profile" # GitHub Actions runs bash with --noprofile make ${{ matrix.tool.name }} -j$(nproc) - name: Check run: make info - name: Checkout third party tests and cores run: | git submodule update --init --recursive --depth 1 third_party/tests git submodule update --init --recursive --depth 1 third_party/cores - name: Run run: | BIG_GENERATORS_EXPR=$(echo $BIG_GENERATORS | sed 's/ /\\|/g') export STABLE_GENERATORS=$(make list-generators | tr ' ' '\n' | grep -v "${BIG_GENERATORS_EXPR}") export UNSTABLE_GENERATORS=$(make list-generators | tr ' ' '\n' | grep "${BIG_GENERATORS_EXPR}") export JOBS=${{ matrix.tool.make_jobs_max }} if [[ "${JOBS}x" == "x" ]]; then export JOBS=$(nproc); fi for gen in ${STABLE_GENERATORS}; do echo "==GEN stable $gen -j $JOBS" ; make generate-$gen -j${JOBS}; make -j ${JOBS}; done for gen in ${UNSTABLE_GENERATORS}; do echo "==GEN unstable $gen" ; make generate-$gen; make; done - name: Prepare Report run: mv out/report/report.csv out/report/${{ matrix.tool.name }}_report.csv - name: Pack results run: | tar -cvf out_${{ matrix.tool.name }}.tar ./out/report/${{ matrix.tool.name }}_report.csv ./out/logs/ - uses: actions/upload-artifact@v4 with: name: report_${{ matrix.tool.name }} path: | out_${{ matrix.tool.name }}.tar **/plot_*.svg Summary: name: Summary runs-on: [self-hosted, Linux, X64, gcp-custom-runners] container: ubuntu:jammy-20221130 needs: Run env: ANALYZER: "$PWD/tools/report_analyzer.py" GRAPHER: "$PWD/tools/history-graph" OUT_REPORT_DIR: "$PWD/out/report/" COMPARE_REPORT: "$OUT_REPORT_DIR/report.csv" REPORTS_HISTORY: "$(mktemp -d --suffix='.history')" BASE_REPORT: "$REPORTS_HISTORY/report.csv" CHANGES_SUMMARY_JSON: "$OUT_REPORT_DIR/tests_summary.json" CHANGES_SUMMARY_MD: "$OUT_REPORT_DIR/tests_summary.md" TESTS_SUMMARY_DIR: "tests_summary/" DEBIAN_FRONTEND: "noninteractive" steps: - name: Checkout code uses: actions/checkout@v2 - name: Setup python run: | apt-get update -qq apt install -y python3 python3-pip wget git curl jq update-alternatives --install /usr/bin/python python /usr/bin/python3 1 update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1 pip install --use-pep517 --upgrade setuptools pip install --use-pep517 -r conf/requirements.txt - name: Install VeeR dependencies run: | apt install -y cpanminus cpanm Bit::Vector JSON - name: Prepare output directories run: | mkdir -p out/report - uses: actions/download-artifact@v4 with: path: ./out/ - name: Extract run: | for file in $(find out/ -name *.tar -print); do tar -xf $file --strip-components=2 -C $(dirname $file); done - name: Checkout third party tests and cores run: | # take verilator from github git config --global url."https://github.com/verilator/verilator".insteadOf http://git.veripool.org/git/verilator git submodule update --init --recursive --depth 1 third_party/tests git submodule update --init --recursive --depth 1 third_party/cores # yosys tool also contains tests git submodule update --init --recursive --depth 1 third_party/tools/yosys # icarus contains tests git submodule update --init --depth 1 third_party/tools/icarus - name: Summary run: | ./.github/workflows/summary.sh ./.github/workflows/report.sh - name: Update sv-tests-results repository if: github.ref == 'refs/heads/master' run: | eval $(ssh-agent -s) ssh-add - <<< "${{ secrets.REPORT_DEPLOY_KEY }}" mkdir -p ~/.ssh chmod 700 ~/.ssh ssh-keyscan -t rsa github.com >> ~/.ssh/known_hosts ./.github/workflows/update_report.sh - name: Prepare artifacts for PR commenter if: github.event_name == 'pull_request' run: | mkdir $TESTS_SUMMARY_DIR echo ${{ github.event.number }} > $TESTS_SUMMARY_DIR/issue_num cp $COMPARE_REPORT $TESTS_SUMMARY_DIR/report_base.csv cp $OUT_REPORT_DIR/report.csv $TESTS_SUMMARY_DIR/report_new.csv cp $OUT_REPORT_DIR/new_*csv $TESTS_SUMMARY_DIR cp $OUT_REPORT_DIR/tests_summary.json $TESTS_SUMMARY_DIR cp $OUT_REPORT_DIR/tests_summary.md $TESTS_SUMMARY_DIR find out -name plot_*.svg -exec cp {} $TESTS_SUMMARY_DIR \; - name: Post GitHub summary run: | cat $CHANGES_SUMMARY_MD > $GITHUB_STEP_SUMMARY - name: Upload artifacts for summary uses: actions/upload-artifact@v4 if: github.event_name == 'pull_request' with: name: tests_summary path: | ./tests_summary/ - name: Find artifacts that are no longer needed id: get-artifacts-to-delete if: github.event_name == 'pull_request' run: | artifacts=$(find ./out -type d -name 'report_*' -exec basename {} \;) echo $artifacts artifacts="${artifacts//'%'/'%25'}" artifacts="${artifacts//$'\n'/'%0A'}" artifacts="${artifacts//$'\r'/'%0D'}" echo "artifacts=$artifacts" >> GITHUB_OUTPUT echo $artifacts - name: Delete Old Artifacts if: github.event_name == 'pull_request' uses: geekyeggo/delete-artifact@v5 with: name: ${{ steps.get-artifacts-to-delete.outputs.artifacts }} Automerge: name: Automerge dependabot pull requests permissions: pull-requests: write contents: write runs-on: ubuntu-latest needs: Summary if: ${{ github.event_name == 'pull_request' && github.event.pull_request.user.login == 'dependabot[bot]' }} steps: - name: Dependabot metadata id: metadata uses: dependabot/fetch-metadata@v1.1.1 with: github-token: "${{ secrets.GITHUB_TOKEN }}" - name: Enable auto-merge for Dependabot PRs run: gh pr merge --auto --merge "$PR_URL" env: PR_URL: ${{ github.event.pull_request.html_url }} GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} ================================================ FILE: .github/workflows/sv-tests-code-quality.yml ================================================ name: "Code Quality Checks" on: push: pull_request: workflow_dispatch: jobs: Test: name: "Code Quality Checks" runs-on: ubuntu-latest steps: - name: Checkout code uses: actions/checkout@v3 with: submodules: true - uses: actions/setup-python@v4 with: python-version: 3.8 - name: Script run: pip install -r conf/requirements.txt - name: Make run: make format - name: Test run: test $(git status --porcelain | wc -l) -eq 0 || { git diff; false; } - name: License uses: SymbiFlow/actions/checks@main with: exclude_directory: | ./.git/ ./.github/ ./.dependabot/ ./miniconda.sh ./build/ third_party: | ./third_party/cores/ ./third_party/tests/ ./third_party/tools/ ================================================ FILE: .github/workflows/update_report.sh ================================================ #!/bin/bash set -euxo pipefail export CURRENT_PATH=$PWD set -ex git clone \ git@github.com:chipsalliance/sv-tests-results.git \ --single-branch \ --depth 1 \ --branch gh-pages \ output cd output || (echo "The output directory doesn't exist! Cloning the sv-tests-results repository failed, please check the ssh-key! Exiting"; exit 1) rm -rf * cp -a $CURRENT_PATH/out/report/* -t . touch .nojekyll git add . GIT_MESSAGE_FILE=/tmp/git-message cat > $GIT_MESSAGE_FILE < /sys/fs/cgroup/memory/$(USE_CGROUP)/$(1)/memory.limit_in_bytes else $(1)-cg: @true endif endef define runner_version_gen $(OUT_DIR)/logs/$(1)/version: ./tools/runner --runner $(1) --version --out $(OUT_DIR)/logs/$(1)/version versions: $(OUT_DIR)/logs/$(1)/version endef define runner_url_gen $(OUT_DIR)/logs/$(1)/url: ./tools/runner --runner $(1) --url --out $(OUT_DIR)/logs/$(1)/url urls: $(OUT_DIR)/logs/$(1)/url endef define generator_gen generate-$(1): $(GENERATORS_DIR)/$(1) $(1) generate-tests: generate-$(1) endef RUNNERS_FOUND := $(wildcard $(RUNNERS_DIR)/*.py) RUNNERS_FOUND := $(RUNNERS_FOUND:$(RUNNERS_DIR)/%=%) RUNNERS_FOUND := $(sort $(basename $(RUNNERS_FOUND))) ifdef RUNNERS_FILTER FILTER := --filter $(RUNNERS_FILTER) endif RUNNERS := $(sort $(shell OUT_DIR=$(OUT_DIR) RUNNERS_DIR=$(RUNNERS_DIR) \ TREE_SITTER_SVERILOG_PARSER_DIR=$(TREE_SITTER_SVERILOG_PARSER_DIR) \ TREE_SITTER_VERILOG_PARSER_DIR=$(TREE_SITTER_VERILOG_PARSER_DIR) \ ./tools/check-runners $(RUNNERS_FOUND) $(FILTER))) TESTS := $(shell find $(TESTS_DIR) -type f -iname *.sv) TESTS := $(TESTS:$(TESTS_DIR)/%=%) GENERATORS := $(wildcard $(GENERATORS_DIR)/*) GENERATORS := $(GENERATORS:$(GENERATORS_DIR)/%=%) space := $(subst ,, ) ifneq ($(USE_ALL_RUNNERS),) ifneq ($(RUNNERS), $(RUNNERS_FOUND)) $(warning Runners found: $(RUNNERS_FOUND)) $(warning Runners defined: $(RUNNERS)) $(error Some runners are missing) endif endif info: @echo -e "Found the following runners:$(subst $(space),"\\n \* ", $(RUNNERS))\n" PY_FILES := $(shell file generators/* tools/* | sed -ne 's/:.*[Pp]ython.*//p') PY_FILES += $(wildcard tools/*.py) PY_FILES += $(wildcard tools/runners/*.py) PY_FILES += $(wildcard conf/report/*.py) format: python3 -m yapf -p -i $(PY_FILES) tests: generate-tests: urls: versions: report: init tests versions urls ./tools/sv-report --revision $(shell git rev-parse --short HEAD) cp $(CONF_DIR)/report/*.css $(OUT_DIR)/report/ cp $(CONF_DIR)/report/*.js $(OUT_DIR)/report/ cp $(CONF_DIR)/report/*.png $(OUT_DIR)/report/ cp $(CONF_DIR)/report/*.svg $(OUT_DIR)/report/ list-generators: @echo $(GENERATORS) $(foreach g, $(GENERATORS), $(eval $(call generator_gen,$(g)))) $(foreach r, $(RUNNERS),$(foreach t, $(TESTS),$(eval $(call runner_test_gen,$(r),$(t))))) $(foreach r, $(RUNNERS),$(eval $(call runner_cg_gen,$(r)))) $(foreach r, $(RUNNERS),$(eval $(call runner_version_gen,$(r)))) $(foreach r, $(RUNNERS),$(eval $(call runner_url_gen,$(r)))) ================================================ FILE: README.md ================================================ # SystemVerilog Tester [![License](https://img.shields.io/github/license/chipsalliance/sv-tests.svg)](https://github.com/chipsalliance/sv-tests/blob/master/LICENSE) [![Build Status](https://github.com/chipsalliance/sv-tests/workflows/sv-tests-ci/badge.svg?branch=master)](https://github.com/chipsalliance/sv-tests/actions) The purpose of this project is to find all the supported and missing SystemVerilog features in various Verilog tools. The report generated from the last passing master build can be viewed [on a dedicated dashboard:](https://chipsalliance.github.io/sv-tests-results/) [![Grid](./img/sv-test-grid.png)](https://chipsalliance.github.io/sv-tests-results/) History of the builds is also tracked and can be seen [on a separate page:](https://chipsalliance.github.io/sv-tests-results/history) [![History](./img/sv-test-history.png)](https://chipsalliance.github.io/sv-tests-results/history) # Running Initialize the submodules: ```bash git submodule update --init --recursive ``` Install all the python dependencies and make sure the installed binaries can be called. ```bash pip3 install --user -r conf/requirements.txt export PATH=~/.local/bin:$PATH ``` Build tools (optional, tools from `PATH` can be used): ```bash make -k runners ``` And then just run: ```bash make generate-tests -j$(nproc) make -j$(nproc) ``` This should generate many log files for all the tools/tests combinations and an `out/report.html` file with a summary of the tested features and tools. If you don't want to generate the report file, but are interested in just running all the tests, you can run: ```bash make tests ``` ## Adding new test cases Adding a new test case is a two step process. First you create the test case itself which should use only a minimal required subset of SystemVerilog to test a particular feature. Additionally each test should cover only a single feature. If the test must use several features, each of those must be also covered in separate test cases. After creating a new test case it must be correctly tagged: * `name` - must be unique and should be directly related to what the test case covers. * `description` - should provide a short description that will be visible in the report page. * `should_fail_because` - must be used if the test is expected to fail and should contain the reason of failure. * `files` - is a list of files used by this test case, can be omitted to use only the main file with metadata. * `incdirs` - can be used to provide a list of include directories, can be omitted to use only the default ones. * `top_module` - optional, allows to specify which module is the top one. * `tags` - tag must be used to specify which part of SystemVerilog specification this test case covers. * `defines` - provides a list of macros for preprocessor. If the test case uses several SystemVerilog features, only the feature directly tested should be included in tags. List of existing tags is located in `conf/lrm.conf`. Finally the file containing the test case and metadata should be placed in `tests/chapter-([0-9]+)/` subdirectory based on the `tags` fields specified earlier. ## Importing existing tests from a test suite/core/tool 1. Add the tests as a submodule to this repository via `git submodule add third_party//`. If you want to add tests from a tool that is already in `third_party/tools` you can skip this step. 2. Add a new tag named `` to `conf/lrm.conf` together with a short description. 3. Generate wrapper `.sv` files by either: * Adding a new config to `conf/generators/meta-path/` that will be used by `generators/path_generator`. * Adding a new generator script to `generators/` that will create required wrappers. First method works well with test suites in which each test case is contained in a separate Verilog file. If the test suite provides metadata that must be processed or you are importing an IP core then you should create custom generator script. Use tag that you added in the previous step. ## Adding a new tool 1. Add the tool as a submodule to this repository via `git submodule add third_party/tools/`. 2. Add a target for building and installing the tool manually in `tools/runners.mk` 3. Create a new runner script in `tools/runners/.py` that will contain a subclass of `BaseRunner` named ``. This subclass will need to at least implement the following methods: * `__init__` to provide general information about the tool. * `prepare_run_cb` to prepare correct tool invocation that will be used during tests. If the new tool is a Python library, reimplement `run` and other supporting methods instead of implementing `prepare_run_cb`. ## Supported tools * [Yosys](https://github.com/yosysHQ/yosys) * [Odin II](https://verilogtorouting.org) * [Verilator](https://verilator.org) * [Icarus](http://iverilog.icarus.com) * [slang](https://github.com/MikePopoloski/slang) * [sv2v(zachjs)](https://github.com/zachjs/sv2v) * [tree-sitter-systemverilog](https://github.com/gmlarumbe/tree-sitter-systemverilog) * [tree-sitter-verilog](https://github.com/tree-sitter/tree-sitter-verilog) * [sv-parser](https://github.com/dalance/sv-parser) * [moore](http://llhd.io) * [verible](https://github.com/google/verible) * [circt-verilog](https://github.com/llvm/circt) * [yosys-slang](https://github.com/povik/yosys-slang) ================================================ FILE: conf/environment.yml ================================================ # Copyright (C) 2019-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC name: sv-test-env channels: - LiteX-Hub # - pkgw-forge # - conda-forge dependencies: # - LiteX-Hub::iverilog # - LiteX-Hub::moore # - LiteX-Hub::odin_ii # - LiteX-Hub::slang # - LiteX-Hub::surelog # - LiteX-Hub::sv-parser # - LiteX-Hub::tree-sitter-verilog # - LiteX-Hub::yosys-uhdm # - LiteX-Hub::verible # - LiteX-Hub::verilator # - gxx_impl_linux-64 # - LiteX-Hub::yosys # - LiteX-Hub::antmicro-yosys-complete # - LiteX-Hub::zachjs-sv2v - ccache - python=3.8 - pip - pip: # Packages installed from PyPI - -r requirements.txt ================================================ FILE: conf/feature-analyzer/keywords.yml ================================================ # Copyright (C) 2019-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC tags: 5.6: - 'accept_on' - 'default' - 'forkjoin' - 'alias' - 'defparam' - 'function' - 'always' - 'design' - 'generate' - 'always_comb' - 'disable' - 'genvar' - 'always_ff' - 'dist' - 'global' - 'always_latch' - 'do' - 'highz0' - 'and' - 'edge' - 'highz1' - 'assert' - 'else' - 'if' - 'assign' - 'end' - 'iff' - 'assume' - 'endcase' - 'ifnone' - 'automatic' - 'endchecker' - 'ignore_bins' - 'before' - 'endclass' - 'illegal_bins' - 'begin' - 'endclocking' - 'implements' - 'bind' - 'endconfig' - 'implies' - 'bins' - 'endfunction' - 'import' - 'binsof' - 'endgenerate' - 'incdir' - 'bit' - 'endgroup' - 'include' - 'break' - 'endinterface' - 'initial' - 'buf' - 'endmodule' - 'inout' - 'bufif0' - 'endpackage' - 'input' - 'bufif1' - 'endprimitive' - 'inside' - 'byte' - 'endprogram' - 'instance' - 'case' - 'endproperty' - 'int' - 'casex' - 'endspecify' - 'integer' - 'casez' - 'endsequence' - 'interconnect' - 'cell' - 'endtable' - 'interface' - 'chandle' - 'endtask' - 'intersect' - 'checker' - 'enum' - 'join' - 'class' - 'event' - 'join_any' - 'clocking' - 'eventually' - 'join_none' - 'cmos' - 'expect' - 'large' - 'config' - 'export' - 'let' - 'const' - 'extends' - 'liblist' - 'constraint' - 'extern' - 'library' - 'context' - 'final' - 'local' - 'continue' - 'first_match' - 'localparam' - 'cover' - 'for' - 'logic' - 'covergroup' - 'force' - 'longint' - 'coverpoint' - 'foreach' - 'macromodule' - 'cross' - 'forever' - 'matches' - 'deassign' - 'fork' - 'medium' - 'modport' - 'reject_on' - 'time' - 'module' - 'release' - 'timeprecision' - 'nand' - 'repeat' - 'timeunit' - 'negedge' - 'restrict' - 'tran' - 'nettype' - 'return' - 'tranif0' - 'new' - 'rnmos' - 'tranif1' - 'nexttime' - 'rpmos' - 'tri' - 'nmos' - 'rtran' - 'tri0' - 'nor' - 'rtranif0' - 'tri1' - 'noshowcancelled' - 'rtranif1' - 'triand' - 'not' - 's_always' - 'trior' - 'notif0' - 's_eventually' - 'trireg' - 'notif1' - 's_nexttime' - 'type' - 'null' - 's_until' - 'typedef' - 'or' - 's_until_with' - 'union' - 'output' - 'scalared' - 'unique' - 'package' - 'sequence' - 'unique0' - 'packed' - 'shortint' - 'unsigned' - 'parameter' - 'shortreal' - 'until' - 'pmos' - 'showcancelled' - 'until_with' - 'posedge' - 'signed' - 'untyped' - 'primitive' - 'small' - 'use' - 'priority' - 'soft' - 'uwire' - 'program' - 'solve' - 'var' - 'property' - 'specify' - 'vectored' - 'protected' - 'specparam' - 'virtual' - 'pull0' - 'static' - 'void' - 'pull1' - 'string' - 'wait' - 'pulldown' - 'strong' - 'wait_order' - 'pullup' - 'strong0' - 'wand' - 'pulsestyle_ondetect' - 'strong1' - 'weak' - 'pulsestyle_onevent' - 'struct' - 'weak0' - 'pure' - 'super' - 'weak1' - 'rand' - 'supply0' - 'while' - 'randc' - 'supply1' - 'wildcard' - 'randcase' - 'sync_accept_on' - 'wire' - 'randsequence' - 'sync_reject_on' - 'with' - 'rcmos' - 'table' - 'within' - 'real' - 'tagged' - 'wor' - 'realtime' - 'task' - 'xnor' - 'ref' - 'this' - 'xor' - 'reg' - 'throughout' ================================================ FILE: conf/feature-analyzer/operators.yml ================================================ # Copyright (C) 2019-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC tags: 5.5: - '=' - '+=' - '-=' - '*=' - '/=' - '%=' - '&=' - '|=' - '^=' - '<<=' - '>>=' - '<<<=' - '>>>=' - '!' - '~' - '&' - '~&' - '|' - '~|' - '^' - '~^' - '^~' - '+' - '-' - '*' - '/' - '%' - '==' - '!=' - '===' - '!==' - '==?' - '!=?' - '&&' - '||' - '**' - '<' - '<=' - '>' - '>=' - '&' - '>>>' - '<<<' - '->' - '<->' - '++' - '--' - '>>' - '<<' 10.4: - '=' - '+=' - '-=' - '*=' - '/=' - '%=' - '&=' - '|=' - '^=' - '<<=' - '>>=' - '<<<=' - '>>>=' - '<=' 11.3: - '=' - '+=' - '-=' - '*=' - '/=' - '%=' - '&=' - '|=' - '^=' - '<<=' - '>>=' - '<<<=' - '>>>=' - '?' - '+' - '-' - '!' - '~' - '&' - '~&' - '|' - '~|' - '^' - '~^' - '^~' - '*' - '/' - '%' - '==' - '!=' - '===' - '!==' - '==?' - '!=?' - '&&' - '||' - '**' - '<' - '<=' - '>' - '>=' - '>>' - '<<' - '>>>' - '<<<' - '++' - '--' - '->' - '<->' ================================================ FILE: conf/feature-analyzer/tags.yml ================================================ # Copyright (C) 2019-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC tags: 5.4: - '//' - '/*' - '*/' 5.6: - '`__FILE__' - '`__LINE__' - '`begin_keywords' - '`celldefine' - '`default_nettype' - '`define' - '`else' - '`elsif' - '`end_keywords' - '`endcelldefine' - '`endif' - '`ifdef' - '`ifndef' - '`include' - '`line' - '`nounconnected_drive' - '`pragma' - '`resetall' - '`timescale' - '`unconnected_drive' - '`undef' - '`undefineall' 6.3: - 'small' - 'medium' - 'large' 6.6: - 'wire' - 'tri' - 'uwire' - 'wor' - 'wand' - 'trior' - 'triand' - 'trireg' - 'tri0' - 'tri1' - 'supply0' - 'supply1' - 'nettype' - 'interconnect' 6.9: - 'reg' - 'logic' - 'bit' 6.11: - 'logic' - 'reg' - 'integer' - 'time' - 'bit' - 'int' - 'byte' - 'shortint' - 'int' - 'integer' - 'longint' - 'unsigned' - 'signed' 6.12: - 'real' - 'shortreal' - 'realtime' 6.13: - 'void' 6.14: - 'chandle' 6.15: - 'class' 6.16: - 'string' 6.17: - 'event' 6.18: - 'typedef' 6.19: - 'enum' 6.20: - 'localparam' - 'parameter' - 'specparam' - 'const' 6.23: - 'type' 6.24: - '$cast' 7.2: - 'struct' - 'struct packed' 7.3: - 'union' - 'union packed' - 'union tagged' - 'union tagged packed' 7.5: - '[]' 7.8: - '[*]' 7.10: - '[$]' - 'pop_front' - 'pop_back' - 'push_front' - 'pop_front' 7.11: - '$left' - '$right' - '$low' - '$high' - '$increment' - '$size' - '$dimensions' - '$unpacked_dimensions' 8.3: - 'class' - 'virtual class' 8.7: - 'function new' 8.10: - 'static function' 8.11: - 'this.' 8.13: - 'extends' 8.15: - 'super.' 8.16: - '$cast' 8.20: - 'virtual function' 8.21: - 'virtual class' - 'pure virtual function' 8.23: - '::' 8.26: - 'interface class' 9.2: - 'initial' - 'always' - 'always_comb' - 'always_latch' - 'always_ff' - 'final' 9.3: - 'begin' - 'end' - 'fork' - 'join' - 'join_any' - 'join_none' 9.4: - 'repeat' - 'wait' - 'wait fork' - 'wait_order' 9.6: - 'wait' - 'wait fork' - 'wait_order' - 'disable' - 'disable fork' 9.7: - 'kill' - 'await' - 'suspend' - 'resume' 10.3: - 'assign' - 'supply1' - 'strong1' - 'pull1' - 'weak1' - 'highz1' - 'supply0' - 'strong0' - 'pull0' - 'weak0' - 'highz0' 10.6: - 'assign' - 'deassign' - 'force' - 'release' 10.11: - 'alias' 11.9: - 'tagged' 11.12: - 'let' 12.4: - 'if' - 'else if' - 'else' - 'unique' - 'unique0' - 'priority' - 'matches' 12.5: - 'case' - 'casez' - 'casex' - 'endcase' - 'matches' - 'inside' - 'default' 12.6: - 'matches' - 'tagged' 12.7: - 'forever' - 'repeat' - 'while' - 'for' - 'do' - 'while' - 'foreach' 12.8: - 'break' - 'continue' - 'return' 13.3: - 'task' - 'endtask' 13.4: - 'function' - 'endfunction' 14.3: - 'clocking' - 'endclocking' 14.11: - '##' 14.12: - 'default clocking' 14.14: - 'global clocking' 15.3: - 'semaphore' 15.4: - 'mailbox' 15.5: - 'event' - 'wait_order' 16.2: - 'assert' - 'assume' - 'cover' - 'restrict' 16.4: - 'assert #0' - 'assert final' - 'assume #0' - 'assume final' - 'cover #0' - 'cover final' 16.8: - 'sequence' - 'endsequence' 16.9: - '$sampled' - '$rose' - '$fell' - '$stable' - '$changed' - '$past' - '$past_gclk' - '$rose_gclk' - '$fell_gclk' - '$stable_gclk' - '$changed_gclk' - '$future_gclk' - '$rising_gclk' - '$falling_gclk' - '$steady_gclk' - '$changing_gclk' - 'intersect' - 'first_match' - 'throughout' - 'within' 16.12: - 'property' - 'endproperty' - 'nexttime' - 's_nexttime' - 'iff' - 'until' - 's_until' - 'until_with' - 's_until_with' - 'implies' - 's_always' - 'eventually' - 's_eventually' - 'accept_on' - 'reject_on' - 'sync_accept_on' - 'sync_reject_on' - '#-#' - '#=#' 16.17: - 'expect' 17.2: - 'checker' - 'endchecker' 17.6: - 'covergroup' - 'coverpoint' - 'endgroup' 20.2: - '$finish' - '$stop' - '$exit' 20.3: - '$realtime' - '$stime' - '$time' 20.4: - '$printtimescale' - '$timeformat' 20.5: - '$bitstoreal' - '$realtobits' - '$bitstoshortreal' - '$shortrealtobits' - '$itor' - '$rtoi' - '$signed' - '$unsigned' - '$cast' 20.6: - '$bits' - '$isunbounded' - '$typename' 20.7: - '$unpacked_dimensions' - '$dimensions' - '$left' - '$right' - '$low' - '$high' - '$increment' - '$size' 20.8: - '$clog2' - '$asin' - '$ln' - '$acos' - '$log10' - '$atan' - '$exp' - '$atan2' - '$sqrt' - '$hypot' - '$pow' - '$sinh' - '$floor' - '$cosh' - '$ceil' - '$tanh' - '$sin' - '$asinh' - '$cos' - '$acosh' - '$tan' - '$atanh' 20.9: - '$countbits' - '$countones' - '$onehot' - '$onehot0' - '$isunknown' 20.10: - '$fatal' - '$error' - '$warning' - '$info' 20.11: - '$fatal' - '$error' - '$warning' - '$info' 20.12: - '$asserton' - '$assertoff' - '$assertkill' - '$assertcontrol' - '$assertpasson' - '$assertpassoff' - '$assertfailon' - '$assertfailoff' - '$assertnonvacuouson' - '$assertvacuousoff' 20.13: - '$sampled' - '$rose' - '$fell' - '$stable' - '$changed' - '$past' - '$past_gclk' - '$rose_gclk' - '$fell_gclk' - '$stable_gclk' - '$changed_gclk' - '$future_gclk' - '$rising_gclk' - '$falling_gclk' - '$steady_gclk' - '$changing_gclk' 20.14: - '$coverage_control' - '$coverage_get_max' - '$coverage_get' - '$coverage_merge' - '$coverage_save' - '$get_coverage' - '$set_coverage_db_name' - '$load_coverage_db' 20.15: - '$random' - '$dist_chi_square' - '$dist_erlang' - '$dist_exponential' - '$dist_normal' - '$dist_poisson' - '$dist_t' - '$dist_uniform' 20.16: - '$q_initialize' - '$q_add' - '$q_remove' - '$q_full' - '$q_exam' 20.17: - '$async$and$array' - '$async$and$plane' - '$async$nand$array' - '$async$nand$plane' - '$async$or$array' - '$async$or$plane' - '$async$nor$array' - '$async$nor$plane' - '$sync$and$array' - '$sync$and$plane' - '$sync$nand$array' - '$sync$nand$plane' - '$sync$or$array' - '$sync$or$plane' - '$sync$nor$array' - '$sync$nor$plane' 20.18: - '$system' 21.2: - '$display' - '$displayb' - '$displayh' - '$displayo' - '$strobe' - '$strobeb' - '$strobeh' - '$strobeo' - '$write' - '$writeb' - '$writeh' - '$writeo' - '$monitor' - '$monitorb' - '$monitorh' - '$monitoro' - '$monitoroff' - '$monitoron' 21.3: - '$fclose' - '$fdisplay' - '$fdisplayb' - '$fdisplayh' - '$fdisplayo' - '$fstrobe' - '$fstrobeb' - '$fstrobeh' - '$fstrobeo' - '$swrite' - '$swriteb' - '$swriteh' - '$swriteo' - '$fscanf' - '$fread' - '$fseek' - '$fflush' - '$feof' - '$fopen' - '$fwrite' - '$fwriteb' - '$fwriteh' - '$fwriteo' - '$fmonitor' - '$fmonitorb' - '$fmonitorh' - '$fmonitoro' - '$sformat' - '$sformatf' - '$fgetc' - '$ungetc' - '$fgets' - '$sscanf' - '$rewind' - '$ftell' - '$ferror' 21.4: - '$readmemb' - '$readmemh' 21.5: - '$writememb' - '$writememh' 21.6: - '$test$plusargs' - '$value$plusargs' 21.7: - '$dumpfile' - 'idumpoff' - '$dumpall' - '$dumpflush' - '$dumpportsoff' - '$dumpportsall' - '$dumpportsflush' - '$dumpvars' - '$dumpon' - '$dumplimit' - '$dumpports' - '$dumpportson' - '$dumpportslimit' 22.3: - '`resetall' 22.4: - '`include' 22.5: - '`define' - '`undef' - '`undefineall' 22.6: - '`else' - '`elsif' - '`endif' - '`ifdef' - '`ifndef' 22.7: - '`timescale' 22.8: - '`default_nettype' 22.9: - '`unconnected_drive' - '`nounconnected_drive' 22.10: - '`celldefine' - '`endcelldefine' 22.11: - '`pragma' 22.12: - '`line' 22.13: - '`__FILE__' - '`__LINE__' 22.14: - '`begin_keywords' - '`end_keywords' 23.2: - 'module' - 'macromodule' - 'endmodule' 23.5: - 'extern module' 24.3: - 'program' - 'endprogram' 25.3: - 'interface' - 'endinterface' 26.2: - 'package' - 'endpackage' 26.3: - 'import' ================================================ FILE: conf/fusesoc-configs/ibex-sim.yml ================================================ # Copyright (C) 2019-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC name: ibex description: Full ibex core test top_module: ibex_simple_system tags: ibex path: third_party/cores/ibex command: fusesoc --cores-root third_party/cores/ibex run --target=sim --setup lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast conf_file: build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/lowrisc_ibex_ibex_simple_system_0.vc test_file: ibex-sim.sv timeout: 100 compatible-runners: verilator slang circt-verilog type: parsing elaboration simulation_without_run ================================================ FILE: conf/fusesoc-configs/veer-eh1-sim.yml ================================================ # Copyright (C) 2019-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC name: veer-eh1 description: Full VeeR EH1 core test top_module: tb_top tags: veer-eh1 path: third_party/cores/veer-eh1 command: fusesoc --cores-root third_party/cores/veer-eh1 run --target=sim --setup --build-root build/veer-eh1_sim chipsalliance.org:cores:VeeR_EH1:1.8 conf_file: build/veer-eh1_sim/sim-verilator/chipsalliance.org_cores_VeeR_EH1_1.8.vc test_file: veer-eh1-sim.sv timeout: 180 compatible-runners: verilator slang circt-verilog type: parsing elaboration simulation_without_run ================================================ FILE: conf/fusesoc-configs/veer-eh1-synth.yml ================================================ # Copyright (C) 2019-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC name: veer-eh1 description: Full VeeR EH1 core test top_module: veer-eh1_wrapper tags: veer-eh1 path: third_party/cores/veer-eh1 command: fusesoc --cores-root third_party/cores/veer-eh1 run --target=synth --setup --build-root build/veer-eh1_synth chipsalliance.org:cores:VeeR_EH1:1.8 conf_file: build/veer-eh1_synth/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.8.tcl test_file: veer-eh1-synth.sv timeout: 180 compatible-runners: yosys-synlig yosys yosys-sv zachjs-sv2v icarus moore moore-parse odin sv-parser tree-sitter-verilog verible verible_extractor Surelog slang-parse circt-verilog type: parsing elaboration ================================================ FILE: conf/generators/meta-path/basejump.json ================================================ { "name": "BaseJumpSTL", "project": "basejump", "paths": [ [ "cores", "basejump_stl", "*" ] ], "matches": [ "*.sv" ], "commons": [ "cores/basejump_stl/bsg_misc/bsg_defines.sv", "cores/basejump_stl/bsg_cache/bsg_cache_pkg.sv", "cores/basejump_stl/bsg_cache/bsg_cache_non_blocking_pkg.sv", "cores/basejump_stl/bsg_dmc/bsg_dmc_pkg.sv", "cores/basejump_stl/bsg_noc/bsg_noc_pkg.sv", "cores/basejump_stl/bsg_noc/bsg_mesh_router_pkg.sv", "cores/basejump_stl/bsg_noc/bsg_wormhole_router_pkg.sv", "cores/basejump_stl/bsg_tag/bsg_tag_pkg.sv", "cores/basejump_stl/bsg_test/bsg_dramsim3_pkg.sv", "cores/basejump_stl/bsg_axi/bsg_axi_pkg.sv" ], "incdirs": [ "cores/basejump_stl/bsg_misc", "cores/basejump_stl/bsg_noc", "cores/basejump_stl/bsg_clk_gen" ], "timeouts": { "bsg_scatter_gather.sv": "60", "bsg_launch_sync_sync.sv": "60", "bsg_cache.sv": "30", "bsg_cache_non_blocking_mhu.sv": "30", "bsg_tag_master.sv": "30", "bsg_round_robin_fifo_to_fifo.sv": "30" }, "blacklist": [ "bsg_1_to_n_tagged_fifo_shared.sv", "bsg_cache_BaseJumpSTL_bsg_cache_to_axi.sv", "bsg_cache_BaseJumpSTL_bsg_cache_to_axi_rx.sv", "bsg_cache_BaseJumpSTL_bsg_cache_to_axi_tx.sv", "bsg_cache_non_blocking_pkg.sv", "bsg_cache_pkg.sv", "bsg_cache_to_dram_ctrl.sv", "bsg_dmc_pkg.sv", "bsg_dramsim3_pkg.sv", "bsg_mem_banked_crossbar.sv", "bsg_mem_multiport.sv", "bsg_mem_multiport_latch_write_banked_bypassing.sv", "bsg_mem_multiport_latch_write_banked_bypassing_sync.sv", "bsg_mesh_router_pkg.sv", "bsg_nonsynth_mixin_motherboard.sv", "bsg_pg_tree.sv", "bsg_sbox_ctrl.sv", "bsg_sbox_ctrl_concentrate.sv", "bsg_sparse_to_dense_boolean.sv", "bsg_tag_pkg.sv", "bsg_test_BaseJumpSTL_bsg_nonsynth_axi_mem.sv", "bsg_wormhole_router_pkg.sv", "test_bsg_clock_params.sv", "bsg_dmc_xilinx_ui_trace_replay.sv", "bsg_nonsynth_profiler.sv" ], "fake_topmodule": true, "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/hdlconvertor.json ================================================ { "name": "hdlconvertor", "project": "hdlconv", "paths": [ ["tests", "hdlconvertor", "tests", "sv_test", "others"], ["tests", "hdlconvertor", "tests", "verilog", "*"] ], "matches": ["*.sv", "*.v"], "blacklist": [ "aFifo.v", "adder_implicit.v", "aes.v", "directive_verilogpp.v", "fifo_rx.sv", "hierarchical_name_of_type.sv", "lfsr_updown_tb.v", "parity_using_function2.v", "stm_import.sv" ], "type": "parsing", "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/hdlconvertor_std2012.json ================================================ { "name": "hdlconvertor_std2012", "project": "hdlconv_std2012", "paths": [ ["tests", "hdlconvertor", "tests", "sv_test", "std2012"] ], "matches": ["*.sv", "*.v"], "blacklist": [ "p12.sv", "p59.sv", "p138.sv", "p140.sv", "p160_2.sv", "p76.sv", "p77.sv", "p87.sv" ], "type": "parsing", "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/hdlconvertor_std2017.json ================================================ { "name": "hdlconvertor_std2017", "project": "hdlconv_std2017", "paths": [ ["tests", "hdlconvertor", "tests", "sv_test", "std2017"] ], "matches": ["*.sv", "*.v"], "blacklist": [ "p95.sv", "p137.sv", "p141.sv", "p142.sv", "p172.sv", "p174_2.sv", "p176.sv", "p180.sv", "p180_2.sv", "p188_3.sv", "p191.sv", "p196_2.sv", "p197.sv", "p201.sv", "p220.sv", "p221.sv", "p229.sv", "p229_2.sv", "p253.sv", "p294.sv", "p295.sv", "p296.sv", "p297.sv", "p333.sv", "p335.sv", "p338.sv", "p339.sv", "p340.sv", "p341.sv", "p342.sv", "p346.sv", "p352.sv", "p477.sv", "p478.sv", "p499.sv", "p504.sv", "p504_2.sv", "p507.sv", "p510.sv", "p522.sv", "p524.sv", "p532.sv", "p535.sv", "p550.sv", "p552.sv", "p557.sv", "p558.sv", "p560.sv", "p565.sv", "p566.sv", "p568.sv", "p573.sv", "p576.sv", "p578.sv", "p580.sv", "p581.sv", "p584.sv", "p594.sv", "p621.sv", "p622.sv", "p700.sv", "p701.sv", "p702.sv", "p704.sv", "p706.sv", "p710.sv", "p711.sv", "p713.sv", "p714.sv", "p716.sv", "p720.sv", "p721.sv", "p724.sv", "p726.sv", "p731.sv", "p732.sv", "p734.sv", "p735.sv", "p736.sv", "p753.sv", "p755.sv", "p764.sv", "p772.sv", "p773.sv", "p777.sv", "p782.sv", "p793.sv", "p794.sv", "p795.sv", "p802.sv", "p825.sv", "p832.sv", "p833.sv", "p834.sv", "p836.sv", "p837.sv", "p886.sv", "p940.sv" ], "type": "parsing", "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/projf-explore.json ================================================ { "name": "projf", "project": "projf-explore", "paths": [ ["tests", "projf-explore", "*", "*", "*"] ], "matches": ["*.sv"], "type": "parsing", "blacklist": [ "MMCME2_BASE.sv", "OBUFDS.sv", "OSERDESE2.sv", "SB_IO.sv", "SB_PLL40_PAD.sv", "clock_1080p.sv", "clock_480p.sv", "clock_720p.sv", "clock_gen_1080p.sv", "clock_gen_480p.sv", "clock_gen_480p_tb.sv", "clock_gen_720p.sv", "clock_gen_sys.sv", "clock_sys.sv", "clock_tb.sv", "clut_simple_tb.sv", "display_480p_tb.sv", "display_720p_tb.sv", "div_int_tb.sv", "div_tb.sv", "draw_char_tb.sv", "draw_circle_tb.sv", "draw_line_1d_tb.sv", "draw_line_tb.sv", "draw_rectangle_fill_tb.sv", "draw_rectangle_tb.sv", "draw_triangle_fill_tb.sv", "draw_triangle_tb.sv", "dvi_generator.sv", "get_glyph_line_tb.sv", "lfsr_tb.sv", "life_tb.sv", "linebuffer_simple_tb.sv", "oserdes_10b.sv", "render_circles.sv", "render_circles_fill.sv", "render_cube.sv", "render_cube_fill.sv", "render_cube_shatter.sv", "render_edge.sv", "render_line.sv", "render_rects.sv", "render_rects_fill.sv", "render_square_colr.sv", "render_teleport.sv", "render_triangles.sv", "render_triangles_fill.sv", "simple_480p_tb.sv", "simple_720p_tb.sv", "sine_table_tb.sv", "spram.sv", "spram_nibble.sv", "sprite_inline_tb.sv", "sprite_rom_tb.sv", "sprite_tb.sv", "sqrt_int_tb.sv", "sqrt_tb.sv", "starfield_tb.sv", "tmds_out.sv", "top.sv", "top_bounce.sv", "top_castle.sv", "top_colour.sv", "top_colour_cycle.sv", "top_david_16colr.sv", "top_david_fizzle.sv", "top_david_mono.sv", "top_david_scale.sv", "top_demo.sv", "top_demo_sb.sv", "top_flag_ethiopia.sv", "top_flag_sweden.sv", "top_graphing.sv", "top_greet.sv", "top_greet_v1.sv", "top_hedgehog.sv", "top_hello.sv", "top_hello_en.sv", "top_hello_jp.sv", "top_hitomezashi.sv", "top_hourglass.sv", "top_mandel.sv", "top_lfsr.sv", "top_life.sv", "top_pong.sv", "top_rasterbars.sv", "top_sinescroll.sv", "top_space_f.sv", "top_square.sv", "top_starfields.sv", "top_tinyf_inline.sv", "top_tinyf_move.sv", "top_tinyf_rom.sv", "top_tinyf_scale.sv", "top_uart.sv", "xd_tb.sv" ], "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/utd-systemverilog.json ================================================ { "name": "utd-sv", "project": "utd-sv", "paths": [ ["tests", "utd-sv"] ], "matches": ["*.v"], "type": "parsing", "results_group": "imported", "blacklist": [ "bw_dtl_impctl_pulldown.v", "bw_dtl_impctl_pullup.v", "bw_r_l2d.v", "bw_zzctu_sync.v", "c2i_buf.v", "c2i_sdp.v", "casez.v", "ccx.v", "ccx_arb_atomq.v", "ccx_arb_srcq.v", "ccx_arbc.v", "chip8_config.v", "cluster_header_dup.v", "core1_config.v", "cpx.v", "cpx_buf_pt.v", "cpx_buf_top.v", "cpx_datacx2_ff.v", "cpx_dp0.v", "cpx_dp2.v", "cpx_dp4.v", "cpx_dp6.v", "cpx_dp_array.v", "cpx_dp_halfarray.v", "cpx_io_grant_ff.v", "ctu_bottom_rptr.v", "ctu_bottom_rptr2.v", "ctu_clsp_clkgn_clksel.v", "ctu_clsp_clkgn_clksw.v", "ctu_clsp_clkgn_ssiclk.v", "ctu_clsp_cmpgif.v", "ctu_clsp_jbusgif.v", "ctu_clsp_synch_cljl.v", "ctu_clsp_synch_dldg.v", "ctu_clsp_synch_jldl.v", "ctu_sync_header.v", "ctu_top_rptr.v", "ctu_top_rptr2.v", "dbginit_mon.v", "dbl_buf.v", "efc_lib.v", "expression_tostring.v", "ff_dram_sc_bank0.v", "ff_dram_sc_bank1.v", "ff_dram_sc_bank2.v", "ff_dram_sc_bank3.v", "ff_jbi_sc0_1.v", "ff_jbi_sc0_2.v", "ff_jbi_sc1_1.v", "ff_jbi_sc1_2.v", "ff_jbi_sc2_1.v", "ff_jbi_sc2_2.v", "ff_jbi_sc3_1.v", "ff_jbi_sc3_2.v", "flop_rptrs_xa0.v", "flop_rptrs_xa1.v", "flop_rptrs_xb0.v", "flop_rptrs_xb1.v", "flop_rptrs_xb2.v", "flop_rptrs_xb3.v", "flop_rptrs_xc0.v", "flop_rptrs_xc1.v", "flop_rptrs_xc2.v", "flop_rptrs_xc3.v", "flop_rptrs_xc4.v", "flop_rptrs_xc5.v", "flop_rptrs_xc6.v", "flop_rptrs_xc7.v", "forever-disable.v", "fpu.v", "fpu_add_ctl.v", "fpu_add_exp_dp.v", "fpu_div.v", "fpu_div_exp_dp.v", "fpu_in_ctl.v", "fpu_in_dp.v", "fpu_mul_ctl.v", "fpu_mul_exp_dp.v", "fpu_out.v", "fpu_out_ctl.v", "fpu_out_dp.v", "fpu_rptr_groups.v", "generate.v", "i2c_fctrl.v", "i2c_fdp.v", "ifdef-2.v", "ifdef-2.v", "io_cpx_reqdata_ff.v", "lsu_dcdp.v", "lsu_pcx_qmon.v", "lsu_qdp1.v", "lsu_qdp2.v", "lsu_rrobin_picker2.v", "lsu_stb_ctldp.v", "lsu_stb_rwdp.v", "lsu_tagdp.v", "lsu_tlbdp.v", "module-instance.v", "operators.v", "pad_ddr0.v", "pad_ddr1.v", "pad_ddr2.v", "pad_ddr3.v", "pad_jbusf.v", "pad_jbusl.v", "pad_jbusr.v", "pcx.v", "pcx_buf_pt.v", "pcx_buf_pt1.v", "pcx_buf_top.v", "pcx_data_px2.v", "pcx_dp0.v", "pcx_dp1.v", "pcx_dp2.v", "pcx_dp3.v", "pcx_dp4.v", "pcx_dp_array.v", "pcx_dp_array02.v", "pcx_dp_array134.v", "sc_0_1_dbg_rptr.v", "sc_2_3_dbg_rptr.v", "scbuf.v", "scbuf_evict.v", "scbuf_fbd.v", "scbuf_rdmard.v", "scdata_ctr_io.v", "scdata_periph_io.v", "scdata_subbank.v", "sctag_arbaddrdp.v", "sctag_dbgdp.v", "sctag_deccdp.v", "sctag_dir_ctl.v", "sctag_dir_in.v", "sctag_dir_out.v", "sctag_dirrep.v", "sctag_dirvec_dp.v", "sctag_oqdp.v", "sctag_retdp.v", "sctag_scbufrep.v", "sctag_snpctl.v", "sctag_snpdp.v", "sctag_tagdp.v", "sctag_tagl_dp.v", "sctag_ua_dp.v", "sctag_vd_dp.v", "sctag_vuad_ctl.v", "sctag_vuad_dpm.v", "sctag_vuad_io.v", "sctag_vuadcol_dp.v", "sctag_vuaddp_ctl.v", "sctag_wbctl.v", "sparc_exu_aluaddsub.v", "sparc_exu_alulogic.v", "sparc_exu_byp_eccgen.v", "sparc_exu_ecc.v", "sparc_exu_ecl_cnt6.v", "sparc_exu_ecl_divcntl.v", "sparc_exu_shft.v", "sparc_ffu_ctl_visctl.v", "sparc_ffu_vis.v", "sparc_ifu_sscan.v", "sparc_ifu_thrcmpl.v", "spu_lsurpt1.v", "spu_maexp.v", "spu_mald.v", "spu_mast.v", "std-3.11.1-parameters.v", "sync_pulse_synchronizer.v", "synchronizer_asr.v", "synchronizer_asr_dup.v", "tlu_misctl.v", "ucb_bus_in.v", "ucb_bus_out.v", "ucb_flow_jbi.v", "ucb_flow_spi.v" ] } ================================================ FILE: conf/generators/meta-path/yosys-asicworld.json ================================================ { "name": "asicworld", "project": "yosys", "paths": [ ["tools", "yosys", "tests", "asicworld"] ], "matches": ["*.v"], "blacklist": ["code_verilog_tutorial_counter_tb.v", "code_hdl_models_arbiter_tb.v", "code_verilog_tutorial_first_counter_tb.v", "code_verilog_tutorial_fsm_full_tb.v", "code_hdl_models_full_subtracter_gates.v", "simple_values.v", "svinterface_at_top.sv"], "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/yosys-errors.json ================================================ { "name": "errors", "project": "yosys", "should_fail_because": "this test imported from yosys repository contains intentional syntax error", "paths": [ ["tools", "yosys", "tests", "errors"] ], "matches": ["*.v"], "blacklist": ["syntax_err06.v", "syntax_err09.v", "syntax_err12.v", "syntax_err13.v"], "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/yosys-memories.json ================================================ { "name": "memories", "project": "yosys", "paths": [ ["tools", "yosys", "tests", "memories"] ], "matches": ["*.v"], "blacklist": ["issue00335.v"], "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/yosys-simple.json ================================================ { "name": "simple", "project": "yosys", "paths": [ ["tools", "yosys", "tests", "simple"] ], "matches": ["*.v"], "blacklist": ["hierdefparam.v", "memory.v", "values.v", "func_width_scope.v", "named_genblk.v", "mem2reg_bounds_tern.v", "module_scope_func.v"], "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/yosys-sva.json ================================================ { "name": "sva", "project": "yosys", "paths": [ ["tools", "yosys", "tests", "sva"] ], "matches": ["*.sv"], "blacklist": ["basic04.sv", "basic05.sv"], "results_group": "imported" } ================================================ FILE: conf/generators/meta-path/yosys-svinterfaces.json ================================================ { "name": "svinterfaces", "project": "yosys", "paths": [ ["tools", "yosys", "tests", "svinterfaces"] ], "matches": ["*.sv"], "blacklist": ["svinterface1.sv", "svinterface_at_top.sv", "load_and_derive.sv", "ondemand.sv", "resolve_types.sv"], "results_group": "imported" } ================================================ FILE: conf/generators/templates/assignment-sim.json ================================================ { "name": "assignment_sim", "filename": "11.4.1--{1}_assignment-sim-{4}.sv", "template": [ "/*", ":name: {1}_assignment_sim_{4}", ":description: {0}= assignment simulation test", ":type: simulation elaboration parsing", ":tags: 11.4.1", "*/", "module top();", "reg [31:0] a;", "wire [31:0] b;", "assign b = 32'd{3};", "final begin", " a = 32'd{2};", " a {0}= b;", " $display(\":assert: (int(%s) == %d)\", \"{2}{0}{3}\", a);", "end", "endmodule" ], "cartesian_product": "true", "values": [[ ["+", "plus"], ["-", "minus"], ["*", "mul"], ["/", "div"], ["%", "mod"], ["&", "and"], ["|", "or"], ["^", "xor"], ["<<", "log_shl"], [">>", "log_shr"] ], [ ["4", "3", "0"], ["4", "4", "1"] ]] } ================================================ FILE: conf/generators/templates/assignment.json ================================================ { "name": "assignment_op", "filename": "11.4.1--{1}_assignment.sv", "template": [ "/*", ":name: {1}_assignment", ":description: {0} assignment test", ":tags: 11.4.1", "*/", "module top();", "int a = 12;", "int b = 5;", "initial begin", " a {0} b;", "end", "endmodule" ], "values": [ ["=", "normal"], ["+=", "plus"], ["-=", "minus"], ["*=", "mul"], ["/=", "div"], ["%=", "mod"], ["&=", "and"], ["|=", "or"], ["^=", "xor"], ["<<=", "log_shl"], [">>=", "log_shr"], ["<<<=", "arith_shl"], [">>>=", "arith_shr"] ] } ================================================ FILE: conf/generators/templates/binary.json ================================================ { "name": "binary_op", "filename": "{2}--binary_op_{1}.sv", "template": [ "/*", ":name: binary_op_{1}", ":description: {0} operator test", ":tags: {2}", "*/", "module top();", "int a = 12;", "int b = 5;", "int c;", "initial begin", " c = a {0} b;", "end", "endmodule" ], "values": [ ["+", "plus", "11.4.3"], ["-", "minus", "11.4.3"], ["*", "mul", "11.4.3"], ["/", "div", "11.4.3"], ["%", "mod", "11.4.3"], ["==", "log_eq", "11.4.5"], ["!=", "log_neq", "11.4.5"], ["===", "case_eq", "11.4.5"], ["!==", "case_neq", "11.4.5"], ["==?", "wild_eq", "11.4.6"], ["!=?", "wild_neq", "11.4.6"], ["&&", "log_and", "11.4.7"], ["||", "log_or", "11.4.7"], ["**", "pow", "11.4.3"], ["<", "lt", "11.4.4"], ["<=", "le", "11.4.4"], [">", "gt", "11.4.4"], [">=", "ge", "11.4.4"], ["&", "bit_and", "11.4.8"], ["|", "bit_or", "11.4.8"], ["^", "bit_xor", "11.4.8"], ["^~", "bit_xnor", "11.4.8"], ["~^", "bit_xnor", "11.4.8"], [">>", "log_shr", "11.4.10"], ["<<", "log_shl", "11.4.10"], [">>>", "arith_shr", "11.4.10"], ["<<<", "arith_shl", "11.4.10"], ["->", "log_imp", "11.4.7"], ["<->", "log_equiv", "11.4.7"] ] } ================================================ FILE: conf/generators/templates/encapsulation-fail.json ================================================ { "name": "encapsulation", "filename": "8.18--{0}.sv", "template": [ "/*", ":name: {0}", ":description: encapsulation test", ":should_fail_because: {1}", ":tags: 8.18", ":type: simulation elaboration", "*/", "module top();", "class a_cls;", " local int a_loc = 21;", " protected int a_prot = 22;", " int a = 23;", "endclass", "class b_cls extends a_cls;", " local int b_loc = 31;", " protected int b_prot = 32;", " int b = 33;", " function void fun();", " $display({2});", " endfunction", "endclass", "b_cls b_obj;", "initial begin", " b_obj = new;", " $display(b_obj.{3});", " b_obj.fun();", "end", "endmodule" ], "values": [ ["inherited_local_from_outside", "It is illegal to access inherited local variable from subclass instance.", "b", "a_loc"], ["local_from_outside", "It is illegal to access local variable from class instance.", "b", "b_loc"], ["inherited_prot_from_outside", "It is illegal to access inherited protected variable from subclass instance.", "b", "a_prot"], ["prot_from_outside", "It is illegal to access protected variable from class instance.", "b", "b_prot"], ["inherited_local_from_inside", "It is illegal to access inherited local variable inside subclass.", "a_loc", "b"] ] } ================================================ FILE: conf/generators/templates/encapsulation-success.json ================================================ { "name": "encapsulation", "filename": "8.18--{0}.sv", "template": [ "/*", ":name: {0}", ":description: encapsulation test", ":tags: 8.18", ":type: simulation elaboration parsing", "*/", "module top();", "class a_cls;", " local int a_loc = 21;", " protected int a_prot = 22;", " int a = 23;", "endclass", "class b_cls extends a_cls;", " local int b_loc = 31;", " protected int b_prot = 32;", " int b = 33;", " function void fun();", " $display({1});", " endfunction", "endclass", "b_cls b_obj;", "initial begin", " b_obj = new;", " $display(b_obj.{2});", " b_obj.fun();", "end", "endmodule" ], "values": [ ["local_from_inside", "b_loc", "b"], ["inherited_prot_from_inside", "a_prot", "b"], ["prot_from_inside", "b_prot", "b"] ] } ================================================ FILE: conf/generators/templates/equality.json ================================================ { "name": "equality_operators_sim", "filename": "11.4.5--equality_operator_{4}.sv", "template": [ "/*", ":name: equality_operator_sim_{4}", ":description: equality operator test in simulation", ":type: simulation elaboration parsing", ":tags: 11.4.5", "*/", "module top();", "wire [7:0] a = {0};", "wire [7:0] b = {1};", "wire c;", "assign a = {0};", "assign b = {1};", "assign c = a {2} b;", "final begin", " $display(\":assert: ('%s' == '%d')\", \"{3}\", c);", "end", "endmodule" ], "values": [ ["8'b1101x001", "8'b1101x001", "==" , "x"], ["8'b1101x001", "8'b1101x000", "==" , "0"], ["8'b1101z001", "8'b1101z001", "==" , "x"], ["8'b1101z001", "8'b1101z000", "==" , "0"], ["8'b11011001", "8'b11011001", "==" , "1"], ["8'b11011001", "8'b11011000", "==" , "0"], ["8'b1101x001", "8'b1101x001", "!=" , "x"], ["8'b1101x001", "8'b1101x000", "!=" , "1"], ["8'b1101z001", "8'b1101z001", "!=" , "x"], ["8'b1101z001", "8'b1101z000", "!=" , "1"], ["8'b11011001", "8'b11011001", "!=" , "0"], ["8'b11011001", "8'b11011000", "!=" , "1"], ["8'b1101x001", "8'b1101x001", "===", "1"], ["8'b1101x001", "8'b1101x000", "===", "0"], ["8'b1101z001", "8'b1101z001", "===", "1"], ["8'b1101z001", "8'b1101z000", "===", "0"], ["8'b11011001", "8'b11011001", "===", "1"], ["8'b11011001", "8'b11011000", "===", "0"], ["8'b1101x001", "8'b1101x001", "!==", "0"], ["8'b1101x001", "8'b1101x000", "!==", "1"], ["8'b1101z001", "8'b1101z001", "!==", "0"], ["8'b1101z001", "8'b1101z000", "!==", "1"], ["8'b11011001", "8'b11011001", "!==", "0"], ["8'b11011001", "8'b11011000", "!==", "1"], ["8'b1101z001", "8'b1101x001", "===", "0"], ["8'b1101z001", "8'b1101x001", "==" , "x"] ] } ================================================ FILE: conf/generators/templates/force-assignments.json ================================================ { "name": "assignment-strengths", "filename": "10.3.4--assignment_{0}_{1}.sv", "template": [ "/*", ":name: cont_assignment_strength_{0}_{1}", ":description: {0} {1} assignment test", ":tags: 10.3.4", "*/", "module top(input a, input b);", "wire ({0}, {1}) w = a & b;", "endmodule" ], "values": [ ["supply1", "supply0"], ["strong1", "supply0"], ["pull1", "supply0"], ["weak1", "supply0"], ["highz1", "supply0"], ["supply1", "strong0"], ["strong1", "strong0"], ["pull1", "strong0"], ["weak1", "strong0"], ["highz1", "strong0"], ["supply1", "pull0"], ["strong1", "pull0"], ["pull1", "pull0"], ["weak1", "pull0"], ["highz1", "pull0"], ["supply1", "weak0"], ["strong1", "weak0"], ["pull1", "weak0"], ["weak1", "weak0"], ["highz1", "weak0"], ["supply1", "highz0"], ["strong1", "highz0"], ["pull1", "highz0"], ["weak1", "highz0"] ] } ================================================ FILE: conf/generators/templates/integers.json ================================================ { "name": "integers", "filename": "6.11--integer_{2}.sv", "template": [ "/*", ":name: integer_{2}", ":description: {1} {0}net test", ":tags: 6.11", "*/", "module top();", "{1} {0}v;", "endmodule" ], "values": [ ["", "shortint", "shortint"], ["", "int", "int"], ["", "longint", "longint"], ["", "byte", "byte"], ["", "bit", "bit"], ["", "logic", "logic"], ["", "reg", "reg"], ["", "integer", "integer"], ["", "time", "time"], ["signed ", "shortint", "signed_shortint"], ["signed ", "int", "signed_int"], ["signed ", "longint", "signed_longint"], ["signed ", "byte", "signed_byte"], ["signed ", "bit", "signed_bit"], ["signed ", "logic", "signed_logic"], ["signed ", "reg", "signed_reg"], ["signed ", "integer", "signed_integer"], ["signed ", "time", "signed_time"], ["unsigned ", "shortint", "unsigned_shortint"], ["unsigned ", "int", "unsigned_int"], ["unsigned ", "longint", "unsigned_longint"], ["unsigned ", "byte", "unsigned_byte"], ["unsigned ", "bit", "unsigned_bit"], ["unsigned ", "logic", "unsigned_logic"], ["unsigned ", "reg", "unsigned_reg"], ["unsigned ", "integer", "unsigned_integer"], ["unsigned ", "time", "unsigned_time"] ] } ================================================ FILE: conf/generators/templates/keywords.json ================================================ { "name": "keywords", "filename": "5.6.2--keyword_{0}.sv", "template": [ "/*", ":name: keyword_{0}", ":description: The '{0}' keyword should be reserved", ":should_fail_because: The '{0}' keyword should be reserved", ":tags: 5.6.2", "*/", "module top();", " bit {0};", "endmodule" ], "values": [ ["accept_on"], ["alias"], ["always"], ["always_comb"], ["always_ff"], ["always_latch"], ["and"], ["assert"], ["assign"], ["assume"], ["automatic"], ["before"], ["begin"], ["bind"], ["bins"], ["binsof"], ["bit"], ["break"], ["buf"], ["bufif0"], ["bufif1"], ["byte"], ["case"], ["casex"], ["casez"], ["cell"], ["chandle"], ["checker"], ["class"], ["clocking"], ["cmos"], ["config"], ["const"], ["constraint"], ["context"], ["continue"], ["cover"], ["covergroup"], ["coverpoint"], ["cross"], ["deassign"], ["default"], ["defparam"], ["design"], ["disable"], ["dist"], ["do"], ["edge"], ["else"], ["end"], ["endcase"], ["endchecker"], ["endclass"], ["endclocking"], ["endconfig"], ["endfunction"], ["endgenerate"], ["endgroup"], ["endinterface"], ["endmodule"], ["endpackage"], ["endprimitive"], ["endprogram"], ["endproperty"], ["endspecify"], ["endsequence"], ["endtable"], ["endtask"], ["enum"], ["event"], ["eventually"], ["expect"], ["export"], ["extends"], ["extern"], ["final"], ["first_match"], ["for"], ["force"], ["foreach"], ["forever"], ["fork"], ["forkjoin"], ["function"], ["generate"], ["genvar"], ["global"], ["highz0"], ["highz1"], ["if"], ["iff"], ["ifnone"], ["ignore_bins"], ["illegal_bins"], ["implements"], ["implies"], ["import"], ["incdir"], ["include"], ["initial"], ["inout"], ["input"], ["inside"], ["instance"], ["int"], ["integer"], ["interconnect"], ["interface"], ["intersect"], ["join"], ["join_any"], ["join_none"], ["large"], ["let"], ["liblist"], ["library"], ["local"], ["localparam"], ["logic"], ["longint"], ["macromodule"], ["matches"], ["medium"], ["modport"], ["module"], ["nand"], ["negedge"], ["nettype"], ["new"], ["nexttime"], ["nmos"], ["nor"], ["noshowcancelled"], ["not"], ["notif0"], ["notif1"], ["null"], ["or"], ["output"], ["package"], ["packed"], ["parameter"], ["pmos"], ["posedge"], ["primitive"], ["priority"], ["program"], ["property"], ["protected"], ["pull0"], ["pull1"], ["pulldown"], ["pullup"], ["pulsestyle_ondetect"], ["pulsestyle_onevent"], ["pure"], ["rand"], ["randc"], ["randcase"], ["randsequence"], ["rcmos"], ["real"], ["realtime"], ["ref"], ["reg"], ["reject_on"], ["release"], ["repeat"], ["restrict"], ["return"], ["rnmos"], ["rpmos"], ["rtran"], ["rtranif0"], ["rtranif1"], ["s_always"], ["s_eventually"], ["s_nexttime"], ["s_until"], ["s_until_with"], ["scalared"], ["sequence"], ["shortint"], ["shortreal"], ["showcancelled"], ["signed"], ["small"], ["soft"], ["solve"], ["specify"], ["specparam"], ["static"], ["string"], ["strong"], ["strong0"], ["strong1"], ["struct"], ["super"], ["supply0"], ["supply1"], ["sync_accept_on"], ["sync_reject_on"], ["table"], ["tagged"], ["task"], ["this"], ["throughout"], ["time"], ["timeprecision"], ["timeunit"], ["tran"], ["tranif0"], ["tranif1"], ["tri"], ["tri0"], ["tri1"], ["triand"], ["trior"], ["trireg"], ["type"], ["typedef"], ["union"], ["unique"], ["unique0"], ["unsigned"], ["until"], ["until_with"], ["untyped"], ["use"], ["uwire"], ["var"], ["vectored"], ["virtual"], ["void"], ["wait"], ["wait_order"], ["wand"], ["weak"], ["weak0"], ["weak1"], ["while"], ["wildcard"], ["wire"], ["with"], ["within"], ["wor"], ["xnor"], ["xor"] ] } ================================================ FILE: conf/generators/templates/logical-equiv.json ================================================ { "name": "logical_equivalence_operator_sim", "filename": "11.4.7--logical_equiv_operator_{2}.sv", "template": [ "/*", ":name: logical_equiv_operator_sim_{2}", ":description: logical equivalence operator test in simulation", ":type: simulation elaboration parsing", ":tags: 11.4.7", "*/", "module top();", "wire a;", "wire b;", "wire c;", "assign a = {0};", "assign b = {1};", "assign c = a <-> b;", "final begin", " $display(\":assert: ((%s) == %d)\", \"(((not {0}) or {1}) and ((not {1}) or {0}))\", c);", "end", "endmodule" ], "values": [ ["0", "0"], ["0", "1"], ["1", "0"], ["1", "1"] ] } ================================================ FILE: conf/generators/templates/logical-impl.json ================================================ { "name": "logical_implication_operator_sim", "filename": "11.4.7--logical_impl_operator_{2}.sv", "template": [ "/*", ":name: logical_impl_operator_sim_{2}", ":description: logical implication operator test in simulation", ":type: simulation elaboration parsing", ":tags: 11.4.7", "*/", "module top();", "wire a;", "wire b;", "wire c;", "assign a = {0};", "assign b = {1};", "assign c = a -> b;", "final begin", " $display(\":assert: ((%s) == %d)\", \"((not {0}) or {1})\", c);", "end", "endmodule" ], "values": [ ["0", "0"], ["0", "1"], ["1", "0"], ["1", "1"] ] } ================================================ FILE: conf/generators/templates/logical.json ================================================ { "name": "logical_operators_sim", "filename": "11.4.7--logical_operator_{4}.sv", "template": [ "/*", ":name: logical_operator_sim_{4}", ":description: logical operator test in simulation", ":type: simulation elaboration parsing", ":tags: 11.4.7", "*/", "module top();", "wire a;", "wire b;", "wire c;", "assign a = {0};", "assign b = {1};", "assign c = a {2} b;", "final begin", " $display(\":assert: ((%s) == %d)\", \"{0} {3} {1}\", c);", "end", "endmodule" ], "cartesian_product": "true", "values": [[ ["0", "0"], ["0", "1"], ["1", "0"], ["1", "1"] ], [ ["&&", "and"], ["||", "or"] ]] } ================================================ FILE: conf/generators/templates/nets.json ================================================ { "name": "nets", "filename": "{1}--net_{0}.sv", "template": [ "/*", ":name: net_{0}", ":description: {0} net test", ":tags: {1}", "*/", "module top();", "{0} v;", "endmodule" ], "values": [ ["wire", "6.6.1"], ["tri", "6.6.1"], ["uwire", "6.6.2"], ["wor", "6.6.3"], ["wand", "6.6.3"], ["trior", "6.6.3"], ["triand", "6.6.3"], ["trireg", "6.6.4"], ["tri0", "6.6.5"], ["tri1", "6.6.5"], ["supply0", "6.6.6"], ["supply1", "6.6.6"] ] } ================================================ FILE: conf/generators/templates/operators-sim.json ================================================ { "name": "operators_sim", "filename": "{2}--{1}_operator_sim_{5}.sv", "template": [ "/*", ":name: {1}_operator_sim_{5}", ":description: {0} operator test in simulation", ":type: simulation elaboration parsing", ":tags: {2}", "*/", "module top();", "wire [31:0] a;", "wire [31:0] b;", "wire [31:0] c;", "assign a = 32'd{3};", "assign b = 32'd{4};", "assign c = a {0} b;", "final begin", " $display(\":assert: (int(%s) == %d)\", \"{3}{0}{4}\", c);", "end", "endmodule" ], "cartesian_product": "true", "values": [[ ["+", "plus", "11.4.3"], ["-", "minus", "11.4.3"], ["*", "mul", "11.4.3"], ["/", "div", "11.4.3"], ["%", "mod", "11.4.3"], ["**", "exp", "11.4.3"], ["==", "log_eq", "11.4.5"], ["!=", "log_neq", "11.4.5"], ["<", "lt", "11.4.4"], ["<=", "le", "11.4.4"], [">", "gt", "11.4.4"], [">=", "ge", "11.4.4"], ["&", "bit_and", "11.4.8"], ["|", "bit_or", "11.4.8"], ["^", "bit_xor", "11.4.8"], ["<<", "log_shl", "11.4.10"], [">>", "log_shr", "11.4.10"] ], [ ["4", "3", "0"], ["4", "4", "1"] ]] } ================================================ FILE: conf/generators/templates/sampled-functions-gclk.json ================================================ { "name": "sampled_functions", "filename": "20.13--{0}.sv", "template": [ "/*", ":name: {0}_function", ":description: ${0} test", ":tags: {1}", ":type: simulation elaboration parsing", "*/", "module top();", "logic a, clk;", "global clocking @(posedge clk); endclocking", "assert property (@(posedge clk) ${0}(a)) else $info;", "endmodule" ], "values": [ ["past_gclk", "20.13 16.9"], ["rose_gclk", "20.13 16.9"], ["fell_gclk", "20.13 16.9"], ["stable_gclk", "20.13 16.9"], ["changed_gclk", "20.13 16.9"], ["future_gclk", "20.13 16.9"], ["rising_gclk", "20.13 16.9"], ["falling_gclk", "20.13 16.9"], ["steady_gclk", "20.13 16.9"], ["changing_gclk", "20.13 16.9"] ] } ================================================ FILE: conf/generators/templates/sampled-functions.json ================================================ { "name": "sampled_functions", "filename": "20.13--{0}.sv", "template": [ "/*", ":name: {0}_function", ":description: ${0} test", ":tags: {1}", ":type: simulation elaboration parsing", "*/", "module top();", "logic a, clk;", "assert property (@(posedge clk) ${0}(a)) else $info;", "endmodule" ], "values": [ ["sampled", "20.13 16.9"], ["rose", "20.13 16.9"], ["fell", "20.13 16.9"], ["stable", "20.13 16.9"], ["changed", "20.13 16.9"], ["past", "20.13 16.9"] ] } ================================================ FILE: conf/generators/templates/simple-logical.json ================================================ { "name": "simple_logical_operators_sim", "filename": "11.4.7--simple_{1}_logical_operator.sv", "template": [ "/*", ":name: simple_{1}_logical_operator_sim", ":description: minimal {0} operator simulation test (without result verification)", ":type: simulation elaboration parsing", ":tags: 11.4.7", "*/", "module top(input a, input b, output c);", " assign c = a {0} b;", "endmodule" ], "values": [ ["&&", "and"], ["||", "or"], ["<->", "equiv"], ["->", "impl"] ] } ================================================ FILE: conf/generators/templates/simple-operators-sim.json ================================================ { "name": "operators_sim", "filename": "{2}--simple_{1}_operator_sim.sv", "template": [ "/*", ":name: simple_{1}_operator_sim", ":description: minimal {0} operator simulation test (without result verification)", ":type: simulation elaboration parsing", ":tags: {2}", "*/", "module top(input [3:0] a, input [3:0] b, output [3:0] c);", " assign c = a {0} b;", "endmodule" ], "values": [ ["+", "plus", "11.4.3"], ["-", "minus", "11.4.3"], ["*", "mul", "11.4.3"], ["/", "div", "11.4.3"], ["%", "mod", "11.4.3"], ["**", "exp", "11.4.3"], ["==", "eq", "11.4.5"], ["!=", "neq", "11.4.5"], ["===", "eq_xz", "11.4.5"], ["!==", "neq_xz", "11.4.5"], ["<", "lt", "11.4.4"], ["<=", "le", "11.4.4"], [">", "gt", "11.4.4"], [">=", "ge", "11.4.4"], ["&", "bit_and", "11.4.8"], ["|", "bit_or", "11.4.8"], ["^", "bit_xor", "11.4.8"], ["<<", "log_shl", "11.4.10"], [">>", "log_shr", "11.4.10"] ] } ================================================ FILE: conf/generators/templates/simple-unary.json ================================================ { "name": "unary_op", "filename": "{2}--simple_unary_op_{1}.sv", "template": [ "/*", ":name: simple_unary_op_{1}", ":description: minimal {0} operator simulation test (without result verification)", ":tags: {2}", "*/", "module top(input [3:0] a, output [3:0] b);", " assign b = {0}a;", "endmodule" ], "values": [ ["+", "plus", "11.3"], ["-", "minus", "11.3"], ["!", "not_log", "11.3"], ["~", "not_bit", "11.4.8"], ["&", "and", "11.4.9"], ["~&", "nand", "11.4.9"], ["|", "or", "11.4.9"], ["~|", "nor", "11.4.9"], ["^", "xor", "11.4.9"], ["~^", "xnor_1", "11.4.9"], ["^~", "xnor_2", "11.4.9"] ] } ================================================ FILE: conf/generators/templates/trig-functions.json ================================================ { "name": "trig_functions", "filename": "20.8--{0}.sv", "template": [ "/*", ":name: {0}_function", ":description: ${0} test", ":tags: 20.8", ":type: simulation elaboration parsing", "*/", "module top();", "initial", "$display(\"%f\", ${0}(4));", "endmodule" ], "values": [ ["sin"], ["cos"], ["tan"], ["asin"], ["acos"], ["atan"], ["sinh"], ["cosh"], ["tanh"], ["asinh"], ["acosh"], ["atanh"] ] } ================================================ FILE: conf/generators/templates/unary.json ================================================ { "name": "unary_op", "filename": "{2}--unary_op_{1}.sv", "template": [ "/*", ":name: unary_op_{1}", ":description: {0} operator test", ":tags: {2}", "*/", "module top();", "int a = 12;", "int b = 5;", "initial begin", " a = {0}b;", "end", "endmodule" ], "values": [ ["+", "plus", "11.3"], ["-", "minus", "11.3"], ["!", "not_log", "11.3"], ["~", "not_bit", "11.4.8"], ["&", "and", "11.4.9"], ["~&", "nand", "11.4.9"], ["|", "or", "11.4.9"], ["~|", "nor", "11.4.9"], ["^", "xor", "11.4.9"], ["~^", "xnor_1", "11.4.9"], ["^~", "xnor_2", "11.4.9"] ] } ================================================ FILE: conf/generators/templates/uniquecase.json ================================================ { "name": "uniquecase", "filename": "12.5.3--{2}.sv", "template": [ "/*", ":name: {1}_{0}", ":description: {0} statement with {1}", ":tags: 12.5.3", "*/", "module top();", "wire [3:0] a = 3;", "reg [3:0] b = 0;", "initial begin", " {1} {0} (a)", " 0, 1: b = 1;", " 2: b = 2;", " 3: b = 3;", " endcase", "end", "endmodule" ], "values": [ ["case", "unique", "unique_case"], ["case", "unique0", "unique0_case"], ["case", "priority", "priority_case"], ["casez", "unique", "unique_casez"], ["casez", "unique0", "unique0_casez"], ["casez", "priority", "priority_casez"], ["casex", "unique", "unique_casex"], ["casex", "unique0", "unique0_casex"], ["casex", "priority", "priority_casex"] ] } ================================================ FILE: conf/generators/templates/uvm-classes_0.json ================================================ { "name": "uvm_classes_0", "filename": "{0}_class_0.sv", "template_file": "uvm-classes_0.sv", "values": [ ["uvm_agent"], ["uvm_component"], ["uvm_driver"], ["uvm_env"], ["uvm_monitor"], ["uvm_sequencer"], ["uvm_scoreboard"], ["uvm_test"] ] } ================================================ FILE: conf/generators/templates/uvm-classes_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: {0}_0 :description: {0} class test :tags: uvm uvm-classes :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class C extends {0}; function new(string name, uvm_component parent = null); super.new(name, parent); `uvm_info("RESULT", "new {0} created", UVM_LOW); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); `uvm_info("RESULT", "build phase completed", UVM_LOW); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); `uvm_info("RESULT", "connect phase completed", UVM_LOW); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); `uvm_info("RESULT", "end of elaboration phase completed", UVM_LOW); endfunction virtual function void start_of_simulation_phase(uvm_phase phase); super.start_of_simulation_phase(phase); `uvm_info("RESULT", "start of simulation phase completed", UVM_LOW); endfunction task run_phase(uvm_phase phase); `uvm_info("RESULT", "run phase phase completed", UVM_LOW); endtask virtual function void extract_phase(uvm_phase phase); super.extract_phase(phase); `uvm_info("RESULT", "extract phase completed", UVM_LOW); endfunction virtual function void check_phase(uvm_phase phase); super.check_phase(phase); `uvm_info("RESULT", "check phase completed", UVM_LOW); endfunction virtual function void report_phase(uvm_phase phase); super.report_phase(phase); `uvm_info("RESULT", "report phase completed", UVM_LOW); endfunction endclass module top; C obj; initial begin obj = new("C"); run_test(); end endmodule ================================================ FILE: conf/generators/templates/uvm-classes_1.json ================================================ { "name": "uvm_classes_1", "filename": "{0}_class_1.sv", "template_file": "uvm-classes_1.sv", "values": [ ["uvm_agent"], ["uvm_component"], ["uvm_driver"], ["uvm_env"], ["uvm_monitor"], ["uvm_sequencer"], ["uvm_scoreboard"], ["uvm_test"] ] } ================================================ FILE: conf/generators/templates/uvm-classes_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: {0}_1 :description: {0} class test :tags: uvm uvm-classes :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" `define PATTERN 2 interface input_if(input clk); logic [7:0] data; modport port(input clk, data); endinterface interface output_if(input clk); logic [7:0] data; modport port(input clk, output data); endinterface module dut(input_if.port in, output_if.port out); always @(posedge in.clk) out.data <= in.data; endmodule class C extends {0}; virtual output_if out_vif; virtual input_if in_vif; `uvm_component_utils(C) function new(string name, uvm_component parent = null); super.new(name, parent); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( "C", "input_if", in_vif)); assert(uvm_resource_db#(virtual output_if)::read_by_name( "C", "output_if", out_vif)); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info("RESULT", $sformatf("Writing %0d to input interface", `PATTERN), UVM_LOW); in_vif.data <= `PATTERN; repeat(2) @(posedge out_vif.clk); if(out_vif.data == `PATTERN) begin `uvm_info("RESULT", $sformatf("Match %d == %d", out_vif.data, `PATTERN), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("Mismatch %d != %d", out_vif.data, `PATTERN)); end phase.drop_objection(this); endtask endclass module top; logic clk; C obj; input_if in(clk); output_if out(clk); dut d(in, out); always #5 clk = !clk; initial begin obj = new("C"); uvm_resource_db#(virtual input_if)::set("C","input_if", in); uvm_resource_db#(virtual output_if)::set("C", "output_if", out); clk = 0; run_test(); end endmodule ================================================ FILE: conf/generators/templates/uvm-classes_2.json ================================================ { "name": "uvm_classes_2", "filename": "{0}_class_2.sv", "template": [ "/*", ":name: {0}_2", ":description: {0} class test", ":tags: uvm uvm-classes", ":type: parsing", ":timeout: 300", "*/", "import uvm_pkg::*;", "`include \"uvm_macros.svh\"\n", "class C extends {0}(\"\", null);", "endclass" ], "values": [ ["uvm_agent"], ["uvm_component"], ["uvm_driver"], ["uvm_env"], ["uvm_monitor"], ["uvm_sequencer"], ["uvm_scoreboard"], ["uvm_test"] ] } ================================================ FILE: conf/generators/templates/uvm-classes_3.json ================================================ { "name": "uvm_classes_3", "filename": "{0}_class_3.sv", "template_file": "uvm-classes_3.sv", "values": [ ["uvm_agent"], ["uvm_component"], ["uvm_driver"], ["uvm_env"], ["uvm_monitor"], ["uvm_sequencer"], ["uvm_scoreboard"], ["uvm_test"] ] } ================================================ FILE: conf/generators/templates/uvm-classes_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: {0}_3 :description: {0} class test :tags: uvm uvm-classes :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class C extends {0}; `uvm_component_utils(C) function new(string name, uvm_component parent = null); super.new(name, parent); `uvm_info("RESULT", "Created new {0}", UVM_LOW); endfunction endclass module top; C obj; initial begin obj = new("C"); end endmodule ================================================ FILE: conf/generators/templates/wildcard-const.json ================================================ { "name": "wildcard_const_operators_sim", "filename": "11.4.6--wildcard_const_operator_{4}.sv", "template": [ "/*", ":name: wildcard_const_operator_sim_{4}", ":description: wildcard operator with constant test in simulation", ":type: simulation elaboration parsing", ":tags: 11.4.6", "*/", "module top();", "logic [3:0] a = {0};", "logic c;", "initial begin", " c = a {2} {1};", " $display(\":assert: ('%s' == '%d')\", \"{3}\", c);", "end", "endmodule" ], "values": [ ["4'b1001", "4'bx001", "==?" , "1"], ["4'b1001", "4'bz001", "==?" , "1"], ["4'bx001", "4'b1001", "==?" , "x"], ["4'bz001", "4'b1001", "==?" , "x"], ["4'bz001", "4'bx001", "==?" , "1"], ["4'b1001", "4'bx001", "!=?" , "0"], ["4'bz001", "4'bx001", "!=?" , "0"], ["4'bz001", "4'b1001", "!=?" , "x"] ] } ================================================ FILE: conf/generators/templates/wildcard.json ================================================ { "name": "wildcard_operators_sim", "filename": "11.4.6--wildcard_operator_{4}.sv", "template": [ "/*", ":name: wildcard_operator_sim_{4}", ":description: wildcard operator test in simulation", ":type: simulation elaboration parsing", ":tags: 11.4.6", "*/", "module top();", "logic [3:0] a = {0};", "logic [3:0] b = {1};", "logic c;", "initial begin", " c = a {2} b;", " $display(\":assert: ('%s' == '%d')\", \"{3}\", c);", "end", "endmodule" ], "values": [ ["4'b1001", "4'bx001", "==?" , "1"], ["4'b1001", "4'bz001", "==?" , "1"], ["4'bx001", "4'b1001", "==?" , "x"], ["4'bz001", "4'b1001", "==?" , "x"], ["4'bz001", "4'bx001", "==?" , "1"], ["4'b1001", "4'bx001", "!=?" , "0"], ["4'bz001", "4'bx001", "!=?" , "0"], ["4'bz001", "4'b1001", "!=?" , "x"] ] } ================================================ FILE: conf/lrm.conf ================================================ # vim: noet tabstop=64 # # input database for the report generator # syntax: # [] # sanity Various sanity checks veer-eh1 VeeR EH1 RISC-V core https://github.com/chipsalliance/Cores-VeeR-EH1 veer-el2 VeeR EL2 RISC-V core https://github.com/chipsalliance/Cores-VeeR-EL2 ibex Ibex RISC-V core https://github.com/lowRISC/ibex fx68k FX68K m68k core https://github.com/ijor/fx68k yosys Tests imported from Yosys https://github.com/YosysHQ/yosys/tree/master/tests/hana hdlconv Tests imported from hdlConvertor https://github.com/Nic30/hdlConvertor/tree/master/tests hdlconv_std2012 Tests imported from hdlConvertor (std2012) https://github.com/Nic30/hdlConvertor/tree/master/tests hdlconv_std2017 Tests imported from hdlConvertor (std2017) https://github.com/Nic30/hdlConvertor/tree/master/tests utd-sv Tests imported from utd-SystemVerilog https://github.com/SymbiFlow/utd-sv uvm Tests imported from UVM https://github.com/SymbiFlow/uvm uvm-req UVM Prerequisites uvm-assertions UVM tests using assertions uvm-scoreboards uvm_scoreboard examples uvm-agents uvm_agent examples uvm-classes Particular UVM classes basejump Tests imported from Basejump STL https://github.com/bespoke-silicon-group/basejump_stl ariane Ariane RISC-V core https://github.com/openhwgroup/cva6 scr1 SCR1 RISC-V core https://github.com/syntacore/scr1 taiga Taiga RISC-V core https://gitlab.com/sfu-rcl/Taiga black-parrot BlackParrot RISC-V core https://github.com/black-parrot/black-parrot rsd RSD RISC-V core https://github.com/rsd-devel/rsd ivtest Tests imported from ivtest https://github.com/steveicarus/iverilog/tree/master/ivtest RgGen RgGen code generator for configuration and status registers https://github.com/rggen/rggen TNoC NoC router and fabric https://github.com/taichi-ishitani/tnoc 5 Lexical conventions 5.1 General 5.2 Lexical tokens 5.3 White space 5.4 Comments 5.5 Operators 5.6 Identifiers, keywords, and system names 5.6.1 Escaped identifiers 5.6.2 Keywords 5.6.3 System tasks and system functions 5.6.4 Compiler directives 5.7 Numbers 5.7.1 Integer literal constants 5.7.2 Real literal constants 5.8 Time literals 5.9 String literals 5.9.1 Special characters in strings 5.10 Structure literals 5.11 Array literals 5.12 Attributes 5.13 Built-in methods 6 Data types 6.1 General 6.2 Data types and data objects 6.3 Value set 6.3.1 Logic values 6.3.2 Strengths 6.3.2.1 Charge strength 6.3.2.2 Drive strength 6.4 Singular and aggregate types 6.5 Nets and variables 6.6 Net types 6.6.1 Wire and tri nets 6.6.2 Unresolved nets 6.6.3 Wired nets 6.6.4 Trireg net 6.6.4.1 Capacitive networks 6.6.4.2 Ideal capacitive state and charge decay 6.6.5 Tri0 and tri1 nets 6.6.6 Supply nets 6.6.7 User-defined nettypes 6.6.8 Generic interconnect 6.7 Net declarations 6.7.1 Net declarations with built-in net types 6.7.2 Net declarations with user-defined nettypes 6.7.3 Initialization of nets with user-defined nettypes 6.8 Variable declarations 6.9 Vector declarations 6.9.1 Specifying vectors 6.9.2 Vector net accessibility 6.10 Implicit declarations 6.11 Integer data types 6.11.1 Integral types 6.11.2 2-state (two-value) and 4-state (four-value) data types 6.11.3 Signed and unsigned integer types 6.12 Real, shortreal, and realtime data types 6.12.1 Operators and real numbers 6.12.2 Conversion 6.13 Void data type 6.14 Chandle data type 6.15 Class 6.16 String data type 6.16.1 Len() 6.16.2 Putc() 6.16.3 Getc() 6.16.4 Toupper() 6.16.5 Tolower() 6.16.6 Compare() 6.16.7 Icompare() 6.16.8 Substr() 6.16.9 Atoi(), atohex(), atooct(), atobin() 6.16.10 Atoreal() 6.16.11 Itoa() 6.16.12 Hextoa() 6.16.13 Octtoa() 6.16.14 Bintoa() 6.16.15 Realtoa() 6.17 Event data type 6.18 User-defined types 6.19 Enumerations 6.19.1 Defining new data types as enumerated types 6.19.2 Enumerated type ranges 6.19.3 Type checking 6.19.4 Enumerated types in numerical expressions 6.19.5 Enumerated type methods 6.19.5.1 First() 6.19.5.2 Last() 6.19.5.3 Next() 6.19.5.4 Prev() 6.19.5.5 Num() 6.19.5.6 Name() 6.19.5.7 Using enumerated type methods 6.20 Constants 6.20.1 Parameter declaration syntax 6.20.2 Value parameters 6.20.2.1 $ as a parameter value 6.20.3 Type parameters 6.20.4 Local parameters (localparam) 6.20.5 Specify parameters 6.20.6 Const constants 6.21 Scope and lifetime 6.22 Type compatibility 6.22.1 Matching types 6.22.2 Equivalent types 6.22.3 Assignment compatible 6.22.4 Cast compatible 6.22.5 Type incompatible 6.22.6 Matching nettypes 6.23 Type operator 6.24 Casting 6.24.1 Cast operator 6.24.2 $cast dynamic casting 6.24.3 Bit-stream casting 6.25 Parameterized data types 7 Aggregate data types 7.1 General 7.2 Structures 7.2.1 Packed structures 7.2.2 Assigning to structures 7.3 Unions 7.3.1 Packed unions 7.3.2 Tagged unions 7.4 Packed and unpacked arrays 7.4.1 Packed arrays 7.4.2 Unpacked arrays 7.4.3 Operations on arrays 7.4.4 Memories 7.4.5 Multidimensional arrays 7.4.6 Indexing and slicing of arrays 7.5 Dynamic arrays 7.5.1 New[ ] 7.5.2 Size() 7.5.3 Delete() 7.6 Array assignments 7.7 Arrays as arguments to subroutines 7.8 Associative arrays 7.8.1 Wildcard index type 7.8.2 String index 7.8.3 Class index 7.8.4 Integral index 7.8.5 Other user-defined types 7.8.6 Accessing invalid indices 7.8.7 Allocating associative array elements 7.9 Associative array methods 7.9.1 Num() and size() 7.9.2 Delete() 7.9.3 Exists() 7.9.4 First() 7.9.5 Last() 7.9.6 Next() 7.9.7 Prev() 7.9.8 Arguments to traversal methods 7.9.9 Associative array assignment 7.9.10 Associative array arguments 7.9.11 Associative array literals 7.10 Queues 7.10.1 Queue operators 7.10.2 Queue methods 7.10.2.1 Size() 7.10.2.2 Insert() 7.10.2.3 Delete() 7.10.2.4 Pop_front() 7.10.2.5 Pop_back() 7.10.2.6 Push_front() 7.10.2.7 Push_back() 7.10.3 Persistence of references to elements of a queue 7.10.4 Updating a queue using assignment and unpacked array concatenation 7.10.5 Bounded queues 7.11 Array querying functions 7.12 Array manipulation methods 7.12.1 Array locator methods 7.12.2 Array ordering methods 7.12.3 Array reduction methods 7.12.4 Iterator index querying 8 Classes 8.1 General 8.2 Overview 8.3 Syntax 8.4 Objects (class instance) 8.5 Object properties and object parameter data 8.6 Object methods 8.7 Constructors 8.8 Typed constructor calls 8.9 Static class properties 8.10 Static methods 8.11 This 8.12 Assignment, renaming, and copying 8.13 Inheritance and subclasses 8.14 Overridden members 8.15 Super 8.16 Casting 8.17 Chaining constructors 8.18 Data hiding and encapsulation 8.19 Constant class properties 8.20 Virtual methods 8.21 Abstract classes and pure virtual methods 8.22 Polymorphism: dynamic method lookup 8.23 Class scope resolution operator :: 8.24 Out-of-block declarations 8.25 Parameterized classes 8.25.1 Class scope resolution operator for parameterized classes 8.26 Interface classes 8.26.1 Interface class syntax 8.26.2 Extends versus implements 8.26.3 Type access 8.26.4 Type usage restrictions 8.26.5 Casting and object reference assignment 8.26.6 Name conflicts and resolution 8.26.6.1 Method name conflict resolution 8.26.6.2 Parameter and type declaration inheritance conflicts and resolution 8.26.6.3 Diamond relationship 8.26.7 Partial implementation 8.26.8 Method default argument values 8.26.9 Constraint blocks, covergroups, and randomization 8.27 Typedef class 8.28 Classes and structures 8.29 Memory management 9 Processes 9.1 General 9.2 Structured procedures 9.2.1 Initial procedures 9.2.2 Always procedures 9.2.2.1 General purpose always procedure 9.2.2.2 Combinational logic always_comb procedure 9.2.2.2.1 Implicit always_comb sensitivities 9.2.2.2.2 always_comb compared to always @* 9.2.2.3 Latched logic always_latch procedure 9.2.2.4 Sequential logic always_ff procedure 9.2.3 Final procedures 9.3 Block statements 9.3.1 Sequential blocks 9.3.2 Parallel blocks 9.3.3 Statement block start and finish times 9.3.4 Block names 9.3.5 Statement labels 9.4 Procedural timing controls 9.4.1 Delay control 9.4.2 Event control 9.4.2.1 Event OR operator 9.4.2.2 Implicit event_expression list 9.4.2.3 Conditional event controls 9.4.2.4 Sequence events 9.4.3 Level-sensitive event control 9.4.4 Level-sensitive sequence controls 9.4.5 Intra-assignment timing controls 9.5 Process execution threads 9.6 Process control 9.6.1 Wait fork statement 9.6.2 Disable statement 9.6.3 Disable fork statement 9.7 Fine-grain process control 10.3 Continuous assignments 10.3.1 The net declaration assignment 10.3.2 The continuous assignment statement 10.3.3 Continuous assignment delays 10.3.4 Continuous assignment strengths 10.4.1 Blocking procedural assignments 10.4.2 Nonblocking procedural assignments 10.6.1 The assign and deassign procedural statements 10.6.2 The force and release procedural statements 11 Operators and expressions 11.1 General 11.2 Overview 11.2.1 Constant expressions 11.2.2 Aggregate expressions 11.3 Operators 11.3.1 Operators with real operands 11.3.2 Operator precedence 11.3.3 Using integer literals in expressions 11.3.4 Operations on logic (4-state) and bit (2-state) types 11.3.5 Operator expression short circuiting 11.3.6 Assignment within an expression 11.4 Operator descriptions 11.4.1 Assignment operators 11.4.2 Increment and decrement operators 11.4.3 Arithmetic operators 11.4.3.1 Arithmetic expressions with unsigned and signed types 11.4.4 Relational operators 11.4.5 Equality operators 11.4.6 Wildcard equality operators 11.4.7 Logical operators 11.4.8 Bitwise operators 11.4.9 Reduction operators 11.4.10 Shift operators 11.4.11 Conditional operator 11.4.12 Concatenation operators 11.4.12.1 Replication operator 11.4.12.2 String concatenation 11.4.13 Set membership operator 11.4.14 Streaming operators (pack/unpack) 11.4.14.1 Concatenation of stream_expressions 11.4.14.2 Re-ordering of the generic stream 11.4.14.3 Streaming concatenation as an assignment target (unpack) 11.4.14.4 Streaming dynamically sized data 11.5 Operands 11.5.1 Vector bit-select and part-select addressing 11.5.2 Array and memory addressing 11.5.3 Longest static prefix 11.6 Expression bit lengths 11.6.1 Rules for expression bit lengths 11.6.2 Example of expression bit-length problem 11.6.3 Example of self-determined expressions 11.7 Signed expressions 11.8 Expression evaluation rules 11.8.1 Rules for expression types 11.8.2 Steps for evaluating an expression 11.8.3 Steps for evaluating an assignment 11.8.4 Handling X and Z in signed expressions 11.9 Tagged union expressions and member access 11.10 String literal expressions 11.10.1 String literal operations 11.10.2 String literal value padding and potential problems 11.10.3 Empty string literal handling 11.11 Minimum, typical, and maximum delay expressions 11.12 Let construct 12 Procedural programming statements 12.1 General 12.2 Overview 12.3 Syntax 12.4 Conditional if-else statement 12.4.1 if-else-if construct 12.4.2 unique-if, unique0-if, and priority-if 12.4.2.1 Violation reports generated by unique-if, unique0-if, and priority-if constructs 12.4.2.2 If statement violation reports and multiple processes 12.5 Case statement 12.5.1 Case statement with do-not-cares 12.5.2 Constant expression in case statement 12.5.3 unique-case, unique0-case, and priority-case 12.5.3.1 Violation reports generated by unique-case, unique0-case, and priority-case constructs 12.5.3.2 Case statement violation reports and multiple processes 12.5.4 Set membership case statement 12.6 Pattern matching conditional statements 12.6.1 Pattern matching in case statements 12.6.2 Pattern matching in if statements 12.6.3 Pattern matching in conditional expressions 12.7 Loop statements 12.7.1 The for-loop 12.7.2 The repeat loop 12.7.3 The foreach-loop 12.7.4 The while-loop 12.7.5 The do...while-loop 12.7.6 The forever-loop 12.8 Jump statements 13.3 Tasks 13.3.1 Static and automatic tasks 13.4 Functions 13.4.1 Return values and void functions 13.4.2 Static and automatic functions 13.4.3 Constant functions 13.4.4 Background processes spawned by function calls 14.3 Clocking block declaration 15.4 Mailboxes 15.5 Named Events 16.2 Overview 16.4 Deferred assertions 16.7 Sequences 16.9 Sequence operations 16.10 Local variables 16.12 Declaring properties 16.14 Concurrent assertions 16.15 Disable iff resolution 16.17 Expect statement 18.4 Random variables 18.4.1 Rand modifier 18.4.2 Randc modifier 18.5 Constraint blocks 18.5.1 External constraint blocks 18.5.2 Constraint inheritance 18.5.3 Set membership 18.5.4 Distribution 18.5.5 Uniqueness constraints 18.5.6 Implication 18.5.7 if–else constraints 18.5.8 Iterative constraints 18.5.8.1 foreach iterative constraints 18.5.8.2 Array reduction iterative constraints 18.5.9 Global constraints 18.5.10 Variable ordering 18.5.11 Static constraint blocks 18.5.12 Functions in constraints 18.5.13 Constraint guards 18.5.14 Soft constraints 18.5.14.1 Soft constraint priorities 18.5.14.2 Discarding soft constraints 18.6 Randomization methods 18.6.1 Randomize() 18.6.2 Pre_randomize() and post_randomize() 18.6.3 Behavior of randomization methods 18.7 In-line constraints—randomize() with 18.7.1 local:: scope resolution 18.8 Disabling random variables with rand_mode() 18.9 Controlling constraints with constraint_mode() 18.10 Dynamic constraint modification 18.11 In-line random variable control 18.11.1 In-line constraint checker 18.12 Randomization of scope variables—std::randomize() 18.12.1 Adding constraints to scope variables—std::randomize() with 18.13 Random number system functions and methods 18.13.1 $urandom 18.13.2 $urandom_range() 18.13.3 srandom() 18.13.4 get_randstate() 18.13.5 set_randstate() 18.14 Random stability 18.14.1 Random stability properties 18.14.2 Thread stability 18.14.3 Object stability 18.15 Manually seeding randomize 18.16 Random weighted case—randcase 18.17 Random sequence generation—randsequence 18.17.1 Random production weights 18.17.2 if–else production statements 18.17.3 Case production statements 18.17.4 Repeat production statements 18.17.5 Interleaving productions—rand join 18.17.6 Aborting productions—break and return 18.17.7 Value passing between productions 20.2 Simulation control system tasks 20.3 Simulation time system functions 20.4 Timescale system tasks 20.5 Conversion functions 20.6 Data query functions 20.7 Array query functions 20.8 Math functions 20.9 Bit vector system functions 20.10 Severity tasks 20.11 Elaboration system tasks 20.13 Sampled value system functions 20.14 Coverage system functions 20.15 Probabilistic distribution functions 21.2 Display system tasks 21.3 File input/output system tasks and system functions 21.4 Loading memory array data from a file 21.6 Command line input 21.7 Value change dump (VCD) files 23.2 Module definitions 22 Compiler directives 22.1 General 22.2 Overview 22.3 resetall 22.4 include 22.5 define, undef and undefineall 22.5.1 define 22.5.2 undef 22.5.3 undefineall 22.6 ifdef, else, elsif, endif, ifndef 22.7 timescale 22.8 default_nettype 22.9 unconnected_drive and nounconnected_drive 22.10 celldefine and endcelldefine 22.11 pragma 22.12 line 22.13 __FILE__ and __LINE__ 24.3 The program construct 25.3 Interface syntax 26.2 Package declarations 26.3 Referencing data in packages ================================================ FILE: conf/meta-tags.conf ================================================ # vim: noet tabstop=16 # # meta-tags configuration file # syntax: # # uvm-req 5.4 5.5 5.6 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.2 6.23 6.24 6.3 6.6 6.9 7.1 7.11 7.2 7.5 8.1 8.11 8.13 8.15 8.16 8.2 8.21 8.23 8.26 8.3 8.7 9.2 9.3 9.4 9.6 9.7 10.11 10.3 10.4 10.6 11.12 11.3 12.4 12.5 12.6 12.7 12.8 13.3 13.4 14.11 15.3 15.4 15.5 16.12 16.17 16.2 16.8 16.9 17.2 20.15 20.2 20.3 20.4 20.5 20.6 20.7 20.9 21.2 21.3 21.6 22.13 22.4 22.5 22.6 22.7 23.2 24.3 25.3 26.2 26.3 ================================================ FILE: conf/report/code-template.html ================================================

{{filename|e}}

{{ code }} ================================================ FILE: conf/report/code.css ================================================ @import 'details-view.css'; :root { font-family: "Courier New", Consolas, monospace; } pre { margin: 0; padding: 4px; } .highlight .hll { background-color: #ffffcc } .highlight .c { color: #228B22 } /* Comment */ .highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */ .highlight .k { color: #8B008B; font-weight: bold } /* Keyword */ .highlight .cm { color: #228B22 } /* Comment.Multiline */ .highlight .cp { color: #1e889b } /* Comment.Preproc */ .highlight .c1 { color: #228B22 } /* Comment.Single */ .highlight .cs { color: #8B008B; font-weight: bold } /* Comment.Special */ .highlight .gd { color: #aa0000 } /* Generic.Deleted */ .highlight .ge { font-style: italic } /* Generic.Emph */ .highlight .gr { color: #aa0000 } /* Generic.Error */ .highlight .gh { color: #000080; font-weight: bold } /* Generic.Heading */ .highlight .gi { color: #00aa00 } /* Generic.Inserted */ .highlight .go { color: #888888 } /* Generic.Output */ .highlight .gp { color: #555555 } /* Generic.Prompt */ .highlight .gs { font-weight: bold } /* Generic.Strong */ .highlight .gu { color: #800080; font-weight: bold } /* Generic.Subheading */ .highlight .gt { color: #aa0000 } /* Generic.Traceback */ .highlight .kc { color: #8B008B; font-weight: bold } /* Keyword.Constant */ .highlight .kd { color: #8B008B; font-weight: bold } /* Keyword.Declaration */ .highlight .kn { color: #8B008B; font-weight: bold } /* Keyword.Namespace */ .highlight .kp { color: #8B008B; font-weight: bold } /* Keyword.Pseudo */ .highlight .kr { color: #8B008B; font-weight: bold } /* Keyword.Reserved */ .highlight .kt { color: #a7a7a7; font-weight: bold } /* Keyword.Type */ .highlight .m { color: #B452CD } /* Literal.Number */ .highlight .s { color: #CD5555 } /* Literal.String */ .highlight .na { color: #658b00 } /* Name.Attribute */ .highlight .nb { color: #658b00 } /* Name.Builtin */ .highlight .nc { color: #008b45; font-weight: bold } /* Name.Class */ .highlight .no { color: #00688B } /* Name.Constant */ .highlight .nd { color: #707a7c } /* Name.Decorator */ .highlight .ne { color: #008b45; font-weight: bold } /* Name.Exception */ .highlight .nf { color: #008b45 } /* Name.Function */ .highlight .nn { color: #008b45; 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} #header_code { position:sticky; left: 0; top: 0; width: calc(100vw - 13px); } .linenodiv a { color: #000000; text-decoration: none; } .linenodiv a:hover { text-decoration: underline; } ================================================ FILE: conf/report/details-view.css ================================================ :root { font-family: sans-serif; font-size: 0.8rem; } * { box-sizing: border-box; } body { margin: 0; padding: 0; width: 100%; min-width: min-content; } header { width: 100%; height: 50px; background-color: #666; color: #fff; font-family: sans-serif; line-height: 1.4rem; padding-left: 20px; margin: 0; display: flex; align-items: center; gap: 0; justify-content: stretch; justify-items: stretch; } h1 { font-size: 1em; margin: 0; padding: 4px; text-decoration: inherit; font-weight: bold; text-transform: uppercase; } h2 { font-size: inherit; margin: 0; padding: 4px; color: inherit; font-weight: normal; } header a { color: inherit; text-decoration: underline; text-underline-position: under; text-decoration-color: #fff4; } header a:hover { background-color: #0004; } pre, code { font-family: "Courier New", Consolas, monospace; } ================================================ FILE: conf/report/filter.js ================================================ // NOTE: Code here uses classes and functions from report.js const HEADER_COLUMNS_COUNT = 2 /// Filter state manager /////////////////////////////////////////////// const filter_state = new StateManager({ hidden_column_ids: { initial: [], validator: (v) => Array.isArray(v), }, row_filter_func: { initial: null, validator: (v) => (typeof v === "function" || v === null) }, cell_filter_func: { initial: null, validator: (v) => (typeof v === "function" || v === null) }, tool_filter: { initial: TOOL_NAMES.map((v) => v.toLowerCase()).sort(), validator: (v) => (Array.isArray(v) && v.every((v) => is_string(v))), }, applied_tool_filter: { initial: TOOL_NAMES.map((v) => v.toLowerCase()).sort(), validator: (v) => (Array.isArray(v) && v.every((v) => is_string(v))), }, coverage_filter: { initial: [">=", 0], validator: (v) => Array.isArray(v), }, applied_coverage_filter: { initial: [">=", 0], validator: (v) => Array.isArray(v), }, type_filter: { initial: ["elaboration", "parsing", "simulation"], validator: (v) => (Array.isArray(v) && v.every((v) => is_string(v))), }, applied_type_filter: { initial: ["elaboration", "parsing", "simulation"], validator: (v) => (Array.isArray(v) && v.every((v) => is_string(v))), }, }) /// EntriesListController ////////////////////////////////////////////// class CoverageFilterEntriesController { constructor(state_manager, element) { this._state = state_manager this._top = element this._first_entry = this._top.querySelector(".p_entry") this._first_operator = this._first_entry.querySelector(".p_entry-operator") this._first_value = this._first_entry.querySelector(".p_entry-value"); [this._first_operator, this._first_value].forEach((element) => { element.addEventListener("change", this._update_state.bind(this)) }) this._entry_template = this._top.querySelector(".p_entry-template") this._add_button = this._top.querySelector(".p_add-entry-button") this._add_button.onclick = this._add_entry_button_clicked.bind(this) this._state.subscribe( ["coverage_filter"], StateManager.debounce(this._state_changed.bind(this))) this._update_state_handle = null } static _select_option(select_element, option_value) { let i = 0 for (const child of select_element.options) { if (child.value === option_value) { select_element.selectedIndex = i return } ++i } select_element.selectedIndex = -1 } _state_changed(state, changed_values) { let entries = [...this._top.querySelectorAll(".p_entry.v_removable")] const values = state.coverage_filter const expected_removable_entries_count = (values.length - 2) / 3 if (entries.length > expected_removable_entries_count) { for (let i = expected_removable_entries_count; i < entries.length; ++i) { entries[i].remove() } entries.splice(expected_removable_entries_count) } else if (entries.length < expected_removable_entries_count) { let last_entry = entries.length > 0 ? entries[entries.lenght-1] : this._first_entry for (let i = entries.length; i < expected_removable_entries_count; ++i) { const new_entry = this._create_entry() last_entry.after(new_entry) entries.push(new_entry) last_entry = new_entry } } CoverageFilterEntriesController._select_option(this._first_operator, values[0]) this._first_value.value = values[1] let i = 2 for (const entry of entries) { CoverageFilterEntriesController._select_option(entry.querySelector(".p_entry-relation"), values[i+0]) CoverageFilterEntriesController._select_option(entry.querySelector(".p_entry-operator"), values[i+1]) entry.querySelector(".p_entry-value").value = values[i + 2] i += 3 } } _add_entry_button_clicked(event) { const entries = this._top.querySelectorAll(".p_entry") const last_entry = entries[entries.length - 1] const new_entry = this._create_entry() last_entry.after(new_entry) new_entry.querySelector("select, input, button").focus() this._update_state() } _update_state() { if (this._update_state_handle !== null) clearTimeout(this._update_state_handle) this._update_state_handle = setTimeout(() => { this._update_state_handle = null const entries = this._top.querySelectorAll(".p_entry.v_removable") const new_state = new Array(2 + 3 * (entries.length)) new_state[0] = this._first_operator.value if (this._first_value.validity.valid) new_state[1] = this._first_value.valueAsNumber|0 else new_state[1] = NaN let i = 2 for (const entry of entries) { new_state[i+0] = entry.querySelector(".p_entry-relation").value new_state[i+1] = entry.querySelector(".p_entry-operator").value const value_field = entry.querySelector(".p_entry-value") if (value_field.validity.valid) new_state[i + 2] = value_field.valueAsNumber|0 else new_state[i + 2] = NaN i += 3 } this._state.state.coverage_filter = new_state }, 100) } _create_entry() { const entry = this._entry_template.content.firstElementChild.cloneNode(true) entry.querySelectorAll("select, input").forEach((element) => { element.addEventListener("change", this._update_state.bind(this)) }) const remove_button = entry.querySelector(".p_remove-entry-button") remove_button.onclick = (event) => { entry.remove() this._update_state() } return entry } } /// CheckboxGroupController //////////////////////////////////////////// class CheckboxGroupController { constructor(state_manager, state_key, checkbox_list) { this._state = state_manager this._key = state_key this._checkboxes = new Map() this._selections = new Set(this._state.state[this._key]) for (const checkbox of checkbox_list) { this._checkboxes.set(checkbox.value, checkbox) checkbox.checked = this._selections.has(checkbox.value) checkbox.addEventListener("change", this._checkbox_changed.bind(this)) } this._state.subscribe( [state_key], StateManager.debounce(this._state_changed.bind(this))) this._update_state_handle = null } _state_changed(state, changed_values) { this._selections = new Set(state[this._key]) for (const [value, checkbox] of this._checkboxes) { checkbox.checked = this._selections.has(value) } } _checkbox_changed(event) { const checkbox = event.target if (checkbox.checked == this._selections.has(checkbox.value)) return if (checkbox.checked) { this._selections.add(checkbox.value) } else { this._selections.delete(checkbox.value) } if (this._update_state_handle === null) { this._update_state_handle = setTimeout(() => { this._update_state_handle = null this._state.state[this._key] = [...this._selections].sort() }, 0) } } } /// FilterController /////////////////////////////////////////////////// class FilterController { constructor(state_manager, elements) { this._state = state_manager this._apply_button = elements.apply_button this._reset_button = elements.reset_button this._error_label = elements.error_label this._apply_button.onclick = this._apply_clicked.bind(this) this._reset_button.onclick = this._reset_clicked.bind(this) this._state.subscribe( ["tool_filter", "coverage_filter", "type_filter", "applied_tool_filter", "applied_coverage_filter", "applied_type_filter"], StateManager.debounce(this._state_changed.bind(this))) } static _is_filter_valid(key, value) { const VALID_OPERATORS = new Set([">=", "<=", ">", "<", "=="]) const VALID_RELATIONS = new Set(["&&", "||"]) switch (key) { case "tool_filter": case "type_filter": return value.length > 0 case "coverage_filter": { if (value.length < 2 || ((value.length - 2) % 3) !== 0) return false if (!VALID_OPERATORS.has(value[0]) || !isFinite(value[1]) || value[1] < 0 || value[1] > 100) return false for (let i = 2; i < value.length; i += 3) { if (!VALID_RELATIONS.has(value[i+0])) return false if (!VALID_OPERATORS.has(value[i+1])) return false if (!isFinite(value[i+2]) || value[i+2] < 0 || value[i+2] > 100) return false } return true } } } _state_changed(state, changed_values) { let apply_possible = false; let reset_possible = false; const ERROR_MSGS = { tool_filter: "No tool selected.", coverage_filter: "Invalid coverage value(s).", type_filter: "No type selected.", } const ERROR_MSG_PREFIX = "Error(s): " const errors = [] for (const key of ["tool_filter", "coverage_filter", "type_filter"]) { if (!deep_eq(state[key], this._state.state_spec[key].initial)) reset_possible = true if (!deep_eq(state[key], state[`applied_${key}`])) apply_possible = true if (!FilterController._is_filter_valid(key, state[key])) errors.push(ERROR_MSGS[key]) } if (errors.length > 0) this._error_label.innerHTML = ERROR_MSG_PREFIX + errors.join(" ") else this._error_label.innerText = "" this._apply_button.disabled = (errors.length != 0) || !apply_possible; this._reset_button.disabled = !reset_possible; } _apply_clicked(event) { const tool_filter = this._state.state.tool_filter const coverage_filter = this._state.state.coverage_filter const type_filter = this._state.state.type_filter this._state.state.applied_tool_filter = tool_filter this._state.state.applied_coverage_filter = coverage_filter this._state.state.applied_type_filter = type_filter if (!(coverage_filter.length === 2 && ( (coverage_filter[0] === ">=" && coverage_filter[1] === 0) || (coverage_filter[0] === "<=" && coverage_filter[1] === 100) ))) { const operator = coverage_filter[0] const value = coverage_filter[1] let coverage_filter_code = `(coverage ${operator} ${value})` for (let i = 2; i < coverage_filter.length; i += 3) { const relation = coverage_filter[i + 0] const operator = coverage_filter[i + 1] const value = coverage_filter[i + 2] coverage_filter_code += ` ${relation} (coverage ${operator} ${value})` } const cell_filter_func_code = `(coverage) => { return (${coverage_filter_code}) }` Log.dbg("filter", "Cell filter function: %o", cell_filter_func_code) const cell_filter_func = eval(cell_filter_func_code) this._state.state.cell_filter_func = cell_filter_func } else { this._state.state.cell_filter_func = null } if (!deep_eq(type_filter, this._state.state_spec.type_filter.initial)) { const type_filter_codes = [] for (const type of type_filter) type_filter_codes.push(`(types.includes("${type}"))`) const type_filter_code = type_filter_codes.join(" || ") const row_filter_func_code = `(types) => { return (${type_filter_code}) }` Log.dbg("filter", "Row filter function: %o", row_filter_func_code) const row_filter_func = eval(row_filter_func_code) this._state.state.row_filter_func = row_filter_func } else { this._state.state.row_filter_func = null } const hidden_column_ids = [] let i = HEADER_COLUMNS_COUNT for (const tool of TOOL_NAMES) { if (!tool_filter.includes(tool.toLowerCase())) hidden_column_ids.push(i) ++i } this._state.state.hidden_column_ids = hidden_column_ids } _reset_clicked(event) { for (const key of ["tool_filter", "coverage_filter", "type_filter"]) { this._state.state[key] = this._state.state_spec[key].initial } } } /// DataTable filter function that does actual filtering /////////////// $.fn.dataTable.ext.search.push(function (settings, searchData, index, rowData, counter) { if (filter_state.state.row_filter_func) { const dt = settings.oInstance.DataTable(); const types = dt.row(index).node().dataset.types.split(" ") if (!filter_state.state.row_filter_func(types)) return false } if (filter_state.state.cell_filter_func) { const hidden_column_ids = filter_state.state.hidden_column_ids const cell_filter_func = filter_state.state.cell_filter_func let i = 0 let has_matching_cell = false; for (let col = HEADER_COLUMNS_COUNT; col < rowData.length; ++col) { if (col === hidden_column_ids[i]) { ++i continue } const coverage = Math.round(parseSimpleFraction(rowData[col]) * 100)|0 if (cell_filter_func(coverage)) { has_matching_cell = true break } } if (!has_matching_cell) return false } return true }) /// Main /////////////////////////////////////////////////////////////// window.addEventListener('DOMContentLoaded', function(event) { // DataTable $('table.dataTable').DataTable({ paging: false, autoWidth: false, order: [ [1, "asc"], ], columns: [ { orderable: false }, { orderDataType: "original-order", type: "num" }, ...TOOL_NAMES.map(() => { return { orderDataType: "simple-fraction", type: "num", } }) ], }) // Update tables when a filter is applied const tables = [] $('table.dataTable').each(function () { const table = $(this).dataTable().api() tables.push(table) filter_state.subscribe( ["hidden_column_ids", "row_filter_func", "cell_filter_func"], StateManager.debounce((state, changed_values) => tables.forEach((table) => { if (changed_values.has("hidden_column_ids")) { table.columns().visible(true) table.columns(state.hidden_column_ids).visible(false) } setTimeout(()=>table.draw(), 0) }), 0)) }) // Filter const filter_section = document.querySelector("#filter-section") const filter_controller = new FilterController(filter_state, { apply_button: document.getElementById("filter-apply-button"), reset_button: document.getElementById("filter-reset-button"), error_label: document.getElementById("filter-error-msg"), }) // Tool filter const tool_filter = filter_section.querySelector(".p_tool-filter") const tool_filter_checkboxes = tool_filter.querySelectorAll("input[type='checkbox']") tool_filter.querySelector(".p_select-all-button").onclick = (event) => { tool_filter_checkboxes.forEach((element) => { if (!element.checked) { element.checked = true element.dispatchEvent(new Event("change")) } }) } tool_filter.querySelector(".p_invert-selection-button").onclick = (event) => { tool_filter_checkboxes.forEach((element) => { element.checked = !(element.checked) element.dispatchEvent(new Event("change")) }) } const tool_filter_controls = new CheckboxGroupController(filter_state, "tool_filter", tool_filter_checkboxes) // Coverage filter const coverage_filter_controls = new CoverageFilterEntriesController(filter_state, filter_section.querySelector(".p_coverage-filter")); // Type filter const type_filter_checkboxes = document.querySelectorAll("#filter-section .p_type-filter input[type='checkbox']") const type_filter_controls = new CheckboxGroupController(filter_state, "type_filter", type_filter_checkboxes) }) ================================================ FILE: conf/report/filter_ui_test.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from selenium import webdriver from selenium.webdriver.support.ui import Select import sys def setDriver(arg=None): global driver if arg is None: driver = webdriver.Chrome() else: driver = arg def openPage(URL): driver.get(URL) driver.implicitly_wait(10) driver.find_element_by_tag_name('button').click() def addEntries(iter): for _ in range(iter): driver.find_element_by_class_name('filter-add').click() def fillEntryType(num, type): entry_type = "//*[@class='filter-entry-type']" select = Select(driver.find_elements_by_xpath(entry_type)[num]) select.select_by_value(type) def fillSpan(entry_id, *args): for i in range(len(args)): entry_operator = f"(//*[@id='filter']/ul/li[{entry_id+1}]/span/select)[{i+1}]" select = Select(driver.find_element_by_xpath(entry_operator)) select.select_by_value(args[i]) def applyFilters(): driver.find_element_by_class_name('filter-apply').click() def removeIcon(num): driver.find_elements_by_class_name('filter-clear')[num].click() def removeAll(): driver.find_element_by_class_name('filter-remove').click() if __name__ == "__main__": URL = sys.argv[1] driver = setDriver(webdriver.Chrome()) openPage(URL) addEntries(3) fillEntryType(0, "coverage") fillEntryType(1, "type") fillEntryType(2, "tool") fillSpan(0, ">", "50", "or", "<", "80") fillSpan(1, "is", "preprocessing") fillSpan(2, "is", "verible", "and", "is", "surelog") applyFilters() removeIcon(2) removeAll() ================================================ FILE: conf/report/footer.html ================================================

Generated using sv-tests, revision: {{revision}}, {% if build_id != 'local' %} build_id: {{build_id}}, {% else %} build_id: {{build_id}}, {% endif %} date: {{datetime}}.

================================================ FILE: conf/report/history-graph-template.html ================================================ ================================================ FILE: conf/report/log-template.html ================================================

{{log['runner']|e}}

{{result.name|e}}

description
{{log['description']|e}}
rc
{{result.exit_code}} (means success: {{log['tool_success']|e}})
{% if should_fail_because|length %}
should_fail_because
{{log['should_fail_because']|e}}
{% endif %}
tags
{{result.tags|join(' ')|e}}
incdirs
    {% for dir in log['incdirs'].split(' ') %}
  • {{dir}}
  • {% endfor %}
top module
{{log['top_module']|e}}
type
{{result.types|join(' ')|e}}
results group
{% if result.results_group|length %}{{result.results_group|e}}{% else %}{% endif %}
mode
{{log['mode']|e}}
files
    {% for f, f_html in input_files_map.items() %}
  • {{f|e}}
  • {% endfor %}
defines
{{log['defines']|e}}
completed
{{log['date_completed']|e}}
time elapsed
{{'%0.3f'| format(result.total_time|float)}}s
ram usage
{{'%d'| format(result.ram_usage|int)}} KB
{% for line in content.split('\n') %} 
{{line}}
{% endfor %}
================================================ FILE: conf/report/log.css ================================================ @import 'details-view.css'; :root { /* Colors */ --white: #FFFFFF; --light-gray: #F9F9F9; --gray: #E6E6E6; --dark-gray: #8E8E93; --black: #2C2C2E; --red: #ED5545; --green: #63C366; --accent: #1226AA; /* Padding */ --gap-l:30px; --gap-m:20px; --gap-s:10px; /* Breakpoints */ --mobile:670px; --tablet:1280px; --desktop:1920px; } section { margin: 0; padding: 4px; overflow: hidden; width: 100%; } section.property-list.test-passed { background-color: #D7ECD4; } section.property-list.test-failed { background-color: #F5CFCA; } section.property-list a:link { color: #00006f; } section.property-list > dl { margin: 0; } section.property-list > dl > div { display: block; line-height: 1.2em; } header.test-passed { background-color: var(--green); position: sticky; left: 0; top: 0; width: calc(100vw - 15px); } header.test-failed { background-color: var(--red); position: sticky; left: 0; top: 0; width: calc(100vw - 15px); } section.property-list > dl dt { display: inline; font-weight: bold; } section.property-list > dl dt::after { content: ":"; } section.property-list > dl dd { margin: 0 0 0 0.5em; display: inline; } section.property-list > dl dd ul { margin: 0 0 0.5rem 1rem; padding: 0; } section.property-list > dl dd ul li { list-style-type: none; } section.log { padding: 4px; background-color: white; } section.log > pre { margin: 0; padding: 0; font-family: "Courier New", Consolas, monospace; } ================================================ FILE: conf/report/navbar.html ================================================
================================================ FILE: conf/report/report-template.html ================================================ {# vim: set ts=2 sts=2 sw=2 et: #} SystemVerilog Report {# Global parameters for scripts and stylesheets #} {% include 'navbar.html' %}
Advanced filters
Tool
{% for tool, tool_info in report.tools|numeric_dictsort %} {% endfor %}
Coverage
%
Type
{% for type in ["Elaboration", "Parsing", "Simulation"] %} {% endfor %}
{% for group, group_data in report.groups|numeric_dictsort %} {% for tool, tool_info in report.tools|numeric_dictsort %} {% endfor %} {% for tag, tools in group_data.tags_tools|tag_dictsort %} {% set tag_info = report.tags[tag] %} {% set types_used_in_the_row = [] %} {% for tool, tool_data in tools.items() %} {% for type in tool_data.types %} {% if type not in types_used_in_the_row %} {% set _ = types_used_in_the_row.append(type) %} {% endif %} {% endfor %} {% endfor %} {% for tool in report.tools|numeric_sort %} {% set attrs = [] %} {% if tool in tools %} {% set tool_data = tools[tool] %} {% set test_status = tool_data.status|string %} {% if test_status != 'test-na' %} {% set _ = attrs.append('class=' ~ (test_status|quote)) %} {% set _ = attrs.append('data-tool=' ~ (tool|lower|escape_attr|quote)) %} {% if test_status == 'test-varied' %} {% set percentage = '%0.0f'|format(100.0 * tool_data.passed_tests / tool_data.total_tests) %} {% set _ = attrs.append('style="--val: '~(percentage)~'%"') %} {% endif %} {% endif %} {% endif %} {% if attrs|length %} {% else %} {% endif %} {% endfor %} {% endfor %} {% for tool in report.tools|numeric_sort %} {% if tool in group_data.summaries %} {% set tool_summary = group_data.summaries[tool] %} {% set passed_tests = tool_summary.total_passed_tests %} {% set total_tests = tool_summary.total_tests %} {% set passed_tests_percentage = '%0.0f'|format(100.0 * passed_tests / total_tests) %} {% else %} {% endif %} {% endfor %} {% for tool in report.tools|numeric_sort %} {% if tool in group_data.summaries %} {% set tool_summary = group_data.summaries[tool] %} {% set passed_tags = tool_summary.total_passed_tags %} {% set tested_tags = tool_summary.total_tested_tags %} {% set passed_tags_percentage = '%0.0f'|format(100.0 * passed_tags / tested_tags) %} {% else %} {% endif %} {% endfor %} {% for tool in report.tools|numeric_sort %} {% if tool in group_data.summaries %} {% set tool_summary = group_data.summaries[tool] %} {% else %} {% endif %} {% endfor %} {% for tool in report.tools|numeric_sort %} {% if tool in group_data.summaries %} {% set tool_summary = group_data.summaries[tool] %} {% else %} {% endif %} {% endfor %} {% for tool in report.tools|numeric_sort %} {% if tool in group_data.summaries %} {% set tool_summary = group_data.summaries[tool] %} {% else %} {% endif %} {% endfor %} {% for tool in report.tools|numeric_sort %} {% if tool in group_data.summaries %} {% set tool_summary = group_data.summaries[tool] %} {% else %} {% endif %} {% endfor %} {% for tool in report.tools|numeric_sort %} {% if tool in group_data.summaries %} {% set tool_summary = group_data.summaries[tool] %} {% else %} {% endif %} {% endfor %}

{{group|e}}

 {{tool|e}}
{%- if tag_info.url -%} {{tag_info.description|e}} {%- else -%} {{tag_info.description|e}} {%- endif -%} {{tag|e}}{{tool_data.passed_tests}}/{{tool_data.total_tests}}
Total tests passed{{passed_tests}}/{{total_tests}}
Total tags passed{{passed_tags}}/{{tested_tags}}
Total time elapsed{{'%0.0f'|format(tool_summary.total_time)}}s
User time elapsed{{'%0.0f'|format(tool_summary.user_time)}}s
System time elapsed{{'%0.0f'|format(tool_summary.system_time)}}s
Maximum ram usage{{'%0.0f'|format(tool_summary.max_ram_usage)}} MB
Average throughput passed for inputs > 1KiB{{'%0.0f'|format(tool_summary.passed_throughput|float)}} KiB/s
{% endfor %}
Download a summary in csv
{% include 'footer.html' %}

TEST DETAILS

================================================ FILE: conf/report/report.css ================================================ :root { /* Colors */ --white: #FFFFFF; --light-gray: #F9F9F9; --gray: #E6E6E6; --dark-gray: #8E8E93; --black: #2C2C2E; --red: #ED5545; --green: #63C366; --accent: #1226AA; /* Padding */ --gap-l:30px; --gap-m:20px; --gap-s:10px; /* Breakpoints */ --mobile:670px; --tablet:1280px; --desktop:1920px; } /******** GENERAL ********/ * { box-sizing: border-box; margin: 0px; } h1{ font-size: 24px; font-family: 'Lato', sans-serif; font-weight: 700 } h2{ font-size: 15px; font-family: 'Lato', sans-serif; font-weight: 500; padding-left: 10px; } h3{ font-size: 14px; font-family: 'Roboto', sans-serif; font-weight: 500; } h4{ font-size: 13px; font-family: 'Roboto', sans-serif; } h5{ font-size: 12px; font-family: 'Roboto', sans-serif; } p{ font-size: 12px; font-weight: 300; } a { font-size: 16px; font-family: 'Roboto', sans-serif; font-weight: 500; color: var(--black); text-decoration: underline; } a:hover { color: var(--accent); transition: ease-in 0.2s; } body { background-color: var(--white); margin: 0; font-family: 'Roboto', sans-serif; width: fit-content; min-width: 100%; font-family: sans-serif; margin: 0; padding: 0 0 var(--panel-height, 0) 0; } footer { display: flex; position:sticky; width: 100%; margin-left: 0 !important; margin-right: 0; align-items: center; justify-content: center; font-size: 10px; flex-direction: column; } /******** HEADER ********/ header { margin-left: var(--gap-m); margin-right: var(--gap-m); z-index: 600; } @media only screen and (max-width: 670px) { header { margin-left: var(--gap-s); margin-right: var(--gap-s); } } .menu { display: flex; flex-direction: row; list-style-type: none; margin: 0; padding: 0; } .menu > li { margin: 0 1rem; overflow: hidden; } .menu-button-container { display: none; height: 100%; width: 30px; cursor: pointer; flex-direction: column; justify-content: center; align-items: center; } #menu-toggle { display: none; } .menu-button,.menu-button::before,.menu-button::after { display: block; background-color: var(--black); position: absolute; height: 3px; width: 20px; transition: transform 400ms cubic-bezier(0.23, 1, 0.32, 1); border-radius: 2px; } .menu-button::before { content: ''; margin-top: -8px; } .menu-button::after { content: ''; margin-top: 8px; } #menu-toggle:checked + .menu-button-container .menu-button::before { margin-top: 0px; transform: rotate(405deg); } #menu-toggle:checked + .menu-button-container .menu-button { background: rgba(255, 255, 255, 0); } #menu-toggle:checked + .menu-button-container .menu-button::after { margin-top: 0px; transform: rotate(-405deg); } @media (max-width: 700px) { .menu-button-container { display: none; } .menu { position: absolute; top: 0; margin-top: 100px; left: 0; flex-direction: column; width: 100%; justify-content: center; align-items: center; z-index:300; } #menu-toggle ~ .menu li { height: 0; margin: 0; padding: 0; border: 0; transition: height 400ms cubic-bezier(0.23, 1, 0.32, 1); } #menu-toggle:checked ~ .menu li { height: 3.5em; padding: 0.5em; transition: height 400ms cubic-bezier(0.23, 1, 0.32, 1); } .menu > li { display: flex; justify-content: center; margin: 0; padding: 0.5em 0; width: 100%; color: var(--black); background-color: var(--white); } .menu > li:not(:last-child) { border-bottom: 1px solid #444; } } .top-nav { display: flex; position: sticky; left: 0; flex-direction: row; align-items: center; justify-content: space-between; background-color: var(--white); height: 100px; width: calc(100vw - 30px); padding: var(--gap-m); } .nav-logo{ display: flex; } .logo-description { width: 300px; font-family: 'Lato'; font-weight: 500; font-size: 13px; word-break: break-all; text-decoration: none; } @media only screen and (max-width: 1200px) { .logo-description { display: none; } } .logo-text { margin-left: var(--gap-m); display: flex; flex-direction: row; align-items: center; } .nav-link{ font-size: 15px; font-family: 'Lato', sans-serif; font-weight: 700; color: var(--black); text-decoration: none; } /******** FILTERS ********/ .dataTables_filter { float: none !important; text-align: center; display: flex; justify-content: flex-end; margin: var(--gap-m); } .dataTables_wrapper .dataTables_filter input { margin-left: 0.5em; } #filter-section { cursor:pointer; color: var(--black); text-decoration:none; font-size: 15px; font-family: "Roboto"; } #filter-section > details > summary { cursor:pointer; color: var(--accent); padding: var(--gap-m) 0; font-size: 15px; font-family: "Roboto"; font-weight: 600; text-transform: uppercase; } marker { content: "> "; } select { padding: var(--gap-s); border-radius: 5px; margin-right: 10px; border: 1px solid var(--dark-gray); } input[type="number" i]{ padding: var(--gap-s); border-radius: 5px; border: 1px solid var(--dark-gray); margin-right: 5px; } button { background-color: var(--white); border-radius: 5px; border:1px solid var(--gray); display:inline-block; cursor:pointer; color: var(--black); padding: var(--gap-s) var(--gap-m); text-decoration:none; font-size: 15px; font-family: "Roboto"; } button:hover { background-color: var(--accent); transition: ease-in 0.2s; color: var(--white); } .p_add-entry-button{ margin-top: 5px; } dt { font-family: 'Roboto'; font-style: normal; font-weight: 600; text-transform: uppercase; color: var(--dark-gray); margin-bottom: 5px; margin-top: 20px; } label { margin-right: 10px; display: block; } #filter-section { padding: var(--gap-m); border-bottom: 1px solid var(--gray); border-top: 1px solid var(--gray); } #filter-apply-button { background-color: var(--accent); transition: ease-in 0.2s; color: var(--white); } .controls{ display:flex; margin-top: 10px; justify-content:flex-end; } .p_checkboxes{ margin-bottom: 5px; } input[type="checkbox" i] { margin-right: 5px; width: 15px; margin-top: 3px; height: 15px; } #report_table-_filter > label { color: var(--black); } #report_table-cores_filter > label { color: var(--black); } #report_table-imported_filter > label { color: var(--black); } form { color: #555; display: flex; padding: 2px; border: 1px solid currentColor; border-radius: 5px; margin: 0 0 30px; } input[type="search"] { background: transparent; height: 45px; min-width: 300px; max-width: 500px; padding: var(--gap-s) var(--gap-s); font-size: 16px; border: 1px solid var(--dark-gray); border-radius: 5px; padding-left: 35px; background: url(search.svg) no-repeat left; background-size: 20px; background-position: 7px; } /******** TABLE ********/ table.dataTable thead th, table.dataTable thead td { border-bottom: none; } table.dataTable { width:100%; overflow:auto; border-collapse: collapse; } .dataTables_info { font-size: 12px; margin-top: 3px; float: none !important; text-align: left; } table.dataTable td, table.dataTable th:nth-of-type(2) { border: 1px solid var(--gray); } tr > th:nth-of-type(1){ font-family: 'Roboto', sans-serif; font-weight: 500; padding-left: 20px; padding-right: 5px; width: 260px; min-width: 260px; height: 60px; border-bottom: 1px solid var(--gray); background-color: var(--white); text-align:left; color: var(--black); } @media only screen and (max-width: 670px) { tr > th:nth-of-type(1){ width: 160px; min-width: 160px; } } tr > th:nth-of-type(2){ font-family: 'Roboto', sans-serif; font-weight: 500; padding: var(--gap-s); min-width:60px; text-align:center; color: var(--dark-gray); word-break: break-word; border-bottom: 1px solid var(--gray); } td{ width:2000px; } th{ width:2000px; word-break: break-word; } thead th { height: 80px; min-width: 90px; background-color: var(--light-gray); border-top: 1px solid var(--gray); border-bottom: 1px solid var(--gray); } table.dataTable > tbody > tr > td { text-align: center; min-width: 90px; color: white; } table.dataTable > tfoot > tr > td { font-weight: normal !important; text-align: center; border: 1px solid var(--gray) !important; overflow: hidden; padding: 0; } table.dataTable > tfoot > tr, tfoot > tr> th:nth-of-type(1) { background-color: var(--light-gray); } @media only screen and (max-width: 670px){ tfoot > tr > th:nth-of-type(1) { max-width: 330px;} } table.dataTable, table.dataTable th, table.dataTable td { box-sizing: border-box; } /******** TEST STATUS ********/ .test-failed { background-color: var(--red); } .test-passed { background-color: var(--green); } .test-varied { background-color: var(--red); background-image:url('data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAEAAAABCAYAAAAfFcSJAAAACXBIWXMAAAsTAAALEwEAmpwYAAAAAXNSR0IArs4c6QAAAARnQU1BAACxjwv8YQUAAAAQSURBVHgBAQUA+v8AY8Nm/wWlAoycuazwAAAAAElFTkSuQmCC'); background-repeat:no-repeat; background-size: var(--val, 100%) 100%; } /******** TABLE SORTING ********/ table.dataTable thead .sorting, table.dataTable thead .sorting_asc, table.dataTable thead .sorting_desc, table.dataTable thead .sorting_asc_disabled, table.dataTable thead .sorting_desc_disabled { cursor: pointer; background-repeat: no-repeat; background-position: bottom right; } table.dataTable thead .sorting { background-image: url("sort_both.png"); } table.dataTable thead .sorting_asc { background-image: url("sort_asc.png"); } table.dataTable thead .sorting_desc { background-image: url("sort_desc.png"); } /******** STICKY COLUMNS ********/ table.dataTable > tbody > tr > th:nth-of-type(-n+2), table.dataTable > tfoot > tr > th:nth-of-type(-n+2) { position: sticky; z-index: 1; } table.dataTable > * > tr > th:nth-of-type(1) { left: 0; } table.dataTable > * > tr > th:nth-of-type(2) { left: 260px; background-color: var(--white); min-width: 120px; width: 120px; border-left: 0; } @media only screen and (max-width: 670px) { table.dataTable > * > tr > th:nth-of-type(2) { left: 160px; min-width: 100px; width: 100px; } } table.dataTable > thead > tr > th:nth-of-type(n+2) { position: sticky; z-index: calc(2 + var(--z, 0)); top: -1px; min-width: 140px; } table.dataTable thead th, table.dataTable thead td { padding: 0px 5px; } table.dataTable > thead > tr > th:nth-of-type(-n+2) { position: sticky; z-index: calc(3 + var(--TOOLS_COUNT, 100)); top: 0; background-color: var(--light-gray); } table.dataTable > tfoot > tr:nth-of-type(-n+2) > td { color: white; font-weight: bold; } table.dataTable tbody th, table.dataTable tbody td { padding: 0px 15px; } table.dataTable tfoot th, table.dataTable tfoot td { padding: 10px 18px 6px 15px; } /******** DETAILS ********/ .c_test-details-panel .p_close-button { background: var(--black); float: top; grid-area: "options"; } .c_test-details-panel { position: fixed; bottom: 0; z-index: 50; width: 100%; display: flex; flex-direction: column; align-items: stretch; justify-items: stretch; justify-content: stretch; overflow-y: hidden; overflow-x: hidden; background-color: white; font-family: "Courier New", Courier, monospace; align-content: space-evenly; } @media only screen and (max-width: 1000px) { .c_test-details-panel { display: flex; flex-direction: column; } } .p_log { width: 50vw; min-height: 30vh; } @media only screen and (max-width: 1000px) { .p_log { width: 100vw; } } .p_file { width:50%; min-height: 30vh; background-color: white; } @media only screen and (max-width: 1000px) { .p_file { width: 100vw; } } .test-details { height: 60px; background-color: var(--light-gray); display: flex; align-items: center; flex-direction: row; color: var(--dark-gray); justify-content: space-between; margin-left: 10px; margin-right: 10px; } .wrapper { width: 60px; } .grid-2{ display: flex; flex-direction: row; } section.log { background-color: white; } @media only screen and (max-width: 1000px) { .grid-2 { display: flex; flex-direction: column; } } .c_test-details-panel.s_hidden { display: none; } .c_test-details-panel > iframe { background-color: #fff; border: none; height: 30vh; } .c_test-details-panel > .p_tests-list { max-height: 20vh; background-color: var(--white); overflow-y: scroll; } .c_test-details-panel > .p_tests-list > button { width: 20%; height: 60px; margin: 0px; cursor: pointer; border: 1px solid var(--white); overflow:hidden; text-overflow: ellipsis; white-space: nowrap; color: white; box-sizing: border-box; } @media only screen and (max-width: 670px) { .c_test-details-panel > .p_tests-list > button { height: 50px; width: 50% } } .c_test-details-panel > .p_tests-list > button:focus { outline:0; } .c_test-details-panel .p_close-button { background: var(--black); border-radius: 25px; float: top; color: white; padding: 12px; width: 35px; height: 35px; display: flex; } .c_test-details-panel > .p_tests-list > .p_item { float: left; background-color: var(--red); } .c_test-details-panel > .p_tests-list > .p_item.s_passed { background-color: var(--green); } .c_test-details-panel > .p_tests-list > .p_item.s_selected { -webkit-box-shadow:inset 0px 0px 0px 5px var(--white); -moz-box-shadow:inset 0px 0px 0px 5px var(--white); box-shadow:inset 0px 0px 0px 5px var(--white); filter: brightness(95%); font-weight: bold; } .ui-widget-shadow { -webkit-box-shadow: none; box-shadow: none; } .ui-tooltip { font-size: 13px; white-space: pre-wrap; max-width: 100%; } .ui-corner-all { border-radius: 0px; } table.dataTable > tbody > tr > td:not(:empty):hover { cursor: pointer; } table.dataTable > tbody > tr > td:not(:empty).s_selected { -webkit-box-shadow:inset 0px 0px 0px 5px var(--gray); -moz-box-shadow:inset 0px 0px 0px 5px var(--gray); box-shadow:inset 0px 0px 0px 5px var(--gray); filter: brightness(95%); font-weight: bold; } /******** STICKY PAGE ********/ header, .dataTables_filter { position: sticky; width: calc(100vw - 30px); left: 0; margin-left: 0 !important; margin-right: 0 !important; } #filter-section, .dataTables_info, #summary-section, footer { position: sticky; width: calc(100vw - 30px); left: 10px; margin-left: 0; margin-right: 0; } iframe[seamless] { border: none; } ================================================ FILE: conf/report/report.js ================================================ /// Utils ////////////////////////////////////////////////////////////// function is_string(o) { return (typeof o === "string" || o instanceof String) } function is_empty(str) { return str.length === 0 } function deep_eq(a, b) { if (Array.isArray(a)) { if (!Array.isArray(b) || a.length != b.length) return false return a.every((v, i) => deep_eq(v, b[i])) } else { return a === b } } function parseSimpleFraction(s, for_sorting=false) { try { let [nom, denom] = s.split("/").map((v) => parseInt(v)) if (for_sorting) { // Add small offsets so that fractions with the same value will be // sorted by denominator (e.g. 0/8 < 0/1, 1/1 < 20/20, etc). nom += 0.000001 denom += 0.000002 } const value = nom / denom return isFinite(value) ? value : NaN } catch (e) { return NaN } } class Log { static dbg(tag, fmt, ...rest) { console.debug(`%c[${tag}]%c ${fmt}`, "text-transform:uppercase;font-weight:bold", "", ...rest) } static err(tag, fmt, ...rest) { console.error(`%c[${tag}]%c ${fmt}`, "text-transform:uppercase;font-weight:bold", "", ...rest) } } /// Custom sorting for DataTable /////////////////////////////////////// // Sorts using original order of HTML table rows $.fn.dataTable.ext.order['original-order'] = function (settings, col) { return [...Array(this.DataTable().data().length).keys()] } $.fn.dataTable.ext.order['simple-fraction'] = function (settings, col) { return this.DataTable().data().map(function (row) { const value = parseSimpleFraction(row[col], true) return isFinite(value) ? value : -Infinity }) } /// ConfigLoader /////////////////////////////////////////////////////// // Global map where loaded configs put data under their individual keys. // The key is: "${tool}/${tag}", where both tool and tag are lowercase. // The variable is considered PRIVATE - do not use it outside of ConfigLoader. config_loader_data = {} class ConfigLoader { constructor() { this._data = null this._loaded_key = null } // Loads config for specified tool and tag. // NOTE: do not call this concurrently multiple times. async load(tool, tag) { console.assert(is_string(tool) && !is_empty(tool), tool) console.assert(is_string(tag) && !is_empty(tag), tag) tool = tool.toLowerCase() tag = tag.toLowerCase() const key = `${tool}/${tag}`; if (this._loaded_key === key) { return this._data } const path = `results/${tool}/${tag}.config.js` config_loader_data[key] = undefined let script = document.createElement("script") const loading_done = new Promise((resolve, reject) => { script.onload = resolve script.onerror = reject }) script.src = path document.head.appendChild(script) try { await loading_done } catch (e) { Log.err("config", "Loading failed.\n" + "tool/tag: %o/%o\nkey: %o\npath: %o\nexception: %o", tool, tag, key, path, e) return null } script.remove() if (config_loader_data[key] === undefined) { Log.err("config", "The loaded config script didn't assign anything to a dedicated global variable. The script probably has been generated incorrectly.\n" + "tool/tag: %o/%o\nkey: %o\npath: %o", tool, tag, key, path) return null } Log.dbg("config", "Loaded. key: %o; path: %o", key, path) this._loaded_key = key this._data = config_loader_data[key] delete config_loader_data[key] return this._data } // Releases data. Note that The data still resides in memory if there // are other references to it. unload() { if (this._loaded_key !== null) { const key = this._loaded_key this._data = null; this._loaded_key = null; Log.dbg("config", "Unloaded. key: %o", key) } } get data() { return this._data } } /// ReportViewerState ////////////////////////////////////////////////// class StateManager { constructor(state_spec) { this._spec = state_spec Object.freeze(state_spec) this._state = new Map() this._subscribers = new Map() for (const [key, spec] of Object.entries(state_spec)) { Log.dbg("state/init", "%s: %o", key, spec.initial) this._state.set(key, spec.initial) this._subscribers.set(key, new Set()) } this._state_proxy = new Proxy(this._state, { get: this._get_state_value.bind(this), set: this._set_state_value.bind(this), }) } _get_state_value(state, key, proxy) { console.assert(state.has(key), key) return state.get(key) } _set_state_value(state, key, value, proxy) { let previous_value = state.get(key) if (deep_eq(value, previous_value)) return true if (this._spec[key].validator) { if (!this._spec[key].validator(value)) { Log.err("state/set", "%s: invalid value: %o", key, value) return false } } if (value instanceof Object) Object.freeze(value) state.set(key, value) Log.dbg("state/change", "%s: %o → %o", key, previous_value, value) this._subscribers.get(key).forEach((callable) => callable(this._state_proxy, new Map([[key, previous_value]]))) return true } subscribe(keys, callable) { if (callable === undefined) { callable = keys keys = this._subscribers.keys() } for (const key of keys) { console.assert(this._subscribers.has(key), key) this._subscribers.get(key).add(callable) } } unsubscribe(keys, callable) { if (callable === undefined) { callable = keys keys = this._subscribers.keys() } for (const key of keys) { console.assert(this._subscribers.has(key), key) this._subscribers.get(key).delete(callable) } } get state() { return this._state_proxy } get state_spec() { return this._spec } static debounce(callable, timeout=0) { function debounce_wrapper(state, changed_values) { if (this.changed_values !== null) { changed_values.forEach((v, k) => { if (!this.changed_values.has(k)) { this.changed_values.set(k, v) } else if (this.changed_values.get(k) === state[k]) { this.changed_values.delete(k) } }) if (this.changed_values.size === 0) clearTimeout(this.handle) return } this.changed_values = changed_values this.handle = setTimeout(() => { this.callable(state, this.changed_values) this.changed_values = null }, this.timeout) } return debounce_wrapper.bind({ callable: callable, timeout: timeout, handle: null, changed_values: null, }) } } /// TestDetailsPanel /////////////////////////////////////////////////// class TestDetailsPanel { constructor(state_manager, html_element) { this._state = state_manager this._panel = html_element this._log = this._panel.querySelector(".p_log") this._file = this._panel.querySelector(".p_file") this._tests_list = this._panel.querySelector(".p_tests-list") this._item_template = this._tests_list.querySelector(".p_item-template") this._close_button = this._panel.querySelector(".p_close-button") this._config = new ConfigLoader() this._test_name_to_id = new Map() this._items = [] this._selected_item = null this._last_viewed_test = null this._state.subscribe( ["tool_tag", "test", "group"], StateManager.debounce(this._state_changed.bind(this))) this._close_button.onclick = () => this.close() } async _state_changed(state, changed_values) { if (changed_values.has("tool_tag") || changed_values.has("group")) { const [tool, tag] = state.tool_tag if (tool === null || tag === null) { this._unload_and_hide() return } let group = state.group if (group === null) { console.assert(state.test !== null, state.test) group = await this._find_group(tool, tag, state.test) if (group !== null) { state.group = group } else { state.tool_tag = [null, null] } return } await this._load_tests(tool, tag, group) this._show_test(state.test) } else if (changed_values.has("test")) { this._show_test(state.test) } } async _find_group(tool, tag, test) { console.assert(is_string(tool) && !is_empty(tool), tool) console.assert(is_string(tag) && !is_empty(tag), tag) console.assert(is_string(test) && !is_empty(test), test) tool = tool.toLowerCase() tag = tag.toLowerCase() const config = await this._config.load(tool, tag) if (config === null) { Log.err("details panel", "Unknown tool/tag: %o/%o", tool, tag) return null } for (const [group, name] of config) { if (name === test) return group } return null } async _load_tests(tool, tag, group) { console.assert(is_string(tool) && !is_empty(tool), tool) console.assert(is_string(tag) && !is_empty(tag), tag) console.assert(is_string(group), group) tool = tool.toLowerCase() tag = tag.toLowerCase() await this._config.load(tool, tag) this._set_selected_item(null) for (const item of this._items) item.remove() this._items = [] this._test_name_to_id.clear() let test_id = -1 for (const [test_group, name, status, log_url, first_input_url] of this._config.data) { ++test_id if (test_group !== group) continue this._test_name_to_id.set(name, test_id) const item = this._item_template.content.firstElementChild.cloneNode(true) if (status) item.classList.add("s_passed") item.querySelector("slot[name='test-name']").replaceWith(name) item._test_id = test_id item.onclick = this._item_clicked.bind(this) this._tests_list.appendChild(item) this._items.push(item) } } _show_test(test) { console.assert(this._current_tool !== null) console.assert(test === null || is_string(test), test) let test_id if (!this._test_name_to_id.has(test)) { if (this._test_name_to_id.has(this._last_viewed_test)) { test = this._last_viewed_test test_id = this._test_name_to_id.get(test) Log.dbg("details panel", "Using last viewed test: %o", test) } else { try { // Use first available test test_id = this._items[0]._test_id test = this._config.data[test_id][1] Log.dbg("details panel", "Using first available test: %o", test) } catch (e) { Log.err("details panel", "Loaded tests list is empty.\n" + "tool/tag: %o/%o", this._current_tool, this._current_test) return } } this._state.state.test = test } else { test_id = this._test_name_to_id.get(test) } const log_url = this._config.data[test_id][3] const first_input_url = this._config.data[test_id][4] const item = this._items.find((e) => e._test_id == test_id) this._open_log(log_url) this._open_file(first_input_url) this._set_selected_item(item) this._last_viewed_test = test this._panel.classList.remove("s_hidden") } _open_log(url) { console.assert(is_string(url) && !is_empty(url), url) this._log.contentWindow.location.replace(url); } _open_file(url) { console.assert(is_string(url) && !is_empty(url), url) this._file.contentWindow.location.replace(url); } _set_selected_item(item) { if (this._selected_item === item) return; if (this._selected_item) this._selected_item.classList.remove("s_selected") if (item) { item.classList.add("s_selected") this._selected_item = item } else { this._selected_item = null } } _item_clicked(event) { const test_id = event.target._test_id console.assert(test_id >= 0 || test_id < this._config.data.length, test_id) const name = this._config.data[test_id][1] const log_url = this._config.data[test_id][3] const first_input_url = this._config.data[test_id][4] this._open_log(log_url) this._open_file(first_input_url) this._set_selected_item(event.target) this._last_viewed_test = name this._state.state.test = name } _unload_and_hide() { this._panel.classList.add("s_hidden") this._open_log("about:blank") this._open_file("about:blank") this._set_selected_item(null) for (const item of this._items) { item.remove() } this._items = [] this._test_name_to_id.clear() this._config.unload() } close() { this._unload_and_hide() this._state.state.tool_tag = [null, null] this._state.state.test = null this._state.state.group = null } } /// TestResultCellsSelectionController ///////////////////////////////// class TestResultCellsSelectionController { constructor(state_manager, tables) { this._state = state_manager this._tables = tables this._selected_cell = null; this._state.subscribe( ["tool_tag", "group"], StateManager.debounce(this._state_changed.bind(this))) for (const table of this._tables) { const cells = table.querySelectorAll("tbody > tr > td:not(:empty)") for (const cell of cells) { cell.onclick = this._cell_clicked.bind(this) } } } _state_changed(state, changed_values) { if (changed_values.has("tool_tag") || changed_values.has("group")) { const [tool, tag] = state.tool_tag const group = state.group if (this._set_selected_cell(tool, tag, group)) this._scroll_selected_cell_into_view() } } _scroll_selected_cell_into_view() { if (this._selected_cell === null) return const cell_to_scroll_to = this._selected_cell setTimeout(() => { if (cell_to_scroll_to === this._selected_cell) { cell_to_scroll_to.scrollIntoView({block: "center", inline: "end"}) } }, 250) } _set_selected_cell(tool, tag, group) { if (tool === null || tag === null || group === null) { this._set_selected_cell_element(null) return false } tool = tool.toLowerCase() tag = tag.toLowerCase() let cell = null for (const table of this._tables) { if (table.dataset.group != group) continue cell = table.querySelector(`tbody > tr[data-tag="${tag}"] > td[data-tool="${tool}"]`); if (cell) break; } cell = cell ? cell : null if (cell === this._selected_cell) return false this._set_selected_cell_element(cell) return true } _set_selected_cell_element(element) { if (element === this._selected_cell) return; if (this._selected_cell) this._selected_cell.classList.remove("s_selected") if (element) { Log.dbg("cell select", "%o", element) element.classList.add("s_selected") this._selected_cell = element } else { Log.dbg("cell select", "%o", null) this._selected_cell = null } } _cell_clicked(event) { const row_element = event.target.parentElement const tbody_element = row_element.parentElement const table_element = tbody_element.parentElement const tool = event.target.dataset.tool const tag = row_element.dataset.tag const group = table_element.dataset.group const [current_tool, current_tag] = this._state.state.tool_tag const current_group = this._state.state.group if (tool === current_tool && tag === current_tag && group == current_group) { this._set_selected_cell_element(null) this._state.state.tool_tag = [null, null] this._state.state.test = null this._state.state.group = null } else { this._set_selected_cell_element(event.target) this._state.state.tool_tag = [tool, tag] this._state.state.test = null this._state.state.group = group } } } /// KeyboardControl //////////////////////////////////////////////////// class KeyboardControl { constructor(state_manager) { this._state = state_manager document.addEventListener("keydown", this._key_pressed.bind(this)) } _key_pressed(event) { switch (event.key) { case "Escape": case "Esc": this._state.state.tool_tag = [null, null] this._state.state.test = null this._state.state.group = null break } } } /// UrlParametersController //////////////////////////////////////////// class UrlParametersController { constructor(state_manager) { this._state = state_manager this._update_state_from_parameters() this._state.subscribe( ["tool_tag", "test", "group"], StateManager.debounce(this._state_changed.bind(this), 125)) window.addEventListener("popstate", (event) => this._update_state_from_parameters()) } _state_changed(state, changed_values) { if (changed_values.has("tool_tag") || changed_values.has("test")) { const [tool, tag] = state.tool_tag const test = state.test const url = UrlParametersController._make_url(tool, tag, test) if (url.href === window.location.href) return history.pushState(null, "", url.href) document.title = UrlParametersController._make_title(tool, tag, test) } } static _make_url(tool, tag, test) { const url = new URL(window.location) if (tool === null || tag === null) { url.hash = "" url.searchParams.delete("v") } else if (test !== null) { url.hash = "" url.searchParams.set("v", `${tool} ${tag} ${test}`) } return url } static _make_title(tool, tag, test) { if (tool === null || tag === null) { return `SystemVerilog Report` } else if (test !== null) { return `${tool}/${tag}/${test} - SystemVerilog Report` } } _update_state_from_parameters() { let url = new URL(window.location) const set_state_if_valid = (tool, tag, test) => { if (tool !== undefined && tool !== "" && tag !== undefined && tag !== "" && test !== undefined && test !== "") { const url = UrlParametersController._make_url(tool, tag, test) if (url.href !== window.location.href) history.replaceState(null, "", url.href) document.title = UrlParametersController._make_title(tool, tag, test) this._state.state.tool_tag = [tool, tag] this._state.state.test = test this._state.state.group = null return true } return false } // Try URL parameter "v" containing "${TOOL} ${TAG} ${TEST}" const v = url.searchParams.get("v") if (is_string(v) && !is_empty(v)) { const values = v.split(" ") let [tool, tag, test] = values if (set_state_if_valid(tool, tag, test)) return } // Try URL hash containing "#${TOOL}|${TAG}|${TEST}" (legacy format) if (is_string(url.hash) && !is_empty(url.hash)) { const hash = decodeURIComponent(url.hash).substr(1) const [tool, tag, test] = hash.split("|") if (set_state_if_valid(tool, tag, test)) return } // Set initial state (no selected test). Required for correct state // restoration from history. set_state_if_valid(null, null, null) } } /// Main /////////////////////////////////////////////////////////////// const state_manager = new StateManager({ tool_tag: { initial: [null, null], validator: (v) => (Array.isArray(v) && ((is_string(v[0]) && is_string(v[1])) || (v[0] === null && v[1] === null))) }, test: { initial: null, validator: (v) => (is_string(v) || v === null) }, group: { initial: null, validator: (v) => (is_string(v) || v === null) }, }) var test_details_panel = null; var cells_selection_controller = null; var keyboard_control = null; var url_parameters_controller = null; window.addEventListener('DOMContentLoaded', function(event) { const test_details_panel_element = document.querySelector( ".c_test-details-panel") test_details_panel = new TestDetailsPanel(state_manager, test_details_panel_element) const tables = document.querySelectorAll(".dataTable") cells_selection_controller = new TestResultCellsSelectionController(state_manager, tables) keyboard_control = new KeyboardControl(state_manager) url_parameters_controller = new UrlParametersController(state_manager) // Track panel height and store it in body's "--panel-height" CSS property // TODO: move to a class, probably to TestDetailsPanel. const panel_resize_observer = new ResizeObserver(entries => { console.assert(entries.length === 1, entries) const panel_entry = entries[0] document.body.style.setProperty("--panel-height", `${panel_entry.borderBoxSize[0].blockSize}px`) }) state_manager.subscribe(["tool_tag"], StateManager.debounce((state, changed_values) => { if (state.tool_tag[0] !== null) { panel_resize_observer.observe(test_details_panel_element, { box: "border-box" }) } else { panel_resize_observer.unobserve(test_details_panel_element) document.body.style.removeProperty("--panel-height") } })) if (state_manager.state.tool_tag[0] !== null) panel_resize_observer.observe(test_details_panel_element, { box: "border-box" }) // Install tooltip component $(function() { $(document).tooltip({ track: true, show: 0, hide: 0 }); }); }) ================================================ FILE: conf/requirements.txt ================================================ pyyaml jinja2 tree_sitter==0.20.4 pygments yapf==0.30.0 psutil mako make_var markupsafe pytablewriter GitPython simplesat==0.8.2 git+https://github.com/lowRISC/edalize.git@ot git+https://github.com/lowRISC/fusesoc.git@ot orderedmultidict ================================================ FILE: conf/runners/libs.json ================================================ { "uvm": { "files": ["tests/uvm/src/uvm_pkg.sv"], "incdirs": ["tests/uvm/src"] } } ================================================ FILE: generators/ariane ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import sys import os import re from make_var import * templ = """/* :name: {name} :description: {description} :files: {files} :incdirs: {incdirs} :defines: {defines} :tags: ariane cva6 :results_group: cores :top_module: {top_module} :timeout: 360 */ """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR and TESTS_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) ariane_path = os.path.abspath(os.path.join(third_party_dir, "cores", "ariane")) hpdcache_path = os.path.join( ariane_path, "core", "cache_subsystem", "hpdcache") # Core-only configs use core/Flist.cva6 with target_cfg substitution. # The testbench config parses verilate_command from the Makefile via make -pn. lists = [ # 64-bit baseline — default config, std write-through cache, Sv39 MMU { 'name': 'cva6_cv64a6_imafdc_sv39', 'description': 'CVA6 64-bit RV64GC, Sv39 MMU, write-through cache', 'target_cfg': 'cv64a6_imafdc_sv39', 'top_module': 'cva6', 'flist': ['core/Flist.cva6'], }, # 64-bit HPDcache — exercises the entirely different HPDcache subsystem RTL { 'name': 'cva6_cv64a6_imafdc_sv39_hpdcache', 'description': 'CVA6 64-bit RV64GC, Sv39, HPDcache', 'target_cfg': 'cv64a6_imafdc_sv39_hpdcache', 'top_module': 'cva6', 'flist': ['core/Flist.cva6'], }, # 64-bit H-extension — hypervisor adds two-stage MMU, new CSRs { 'name': 'cva6_cv64a6_imafdch_sv39', 'description': 'CVA6 64-bit RV64GC + H-extension, Sv39', 'target_cfg': 'cv64a6_imafdch_sv39', 'top_module': 'cva6', 'flist': ['core/Flist.cva6'], }, # 32-bit — different XLEN, Sv32 MMU, no FPU { 'name': 'cva6_cv32a6_imac_sv32', 'description': 'CVA6 32-bit RV32IMAC, Sv32 MMU', 'target_cfg': 'cv32a6_imac_sv32', 'top_module': 'cva6', 'flist': ['core/Flist.cva6'], }, # Testbench — APU wrapper, AXI, peripherals, RVFI { 'name': 'cva6_tb_cv64a6_imafdc_sv39', 'description': 'CVA6 64-bit testharness with SoC peripherals', 'top_module': 'ariane_testharness', 'use_makefile': True, }, ] env_vars = { '${CVA6_REPO_DIR}': ariane_path, '${HPDCACHE_DIR}': hpdcache_path, '${CVA6_TB_DIR}': os.path.join(ariane_path, 'verif', 'tb', 'core'), } def expand_vars(line, target_cfg): for var, val in env_vars.items(): line = line.replace(var, val) line = line.replace('${TARGET_CFG}', target_cfg) return line def process_filelist(flist_path, target_cfg, incdirs, defines, sources): with open(flist_path) as f: for line in f: line = line.strip() if not line or line.startswith('//'): continue line = expand_vars(line, target_cfg) if line.startswith('+incdir+'): incdirs.add(line.partition('+incdir+')[2]) elif line.startswith('+define+'): defines.add(line.partition('+define+')[2]) elif line.startswith('-F'): nested = line.split(None, 1)[1].strip() if os.path.isfile(nested): process_filelist( nested, target_cfg, incdirs, defines, sources) elif re.search(r'\.(sv|v)$', line): if os.path.isfile(line): sources.append(line) def get_verilate_command_sources(): """Use make -pn to get the expanded verilate_command, then extract sources, incdirs, defines, and top_module from it.""" main_path = os.path.abspath(os.getcwd()) os.chdir(ariane_path) os.environ['RISCV'] = "./" M = make_vars(origin=['makefile']) os.chdir(main_path) try: ver_cmd = M['makefile']['verilate_command'] except KeyError: print("Warning: verilate_command not found in Makefile") return [], set(), set(), 'ariane_testharness' incdirs = set() defines = set() sources = [] top_module = 'ariane_testharness' seen = set() # Verilator auto-defines VERILATOR; add it for other tools (e.g. slang) # that don't. This controls ifdef guards for UVM includes, mock UART, etc. defines.add('VERILATOR') tokens = iter(ver_cmd.split()) for tok in tokens: tok = tok.strip() if tok.startswith('+incdir+'): incdirs.add(tok.partition('+incdir+')[2]) elif tok.startswith('+define+'): d = tok.partition('+define+')[2] if d: defines.add(d) elif tok == '-f': flist = next(tokens, '').strip() flist_path = os.path.join(ariane_path, flist) if os.path.isfile(flist_path): process_filelist( flist_path, 'cv64a6_imafdc_sv39', incdirs, defines, sources) seen.update(sources) elif tok == '--top-module': top_module = next(tokens, top_module).strip() elif re.search(r'\.(sv|v)$', tok): path = tok if os.path.isabs(tok) else os.path.join( ariane_path, tok) if os.path.isfile(path) and path not in seen: sources.append(path) seen.add(path) return sources, incdirs, defines, top_module test_dir = os.path.join(tests_dir, 'generated', tests_subdir) os.makedirs(test_dir, exist_ok=True) for entry in lists: incdirs = set() defines = set() sources = [] if entry.get('use_makefile'): sources, incdirs, defines, top = get_verilate_command_sources() entry['top_module'] = top else: for flist in entry['flist']: flist_path = os.path.join(ariane_path, flist) if not os.path.isfile(flist_path): print(f"Warning: flist not found: {flist_path}, skipping") continue process_filelist( flist_path, entry['target_cfg'], incdirs, defines, sources) if not sources: print(f"Warning: no sources for {entry['name']}, skipping") continue test_file = os.path.join(test_dir, entry['name'] + '.sv') with open(test_file, 'w') as f: f.write( templ.format( name=entry['name'], description=entry['description'], files=' '.join(sources), incdirs=' '.join(sorted(incdirs)), defines=' '.join(sorted(defines)), top_module=entry['top_module'], )) print(f"Generated: {test_file}") ================================================ FILE: generators/black-parrot ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import re import sys templ = """/* :name: {3} :description: black-parrot core test :files: {0} :incdirs: {1} :top_module: {2} :tags: black-parrot :results_group: cores :timeout: 1000 */ """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) bp_path = os.path.abspath( os.path.join(third_party_dir, "cores", "black-parrot")) # BlackParrot has RTL in the main repo and in the BaseJump STL submodule cmd = f"git submodule update --init --checkout {bp_path}" print(cmd) os.system(cmd) cmd = f"cd {bp_path}; git submodule update --init --recursive external/basejump_stl" print(cmd) os.system(cmd) cmd = f"cd {bp_path}; git submodule update --init --recursive external/HardFloat" print(cmd) os.system(cmd) lists = [ { 'name': 'bp_default', 'cfg': 'e_bp_default_cfg', 'flist': 'bp_top/syn/flist.vcs' }, { 'name': 'bp_unicore', 'cfg': 'e_bp_unicore_cfg', 'flist': 'bp_top/syn/flist.vcs' }, { 'name': 'bp_multicore_1', 'cfg': 'e_bp_multicore_1_cfg', 'flist': 'bp_top/syn/flist.vcs' }, { 'name': 'bp_multicore_1_cce_ucode', 'cfg': 'e_bp_multicore_1_cce_ucode_cfg', 'flist': 'bp_top/syn/flist.vcs' }, { 'name': 'bp_multicore_4', 'cfg': 'e_bp_multicore_4_cfg', 'flist': 'bp_top/syn/flist.vcs' }, { 'name': 'bp_multicore_4_cce_ucode_cfg', 'cfg': 'e_bp_multicore_4_cce_ucode_cfg', 'flist': 'bp_top/syn/flist.vcs' } ] dirs = { '$BP_COMMON_DIR': 'bp_common', '$BP_FE_DIR': 'bp_fe', '$BP_BE_DIR': 'bp_be', '$BP_ME_DIR': 'bp_me', '$BP_TOP_DIR': 'bp_top', '$BP_EXTERNAL_DIR': 'external', '$BASEJUMP_STL_DIR': 'external/basejump_stl', '$HARDFLOAT_DIR': 'external/HardFloat', } def expandPaths(p): for d in dirs: p = re.sub(re.escape(d), dirs[d], p) return os.path.join(bp_path, p) test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) for l in lists: sources = '' incdirs = '' with open(os.path.join(bp_path, l['flist'])) as f: for line in f: line = re.sub(r'^\+define\+.*?$', '', line) line = re.sub(r'//.*?$', '', line) line = re.sub(r'#.*?$', '', line) res = re.match(r'^\+incdir\+(.*?)$', line) if res is not None: incdirs += expandPaths(res.group(1)) + ' ' continue if len(line.strip()) > 0: sources += expandPaths(line.strip()) + ' ' test_file = os.path.join(test_dir, l['name'] + '.sv') cfg = l['cfg'] cmd = f"sed 's/BP_CFG_FLOWVAR/{cfg}/g' {bp_path}/bp_top/test/tb/bp_tethered/wrapper.sv > {test_file}" print(cmd) os.system(cmd) sources += os.path.realpath(test_file) with open(test_file, "r+") as f: content = f.read() f.seek(0, 0) f.write(templ.format(sources, incdirs, "wrapper", l['name']) + content) ================================================ FILE: generators/easyUVM ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys import yaml templ = """/* :name: easyUVM :description: UVM testbench test :files: {0} :incdirs: {1} :tags: uvm :timeout: 300 :unsynthesizable: 1 */ """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) uvm_path = os.path.abspath(os.path.join(third_party_dir, "tests", "easyUVM")) sources = os.path.join(uvm_path, 'top.sv') incdirs = uvm_path test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) test_file = os.path.join(test_dir, "top.sv") with open(test_file, "w") as f: f.write(templ.format(sources, incdirs)) ================================================ FILE: generators/fusesoc ================================================ #!/usr/bin/env python3 import os import re import sys import yaml import subprocess import collections import make_var templ = """/* :name: {0} :description: {1} :files: {2} :incdirs: {3} :defines: {4} :top_module: {5} :tags: {6} :timeout: {7} :results_group: cores :compatible-runners: {8} :type: {9} """ try: tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the TESTS_DIR and CONF_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) fusesoc_conf_subdir = "fusesoc-configs" fusesoc_conf_files = os.listdir( os.path.abspath(os.path.join(conf_dir, fusesoc_conf_subdir))) for fusesoc_conf_file in fusesoc_conf_files: fusesoc_conf_file = os.path.abspath( os.path.join(conf_dir, fusesoc_conf_subdir, fusesoc_conf_file)) if not os.path.isfile(fusesoc_conf_file): continue with open(fusesoc_conf_file, 'r') as stream: try: yml_conf = yaml.safe_load(stream) except yaml.YAMLError as err: print(err) sys.exit(1) try: yml_conf["name"] yml_conf["description"] yml_conf["top_module"] yml_conf["tags"] yml_conf["path"] yml_conf["command"] yml_conf["conf_file"] yml_conf["test_file"] yml_conf["timeout"] yml_conf["compatible-runners"] yml_conf["type"] except KeyError as err: print("No key", err, "in file", fusesoc_conf_file) continue test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) test_file = os.path.join(test_dir, yml_conf["test_file"]) command_list = list(yml_conf["command"].split(" ")) subprocess.call( command_list, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) core_conf_path = os.path.abspath(yml_conf["conf_file"]) sources_path = os.path.dirname(core_conf_path) incdirs = '' sources = '' defines = '' runner_flags = collections.defaultdict(str) if core_conf_path.endswith(".vc") or core_conf_path.endswith(".scr"): with open(core_conf_path, "r") as f: for line in f: line = line.strip() if line.startswith("+incdir+"): incdirs += os.path.join( sources_path, line.partition("+incdir+")[2]) + ' ' elif (core_conf_path.endswith('.vc') and line.startswith("--top-module")): top_module = line.partition("--top-module ")[2] elif line.startswith("-D"): defines += line[2:] + ' ' elif line.startswith("-CFLAGS"): runner_flags["verilator"] += "-CFLAGS -I" + os.path.join( sources_path, line.partition("-CFLAGS -I")[2]) + ' ' elif line.startswith("-LDFLAGS"): runner_flags["verilator"] += line + ' ' elif not line.startswith("-") and line: sources += os.path.join(sources_path, line) + ' ' try: make_vars = make_var.make_vars( cmd="make -pn -f " + os.path.join(sources_path, "config.mk")) runner_flags["verilator"] += make_vars["makefile"][ "VERILATOR_OPTIONS"] except: pass elif core_conf_path.endswith(".tcl"): with open(core_conf_path, "r") as f: for line in f: line = line.strip() src_file_match = re.match( r"read_verilog\s+-sv\s+{?(.+?)}?\s*$", line) if src_file_match: src_file = src_file_match.group(1) sources += os.path.join(sources_path, src_file) + " " elif line.startswith("set_property include_dirs "): line.replace("set_property include_dirs ", "") # Skip unnecessary information here, leave only paths to include dirs split = line.split(" ")[3:-3] for s in split: incdirs += os.path.join(sources_path, s) + " " else: print( f"Unsupported config file: {core_conf_path}, currently supports only .vc, .scr and .tcl files" ) sys.exit(1) # Fusesoc files dedicated for Verilator contains top module if not core_conf_path.endswith('.vc'): top_module = yml_conf["top_module"] with open(test_file, "w") as f: f.write( templ.format( yml_conf["name"], yml_conf["description"], sources, incdirs, defines, top_module, yml_conf["tags"], yml_conf["timeout"], yml_conf["compatible-runners"], yml_conf["type"])) for runner, flags in runner_flags.items(): f.write(f":runner_{runner}_flags: {flags}\n") f.write("*/") ================================================ FILE: generators/fx68k ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys templ = """/* :name: fx68k :description: Full fx68k core test :files: {0} :tags: fx68k :results_group: cores :timeout: 100 */ """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR and TESTS_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) fx68k_path = os.path.abspath(os.path.join(third_party_dir, "cores", "fx68k")) fx68k_sources = ['fx68k.sv', 'fx68kAlu.sv', 'uaddrPla.sv'] sources = '' for src in fx68k_sources: sources += os.path.join(fx68k_path, src) + ' ' test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) test_file = os.path.join(test_dir, "fx68k.sv") with open(test_file, "w") as f: f.write(templ.format(sources)) ================================================ FILE: generators/ivtest ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import re import os import sys import glob templ = """/* :name: {0} :description: Test imported from ivtest :files: {1} :incdirs: {3} :tags: ivtest :results_group: imported :type: simulation elaboration parsing {2} {4} */ """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) type_should_fail = ['CE', 'RE'] # FIXME: this all needs to be updated to properly load the ivtest *.list # files like is done with the ivtest driver along with the correct # override of the various tests. ivtest_list_exclude = [ 'blif.list', # Skip the BLIF test list 'regress-ivl1.list', # Skip the Icarus specific test list 'regress-ivl2.list', # Skip the Icarus strict test list 'regress-msys2.list', # Skip the msys2 override test list 'regress-v10.list', # Skip the v10 override test list 'regress-v11.list', # Skip the v11 override test list 'regress-v12.list', # Skip the v12 override test list 'regress-vams.list', # Skip the VAMS test list 'regress-vhdl.list', # Skip the VHDL test list 'regress-vlog95.list', # Skip the vlog95 override test list 'vhdl_regress.list', # Skip the VHDL side test list 'vpi_regress.list' # Skip the VPI test list ] ivtest_file_exclude = [ # The following are invalid per the latest standard, but are supported by # commercial tools. For now exclude these tests in sv-tests. # '{} (empty array) 'sv_array_assign_pattern2', 'sv_darray_args1', 'sv_darray_args2', 'sv_darray_args2b', 'sv_darray_args3', 'sv_darray_args4', 'sv_queue_real', 'sv_queue_string', 'sv_queue_vec', # pullup/down with multiple terminals 'pr1787423', 'pr1787423b', 'pr2834340', 'pr2834340b', # Parallel path '=>' with multiple input terminals 'pr1877743', 'specify_01', # Parameter override without parens 'pr3194155', 'z1', 'z2', # Empty parameter override 'pr1716276', # Package scope event access 'sv_wildcard_import2', 'sv_wildcard_import3', # Packed dims support [] for [0:-1] just like unpacked dims 'display_bug', # `protect compiler directives 'pr478', # `suppress_faults compiler directives 'pr1467825', # generate begin/end was valid when generate was initially defined 'br988', 'pr2257003', 'pr2257003b', # Using %v with a variable 'pr923', # $itor(real) and $rtoi(self-determined integer) 'itor_rtoi', # $printtimescale() can be passed more than a module identifier 'pr1701855b', # Extra module instance parameters are a warning and then ignored 'param_test3', # Initialization can be used with non-ANSI port definitions 'pr2790236', # A foreach can have statement_or_null 'sf1289', # These are optional system tasks and functions and may not be supported 'countdrivers1', 'countdrivers2', 'countdrivers3', 'countdrivers4', 'countdrivers5', # Icarus checks that always blocks have delay constructs to prevent # infinite loops. For now exclude these. I would ideally like to make # these marked as fails for Icarus and and correctly parsed for others. 'always4A', 'always4B', 'always311A', 'always311B', 'always312A', 'always312B', 'always312C', 'always312D', 'always312E', 'always312F', 'always312G', 'always312H', 'always312I', 'always313A', 'always313B', 'always313C', 'always313D', 'always313E', 'always313F', 'always313G', 'always313H', 'always313J', 'always319A', 'always319B', 'always3110A', 'br991b', 'pr1862744b', # Icarus checks that the always_* processes do not contain delay # constructs and that the always_ff has a sensitivity list. These should # should fail in Icarus, but should parse correctly. 'always_comb_fail3', 'always_comb_fail4', 'always_comb_fail', 'always_ff_fail2', 'always_ff_fail3', 'always_ff_fail4', 'always_ff_fail', 'always_ff_no_sens', 'always_latch_fail3', 'always_latch_fail4', 'always_latch_fail', 'always_latch_no_sens', # '@ *' is valid and supported by commercial tools 'case3', 'wildsense', # The following tests need to be looked at and verified 'pr1723367', # scalar with vectored net 'undef', # undefined macro behaviour is ambiguous 'sformatf', # Too many arguments passed to $sformatf 'format', # Missing argument to $display # These tests use procedural continuous assigns with bit selects on the lhs, # which is not allowed according to the LRM. 'array_lval_select3a', 'assign32E', 'assign_deassign_pv', 'force_lval_part', 'force_release_reg_pv', 'pr1832097b', 'pr2943394', # These tests are marked 'designed to fail' but are actually valid. 'sv_port_default14', 'br995', 'br_gh306a', 'br_gh306b', 'case5synfail', 'casesynth8', 'dffsynth8', 'br1015a', 'br1027a', 'br1027c', 'br1027e', 'br_gh25a', 'br_gh25b', 'check_constant_3', 'function4', 'no_timescale_in_module', 'pr1704013', 'scope2b', 'event_array', # $dumpvars with bit selects, doesn't appear to be legal and commercial tools disallow 'array_word_check', 'dump_memword', # defparam targeting a localparam isn't allowed 'br_gh157', 'scoped_events', # Module ANSI ports are redeclared in body 'br_ml20150606', # This expects failure because of unsized literal in a concat, but pretty much # all tools allow this (usually with a warning) as an extension because tons of code # in the wild does it. 'indef_width_concat', # Primitive port connections cannot use the '.name()' syntax 'pr938b', 'udp_dff', # Icarus checks that final-blocks do not have non-blocking assignments but # a strict reading of IEEE 1800-2017, $9.2.3 does not require this, even # though the non-blocking assignment will have no effect. 'program3b', # A wire with 'real' type is not allowed (commercial tools disallow) 'br_gh156', 'br_gh556', # This test forgets to add parenthesis to a module instantiation. 'br_gh553', # Expects pass or failure for out-of-bounds access but most tools warn instead of # hard error and LRM specifies what the runtime behavior is. 'br_gh840a', 'br_gh840b', 'assign_op_oob', 'assign_op_real_array_oob', # Provides connection for null port, LRM is unclear but all commercial tools disallow this 'pr1723367', # Expects failure for using a slice in $readmemh but the LRM explicitly allows for this. # VCS fails but other tools allow. 'readmemh5', # Illegal; IEEE says parameters may be limited to 32 bits if no type is provided 'ilongint_test', # Expects failure but IEEE does not disallow zero size arrays (parameters may cause this) 'br_ml20181012d', # Test does not compile without __ICARUS__ 'implicit_cast12', 'implicit_cast13', # Illegal, f_ffffffff has too many digits for int 'sv_class8', # output directory doesn't exist 'writememb1', 'writememb2', 'writememh1', 'writememh2', # negative tests 'writememerror', 'uwire_fail', # Null object dereferenced 'br_gh104a', # Some tools error others warn, it's not clear in LRM what the requirements are 'br_gh230', # Zero sized constant is illegal, but some tools warn and ignore 'br_gh60a', # String type is not implicitly assignment compatible to a packed vector, but some allow 'br_ml20180227', # Negative test wrong, what is tested appears legal on other simulators and by IEEE 'comment1', # Checked values FAILED on multiple other simulators 'concat4', # Illegal, but some tooks just warn 'enum_test3', # Fails on others; does not appear to match IEEE's description of define identifiers 'escaped_macro_name', # Checked values FAILED on multiple other simulators 'func_init_var3', # Negative test that in some tools throws a warning rather than fatal error 'pr1938138', # Unclear, most tools hard error but for some tools allow 'pr2794144', # Modules ignored due to module ordering sv-test driver limitation 'br_gh104b', 'check_constant_2', 'def_nettype_none', 'implicitport2', 'implicitport3', 'implicitport6', 'mhead_task', 'pr1587634', 'pr1698659', 'pr2076425', 'pr2792883', 'shellho1', # needs data text file that this test harness doesn't enable finding 'pr2800985a', # primitive table rows are invalid, fails on multiple commercial tools 'pr3587570', # Compilation errors with other simulators 'pr1520314', # Synthesis one-hot assertion fails 'onehot', # Primitive connect to real 'br_gh1182', # Intentional assertion failures 'sv_deferred_assert1', 'sv_deferred_assert2', 'sv_deferred_assume1', 'sv_deferred_assume2', 'sv_immediate_assert', 'sv_immediate_assume', 'case_priority', 'case_unique', # IEEE 22.2 directives must be on same line 'br_gh782b', 'br_gh782c', 'br_gh782e', 'br_gh782f', # Requires iv-specific $abstime/$is_signed 'pr2590274a', 'pr2590274b', 'pr2590274c', 'struct_member_signed', 'struct_signed', # '%d' with string argument 'sv_cast_typedef', # IEEE does not disallow void' of a void function/task, 4 of 5 simulators take it # (Useful in macros that void-call a passed func/task name without knowing dtype) 'sv_void_cast_fail1', 'sv_void_cast_fail2', # Declares ports in the module body without declaring them in the header. # The LRM does not allow this. All tools tried fail on this. 'module_output_port_sv_var2', 'module_output_port_var2', # References a compilation unit-level item from within a package, which is not allowed 'sv_ps_type_class1', # These need to be run in a Verilog-specific mode once sv-tests has one, since they expect # failure even though SystemVerilog allows them. 'br_gh956a', 'module_inout_port_type', 'module_input_port_list_def', 'module_input_port_type', 'parameter_in_generate1', 'parameter_no_default', 'parameter_omit1', 'parameter_omit2', 'parameter_omit3', 'unnamed_block_var_decl', 'unnamed_fork_var_decl', # References a non-existent module 'macro_args', # Nested block comments are disallowed currently in SystemVerilog, however # all simulators take this, so allowing it. 'macro_comment_multiline', # It's not illegal to declare a range on a non-ANSI port declaration even # if the 'direction' declaration for the port does not have it. LRM does not # specify such a restriction, all tools support it. 'module_nonansi_vec_fail2', 'task_nonansi_vec_fail3', # Wrapper script doesn't pass parameter to non-Icarus tools, so test fails 'parameter_no_default_toplvl', # Wrapper script doean't give a top-module and fails as `celldefine's are # assumed part of libraries and not automatically processed otherwise 'specify1', # Declares "x" twice (Unlike modules, task/func 'dtype x' # must be after 'input x'. All non-Icarus simulators agree. 'task_nonansi_enum2', 'task_nonansi_int2', 'task_nonansi_integer2', 'task_nonansi_parray2', 'task_nonansi_real2', 'task_nonansi_time2', 'task_nonansi_vec2', # Test should expect fail: IEEE does not allow .* to connect to empty ports 'br_gh530', # The LRM does not seem to support the idea of leaking enum members out of a surrounding # struct scope, though some tools support it. VCS does not. 'enum_in_struct', # All tools allow this. The LRM contains some conflicting wording on this, but shows # an example that implies it should be allowed. 'sv_export_fail1', # Redefining the same UDP is above what IEEE specifies; it's an error on some tools, # warning on others (which pick first or last defined), and ignored on yet others. 'br_gh1175f', # These appear to be mismarked, should be expect-fail, referencing an implicit # net before it's declared. All commercial tools fail on this. 'pr1909940', 'pr1909940b', ] ivtest_extra_args = { # Long running 'comp1000': ':timeout: 360', 'comp1001': ':timeout: 360', # Promote warning to error to match iverilog 'porttest3': ':runner_verilator_flags: -Werror-ASSIGNIN', 'pow_ca_signed': ':runner_verilator_flags: --converge-limit 1000000', 'pow_ca_unsigned': ':runner_verilator_flags: --converge-limit 1000000', } ivtest_dir = os.path.abspath( os.path.join(third_party_dir, "tools", "icarus", "ivtest")) ivtest_list_exclude = set( map(lambda x: os.path.join(ivtest_dir, x), ivtest_list_exclude)) ivtest_lists = sorted( list( set(glob.glob(os.path.join(ivtest_dir, '*.list'))) - ivtest_list_exclude)) tests = [] skip = False incdirs = [ivtest_dir, os.path.join(ivtest_dir, 'ivltests')] for l in ivtest_lists: list_filename = re.match(r'.*/([^/]*)\.list', l).group(1) with open(l, 'r') as f: for line in f: if skip: skip = False continue # remove comments line = re.sub(r'#.*?\n', '', line) # skip multiline definitions if re.search(r'\\\n', line): skip = True continue line = line.split() if len(line) < 3: continue # skip Not Implemented tests if re.match('NI', line[1]): continue name = line[0] path = os.path.join(ivtest_dir, line[2], line[0] + '.v') should_fail_because = '' # sanitize name name = re.sub(r'\W', '', name) if name in ivtest_file_exclude: continue for t in type_should_fail: if re.match(t, line[1]): should_fail_because = ':should_fail_because: this test was imported from ivtest and is designed to fail' extra_args = '' if name in ivtest_extra_args: extra_args += ivtest_extra_args[name] tests.append( ( list_filename + '_' + name + '_iv', path, should_fail_because, ' '.join(incdirs), extra_args)) test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) for test in tests: test_file = os.path.join(test_dir, test[0] + '.sv') with open(test_file, "w") as f: f.write(templ.format(*test)) ================================================ FILE: generators/path_generator ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys import json import glob templ = """/* :name: {name} :description: Tests imported from {project} :files: {files} :incdirs: {incdirs} :tags: {project} {extra_tags} */ {extra_code} """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the TESTS_DIR and CONF_DIR variables first") sys.exit(1) name = '' project = '' paths = [[]] matches = [] for cfg in glob.glob(os.path.join(conf_dir, 'generators', 'meta-path', '*.json')): with open(cfg, 'r') as jf: global_extra_tags = [] extra_code = "" data = json.load(jf) name = data['name'] project = data['project'] if 'should_fail_because' in data: global_extra_tags.append( f":should_fail_because: {data['should_fail_because']}") paths = data['paths'] matches = data['matches'] blacklist = data.get('blacklist', ['']) commons = data.get('commons', []) incdirs = data.get('incdirs', []) timeouts = data.get('timeouts', {}) test_type = data.get('type', None) results_group = data.get('results_group', None) if test_type is not None: global_extra_tags.append(f":type: {test_type}") if results_group is not None: global_extra_tags.append(f":results_group: {results_group}") if 'fake_topmodule' in data: global_extra_tags.append(":top_module: top") extra_code = "module top; endmodule" test_dir = os.path.join(tests_dir, 'generated', project) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) for path in paths: for match in matches: search_path = os.path.abspath( os.path.join(third_party_dir, *path, match)) for f in glob.glob(search_path): # make a copy of extra tags for a particular test extra_tags = global_extra_tags[:] basename = os.path.basename(f) if blacklist.count(basename) > 0: print("Skipping blacklisted file: {}".format(f)) continue fname = name + '_' + os.path.basename(os.path.splitext(f)[0]) # check if this file is in folder inside test directory folder_path = f.replace( os.path.commonprefix([f, search_path]), "") folder_path = os.path.dirname(folder_path) folder_path = folder_path.replace("/", "_") if folder_path != "": fname = folder_path + "_" + fname test_file = os.path.join(test_dir, fname + '.sv') incs = os.path.dirname(f) for common in commons: f = os.path.abspath( os.path.join(third_party_dir, common)) + " " + f # add the test snippet do the beginning of the list f = os.path.abspath(test_file) + " " + f for incdir in incdirs: incs = os.path.abspath( os.path.join(third_party_dir, incdir)) + " " + incs if basename in timeouts: extra_tags.append(f":timeout: {timeouts[basename]}") extra_tags = "\n".join(extra_tags) with open(test_file, "w") as sv: sv.write( templ.format( project=project, files=f, name=fname, incdirs=incs, extra_tags=extra_tags, extra_code=extra_code)) ================================================ FILE: generators/rggen ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys import glob import re templ = """/* :name: RgGen :description: Full RgGen test :files: {0} :tags: RgGen :top_module: rggen :results_group: cores :timeout: 100 */ """ wrapper_tmpl = """ module rggen; import rggen_rtl_pkg::*; logic clk; logic rst_n; rggen_apb_if #(16, 32) apb_if[2](); logic [3:0] register_0_bit_field_0; logic [3:0] register_0_bit_field_1; logic register_0_bit_field_2; logic [1:0] register_0_bit_field_3; logic [1:0] register_0_bit_field_4; logic [1:0] register_0_bit_field_5; logic [1:0] register_0_bit_field_6; logic register_1; logic [3:0] register_2_bit_field_0; logic register_2_bit_field_2_valid; logic [1:0][3:0] register_2_bit_field_2; logic [1:0][3:0] register_2_bit_field_3; logic [3:0] register_3_bit_field_0; logic [3:0] register_3_bit_field_1; logic [3:0] register_3_bit_field_2_trigger; logic [3:0] register_3_bit_field_3_trigger; logic [3:0] register_4_bit_field_0_set; logic [3:0] register_4_bit_field_0; logic [3:0] register_4_bit_field_1_set; logic [3:0] register_4_bit_field_1; logic [3:0] register_4_bit_field_1_unmasked; logic [3:0] register_4_bit_field_3_clear; logic [3:0] register_4_bit_field_3; logic register_5_bit_field_0_clear; logic [1:0] register_5_bit_field_0; logic [1:0] register_5_bit_field_1; logic register_5_bit_field_2_set; logic [1:0] register_5_bit_field_2; logic [1:0] register_5_bit_field_3; logic register_5_bit_field_4_valid; logic [1:0] register_5_bit_field_4[2]; logic [1:0] register_5_bit_field_5[2]; logic register_5_bit_field_6_enable; logic [1:0] register_5_bit_field_6; logic [1:0] register_5_bit_field_7; logic [1:0] register_5_bit_field_8; logic register_5_bit_field_9_lock; logic [1:0] register_5_bit_field_9; logic [1:0] register_5_bit_field_10; logic [1:0] register_5_bit_field_11; logic [3:0] register_6_bit_field_0_set; logic [3:0] register_6_bit_field_0; logic [3:0] register_6_bit_field_1_set; logic [3:0] register_6_bit_field_1; logic [3:0] register_6_bit_field_1_unmasked; logic [3:0] register_6_bit_field_3_set; logic [3:0] register_6_bit_field_3; logic [3:0] register_6_bit_field_4_set; logic [3:0] register_6_bit_field_4; logic [3:0] register_6_bit_field_4_unmasked; logic [3:0] register_6_bit_field_6_clear; logic [3:0] register_6_bit_field_6; logic [3:0] register_6_bit_field_7_clear; logic [3:0] register_6_bit_field_7; logic [3:0] register_6_bit_field_8; logic [3:0] register_6_bit_field_9; logic [3:0] register_7_bit_field_0; logic [3:0] register_7_bit_field_1; logic [3:0] register_7_bit_field_2; logic [3:0] register_7_bit_field_3; logic [3:0] register_8_bit_field_0_set; logic [3:0] register_8_bit_field_0; logic [3:0] register_8_bit_field_1_clear; logic [3:0] register_8_bit_field_1; logic [3:0] register_8_bit_field_2_set; logic [3:0] register_8_bit_field_2; logic [3:0] register_8_bit_field_3_clear; logic [3:0] register_8_bit_field_3; logic [3:0] register_8_bit_field_4; logic [3:0] register_8_bit_field_5; logic [1:0] register_9_bit_field_0; logic [1:0] register_9_bit_field_1; logic [1:0] register_9_bit_field_2; logic [1:0][1:0] register_9_bit_field_3; logic [1:0] register_9_bit_field_4; logic [1:0] register_9_bit_field_5; logic [3:0][3:0][1:0] register_10_bit_field_0; logic [3:0][3:0][1:0] register_10_bit_field_1; logic [3:0][3:0][1:0] register_10_bit_field_2; logic [1:0][3:0][3:0][7:0] register_11_bit_field_0; logic [1:0][3:0][3:0][7:0] register_11_bit_field_1; logic register_12_bit_field_0; logic register_12_bit_field_1; logic [1:0] register_13_bit_field_0; logic [1:0] register_13_bit_field_1; logic [1:0] register_13_bit_field_2; logic [1:0] register_13_bit_field_3; logic register_13_bit_field_3_write_trigger; logic register_13_bit_field_3_read_trigger; logic [1:0] register_13_bit_field_4; logic [1:0] register_13_bit_field_5; logic [1:0] register_13_bit_field_6; logic [1:0] register_13_bit_field_6_hw_clear; logic [1:0] register_13_bit_field_7; logic [1:0] register_13_bit_field_7_hw_set; logic [1:0] register_13_bit_field_8; logic register_13_bit_field_8_hw_write_enable; logic [1:0] register_13_bit_field_8_hw_write_data; logic register_15_bit_field_0; logic register_16_bit_field_0; logic [15:0] register_17_bit_field_0; rggen_bus_if #(8, 32) register_19_bus_if(); always_comb begin register_2_bit_field_0 = register_0_bit_field_0; register_2_bit_field_2_valid = register_3_bit_field_3_trigger[0]; register_2_bit_field_2[0] = register_0_bit_field_0; register_2_bit_field_3[0] = register_0_bit_field_0; register_4_bit_field_0_set = register_3_bit_field_3_trigger; register_4_bit_field_1_set = register_3_bit_field_3_trigger; register_4_bit_field_3_clear = register_3_bit_field_2_trigger; register_5_bit_field_0_clear = register_3_bit_field_2_trigger[0]; register_5_bit_field_2_set = register_3_bit_field_2_trigger[0]; register_5_bit_field_4_valid = register_3_bit_field_3_trigger[0]; register_5_bit_field_4[0] = register_0_bit_field_0[1:0]; register_5_bit_field_5[0] = register_0_bit_field_0[1:0]; register_5_bit_field_6_enable = register_0_bit_field_2; register_5_bit_field_9_lock = register_0_bit_field_2; register_6_bit_field_0_set = register_3_bit_field_3_trigger; register_6_bit_field_1_set = register_3_bit_field_3_trigger; register_6_bit_field_3_set = register_3_bit_field_3_trigger; register_6_bit_field_4_set = register_3_bit_field_3_trigger; register_6_bit_field_6_clear = register_3_bit_field_2_trigger; register_6_bit_field_7_clear = register_3_bit_field_2_trigger; register_8_bit_field_0_set = register_3_bit_field_3_trigger; register_8_bit_field_1_clear = register_3_bit_field_2_trigger; register_8_bit_field_2_set = register_3_bit_field_3_trigger; register_8_bit_field_3_clear = register_3_bit_field_2_trigger; register_9_bit_field_1 = register_0_bit_field_0[1:0]; register_9_bit_field_3[1] = register_0_bit_field_0[1:0]; register_9_bit_field_4 = register_0_bit_field_0[1:0]; register_9_bit_field_5 = register_0_bit_field_0[1:0]; register_13_bit_field_1 = register_13_bit_field_0; register_13_bit_field_6_hw_clear = register_13_bit_field_3_read_trigger; register_13_bit_field_7_hw_set = register_13_bit_field_3_read_trigger; register_13_bit_field_8_hw_write_enable = register_13_bit_field_3_write_trigger; register_13_bit_field_8_hw_write_data = register_13_bit_field_3; register_15_bit_field_0 = register_0_bit_field_0[0]; end block_0 #( .ADDRESS_WIDTH (16 ), .PRE_DECODE (1'b1 ), .INSERT_SLICER (1'b1 ), .DEFAULT_READ_DATA (32'hDEAD_BEAF ), .REGISTER_10_BIT_FIELD_1_INITIAL_VALUE ({2'h3, 2'h2, 2'h1, 2'h0} ) ) u_block_0 ( .i_clk (clk ), .i_rst_n (rst_n ), .apb_if (apb_if[0] ), .o_register_0_bit_field_0 (register_0_bit_field_0 ), .o_register_0_bit_field_1 (register_0_bit_field_1 ), .o_register_0_bit_field_2 (register_0_bit_field_2 ), .o_register_0_bit_field_3 (register_0_bit_field_3 ), .o_register_0_bit_field_4 (register_0_bit_field_4 ), .o_register_0_bit_field_5 (register_0_bit_field_5 ), .o_register_0_bit_field_6 (register_0_bit_field_6 ), .i_register_0_bit_field_6 (register_0_bit_field_6 ), .o_register_1 (register_1 ), .i_register_2_bit_field_0 (register_2_bit_field_0 ), .i_register_2_bit_field_2_valid (register_2_bit_field_2_valid ), .i_register_2_bit_field_2 (register_2_bit_field_2[0] ), .o_register_2_bit_field_2 (register_2_bit_field_2[1] ), .i_register_2_bit_field_3 (register_2_bit_field_3[0] ), .o_register_2_bit_field_3 (register_2_bit_field_3[1] ), .o_register_3_bit_field_0 (register_3_bit_field_0 ), .o_register_3_bit_field_1 (register_3_bit_field_1 ), .o_register_3_bit_field_2_trigger (register_3_bit_field_2_trigger ), .o_register_3_bit_field_3_trigger (register_3_bit_field_3_trigger ), .i_register_4_bit_field_0_set (register_4_bit_field_0_set ), .o_register_4_bit_field_0 (register_4_bit_field_0 ), .i_register_4_bit_field_1_set (register_4_bit_field_1_set ), .o_register_4_bit_field_1 (register_4_bit_field_1 ), .o_register_4_bit_field_1_unmasked (register_4_bit_field_1_unmasked ), .i_register_4_bit_field_3_clear (register_4_bit_field_3_clear ), .o_register_4_bit_field_3 (register_4_bit_field_3 ), .i_register_5_bit_field_0_clear (register_5_bit_field_0_clear ), .o_register_5_bit_field_0 (register_5_bit_field_0 ), .o_register_5_bit_field_1 (register_5_bit_field_1 ), .i_register_5_bit_field_2_set (register_5_bit_field_2_set ), .o_register_5_bit_field_2 (register_5_bit_field_2 ), .o_register_5_bit_field_3 (register_5_bit_field_3 ), .i_register_5_bit_field_4_valid (register_5_bit_field_4_valid ), .i_register_5_bit_field_4 (register_5_bit_field_4[0] ), .o_register_5_bit_field_4 (register_5_bit_field_4[1] ), .i_register_5_bit_field_5 (register_5_bit_field_5[0] ), .o_register_5_bit_field_5 (register_5_bit_field_5[1] ), .i_register_5_bit_field_6_enable (register_5_bit_field_6_enable ), .o_register_5_bit_field_6 (register_5_bit_field_6 ), .o_register_5_bit_field_7 (register_5_bit_field_7 ), .o_register_5_bit_field_8 (register_5_bit_field_8 ), .i_register_5_bit_field_9_lock (register_5_bit_field_9_lock ), .o_register_5_bit_field_9 (register_5_bit_field_9 ), .o_register_5_bit_field_10 (register_5_bit_field_10 ), .o_register_5_bit_field_11 (register_5_bit_field_11 ), .i_register_6_bit_field_0_set (register_6_bit_field_0_set ), .o_register_6_bit_field_0 (register_6_bit_field_0 ), .i_register_6_bit_field_1_set (register_6_bit_field_1_set ), .o_register_6_bit_field_1 (register_6_bit_field_1 ), .o_register_6_bit_field_1_unmasked (register_6_bit_field_1_unmasked ), .i_register_6_bit_field_3_set (register_6_bit_field_3_set ), .o_register_6_bit_field_3 (register_6_bit_field_3 ), .i_register_6_bit_field_4_set (register_6_bit_field_4_set ), .o_register_6_bit_field_4 (register_6_bit_field_4 ), .o_register_6_bit_field_4_unmasked (register_6_bit_field_4_unmasked ), .i_register_6_bit_field_6_clear (register_6_bit_field_6_clear ), .o_register_6_bit_field_6 (register_6_bit_field_6 ), .i_register_6_bit_field_7_clear (register_6_bit_field_7_clear ), .o_register_6_bit_field_7 (register_6_bit_field_7 ), .o_register_6_bit_field_8 (register_6_bit_field_8 ), .o_register_6_bit_field_9 (register_6_bit_field_9 ), .o_register_7_bit_field_0 (register_7_bit_field_0 ), .o_register_7_bit_field_1 (register_7_bit_field_1 ), .o_register_7_bit_field_2 (register_7_bit_field_2 ), .o_register_7_bit_field_3 (register_7_bit_field_3 ), .i_register_8_bit_field_0_set (register_8_bit_field_0_set ), .o_register_8_bit_field_0 (register_8_bit_field_0 ), .i_register_8_bit_field_1_clear (register_8_bit_field_1_clear ), .o_register_8_bit_field_1 (register_8_bit_field_1 ), .i_register_8_bit_field_2_set (register_8_bit_field_2_set ), .o_register_8_bit_field_2 (register_8_bit_field_2 ), .i_register_8_bit_field_3_clear (register_8_bit_field_3_clear ), .o_register_8_bit_field_3 (register_8_bit_field_3 ), .o_register_8_bit_field_4 (register_8_bit_field_4 ), .o_register_8_bit_field_5 (register_8_bit_field_5 ), .o_register_9_bit_field_0 (register_9_bit_field_0 ), .o_register_9_bit_field_0_write_trigger (), .o_register_9_bit_field_0_read_trigger (), .i_register_9_bit_field_1 (register_9_bit_field_1 ), .o_register_9_bit_field_1_read_trigger (), .o_register_9_bit_field_2 (register_9_bit_field_2 ), .o_register_9_bit_field_2_write_trigger (), .o_register_9_bit_field_3 (register_9_bit_field_3[0] ), .i_register_9_bit_field_3 (register_9_bit_field_3[1] ), .o_register_9_bit_field_3_write_trigger (), .o_register_9_bit_field_3_read_trigger (), .i_register_9_bit_field_4 (register_9_bit_field_4 ), .o_register_9_bit_field_4_trigger (), .i_register_9_bit_field_5 (register_9_bit_field_5 ), .o_register_9_bit_field_5_trigger (), .o_register_10_bit_field_0 (register_10_bit_field_0 ), .o_register_10_bit_field_1 (register_10_bit_field_1 ), .o_register_10_bit_field_2 (register_10_bit_field_2 ), .o_register_11_bit_field_0 (register_11_bit_field_0 ), .o_register_11_bit_field_1 (register_11_bit_field_1 ), .o_register_12_bit_field_0 (register_12_bit_field_0 ), .o_register_12_bit_field_1 (register_12_bit_field_1 ), .o_register_13_bit_field_0 (register_13_bit_field_0 ), .i_register_13_bit_field_1 (register_13_bit_field_1 ), .o_register_13_bit_field_2 (register_13_bit_field_2 ), .o_register_13_bit_field_3 (register_13_bit_field_3 ), .o_register_13_bit_field_3_write_trigger (register_13_bit_field_3_write_trigger ), .o_register_13_bit_field_3_read_trigger (register_13_bit_field_3_read_trigger ), .o_register_13_bit_field_4 (register_13_bit_field_4 ), .o_register_13_bit_field_5 (register_13_bit_field_5 ), .o_register_13_bit_field_6 (register_13_bit_field_6 ), .i_register_13_bit_field_6_hw_clear (register_13_bit_field_6_hw_clear ), .o_register_13_bit_field_7 (register_13_bit_field_7 ), .i_register_13_bit_field_7_hw_set (register_13_bit_field_7_hw_set ), .o_register_13_bit_field_8 (register_13_bit_field_8 ), .i_register_13_bit_field_8_hw_write_enable (register_13_bit_field_8_hw_write_enable ), .i_register_13_bit_field_8_hw_write_data (register_13_bit_field_8_hw_write_data ), .i_register_14_bit_field_0_up (register_0_bit_field_0[0] ), .i_register_14_bit_field_0_down (register_0_bit_field_1[0] ), .i_register_14_bit_field_0_clear (register_3_bit_field_3_trigger[0] ), .o_register_14_bit_field_0 (register_14_bit_field_0 ), .i_register_14_bit_field_1_up (register_0_bit_field_0[0] ), .i_register_14_bit_field_1_down (register_0_bit_field_1[0] ), .i_register_15_bit_field_0 (register_15_bit_field_0 ), .o_register_16_bit_field_0 (register_16_bit_field_0 ), .o_register_17_bit_field_0 (register_17_bit_field_0 ), .register_19_bus_if (register_19_bus_if ) ); rggen_apb_bridge u_bridge ( .i_clk (clk ), .i_rst_n (rst_n ), .bus_if (register_19_bus_if ), .apb_if (apb_if[1] ) ); block_1 u_block_1 ( .i_clk (clk ), .i_rst_n (rst_n ), .apb_if (apb_if[1] ), .o_register_file_0_register_0_bit_field_0 (), .o_register_file_0_register_1_bit_field_0 (), .o_register_file_1_register_0_bit_field_0 (), .o_register_file_1_register_1_bit_field_0 (), .o_register_file_2_register_file_0_register_0_bit_field_0 (), .o_register_file_2_register_file_0_register_0_bit_field_1 (), .o_register_file_2_register_file_0_register_0_bit_field_2 (), .o_register_file_2_register_file_0_register_1_bit_field_0 () ); endmodule """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) rggen_sample_path = os.path.abspath( os.path.join(third_party_dir, "cores", "rggen-sample")) rggen_sv_rtl_path = os.path.abspath( os.path.join(third_party_dir, "cores", "rggen-sv-rtl")) sources = '' def is_valid_rggen_file(line): if line.startswith("-f"): return False elif re.search(r'axi|wishbone', line) is not None: return False else: return True with open(os.path.join(rggen_sv_rtl_path, "compile.f"), "r") as f: for line in f.readlines(): if is_valid_rggen_file(line): line = line.strip() line = line.replace("${RGGEN_SV_RTL_ROOT}", rggen_sv_rtl_path) sources += line + " " sources += os.path.join(rggen_sample_path, "block_0.sv") + " " sources += os.path.join(rggen_sample_path, "block_1.sv") + " " test_file = os.path.abspath(os.path.join(test_dir, "rggen.sv")) sources += test_file with open(test_file, "w") as f: f.write(templ.format(sources)) f.write(wrapper_tmpl) ================================================ FILE: generators/rsd ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys import glob import re templ = """/* :name: rsd :description: Full RSD core test :files: {0} :incdirs: {1} :tags: rsd :top_module: Core :results_group: cores :timeout: 100 */ """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) rsd_path = os.path.abspath( os.path.join(third_party_dir, "cores", "rsd", "Processor", "Src")) rsd_core_make = os.path.join(rsd_path, "Makefiles", "CoreSources.inc.mk") test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) test_file = os.path.join(test_dir, "rsd.sv") sources = os.path.abspath(test_file) + ' ' incdirs = os.path.join(rsd_path, "") + ' ' with open(rsd_core_make, "r") as f: in_source_list = False for line in f.readlines(): line = re.sub(r"#.+[\n\r]$", "", line) # Remove comments # Find lines starting with "TYPES|CORE_MODULES=" and not ending with "\". m = re.search(r"^(TYPES|CORE_MODULES)[\s]*=(.+)$", line) if m: line = m.group(2) # Remove TYPES|CORE_MODULES= in_source_list = True if in_source_list: # Find the end of source list m = re.search(r"\\[\n\r]*$", line) if not m: in_source_list = False # Remove backslash and spaces line = re.sub(r"\\[\n\r]*$", "", line) line = line.strip() if (line != ""): for i in line.split(r"\s+"): sources += os.path.join(rsd_path, i) + ' ' with open(test_file, "w") as f: f.write(templ.format(sources, incdirs)) f.write("`define RSD_SYNTHESIS\n") f.write("`define RSD_SYNTHESIS_DESIGN_COMPILER\n") f.write("`define RSD_MARCH_FP_PIPE\n") ================================================ FILE: generators/scr1 ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys templ = """/* :name: scr1 :description: Full scr1 core test :files: {0} :incdirs: {1} :tags: scr1 :top_module: scr1_top_tb_axi :results_group: cores :timeout: 100 */ """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) scr1_path = os.path.abspath( os.path.join(third_party_dir, "cores", "scr1", "src")) flist = ['core.files', 'axi_top.files', 'axi_tb.files'] sources = '' incdirs = '' files = [] includes = ['includes', 'tb'] for fname in flist: with open(os.path.join(scr1_path, fname)) as f: for line in f: files += [line.strip()] for sv in files: sources += os.path.join(scr1_path, sv) + ' ' for inc in includes: incdirs += os.path.join(scr1_path, inc) + ' ' test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) test_file = os.path.join(test_dir, "scr1.sv") with open(test_file, "w") as f: f.write(templ.format(sources, incdirs)) ================================================ FILE: generators/template_generator ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys import json import glob import itertools try: tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the TESTS_DIR and CONF_DIR variables first") sys.exit(1) name = '' fname = '' templ = '' vals = [] for cfg in glob.glob(os.path.join(conf_dir, 'generators', 'templates', '*.json')): with open(cfg, 'r') as jf: data = json.load(jf) name = data['name'] fname = data['filename'] if 'template' in data.keys(): templ = '\n'.join(data['template']) elif 'template_file' in data.keys(): try: with open(os.path.join(conf_dir, 'generators', 'templates', data['template_file']), 'r') as t: templ = t.read() except FileNotFoundError: print("Template file " + data['template_file'] + " not found") sys.exit(1) else: print("No template or template_file specified ") sys.exit(1) vals = data['values'] if data.get('cartesian_product', False): prod = list(itertools.product(*vals)) vals = [x[0] + x[1] for x in prod] test_dir = os.path.join(tests_dir, 'generated', name) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) for idx, val in enumerate(vals): test_file = os.path.join(test_dir, fname.format(*val, idx)) with open(test_file, "w") as wf: wf.write(templ.format(*val, idx)) ================================================ FILE: generators/tnoc ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys import glob templ = """/* :name: TNoC :description: Full TNoC core test :files: {0} :tags: TNoC :top_module: tnoc :results_group: cores :timeout: 100 */ """ wrapper_tmpl = """ module tnoc ( input var i_clk, input var i_rst_n ); import tnoc_pkg::*; localparam tnoc_packet_config PACKET_CONFIG = '{ size_x: 3, size_y: 3, virtual_channels: 2, tags: 32, address_width: 64, data_width: 64, max_data_width: 64, max_byte_length: 32 * (64 / 8) }; tnoc_types #(PACKET_CONFIG) types(); tnoc_flit_if #(PACKET_CONFIG) receiver_if[9](types); tnoc_flit_if #(PACKET_CONFIG) sender_if[9](types); tnoc_fabric #(PACKET_CONFIG) u_fabric (.*); endmodule """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) tnoc_path = os.path.abspath(os.path.join(third_party_dir, "cores", "tnoc")) tbcm_path = os.path.join(tnoc_path, "rtl", "bcm") tnoc_file_lists = [ os.path.join(tbcm_path, "compile.f"), os.path.join(tnoc_path, "rtl", "common", "compile.f"), os.path.join(tnoc_path, "rtl", "router", "compile.f"), os.path.join(tnoc_path, "rtl", "fabric", "compile.f") ] sources = '' for file_list in tnoc_file_lists: with open(file_list, "r") as f: for line in f.readlines(): sources += line.strip() + " " sources = sources.replace("${TBCM_HOME}", tbcm_path) sources = sources.replace("${TNOC_HOME}", tnoc_path) test_file = os.path.abspath(os.path.join(test_dir, "tnoc.sv")) sources += test_file with open(test_file, "w") as f: f.write(templ.format(sources)) f.write(wrapper_tmpl) ================================================ FILE: generators/veer-config ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys import subprocess variants = [ { "test_type": "sim", "name": "veer-el2", "description": "Full VeeR EL2 core test", "top_module": "tb_top", "tags": "veer-el2", "compatible-runners": "verilator slang", "type": "parsing elaboration simulation_without_run", }, { "test_type": "synth", "name": "veer-el2", "description": "Full VeeR EL2 core test", "top_module": "veer-el2_wrapper", "tags": "veer-el2", "compatible-runners": "yosys-synlig yosys yosys-sv zachjs-sv2v icarus moore moore-parse odin sv-parser tree-sitter-verilog verible verible_extractor Surelog slang-parse", "type": "parsing elaboration", }, ] templ = """/* :name: {0} :description: {1} :files: {2} :incdirs: {3} :top_module: {4} :tags: {5} :timeout: 1000 :results_group: cores :compatible-runners: {6} :type: {7} {8} */ """ try: tests_dir = os.environ['TESTS_DIR'] third_party_dir = os.environ['THIRD_PARTY_DIR'] except KeyError: print("Export the TESTS_DIR and THIRD_PARTY_DIR variables first") print(os.environ) sys.exit(1) for v in variants: test_type = v["test_type"] name = v["name"] description = v["description"] top_module = v["top_module"] tags = v["tags"] compatible_runners = v["compatible-runners"] type = v["type"] include_dir = os.path.abspath( os.path.join(third_party_dir, "cores", name, "design", "include")) testbench_dir = os.path.abspath( os.path.join(third_party_dir, "cores", name, "testbench")) build_dir = os.path.abspath( os.path.join( tests_dir, "generated", "veer-config", name + "_" + test_type)) os.environ["BUILD_PATH"] = build_dir os.makedirs(build_dir, exist_ok=True) # Generate VeeR config headers veer_config = os.path.join( third_party_dir, "cores", name, "configs", "veer.config") ret = subprocess.run([veer_config], capture_output=True) if ret.returncode != 0: print(ret.stderr) print("VeeR configuration failed!") exit(ret.returncode) sources = "" # Insert common configuration headers before common VeeR sources common_defines = os.path.abspath( os.path.join(build_dir, "common_defines.vh")) el2_pdef = os.path.abspath(os.path.join(build_dir, "el2_pdef.vh")) sources += common_defines + " " + el2_pdef + " " # Setup common VeeR sources for (dirpath, dirnames, filenames) in os.walk(os.path.join(third_party_dir, "cores", name, "design")): if dirpath.endswith("include"): continue for f in filenames: if f.endswith(("sv", "v")): sources += os.path.abspath(os.path.join(dirpath, f)) + " " # Setup simulation specific sources and verilator args incdirs = build_dir + " " + include_dir extra_args = "" if test_type == "sim": incdirs += " " + testbench_dir for (dirpath, dirnames, filenames) in os.walk(os.path.join(third_party_dir, "cores", name, "testbench")): if 'uvm' in dirnames: # Skip uvm dir as it uses a custom Makefile dirnames.remove('uvm') for f in filenames: if 'axi_crossbar_wrap_2x1' in f: # Skip this file as it's unused without a specific define # and contains invalid syntax that can cause tools to fail continue if f.endswith(("sv", "v")): sources += os.path.abspath(os.path.join(dirpath, f)) + " " extra_args += ":runner_verilator_flags:" extra_args += " -CFLAGS -I" + build_dir extra_args += " -CFLAGS -I" + include_dir extra_args += " -CFLAGS -I" + testbench_dir extra_args += " -Wno-WIDTH" with open(common_defines, 'a') as cdf: cdf.write("`undef RV_ASSERT_ON") # Insert VeeR includes before other sources for (dirpath, dirnames, filenames) in os.walk(os.path.join(third_party_dir, "cores", name, "design", "include")): for f in filenames: if f.endswith(("sv", "v")): sources = os.path.abspath( os.path.join(dirpath, f)) + " " + sources # Write generated test to a file test_file = os.path.join(build_dir, name + "_" + test_type + ".sv") with open(test_file, "w") as tf: tf.write( templ.format( name, description, sources, incdirs, top_module, tags, compatible_runners, type, extra_args)) ================================================ FILE: generators/yosys_hana ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys import glob templ = """/* :name: {1} :description: Tests imported from yosys :files: {0} :results_group: imported :tags: yosys */ """ try: third_party_dir = os.environ['THIRD_PARTY_DIR'] tests_dir = os.environ['TESTS_DIR'] conf_dir = os.environ['CONF_DIR'] except KeyError: print("Export the THIRD_PARTY_DIR, TESTS_DIR and CONF_DIR variables first") sys.exit(1) try: tests_subdir = sys.argv[1] except IndexError: print("Usage: ./generator ") sys.exit(1) yosys_path = os.path.abspath(os.path.join(third_party_dir, "tools", "yosys")) hana_vlib = os.path.join(yosys_path, 'tests', 'hana', 'hana_vlib.v') test_dir = os.path.join(tests_dir, 'generated', tests_subdir) if not os.path.isdir(test_dir): os.makedirs(test_dir, exist_ok=True) for f in glob.glob(os.path.join(yosys_path, 'tests', 'hana', 'test*.v')): # test_parser has invalid syntax if 'test_parser.v' in f: continue fname = 'hana_' + os.path.basename(os.path.splitext(f)[0]) test_file = os.path.join(test_dir, fname + '.sv') with open(test_file, "w") as sv: sv.write(templ.format(f + ' ' + hana_vlib, fname)) ================================================ FILE: tests/README.md ================================================ # Tests This directory contains various tests. The tests are divided into various directories. ## Chapter tests The purpose of these tests is to verify individual features of each LRM chapter (and subchapters). They are minimal by design and when possible, test an isolated SystemVerilog construct. ## Generated tests Some of the tests are not stored directly in the repositories, but dynamically generated using various scripts. The `make generate` target runs all the generators. It creates a `generated` directory alongside the directories for each chapter and puts the generated test cases inside it. The generators are stored in the [generators](https://github.com/SymbiFlow/sv-tests/tree/master/generators) directory. The configuration for generators is stored in the [conf/generators](https://github.com/SymbiFlow/sv-tests/tree/master/conf/generators) directory. There are various types of generators. Some generate fairly simple tests, but does so in a bulk to generate multiple similar tests. An example of this would be the [template generator](https://github.com/SymbiFlow/sv-tests/blob/master/generators/template_generator). It has a multitude of various configs, one interesting example would be the [logical operators](https://github.com/SymbiFlow/sv-tests/blob/master/conf/generators/templates/logical.json) tests. Some generators generate more sophisticated test cases. These can for example be tests of full blown soft cores. An example of this would be the [BlackParrot](https://github.com/SymbiFlow/sv-tests/blob/master/generators/black-parrot) generator. It generates a wrapper which makes it possible to use BlackParrot as a test. ## UVM tests The repository contains multiple tests dedicated to verifying UVM support of various tools. The source code of UVM is stored in the [third party](https://github.com/SymbiFlow/sv-tests/tree/master/third_party/tests) directory. The tests that want to include it need to include the `uvm` tag on the list of their tags. The tests that use UVM are stored in various places, for example: * Multiple tests are stored in the [testbenches](https://github.com/SymbiFlow/sv-tests/tree/master/tests/testbenches) directory. * Some UVM tests are stored in the chapters directories, mostly chapter-16 and chapter-18. * There is a test generator for [EasyUVM](https://github.com/SymbiFlow/sv-tests/blob/master/generators/easyUVM). * There are multiple UVM tests that use the template generator (see the ``uvm*`` files in the [conf](https://github.com/SymbiFlow/sv-tests/blob/master/conf/generators/templates/) directory). ================================================ FILE: tests/chapter-10/10.3--proc-assignment--bad.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: proc_assignment__bad :description: continuous assignment with delay test :should_fail_because: Illegal to procedurally assign to wire, IEEE Table 10-1 :tags: 10.3 :type: simulation elaboration */ module top(input a, input b); wire w; // Illegal to procedurally assign to wire, IEEE Table 10-1 initial w = #10 a & b; endmodule ================================================ FILE: tests/chapter-10/10.3.1--net-decl-assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: net_decl_assignment :description: net declaration assignment test :tags: 10.3.1 */ module top(input a, input b); wire w = a & b; endmodule ================================================ FILE: tests/chapter-10/10.3.1--one-net.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: one_net_assign :description: simple net declaration assignment test :tags: 10.3.1 :type: simulation elaboration parsing */ module top(input a, output b); assign b = a; endmodule ================================================ FILE: tests/chapter-10/10.3.2--cont-assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cont_assignment :description: continuous assignment test :tags: 10.3.2 */ module top(input a, input b); wire w; assign w = a & b; endmodule ================================================ FILE: tests/chapter-10/10.3.3--cont-assignment-delay.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cont_assignment_delay :description: continuous assignment with delay test :tags: 10.3.3 */ module top(input a, input b); wire w; assign #10 w = a & b; endmodule ================================================ FILE: tests/chapter-10/10.3.3--cont-assignment-net-delay.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cont_assignment_net_delay :description: continuous assignment with net delay test :tags: 10.3.3 */ module top(input a, input b); wire #10 w; assign w = a & b; endmodule ================================================ FILE: tests/chapter-10/10.4.1--blocking-assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: blocking_assignment :description: blocking assignment test :tags: 10.4.1 :type: simulation elaboration parsing */ module top(); logic a = 3; logic b = 2; initial begin a = 1; b = a; $display(":assert: (%d == %d)", a, b); end endmodule ================================================ FILE: tests/chapter-10/10.4.2--non-blocking-assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: non_blocking_assignment :description: non-blocking assignment test :tags: 10.4.2 */ module top(); logic a; initial begin a <= 2; end endmodule ================================================ FILE: tests/chapter-10/10.6.1--assign-deassign.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assign_deassign :description: assign-deassign statements test :tags: 10.6.1 */ module top(clk, q, d, clr, set); input clk, d, clr, set; output q; logic q; always @(clr or set) if (clr) assign q = 0; else if (set) assign q = 1; else deassign q; always @(posedge clk) q <= d; endmodule ================================================ FILE: tests/chapter-10/10.6.2--force-release.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: force_release :description: force-release statements test :tags: 10.6.2 */ module flop(clk, q, d); input clk, d; output q; logic q; always @(posedge clk) q <= d; endmodule module top(clk, q, d, f1, f0); input clk, d, f1, f0; output q; wire q; flop u_flop (.*); always @(f1 or f0) if (f0) force u_flop.q = 0; else if (f1) force u_flop.q = 1; else release u_flop.q; endmodule ================================================ FILE: tests/chapter-11/11.10--string_bit_array-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_bit_array_sim :description: string stored in bit array simulation test :type: simulation elaboration parsing :tags: 11.10 */ module top(); bit [8*14:1] a; initial begin a = "Test"; $display(":assert: ('Test' == '%0s')", a); end endmodule ================================================ FILE: tests/chapter-11/11.10--string_bit_array.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_bit_array :description: string stored in bit array test :tags: 11.10 */ module top(); bit [8*14:1] a; initial begin a = "Test"; end endmodule ================================================ FILE: tests/chapter-11/11.10.1--string_compare.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_compare :description: string comparison test :type: simulation elaboration parsing :tags: 11.10.1 */ module top(); bit [8*14:1] a; bit [8*14:1] b; initial begin a = "Test"; b = "Test"; $display(":assert:('%s' == '%s')", a, b); end endmodule ================================================ FILE: tests/chapter-11/11.10.1--string_concat.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_concat :description: string concatenation test :type: simulation elaboration parsing :tags: 11.10.1 */ module top(); bit [8*14:1] a; bit [8*14:1] b; initial begin a = "Test"; b = "TEST"; $display(":assert: ('TEST' in '%s')", {a, b}); $display(":assert: ('Test' in '%s')", {a, b}); end endmodule ================================================ FILE: tests/chapter-11/11.10.1--string_copy.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_copy :description: string copy test :type: simulation elaboration parsing :tags: 11.10.1 */ module top(); bit [8*14:1] a; bit [8*14:1] b; initial begin a = "Test"; b = a; $display(":assert:('%s' == '%s')", a, b); end endmodule ================================================ FILE: tests/chapter-11/11.10.3--empty_string-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: empty_string_sim :description: empty string simulation test :type: simulation elaboration parsing :tags: 11.10.3 */ module top(); bit [8*14:1] a; initial begin a = ""; $display(":assert: (1 == %d)", a == 0); end endmodule ================================================ FILE: tests/chapter-11/11.10.3--empty_string.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: empty_string :description: empty string test :tags: 11.10.3 */ module top(); bit [8*14:1] a; initial begin a = ""; assert(a == 0); end endmodule ================================================ FILE: tests/chapter-11/11.11--min_max_avg_delay.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: min_max_avg_delay :description: minimum, typical and maximum delay expressions test :tags: 11.11 */ module top(); initial begin #(100:200:300) $display("Done"); end endmodule ================================================ FILE: tests/chapter-11/11.12--let_construct.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: let_construct :description: let construct test :tags: 11.12 */ module top(); logic [3:0] a = 12; logic [3:0] b = 15; logic [3:0] c = 7; logic d; let op(x, y, z) = |((x | y) & z); initial begin d = op(.x(a), .y(b), .z(c)); end endmodule ================================================ FILE: tests/chapter-11/11.3.5--expr_short_circuit.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: expr_short_circuit :description: expression short circuiting test :type: simulation elaboration parsing :tags: 11.3.5 */ module top(); logic a = 1; logic b = 1; logic c = 0; logic d; function int fun(logic a); $display(":assert: (False)"); return a; endfunction initial begin d = a && (b || fun(c)); $display(":assert: (1 == %d)", d); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--assign_in_exp-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assign_in_exp_sim :description: assignment in expression simulation test :type: simulation elaboration parsing :tags: 11.3.6 */ module top(); int a; int b; int c; initial begin c = a; b = (a-=1); $display(":assert: (%d == %d)", b, (c-1)); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--assign_in_exp.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assign_in_exp :description: assignment in expression test :tags: 11.3.6 */ module top(); int a; int b; initial begin b = (a-=1); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--assign_in_expr-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assign_in_expr_sim :description: assignment in expression simulation test :type: simulation elaboration parsing :tags: 11.3.6 */ module top(); int a; int b; int c; initial begin a = (b = (c = 5)); $display(":assert: (5 == %d)", a); $display(":assert: (5 == %d)", b); $display(":assert: (5 == %d)", c); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--assign_in_expr.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assign_in_expr :description: assignment in expression test :tags: 11.3.6 */ module top(); int a; int b; int c; initial begin a = (b = (c = 5)); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--assign_in_expr_inv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assign_in_expr_inv :description: invalid assignment in expression test :should_fail_because: blocking assignments within expression must be enclosed in parentheses :tags: 11.3.6 */ module top(); int a; int b; int c; initial begin a = b = c = 5; end endmodule ================================================ FILE: tests/chapter-11/11.3.6--assign_in_expression-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assign_in_expression_sim :description: assignment in expression simulation test :type: simulation elaboration parsing :tags: 11.3.6 */ module top(); int a; int b; int c; initial begin c = a; b = (++a); $display(":assert: (%d == %d)", b, (c+1)); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--assign_in_expression.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assign_in_expression :description: assignment in expression test :tags: 11.3.6 */ module top(); int a; int b; initial begin b = (++a); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--assignment_in_expression-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assignment_in_expression_sim :description: assignment in expression simulation test :type: simulation elaboration parsing :tags: 11.3.6 */ module top(); int a; int b; int c; initial begin c = a; b = (a+=1); $display(":assert: (%d == %d)", b, (c+1)); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--assignment_in_expression.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assignment_in_expression :description: assignment in expression test :tags: 11.3.6 */ module top(); int a; int b; initial begin b = (a+=1); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--two_assign_in_expr-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: two_assignments_in_expression_sim :description: assignment in expression simulation test :type: simulation elaboration parsing :tags: 11.3.6 */ module top(); int a; int b; int c; int d; int e; initial begin c = a; e = b; d = ((b += (a+=1) + 1)); $display(":assert: (%d == %d)", b, (e+c+2)); $display(":assert: (%d == %d)", d, (e+c+2)); end endmodule ================================================ FILE: tests/chapter-11/11.3.6--two_assign_in_expr.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: two_assignments_in_expression :description: assignment in expression test :tags: 11.3.6 */ module top(); int a; int b; int c; int d; int e; initial begin c = a; e = b; d = ((b += (a+=1) + 1)); end endmodule ================================================ FILE: tests/chapter-11/11.4.1--assignment-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assignment_sim :description: assignment simulation test :type: simulation elaboration parsing :tags: 11.4.1 */ module top(); reg [3:0] a; reg [3:0] b; initial begin a = 4'd12; b = 4'd5; $display(":assert: (12 == %d)", a); a = b; $display(":assert: (5 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.4.10--arith-shift-assignment-signed.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arith_shift_assignment_signed :description: arithmetic shift assignment operator test :type: simulation elaboration parsing :tags: 11.4.10 */ module top(); logic signed [7:0] a, b, c; initial begin a = -120; // 128 + 8 b = a; c = a; b <<<= 3; c >>>= 3; $display(":assert: ( 64 == %d)", b); $display(":assert: ( -15 == %d)", c); end endmodule ================================================ FILE: tests/chapter-11/11.4.10--arith-shift-assignment-unsigned.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arith_shift_assignment_unsigned :description: arithmetic shift assignment operator test :type: simulation elaboration parsing :tags: 11.4.10 */ module top(); logic [7:0] a, b, c; initial begin a = 8; b = a; c = a; b <<<= 3; c >>>= 3; $display(":assert: (64 == %d)", b); $display(":assert: (1 == %d)", c); end endmodule ================================================ FILE: tests/chapter-11/11.4.10--arith-shift-signed.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arith_shift_signed :description: arithmetic shift operator test :type: simulation elaboration parsing :tags: 11.4.10 */ module top(); logic signed [7:0] a, b, c; initial begin a = -120; // 128 + 8 b = (a <<< 3); c = (a >>> 3); $display(":assert: ( 64 == %d)", b); $display(":assert: ( -15 == %d)", c); end endmodule ================================================ FILE: tests/chapter-11/11.4.10--arith-shift-unsigned.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arith_shift_unsigned :description: arithmetic shift operator test :type: simulation elaboration parsing :tags: 11.4.10 */ module top(); logic [7:0] a, b, c; initial begin a = 8; b = (a <<< 3); c = (a >>> 3); $display(":assert: (64 == %d)", b); $display(":assert: (1 == %d)", c); end endmodule ================================================ FILE: tests/chapter-11/11.4.11--cond_op-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cond_op_sim :description: ?: operator simulation test :type: simulation elaboration parsing :tags: 11.4.11 */ module top(); int a = 12; int b = 5; int c; initial begin c = (a > b) ? 11 : 13; $display(":assert: (11 == %d)", c); end endmodule ================================================ FILE: tests/chapter-11/11.4.11--cond_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cond_op :description: ?: operator test :tags: 11.4.11 */ module top(); int a = 12; int b = 5; int c; initial begin c = (a > b) ? 11 : 13; end endmodule ================================================ FILE: tests/chapter-11/11.4.12--concat_op-bit_select.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: concat_op-bit_select :description: concatenation operator w/ bit selection test :tags: 11.4.12 */ module top(); bit [3:0] a; bit [7:0] b = 8'b10101100; bit [7:0] c = 8'b01010011; initial begin a = {b, c}[9:6]; end endmodule ================================================ FILE: tests/chapter-11/11.4.12--concat_op-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: concat_op_sim :description: concatenation operator simulation test :type: simulation elaboration parsing :tags: 11.4.12 */ module top(); bit [15:0] a; bit [7:0] b = 8'h89; bit [7:0] c = 8'h12; initial begin a = {b, c}; $display(":assert: (0x8912 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.4.12--concat_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: concat_op :description: concatenation operator test :tags: 11.4.12 */ module top(); bit [15:0] a; bit [7:0] b = 8'b10101100; bit [7:0] c = 8'b01010011; initial begin a = {b, c}; end endmodule ================================================ FILE: tests/chapter-11/11.4.12.1--nested_repl_op-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: nested_repl_op_sim :description: nested replication operator simulation test :type: simulation elaboration parsing :tags: 11.4.12.1 */ module top(); bit [15:0] a; bit [1:0] b = 2'b10; bit [1:0] c = 2'b01; bit [3:0] d = 4'b1111; initial begin a = {{3{b, c}}, d}; $display(":assert: (0b1001100110011111 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.4.12.1--nested_repl_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: nested_repl_op :description: nested replication operator test :tags: 11.4.12.1 */ module top(); bit [15:0] a; bit [1:0] b = 2'b10; bit [1:0] c = 2'b01; bit [3:0] d = 4'b1111; initial begin a = {{3{b, c}}, d}; end endmodule ================================================ FILE: tests/chapter-11/11.4.12.1--repl_op-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: repl_op_sim :description: replication operator simulation test :type: simulation elaboration parsing :tags: 11.4.12.1 */ module top(); bit [15:0] a; bit [1:0] b = 2'b10; initial begin a = {8{b}}; $display(":assert: (0b1010101010101010 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.4.12.1--repl_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: repl_op :description: replication operator test :tags: 11.4.12.1 */ module top(); bit [15:0] a; bit [1:0] b = 2'b10; initial begin a = {8{b}}; end endmodule ================================================ FILE: tests/chapter-11/11.4.12.2--string_concat_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_concat_op :description: string concatenation operator test :tags: 11.4.12.2 :type: simulation elaboration parsing */ module top(); string str; initial begin str = {"Hello", "_", "World", "!"}; $display(":assert:('%s' == 'Hello_World!')", str); end endmodule ================================================ FILE: tests/chapter-11/11.4.12.2--string_repl_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_repl_op :description: string replication operator test :tags: 11.4.12.2 :type: simulation elaboration parsing */ module top(); string str; initial begin str = {4{"test"}}; $display(":assert:('%s' == 'testtesttesttest')", str); end endmodule ================================================ FILE: tests/chapter-11/11.4.13--set_member-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: set_member_sim :description: inside operator simulation test :type: simulation elaboration parsing :tags: 11.4.13 */ module top(); int a = 12; initial begin $display(":assert: (1 == %d)", a inside {2, 4, 6, 8, 10, 12}); end endmodule ================================================ FILE: tests/chapter-11/11.4.13--set_member.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: set_member :description: inside operator test :tags: 11.4.13 */ module top(); int a; int b = 12; localparam c = 5; localparam d = 7; initial begin a = b inside {c, d}; end endmodule ================================================ FILE: tests/chapter-11/11.4.14.1--stream_concat-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: stream_concat_sim :description: stream concatenation simulation test :type: simulation elaboration parsing :tags: 11.4.14.1 */ module top(); int a = {"A", "B", "C", "D"}; int b = {"E", "F", "G", "H"}; logic [63:0] c; initial begin c = {>> 8 {a, b}}; $display(":assert: (((%d << 32) + %d) == %d) ", a, b, c); end endmodule ================================================ FILE: tests/chapter-11/11.4.14.1--stream_concat.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: stream_concat :description: stream concatenation test :tags: 11.4.14.1 */ module top(); int a = {"A", "B", "C", "D"}; int b = {"E", "F", "G", "H"}; logic [63:0] c; initial begin c = {>> 8 {a, b}}; end endmodule ================================================ FILE: tests/chapter-11/11.4.14.2--reorder_stream-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: reorder_stream_sim :description: stream reordering simulation test :type: simulation elaboration parsing :tags: 11.4.14.2 */ module top(); int a = {"A", "B", "C", "D"}; int b; initial begin b = {<< 8 {a}}; $display(":assert: (0x44434241 == 0x%x)", b); end endmodule ================================================ FILE: tests/chapter-11/11.4.14.2--reorder_stream.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: reorder_stream :description: stream reordering test :tags: 11.4.14.2 */ module top(); int a = {"A", "B", "C", "D"}; int b; initial begin b = {<< 8 {a}}; end endmodule ================================================ FILE: tests/chapter-11/11.4.14.2--reorder_stream_byte-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: reorder_stream_byte_sim :description: stream reordering simulation test :type: simulation elaboration parsing :tags: 11.4.14.2 */ module top(); int a = {"A", "B", "C", "D"}; int b; initial begin b = {<< byte {a}}; $display(":assert: (0x44434241 == 0x%x)", b); end endmodule ================================================ FILE: tests/chapter-11/11.4.14.2--reorder_stream_byte.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: reorder_stream_byte :description: stream reordering test :tags: 11.4.14.2 */ module top(); int a = {"A", "B", "C", "D"}; int b; initial begin b = {<< byte {a}}; end endmodule ================================================ FILE: tests/chapter-11/11.4.14.3--unpack_stream-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpack_stream_sim :description: stream unpack simulation test :type: simulation elaboration parsing :tags: 11.4.14.3 */ module top(); int a = 1; int b = 2; int c = 3; initial begin bit [95:0] d = {<< 32 {a, b, c}}; $display(":assert: (((%d << 64) + (%d << 32) + %d) == %d)", c, b, a, d); end endmodule ================================================ FILE: tests/chapter-11/11.4.14.3--unpack_stream.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpack_stream :description: stream unpack test :tags: 11.4.14.3 */ module top(); int a = 1; int b = 2; int c = 3; initial begin bit [95:0] d = {<<{a, b, c}}; end endmodule ================================================ FILE: tests/chapter-11/11.4.14.3--unpack_stream_inv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpack_stream_inv :description: invalid stream unpack test :should_fail_because: stream is wider than assignment target :tags: 11.4.14.3 :runner_verilator_flags: -Werror-WIDTH :type: simulation elaboration */ module top(); int a = 1; int b = 2; int c = 3; initial begin int d = {<<{a, b, c}}; end endmodule ================================================ FILE: tests/chapter-11/11.4.14.3--unpack_stream_pad-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpack_stream_pad_sim :description: padded stream unpack simulation test :type: simulation elaboration parsing :tags: 11.4.14.3 */ module top(); int a = 1; int b = 2; int c = 3; bit ok; initial begin bit [127:0] d = {<< 32 {a, b, c}}; ok = d == 128'h00000003_00000002_00000001_00000000; $display(":assert: (%0d == %0d)", ok, 1); end endmodule ================================================ FILE: tests/chapter-11/11.4.14.3--unpack_stream_pad.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpack_stream_pad :description: padded stream unpack test :tags: 11.4.14.3 */ module top(); int a = 1; int b = 2; int c = 3; initial begin bit [127:0] d = {<<{a, b, c}}; end endmodule ================================================ FILE: tests/chapter-11/11.4.14.4--dynamic_array_stream-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dynamic_array_unpack_stream_sim :description: stream unpack simulation test with dynamic array :type: simulation elaboration parsing :tags: 11.4.14.4 :unsynthesizable: 1 */ module top(); int i_header; int i_len; byte i_data[]; int i_crc; int o_header; int o_len; byte o_data[]; int o_crc; initial begin byte pkt[$]; i_header = 12; i_len = 5; i_crc = 42; i_data = new[5]; i_data[0] = 1; i_data[1] = 2; i_data[2] = 3; i_data[3] = 4; i_data[4] = 5; pkt = {<< 8 {i_header, i_len, i_crc, i_data}}; {<< 8 {o_header, o_len, o_crc, o_data}} = pkt; $display(":assert: (12 == %d)", o_header); $display(":assert: (5 == %d)", o_len); $display(":assert: (42 == %d)", o_crc); end endmodule ================================================ FILE: tests/chapter-11/11.4.14.4--dynamic_array_stream.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dynamic_array_unpack_stream :description: stream unpack test with dynamic array :tags: 11.4.14.4 :unsynthesizable: 1 */ module top(); int i_header; int i_len; byte i_data[]; int i_crc; int o_header; int o_len; byte o_data[]; int o_crc; initial begin byte pkt[$]; i_header = 12; i_len = 5; i_data = new[5]; i_crc = 42; pkt = {<< 8 {i_header, i_len, i_data, i_crc}}; {<< 8 {o_header, o_len, o_data, o_crc}} = pkt; end endmodule ================================================ FILE: tests/chapter-11/11.4.14.4--dynamic_array_stream_with.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dynamic_array_unpack_stream_with :description: stream unpack test with dynamic array using with :tags: 11.4.14.4 :unsynthesizable: 1 */ module top(); int i_header; int i_len; byte i_data[]; int i_crc; int o_header; int o_len; byte o_data[]; int o_crc; initial begin byte pkt[$]; i_header = 12; i_len = 5; i_data = new[5]; i_crc = 42; pkt = {<< 8 {i_header, i_len, i_data, i_crc}}; {<< 8 {o_header, o_len, o_data with [0 +: o_len], o_crc}} = pkt; end endmodule ================================================ FILE: tests/chapter-11/11.4.2--unary_op_dec-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unary_op_dec_sim :description: -- operator simulation test type: simulation elaboration parsing :tags: 11.4.2 */ module top(); int a = 12; initial begin a--; $display(":assert: (11 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.4.2--unary_op_dec.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unary_op_dec :description: -- operator test :tags: 11.4.2 */ module top(); int a = 12; initial begin a--; end endmodule ================================================ FILE: tests/chapter-11/11.4.2--unary_op_inc-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unary_op_inc_sim :description: ++ operator simulation test type: simulation elaboration parsing :tags: 11.4.2 */ module top(); int a = 12; initial begin a++; $display(":assert: (13 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.4.2--unary_op_inc.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unary_op_inc :description: ++ operator test :tags: 11.4.2 */ module top(); int a = 12; initial begin a++; end endmodule ================================================ FILE: tests/chapter-11/11.4.5--equality-op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: equality_op :description: equality operator test :type: simulation elaboration parsing :tags: 11.4.5 */ module top(); reg [7:0] a, b, c, d, e, f; initial begin a = 8'b1101x001; b = 8'b1101x000; c = 8'b1101z001; d = 8'b1101z000; e = 8'b11011001; f = 8'b11011000; $display(":assert: (0 == %d)", a == b); $display(":assert: (0 == %d)", c == d); $display(":assert: (0 == %d)", e == f); $display(":assert: (0 == %d)", a === b); $display(":assert: (0 == %d)", c === d); $display(":assert: (0 == %d)", e === f); end endmodule ================================================ FILE: tests/chapter-11/11.5.1--idx_neg_part_select-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: idx_neg_part_select_sim :description: indexed negative part-select bit simulation test :type: simulation elaboration parsing :tags: 11.5.1 */ module top(); logic [15:0] a = 16'h1234; logic [7:0] b; initial begin b = a[15-:8]; $display(":assert: (0x12 == 0x%x)", b); end endmodule ================================================ FILE: tests/chapter-11/11.5.1--idx_neg_part_select.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: idx_neg_part_select :description: indexed negative part-select bit test :tags: 11.5.1 */ module top(); logic [15:0] a; logic [3:0] b; initial begin b = a[11-:4]; end endmodule ================================================ FILE: tests/chapter-11/11.5.1--idx_pos_part_select-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: idx_pos_part_select_sim :description: indexed positive part-select bit simulation test :type: simulation elaboration parsing :tags: 11.5.1 */ module top(); logic [15:0] a = 16'h1234; logic [7:0] b; initial begin b = a[0+:8]; $display(":assert: (0x34 == 0x%x)", b); end endmodule ================================================ FILE: tests/chapter-11/11.5.1--idx_pos_part_select.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: idx_pos_part_select :description: indexed positive part-select bit test :tags: 11.5.1 */ module top(); logic [15:0] a; logic [3:0] b; initial begin b = a[11+:4]; end endmodule ================================================ FILE: tests/chapter-11/11.5.1--idx_select-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: idx_select_sim :description: indexed select bit simulation test :type: simulation elaboration parsing :tags: 11.5.1 */ module top(); logic [15:0] a = 16'h1000; logic b; logic c; initial begin b = a[12]; c = a[5]; $display(":assert: (1 == %d)", b); $display(":assert: (0 == %d)", c); end endmodule ================================================ FILE: tests/chapter-11/11.5.1--idx_select.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: idx_select :description: indexed select bit test :tags: 11.5.1 */ module top(); logic [15:0] a; logic b; initial begin b = a[11]; end endmodule ================================================ FILE: tests/chapter-11/11.5.1--non_idx_part_select-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: non_idx_part_select_sim :description: non-indexed part-select bit simulation test :type: simulation elaboration parsing :tags: 11.5.1 */ module top(); logic [15:0] a = 16'h1234; logic [3:0] b; initial begin b = a[11:8]; $display(":assert: (2 == %d)", b); end endmodule ================================================ FILE: tests/chapter-11/11.5.1--non_idx_part_select.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: non_idx_part_select :description: non-indexed part-select bit test :tags: 11.5.1 */ module top(); logic [15:0] a; logic [3:0] b; initial begin b = a[11:8]; end endmodule ================================================ FILE: tests/chapter-11/11.5.2--array_addressing-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array_addressing_sim :description: array addressing simulation test :type: simulation elaboration parsing :tags: 11.5.2 */ module top(); logic [7:0] mem [0:1023]; logic [7:0] a; initial begin mem[123] = 125; a = mem[123]; $display(":assert: (125 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.5.2--array_addressing.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array_addressing :description: array addressing test :tags: 11.5.2 */ module top(); logic [7:0] mem [0:1023]; logic [7:0] a; initial begin a = mem[123]; end endmodule ================================================ FILE: tests/chapter-11/11.5.2--multi_dim_array_addressing-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: multi_dim_array_addressing_sim :description: multi-dimensional array addressing simulation test :type: simulation elaboration parsing :tags: 11.5.2 */ module top(); logic [7:0] mem [0:1023][0:3]; logic [7:0] a; initial begin mem[123][2] = 125; a = mem[123][2]; $display(":assert: (125 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.5.2--multi_dim_array_addressing.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: multi_dim_array_addressing :description: multi-dimensional array addressing test :tags: 11.5.2 */ module top(); logic [7:0] mem [0:1023][0:3]; logic [7:0] a; initial begin a = mem[123][2]; end endmodule ================================================ FILE: tests/chapter-11/11.7--signed_func-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: signed_func_sim :description: $signed() simulation test :type: simulation elaboration parsing :tags: 11.7 */ module top(); logic signed [7:0] a; initial begin a = $signed(4'b1000); $display(":assert: (-8 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.7--signed_func.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: signed_func :description: $signed() test :tags: 11.7 */ module top(); logic signed [7:0] a; initial begin a = $signed(4'b1000); end endmodule ================================================ FILE: tests/chapter-11/11.7--unsigned_func-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unsigned_func_sim :description: $unsigned() simulation test :type: simulation elaboration parsing :tags: 11.7 */ module top(); logic [7:0] a; initial begin a = $unsigned(-4); $display(":assert: (0b11111100 == %d)", a); end endmodule ================================================ FILE: tests/chapter-11/11.7--unsigned_func.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unsigned_func :description: $unsigned() test :tags: 11.7 */ module top(); logic [7:0] a; initial begin a = $unsigned(-4); end endmodule ================================================ FILE: tests/chapter-11/11.9--tagged_union.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: tagged_union :description: tagged union test :tags: 11.9 */ module top(); typedef union tagged { void Invalid; int Valid; } u_int; u_int a, b; initial begin a = tagged Invalid; b = tagged Valid(42); end endmodule ================================================ FILE: tests/chapter-11/11.9--tagged_union_member_access-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: tagged_union_member_access_sim :description: tagged union member access simulation test :type: simulation elaboration parsing :tags: 11.9 */ module top(); typedef union tagged { void Invalid; int Valid; } u_int; u_int a; int b; initial begin a = tagged Valid(42); b = a.Valid; $display(":assert: (42 == %d)", b); end endmodule ================================================ FILE: tests/chapter-11/11.9--tagged_union_member_access.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: tagged_union_member_access :description: tagged union member access test :tags: 11.9 */ module top(); typedef union tagged { void Invalid; int Valid; } u_int; u_int a, b; int c; initial begin a = tagged Invalid; b = tagged Valid(42); c = b.Valid; end endmodule ================================================ FILE: tests/chapter-11/11.9--tagged_union_member_access_inv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: tagged_union_member_access_inv :description: invalid tagged union member access test :should_fail_because: accessing wrong member should result in run-time error :tags: 11.9 :type: simulation */ module top(); typedef union tagged { void Invalid; int Valid; } u_int; u_int a, b; int c; initial begin a = tagged Invalid; b = tagged Valid(42); c = a.Valid; end endmodule ================================================ FILE: tests/chapter-11/simple/11.4.11--simple_cond_op-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_cond_op_sim :description: minimal ?: operator simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.4.11 */ module top(input a, output b); assign b = (a) ? 0 : 1; endmodule ================================================ FILE: tests/chapter-11/simple/11.4.12--simple_concat_op-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_concat_op_sim :description: minimal concatenation operator simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.4.12 */ module top(input [1:0] a, input [1:0] b, output [3:0] c); assign c = {a, b}; endmodule ================================================ FILE: tests/chapter-11/simple/11.4.12.1--simple_repl_op-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_repl_op_sim :description: minimal replication operator simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.4.12.1 */ module top(input [1:0] a, output [15:0] b); assign b = {8{a}}; endmodule ================================================ FILE: tests/chapter-11/simple/11.4.13--simple_set_member-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_set_member_sim :description: minimal inside operator simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.4.13 */ module top(input [3:0] a, output b); assign b = (a inside {2, 3, 4, 5}); endmodule ================================================ FILE: tests/chapter-11/simple/11.4.14.3--simple_unpack_stream-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_unpack_stream_sim :description: minimal stream unpack simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.4.14.3 */ module top(input [1:0] a, input [1:0] b, input [1:0] c, output [5:0] d); assign d = {<<2 {a, b, c}}; endmodule ================================================ FILE: tests/chapter-11/simple/11.5.1--simple_idx_neg_part_select-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_idx_neg_part_select_sim :description: minimal indexed negative part-select bit simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.5.1 */ module top(input [15:0] a, output [3:0] b); assign b = a[15-:4]; endmodule ================================================ FILE: tests/chapter-11/simple/11.5.1--simple_idx_pos_part_select-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_idx_pos_part_select_sim :description: minimal indexed positive part-select bit simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.5.1 */ module top(input [15:0] a, output [3:0] b); assign b = a[0+:4]; endmodule ================================================ FILE: tests/chapter-11/simple/11.5.1--simple_idx_select-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_idx_select_sim :description: minimal indexed select bit simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.5.1 */ module top(input [3:0] a, output b); assign b = a[2]; endmodule ================================================ FILE: tests/chapter-11/simple/11.5.1--simple_non_idx_part_select-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_non_idx_part_select_sim :description: minimal non-indexed part-select bit simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.5.1 */ module top(input [7:0] a, output [1:0] b); assign b = a[7:6]; endmodule ================================================ FILE: tests/chapter-11/simple/11.5.2--simple_array_addressing-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: simple_array_addressing_sim :description: minimal array addressing simulation test (without result verification) :type: simulation elaboration parsing :tags: 11.5.2 */ module top(input [7:0] a, output [7:0] b); reg [7:0] mem [0:255]; assign b = mem[a]; endmodule ================================================ FILE: tests/chapter-12/12.4--if.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if :description: A module testing if statement :tags: 12.4 */ module if_tb (); wire a = 0; reg b = 0; always @* begin if(a) b = 1; end endmodule ================================================ FILE: tests/chapter-12/12.4--if_else.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else :description: A module testing if-else statement :tags: 12.4 */ module if_tb (); wire a = 0; reg b = 0; always @* begin if(a) b = 1; else b = 0; end endmodule ================================================ FILE: tests/chapter-12/12.4.1--if_else_if.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_if :description: A module testing if-else-if statement :tags: 12.4.1 */ module if_tb (); wire a = 0; reg b = 0; wire c = 0; reg d = 0; always @* begin if(a) b = 1; else if(c) d = 1; else b = 0; end endmodule ================================================ FILE: tests/chapter-12/12.4.2--priority_if.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: priority_if :description: A module testing priority-if statement :tags: 12.4.2 */ module if_tb (); wire [3:0] a = 0; reg [1:0] b = 0; always @* begin priority if(a[0] == 0) b = 1; else if(a[1] == 0) b = 2; end endmodule ================================================ FILE: tests/chapter-12/12.4.2--unique0_if.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unique0_if :description: A module testing unique0-if statement :tags: 12.4.2 */ module if_tb (); wire [3:0] a = 0; reg [1:0] b = 0; always @* begin unique0 if(a == 0) b = 1; else if(a == 1) b = 2; end endmodule ================================================ FILE: tests/chapter-12/12.4.2--unique_if.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unique_if :description: A module testing unique-if statement :tags: 12.4.2 */ module if_tb (); wire [3:0] a = 0; reg [1:0] b = 0; always @* begin unique if(a == 0) b = 1; else if(a == 1) b = 2; end endmodule ================================================ FILE: tests/chapter-12/12.5--case.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: case :description: A module testing case statement :tags: 12.5 */ module case_tb (); wire [3:0] a = 0; reg [3:0] b = 0; always @* begin case(a) 4'h0: b = 12; 4'h3: b = 4; 4'hf: b = 8; default b = 0; endcase end endmodule ================================================ FILE: tests/chapter-12/12.5.1--casex.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: casex :description: A module testing casex statement :tags: 12.5.1 */ module case_tb (); wire [3:0] a = 4'b10zx; reg [3:0] b = 0; always @* begin casex(a) 4'b1xz?: b = 1; 4'b01xx: b = 2; 4'b001x: b = 3; 4'b0001: b = 4; default b = 0; endcase end endmodule ================================================ FILE: tests/chapter-12/12.5.1--casez.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: casez :description: A module testing casez statement :tags: 12.5.1 */ module case_tb (); wire [3:0] a = 4'b1z11; reg [3:0] b = 0; always @* begin casez(a) 4'b1zzz: b = 1; 4'b01z?: b = 2; 4'b001z: b = 3; 4'b0001: b = 4; default b = 0; endcase end endmodule ================================================ FILE: tests/chapter-12/12.5.2--case_const.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: case_constant :description: A module testing case statement with constant expression :tags: 12.5.2 */ module case_tb (); wire [3:0] a = 0; reg [3:0] b = 0; always @* begin case(1) a[0] : b = 1; a[1] : b = 2; a[2] : b = 3; a[3] : b = 4; default b = 0; endcase end endmodule ================================================ FILE: tests/chapter-12/12.5.4--case_set.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: case_set :description: A module testing case set membership :tags: 12.5.4 */ module case_tb (); reg [3:0] a = 0; reg [3:0] b = 0; always @* begin case(a) inside 1, 3: b = 1; 4'b01??, [5:6]: b = 2; default b = 3; endcase end endmodule ================================================ FILE: tests/chapter-12/12.6.1--case_pattern.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: case_pattern :description: A module testing pattern matching in case statements :tags: 12.6.1 */ module case_tb (); typedef union tagged { struct { bit [3:0] val1, val2; } a; struct { bit [7:0] val1, val2; } b; struct { bit [15:0] val1, val2; } c; } u; u tmp; initial case (tmp) matches tagged a '{.v, 0} : $display("a %d", v); tagged a '{.v1, .v2} : $display("a %d %d", v1, v2); tagged b '{.v1, .v2} : $display("b %d %d", v1, v2); tagged c '{0, .v} : $display("c %d", v); endcase endmodule ================================================ FILE: tests/chapter-12/12.6.1--casex_pattern.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: casex_pattern :description: A module testing pattern matching in casex statements :tags: 12.6.1 */ module case_tb (); typedef union tagged { struct { bit [3:0] val1, val2; } a; struct { bit [7:0] val1, val2; } b; struct { bit [15:0] val1, val2; } c; } u; u tmp; initial casex (tmp) matches tagged a '{.v, 4'b00?x} : $display("a %d", v); tagged a '{.v1, .v2} : $display("a %d %d", v1, v2); tagged b '{.v1, .v2} : $display("b %d %d", v1, v2); tagged c '{4'h??0x, .v} : $display("c %d", v); endcase endmodule ================================================ FILE: tests/chapter-12/12.6.1--casez_pattern.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: casez_pattern :description: A module testing pattern matching in casez statements :tags: 12.6.1 */ module case_tb (); typedef union tagged { struct { bit [3:0] val1, val2; } a; struct { bit [7:0] val1, val2; } b; struct { bit [15:0] val1, val2; } c; } u; u tmp; initial casez (tmp) matches tagged a '{.v, 4'bzz0?} : $display("a %d", v); tagged a '{.v1, .v2} : $display("a %d %d", v1, v2); tagged b '{.v1, .v2} : $display("b %d %d", v1, v2); tagged c '{4'hz00?, .v} : $display("c %d", v); endcase endmodule ================================================ FILE: tests/chapter-12/12.6.2--if_pattern.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_pattern :description: A module testing pattern matching in if statements :tags: 12.6.2 */ module case_tb (); typedef union tagged { struct { bit [3:0] val1, val2; } a; struct { bit [7:0] val1, val2; } b; struct { bit [15:0] val1, val2; } c; } u; u tmp; initial if (tmp matches tagged a '{4'b01zx, .v}) $display("a %d", v); endmodule ================================================ FILE: tests/chapter-12/12.6.3--conditional_pattern.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: conditional_pattern :description: A module testing pattern matching in conditional expressions :tags: 12.6.3 */ module case_tb (); typedef union tagged { struct { bit [3:0] val1, val2; } a; struct { bit [7:0] val1, val2; } b; struct { bit [15:0] val1, val2; } c; } u; u tmp; bit [3:0] val; initial begin val = tmp matches tagged a '{4'b01zx, .v} ? 1 : 2; end endmodule ================================================ FILE: tests/chapter-12/12.7.1--for.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: for_loop :description: A module testing for loop :tags: 12.7.1 */ module for_tb (); initial begin for (int i = 0; i < 256; i++) $display("%d", i); end endmodule ================================================ FILE: tests/chapter-12/12.7.2--repeat.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: repeat_loop :description: A module testing repeat loop :tags: 12.7.2 */ module repeat_tb (); int a = 128; initial begin repeat(a) $display("repeat"); end endmodule ================================================ FILE: tests/chapter-12/12.7.3--foreach-synth.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: foreach_loop_synth :description: A module testing foreach loop :tags: 12.7.3 */ module test (); logic [15:0] test [4] = '{16'h1111, 16'h2222, 16'h3333, 16'h4444}; logic [15:0] copy [4]; always_comb begin foreach(test[i]) begin copy[i] = test[i]; end end endmodule ================================================ FILE: tests/chapter-12/12.7.3--foreach.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: foreach_loop :description: A module testing foreach loop :tags: 12.7.3 :unsynthesizable: 1 */ module foreach_tb (); string test [4] = '{"111", "222", "333", "444"}; initial begin foreach(test[i]) $display(i, test[i]); end endmodule ================================================ FILE: tests/chapter-12/12.7.4--while.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: while_loop :description: A module testing while loop :tags: 12.7.4 */ module while_tb (); string test [4] = '{"111", "222", "333", "444"}; initial begin int i = 0; while(test[i] != "222")begin $display(i, test[i]); i++; end end endmodule ================================================ FILE: tests/chapter-12/12.7.5--dowhile.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dowhile_loop :description: A module testing do..while loop :tags: 12.7.5 */ module dowhile_tb (); string test [4] = '{"111", "222", "333", "444"}; initial begin int i = 0; do begin $display(i, test[i]); i++; end while(test[i] != "222"); end endmodule ================================================ FILE: tests/chapter-12/12.7.6--forever.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: forever_loop :description: A module testing forever loop :tags: 12.7.6 :unsynthesizable: 1 */ module forever_tb (); initial begin forever begin : loop disable loop; end end endmodule ================================================ FILE: tests/chapter-12/12.8--break.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: jump_break :description: A module testing break statement :tags: 12.8 :type: simulation elaboration parsing */ module jump_tb (); initial begin int i; for (i = 0; i < 256; i++)begin if(i > 100) break; end $display(":assert:(%d == 101)", i); end endmodule ================================================ FILE: tests/chapter-12/12.8--continue.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: jump_continue :description: A module testing continue statement :tags: 12.8 :type: simulation elaboration parsing */ module jump_tb (); initial begin for (int i = 0; i < 256; i++)begin if(i < 255) continue; $display(":assert:(%d == 255)", i); end end endmodule ================================================ FILE: tests/chapter-12/12.8--return.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: jump_return :description: A module testing return statement :tags: 12.8 */ module jump_tb (); function void fun(input int a); $display("a"); if(a == 21) return; $display(a); return; endfunction initial begin for (int i = 0; i < 256; i++)begin fun(i); end end endmodule ================================================ FILE: tests/chapter-12/12.8--return_val.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: jump_return_expr :description: A module testing return statement :tags: 12.8 */ module jump_tb (); function int fun(input int a); return a * 3; endfunction initial begin for (int i = 0; i < 256; i++)begin $display(fun(i)); end end endmodule ================================================ FILE: tests/chapter-13/13.3--task-label.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: task-label :description: test w/ named end test :tags: 13.3 :type: simulation elaboration parsing */ module top(); task mytask; $display(":assert: True"); endtask : mytask initial mytask; endmodule ================================================ FILE: tests/chapter-13/13.3--task.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: task :description: task test :tags: 13.3 :type: simulation elaboration parsing */ module top(); task mytask; $display(":assert: True"); endtask initial mytask; endmodule ================================================ FILE: tests/chapter-13/13.3.1--task-automatic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: task_automatic :description: automatic task test :tags: 13.3.1 :type: simulation elaboration parsing */ module top(); task automatic mytask; int a = 0; a++; $display(":assert:(%d == 1)", a); endtask initial begin mytask; mytask; mytask; mytask; end endmodule ================================================ FILE: tests/chapter-13/13.3.1--task-static.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: task_static :description: static task test :tags: 13.3.1 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); task static mytask(int test); int a = 0; a++; if (test) $display(":assert:(%d != 1)", a); else $display(":assert:(%d == 1)", a); endtask initial begin mytask(0); mytask(1); mytask(1); mytask(1); end endmodule ================================================ FILE: tests/chapter-13/13.4--function-label.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: function :description: function w/ named end test :tags: 13.4 :type: simulation elaboration parsing */ module top(); function int test(int val); return val + 1; endfunction : test initial $display(":assert: (%d == 2)", test(1)); endmodule ================================================ FILE: tests/chapter-13/13.4--function.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: function :description: function test :tags: 13.4 :type: simulation elaboration parsing */ module top(); function int test(int val); return val + 1; endfunction initial $display(":assert: (%d == 2)", test(1)); endmodule ================================================ FILE: tests/chapter-13/13.4.1--function-return-assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: function_return_assignment :description: function return value assignment test :tags: 13.4.1 :type: simulation elaboration parsing */ module top(); function int add(int a, int b); add = a + b; endfunction initial $display(":assert: (%d == 90)", add(30, 60)); endmodule ================================================ FILE: tests/chapter-13/13.4.1--function-return.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: function_return :description: function return value test :tags: 13.4.1 :type: simulation elaboration parsing */ module top(); function int add(int a, int b); return a + b; endfunction initial $display(":assert: (%d == 90)", add(30, 60)); endmodule ================================================ FILE: tests/chapter-13/13.4.1--function-void-return.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: function_void_return :description: void function return value test :should_fail_because: void function returns value :tags: 13.4.1 :type: simulation elaboration */ module top(); function void add(int a, int b); $display("%d+%d=", a, b); return a + b; endfunction initial $display("%d", add(45, 90)); endmodule ================================================ FILE: tests/chapter-13/13.4.2--function-automatic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: function_automatic :description: automatic function test :tags: 13.4.2 :type: simulation elaboration parsing */ module top(); function automatic int add(int val); int a = 0; a = a + val; return a; endfunction initial begin $display(":assert: (%d == 5)", add(5)); $display(":assert: (%d == 5)", add(5)); $display(":assert: (%d == 5)", add(5)); $display(":assert: (%d == 5)", add(5)); end endmodule ================================================ FILE: tests/chapter-13/13.4.2--function-recursive.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC // -*- coding: utf-8 -*- // SPDX-License-Identifier: ISC // // Copyright (C) 2020 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC /* :name: function_recursive :description: recursive function test :tags: 13.4.2 :type: simulation elaboration parsing */ module top(); function automatic int factorial(int val); if(val == 0) return 1; return factorial(val-1) * val; endfunction initial begin $display(":assert: (%d == 1)", factorial(0)); $display(":assert: (%d == 1)", factorial(1)); $display(":assert: (%d == 2)", factorial(2)); $display(":assert: (%d == 120)", factorial(5)); $display(":assert: (%d == 39916800)", factorial(11)); end endmodule ================================================ FILE: tests/chapter-13/13.4.2--function-static.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: function_static :description: static function test :tags: 13.4.2 :unsynthesizable: 1 */ module top(); function static int add(int val); int a = 0; a = a + val; return a; endfunction initial begin $display(":assert: (%d == 5)", add(5)); $display(":assert: (%d == 10)", add(5)); $display(":assert: (%d == 15)", add(5)); $display(":assert: (%d == 20)", add(5)); end endmodule ================================================ FILE: tests/chapter-13/13.4.3--const-function.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: const_function :description: const function test :tags: 13.4.3 :type: simulation elaboration parsing */ module top(); localparam a = fun(3); function int fun(int val); return val + 1; endfunction initial $display(":assert: (%d == 4)", a); endmodule ================================================ FILE: tests/chapter-13/13.4.4--fork-invalid.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: function_fork_invalid :description: function invalid fork test :should_fail_because: only fork-join_none is permitted inside a function :tags: 13.4.4 :type: simulation elaboration :unsynthesizable: 1 */ module top(); function int fun(int val); fork $display("abc"); $display("def"); join_any return val + 2; endfunction initial $display("$d", fun(2)); endmodule ================================================ FILE: tests/chapter-13/13.4.4--fork-valid.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: function_fork_valid :description: function valid fork test :tags: 13.4.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); function int fun(int val); fork $display("abc"); $display("def"); join_none return val + 2; endfunction initial $display("$d", fun(2)); endmodule ================================================ FILE: tests/chapter-14/14.3--clocking-block-signals-error.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: clocking_block_signals_fail :description: clocking block with signals test :should_fail_because: assigning to net from procedural context :type: simulation elaboration :tags: 14.3 :unsynthesizable: 1 */ module top(input clk, input a, output b, output c); clocking ck1 @(posedge clk); default input #10ns output #5ns; input a; output b; output #3ns c; endclocking always_ff @(posedge clk) begin b <= a; c <= a; end endmodule ================================================ FILE: tests/chapter-14/14.3--clocking-block-signals.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: clocking_block_signals :description: clocking block with signals test :tags: 14.3 :unsynthesizable: 1 */ module top(input clk, input a, output logic b, output logic c); clocking ck1 @(posedge clk); default input #10ns output #5ns; input a; output b; output #3ns c; endclocking always_ff @(posedge clk) begin b <= a; c <= a; end endmodule ================================================ FILE: tests/chapter-14/14.3--clocking-block.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: clocking_block :description: clocking block test :tags: 14.3 :unsynthesizable: 1 */ module top(input clk); clocking ck1 @(posedge clk); default input #10ns output #5ns; endclocking endmodule ================================================ FILE: tests/chapter-14/14.3--default-clocking-block.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: default_clocking_block :description: default clocking block test :tags: 14.3 :unsynthesizable: 1 */ module top(input clk); default clocking @(posedge clk); default input #10ns output #5ns; endclocking endmodule ================================================ FILE: tests/chapter-14/14.3--global-clocking-block.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: global_clocking_block :description: global clocking block test :tags: 14.3 :unsynthesizable: 1 */ module top(input clk); global clocking ck1 @(posedge clk); endclocking endmodule ================================================ FILE: tests/chapter-15/15.4--mailbox-blocking.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: mailbox_blocking :description: blocking mailbox test :tags: 15.4 :type: simulation elaboration parsing */ module top(); mailbox #(string) m; initial begin string msg = "abc"; string r; string r_peek; m = new(); m.put(msg); m.peek(r_peek); $display(":assert: (%d == 1)", m.num()); m.get(r); $display(":assert: ('%s' == '%s')", r, r_peek); end endmodule ================================================ FILE: tests/chapter-15/15.4--mailbox-non-blocking.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: mailbox_non_blocking :description: non-blocking mailbox test :tags: 15.4 :type: simulation elaboration parsing */ module top(); mailbox #(string) m; initial begin string msg = "abc"; string r; string r_peek; int i; m = new(); i = m.try_put(msg); m.peek(r_peek); $display(":assert: (%d == 1)", m.num()); i = m.try_get(r); $display(":assert: ('%s' == '%s')", r, r_peek); end endmodule ================================================ FILE: tests/chapter-15/15.5.1--named-event-trigger-blocking.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: named_event_trigger_blocking :description: Trigger named event, blocking :tags: 15.5 :top_module: top :unsynthesizable: 1 */ module inner(); initial -> top.e; endmodule module top(); event e; initial begin // Normal trigger -> e; // Nonblocking trigger ->> e; end endmodule class foo; event e; task wait_e(); ->e; endtask; endclass ================================================ FILE: tests/chapter-15/15.5.1--named-event-trigger-non-blocking.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: named_event_trigger_non_blocking :description: Trigger named event, non-blocking :tags: 15.5 :top_module: top :unsynthesizable: 1 */ module inner(); initial ->> top.e; endmodule module top(); event e; initial begin // Nonblocking trigger ->> e; end endmodule class foo; event e; task wait_e(); ->> e; endtask; endclass ================================================ FILE: tests/chapter-15/15.5.2--named-event-wait.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: named_event_wait :description: Wait for a named event :tags: 15.5 :top_module: top :unsynthesizable: 1 */ module inner(); initial @top.e; endmodule module top(); event e; initial begin @ e; end endmodule class foo; event e; task wait_e(); @e; endtask; endclass ================================================ FILE: tests/chapter-16/16.10--property-local-var-fail.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_local_var_fail_test :description: failing property with local variables :should_fail_because: pipeline increments value by 4 but property expects incrementation by 3 :type: simulation :tags: 16.10 :unsynthesizable: 1 */ module clk_gen( input valid, input clk, output reg [7:0] out, input [7:0] in ); reg [7:0] data_reg_0; reg [7:0] data_reg_1; reg [7:0] data_reg_2; initial begin data_reg_0 = 0; data_reg_1 = 0; data_reg_2 = 0; out = 0; end always @(posedge clk) begin if (valid) begin data_reg_0 <= in + 1; data_reg_1 <= data_reg_0 + 1; data_reg_2 <= data_reg_1 + 1; out <= data_reg_2 + 1; end end endmodule: clk_gen module top(); int cycle; logic valid; logic clk; logic [7:0] out; logic [7:0] in; clk_gen dut(.valid(valid), .clk(clk), .out(out), .in(in)); initial begin cycle = 0; clk = 0; valid = 1; end property prop; int x; @(posedge clk) (valid, x = in) |-> ##4 (out == x + 3); endproperty assert property (prop) else $error($sformatf("property check failed :assert: (False)")); assign in = cycle; always @(posedge clk) cycle <= cycle + 1; initial begin forever begin #(50) clk = ~clk; end end initial #1000 $finish; endmodule ================================================ FILE: tests/chapter-16/16.10--property-local-var-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_local_var_test_uvm :description: property with local variables in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input valid, input clk, output reg [7:0] out, input [7:0] in ); reg [7:0] data_reg_0; reg [7:0] data_reg_1; reg [7:0] data_reg_2; initial begin data_reg_0 = 0; data_reg_1 = 0; data_reg_2 = 0; out = 0; end always @(posedge clk) begin if (valid) begin data_reg_0 <= in + 1; data_reg_1 <= data_reg_0 + 1; data_reg_2 <= data_reg_1 + 1; out <= data_reg_2 + 1; end end endmodule: clk_gen interface clk_gen_if( output bit valid, output bit clk, input [7:0] out, output bit [7:0] in ); endinterface: clk_gen_if string label = "SEQUENCE_LOCAL_VAR_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; int cycle = 0; clk_gen_if dif(); clk_gen dut(.valid(dif.valid), .clk(dif.clk), .out(dif.out), .in(dif.in)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk = 0; dif.valid = 1; run_test(); end property prop; int x; @(posedge dif.clk) (dif.valid, x = dif.in) |-> ##4 (dif.out == x + 4); endproperty assert property (prop) else `uvm_info(label, $sformatf("property check failed :assert: (False)"), UVM_LOW); assign dif.in = cycle; always @(posedge dif.clk) cycle <= cycle + 1; initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.10--property-local-var.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_local_var_test :description: property with local variables :type: simulation elaboration parsing :tags: 16.10 :unsynthesizable: 1 */ module clk_gen( input valid, input clk, output reg [7:0] out, input [7:0] in ); reg [7:0] data_reg_0; reg [7:0] data_reg_1; reg [7:0] data_reg_2; initial begin data_reg_0 = 0; data_reg_1 = 0; data_reg_2 = 0; out = 0; end always @(posedge clk) begin if (valid) begin data_reg_0 <= in + 1; data_reg_1 <= data_reg_0 + 1; data_reg_2 <= data_reg_1 + 1; out <= data_reg_2 + 1; end end endmodule: clk_gen module top(); int cycle; logic valid; logic clk; logic [7:0] out; logic [7:0] in; clk_gen dut(.valid(valid), .clk(clk), .out(out), .in(in)); initial begin cycle = 0; clk = 0; valid = 1; end property prop; int x; @(posedge clk) (valid, x = in) |-> ##4 (out == x + 4); endproperty assert property (prop) else $error($sformatf("property check failed :assert: (False)")); assign in = cycle; always @(posedge clk) cycle <= cycle + 1; initial begin forever begin #(50) clk = ~clk; end end initial #1000 $finish; endmodule ================================================ FILE: tests/chapter-16/16.10--sequence-local-var-fail.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_local_var_fail_test :description: failing sequence with local variables :should_fail_because: pipeline increments value by 4 but sequence expects incrementation by 3 :type: simulation :tags: 16.10 :unsynthesizable: 1 */ module clk_gen( input valid, input clk, output reg [7:0] out, input [7:0] in ); reg [7:0] data_reg_0; reg [7:0] data_reg_1; reg [7:0] data_reg_2; initial begin data_reg_0 = 0; data_reg_1 = 0; data_reg_2 = 0; out = 0; end always @(posedge clk) begin if (valid) begin data_reg_0 <= in + 1; data_reg_1 <= data_reg_0 + 1; data_reg_2 <= data_reg_1 + 1; out <= data_reg_2 + 1; end end endmodule: clk_gen module top(); int cycle; logic valid; logic clk; logic [7:0] out; logic [7:0] in; clk_gen dut(.valid(valid), .clk(clk), .out(out), .in(in)); initial begin cycle = 0; clk = 0; valid = 1; end sequence seq; int x; @(posedge clk) (valid, x = in) ##4 (out == x + 3); endsequence assert property (seq) else $error($sformatf("sequence check failed :assert: (False)")); assign in = cycle; always @(posedge clk) cycle <= cycle + 1; initial begin forever begin #(50) clk = ~clk; end end initial #1000 $finish; endmodule ================================================ FILE: tests/chapter-16/16.10--sequence-local-var-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_local_var_test_uvm :description: sequence with local variables in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input valid, input clk, output reg [7:0] out, input [7:0] in ); reg [7:0] data_reg_0; reg [7:0] data_reg_1; reg [7:0] data_reg_2; initial begin data_reg_0 = 0; data_reg_1 = 0; data_reg_2 = 0; out = 0; end always @(posedge clk) begin if (valid) begin data_reg_0 <= in + 1; data_reg_1 <= data_reg_0 + 1; data_reg_2 <= data_reg_1 + 1; out <= data_reg_2 + 1; end end endmodule: clk_gen interface clk_gen_if( output bit valid, output bit clk, input [7:0] out, output bit [7:0] in ); endinterface: clk_gen_if string label = "SEQUENCE_LOCAL_VAR_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; int cycle = 0; clk_gen_if dif(); clk_gen dut(.valid(dif.valid), .clk(dif.clk), .out(dif.out), .in(dif.in)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk = 0; dif.valid = 1; run_test(); end sequence seq; int x; @(posedge dif.clk) (dif.valid, x = dif.in) ##4 (dif.out == x + 4); endsequence assert property (seq) else `uvm_error(label, $sformatf("sequence check failed :assert: (False)")); assign dif.in = cycle; always @(posedge dif.clk) cycle <= cycle + 1; initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.10--sequence-local-var.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_local_var_test :description: sequence with local variables :type: simulation elaboration parsing :tags: 16.10 :unsynthesizable: 1 */ module clk_gen( input valid, input clk, output reg [7:0] out, input [7:0] in ); reg [7:0] data_reg_0; reg [7:0] data_reg_1; reg [7:0] data_reg_2; initial begin data_reg_0 = 0; data_reg_1 = 0; data_reg_2 = 0; out = 0; end always @(posedge clk) begin if (valid) begin data_reg_0 <= in + 1; data_reg_1 <= data_reg_0 + 1; data_reg_2 <= data_reg_1 + 1; out <= data_reg_2 + 1; end end endmodule: clk_gen module top(); int cycle; logic valid; logic clk; logic [7:0] out; logic [7:0] in; clk_gen dut(.valid(valid), .clk(clk), .out(out), .in(in)); initial begin cycle = 0; clk = 0; valid = 1; end sequence seq; int x; @(posedge clk) (valid, x = in) ##4 (out == x + 4); endsequence assert property (seq) else $error($sformatf("sequence check failed :assert: (False)")); assign in = cycle; always @(posedge clk) cycle <= cycle + 1; initial begin forever begin #(50) clk = ~clk; end end initial #1000 $finish; endmodule ================================================ FILE: tests/chapter-16/16.11--sequence-subroutine-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_subroutine_test_uvm :description: sequence with subroutine in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input valid, input clk, output reg [7:0] out, input [7:0] in ); reg [7:0] data_reg_0; reg [7:0] data_reg_1; reg [7:0] data_reg_2; initial begin data_reg_0 = 0; data_reg_1 = 0; data_reg_2 = 0; out = 0; end always @(posedge clk) begin if (valid) begin data_reg_0 <= in + 1; data_reg_1 <= data_reg_0 + 1; data_reg_2 <= data_reg_1 + 1; out <= data_reg_2 + 1; end end endmodule: clk_gen interface clk_gen_if( output bit valid, output bit clk, input [7:0] out, output bit [7:0] in ); endinterface: clk_gen_if string label = "SEQUENCE_LOCAL_VAR_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; int cycle = 0; clk_gen_if dif(); clk_gen dut(.valid(dif.valid), .clk(dif.clk), .out(dif.out), .in(dif.in)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk = 0; dif.valid = 1; run_test(); end sequence seq; int x; @(posedge dif.clk) (dif.valid, x = dif.in) ##4 (dif.out == x + 4, $display("print in sequence")); endsequence assert property (seq) else `uvm_info(label, $sformatf("sequence check failed"), UVM_LOW); assign dif.in = cycle; always @(posedge dif.clk) cycle <= cycle + 1; initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.12--property-disable-iff.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_disable_iff_min_test :description: minimal property disable iff test :tags: 16.12 */ module top(); logic clk; logic a; logic b; logic c; assert property ( @(posedge clk) disable iff (a) b |-> c ); endmodule ================================================ FILE: tests/chapter-16/16.12--property-disj.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_disj_test :description: property || test :tags: 16.12 */ module top(); logic clk; logic a; logic b; assert property ( @(posedge clk) a || b ); endmodule ================================================ FILE: tests/chapter-16/16.12--property-iff.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_iff_test :description: property iff test :tags: 16.12 */ module top(); logic clk; logic a; logic b; assert property ( @(posedge clk) a iff b ); endmodule ================================================ FILE: tests/chapter-16/16.12--property-interface-prec-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_interface_prec_test_uvm :description: interface property with precondition in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mem_ctrl ( input clk, output reg read, output reg write, output reg [7:0] addr, output reg [7:0] dout, input [7:0] din ); reg phase; reg [7:0] addr_i; initial begin phase = 0; read = 0; write = 0; end always @(posedge clk) begin read <= 0; write <= 0; addr <= addr_i; if(phase) begin read <= 1; end else begin write <= 1; end dout <= din; addr_i <= addr_i + 1; phase <= ~phase; end endmodule: mem_ctrl string label = "PROPERTY_UVM"; interface mem_ctrl_if( output bit clk, input read, input write, input [7:0] addr, input [7:0] dout, output reg [7:0] din ); assert property (@(posedge clk) read |=> write ) else `uvm_error(label, $sformatf("write after read :assert: (False)")); endinterface: mem_ctrl_if class env extends uvm_env; virtual mem_ctrl_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name( get_full_name(), "mem_ctrl_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mem_ctrl_if dif(); mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din)); initial begin environment = new("env"); uvm_resource_db#(virtual mem_ctrl_if)::set("env", "mem_ctrl_if", dif); dif.clk = 0; run_test(); end initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.12--property-interface-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_interface_test_uvm :description: interface property test with UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mem_ctrl ( input clk, output reg read, output reg write, output reg [7:0] addr, output reg [7:0] dout, input [7:0] din ); reg phase; reg [7:0] addr_i; initial begin phase = 0; read = 0; write = 0; end always @(posedge clk) begin read <= 0; write <= 0; addr <= addr_i; if(phase) begin read <= 1; end else begin write <= 1; end dout <= din; addr_i <= addr_i + 1; phase <= ~phase; end endmodule: mem_ctrl string label = "PROPERTY_INTERFACE_UVM"; interface mem_ctrl_if( output bit clk, input read, input write, input [7:0] addr, input [7:0] dout, output reg [7:0] din ); assert property (@(posedge clk) !(read & write)) else `uvm_error(label, $sformatf("read and write both asserted :assert: (False)")); endinterface: mem_ctrl_if class env extends uvm_env; virtual mem_ctrl_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name( get_full_name(), "mem_ctrl_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mem_ctrl_if dif(); mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din)); initial begin environment = new("env"); uvm_resource_db#(virtual mem_ctrl_if)::set("env", "mem_ctrl_if", dif); dif.clk = 0; run_test(); end initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.12--property-prec-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_prec_test_uvm :description: property with precondition in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mem_ctrl ( input clk, output reg read, output reg write, output reg [7:0] addr, output reg [7:0] dout, input [7:0] din ); reg phase; reg [7:0] addr_i; initial begin phase = 0; read = 0; write = 0; end always @(posedge clk) begin read <= 0; write <= 0; addr <= addr_i; if(phase) begin read <= 1; end else begin write <= 1; end dout <= din; addr_i <= addr_i + 1; phase <= ~phase; end endmodule: mem_ctrl interface mem_ctrl_if( output bit clk, input read, input write, input [7:0] addr, input [7:0] dout, output reg [7:0] din ); endinterface: mem_ctrl_if string label = "PROPERTY_UVM"; class env extends uvm_env; virtual mem_ctrl_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name( get_full_name(), "mem_ctrl_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mem_ctrl_if dif(); mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din)); initial begin environment = new("env"); uvm_resource_db#(virtual mem_ctrl_if)::set("env", "mem_ctrl_if", dif); dif.clk = 0; run_test(); end assert property (@(posedge dif.clk) dif.read |=> dif.write ) else `uvm_error(label, $sformatf("write after read :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.12--property-prec.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_prec_test :description: property with precondition test :tags: 16.12 */ module top(); logic clk; logic a; logic b; assert property ( @(posedge clk) a |-> b); endmodule ================================================ FILE: tests/chapter-16/16.12--property-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_test_uvm :description: property test with UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mem_ctrl ( input clk, output reg read, output reg write, output reg [7:0] addr, output reg [7:0] dout, input [7:0] din ); reg phase; reg [7:0] addr_i; initial begin phase = 0; read = 0; write = 0; end always @(posedge clk) begin read <= 0; write <= 0; addr <= addr_i; if(phase) begin read <= 1; end else begin write <= 1; end dout <= din; addr_i <= addr_i + 1; phase <= ~phase; end endmodule: mem_ctrl interface mem_ctrl_if( output bit clk, input read, input write, input [7:0] addr, input [7:0] dout, output reg [7:0] din ); endinterface: mem_ctrl_if string label = "PROPERTY_UVM"; class env extends uvm_env; virtual mem_ctrl_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name( get_full_name(), "mem_ctrl_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mem_ctrl_if dif(); mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din)); initial begin environment = new("env"); uvm_resource_db#(virtual mem_ctrl_if)::set("env", "mem_ctrl_if", dif); dif.clk = 0; run_test(); end assert property (@(posedge dif.clk) !(dif.read & dif.write)) else `uvm_error(label, $sformatf("read and write both asserted :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.12--property.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_test :description: property test :tags: 16.12 */ module top(); logic clk; logic a; assert property ( @(posedge clk) (a == 1)); endmodule ================================================ FILE: tests/chapter-16/16.13--sequence-multiclock-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_multiclock_test_uvm :description: sequence with local variables in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input clk0, input clk1, output reg out0, output reg out1 ); initial begin out0 = 0; out1 = 0; end always @(posedge clk0) begin out0 <= 1; end always @(posedge clk1) begin out1 <= 1; end endmodule: clk_gen interface clk_gen_if( output bit clk0, output bit clk1, input out0, input out1 ); endinterface: clk_gen_if string label = "SEQUENCE_MULTICLOCK_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk0); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; clk_gen_if dif(); clk_gen dut(.clk0(dif.clk0), .clk1(dif.clk1), .out0(dif.out0), .out1(dif.out1)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk0 = 0; dif.clk1 = 0; run_test(); end sequence seq; @(posedge dif.clk0) ##1 dif.out0 ##1 @(posedge dif.clk1) dif.out1; endsequence assert property (seq) else `uvm_error(label, $sformatf("sequence check failed :assert: (False)")); initial begin forever begin #(50) dif.clk0 = ~dif.clk0; #(150) dif.clk1 = ~dif.clk1; end end endmodule ================================================ FILE: tests/chapter-16/16.14--assume-property-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assume_property_test_uvm :description: assume property test with UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mem_ctrl ( input clk, output reg read, output reg write, output reg [7:0] addr, output reg [7:0] dout, input [7:0] din ); reg phase; reg [7:0] addr_i; initial begin phase = 0; read = 0; write = 0; end always @(posedge clk) begin read <= 0; write <= 0; addr <= addr_i; if(phase) begin read <= 1; end else begin write <= 1; end dout <= din; addr_i <= addr_i + 1; phase <= ~phase; end endmodule: mem_ctrl interface mem_ctrl_if( output bit clk, input read, input write, input [7:0] addr, input [7:0] dout, output reg [7:0] din ); endinterface: mem_ctrl_if string label = "PROPERTY_UVM"; class env extends uvm_env; virtual mem_ctrl_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name( get_full_name(), "mem_ctrl_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mem_ctrl_if dif(); mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din)); initial begin environment = new("env"); uvm_resource_db#(virtual mem_ctrl_if)::set("env", "mem_ctrl_if", dif); dif.clk = 0; run_test(); end assume property (@(posedge dif.clk) !(dif.read & dif.write)) else `uvm_error(label, $sformatf("read and write both asserted :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.14--assume-property.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assume_property_test :description: assume property test :tags: 16.14 */ module top(); logic clk; logic a; assume property ( @(posedge clk) (a == 1)); endmodule ================================================ FILE: tests/chapter-16/16.15--property-disable-iff-fail.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_disable_iff_fail_test :description: failing property with disable iff :should_fail_because: disable iff uses wrong reset polarity :type: simulation :tags: 16.15 :unsynthesizable: 1 */ module clk_gen( input rst, input clk, output reg out ); initial begin out = 0; end always @(posedge clk or posedge rst) begin if (rst) out <= 0; else out <= 1; end endmodule: clk_gen module top(); logic rst; logic clk; logic out; clk_gen dut(.rst(rst), .clk(clk), .out(out)); initial begin clk = 0; rst = 1; end property prop; @(posedge clk) disable iff (~rst) out; endproperty assert property (prop) else $error($sformatf("property check failed :assert: (True)")); initial begin forever begin #(50) clk = ~clk; end end initial #1000 $finish; endmodule ================================================ FILE: tests/chapter-16/16.15--property-disable-iff.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_disable_iff_test :description: property with disable iff :type: simulation elaboration parsing :tags: 16.15 :unsynthesizable: 1 */ module clk_gen( input rst, input clk, output reg out ); initial begin out = 0; end always @(posedge clk or posedge rst) begin if (rst) out <= 0; else out <= 1; end endmodule: clk_gen module top(); logic rst; logic clk; logic out; clk_gen dut(.rst(rst), .clk(clk), .out(out)); initial begin clk = 0; rst = 1; end property prop; @(posedge clk) disable iff (rst) out; endproperty assert property (prop) else $error($sformatf("property check failed :assert: (False)")); initial begin forever begin #(50) clk = ~clk; end end initial #1000 $finish; endmodule ================================================ FILE: tests/chapter-16/16.15--property-iff-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: property_disable_iff_test_uvm :description: property with disable iff test with UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input rst, input clk, output reg out ); initial begin out = 0; end always @(posedge clk or posedge rst) begin if (rst) out <= 0; else out <= 1; end endmodule: clk_gen interface clk_gen_if( output bit rst, output bit clk, input out ); endinterface: clk_gen_if string label = "IFF_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; clk_gen_if dif(); clk_gen dut(.clk(dif.clk), .rst(dif.rst), .out(dif.out)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk = 0; dif.rst = 1; run_test(); end property prop; @(posedge dif.clk) disable iff (dif.rst) dif.out; endproperty assert property (prop) else $error($sformatf("property check failed :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.17--expect-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: expect_test_uvm :description: expect in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mem_ctrl ( input clk, output reg read, output reg write, output reg [7:0] addr, output reg [7:0] dout, input [7:0] din ); reg phase; reg [7:0] addr_i; initial begin phase = 0; read = 1; write = 0; end always @(posedge clk) begin read <= 0; write <= 0; addr <= addr_i; if(phase) begin read <= 1; end else begin write <= 1; end dout <= din; addr_i <= addr_i + 1; phase <= ~phase; end endmodule: mem_ctrl interface mem_ctrl_if( output bit clk, input read, input write, input [7:0] addr, input [7:0] dout, output reg [7:0] din ); endinterface: mem_ctrl_if string label = "EXPECT_UVM"; class env extends uvm_env; virtual mem_ctrl_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name( get_full_name(), "mem_ctrl_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(4) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mem_ctrl_if dif(); mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din)); initial begin environment = new("env"); uvm_resource_db#(virtual mem_ctrl_if)::set("env", "mem_ctrl_if", dif); dif.clk = 0; run_test(); end initial begin expect (@(posedge dif.clk) dif.read ##1 dif.write) else `uvm_error(label, $sformatf("expect failed :assert: (False)")); end initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.17--expect.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: expect_test :description: expect test :tags: 16.17 */ module top(); logic clk; logic a; logic b; initial begin expect (@(posedge clk) a ##1 b); end endmodule ================================================ FILE: tests/chapter-16/16.2--assert-final-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assert_final_test_uvm :description: assert final test with UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module inverter ( input [7:0] a, output [7:0] b ); assign b = !a; endmodule: inverter interface inverter_if( output reg [7:0] a, input [7:0] b ); endinterface: inverter_if string label = "ASSERT_FINAL_UVM"; class env extends uvm_env; virtual inverter_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual inverter_if)::read_by_name( get_full_name(), "inverter_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin int a = 8'h35; m_if.a <= a; assert final (m_if.a != m_if.b) else $error($sformatf("assert failed :assert: (False)")); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top; env environment; inverter_if dif(); inverter dut(.a(dif.a), .b(dif.b)); initial begin environment = new("env"); uvm_resource_db#(virtual inverter_if)::set("env", "inverter_if", dif); run_test(); end endmodule ================================================ FILE: tests/chapter-16/16.2--assert-final.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assert_final_test :description: assert final test :tags: 16.4 */ module top(); logic a = 1; assert final (a != 0); endmodule ================================================ FILE: tests/chapter-16/16.2--assert-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assert_test_uvm :description: assert test with UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module adder ( input clk, input [7:0] a, input [7:0] b, output reg [8:0] c ); always @ (posedge clk) begin c <= a + b; end endmodule: adder interface adder_if( output bit clk, output reg [7:0] a, output reg [7:0] b, input [8:0] c ); endinterface: adder_if string label = "ASSERT_UVM"; class env extends uvm_env; virtual adder_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual adder_if)::read_by_name( get_full_name(), "adder_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin int a = 8'h35, b = 8'h79; @(m_if.clk); m_if.a <= a; m_if.b <= b; repeat(3) @(m_if.clk); assert (m_if.c == (a + b)) else `uvm_error(label, $sformatf("c(%0d) != a + b(%0d) :assert: (False)", m_if.c, a + b)); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top; env environment; adder_if dif(); adder dut(.clk(dif.clk), .a(dif.a), .b(dif.b), .c(dif.c)); initial begin environment = new("env"); uvm_resource_db#(virtual adder_if)::set("env", "adder_if", dif); dif.clk = 0; run_test(); end initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.2--assert.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assert_test :description: assert test :tags: 16.2 */ module top(); logic a = 1; initial assert (a != 0); endmodule ================================================ FILE: tests/chapter-16/16.2--assert0-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assert0_test_uvm :description: assert0 test with UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module inverter ( input [7:0] a, output [7:0] b ); assign b = !a; endmodule: inverter interface inverter_if( output reg [7:0] a, input [7:0] b ); endinterface: inverter_if string label = "ASSERT0_UVM"; class env extends uvm_env; virtual inverter_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual inverter_if)::read_by_name( get_full_name(), "inverter_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin int a = 8'h35; m_if.a <= a; assert #0 (m_if.a != m_if.b) else $error($sformatf("assert failed :assert: (False)")); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top; env environment; inverter_if dif(); inverter dut(.a(dif.a), .b(dif.b)); initial begin environment = new("env"); uvm_resource_db#(virtual inverter_if)::set("env", "inverter_if", dif); run_test(); end endmodule ================================================ FILE: tests/chapter-16/16.2--assert0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assert0_test :description: assert #0 test :tags: 16.4 */ module top(); logic a = 1; assert #0 (a != 0); endmodule ================================================ FILE: tests/chapter-16/16.2--assume-final.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assume_final_test :description: assume final test :tags: 16.4 */ module top(input logic a); assume final (a != 0); endmodule ================================================ FILE: tests/chapter-16/16.2--assume-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assume_test_uvm :description: assert test with UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module adder ( input clk, input [7:0] a, input [7:0] b, output reg [8:0] c ); always @ (posedge clk) begin c <= a + b; end endmodule: adder interface adder_if( output bit clk, output reg [7:0] a, output reg [7:0] b, input [8:0] c ); endinterface: adder_if string label = "ASSERT_UVM"; class env extends uvm_env; virtual adder_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual adder_if)::read_by_name( get_full_name(), "adder_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin int a = 8'h35, b = 8'h79; @(m_if.clk); m_if.a <= a; m_if.b <= b; repeat(3) @(m_if.clk); assume (m_if.c == (a + b)) else `uvm_error(label, $sformatf("c(%0d) != a + b(%0d) :assert: (False)", m_if.c, a + b)); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top; env environment; adder_if dif(); adder dut(.clk(dif.clk), .a(dif.a), .b(dif.b), .c(dif.c)); initial begin environment = new("env"); uvm_resource_db#(virtual adder_if)::set("env", "adder_if", dif); dif.clk = 0; run_test(); end initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.2--assume.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assume_test :description: assume test :tags: 16.2 */ module top(input logic a); initial assume (a != 0); endmodule ================================================ FILE: tests/chapter-16/16.2--assume0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assume0_test :description: assume #0 test :tags: 16.4 */ module top(input logic a); assume #0 (a != 0); endmodule ================================================ FILE: tests/chapter-16/16.2--cover-final.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cover_final_test :description: cover final test :tags: 16.4 */ module top(); logic a = 1; cover final (a != 0); endmodule ================================================ FILE: tests/chapter-16/16.2--cover.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cover_test :description: cover test :tags: 16.2 */ module top(); logic a = 1; initial cover (a != 0); endmodule ================================================ FILE: tests/chapter-16/16.2--cover0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cover0_test :description: cover #0 test :tags: 16.4 */ module top(); logic a = 1; cover #0 (a != 0); endmodule ================================================ FILE: tests/chapter-16/16.7--sequence-and-range-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_range_and_op_test_uvm :description: sequence with range and "and" operator in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mod ( input clk, input req, output reg gnt0, output reg gnt1, output reg gnt2 ); int cnt = 0; bit req_old = 0; initial begin gnt0 = 0; gnt1 = 0; gnt2 = 0; end always @(posedge clk) begin req_old <= req; if (req & ~req_old) begin cnt <= 0; gnt0 <= 0; gnt1 <= 0; gnt2 <= 0; end else begin if (cnt < 16) begin cnt <= cnt+1; end if (cnt == 3) gnt0 <= 1; if (cnt == 6) gnt1 <= 1; if (cnt == 7) gnt2 <= 1; end end endmodule: mod interface mod_if( output bit clk, output bit req, input gnt0, input gnt1, input gnt2 ); endinterface: mod_if string label = "SEQUENCE_AND_UVM"; class env extends uvm_env; virtual mod_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mod_if)::read_by_name( get_full_name(), "mod_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mod_if dif(); mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2)); initial begin environment = new("env"); uvm_resource_db#(virtual mod_if)::set("env", "mod_if", dif); dif.clk = 0; run_test(); end initial begin dif.req = 1; end sequence seq; @(posedge dif.clk) ((dif.req ##[1:6] dif.gnt0) and (dif.req ##[1:9] dif.gnt1)) ##0 dif.gnt2; endsequence assert property (seq) else `uvm_error(label, $sformatf("seq failed :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.7--sequence-and-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_and_op_test_uvm :description: sequence with "and" operator in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mod ( input clk, input req, output reg gnt0, output reg gnt1, output reg gnt2 ); int cnt = 0; bit req_old = 0; initial begin gnt0 = 0; gnt1 = 0; gnt2 = 0; end always @(posedge clk) begin req_old <= req; if (req & ~req_old) begin cnt <= 0; gnt0 <= 0; gnt1 <= 0; gnt2 <= 0; end else begin if (cnt < 16) begin cnt <= cnt+1; end if (cnt == 3) gnt0 <= 1; if (cnt == 6) gnt1 <= 1; if (cnt == 7) gnt2 <= 1; end end endmodule: mod interface mod_if( output bit clk, output bit req, input gnt0, input gnt1, input gnt2 ); endinterface: mod_if string label = "SEQUENCE_AND_UVM"; class env extends uvm_env; virtual mod_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mod_if)::read_by_name( get_full_name(), "mod_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mod_if dif(); mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2)); initial begin environment = new("env"); uvm_resource_db#(virtual mod_if)::set("env", "mod_if", dif); dif.clk = 0; run_test(); end initial begin dif.req = 1; end sequence seq; @(posedge dif.clk) ((dif.req ##5 dif.gnt0) and (dif.req ##8 dif.gnt1)) ##0 dif.gnt2; endsequence assert property (seq) else `uvm_error(label, $sformatf("seq failed :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.7--sequence-intersect-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_intersect_op_test_uvm :description: sequence with "intersect" operator in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mod ( input clk, input req, output reg gnt0, output reg gnt1, output reg gnt2 ); int cnt = 0; bit req_old = 0; initial begin gnt0 = 0; gnt1 = 0; gnt2 = 0; end always @(posedge clk) begin req_old <= req; if (req & ~req_old) begin cnt <= 0; gnt0 <= 0; gnt1 <= 0; gnt2 <= 0; end else begin if (cnt < 16) begin cnt <= cnt+1; end if (cnt == 3) gnt0 <= 1; if (cnt == 3) gnt1 <= 1; if (cnt == 7) gnt2 <= 1; end end endmodule: mod interface mod_if( output bit clk, output bit req, input gnt0, input gnt1, input gnt2 ); endinterface: mod_if string label = "SEQUENCE_AND_UVM"; class env extends uvm_env; virtual mod_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mod_if)::read_by_name( get_full_name(), "mod_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mod_if dif(); mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2)); initial begin environment = new("env"); uvm_resource_db#(virtual mod_if)::set("env", "mod_if", dif); dif.clk = 0; run_test(); end initial begin dif.req = 1; end sequence seq; @(posedge dif.clk) (dif.req ##5 dif.gnt0) intersect (dif.req ##[1:9] dif.gnt1); endsequence assert property (seq) else `uvm_error(label, $sformatf("seq failed :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.7--sequence-or-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_or_op_test_uvm :description: sequence with "or" operator in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mod ( input clk, input req, output reg gnt0, output reg gnt1, output reg gnt2 ); int cnt = 0; bit req_old = 0; initial begin gnt0 = 0; gnt1 = 0; gnt2 = 0; end always @(posedge clk) begin req_old <= req; if (req & ~req_old) begin cnt <= 0; gnt0 <= 0; gnt1 <= 0; gnt2 <= 0; end else begin if (cnt < 16) begin cnt <= cnt+1; end if (cnt == 3) gnt0 <= 1; if (cnt == 6) gnt1 <= 1; if (cnt == 7) gnt2 <= 1; end end endmodule: mod interface mod_if( output bit clk, output bit req, input gnt0, input gnt1, input gnt2 ); endinterface: mod_if string label = "SEQUENCE_AND_UVM"; class env extends uvm_env; virtual mod_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mod_if)::read_by_name( get_full_name(), "mod_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mod_if dif(); mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2)); initial begin environment = new("env"); uvm_resource_db#(virtual mod_if)::set("env", "mod_if", dif); dif.clk = 0; run_test(); end initial begin dif.req = 1; end sequence seq; @(posedge dif.clk) (dif.req ##5 dif.gnt0) or (dif.req ##3 dif.gnt1); endsequence assert property (seq) else `uvm_error(label, $sformatf("seq failed :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.7--sequence-throughout-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_throughout_op_test_uvm :description: sequence with "throughout" operator in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mod ( input clk, input req, output reg gnt0, output reg gnt1, output gnt2 ); int cnt = 0; bit req_old = 0; initial begin gnt0 = 0; gnt1 = 0; end assign gnt2 = req; always @(posedge clk) begin req_old <= req; if (req & ~req_old) begin cnt <= 0; gnt0 <= 0; gnt1 <= 0; end else begin if (cnt < 16) begin cnt <= cnt+1; end if (cnt == 3) gnt0 <= 1; if (cnt == 3) gnt1 <= 1; end end endmodule: mod interface mod_if( output bit clk, output bit req, input gnt0, input gnt1, input gnt2 ); endinterface: mod_if string label = "SEQUENCE_AND_UVM"; class env extends uvm_env; virtual mod_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mod_if)::read_by_name( get_full_name(), "mod_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mod_if dif(); mod dut(.clk(dif.clk), .req(dif.req), .gnt0(dif.gnt0), .gnt1(dif.gnt1), .gnt2(dif.gnt2)); initial begin environment = new("env"); uvm_resource_db#(virtual mod_if)::set("env", "mod_if", dif); dif.clk = 0; run_test(); end initial begin dif.req = 1; end sequence seq; @(posedge dif.clk) (dif.req ##5 dif.gnt0) intersect (dif.req ##[1:9] dif.gnt1); endsequence assert property (@(posedge dif.clk) dif.gnt2 throughout seq) else `uvm_error(label, $sformatf("seq failed :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.7--sequence-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_test_uvm :description: sequence in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module mem_ctrl ( input clk, output reg read, output reg write, output reg [7:0] addr, output reg [7:0] dout, input [7:0] din ); reg phase; reg [7:0] addr_i; initial begin phase = 0; read = 1; write = 0; end always @(posedge clk) begin read <= 0; write <= 0; addr <= addr_i; if(phase) begin read <= 1; end else begin write <= 1; end dout <= din; addr_i <= addr_i + 1; phase <= ~phase; end endmodule: mem_ctrl interface mem_ctrl_if( output bit clk, input read, input write, input [7:0] addr, input [7:0] dout, output reg [7:0] din ); endinterface: mem_ctrl_if string label = "SEQUENCE_UVM"; class env extends uvm_env; virtual mem_ctrl_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual mem_ctrl_if)::read_by_name( get_full_name(), "mem_ctrl_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(1) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; mem_ctrl_if dif(); mem_ctrl dut(.clk(dif.clk), .read(dif.read), .write(dif.write), .addr(dif.addr), .dout(dif.dout), .din(dif.din)); initial begin environment = new("env"); uvm_resource_db#(virtual mem_ctrl_if)::set("env", "mem_ctrl_if", dif); dif.clk = 0; run_test(); end sequence seq; @(posedge dif.clk) dif.read ##1 dif.write; endsequence assert property (seq) else `uvm_error(label, $sformatf("seq failed :assert: (False)")); initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.7--sequence.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_test :description: sequence test :tags: 16.7 :unsynthesizable: 1 */ module top(); logic clk; logic a; logic b; sequence seq; @(posedge clk) a ##1 b; endsequence assert property (seq); endmodule ================================================ FILE: tests/chapter-16/16.9--sequence-changed-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_changed_test_uvm :description: sequence with "changed" task in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input clk, output out ); int cnt = 0; bit clk_reg = 0; assign out = clk_reg; initial begin cnt = 0; clk_reg = 0; end always @(posedge clk) begin cnt <= cnt + 1; if (cnt > 5) begin clk_reg = 1; cnt = 5; end end endmodule: clk_gen interface clk_gen_if( output bit clk, input out ); endinterface: clk_gen_if string label = "SEQUENCE_FUNC_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; int cycle = 0; clk_gen_if dif(); clk_gen dut(.clk(dif.clk), .out(dif.out)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk = 0; run_test(); end sequence seq; @(posedge dif.clk) $changed(dif.out); endsequence assert property (seq) else `uvm_info(label, $sformatf("$changed(dif.out) failed :assert: (%d != 8)", cycle), UVM_LOW); always @(posedge dif.clk) cycle <= cycle + 1; initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.9--sequence-cons-repetition.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_consecutive_repetition_test :description: sequence with consecutive repetition operator test :tags: 16.9 :unsynthesizable: 1 */ module top(); logic clk; logic a; logic b; sequence seq; @(posedge clk) b ##1 a [*2:10] ##1 b; endsequence assert property (seq); endmodule ================================================ FILE: tests/chapter-16/16.9--sequence-fell-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_fell_test_uvm :description: sequence with "fell" task in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input clk, output out ); int cnt = 0; bit clk_reg = 0; assign out = clk_reg; initial begin cnt = 0; clk_reg = 1; end always @(posedge clk) begin cnt <= cnt + 1; if (cnt > 5) begin clk_reg = 0; cnt = 5; end end endmodule: clk_gen interface clk_gen_if( output bit clk, input out ); endinterface: clk_gen_if string label = "SEQUENCE_FUNC_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; int cycle = 0; clk_gen_if dif(); clk_gen dut(.clk(dif.clk), .out(dif.out)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk = 0; run_test(); end sequence seq; @(posedge dif.clk) $fell(dif.out); endsequence assert property (seq) else `uvm_info(label, $sformatf("$fell(dif.out) failed :assert: (%d != 8)", cycle), UVM_LOW); always @(posedge dif.clk) cycle <= cycle + 1; initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.9--sequence-goto-repetition.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_goto_repetition_test :description: sequence with goto repetition operator test :tags: 16.9 :unsynthesizable: 1 */ module top(); logic clk; logic a; logic b; sequence seq; @(posedge clk) b ##1 a [->2:10] ##1 b; endsequence assert property (seq); endmodule ================================================ FILE: tests/chapter-16/16.9--sequence-noncons-repetition.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_nonconsecutive_repetition_test :description: sequence with nonconsecutive repetition operator test :tags: 16.9 :unsynthesizable: 1 */ module top(); logic clk; logic a; logic b; sequence seq; @(posedge clk) b ##1 a [=2:10] ##1 b; //should be equal to: b ##1 a ##1 a ##1 a ##1 b endsequence assert property (seq); endmodule ================================================ FILE: tests/chapter-16/16.9--sequence-past-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_past_test_uvm :description: sequence with "past" task in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input clk, output out ); int cnt = 0; bit clk_reg = 0; assign out = clk_reg; initial begin cnt = 0; clk_reg = 0; end always @(posedge clk) begin cnt <= cnt + 1; if (cnt > 5) begin clk_reg = 1; cnt = 5; end end endmodule: clk_gen interface clk_gen_if( output bit clk, input out ); endinterface: clk_gen_if string label = "SEQUENCE_FUNC_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; int cycle = 0; clk_gen_if dif(); clk_gen dut(.clk(dif.clk), .out(dif.out)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk = 0; run_test(); end sequence seq; @(posedge dif.clk) ~$past(dif.out) & dif.out; endsequence assert property (seq) else `uvm_info(label, $sformatf("$past(dif.out) failed :assert: (%d != 8)", cycle), UVM_LOW); always @(posedge dif.clk) cycle <= cycle + 1; initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.9--sequence-rose-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_rose_test_uvm :description: sequence with "rose" task in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input clk, output out ); int cnt = 0; bit clk_reg = 0; assign out = clk_reg; initial begin cnt = 0; clk_reg = 0; end always @(posedge clk) begin cnt <= cnt + 1; if (cnt > 5) begin clk_reg = 1; cnt = 5; end end endmodule: clk_gen interface clk_gen_if( output bit clk, input out ); endinterface: clk_gen_if string label = "SEQUENCE_FUNC_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; int cycle = 0; clk_gen_if dif(); clk_gen dut(.clk(dif.clk), .out(dif.out)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk = 0; run_test(); end sequence seq; @(posedge dif.clk) $rose(dif.out); endsequence assert property (seq) else `uvm_info(label, $sformatf("$rose(dif.out) failed :assert: (%d != 8)", cycle), UVM_LOW); always @(posedge dif.clk) cycle <= cycle + 1; initial begin forever begin #(50) dif.clk = ~dif.clk; end end endmodule ================================================ FILE: tests/chapter-16/16.9--sequence-stable-uvm.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequence_stable_test_uvm :description: sequence with "stable" task in UVM :type: simulation elaboration parsing :tags: uvm uvm-assertions :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" module clk_gen( input clk, output out ); assign out = 0; endmodule: clk_gen interface clk_gen_if( output bit clk, input out ); endinterface: clk_gen_if string label = "SEQUENCE_FUNC_UVM"; class env extends uvm_env; virtual clk_gen_if m_if; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction function void connect_phase(uvm_phase phase); `uvm_info(label, "Started connect phase", UVM_LOW); assert(uvm_resource_db#(virtual clk_gen_if)::read_by_name( get_full_name(), "clk_gen_if", m_if)); `uvm_info(label, "Finished connect phase", UVM_LOW); endfunction: connect_phase task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info(label, "Started run phase", UVM_LOW); begin repeat(10) @(posedge m_if.clk); end `uvm_info(label, "Finished run phase", UVM_LOW); phase.drop_objection(this); endtask: run_phase endclass module top(); env environment; int cycle = 0; clk_gen_if dif(); clk_gen dut(.clk(dif.clk), .out(dif.out)); initial begin environment = new("env"); uvm_resource_db#(virtual clk_gen_if)::set("env", "clk_gen_if", dif); dif.clk = 0; run_test(); end sequence seq; @(posedge dif.clk) $stable(dif.out); endsequence assert property (seq) else `uvm_info(label, $sformatf("$stable(dif.out) returned false :assert: (%d == 1)", cycle), UVM_LOW); initial begin forever begin #(50) dif.clk = ~dif.clk; cycle = cycle + 1; end end endmodule ================================================ FILE: tests/chapter-18/18.10--dynamic-constraint-modification_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dynamic_constraint_modification_0 :description: dynamic constraint modification test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c { b dist { 3 := 0, 10 := 1}; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize() with { b dist { 3 := 1, 10 := 0}; }; if(obj.b == 3) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.11--in-line-random-variable-control_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_random_variable-control_0 :description: in-line random variable control test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x = 0, y = 0; int v = 0, w = 0; constraint c { x < v && y > w; }; endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin /* random variables: v, w state variables: x, y */ obj.randomize(v, w); if(obj.x == 0 && obj.y == 0) begin `uvm_info("RESULT", $sformatf("obj.x = %0d obj.v = %0d obj.y = %0d obj.w = %0d SUCCESS", obj.x, obj.v, obj.y, obj.w), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d obj.v = %0d obj.y = %0d obj.w = %0d FAILED", obj.x, obj.v, obj.y, obj.w)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.11--in-line-random-variable-control_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_random_variable-control_1 :description: in-line random variable control test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; randc bit [7:0] x = 0, y = 0; bit [7:0] v = 0, w = 0; constraint c { x < v && y > w; }; endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin /* random variables: v, w state variables: x, y */ obj.randomize(v, w); if(obj.x == 0 && obj.y == 0) begin `uvm_info("RESULT", $sformatf("obj.x = %0d obj.v = %0d obj.y = %0d obj.w = %0d SUCCESS", obj.x, obj.v, obj.y, obj.w), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d obj.v = %0d obj.y = %0d obj.w = %0d FAILED", obj.x, obj.v, obj.y, obj.w)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.11.1--in-line-constraint-checker_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_constraint_checker_0 :description: in-line constraint checker test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; int v; constraint c1 { x < v; }; endclass class env extends uvm_env; a obj = new; int ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.x = 2; obj.v = 1; ret = obj.randomize(null); if(ret == 0 && obj.x == 2 && obj.v == 1) begin `uvm_info("RESULT", $sformatf("obj.x = %0d obj.v = %0d SUCCESS", obj.x, obj.v), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d obj.v = %0d FAILED", obj.x, obj.v)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.11.1--in-line-constraint-checker_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_constraint_checker_1 :description: in-line constraint checker test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; randc bit [7:0] x; bit [7:0] v; constraint c1 { x < v; }; endclass class env extends uvm_env; a obj = new; int ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.x = 2; obj.v = 1; ret = obj.randomize(null); if(ret == 0 && obj.x == 2 && obj.v == 1) begin `uvm_info("RESULT", $sformatf("obj.x = %0d obj.v = %0d SUCCESS", obj.x, obj.v), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d obj.v = %0d FAILED", obj.x, obj.v)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.12--randomization-of-scope-variables_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: randomization_of_scope_variables_0 :description: Randomization of scope variables - std::randomize() test :tags: 18.12 */ class a; function int do_randomize(); int x, success; success = std::randomize(x); return success; endfunction endclass ================================================ FILE: tests/chapter-18/18.12--randomization-of-scope-variables_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: randomization_of_scope_variables_1 :description: Randomization of scope variables - std::randomize() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; function int do_randomize(); int x, success; success = std::randomize(x); return success; endfunction endclass class env extends uvm_env; a obj = new; int ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin ret = obj.do_randomize(); if(ret == 1) begin `uvm_info("RESULT", $sformatf("ret = %0d SUCCESS", ret), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret = %0d FAILED", ret)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.12.1--adding-constraints-to-scope-variables_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: adding_constraints_to_scope_variables_0 :description: Adding constraints to scope variables—std::randomize() with - test :tags: 18.12.1 */ class a; function int do_randomize(int y); int x, success; success = std::randomize(x) with {x > 0; x < y;}; return success; endfunction endclass ================================================ FILE: tests/chapter-18/18.12.1--adding-constraints-to-scope-variables_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: adding_constraints_to_scope_variables_1 :description: Adding constraints to scope variables—std::randomize() with - test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; function int do_randomize(int y); int x, success; success = std::randomize(x) with {x > 0; x < y;}; return success; endfunction endclass class env extends uvm_env; a obj = new; int ret, y = 20; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin ret = obj.do_randomize(y); if(ret == 1) begin `uvm_info("RESULT", $sformatf("ret = %0d SUCCESS", ret), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret = %0d FAILED", ret)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.13.1--urandom_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: urandom_0 :description: urandom() test :tags: 18.13.1 */ class a; function int unsigned do_urandom(); int unsigned x; x = $urandom(); return x; endfunction endclass ================================================ FILE: tests/chapter-18/18.13.1--urandom_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: urandom_1 :description: urandom() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; function int unsigned do_urandom(); int unsigned x; x = $urandom(); return x; endfunction endclass class env extends uvm_env; a obj = new; int unsigned ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin ret = obj.do_urandom(); if(ret >= 0) begin `uvm_info("RESULT", $sformatf("ret = %0d SUCCESS", ret), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret = %0d FAILED", ret)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.13.1--urandom_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: urandom_2 :description: urandom() test :tags: 18.13.1 */ class a; function int unsigned do_urandom(int seed); int unsigned x; x = $urandom(seed); return x; endfunction endclass ================================================ FILE: tests/chapter-18/18.13.1--urandom_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: urandom_3 :description: urandom() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; function int unsigned do_urandom(int seed); int unsigned x; x = $urandom(seed); return x; endfunction endclass class env extends uvm_env; a obj = new; int unsigned ret1, ret2; int seed = 254; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin ret1 = obj.do_urandom(seed); ret2 = obj.do_urandom(seed); if(ret1 == ret2) begin `uvm_info("RESULT", $sformatf("ret1 = %0d ret2 = %0d SUCCESS", ret1, ret2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret1 = %0d ret2 = %0d FAILED", ret1, ret2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.13.2--urandom_range_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: urandom_range_0 :description: urandom_range() test :tags: 18.13.2 */ class a; function int do_urandom_range(int unsigned maxval, int unsigned minval); int unsigned val; val = $urandom_range(maxval, minval); return val; endfunction endclass ================================================ FILE: tests/chapter-18/18.13.2--urandom_range_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: urandom_range_1 :description: urandom_range() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; function int unsigned do_urandom_range(int unsigned maxval, int unsigned minval); int unsigned val; val = $urandom_range(maxval, minval); return val; endfunction endclass class env extends uvm_env; a obj = new; int unsigned max = 10, min = 1, ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin ret = obj.do_urandom_range(max, min); if(ret >= min && ret <= max) begin `uvm_info("RESULT", $sformatf("ret = %0d SUCCESS", ret), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret = %0d FAILED", ret)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.13.2--urandom_range_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: urandom_range_2 :description: urandom_range() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; function int unsigned do_urandom_range(int unsigned maxval, int unsigned minval); int unsigned val; val = $urandom_range(maxval, minval); return val; endfunction endclass class env extends uvm_env; a obj = new; int unsigned max = 10, min = 1, ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin /* If max is less than min, then arguments should be automatically reversed */ ret = obj.do_urandom_range(min, max); if(ret >= min && ret <= max) begin `uvm_info("RESULT", $sformatf("ret = %0d SUCCESS", ret), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret = %0d FAILED", ret)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.13.2--urandom_range_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: urandom_range_3 :description: urandom_range() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; function int unsigned do_urandom_range(int unsigned maxval); int unsigned val; val = $urandom_range(maxval); return val; endfunction endclass class env extends uvm_env; a obj = new; int unsigned max = 10, ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin ret = obj.do_urandom_range(max); if(ret >= 0 && ret <= max) begin `uvm_info("RESULT", $sformatf("ret = %0d SUCCESS", ret), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret = %0d FAILED", ret)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.13.3--srandom_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: srandom_0 :description: srandom() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; constraint c {x > 0 && x < 30;}; endclass class env extends uvm_env; a obj = new; int ret1, ret2, prev_x, seed = 20; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.srandom(seed); ret1 = obj.randomize(); prev_x = obj.x; obj.srandom(seed); ret2 = obj.randomize(); if(ret1 == 1 && ret2 == 1 && obj.x > 0 && obj.x < 30 && prev_x == obj.x) begin `uvm_info("RESULT", $sformatf("prev_x = %0d obj.x = %0d SUCCESS", prev_x, obj.x), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("prev_x = %0d obj.x = %0d FAILED", prev_x, obj.x)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.13.4--get_randstate_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: get_randstate_0 :description: get_randstate() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; endclass class env extends uvm_env; a obj = new; string randstate; int ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin ret = obj.randomize(); randstate = obj.get_randstate(); if(ret == 1 && randstate != "") begin `uvm_info("RESULT", $sformatf("ret = %0d randstate = %s SUCCESS", ret, randstate), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret = %0d randstate = %s FAILED", ret, randstate)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.13.5--set_randstate_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: set_randstate_0 :description: set_randstate() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; endclass class env extends uvm_env; a obj = new; string randstate; int prev_x; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin randstate = obj.get_randstate(); obj.randomize(); prev_x = obj.x; obj.set_randstate(randstate); obj.randomize(); if(obj.x == prev_x) begin `uvm_info("RESULT", $sformatf("obj.x = %0d prev_x = %0d SUCCESS", obj.x, prev_x), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d prev_x = %0d FAILED", obj.x, prev_x)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.14--random-stability_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_stability_0 :description: random stability - urandom_range test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class env extends uvm_env; int unsigned val1, val2; process p; string randstate; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin p = process::self(); randstate = p.get_randstate(); val1 = $urandom_range(0, 1000); p.set_randstate(randstate); val2 = $urandom_range(0, 1000); if(val1 == val2) begin `uvm_info("RESULT", $sformatf("val1 = %0d val2 = %0d SUCCESS", val1, val2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("val1 = %0d val2 = %0d FAILED", val1, val2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.14--random-stability_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_stability_1 :description: random stability - shuffle test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class env extends uvm_env; int tab1[5] = { 1, 2, 3, 4, 5 }; int tab2[5] = { 1, 2, 3, 4, 5 }; process p; string randstate; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin p = process::self(); randstate = p.get_randstate(); tab1.shuffle; p.set_randstate(randstate); tab2.shuffle; if(tab1 == tab2) begin `uvm_info("RESULT", $sformatf("tab1 = %p tab2 = %p SUCCESS", tab1, tab2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("tab1 = %p tab2 = %p FAILED", tab1, tab2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.14--random-stability_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_stability_2 :description: random stability - randcase test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class env extends uvm_env; int x, y; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin for (int i = 0; i < 10; i++) randcase 0 : x = x + 1; 1 : y = y + 1; endcase if(x == 0 && y == 10) begin `uvm_info("RESULT", $sformatf("x = %0d y = %0d SUCCESS", x, y), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("x = %0d y = %0d FAILED", x, y)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.14--random-stability_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_stability_3 :description: random stability - randcase test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class env extends uvm_env; process p; string randstate; int x, y; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin p = process::self(); randstate = p.get_randstate(); randcase 2 : x = 1; 2 : x = 2; 2 : x = 3; 2 : x = 4; 2 : x = 5; endcase p.set_randstate(randstate); randcase 2 : y = 1; 2 : y = 2; 2 : y = 3; 2 : y = 4; 2 : y = 5; endcase if(x == y) begin `uvm_info("RESULT", $sformatf("x = %0d y = %0d SUCCESS", x, y), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("x = %0d y = %0d FAILED", x, y)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.14.2--thread-stability_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: thread_stability_0 :description: thread stability test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class env extends uvm_env; int unsigned val1, val2; process p1, p2; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin fork begin p1 = process::self(); p1.srandom(100); val1 = $urandom; end begin p2 = process::self(); p2.srandom(100); val2 = $urandom; end join if(val1 == val2) begin `uvm_info("RESULT", $sformatf("val1 = %0d val2 = %0d SUCCESS", val1, val2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("val1 = %0d val2 = %0d FAILED", val1, val2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.14.2--thread-stability_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: thread_stability_1 :description: thread stability test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class env extends uvm_env; int unsigned val1, val2; process p1, p2; string randstate1, randstate2; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin fork begin p1 = process::self(); randstate1 = p1.get_randstate(); val1 = $urandom; end begin p2 = process::self(); randstate2 = p2.get_randstate(); val2 = $urandom; end join if(val1 != val2 && randstate1 != randstate2) begin `uvm_info("RESULT", $sformatf("val1 = %0d val2 = %0d SUCCESS", val1, val2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("val1 = %0d val2 = %0d FAILED", val1, val2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.14.3--object-stability_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: object_stability_0 :description: object stability test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a1; rand int x; endclass class a2; rand int y; endclass class env extends uvm_env; a1 obj1 = new(); a2 obj2 = new(); string randstate1, randstate2; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin randstate1 = obj1.get_randstate(); randstate2 = obj2.get_randstate(); obj1.randomize(); obj2.randomize(); if(obj1.x != obj2.y && randstate1 != randstate2) begin `uvm_info("RESULT", $sformatf("obj1.x = %0d obj2.y = %0d SUCCESS", obj1.x, obj2.y), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj1.x = %0d obj2.y = %0d FAILED", obj1.x, obj2.y)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.14.3--object-stability_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: object_stability_1 :description: object stability test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a1; rand int x; function new (int seed); this.srandom(seed); endfunction endclass class a2; rand int y; function new (int seed); this.srandom(seed); endfunction endclass class env extends uvm_env; a1 obj1 = new(200); a2 obj2 = new(200); string randstate1, randstate2; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin randstate1 = obj1.get_randstate(); randstate2 = obj2.get_randstate(); obj1.randomize(); obj2.randomize(); if(obj1.x == obj2.y && randstate1 == randstate2) begin `uvm_info("RESULT", $sformatf("obj1.x = %0d obj2.y = %0d SUCCESS", obj1.x, obj2.y), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj1.x = %0d obj2.y = %0d FAILED", obj1.x, obj2.y)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.15--manually-seeding-randomize_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: manually_seeding_randomize_0 :description: manually seeding randomize test :tags: 18.15 :unsynthesizable: 1 */ class a; rand int x; function new (int seed); this.srandom(seed); endfunction endclass ================================================ FILE: tests/chapter-18/18.15--manually-seeding-randomize_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: manually_seeding_randomize_1 :description: manually seeding randomize test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; function new (int seed); this.srandom(seed); endfunction endclass class env extends uvm_env; a obj = new(100); int prev_x; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); prev_x = obj.x; obj.srandom(100); obj.randomize(); if(obj.x == prev_x) begin `uvm_info("RESULT", $sformatf("obj.x = %0d prev_x = %0d SUCCESS", obj.x, prev_x), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d prev_x = %0d FAILED", obj.x, prev_x)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.16--random-weighted-case-randcase_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_weighted_case_randcase_0 :description: randcase test :tags: 18.16 :type: simulation elaboration parsing */ function int F(); int a; randcase 0 : a = 5; 1 : a = 10; endcase return a; endfunction module top; int x; initial begin x = F(); $display(":assert: (10 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.16--random-weighted-case-randcase_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_weighted_case_randcase_2 :description: randcase test :tags: 18.16 :type: simulation elaboration parsing */ function int F(int y); int a; randcase y - y : a = 5; y + y : a = 10; endcase return a; endfunction module top; int x; initial begin x = F(6); $display(":assert: (10 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17--random-sequence-generation-randsequence_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_sequence_generation_randsequence_0 :description: randsequence test :type: simulation elaboration parsing :tags: 18.17 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : first second done; first : { x = x + 1; }; second : { x = x + 2; }; done : { x = x + 3; }; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (6 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17--random-sequence-generation-randsequence_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_sequence_generation_randsequence_2 :description: randsequence test :type: simulation elaboration parsing :tags: 18.17 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : first | second; first : { x = -2; }; second : { x = 2; }; endsequence return x; endfunction module top; int x; initial begin x = F(); if (x != 2 && x != -2) $stop; end endmodule ================================================ FILE: tests/chapter-18/18.17.1--random-production-weights_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_production_weights_0 :description: randsequence weights test :type: simulation elaboration parsing :tags: 18.17.1 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : first := 1 | second := 0; first : { x = 2; }; second : { x = -2; }; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (2 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17.2--if-else-production-statements_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_production_statements_0 :description: randcase if-else test :type: simulation elaboration parsing :tags: 18.17.2 :unsynthesizable: 1 */ function int F(); int x; int switch = 1; randsequence( main ) main : first; first : { if(switch) x = 10; else x = 5; }; endsequence return x; endfunction module top; int x; initial begin x = F(); if (x != 10) $stop; end endmodule ================================================ FILE: tests/chapter-18/18.17.2--if-else-production-statements_0_fail.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_production_statements_0_fail :description: randcase if-else test :should_fail_because: switch variable not declared :type: elaboration :tags: 18.17.2 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : first; first : { if(switch ) x = 10; else x = 5; }; endsequence return x; endfunction ================================================ FILE: tests/chapter-18/18.17.2--if-else-production-statements_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_production_statements_2 :description: randcase if-else test :type: simulation elaboration parsing :tags: 18.17.2 :unsynthesizable: 1 */ function int F(); int x; int switch = 1; randsequence( main ) main : first; first : if(switch) second else third; second : { x = 10; }; third : { x = 5; }; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (10 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17.2--if-else-production-statements_2_fail.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_production_statements_2_fail :description: randcase if-else test :should_fail_because: switch variable not declared :type: elaboration :tags: 18.17.2 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : first; first : if(switch) second else third; second : { x = 10; }; third : { x = 5; }; endsequence return x; endfunction ================================================ FILE: tests/chapter-18/18.17.3--case-production-statements_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: case_production_statements_0 :description: randcase case statement test :type: simulation elaboration parsing :tags: 18.17.3 :unsynthesizable: 1 */ function int F(); int x; int switch = 1; randsequence( main ) main : case (switch) 0 : zero; 1 : first; 2 : second; default : third; endcase; zero : { x = 0; }; first : { x = 10; }; second : { x = 2; }; third : { x = 3; }; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (10 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17.3--case-production-statements_0_fail.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: case_production_statements_0_fail :description: randcase case statement test :should_fail_because: switch variable not declared :type: elaboration :tags: 18.17.3 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : case (switch) 0 : zero; 1 : first; 2 : second; default : third; endcase; zero2 : { x = 0; }; first : { x = 10; }; second : { x = 2; }; third : { x = 3; }; endsequence return x; endfunction ================================================ FILE: tests/chapter-18/18.17.4--repeat-production-statements_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: repeat_production_statements_0 :description: repeat statement test :type: simulation elaboration parsing :tags: 18.17.4 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : first; first : repeat(10) second; second : { x = x + 1; }; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (10 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17.5--interleaving-productions-rand-join_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: interleaving_productions_rand_join_0 :description: rand join statement test :type: simulation elaboration parsing :tags: 18.17.5 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : rand join first second; first : { x = x + 20; }; second : { x = x - 10; }; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (10 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17.5--interleaving-productions-rand-join_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: interleaving_productions_rand_join_2 :description: rand join statement test :type: simulation elaboration parsing :tags: 18.17.5 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : rand join (0.5) first second; first : { x = x + 20; }; second : { x = x - 10; }; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (10 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17.6--aborting-productions-break-and-return_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: aborting_productions_break_and_return_0 :description: break statement test :type: simulation elaboration parsing :tags: 18.17.6 :unsynthesizable: 1 */ function int F(); int x; int break_on = 1; randsequence( main ) main : first second third; first : { x = x + 10; }; second : { if(break_on == 1) break; } fourth; third : { x = x + 10; }; fourth : { x = x + 15; }; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (10 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17.6--aborting-productions-break-and-return_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: aborting_productions_break_and_return_2 :description: return statement test :type: simulation elaboration parsing :tags: 18.17.6 :unsynthesizable: 1 */ function int F(); int x; static int return_on = 1; randsequence( main ) main : first second third; first : { x = x + 20; }; second : { if(return_on == 1) return; x = x + 10; }; third : { x = x + 5;}; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (25 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.17.6--aborting-productions-break-and-return_2_fail.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: aborting_productions_break_and_return_2_fail :description: return statement test :should_fail_because: typo in production name :type: elaboration :tags: 18.17.6 :unsynthesizable: 1 */ function int F(); int x; static int return_on = 1; randsequence( main ) main : first secondi third; first : { x = x + 20; }; second : { if(return_on == 1) return; x = x + 10; }; third : { x = x + 5;}; endsequence return x; endfunction ================================================ FILE: tests/chapter-18/18.17.7--value-passing-between-productions_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: value_passing_between_productions_0 :description: value passing in randsequence test :type: simulation elaboration parsing :tags: 18.17.7 :unsynthesizable: 1 */ function int F(); int x; randsequence( main ) main : first second third; first : add(10); second : add(5); third : add(2); void add(int y) : { x = x + y; }; endsequence return x; endfunction module top; int x; initial begin x = F(); $display(":assert: (17 == %d)", x); end endmodule ================================================ FILE: tests/chapter-18/18.4.1--rand-modifier.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: rand_modifier :description: rand modifier test :tags: 18.4.1 */ class a; rand int b; endclass ================================================ FILE: tests/chapter-18/18.4.2--randc-modifier.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: randc_modifier :description: randc modifier test :tags: 18.4.2 */ class a; randc int b; endclass ================================================ FILE: tests/chapter-18/18.5--constraint-blocks_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constraint_blocks_0 :description: constraint blocks test :tags: 18.5 */ class a; rand int b; constraint c { b == 0; } endclass ================================================ FILE: tests/chapter-18/18.5--constraint-blocks_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constraint_blocks_1 :description: constraint blocks test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c { b == 5; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 5) begin `uvm_info("RESULT", $sformatf("b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.1--explicit-external-constraint_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: explicit_external_constraint_0 :description: explicit external constraint test :tags: 18.5.1 */ class a; rand int b; extern constraint c; endclass constraint a::c { b == 0; } ================================================ FILE: tests/chapter-18/18.5.1--explicit-external-constraint_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: explicit_external_constraint_1 :description: explicit external constraint test :should_fail_because: explicit contraint needs to be defined :tags: 18.5.1 :type: simulation elaboration */ class a; rand int b; extern constraint c; endclass ================================================ FILE: tests/chapter-18/18.5.1--explicit-external-constraint_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: explicit_external_constraint_2 :description: explicit external constraint test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; extern constraint c; endclass constraint a::c { b == 5; } class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 5) begin `uvm_info("RESULT", $sformatf("b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.1--implicit-external-constraint_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implicit_external_constraint_0 :description: implicit external constraint test :tags: 18.5.1 */ class a; rand int b; constraint c; endclass constraint a::c { b == 0; } ================================================ FILE: tests/chapter-18/18.5.1--implicit-external-constraint_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implicit_external_constraint_1 :description: implicit external constraint test :tags: 18.5.1 */ class a; rand int b; constraint c; endclass ================================================ FILE: tests/chapter-18/18.5.1--implicit-external-constraint_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implicit_external_constraint_2 :description: implicit external constraint test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c; endclass constraint a::c { b == 5; } class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 5) begin `uvm_info("RESULT", $sformatf("b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.10--variable-ordering_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: variable_ordering_0 :description: variable ordering test :tags: 18.5.10 */ class a; rand bit b1; rand int b2; constraint c1 { b1 -> b2 == 0; } constraint c2 { solve b1 before b2; } endclass ================================================ FILE: tests/chapter-18/18.5.10--variable-ordering_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: variable_ordering_1 :description: variable ordering test :should_fail_because: randc vars are not allowed, they are always solved before any other :tags: 18.5.10 :type: simulation elaboration */ class a; rand bit b1; randc int b2; constraint c1 { b1 -> b2 == 0; } constraint c2 { solve b1 before b2; } endclass ================================================ FILE: tests/chapter-18/18.5.11--static-constraint-blocks_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: static_constraint_blocks_0 :description: static constraint blocks test :tags: 18.5.11 :unsynthesizable: 1 */ class a; rand int b; static constraint c1 { b == 5; } endclass ================================================ FILE: tests/chapter-18/18.5.11--static-constraint-blocks_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: static_constraint_blocks_1 :description: static constraint blocks test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; static constraint c1 { b == 5; } static constraint c2 { b == 2; } endclass class env extends uvm_env; a obj1 = new; a obj2 = new; function new(string name, uvm_component parent = null); super.new(name, parent); /* shall affect all instances of constraint c2 */ obj1.c1.constraint_mode(0); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj1.randomize(); obj2.randomize(); if(obj1.b == 2 && obj2.b == 2) begin `uvm_info("RESULT", $sformatf("obj1.b = %0d obj2.b = %0d SUCCESS", obj1.b, obj2.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj1.b = %0d obj2.b = %0d FAILED", obj1.b, obj2.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.12--functions-in-constraint_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: functions_in_constraints_0 :description: functions in constraints test :tags: 18.5.12 */ class a; rand int b1, b2; function int F (input int d); F=d; endfunction constraint c1 { b1 == 5; } constraint c2 { b2 == F(b1); } endclass ================================================ FILE: tests/chapter-18/18.5.12--functions-in-constraint_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: functions_in_constraint_1 :description: functions in constraint test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b1, b2; function int F (input int d); F=d; endfunction constraint c1 { b1 == 5; } constraint c2 { b2 == F(b1); } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b2 == 5) begin `uvm_info("RESULT", $sformatf("obj.b2 = %0d SUCCESS", obj.b2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b2 = %0d FAILED", obj.b2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.13--constraint-guards_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constraint_guards_0 :description: constraint guards test :tags: 18.5.13 */ class b; int d1; endclass class a; rand int b1; b next; constraint c1 { if (next == null) b1 == 5; } endclass ================================================ FILE: tests/chapter-18/18.5.13--constraint-guards_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constraint_guards_1 :description: constraint guards test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class b; int d1; endclass class a; rand int b1; b next; constraint c1 { if (next == null) b1 == 5; } endclass class env extends uvm_env; a obj1 = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj1.randomize(); if(obj1.b1 == 5) begin `uvm_info("RESULT", $sformatf("obj1.b1 = %0d SUCCESS", obj1.b1), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj1.b1 = %0d FAILED", obj1.b1)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.14--soft-constraints_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: soft_constraints_0 :description: soft constraints test :tags: 18.5.14 */ class a; rand int b; constraint c { soft b > 4; soft b < 12; } endclass ================================================ FILE: tests/chapter-18/18.5.14--soft-constraints_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: soft_constraints_1 :description: soft constraints test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c { soft b > 4; soft b < 12; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b > 4 && obj.b < 12) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.14--soft-constraints_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: soft_constraints_2 :description: soft constraints test :should_fail_because: Soft constraints can only be specified on random variables; they may not be specified for randc variables. :tags: 18.5.14 :type: simulation elaboration */ class a; randc int b; constraint c { soft b > 4; soft b < 12; } endclass ================================================ FILE: tests/chapter-18/18.5.14.1--soft-constraint-priorities_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: soft_constraint_priorities_0 :description: soft constraint priorities test :tags: 18.5.14.1 */ class a1; rand int b; constraint c1 { soft b > 4; soft b < 12; } endclass class a2 extends a1; constraint c2 { soft b == 20; } endclass ================================================ FILE: tests/chapter-18/18.5.14.1--soft-constraint-priorities_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: soft_constraint_priorities_1 :description: soft constraint priorities test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a1; rand int b; constraint c1 { soft b > 4; soft b < 12; } endclass class a2 extends a1; constraint c2 { soft b == 20; } endclass class env extends uvm_env; a2 obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 20) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.14.1--soft-constraint-priorities_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: soft_constraint_priorities_2 :description: soft constraint priorities test :tags: 18.5.14.1 */ class a1; rand int b; constraint c1 { soft b > 4; soft b < 12; } endclass class a2 extends a1; constraint c2 { soft b == 20; } constraint c3; endclass constraint a2::c3 { soft b > 100; }; ================================================ FILE: tests/chapter-18/18.5.14.1--soft-constraint-priorities_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: soft_constraint_priorities_3 :description: soft constraint priorities test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a1; rand int b; constraint c1 { soft b > 4; soft b < 12; } endclass class a2 extends a1; constraint c2 { soft b == 20; } constraint c3; endclass constraint a2::c3 { soft b > 100; }; class env extends uvm_env; a2 obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b > 100) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.14.1--soft-constraint-priorities_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: soft_constraint_priorities_4 :description: soft constraint priorities test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a1; rand int b; constraint c1 { soft b > 4; soft b < 12; } endclass class a2 extends a1; constraint c2 {soft b == 20; } constraint c3; endclass constraint a2::c3 { soft b > 100; }; class env extends uvm_env; a2 obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize() with { soft b == 90; }; if(obj.b == 90) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.14.2--discarding-soft-constraints_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: discarding_soft_constraints_0 :description: discarding soft constraints test :tags: 18.5.14.2 */ class a; rand int b; constraint c1 { soft b > 4; soft b < 12; } constraint c2 { disable soft b; } constraint c3 { soft b == 20; } endclass ================================================ FILE: tests/chapter-18/18.5.14.2--discarding-soft-constraints_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: discarding_soft_constraints_1 :description: discarding soft constraints test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c1 { soft b > 4; soft b < 12; } constraint c2 { disable soft b; } constraint c3 { soft b == 20; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 20) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.14.2--discarding-soft-constraints_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: discarding_soft_constraints_2 :description: discarding soft constraints test :tags: 18.5.14.2 */ class a; rand int b; constraint c1 { soft b > 4; soft b < 12; } constraint c2 { disable soft b; soft b == 20; } endclass ================================================ FILE: tests/chapter-18/18.5.14.2--discarding-soft-constraints_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: discarding_soft_constraints_3 :description: discarding soft constraints test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c1 { soft b > 4; soft b < 12; } constraint c2 { disable soft b; } constraint c3 { soft b == 20; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 20) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.14.2--discarding-soft-constraints_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: discarding_soft_constraints_5 :description: discarding soft constraints test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c1 { soft b > 4; soft b < 12; } constraint c2 { disable soft b; } constraint c3 { soft b == 20; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 20) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.2--constraint-inheritance_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constraint_inheritance_0 :description: contraint inheritance test :tags: 18.5.2 */ class a; rand int b; constraint c { b == 5; }; endclass class a2 extends a; rand int b2; constraint c2 { b2 == b; } endclass ================================================ FILE: tests/chapter-18/18.5.2--constraint-inheritance_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constraint_inheritance_1 :description: contraint inheritance test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c { b == 5; }; endclass class a2 extends a; rand int b2; constraint c2 { b2 == b; } endclass class env extends uvm_env; a2 obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b2 == 5) begin `uvm_info("RESULT", $sformatf("b2 = %0d SUCCESS", obj.b2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b2 = %0d FAILED", obj.b2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.2--pure-constraint_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pure_constraint_0 :description: pure constraint test :tags: 18.5.2 :unsynthesizable: 1 */ virtual class a; pure constraint c; endclass class a2 extends a; rand int b2; constraint c { b2 == 5; } endclass ================================================ FILE: tests/chapter-18/18.5.2--pure-constraint_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pure_constraint_1 :description: pure constraint test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" virtual class a; pure constraint c; endclass class a2 extends a; rand int b2; constraint c { b2 == 5; } endclass class env extends uvm_env; a2 obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b2 == 5) begin `uvm_info("RESULT", $sformatf("b2 = %0d SUCCESS", obj.b2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b2 = %0d FAILED", obj.b2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.2--pure-constraint_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pure_constraint_2 :description: pure constraint test :should_fail_because: pure constraint must be implemented by non-virtual class :tags: 18.5.2 :type: simulation elaboration */ virtual class a; pure constraint c; endclass class a2 extends a; endclass ================================================ FILE: tests/chapter-18/18.5.2--pure-constraint_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pure_constraint_3 :description: pure constraint test :tags: 18.5.2 */ virtual class a; pure constraint c; endclass virtual class a2 extends a; endclass ================================================ FILE: tests/chapter-18/18.5.3--set-membership_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: set_membership_0 :description: set membership test :tags: 18.5.3 */ class a; rand int b; constraint c { b inside {3, 10}; } endclass ================================================ FILE: tests/chapter-18/18.5.3--set-membership_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: set_membership_1 :description: set membership test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c { b inside {3, 10}; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b inside {3, 10}) begin `uvm_info("RESULT", $sformatf("b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.4--distribution_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: distribution_0 :description: distribution test :tags: 18.5.4 */ class a; rand int b; constraint c { b dist {3 := 1, 10 := 2}; } endclass ================================================ FILE: tests/chapter-18/18.5.4--distribution_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: distribution_1 :description: distribution test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c { b dist {3 := 0, 10 := 5}; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 10) begin `uvm_info("RESULT", $sformatf("b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.4--distribution_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: distribution_2 :description: distribution test :should_fail_because: distribution shall not be applied to randc variables :tags: 18.5.4 :type: simulation elaboration */ class a; randc int b; constraint c { b dist {3 := 0, 10 := 5}; } endclass ================================================ FILE: tests/chapter-18/18.5.5--uniqueness-constraints_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uniqueness_constraints_0 :description: uniqueness constraints test :tags: 18.5.5 */ class a; rand int b1, b2; constraint c1 { b1 inside {3, 10}; } constraint c2 { b2 inside {3, 10}; } constraint c3 { unique {b1, b2}; } endclass ================================================ FILE: tests/chapter-18/18.5.5--uniqueness-constraints_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uniqueness_constraints_1 :description: uniqueness constraints test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b1, b2; constraint c1 { b1 inside {3, 10}; } constraint c2 { b2 inside {3, 10}; } constraint c3 { unique {b1, b2}; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if((obj.b1 == 3 && obj.b2 == 10) || (obj.b2 == 3 && obj.b1 == 10)) begin `uvm_info("RESULT", $sformatf("b1 = %0d b2 = %0d SUCCESS", obj.b1, obj.b2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b1 = %0d b2 = %0d FAILED", obj.b1, obj.b2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.6--implication_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implication_0 :description: implication test :tags: 18.5.6 */ class a; rand int b1, b2; constraint c1 { b1 == 5; } constraint c2 { b1 == 5 -> b2 == 10; } endclass ================================================ FILE: tests/chapter-18/18.5.6--implication_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implication_1 :description: implication test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b1, b2; constraint c1 { b1 == 5; } constraint c2 { b1 == 5 -> b2 == 10; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b1 == 5 && obj.b2 == 10) begin `uvm_info("RESULT", $sformatf("b1 = %0d b2 = %0d SUCCESS", obj.b1, obj.b2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b1 = %0d b2 = %0d FAILED", obj.b1, obj.b2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.7--if-else-constraints_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_constraints_0 :description: if-else constraints test :tags: 18.5.7 */ class a; rand int b1, b2; constraint c1 { b1 == 5; } constraint c2 { if(b1 == 5) b2 == 10; } endclass ================================================ FILE: tests/chapter-18/18.5.7--if-else-constraints_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_constraints_1 :description: if-else constraints test :tags: 18.5.7 */ class a; rand int b1, b2; constraint c1 { b1 == 5; } constraint c2 { if (b1 == 0) b2 == 10; else b2 == 15;} endclass ================================================ FILE: tests/chapter-18/18.5.7--if-else-constraints_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_constraints_2 :description: if-else constraints test :tags: 18.5.7 */ class a; rand int b1, b2; constraint c1 { b1 == 5; } constraint c2 { if (b1 == 0) b2 == 10; else if (b1 == 5) b2 == 3; else b2 == 15;} endclass ================================================ FILE: tests/chapter-18/18.5.7--if-else-constraints_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_constraints_3 :description: if-else constraints test :tags: 18.5.7 */ class a; rand int b1, b2, b3; constraint c1 { b1 == 5; } constraint c2 { b2 == 3; } constraint c3 { if (b1 == 0) if (b2 == 2) b3 == 4; else b3 == 10;} endclass ================================================ FILE: tests/chapter-18/18.5.7--if-else-constraints_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: if_else_constraints_4 :description: if-else constraints test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b1, b2, b3; constraint c1 { b1 == 5; } constraint c2 { b2 == 3; } constraint c3 { if (b1 == 5) if (b2 == 2) b3 == 4; else b3 == 10;} endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b3 == 10) begin `uvm_info("RESULT", $sformatf("b3 = %0d SUCCESS", obj.b3), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("b3 = %0d FAILED", obj.b3)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.8.1--foreach-iterative-constraints_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: foreach_iterative_constraints_0 :description: foreach iterative constraints test :tags: 18.5.8.1 :unsynthesizable: 1 */ class a; rand int B[5]; constraint c { foreach ( B [ i ] ) B[i] == 5; } endclass ================================================ FILE: tests/chapter-18/18.5.8.1--foreach-iterative-constraints_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: foreach_iterative_constraints_1 :description: foreach iterative constraints test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int B[5]; constraint c { foreach ( B [ i ] ) B[i] == 5; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.B.sum() == 25) begin `uvm_info("RESULT", $sformatf("sum = %0d SUCCESS", obj.B.sum()), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("sum = %0d FAILED", obj.B.sum())); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.8.2--array-reduction-iterative-constraints_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array_reduction_iterative_constraints_0 :description: array reduction iterative constraints test :tags: 18.5.8.2 */ class a; rand int B[5]; constraint c { B.sum() == 5; } endclass ================================================ FILE: tests/chapter-18/18.5.8.2--array-reduction-iterative-constraints_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array_reduction_iterative_constraints_1 :description: array reduction iterative constraints test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int B[5]; constraint c { B.sum() == 5; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.B.sum() == 5) begin `uvm_info("RESULT", $sformatf("sum = %0d SUCCESS", obj.B.sum()), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("sum = %0d FAILED", obj.B.sum())); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.5.9--global-constraints_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: global_constraints_0 :description: global constraints test :tags: 18.5.9 */ class a; rand int v; endclass class b; rand a aObj; rand int v; constraint c { aObj.v < v; } endclass ================================================ FILE: tests/chapter-18/18.5.9--global-constraints_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: global_constraints_1 :description: global constraints test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int v; endclass class b extends a; rand a aObj; constraint c { aObj.v < v; } endclass class env extends uvm_env; b bObj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin bObj.randomize(); if(bObj.aObj.v < bObj.v) begin `uvm_info("RESULT", $sformatf("%0d < %0d SUCCESS", bObj.aObj.v, bObj.v), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("%0d !< %0d FAILED", bObj.aObj.v, bObj.v)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.6.1--randomize-method_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: randomize_method_0 :description: randomize() method test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c { b == 20; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin int success = obj.randomize(); if(success == 1) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.6.2--post-randomize_method_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: post_randomize_method_0 :description: post_randomize() method test :tags: 18.6.2 */ class a; rand int b; int d; constraint c { b == 5; } function void post_randomize(); d = 20; endfunction endclass ================================================ FILE: tests/chapter-18/18.6.2--post-randomize_method_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: post_randomize_method_1 :description: post_randomize() method test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; int d; constraint c { b == 5; } function void post_randomize(); d = 20; endfunction endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 5 && obj.d == 20) begin `uvm_info("RESULT", $sformatf("obj.b = %0d obj.d = %0d SUCCESS", obj.b, obj.d), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d obj.d = %0d FAILED", obj.b, obj.d)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.6.2--pre-randomize-method_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pre_randomize_method_0 :description: pre_randomize() method test :tags: 18.6.2 */ class a; rand int b; int d; constraint c { b == 5; } function void pre_randomize(); d = 20; endfunction endclass ================================================ FILE: tests/chapter-18/18.6.2--pre-randomize-method_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pre_randomize_method_1 :description: pre_randomize() method test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; int d; constraint c { b == 5; } function void pre_randomize(); d = 20; endfunction endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(obj.b == 5 && obj.d == 20) begin `uvm_info("RESULT", $sformatf("obj.b = %0d obj.d = %0d SUCCESS", obj.b, obj.d), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d obj.d = %0d FAILED", obj.b, obj.d)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.6.3--behavior-of-randomization-methods_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: behavior_of_randomization_methods_0 :description: static random variables test :tags: 18.6.3 :unsynthesizable: 1 */ class a; static rand int b; constraint c { b > 5; b < 12; } endclass ================================================ FILE: tests/chapter-18/18.6.3--behavior-of-randomization-methods_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: behavior_of_randomization_methods_1 :description: static random variables test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; static rand int b; constraint c { b > 5; b < 12; } endclass class env extends uvm_env; a obj1 = new; a obj2 = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj1.randomize(); if(obj1.b == obj2.b) begin `uvm_info("RESULT", $sformatf("obj1.b = %0d obj2.b = %0d SUCCESS", obj1.b, obj2.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj1.b = %0d obj2.b = %0d FAILED", obj1.b, obj2.b)); end obj2.randomize(); if(obj1.b == obj2.b) begin `uvm_info("RESULT", $sformatf("obj1.b = %0d obj2.b = %0d SUCCESS", obj1.b, obj2.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj1.b = %0d obj2.b = %0d FAILED", obj1.b, obj2.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.6.3--behavior-of-randomization-methods_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: behavior_of_randomization_methods_2 :description: If randomize() fails, the constraints are infeasible, and the random variables retain their previous values. :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b = 1; /* Create infeasible constraint */ constraint c { b == 0 && b > 0; } endclass class env extends uvm_env; a obj = new; int prev_value, status; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin prev_value = obj.b; status = obj.randomize(); if(status == 0 && prev_value == obj.b) begin `uvm_info("RESULT", $sformatf("obj.b = %0d prev_value = %0d SUCCESS", obj.b, prev_value), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d prev_value = %0d FAILED", obj.b, prev_value)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.6.3--behavior-of-randomization-methods_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: behavior_of_randomization_methods_3 :description: If randomize() fails, post_randomize() is not called. :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; int d = 1; constraint c { b == 0 && b > 0; } function void post_randomize(); d = 20; endfunction endclass class env extends uvm_env; a obj = new; int status; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin status = obj.randomize(); if(status == 0 && obj.d == 1) begin `uvm_info("RESULT", $sformatf("obj.d = %0d SUCCESS", obj.d), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.d = %0d FAILED", obj.d)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.6.3--behavior-of-randomization-methods_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: behavior_of_randomization_methods_4 :description: behavior of randomization methods test :should_fail_because: The randomize() method is built-in and cannot be overridden. :tags: 18.6.3 :type: simulation elaboration */ class a; rand int b; constraint c { b > 5 && b < 12; } function void randomize(); b = 7; endfunction endclass ================================================ FILE: tests/chapter-18/18.6.3--behavior-of-randomization-methods_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: behavior_of_randomization_methods_5 :description: behavior of randomization methods test :should_fail_because: The randomize() method is built-in and cannot be overridden. :tags: uvm-random uvm :type: simulation elaboration :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int b; constraint c { b > 5 && b < 12; } function void randomize(); b = 7; endfunction endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize(); if(b > 5 && b < 12) begin `uvm_info("RESULT", $sformatf("obj.b = %0d SUCCESS", obj.b), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.b = %0d FAILED", obj.b)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.7--in-line-constraints--randomize_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_constraints--randomize_0 :description: in-line constraints test - randomize() :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand bit [7:0] x, y, z; constraint c { z == x + y; } endclass class env extends uvm_env; a obj = new; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.randomize() with { x < y; }; if(obj.z == obj.x + obj.y && obj.x < obj.y) begin `uvm_info("RESULT", $sformatf("obj.x = %0d obj.y = %0d obj.z = %0d SUCCESS", obj.x, obj.y, obj.z), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d obj.y = %0d obj.z = %0d FAILED", obj.x, obj.y, obj.z)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.7--in-line-constraints--randomize_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_constraints--randomize_1 :description: in-line constraints test - randomize() :tags: 18.7 :unsynthesizable: 1 */ class a1; rand int x; endclass class a2; int x, y; task do_randomize(a1 obj, int x, int z); int result; result = obj.randomize() with {x > 0; x < y + z;}; endtask endclass ================================================ FILE: tests/chapter-18/18.7--in-line-constraints--randomize_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_constraints--randomize_2 :description: in-line constraints test - randomize() :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a1; rand int x; endclass class a2; int x, y; task do_randomize(a1 obj, int x, int z); int result; /* In the line below x should be a member of class a1 */ result = obj.randomize() with {x > 0; x < y + z;}; endtask endclass class env extends uvm_env; a1 obj1 = new; a2 obj2 = new; int z; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj2.x = -20; obj2.y = 5; z = 10; obj2.do_randomize(obj1, -20, z); if(obj1.x > 0 && obj1.x < obj2.y + z) begin `uvm_info("RESULT", $sformatf("obj1.x = %0d obj2.x = %0d obj2.y = %0d SUCCESS", obj1.x, obj2.x, obj2.y), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj1.x = %0d obj2.x = %0d obj2.y = %0d FAILED", obj1.x, obj2.x, obj2.y)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.7--in-line-constraints--randomize_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_constraints--randomize_3 :description: in-line constraints test - randomize() :tags: 18.7 */ class a; rand int x; endclass function int F(a obj, int y); F = obj.randomize() with (x) { x > 0; x < y; }; endfunction ================================================ FILE: tests/chapter-18/18.7--in-line-constraints--randomize_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_constraints--randomize_4 :description: in-line constraints test - randomize() :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; endclass function int F(a obj, int y); F = obj.randomize() with (x) { x > 0; x < y; }; endfunction class env extends uvm_env; a obj = new; int y; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin y = 10; F(obj, y); if(obj.x > 0 && obj.x < y) begin `uvm_info("RESULT", $sformatf("obj.x = %0d y = %0d SUCCESS", obj.x, y), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d y = %0d FAILED", obj.x, y)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.7--in-line-constraints--randomize_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_constraints--randomize_5 :description: in-line constraints test - randomize() :tags: 18.7 */ class a; rand int x; int y = -1; endclass function int F(a obj, int y); F = obj.randomize() with (x) { x > 0; x < y; }; endfunction ================================================ FILE: tests/chapter-18/18.7--in-line-constraints--randomize_6.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: in-line_constraints--randomize_6 :description: in-line constraints test - randomize() :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; int y = -1; endclass function int F(a obj, int y); F = obj.randomize() with (x) { x > 0; x < y; }; endfunction class env extends uvm_env; a obj = new; int y; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin y = 10; F(obj, y); if(obj.x > 0 && obj.x < y) begin `uvm_info("RESULT", $sformatf("obj.x = %0d y = %0d SUCCESS", obj.x, y), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d y = %0d FAILED", obj.x, y)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.7.1--local-scope-resolution_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: local_scope_resolution_0 :description: local:: scope resolution test :tags: 18.7.1 */ class a; rand int x; endclass function int F(a obj, int x); F = obj.randomize() with {x < local::x; }; endfunction ================================================ FILE: tests/chapter-18/18.7.1--local-scope-resolution_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: local_scope_resolution_1 :description: local:: scope resolution test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; endclass function int F(a obj, int x); F = obj.randomize() with {x > 0; x < local::x; }; endfunction class env extends uvm_env; a obj = new; int x; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin x = 10; F(obj, x); if(obj.x < x) begin `uvm_info("RESULT", $sformatf("obj.x = %0d x = %0d SUCCESS", obj.x, x), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("obj.x = %0d x = %0d FAILED", obj.x, x)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: disabling-random-variables-with-rand_mode_0 :description: rand_mode() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; constraint c {x > 0; x < 12; } endclass class env extends uvm_env; a obj = new; int ret1, ret2; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.x.rand_mode(0); ret1 = obj.x.rand_mode(); ret2 = obj.randomize(); if(ret1 == 0 && ret2 == 0) begin `uvm_info("RESULT", $sformatf("ret1 = %0d ret2 = %0d SUCCESS", ret1, ret2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret1 = %0d ret2 = %0d FAILED", ret1, ret2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: disabling-random-variables-with-rand_mode_1 :description: rand_mode() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; randc bit [7:0] x; constraint c {x > 0; x < 12; } endclass class env extends uvm_env; a obj = new; int ret1, ret2; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.x.rand_mode(0); ret1 = obj.x.rand_mode(); ret2 = obj.randomize(); if(ret1 == 0 && ret2 == 0) begin `uvm_info("RESULT", $sformatf("ret1 = %0d ret2 = %0d SUCCESS", ret1, ret2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret1 = %0d ret2 = %0d FAILED", ret1, ret2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: disabling-random-variables-with-rand_mode_2 :description: rand_mode() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x, y; constraint c {x > 0; x < 12; } endclass class env extends uvm_env; a obj = new; int ret1, ret2; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.rand_mode(0); obj.x.rand_mode(1); ret1 = obj.x.rand_mode(); ret2 = obj.randomize(); if(ret1 == 1 && ret2 == 1 && obj.x > 0 && obj.x < 12) begin `uvm_info("RESULT", $sformatf("ret1 = %0d ret2 = %0d obj.x = %0d SUCCESS", ret1, ret2, obj.x), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret1 = %0d ret2 = %0d obj.x = %0d FAILED", ret1, ret2, obj.x)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: disabling-random-variables-with-rand_mode_3 :description: rand_mode() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; static rand int x; constraint c {x > 0; x < 12; } endclass class env extends uvm_env; a obj1 = new; a obj2 = new; int ret1, ret2; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj1.x.rand_mode(0); ret1 = obj1.x.rand_mode(); ret2 = obj2.x.rand_mode(); if(ret1 == 0 && ret2 == 0) begin `uvm_info("RESULT", $sformatf("ret1 = %0d ret2 = %0d SUCCESS", ret1, ret2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret1 = %0d ret2 = %0d FAILED", ret1, ret2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: disabling-random-variables-with-rand_mode_4 :description: rand_mode() test :should_fail_because: The rand_mode() method is built-in and cannot be overridden. :tags: 18.8 :type: simulation elaboration */ class a1; rand int x; function int rand_mode(); return 1; endfunction endclass ================================================ FILE: tests/chapter-18/18.8--disabling-random-variables-with-rand_mode_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: disabling-random-variables-with-rand_mode_5 :description: rand_mode() test :should_fail_because: The rand_mode() method is built-in and cannot be overridden. :tags: uvm-random uvm :type: simulation elaboration :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; function int rand_mode(); return 1; endfunction endclass class env extends uvm_env; a obj = new; int ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin ret = obj.x.rand_mode(); if(ret == 1) begin `uvm_info("RESULT", $sformatf("ret = %0d SUCCESS", ret), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret = %0d FAILED", ret)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.9--controlling-constraints-with-constraint_mode_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: controlling-constraints-with-constraint_mode_0 :description: constraint_mode() test :tags: uvm-random uvm :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; constraint c1 { x < 0; } constraint c2 { x > 0; } endclass class env extends uvm_env; a obj = new; int ret1, ret2; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin obj.c1.constraint_mode(0); ret1 = obj.c1.constraint_mode(); ret2 = obj.c2.constraint_mode(); obj.randomize(); if(obj.x > 0 && ret1 == 0 && ret2 == 1) begin `uvm_info("RESULT", $sformatf("ret1 = %0d ret2 = %0d SUCCESS", ret1, ret2), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret1 = %0d ret2 = %0d FAILED", ret1, ret2)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-18/18.9--controlling-constraints-with-constraint_mode_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: controlling_constraints_with_constraint_mode_1 :description: constraint_mode() test :should_fail_because: The constraint_mode() method is built-in and cannot be overridden. :tags: 18.8 :type: simulation elaboration */ class a; rand int x; function int constraint_mode(); return 1; endfunction endclass ================================================ FILE: tests/chapter-18/18.9--controlling-constraints-with-constraint_mode_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: controlling-constraints-with-constraint_mode_2 :description: constraint_mode() test :should_fail_because: The constraint_mode() method is built-in and cannot be overridden. :tags: uvm-random uvm :type: simulation elaboration :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class a; rand int x; function int constraint_mode(); return 1; endfunction endclass class env extends uvm_env; a obj = new; int ret; function new(string name, uvm_component parent = null); super.new(name, parent); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); begin ret = obj.constraint_mode(); if(ret == 1) begin `uvm_info("RESULT", $sformatf("ret = %0d SUCCESS", ret), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("ret = %0d FAILED", ret)); end end phase.drop_objection(this); endtask: run_phase endclass module top; env environment; initial begin environment = new("env"); run_test(); end endmodule ================================================ FILE: tests/chapter-20/20.10--error.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: error_task :description: $error test :tags: 20.10 :type: parsing Note this is not a simulation test, as the $warning may result in some simulators returning bad exit status. :unsynthesizable: 1 */ module top(); initial begin $error("error"); end endmodule ================================================ FILE: tests/chapter-20/20.10--fatal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fatal_task :description: $fatal test :tags: 20.10 :type: parsing Note this is not a simulation test, as the $warning may result in some simulators returning bad exit status. :unsynthesizable: 1 */ module top(); initial begin $fatal(2, "fatal"); end endmodule ================================================ FILE: tests/chapter-20/20.10--info.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: info_task :description: $info test :tags: 20.10 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); initial begin $info("info"); end endmodule ================================================ FILE: tests/chapter-20/20.10--warning.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: warning_task :description: $warning test :tags: 20.10 :type: parsing Note this is not a simulation test, as the $warning may result in some simulators returning bad exit status. :unsynthesizable: 1 */ module top(); initial begin $warning("warning"); end endmodule ================================================ FILE: tests/chapter-20/20.14--coverage.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: coverage_routines :description: coverage routine test :tags: 20.14 :type: simulation elaboration parsing :unsynthesizable: 1 */ module DUT; endmodule module top(); int unsigned i; real r; DUT unit1(); DUT unit2(); initial begin i = $coverage_control(`SV_COV_CHECK, `SV_COV_TOGGLE, `SV_COV_HIER, $root); i = $coverage_control(`SV_COV_RESET, `SV_COV_TOGGLE, `SV_COV_MODULE, "DUT"); i = $coverage_control(`SV_COV_RESET, `SV_COV_TOGGLE, `SV_COV_MODULE, $root.top.unit1); i = $coverage_control(`SV_COV_STOP, `SV_COV_TOGGLE, `SV_COV_HIER, $root.top.unit2); i = $coverage_control(`SV_COV_START, `SV_COV_TOGGLE, `SV_COV_HIER, "DUT"); i = $coverage_get_max(`SV_COV_TOGGLE, `SV_COV_HIER, "DUT"); r = $coverage_get(`SV_COV_STATEMENT, `SV_COV_HIER, $root.top.unit1); i = $coverage_merge(`SV_COV_ASSERTION, "some_name"); i = $coverage_save(`SV_COV_FSM_STATE, "some_name"); $set_coverage_db_name("coverage.db"); $load_coverage_db("coverage.db"); r = $get_coverage(); end endmodule ================================================ FILE: tests/chapter-20/20.15--dist_chi_square.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dist_chi_square_function :description: $dist_chi_square test :tags: 20.15 :type: simulation elaboration parsing */ module top(); initial begin integer seed = 1234; $display("%d", $dist_chi_square(seed, 3)); end endmodule ================================================ FILE: tests/chapter-20/20.15--dist_erlang.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dist_erlang_function :description: $dist_erlang test :tags: 20.15 :type: simulation elaboration parsing */ module top(); initial begin integer seed = 1234; $display("%d", $dist_erlang(seed, 3, 100)); end endmodule ================================================ FILE: tests/chapter-20/20.15--dist_exponential.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dist_exponential_function :description: $dist_exponential test :tags: 20.15 :type: simulation elaboration parsing */ module top(); initial begin integer seed = 1234; $display("%d", $dist_exponential(seed, 100)); end endmodule ================================================ FILE: tests/chapter-20/20.15--dist_normal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dist_normal_function :description: $dist_normal test :tags: 20.15 :type: simulation elaboration parsing */ module top(); initial begin integer seed = 1234; $display("%d", $dist_normal(seed, 0, 100)); end endmodule ================================================ FILE: tests/chapter-20/20.15--dist_poisson.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dist_poisson_function :description: $dist_poisson test :tags: 20.15 :type: simulation elaboration parsing */ module top(); initial begin integer seed = 1234; $display("%d", $dist_poisson(seed, 100)); end endmodule ================================================ FILE: tests/chapter-20/20.15--dist_t.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dist_t_function :description: $dist_t test :tags: 20.15 :type: simulation elaboration parsing */ module top(); initial begin integer seed = 1234; $display("%d", $dist_t(seed, 3)); end endmodule ================================================ FILE: tests/chapter-20/20.15--dist_uniform.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dist_uniform_function :description: $dist_uniform test :tags: 20.15 :type: simulation elaboration parsing */ module top(); initial begin integer seed = 1234; $display("%d", $dist_uniform(seed, 0, 100)); end endmodule ================================================ FILE: tests/chapter-20/20.15--random.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: random_function :description: $random test :tags: 20.15 :type: simulation elaboration parsing */ module top(); initial begin $display("%d", $random); end endmodule ================================================ FILE: tests/chapter-20/20.2--exit.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: exit_task :description: $exit test :tags: 20.2 :unsynthesizable: 1 */ module top(); initial $exit; endmodule ================================================ FILE: tests/chapter-20/20.2--finish.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: finish_task :description: $finish test :tags: 20.2 :unsynthesizable: 1 */ module top(); initial $finish; endmodule ================================================ FILE: tests/chapter-20/20.2--stop.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: stop_task :description: $stop test :tags: 20.2 :unsynthesizable: 1 */ module top(); initial $stop; endmodule ================================================ FILE: tests/chapter-20/20.3--realtime.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: realtime_task :description: $realtime test :tags: 20.3 :unsynthesizable: 1 */ module top(); initial $display($realtime); endmodule ================================================ FILE: tests/chapter-20/20.3--stime.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: stime_task :description: $stime test :tags: 20.3 :unsynthesizable: 1 */ module top(); initial $display($stime); endmodule ================================================ FILE: tests/chapter-20/20.3--time.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: time_task :description: $time test :tags: 20.3 :unsynthesizable: 1 */ module top(); initial $display($time); endmodule ================================================ FILE: tests/chapter-20/20.4--printtimescale-hier.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: printtimescale_hier_task :description: $printtimescale hierarchy test :tags: 20.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ `timescale 1 ms / 1 us module top(); initial $printtimescale(mod0.m); endmodule `timescale 1 us / 1 ns module mod0(); mod1 m(); endmodule `timescale 1 ns / 1 ps module mod1(); initial $display("mod1"); endmodule ================================================ FILE: tests/chapter-20/20.4--printtimescale.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: printtimescale_task :description: $printtimescale test :tags: 20.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ `timescale 1 ms / 1 us module top(); initial $printtimescale; endmodule ================================================ FILE: tests/chapter-20/20.4--timeformat.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: timeformat_task :description: $timeformat test :tags: 20.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ `timescale 1 fs / 1 fs module top(); initial begin $timeformat(-9, 5, "ns", 10); $display("%t", $realtime); end endmodule ================================================ FILE: tests/chapter-20/20.5--itor.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: itor_function :description: $itor test :tags: 20.5 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%f == 20.0)", $itor(20)); end endmodule ================================================ FILE: tests/chapter-20/20.5--real-bits-conv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: realtobits_bitstoreal_functions :description: $realtobits and $bitstoreal test :tags: 20.5 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%f == 12.45)", $bitstoreal($realtobits(12.45))); end endmodule ================================================ FILE: tests/chapter-20/20.5--rtoi.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: rtoi_function :description: $rtoi test :tags: 20.5 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%d == 21)", $rtoi(21.37)); end endmodule ================================================ FILE: tests/chapter-20/20.5--shortreal-bits-conv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: shortrealtobits_bitstoshortreal_functions :description: $shortrealtobits and $bitstoshortreal test :tags: 20.5 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); shortreal s; initial begin s = $bitstoshortreal($shortrealtobits(12.45)); $display(":assert: (%0d == 1)", (s > 12.449 && s < 12.451)); end endmodule ================================================ FILE: tests/chapter-20/20.6--bits.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: bits_function :description: $bits test :tags: 20.6 :type: simulation elaboration parsing */ module top(); initial begin logic [31:0] val; $display(":assert: (%d == 32)", $bits(val)); end endmodule ================================================ FILE: tests/chapter-20/20.6--bits_type.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: bits_type_function :description: $bits with type argument :tags: 20.6 :type: simulation elaboration parsing */ module top(); typedef struct packed { logic val1; bit [7:0] val2; } mystruct; initial begin $display(":assert: (%d == 9)", $bits(mystruct)); end endmodule ================================================ FILE: tests/chapter-20/20.6--isunbounded.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: isunbounded_function :description: $isunbounded test :tags: 20.6 :type: simulation elaboration parsing */ module top(); parameter int i = $; initial begin $display(":assert: (%d == 0)", $isunbounded(1)); $display(":assert: (%d == 1)", $isunbounded(i)); end endmodule ================================================ FILE: tests/chapter-20/20.6--typename.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typename_function :description: $typename test :tags: 20.6 :type: simulation elaboration parsing */ module top(); initial begin logic val; $display(":assert: ('%s' == 'logic')", $typename(val)); end endmodule ================================================ FILE: tests/chapter-20/20.6--typename_type.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typename_type_function :description: $typename with type as an argument :tags: 20.6 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: ('%s' == 'logic')", $typename(logic)); end endmodule ================================================ FILE: tests/chapter-20/20.7--array-queries-multi-dim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array_queries_multi_dim :description: multi-dimensional array query function tests :tags: 20.7 :type: simulation elaboration parsing */ module top(); logic [31:0] arr [15:0]; initial begin $display(":assert: (%d == 2)", $dimensions(arr)); $display(":assert: (%d == 1)", $increment(arr, 2)); $display(":assert: (%d == 0)", $right(arr, 2)); $display(":assert: (%d == 31)", $left(arr, 2)); $display(":assert: (%d == 0)", $right(arr, 1)); $display(":assert: (%d == 15)", $left(arr, 1)); $display(":assert: (%d == 0)", $low(arr, 2)); $display(":assert: (%d == 31)", $high(arr, 2)); $display(":assert: (%d == 32)", $size(arr, 2)); end endmodule ================================================ FILE: tests/chapter-20/20.7--array-queries.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array_queries :description: array query function tests :tags: 20.7 :type: simulation elaboration parsing */ module top(); logic [31:0] arr; initial begin $display(":assert: (%d == 0)", $unpacked_dimensions(arr)); $display(":assert: (%d == 1)", $dimensions(arr)); $display(":assert: (%d == 1)", $increment(arr)); $display(":assert: (%d == 0)", $right(arr)); $display(":assert: (%d == 31)", $left(arr)); $display(":assert: (%d == 0)", $low(arr)); $display(":assert: (%d == 31)", $high(arr)); $display(":assert: (%d == 32)", $size(arr)); end endmodule ================================================ FILE: tests/chapter-20/20.8--atan2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: atan2_function :description: $atan2 test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display("%f", $atan2(2.1, 3.7)); end endmodule ================================================ FILE: tests/chapter-20/20.8--ceil.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: ceil_function :description: $ceil test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%f == 4)", $ceil(3.7)); end endmodule ================================================ FILE: tests/chapter-20/20.8--clog2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: clog2_function :description: $clog2 test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%d == 5)", $clog2(32)); end endmodule ================================================ FILE: tests/chapter-20/20.8--exp.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: exp_function :description: $exp test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%f > 2.718) and (%f < 2.719)", $exp(1), $exp(1)); end endmodule ================================================ FILE: tests/chapter-20/20.8--floor.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: floor_function :description: $floor test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%f == 2)", $floor(2.1)); end endmodule ================================================ FILE: tests/chapter-20/20.8--hypot.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: hypot_function :description: $hypot test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display("%f", $hypot(2.1, 3.7)); end endmodule ================================================ FILE: tests/chapter-20/20.8--ln.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: ln_function :description: $ln test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%d == 0)", $ln(1)); end endmodule ================================================ FILE: tests/chapter-20/20.8--log10.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: log10_function :description: $log10 test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%d == 2)", $log10(100)); end endmodule ================================================ FILE: tests/chapter-20/20.8--pow.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pow_function :description: $pow test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%f == 5.0625)", $pow(2.25, 2)); end endmodule ================================================ FILE: tests/chapter-20/20.8--sqrt.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sqrt_function :description: $sqrt test :tags: 20.8 :type: simulation elaboration parsing */ module top(); initial begin $display(":assert: (%d == 3)", $sqrt(9)); end endmodule ================================================ FILE: tests/chapter-20/20.9--countbits.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: countbits_function :description: $countbits test :tags: 20.9 :type: simulation elaboration parsing */ module top(); initial begin logic [31:0] val = 32'h70008421; $display(":assert: (%d == 7)", $countbits(val, '1)); $display(":assert: (%d == 7)", $countones(val)); $display(":assert: (%d == 25)", $countbits(val, '0)); $display(":assert: (%d == 32)", $countbits(val, '0, '1)); $display(":assert: (%d == 0)", $countbits(val, 'x, 'z)); end endmodule ================================================ FILE: tests/chapter-20/20.9--isunknown.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: isunknown_function :description: $isunknown test :tags: 20.9 :type: simulation elaboration parsing */ module top(); initial begin parameter [3:0] val0 = 4'b000x; parameter [3:0] val1 = 4'b000z; parameter [3:0] val2 = 4'b00xz; parameter [3:0] val3 = 4'b0000; $display(":assert: (%d == 1)", $isunknown(val0)); $display(":assert: (%d == 1)", $isunknown(val1)); $display(":assert: (%d == 1)", $isunknown(val2)); $display(":assert: (%d == 0)", $isunknown(val3)); end endmodule ================================================ FILE: tests/chapter-20/20.9--onehot.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: onehot_function :description: $onehot test :tags: 20.9 :type: simulation elaboration parsing */ module top(); initial begin logic [31:0] val0 = 32'h00010000; logic [31:0] val1 = 32'h00010100; logic [31:0] val2 = 32'h00000000; $display(":assert: (%d == 1)", $onehot(val0)); $display(":assert: (%d == 0)", $onehot(val1)); $display(":assert: (%d == 0)", $onehot(val2)); end endmodule ================================================ FILE: tests/chapter-20/20.9--onehot0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: onehot0_function :description: $onehot0 test :tags: 20.9 :type: simulation elaboration parsing */ module top(); initial begin logic [31:0] val0 = 32'h00010000; logic [31:0] val1 = 32'h00030000; logic [31:0] val2 = 32'h00000000; $display(":assert: (%d == 1)", $onehot0(val0)); $display(":assert: (%d == 0)", $onehot0(val1)); $display(":assert: (%d == 1)", $onehot0(val2)); end endmodule ================================================ FILE: tests/chapter-21/21.2--display-boh.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: display_boh :description: $display test :tags: 21.2 :type: simulation elaboration parsing */ module top(); initial begin int val = 1234; $displayb(val); $displayo(val); $displayh(val); end endmodule ================================================ FILE: tests/chapter-21/21.2--display.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: display_task :description: $display test :tags: 21.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); initial begin int val = 1234; $display(val); end endmodule ================================================ FILE: tests/chapter-21/21.2--monitor.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: monitor_task :description: $monitor test :tags: 21.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); int a; initial begin $monitoron; $monitor(a); $monitorb(a); $monitoro(a); $monitorh(a); $monitoroff; end endmodule ================================================ FILE: tests/chapter-21/21.2--strobe.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: strobe_task :description: $strobe test :tags: 21.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); logic clk; int a; always @(posedge clk) begin $strobe(a); $strobeb(a); $strobeo(a); $strobeh(a); end endmodule ================================================ FILE: tests/chapter-21/21.2--write-boh.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: write_boh :description: $write test :tags: 21.2 :type: simulation elaboration parsing */ module top(); initial begin int val = 1234; $writeb(val); $writeo(val); $writeh(val); end endmodule ================================================ FILE: tests/chapter-21/21.2--write.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: write_task :description: $write test :tags: 21.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); initial begin int val = 1234; $write(val); end endmodule ================================================ FILE: tests/chapter-21/21.3--fdisplay-boh.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fdisplay_boh :description: $fdisplay test :tags: 21.3 :type: simulation elaboration parsing */ module top(); int fd; string str = "abc"; initial begin fd = $fopen("tmp.txt", "w"); $fdisplayb(fd, str); $fdisplayo(fd, str); $fdisplayh(fd, str); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--fdisplay.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fdisplay_task :description: $fdisplay test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); int fd; string str = "abc"; initial begin fd = $fopen("tmp.txt", "w"); $fdisplay(fd, str); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--feof.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: feof_function :description: $feof test :tags: 21.3 :type: simulation elaboration parsing */ module top(); initial begin int fd; fd = $fopen("tmp.txt", "w"); $display($feof(fd)); $fclose(fd); end endmodule ================================================ FILE: tests/chapter-21/21.3--ferror.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: ferror_function :description: $ferror test :tags: 21.3 :type: simulation elaboration parsing */ module top(); initial begin int fd; string str; integer errno; fd = $fopen("tmp.txt", "w"); errno = $ferror(fd, str); $display(errno); $display(str); $fclose(fd); end endmodule ================================================ FILE: tests/chapter-21/21.3--fflush.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fflush_task :description: $fflush test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); initial begin int fd; fd = $fopen("tmp.txt", "w"); $fflush(); $fclose(fd); end endmodule ================================================ FILE: tests/chapter-21/21.3--fgetc.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fgetc_function :description: $fgetc test :tags: 21.3 :type: simulation elaboration parsing */ module top(); int fd; int c; initial begin fd = $fopen("tmp.txt", "w"); c = $fgetc(fd); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--fgets.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fgets_function :description: $fgets test :tags: 21.3 :type: simulation elaboration parsing */ module top(); int fd; string tmp; initial begin fd = $fopen("tmp.txt", "w"); $fgets(tmp, fd); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--file.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: file_tasks :description: $fopen and $fclose test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); initial begin int fd; fd = $fopen("tmp.txt", "w"); $fclose(fd); end endmodule ================================================ FILE: tests/chapter-21/21.3--fmonitor.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fmonitor_task :description: $fmonitor test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); logic a; int fd; string str = "abc"; initial begin fd = $fopen("tmp.txt", "w"); $fmonitor(fd, a); $fmonitorb(fd, a); $fmonitoro(fd, a); $fmonitorh(fd, a); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--fpos.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: file_pos_tasks :description: $fseek, $ftell and $rewind test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); initial begin int fd; fd = $fopen("tmp.txt", "w"); $display(":assert: (%d == 0)", $ftell(fd)); $fseek(fd, 12, 0); $display(":assert: (%d == 12)", $ftell(fd)); $rewind(fd); $display(":assert: (%d == 0)", $ftell(fd)); $fclose(fd); end endmodule ================================================ FILE: tests/chapter-21/21.3--fread.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fread_task :description: $fread test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); int fd; int c; initial begin fd = $fopen("tmp.txt", "w"); $fread(c, fd); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--fscanf.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fscanf_task :description: $fscanf test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); int fd; int c; initial begin fd = $fopen("tmp.txt", "w"); $fscanf(fd, "%d", c); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--fstrobe.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fstrobe_task :description: $fstrobe test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); logic clk; logic a; int fd; always @(posedge clk) begin $fstrobe(fd, a); $fstrobe(fd, a); $fstrobe(fd, a); $fstrobe(fd, a); end initial begin fd = $fopen("tmp.txt", "w"); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--fwrite-boh.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fwrite_boh :description: $fwrite test :tags: 21.3 :type: simulation elaboration parsing */ module top(); int fd; string str = "abc"; initial begin fd = $fopen("tmp.txt", "w"); $fwriteb(fd, str); $fwriteo(fd, str); $fwriteh(fd, str); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--fwrite.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fwrite_task :description: $fwrite test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); int fd; string str = "abc"; initial begin fd = $fopen("tmp.txt", "w"); $fwrite(fd, str); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.3--sscanf.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sscanf_task :description: $sscanf test :tags: 21.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); string str = "1234"; int c; initial begin $sscanf(str, "%d", c); $display(":assert: (%d == %s)", c, str); end endmodule ================================================ FILE: tests/chapter-21/21.3--ungetc.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: ungetc_function :description: $ungetc test :tags: 21.3 :type: simulation elaboration parsing */ module top(); int fd; initial begin fd = $fopen("tmp.txt", "w"); $ungetc(123, fd); $display(":assert: (%d == %d)", 123, $fgetc(fd)); end final $fclose(fd); endmodule ================================================ FILE: tests/chapter-21/21.4--readmemb.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: readmemb_task :description: $readmemb test :tags: 21.4 :type: parsing */ module top(); logic [31:0] mem0 [1023:0]; string fname0 = "test0.mem"; initial begin $readmemb(fname0, mem0); end endmodule ================================================ FILE: tests/chapter-21/21.4--readmemh.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: readmemh_task :description: $readmemh test :tags: 21.4 :type: parsing */ module top(); logic [31:0] mem1 [1023:0]; string fname1 = "test1.mem"; initial begin $readmemh(fname1, mem1); end endmodule ================================================ FILE: tests/chapter-21/21.6--test.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: test_plusargs :description: $test$plusargs test :tags: 21.6 :type: simulation elaboration parsing */ module top(); initial begin if ($test$plusargs("TEST")) $display("TEST argument found"); else $display("TEST argument not found"); end endmodule ================================================ FILE: tests/chapter-21/21.6--value.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: value_plusargs :description: $value$plusargs test :tags: 21.6 :type: simulation elaboration parsing */ module top(); integer i; initial begin if ($value$plusargs("TEST=%d", i)) $display("i=%d", i); else $display("TEST not found"); end endmodule ================================================ FILE: tests/chapter-21/21.7--dumpfile.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: vcd_dump_test :description: vcd dump tests :tags: 21.7 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); integer i; initial begin $dumpfile("out.vcd"); $dumpvars; $dumplimit(1024*1024); i = 1; #100 i = 2; #200 $dumpoff; i = 3; #800 $dumpon; i = 4; #100 $dumpflush; i = 5; #300 $dumpall; i = 6; end endmodule ================================================ FILE: tests/chapter-21/21.7--dumpports.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: vcd_dumpports_test :description: vcd dump ports tests :tags: 21.7 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top(); integer i; string fname = "out.vcd"; initial begin $dumpports(top, fname); $dumpportslimit(1024*1024, fname); i = 1; #100 i = 2; #200 $dumpportsoff(fname); i = 3; #800 $dumpportson(fname); i = 4; #100 $dumpportsflush(fname); i = 5; #300 $dumpportsall(fname); i = 6; end endmodule ================================================ FILE: tests/chapter-22/22.10--celldefine-basic-1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.10--celldefine-basic-1 :description: Test :tags: 22.10 :type: preprocessing */ `celldefine `endcelldefine ================================================ FILE: tests/chapter-22/22.10--celldefine-basic-2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.10--celldefine-basic-2 :description: Test :tags: 22.10 :type: preprocessing */ `celldefine ================================================ FILE: tests/chapter-22/22.11--pragma-basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.11--pragma-basic :description: Test :tags: 22.11 :type: preprocessing */ `pragma pragma_name "pragma_value" ================================================ FILE: tests/chapter-22/22.11--pragma-complex.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.11--pragma-complex :description: Test :tags: 22.11 :type: preprocessing */ `pragma foo something, somethingelse = 7, "abcdef" ================================================ FILE: tests/chapter-22/22.11--pragma-invalid.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.11--pragma-invalid :description: Test :should_fail_because: The pragma specification is identified by the pragma_name, which follows the `pragma directive. :tags: 22.11 :type: preprocessing */ `pragma ================================================ FILE: tests/chapter-22/22.11--pragma-nested.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.11--pragma-nested :description: Test :tags: 22.11 :type: preprocessing */ `pragma foo something, somethingelse = 7, "abcdef", ( hello, ( "world", pr = 4, "gm" ) ), a ================================================ FILE: tests/chapter-22/22.11--pragma-number-multi.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.11--pragma-number-multi :description: Test :tags: 22.11 :type: preprocessing */ `pragma pragma_number_other a = 123, b = 4 ================================================ FILE: tests/chapter-22/22.11--pragma-number.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.11--pragma-number :description: Test :tags: 22.11 :type: preprocessing */ `pragma pragma_number 123 ================================================ FILE: tests/chapter-22/22.12--line-basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.12--line-basic :description: Test :tags: 22.12 :type: preprocessing */ `line 1 "somefile" 2 ================================================ FILE: tests/chapter-22/22.12--line-complex.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.12--line-complex :description: Test :tags: 22.12 :type: preprocessing */ `line 1 "somefile" 2 `line 123 "someother" 1 `line 8273 "somefile" 0 `resetall `line 5 "foo" 2 ================================================ FILE: tests/chapter-22/22.12--line-illegal-1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.12--line-illegal-1 :description: The level parameter shall be 0, 1, or 2 :should_fail_because: The level parameter shall be 0, 1, or 2 :tags: 22.12 :type: preprocessing */ `line 1 "somefile" 3 ================================================ FILE: tests/chapter-22/22.12--line-illegal-2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.12--line-illegal-2 :description: The filename parameter shall be a string literal :should_fail_because: The filename parameter shall be a string literal :tags: 22.12 :type: preprocessing */ `line 1 somefile 2 ================================================ FILE: tests/chapter-22/22.12--line-illegal-3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.12--line-illegal-3 :description: The number parameter shall be a positive integer that specifies the new line number :should_fail_because: The number parameter shall be a positive integer that specifies the new line number :tags: 22.12 :type: preprocessing */ `line -12 "somefile" 3 ================================================ FILE: tests/chapter-22/22.12--line-illegal-4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.12--line-illegal-4 :description: The level parameter shall be 0, 1, or 2 :should_fail_because: The level parameter shall be 0, 1, or 2 :tags: 22.12 :type: preprocessing */ `line 1 "somefile" ================================================ FILE: tests/chapter-22/22.12--line-illegal-5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.12--line-illegal-5 :description: Missing filename :should_fail_because: Missing filename :tags: 22.12 :type: preprocessing */ `line 1 ================================================ FILE: tests/chapter-22/22.3--resetall_basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.3--resetall_basic :description: Test :tags: 22.3 :type: preprocessing parsing */ `resetall module top (); endmodule ================================================ FILE: tests/chapter-22/22.3--resetall_illegal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.3--resetall_illegal :description: It shall be illegal for the `resetall directive to be specified within a design element. :should_fail_because: It shall be illegal for the `resetall directive to be specified within a design element. :tags: 22.3 :type: preprocessing parsing */ `resetall module top (); `resetall endmodule ================================================ FILE: tests/chapter-22/22.3--resetall_multiple.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.3--resetall_multiple :description: Test :tags: 22.3 :type: preprocessing parsing */ `resetall `resetall `resetall module top (); endmodule ================================================ FILE: tests/chapter-22/22.4--check_included_definitions.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.4--check_included_definitions :description: Test :tags: 22.4 :type: preprocessing parsing */ `include "include_directory/defs.sv" module top (); initial begin $display(":assert:(`TWO_PLUS_TWO == 5)"); $display(":assert:('%s' == '%s')", `define_var, "define_var"); end endmodule ================================================ FILE: tests/chapter-22/22.4--include_basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.4--include_basic :description: Test :tags: 22.4 :type: preprocessing parsing */ `include "dummy_include.sv" module top (); endmodule ================================================ FILE: tests/chapter-22/22.4--include_basic_rpath.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.4--include_basic_rpath :description: Test :tags: 22.4 :type: preprocessing parsing */ `include "dummy_include.sv" module top (); endmodule ================================================ FILE: tests/chapter-22/22.4--include_from_other_directory.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.4--include_from_other_directory :description: Test :tags: 22.4 :type: preprocessing parsing */ `include "include_directory/defs.sv" module top (); endmodule ================================================ FILE: tests/chapter-22/22.4--include_via_define.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.4--include_via_define :description: Though not well documented, real world code does `defines that cause includes :tags: 22.4 :type: preprocessing parsing */ `define DO_INCLUDE(FN) `include FN // Check that multiple define references don't throw a multiple `include-on-line error `DO_INCLUDE("dummy_include.sv") `DO_INCLUDE("dummy_include.sv") // Check that ifdefs `ifdef NEVER `DO_INCLUDE("SHOULD_NOT_BE_INCLUDED") `endif module top (); endmodule ================================================ FILE: tests/chapter-22/22.4--include_with_comment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.4--include_with_comment :description: Test :tags: 22.4 :type: preprocessing parsing */ `include "dummy_include.sv" // comments after `include are perfectly legal module top (); endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_1 :description: Test :tags: 22.5.1 :type: preprocessing */ `define D(x,y) initial $display("start", x , y, "end"); module top (); `D( "msg1" , "msg2" ) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_10.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_10 :description: Test :tags: 22.5.1 :type: preprocessing */ `define MACRO1(a=5,b="B",c) initial $display(a,,b,,c); module top (); `MACRO1 ( 1 , , 3 ) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_11.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_11 :description: Test :tags: 22.5.1 :type: preprocessing */ `define MACRO1(a=5,b="B",c) initial $display(a,,b,,c); module top (); `MACRO1 ( , 2, ) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_12.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_12 :description: Test :should_fail_because: If fewer actual arguments are specified than the number of formal arguments and all the remaining formal arguments have defaults, then the defaults are substituted for the additional formal arguments. It shall be an error if any of the remaining formal arguments does not have a default specified. :tags: 22.5.1 :type: preprocessing */ `define MACRO1(a=5,b="B",c) initial $display(a,,b,,c); module top (); `MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_13.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_13 :description: Test :tags: 22.5.1 :type: preprocessing */ `define MACRO2(a=5, b, c="C") initial $display(a,,b,,c); module top (); `MACRO2 (1, , 3) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_14.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_14 :description: Test :tags: 22.5.1 :type: preprocessing */ `define MACRO2(a=5, b, c="C") initial $display(a,,b,,c); module top (); `MACRO2 (, 2, ) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_15.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_15 :description: Test :tags: 22.5.1 :type: preprocessing */ `define MACRO2(a=5, b, c="C") initial $display(a,,b,,c); module top (); `MACRO2 (, 2) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_16.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_16 :description: Test :tags: 22.5.1 :type: preprocessing */ `define MACRO3(a=5, b=0, c="C") initial $display(a,,b,,c); module top (); `MACRO3 ( 1 ) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_17.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_17 :description: Test :tags: 22.5.1 :type: preprocessing */ `define MACRO3(a=5, b=0, c="C") initial $display(a,,b,,c); module top (); `MACRO3 ( ) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_18.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_18 :description: Test :should_fail_because: For a macro with arguments, the parentheses are always required in the macro call, even if all the arguments have defaults. :tags: 22.5.1 :type: preprocessing */ `define MACRO3(a=5, b=0, c="C") initial $display(a,,b,,c); module top (); `MACRO3 endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_19.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_19 :description: Test :tags: 22.5.1 :type: preprocessing */ `define wordsize 8 module top (); logic [1:`wordsize] data; endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_2 :description: Test :tags: 22.5.1 :type: preprocessing */ `define D(x,y) initial $display("start", x , y, "end"); module top (); `D( " msg1", ) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_20.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_20 :description: Test :tags: 22.5.1 :type: preprocessing */ `define var_nand(dly) nand #dly module top (); `var_nand(2) g121 (q21, n10, n11); `var_nand(5) g122 (q22, n10, n11); endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_21.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_21 :description: Test :should_fail_because: text specified for macro text shall not be split across string literals :tags: 22.5.1 :type: preprocessing */ `define first_half "start of string module top (); initial $display(`first_half end of string"); endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_22.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_22 :description: Test :tags: 22.5.1 :type: preprocessing */ `define max(a,b)((a) > (b) ? (a) : (b)) ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_23.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_23 :description: Test :should_fail_because: All compiler directives shall be considered predefined macro names; it shall be illegal to redefine a compiler directive as a macro name. :tags: 22.5.1 :type: preprocessing */ `define define "illegal" ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_24.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_24 :description: Test :tags: 22.5.1 :type: preprocessing */ module top (); `define HI Hello `define LO "`HI, world" `define H(x) "Hello, x" initial begin $display("`HI, world"); $display(`LO); $display(`H(world)); end endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_25.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_25 :description: Test :tags: 22.5.1 :type: preprocessing */ `define msg(x,y) `"x: `\`"y`\`"`" module top (); initial $display(`msg(left side,right side)); endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_26.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_26 :description: Test :tags: 22.5.1 :type: preprocessing */ `define append(f) f``_master module top (); initial $display(`append(clock)); endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_3 :description: Test :tags: 22.5.1 :type: preprocessing */ `define D(x,y) initial $display("start", x , y, "end"); module top (); `D(, "msg2 ") endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_4 :description: Test :tags: 22.5.1 :type: preprocessing */ `define D(x,y) initial $display("start", x , y, "end"); module top (); `D(,) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_5 :description: Test :tags: 22.5.1 :type: preprocessing */ `define D(x,y) initial $display("start", x , y, "end"); module top (); `D( , ) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_6.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_6 :description: Test :should_fail_because: If fewer actual arguments are specified than the number of formal arguments and all the remaining formal arguments have defaults, then the defaults are substituted for the additional formal arguments. It shall be an error if any of the remaining formal arguments does not have a default specified. :tags: 22.5.1 :type: preprocessing */ `define D(x,y) initial $display("start", x , y, "end"); module top (); `D("msg1") endmodule ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_7.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_7 :description: Test :should_fail_because: To use a macro defined with arguments, the name of the text macro shall be followed by a list of actual arguments in parentheses, separated by commas. :tags: 22.5.1 :type: preprocessing */ `define D(x,y) initial $display("start", x , y, "end"); `D() ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_8.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_8 :description: Test :should_fail_because: It shall be an error to specify more actual arguments than the number of formal arguments. :tags: 22.5.1 :type: preprocessing */ `define D(x,y) initial $display("start", x , y, "end"); `D(,,) ================================================ FILE: tests/chapter-22/22.5.1--define-expansion_9.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_expansion_9 :description: Test :tags: 22.5.1 :type: preprocessing */ `define MACRO1(a=5,b="B",c) initial $display(a,,b,,c); module top (); `MACRO1 ( , 2, 3 ) endmodule ================================================ FILE: tests/chapter-22/22.5.1--define.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define :description: Test :tags: 22.5.1 :type: preprocessing */ `define FOUR 5 `define SOMESTRING "somestring" ================================================ FILE: tests/chapter-22/22.5.1--define_and_resetall.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--define_and_resetall :description: The text macro facility is not affected by the compiler directive `resetall :tags: 22.5.1 :type: simulation elaboration preprocessing */ `define SOMESTRING "somestring" `resetall module top (); initial begin $display(":assert:('%s' == '%s')", `SOMESTRING, "somestring"); end endmodule ================================================ FILE: tests/chapter-22/22.5.1--include-define-expansion.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.1--include-define-expansion :description: Test :tags: 22.5.1 :type: preprocessing */ `define foo(the_file) `"the_file`" `include `foo(dummy_include.sv) ================================================ FILE: tests/chapter-22/22.5.2--undef-basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.2--undef-basic :description: Test :tags: 22.5.2 :type: preprocessing */ `define FOO "foo" `undef FOO ================================================ FILE: tests/chapter-22/22.5.2--undef-nonexisting.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.2--undef-nonexisting :description: Test :tags: 22.5.2 :type: preprocessing */ `undef FOO `undef BAR ================================================ FILE: tests/chapter-22/22.5.3--undefineall-and-redefine.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.3--undefineall-and-redefine :description: Test :tags: 22.5.3 :type: preprocessing */ `define FOO "foo" `undefineall `define FOO 5 `undefineall `define FOO(x,y) (x + y) ================================================ FILE: tests/chapter-22/22.5.3--undefineall-basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.5.3--undefineall-basic :description: Test :tags: 22.5.3 :type: preprocessing */ `undefineall ================================================ FILE: tests/chapter-22/22.6--ifdef-behavioral.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.6--ifdef-behavioral :description: Test :tags: 22.6 :type: preprocessing */ module and_op (a, b, c); output a; input b, c; `ifdef behavioral wire a = b & c; `else and a1 (a,b,c); `endif endmodule ================================================ FILE: tests/chapter-22/22.6--ifdef-chained-nested.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.6--ifdef-chained-nested :description: Test :tags: 22.6 :type: preprocessing */ module test; `ifdef first_block `ifndef second_nest initial $display("first_block is defined"); `else initial $display("first_block and second_nest defined"); `endif `elsif second_block initial $display("second_block defined, first_block is not"); `else `ifndef last_result initial $display("first_block, second_block,", " last_result not defined."); `elsif real_last initial $display("first_block, second_block not defined,", " last_result and real_last defined."); `else initial $display("Only last_result defined!"); `endif `endif endmodule ================================================ FILE: tests/chapter-22/22.6--ifdef-nested.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.6--ifdef-nested :description: Test :tags: 22.6 :type: preprocessing */ module test(out); output out; `define wow `define nest_one `define second_nest `define nest_two `ifdef wow initial $display("wow is defined"); `ifdef nest_one initial $display("nest_one is defined"); `ifdef nest_two initial $display("nest_two is defined"); `else initial $display("nest_two is not defined"); `endif `else initial $display("nest_one is not defined"); `endif `else initial $display("wow is not defined"); `ifdef second_nest initial $display("second_nest is defined"); `else initial $display("second_nest is not defined"); `endif `endif endmodule ================================================ FILE: tests/chapter-22/22.7--timescale-basic-1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.7--timescale-basic-1 :description: Test :tags: 22.7 :type: preprocessing */ `timescale 1 ns / 1 ps ================================================ FILE: tests/chapter-22/22.7--timescale-basic-2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.7--timescale-basic-2 :description: Test :tags: 22.7 :type: preprocessing */ `timescale 10 us / 100 ns ================================================ FILE: tests/chapter-22/22.7--timescale-basic-3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.7--timescale-basic-3 :description: Test :should_fail_because: The integers in `timescale arguments specify an order of magnitude for the size of the value; the valid integers are 1, 10, and 100 :tags: 22.7 :type: simulation elaboration */ `timescale 9 ns / 1 ps ================================================ FILE: tests/chapter-22/22.7--timescale-basic-4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.7--timescale-basic-4 :description: Test :should_fail_because: The time_precision argument shall be at least as precise as the time_unit argument; it cannot specify a longerunit of time than time_unit. :tags: 22.7 :type: simulation elaboration */ `timescale 1 ns / 10 ns ================================================ FILE: tests/chapter-22/22.7--timescale-module.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.7--timescale-module :description: Test :tags: 22.7 :type: preprocessing :unsynthesizable: 1 */ `timescale 10 ns / 1 ns module test; logic set; parameter d = 1.55; initial begin #d set = 0; #d set = 1; end endmodule ================================================ FILE: tests/chapter-22/22.7--timescale-reset.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.7--timescale-reset :description: Test :tags: 22.7 :type: preprocessing */ `timescale 1 ns / 1 ps `resetall `timescale 10 us / 100 ns ================================================ FILE: tests/chapter-22/22.8--default_nettype-redefinition.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.8--default_nettype-redefinition :description: Test :tags: 22.8 :type: preprocessing */ `default_nettype wire `default_nettype tri `default_nettype tri0 `default_nettype tri1 `default_nettype wand `default_nettype triand `default_nettype wor `default_nettype trior `default_nettype trireg `default_nettype uwire `default_nettype none ================================================ FILE: tests/chapter-22/22.8--default_nettype.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.8--default_nettype :description: Test :tags: 22.8 :type: preprocessing */ `default_nettype wire ================================================ FILE: tests/chapter-22/22.9--unconnected_drive-basic-2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.9--unconnected_drive-basic-2 :description: Test :tags: 22.9 :type: preprocessing */ `unconnected_drive pull1 ================================================ FILE: tests/chapter-22/22.9--unconnected_drive-basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.9--unconnected_drive-basic :description: Test :tags: 22.9 :type: preprocessing */ `unconnected_drive pull1 `nounconnected_drive ================================================ FILE: tests/chapter-22/22.9--unconnected_drive-invalid-1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.9--unconnected_drive-invalid-1 :description: Test :should_fail_because: The directive `unconnected_drive takes one of two arguments - pull1 or pull0. :tags: 22.9 :type: simulation elaboration */ `unconnected_drive `nounconnected_drive ================================================ FILE: tests/chapter-22/22.9--unconnected_drive-invalid-2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.9--unconnected_drive-invalid-2 :description: Test unconnected drive macro with argument other than pull0 and pull1 :should_fail_because: The directive `unconnected_drive takes one of two arguments - pull1 or pull0 :tags: 22.9 :type: simulation elaboration */ `unconnected_drive pull2 `nounconnected_drive ================================================ FILE: tests/chapter-22/22.9--unconnected_drive-invalid-3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: 22.9--unconnected_drive-invalid-3 :description: Test :should_fail_because: use a strength keyword with `nounconnected_drive macro :tags: 22.9 :type: simulation elaboration */ `unconnected_drive pull0 `nounconnected_drive pull0 ================================================ FILE: tests/chapter-22/dummy_include.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dummy_include :description: Utility for testing `include directive :type: preprocessing :tags: 22.4 */ ================================================ FILE: tests/chapter-22/include_directory/defs.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: defs :description: Utility for testing `include directive :type: preprocessing :tags: 22.4 */ `define define_var "define_var" `define TWO_PLUS_TWO 5 ================================================ FILE: tests/chapter-23/23.2--macromodule-definition.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: macromodule_definition :description: macromodule definition test :tags: 23.2 */ macromodule top(); endmodule ================================================ FILE: tests/chapter-23/23.2--module-definition.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: module_definition :description: module definition test :tags: 23.2 */ module top(); endmodule ================================================ FILE: tests/chapter-23/23.2--module-label.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: module_definition :description: module w/ named end test :tags: 23.2 :type: simulation elaboration parsing */ module top(); endmodule : top ================================================ FILE: tests/chapter-24/24.3--program.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: program_construct :description: program construct test :tags: 24.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ program prog(input wire a, input wire b); initial $display(":assert: (%d == %d)", a, b); endprogram module top(); wire a = 1; wire b = 1; prog p(a, b); endmodule ================================================ FILE: tests/chapter-25/25.3-interface.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: interface :description: interface test :tags: 25.3 :top_module: top */ interface test_bus; logic test_pad; endinterface: test_bus module sub(test_bus iface); endmodule module top; test_bus iface(); sub sub (.iface); endmodule ================================================ FILE: tests/chapter-26/26.2--package-decl.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: package_decl :description: package declaration test :tags: 26.2 */ module top(); endmodule package mypkg; function int add(int a, b); return a + b; endfunction endpackage : mypkg ================================================ FILE: tests/chapter-26/26.3--package-ref.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: package_ref :description: package reference test :tags: 26.3 :type: simulation elaboration parsing */ package mypkg; function int add(int a, b); return a + b; endfunction endpackage : mypkg module top(); initial $display(":assert: (%d == 4)", mypkg::add(1, 3)); endmodule ================================================ FILE: tests/chapter-5/5.10-structure-arrays-illegal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: structure-arrays-illegal :description: Structure array assignment tests :should_fail_because: C-like assignment is illegal :tags: 5.10 :type: simulation elaboration */ module top(); typedef struct { int a; int b; } ms_t; /* C-like assignment is illegal */ ms_t ms[1:0] = '{0, 0, 1, 1}; endmodule ================================================ FILE: tests/chapter-5/5.10-structure-arrays.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: structure-arrays :description: Structure array assignment tests :tags: 5.10 */ module top(); typedef struct { int a; int b; } ms_t; ms_t ms[1:0] = '{'{0, 0}, '{1, 1}}; endmodule ================================================ FILE: tests/chapter-5/5.10-structure-replication.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: structure-replication :description: Structure replication assignment tests :tags: 5.10 */ module top(); struct {int X,Y,Z;} XYZ = '{3{1}}; typedef struct {int a,b[4];} ab_t; int a,b,c; initial begin ab_t v1[1:0] [2:0]; v1 = '{2{'{3{'{a,'{2{b,c}}}}}}}; end endmodule ================================================ FILE: tests/chapter-5/5.10-structures.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: structure :description: Structure assignment tests :tags: 5.10 */ module top(); typedef struct { int a; int b; } ms_t; ms_t ms; initial begin ms = '{ 0, 1}; ms = '{ default:1, int:1}; ms = '{ int:0, int:1}; end endmodule ================================================ FILE: tests/chapter-5/5.11-arrays-key-index.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-key-index :description: Basic arrays test :tags: 5.11 */ module top(); typedef int triple [1:3]; triple b = '{1:1, default:0}; endmodule ================================================ FILE: tests/chapter-5/5.11-arrays-replication.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-replication :description: Basic arrays test :tags: 5.11 */ module top(); int n[1:2][1:6] = '{2{'{3{4, 5}}}}; endmodule ================================================ FILE: tests/chapter-5/5.11-arrays.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays :description: Basic arrays test :tags: 5.11 */ module top(); int n[1:2][1:3] = '{'{0,1,2},'{3{4}}}; endmodule ================================================ FILE: tests/chapter-5/5.12-attributes-case.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: attributes-case :description: Assing attributes to a case statement :tags: 5.12 */ module top(); reg [1:0] a; bit b; initial begin (* full_case, parallel_case *) case (a) 2'b00 : b = 0; 2'b01, 2'b10 : b = 1; default : b = 0; endcase (* full_case = 1 *) (* parallel_case = 1 *) case (a) 2'b00 : b = 0; 2'b01, 2'b10 : b = 1; default : b = 0; endcase (* full_case, parallel_case = 0 *) case (a) 2'b00 : b = 0; 2'b01, 2'b10 : b = 1; default : b = 0; endcase end endmodule ================================================ FILE: tests/chapter-5/5.12-attributes-conditional.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: attributes-conditional :description: Assing attributes to a conditional operator :tags: 5.12 */ module top(); bit a, b, c, d; initial begin a = b ? (* no_glitch *) c : d; end endmodule ================================================ FILE: tests/chapter-5/5.12-attributes-module.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: attributes-module :description: Assing attributes to a module :tags: 5.12 */ (* optimize_power *) module topa(); endmodule (* optimize_power=0 *) module topb(); endmodule (* optimize_power=1 *) module topc(); endmodule ================================================ FILE: tests/chapter-5/5.12-attributes-operator.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: attributes-operator :description: Assing attributes to an operator :tags: 5.12 */ module top(); logic [7:0] a; logic [7:0] b; logic [7:0] c; initial begin a = b + (* mode = "cla" *) c; end endmodule ================================================ FILE: tests/chapter-5/5.12-attributes-variable.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: attributes-variable :description: Assing attributes to a variable :tags: 5.12 */ module top(); (* fsm_state *) logic [7:0] a; (* fsm_state=1 *) logic [7:0] b; (* fsm_state=0 *) logic [7:0] c; endmodule ================================================ FILE: tests/chapter-5/5.13-builtin-methods-strings.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: builtin-methods-string :description: Check if built-in methods can be called :tags: 5.13 */ module top(); string a = "test"; initial begin $display("length check: %d\n", a.len()); end endmodule ================================================ FILE: tests/chapter-5/5.4--coments.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: comments :description: A module testing system verilog comments :tags: 5.4 */ module empty ( ); /* multi line comment */ // single line comment endmodule ================================================ FILE: tests/chapter-5/5.6--identifiers.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: identifiers :description: Identifiers that should be accepted :tags: 5.6 */ module identifiers(); reg shiftreg_a; reg busa_index; reg error_condition; reg merge_ab; reg _bus3; reg n$657; /* Should also be case sensitive, * should not cause a conflict here */ reg sensitive; reg Sensitive; endmodule ================================================ FILE: tests/chapter-5/5.6--wrong-identifiers.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: wrong-identifiers :description: Identifiers that should not be accepted :should_fail_because: The first character of a simple identifier shall not be a digit or $ :tags: 5.6 */ module identifiers(); reg $dollar; reg 0number; endmodule ================================================ FILE: tests/chapter-5/5.6.1--escaped-identifiers.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: escaped-identifiers :description: Escaped identifiers that should be accepted :tags: 5.6.1 */ module identifiers(); reg \busa+index ; reg \-clock ; reg \***error-condition*** ; reg \net1/\net2 ; reg \{a,b} ; reg \a*(b+c) ; endmodule ================================================ FILE: tests/chapter-5/5.6.1--nonescaped-access.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: nonescaped-access :description: Escaped identifiers can be referenced by nonescaped name :tags: 5.6.1 */ `default_nettype none module identifiers(); reg \cpu3 ; wire reference_test; assign reference_test = cpu3; endmodule ================================================ FILE: tests/chapter-5/5.6.3--system-functions.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: system-functions :description: Calling system functions :tags: 5.6.3 */ module systemfn(); /* Note: * This does not test all the individual system calls. * It just verifies if the concept exists using one of the * calls. */ initial $display("hello world"); endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-begin-keywords.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: begin-keywords :description: Begin keywords check :tags: 5.6.4 */ `begin_keywords "1364-2001" // use IEEE Std 1364-2001 Verilog keywords module b_kw(); reg logic; // OK: "logic" is not a keyword in 1364-2001 endmodule `end_keywords ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-celldefine.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: celldefine :description: Celldefine check :tags: 5.6.4 */ `celldefine module cd(); endmodule `endcelldefine module ncd(); endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-debug-line.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: debug-line :description: Debugging compiler directives :tags: 5.6.4 */ module directives(); `line 1 "5.6.4--compiler-directives-debug-line.sv" 1 endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-debug.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: debug-directives :description: Debugging compiler directives :tags: 5.6.4 */ module directives(); initial $display("At %s @ %d\n", `__FILE__, `__LINE__); endmodule; ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-default-nettype.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: default-nettype :description: Default nettype check :tags: 5.6.4 */ `default_nettype wire `default_nettype none module dn(); endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-define.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: define-directive :description: Define and undef checks :tags: 5.6.4 */ `define XXX 1 `ifdef XXX `undef XXX `elsif YYY `define XXX 0 `endif `ifndef YYY `define YYY 0 `else `define XXX 0 `endif `undefineall module d(); endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-include.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: include-directive :description: Include empty file :tags: 5.6.4 */ `include "/dev/null" module empty(); endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-pragma.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pragma-directive :description: Try to set a pragma :tags: 5.6.4 */ module ts(); `pragma protect wire protected_wire; `pragma protect end endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-preprocessor-macro_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: compiler_directives_preprocessor_macro_0 :description: Read preprocessing macro from template (:defines: marker) :tags: 5.6.4 :type: preprocessing :defines: TEST_VAR */ `ifdef TEST_VAR `else TEST_VAR parsed not correctly from template `endif ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-preprocessor-macro_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: compiler_directives_preprocessor_macro_1 :description: Read preprocessing macro from template (:defines: marker) :tags: 5.6.4 :defines: VAR_1=2 VAR_2=5 */ module top(); int a = `VAR_1 + `VAR_2; initial begin if (a == 7) $display(":assert:(True)"); else $display(":assert:(False)"); end endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-resetall.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: resetall-directive :description: Check for the resetall directive :tags: 5.6.4 */ `resetall module ts(); endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-timescale.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: timescale-directive :description: Set timescale :tags: 5.6.4 */ `timescale 1 ns / 1 ps module ts(); endmodule ================================================ FILE: tests/chapter-5/5.6.4--compiler-directives-unconnected-drive.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unconnected-drive :description: Unconnected drive keywords :tags: 5.6.4 :type: preprocessing */ `unconnected_drive pull1 module ts(); endmodule `nounconnected_drive ================================================ FILE: tests/chapter-5/5.7.1--integers-left-padding-bit.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: integers-left-padding-bit :description: Automatic left padding of literal numbers using single-bit value :tags: 5.7.1 */ module top(); logic [15:0] a, b, c, d; initial begin a = '0; // sets all 16 bits to 0 b = '1; // sets all 16 bits to 1 c = 'x; // sets all 16 bits to x d = 'z; // sets all 16 bits to z end endmodule ================================================ FILE: tests/chapter-5/5.7.1--integers-left-padding.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: integers-left-padding :description: Automatic left padding of literal constant numbers :tags: 5.7.1 */ module top(); logic [11:0] a, b, c, d; logic [84:0] e, f, g; initial begin a = 'h x; // yields xxx b = 'h 3x; // yields 03x c = 'h z3; // yields zz3 d = 'h 0z3; // yields 0z3 e = 'h5; // yields {82{1'b0},3'b101} f = 'hx; // yields {85{1'hx}} g = 'hz; // yields {85{1'hz}} end endmodule ================================================ FILE: tests/chapter-5/5.7.1--integers-signed-illegal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: integers-sized-illegal :description: Integer literal constants :should_fail_because: illegal negative decimal syntax, proper one is -8'd6 :tags: 5.7.1 */ module top(); logic [7:0] a; initial begin a = 8'd-6; end endmodule ================================================ FILE: tests/chapter-5/5.7.1--integers-signed.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: integers-signed :description: Integer literal constants :tags: 5.7.1 */ module top(); logic [7:0] a; logic [3:0] b; logic [3:0] c; logic [15:0] d; initial begin a = -8'd 6; // this defines the two's-complement of 6, // held in 8 bits—equivalent to -(8'd 6) b = 4'shf; // this denotes the 4-bit number '1111', to // be interpreted as a two's-complement number, // or '-1'. This is equivalent to -4'h 1 c = -4'sd15; // this is equivalent to -(-4'd 1), or '0001' d = 16'sd?; // the same as 16'sbz end endmodule ================================================ FILE: tests/chapter-5/5.7.1--integers-sized.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: integers-sized :description: Integer literal constants :tags: 5.7.1 */ module top(); logic [3:0] a; logic [4:0] b; logic [ 2:0] c; logic [11:0] d; logic [15:0] e; initial begin a = 4'b1001; // is a 4-bit binary number b = 5'D3; // is a 5-bit decimal number c = 3'b01x; // is a 3-bit number with the least // significant bit unknown d = 12'hx; // is a 12-bit unknown number e = 16'hz; // is a 16-bit high-impedance number end endmodule ================================================ FILE: tests/chapter-5/5.7.1--integers-token.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: integers-token :description: Testing the integer variable type :tags: 5.7.1 */ module top(); integer a; endmodule ================================================ FILE: tests/chapter-5/5.7.1--integers-underscores.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: integers-underscores :description: Automatic left padding of literal numbers using single-bit value :tags: 5.7.1 */ module top(); logic [31:0] a; logic [15:0] b; logic [31:0] c; initial begin a = 27_195_000; // unsized decimal 27195000 b = 16'b0011_0101_0001_1111; // 16-bit binary number c = 32 'h 12ab_f001; // 32-bit hexadecimal number end endmodule ================================================ FILE: tests/chapter-5/5.7.1--integers-unsized-illegal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: integers-unsized-illegal :description: Integer literal constants :should_fail_because: hexadecimal format requires 'h :tags: 5.7.1 */ module top(); logic [31:0] a; initial begin a = 4af; // is illegal (hexadecimal format requires 'h) end endmodule ================================================ FILE: tests/chapter-5/5.7.1--integers-unsized.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: integers-unsized :description: Integer literal constantsa :tags: 5.7.1 */ module top(); logic [31:0] a; initial begin a = 659; // is a decimal number a = 'h 837FF; // is a hexadecimal number a = 'o7460; // is an octal number end endmodule ================================================ FILE: tests/chapter-5/5.7.2-real-constants-illegal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: real-constants-illegal :description: Examples of real literal constants :should_fail_because: Real literal constants must have at least one digit on each side of the decimal point :tags: 5.7.2 */ module top(); logic [31:0] a; initial begin a = .12; a = 9.; a = 4.E3; a = .2e-7; end endmodule ================================================ FILE: tests/chapter-5/5.7.2-real-constants.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: real-constants :description: Examples of real literal constants :tags: 5.7.2 */ module top(); logic [31:0] a; initial begin a = 1.2; a = 0.1; a = 2394.26331; a = 1.2E12; // the exponent symbol can be e or E a = 1.30e-2; a = 0.1e-0; a = 23E10; a = 29E-2; a = 236.123_763_e-12; // underscores are ignored end endmodule ================================================ FILE: tests/chapter-5/5.7.2-real-token.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: real-token :description: Testing the real variable type :tags: 5.7.2 :unsynthesizable: 1 */ module top(); real a; endmodule ================================================ FILE: tests/chapter-5/5.8-time-literals.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: time-literals :description: Examples of time literals :tags: 5.8 :unsynthesizable: 1 */ `timescale 100ps/10ps module top(); time a; initial begin a = 1fs; a = 1ps; a = 1ns; a = 1us; a = 1ms; a = 1s; /* real */ a = 2.1ms; end; endmodule ================================================ FILE: tests/chapter-5/5.9-string-assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string-assignment :description: String assignment tests :tags: 5.9 */ module top(); byte a; bit [7:0] b; logic [7:0] c; initial begin a = "a"; b = "b"; c = "c"; end endmodule ================================================ FILE: tests/chapter-5/5.9-string-basics.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string-basic :description: Basic string example :tags: 5.9 5.3 */ module top(); initial begin $display("one line"); end endmodule ================================================ FILE: tests/chapter-5/5.9-string-broken-line.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string-broken-line :description: Basic broken line string example :tags: 5.9 */ module top(); initial begin $display("broken \ line"); end endmodule ================================================ FILE: tests/chapter-5/5.9-string-word-assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string-word-assignment :description: String assignment tests :tags: 5.9 */ module top(); bit [8 * 3 - 1 : 0] a = "hi0"; // Note as of January 2020 several commercial simulators do not support unpacked byte // assignment from strings: byte b[3 : 0] = "hi2"; endmodule ================================================ FILE: tests/chapter-5/5.9.1-string-special-chars.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string-special-chars :description: Special characters in strings :tags: 5.9.1 */ module top(); initial begin $display("newline \n"); $display("tab \t"); $display("backslash \\"); $display("quote \""); $display("vertical tab \v"); $display("form feed \f"); $display("bell \a"); $display("octal \123"); $display("hex \x12"); end endmodule ================================================ FILE: tests/chapter-6/6.10--implicit_continuous_assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implicit_continuous_assignment :description: implicit declaration in continuous assignment tests :tags: 6.10 */ module top(); wire [3:0] a = 8; wire [3:0] b = 5; assign c = | (a | b); endmodule ================================================ FILE: tests/chapter-6/6.10--implicit_port.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implicit_port :description: implicit port signal tests :tags: 6.10 */ module top(input [3:0] a, input [3:0] b); wire [3:0] c; assign c = a | b; endmodule ================================================ FILE: tests/chapter-6/6.10--implicit_port_connection.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implicit_port_connection :description: implicit port connection tests :tags: 6.10 */ module top(); wire a = 1; wire b = 0; wire d; test mod(a, b, c); assign d = c; endmodule module test(input a, input b, output c); assign c = a | b; endmodule ================================================ FILE: tests/chapter-6/6.12--real.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: real :description: real type tests :tags: 6.12 :unsynthesizable: 1 */ module top(); real a = 0.5; endmodule ================================================ FILE: tests/chapter-6/6.12--real_bit_select.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: real_idx :description: real indexing tests :should_fail_because: it is illegal to do bit select on real data type :tags: 6.12 :type: simulation elaboration :unsynthesizable: 1 */ module top(); real a = 0.5; wire b; assign b = a[2]; endmodule ================================================ FILE: tests/chapter-6/6.12--real_bit_select_idx.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: real_bit_select :description: real bit select tests :should_fail_because: it is illegal to do bit select on real data type :tags: 6.12 :type: simulation elaboration :unsynthesizable: 1 */ module top(); real a = 0.5; wire [3:0] b; wire c; assign c = b[a]; endmodule ================================================ FILE: tests/chapter-6/6.12--real_edge.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: real_edge :description: real edge event tests :should_fail_because: it is illegal to use edge event controls on real type :tags: 6.12 :type: simulation elaboration :unsynthesizable: 1 */ module top(); real a = 0.5; always @(posedge a) $display("posedge"); endmodule ================================================ FILE: tests/chapter-6/6.12--realtime.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: realtime :description: realtime type tests :tags: 6.12 :unsynthesizable: 1 */ module top(); realtime a = 0.5; endmodule ================================================ FILE: tests/chapter-6/6.12--shortreal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: shortreal :description: shortreal type tests :tags: 6.12 :unsynthesizable: 1 */ module top(); shortreal a = 0.5; endmodule ================================================ FILE: tests/chapter-6/6.13--void.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: void :description: void type tests :tags: 6.13 :type: simulation elaboration parsing */ module top(); function void fun(); $display(":assert:(True)"); endfunction initial fun(); endmodule ================================================ FILE: tests/chapter-6/6.14--chandle.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: chandle :description: chandle type tests :tags: 6.14 :unsynthesizable: 1 */ module top(); chandle a; endmodule ================================================ FILE: tests/chapter-6/6.16--string.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string :description: string type tests :tags: 6.16 */ module top(); string a; endmodule ================================================ FILE: tests/chapter-6/6.16.1--string_len.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_len :description: string.len() tests :tags: 6.16.1 */ module top(); string a = "Test"; int b = a.len(); endmodule ================================================ FILE: tests/chapter-6/6.16.10--string_atoreal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_atoreal :description: string.atoreal() tests :tags: 6.16.10 :unsynthesizable: 1 */ module top(); string a = "4.76"; real b = a.atoreal(); endmodule ================================================ FILE: tests/chapter-6/6.16.11--string_itoa.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_itoa :description: string.itoa() tests :tags: 6.16.11 */ module top(); string a; initial a.itoa(12); endmodule ================================================ FILE: tests/chapter-6/6.16.12--string_hextoa.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_hextoa :description: string.hextoa() tests :tags: 6.16.12 */ module top(); string a; initial a.hextoa(12); endmodule ================================================ FILE: tests/chapter-6/6.16.13--string_octtoa.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_octtoa :description: string.octtoa() tests :tags: 6.16.13 */ module top(); string a; initial a.octtoa(12); endmodule ================================================ FILE: tests/chapter-6/6.16.14--string_bintoa.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_bintoa :description: string.bintoa() tests :tags: 6.16.14 */ module top(); string a; initial a.bintoa(12); endmodule ================================================ FILE: tests/chapter-6/6.16.15--string_realtoa.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_realtoa :description: string.realtoa() tests :tags: 6.16.15 */ module top(); string a; initial a.realtoa(4.76); endmodule ================================================ FILE: tests/chapter-6/6.16.2--string_putc.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_putc :description: string.putc() tests :tags: 6.16.2 */ module top(); string a = "Test"; initial a.putc(2, "B"); endmodule ================================================ FILE: tests/chapter-6/6.16.3--string_getc.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_getc :description: string.getc() tests :tags: 6.16.3 */ module top(); string a = "Test"; byte b = a.getc(2); endmodule ================================================ FILE: tests/chapter-6/6.16.4--string_toupper.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_toupper :description: string.toupper() tests :tags: 6.16.4 */ module top(); string a = "Test"; string b = a.toupper(); endmodule ================================================ FILE: tests/chapter-6/6.16.5--string_tolower.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_tolower :description: string.tolower() tests :tags: 6.16.5 */ module top(); string a = "Test"; string b = a.tolower(); endmodule ================================================ FILE: tests/chapter-6/6.16.6--string_compare.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_compare_fn :description: string.compare() tests :tags: 6.16.6 */ module top(); string a = "Test"; string b = "TEST"; int c = a.compare(b); endmodule ================================================ FILE: tests/chapter-6/6.16.7--string_icompare.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_icompare :description: string.icompare() tests :tags: 6.16.7 */ module top(); string a = "Test"; string b = "TEST"; int c = a.icompare(b); endmodule ================================================ FILE: tests/chapter-6/6.16.8--string_substr.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_substr :description: string.substr() tests :tags: 6.16.8 */ module top(); string a = "Test"; string b = a.substr(1, 2); endmodule ================================================ FILE: tests/chapter-6/6.16.9--string_atobin.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_atobin :description: string.atobin() tests :tags: 6.16.9 */ module top(); string a = "10101"; int b = a.atobin(); endmodule ================================================ FILE: tests/chapter-6/6.16.9--string_atohex.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_atohex :description: string.atohex() tests :tags: 6.16.9 */ module top(); string a = "0xff"; int b = a.atohex(); endmodule ================================================ FILE: tests/chapter-6/6.16.9--string_atoi.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_atoi :description: string.atoi() tests :tags: 6.16.9 */ module top(); string a = "1234"; int b = a.atoi(); endmodule ================================================ FILE: tests/chapter-6/6.16.9--string_atooct.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: string_atooct :description: string.atooct() tests :tags: 6.16.9 */ module top(); string a = "777"; int b = a.atooct(); endmodule ================================================ FILE: tests/chapter-6/6.17--event.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event :description: event type tests :tags: 6.17 :unsynthesizable: 1 */ module top(); event a; endmodule ================================================ FILE: tests/chapter-6/6.18--typedef.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef :description: user types tests :tags: 6.18 */ module top(); typedef logic logic_t; logic_t a; endmodule ================================================ FILE: tests/chapter-6/6.19--enum_anon.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_anon :description: anonymous enum tests :tags: 6.19 */ module top(); enum {a, b, c} val; endmodule ================================================ FILE: tests/chapter-6/6.19--enum_value_inv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_value_inv :description: Tests that tools diagnose invalid enum value assignments :should_fail_because: If the integer value expression is a sized literal constant, it shall be an error if the size is different from the enum base type, even if the value is within the representable range. :tags: 6.19 :runner_verilator_flags: -Werror-WIDTH :type: simulation elaboration */ module top(); // 6.19 says: // If the integer value expression is a sized literal constant, it shall // be an error if the size is different from the enum base type, even if // the value is within the representable range. enum logic [2:0] { Global = 4'h2, Local = 4'h3 } myenum; endmodule ================================================ FILE: tests/chapter-6/6.19--enum_xx.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_xx :description: enum with x tests :tags: 6.19 */ module top(); enum integer {a=0, b={32{1'bx}}, c=1} val; endmodule ================================================ FILE: tests/chapter-6/6.19--enum_xx_inv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_xx_inv :description: invalid enum with x tests :should_fail_because: An enumerated name with x or z assignments assigned to an enum with no explicit data type or an explicit2-state declaration shall be a syntax error :tags: 6.19 :type: simulation elaboration */ module top(); enum bit [1:0] {a=0, b=2'bxx, c=1} val; endmodule ================================================ FILE: tests/chapter-6/6.19--enum_xx_inv_order.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_xx_inv_order :description: unassigned name following enum with x tests :should_fail_because: An unassigned enumerated name that follows an enum name with x or z assignments shall be a syntax error. :tags: 6.19 :type: simulation elaboration */ module top(); enum integer {a=0, b={32{1'bx}}, c} val; endmodule ================================================ FILE: tests/chapter-6/6.19.1--enum_typedef.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_typedef :description: typedef enum tests :tags: 6.19.1 */ module top(); typedef enum {a, b, c} e; e val; endmodule ================================================ FILE: tests/chapter-6/6.19.2--enum_sequence.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_sequence :description: enum sequence tests :tags: 6.19.2 */ module top(); enum {start=10, step[10]} e; endmodule ================================================ FILE: tests/chapter-6/6.19.2--enum_sequence_range.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_sequence_range :description: enum sequence range tests :tags: 6.19.2 */ module top(); enum {start=10, stop[11:13]} e; endmodule ================================================ FILE: tests/chapter-6/6.19.3--enum_type_checking.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_type_checking :description: enum type checking tests :tags: 6.19.3 */ module top(); typedef enum {a, b, c, d} e; initial begin e val; val = a; end endmodule ================================================ FILE: tests/chapter-6/6.19.3--enum_type_checking_inv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_type_checking_inv :description: invalid enum assignment tests :should_fail_because: enum enforces strict type checking rules :tags: 6.19.3 :type: simulation elaboration */ module top(); typedef enum {a, b, c, d} e; initial begin e val; val = 1; end endmodule ================================================ FILE: tests/chapter-6/6.19.4--enum_numerical_expr.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_numerical_expr :description: enum numerical expression tests :tags: 6.19.4 */ module top(); typedef enum {a, b, c, d} e; initial begin integer i; e val; val = a; i = val * 4; end endmodule ================================================ FILE: tests/chapter-6/6.19.4--enum_numerical_expr_cast.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_numerical_expr_cast :description: enum numerical expression with casting :tags: 6.19.4 */ module top(); typedef enum {a, b, c, d} e; initial begin e val; val = a; val = e'(val+1); end endmodule ================================================ FILE: tests/chapter-6/6.19.4--enum_numerical_expr_no_cast.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_numerical_expr_no_cast :description: enum numerical expression without casting :should_fail_because: enum numerical expression without casting :tags: 6.19.4 :type: simulation elaboration */ module top(); typedef enum {a, b, c, d} e; initial begin e val; val = a; val += 1; end endmodule ================================================ FILE: tests/chapter-6/6.19.5.1--enum_first.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_first :description: enum first method tests :tags: 6.19.5.1 */ module top(); typedef enum {a, b, c, d} e; initial begin e val = a; val = val.first(); end endmodule ================================================ FILE: tests/chapter-6/6.19.5.2--enum_last.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_last :description: enum last method tests :tags: 6.19.5.2 */ module top(); typedef enum {a, b, c, d} e; initial begin e val = a; val = val.last(); end endmodule ================================================ FILE: tests/chapter-6/6.19.5.3--enum_next.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_next :description: enum next method tests :tags: 6.19.5.3 */ module top(); typedef enum {a, b, c, d} e; initial begin e val = a; val = val.next(); end endmodule ================================================ FILE: tests/chapter-6/6.19.5.4--enum_prev.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_prev :description: enum prev method tests :tags: 6.19.5.4 */ module top(); typedef enum {a, b, c, d} e; initial begin e val = b; val = val.prev(); end endmodule ================================================ FILE: tests/chapter-6/6.19.5.5--enum_num.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_num :description: enum num method tests :tags: 6.19.5.5 */ module top(); typedef enum {a, b, c, d} e; initial begin e val = a; int n = val.num(); end endmodule ================================================ FILE: tests/chapter-6/6.19.5.6--enum_name.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: enum_name :description: enum name method tests :tags: 6.19.5.6 */ module top(); typedef enum {a, b, c, d} e; initial begin e val = a; string s = val.name(); end endmodule ================================================ FILE: tests/chapter-6/6.20.2--parameter.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameter :description: parameter tests :tags: 6.20.2 */ module top(); parameter p = 123; endmodule ================================================ FILE: tests/chapter-6/6.20.2--parameter_aggregate.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameter_aggregate :description: parameter aggregate type tests :tags: 6.20.2 */ module top(); parameter logic [31:0] p [3:0] = '{1, 2, 3, 4}; endmodule ================================================ FILE: tests/chapter-6/6.20.2--parameter_dep.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameter_dep :description: parameter depending on another parameter tests :tags: 6.20.2 */ module top(); parameter p1 = 123; parameter p2 = p1 * 3; endmodule ================================================ FILE: tests/chapter-6/6.20.2--parameter_port_list.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameter_port_list :description: parameter port list tests :tags: 6.20.2 */ module top #(p = 12); endmodule ================================================ FILE: tests/chapter-6/6.20.2--parameter_range.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameter_range :description: parameter with implied range tests :tags: 6.20.2 */ module top(); parameter p = 16'h1234; endmodule ================================================ FILE: tests/chapter-6/6.20.2--parameter_real.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameter_real :description: parameter with real value test :tags: 6.20.2 */ module top(); parameter p = 4.76; endmodule ================================================ FILE: tests/chapter-6/6.20.3--parameter_type.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameter_type :description: parameter type tests :tags: 6.20.3 :unsynthesizable: 1 */ module top #(type T = real); endmodule ================================================ FILE: tests/chapter-6/6.20.4--localparam.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: localparam :description: localparam without type specifier :tags: 6.20.4 */ module top(); localparam p = 123; endmodule ================================================ FILE: tests/chapter-6/6.20.4--localparam_int.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: localparam_int :description: localparam integer type :tags: 6.20.4 */ module top(); localparam int p = 123; endmodule ================================================ FILE: tests/chapter-6/6.20.4--localparam_logic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: localparam_logic :description: localparam with logic type :tags: 6.20.4 */ module top(); localparam [10:0] p = 1 << 5; localparam logic [10:0] q = 1 << 5; endmodule ================================================ FILE: tests/chapter-6/6.20.4--localparam_string.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: localparam_string :description: localparam string typed :tags: 6.20.4 */ module top(); localparam s1 = "foo"; localparam string s2 = "bar"; endmodule ================================================ FILE: tests/chapter-6/6.20.4--localparam_unsigned_int.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: localparam_uint :description: localparam unsigned typed :tags: 6.20.4 */ module top(); localparam int unsigned q = 123; endmodule ================================================ FILE: tests/chapter-6/6.20.5--specparam.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: specparam :description: specparam tests :tags: 6.20.5 */ module top(); specparam delay = 50; endmodule ================================================ FILE: tests/chapter-6/6.20.5--specparam_inv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: specparam_inv :description: specparam assignment to param should be invalid :should_fail_because: specparam assignment to param should be invalid :tags: 6.20.5 :type: simulation elaboration */ module top(); specparam delay = 50; parameter p = delay + 2; endmodule ================================================ FILE: tests/chapter-6/6.20.6--const.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: const :description: const test :tags: 6.20.6 :unsynthesizable: 1 */ module top(); class test_cls; int a; task test_method(int val); $display("test_method"); a += val; endtask endclass const test_cls test_obj = new; endmodule ================================================ FILE: tests/chapter-6/6.23--localparam_type_decl.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: localparam_type_decl :description: Declare a type with a localparam :tags: 6.23 */ module top ; localparam type testtype = logic; testtype t; endmodule ================================================ FILE: tests/chapter-6/6.23--type_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: type_op :description: type operator tests :tags: 6.23 :unsynthesizable: 1 */ module top(); real a = 4.76; real b = 0.74; var type(a+b) c; endmodule ================================================ FILE: tests/chapter-6/6.23--type_op_compare.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: type_op_compare :description: type comparison tests :tags: 6.23 */ module top #( parameter type T = type(logic[11:0]) ) (); initial begin case (type(T)) type(logic[11:0]) : ; default : $stop; endcase if (type(T) == type(logic[12:0])) $stop; if (type(T) != type(logic[11:0])) $stop; if (type(T) === type(logic[12:0])) $stop; if (type(T) !== type(logic[11:0])) $stop; $finish; end endmodule ================================================ FILE: tests/chapter-6/6.24.1--cast_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cast_op :description: cast operator :tags: 6.24.1 */ module top(); int a = int'(2.1 * 3.7); endmodule ================================================ FILE: tests/chapter-6/6.24.2--cast_fn.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cast_fn :description: $cast function :tags: 6.24.2 */ module top(); int a; initial if (! $cast(a, 2.1 * 3.7)) $display("cast failed"); endmodule ================================================ FILE: tests/chapter-6/6.24.2--cast_task.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cast_task :description: $cast task :tags: 6.24.2 8.16 */ module top(); int a; initial $cast(a, 2.1 * 3.7); endmodule ================================================ FILE: tests/chapter-6/6.24.3--bitstream_cast.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: bitstream_cast :description: bitstream cast function :tags: 6.24.3 */ module top(); struct packed {logic [7:0] a; logic [7:0] b; logic [15:0] c;} s; integer a = integer'(s); endmodule ================================================ FILE: tests/chapter-6/6.5--variable_assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: variable_assignment :description: Variable assignment tests :tags: 6.5 */ module top(); int v; assign v = 12; endmodule ================================================ FILE: tests/chapter-6/6.5--variable_mixed_assignments.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: variable_mixed_assignments :description: Variable mixed assignments tests :should_fail_because: mixing procedural and continuous assignments is illegal :tags: 6.5 :type: simulation elaboration */ module top(); wire clk = 0; int v; assign v = 12; always @(posedge clk) v <= ~v; endmodule ================================================ FILE: tests/chapter-6/6.5--variable_multiple_assignments.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: variable_multiple_assignments :description: Variable multiple assignments tests :should_fail_because: it shall be an error to have multiple continuous assignments :tags: 6.5 :type: simulation elaboration */ module top(); int v; assign v = 12; assign v = 13; endmodule ================================================ FILE: tests/chapter-6/6.5--variable_redeclare.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: variable_redeclare :description: Variable redeclaration tests :should_fail_because: Variable redeclaration :tags: 6.5 :type: simulation elaboration */ module top(); reg v; wire v; endmodule ================================================ FILE: tests/chapter-6/6.6.7--nettype.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: nettype :description: user-defined nettype tests :tags: 6.6.7 */ module top(); nettype real real_net; endmodule ================================================ FILE: tests/chapter-6/6.6.7--nettype_resolution_fn.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: nettype_resolution_fn :description: user-defined nettype with resolution function tests :tags: 6.6.7 :unsynthesizable: 1 */ module top(); function automatic real real_sum (input real driver[]); real_sum = 0.0; foreach (driver[i]) real_sum += driver[i]; endfunction nettype real real_net with real_sum; endmodule ================================================ FILE: tests/chapter-6/6.6.8--interconnect.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: interconnect :description: generic interconnect tests :tags: 6.6.8 */ module top(); interconnect bus; mod_i m1(bus); mod_o m2(bus); endmodule module mod_i(input in); endmodule module mod_o(output out); endmodule ================================================ FILE: tests/chapter-6/6.9.1--logic_vector.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: logic_vector :description: logic vector tests :tags: 6.9.1 */ module top(); logic [15:0] a; endmodule ================================================ FILE: tests/chapter-6/6.9.2--vector_scalared.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: vector_scalared :description: scalared vector tests :tags: 6.9.2 */ module top(); tri1 scalared [15:0] a = 0; endmodule ================================================ FILE: tests/chapter-6/6.9.2--vector_vectored.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: vector_vectored :description: vectored vector tests :tags: 6.9.2 */ module top(); tri1 vectored [15:0] a; endmodule ================================================ FILE: tests/chapter-6/6.9.2--vector_vectored_inv.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: vector_vectored_inv :description: vectored vector invalid access tests :should_fail_because: bit selects are not permitted on vectored vector nets :tags: 6.9.2 */ module top(); logic vectored [15:0] a = 0; assign a[1] = 1; endmodule ================================================ FILE: tests/chapter-7/arrays/associative/alloc.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-allocating-elements :description: Test associative arrays elements allocation :tags: 7.8.7 7.8 7.9.1 :type: simulation elaboration parsing */ module top (); int arr [ int ]; initial begin $display(":assert: (%d == 0)", arr.size); arr[10] = 10; $display(":assert: (%d == 1)", arr.size); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/arguments.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-as-arguments :description: Test passing associative array as arugments support :tags: 7.9.10 7.8 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); string arraya[int]; task fun (string arrayb[int]); arrayb[ 1 ] = "d"; $display(":assert: (('%s' == 'a') and ('%s' == 'd') and ('%s' == 'c'))", arrayb[0], arrayb[1], arrayb[2]); endtask initial begin arraya[ 0 ] = "a"; arraya[ 1 ] = "b"; arraya[ 2 ] = "c"; $display(":assert: (('%s' == 'a') and ('%s' == 'b') and ('%s' == 'c'))", arraya[0], arraya[1], arraya[2]); fun(arraya); $display(":assert: (('%s' == 'a') and ('%s' == 'b') and ('%s' == 'c'))", arraya[0], arraya[1], arraya[2]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-assignment :description: Test associative arrays assignment support :tags: 7.9.9 7.8 :type: simulation elaboration parsing */ module top (); string words [ int ]; string w [ int ]; initial begin words[0] = "hello"; words[1] = "happy"; words[2] = "world"; $display(":assert: (('%s' == 'hello') and ('%s' == 'happy') and ('%s' == 'world'))", words[0], words[1], words[2]); w = words; w[1] = "sad"; $display(":assert: (('%s' == 'hello') and ('%s' == 'happy') and ('%s' == 'world'))", words[0], words[1], words[2]); $display(":assert: (('%s' == 'hello') and ('%s' == 'sad') and ('%s' == 'world'))", w[0], w[1], w[2]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/class.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-class :description: Test associative arrays support :tags: 7.8.3 7.8 */ module top (); class C; int x; endclass int arr [ C ]; endmodule ================================================ FILE: tests/chapter-7/arrays/associative/integral.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-integral :description: Test associative arrays support :tags: 7.8.4 7.8 */ module top (); int arr [ integer ]; endmodule ================================================ FILE: tests/chapter-7/arrays/associative/literals.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-literals :description: Test associative arrays literals support :tags: 7.9.11 7.8 :type: simulation elaboration parsing */ module top (); string words [int] = '{default: "hello"}; initial begin $display(":assert: ('%s' == 'hello')", words[1]); words[1] = "world"; $display(":assert: (('%s' == 'hello') and ('%s' == 'world'))", words[0], words[1]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-find-first-index :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); string s[] = { "hello", "sad", "hello", "world" }; int qi[$]; initial begin qi = s.find_first_index with ( item == "hello" ); $display(":assert: (%d == 1)", qi.size); $display(":assert: (%d == 0)", qi[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/find-first.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-find-first :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); string s[] = { "hello", "sad", "hello", "world" }; string qs[$]; initial begin qs = s.find_first with ( item == "hello" ); $display(":assert: (%d == 1)", qs.size); $display(":assert: ('%s' == 'hello')", qs[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/find-index.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-find-index :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); string s[] = { "hello", "sad", "world" }; int qi[$]; initial begin qi = s.find_index with ( item == "world" ); $display(":assert: (%d == 1)", qi.size); $display(":assert: (%d == 2)", qi[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-find-last-index :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); string s[] = { "hello", "sad", "hello", "world" }; int qi[$]; initial begin qi = s.find_last_index with ( item == "hello" ); $display(":assert: (%d == 1)", qi.size); $display(":assert: (%d == 2)", qi[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/find-last.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-find-last :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); string s[] = { "hello", "sad", "hello", "world" }; string qs[$]; initial begin qs = s.find_last with ( item == "hello" ); $display(":assert: (%d == 1)", qs.size); $display(":assert: ('%s' == 'hello')", qs[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/find.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-find :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); string s[] = { "hello", "sad", "world" }; string qs[$]; initial begin qs = s.find with ( item == "sad" ); $display(":assert: (%d == 1)", qs.size); $display(":assert: ('%s' == 'sad')", qs[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/max.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-max :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int s[] = { 10, 20, 2, 11, 5 }; int qi[$]; initial begin qi = s.max; $display(":assert: (%d == 1)", qi.size); $display(":assert: (%d == 20)", qi[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/min.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-min :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int s[] = { 10, 20, 2, 11, 5 }; int qi[$]; initial begin qi = s.min; $display(":assert: (%d == 1)", qi.size); $display(":assert: (%d == 2)", qi[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/unique-index.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-unique-index :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 7.12.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int s[] = { 10, 10, 3, 20, 20, 10 }; int qi[$]; initial begin qi = s.unique_index; $display(":assert: (%d == 3)", qi.size); qi.sort; $display(":assert: ((%d == 0) and (%d == 2) and (%d == 3))", qi[0], qi[1], qi[2]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/locator-methods/unique.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-locator-methods-unique :description: Test support of array locator methods :tags: 7.12.1 7.12 7.10 7.12.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int s[] = { 10, 10, 3, 20, 20, 10 }; int qi[$]; initial begin qi = s.unique; $display(":assert: (%d == 3)", qi.size); qi.sort; $display(":assert: ((%d == 3) and (%d == 10) and (%d == 20))", qi[0], qi[1], qi[2]); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/methods/delete.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-delete :description: Test support of associative arrays methods (delete) :tags: 7.9.2 7.9 :type: simulation elaboration parsing */ module top (); int map [ string ]; initial begin map[ "hello" ] = 1; map[ "sad" ] = 2; map[ "world" ] = 3; $display(":assert: (%d == 3)", map.size); map.delete( "sad" ); $display(":assert: (%d == 2)", map.size); map.delete; $display(":assert: (%d == 0)", map.size); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/methods/exists.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-exists :description: Test support of associative arrays methods (exists) :tags: 7.9.3 7.9 :type: simulation elaboration parsing */ module top (); int map [ string ]; initial begin map[ "hello" ] = 1; map[ "sad" ] = 2; map[ "world" ] = 3; $display(":assert: (%d == 1)", map.exists( "sad" )); $display(":assert: (%d == 0)", map.exists( "happy" )); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/methods/first.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-first :description: Test support of associative arrays methods (first) :tags: 7.9.4 7.9 :type: simulation elaboration parsing */ module top (); int map [ string ]; string s; int rc; initial begin // empty, should return zero rc = map.first( s ); $display(":assert: (%d == 0)", rc); map[ "hello" ] = 1; map[ "sad" ] = 2; map[ "world" ] = 3; rc = map.first( s ); $display(":assert: ((%d == 1) and ('%s' == 'hello'))", rc, s); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/methods/last.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-last :description: Test support of associative arrays methods (last) :tags: 7.9.5 7.9 :type: simulation elaboration parsing */ module top (); int map [ string ]; string s; int rc; initial begin // empty, should return zero rc = map.last( s ); $display(":assert: (%d == 0)", rc); map[ "hello" ] = 1; map[ "sad" ] = 2; map[ "world" ] = 3; rc = map.last( s ); $display(":assert: ((%d == 1) and ('%s' == 'world'))", rc, s); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/methods/next.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-next :description: Test support of associative arrays methods (next) :tags: 7.9.6 7.9 :type: simulation elaboration parsing */ module top (); int map [ string ]; string s; int rc; initial begin map[ "hello" ] = 1; map[ "sad" ] = 2; map[ "world" ] = 3; rc = map.first( s ); $display(":assert: ((%d == 1) and ('%s' == 'hello'))", rc, s); rc = map.next( s ); $display(":assert: ((%d == 1) and ('%s' == 'sad'))", rc, s); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/methods/num.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-num :description: Test support of associative arrays methods (num) :tags: 7.9.1 7.9 :type: simulation elaboration parsing */ module top (); int arr [ int ]; initial begin $display(":assert: (%d == 0)", arr.num); arr[ 3 ] = 1; $display(":assert: (%d == 1)", arr.num); arr[ 16'hffff ] = 2; $display(":assert: (%d == 2)", arr.num); arr[ 4'b1000 ] = 3; $display(":assert: (%d == 3)", arr.num); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/methods/prev.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-prev :description: Test support of associative arrays methods (prev) :tags: 7.9.7 7.9 :type: simulation elaboration parsing */ module top (); int map [ string ]; string s; int rc; initial begin map[ "hello" ] = 1; map[ "sad" ] = 2; map[ "world" ] = 3; rc = map.last( s ); $display(":assert: ((%d == 1) and ('%s' == 'world'))", rc, s); rc = map.prev( s ); $display(":assert: ((%d == 1) and ('%s' == 'sad'))", rc, s); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/methods/size.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-size :description: Test support of associative arrays methods (size) :tags: 7.9.1 7.9 :type: simulation elaboration parsing */ module top (); int arr [ int ]; initial begin $display(":assert: (%d == 0)", arr.size); arr[ 3 ] = 1; $display(":assert: (%d == 1)", arr.size); arr[ 16'hffff ] = 2; $display(":assert: (%d == 2)", arr.size); arr[ 4'b1000 ] = 3; $display(":assert: (%d == 3)", arr.size); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/methods/traversal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-arg-traversal :description: Test support of associative arrays methods :tags: 7.9.8 7.9 :type: simulation elaboration parsing */ module top (); string map[ byte ]; byte ix; int rc; initial begin map[ 1000 ] = "a"; rc = map.first( ix ); $display(":assert: ( ('%0d' == '1') and ('%b' == '11101000') )", rc, ix); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/nonexistent.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-access-nonexistent :description: Test access to nonexistent associative array element :tags: 7.8.6 7.9.1 :type: simulation elaboration parsing */ module top (); int arr [ int ]; int r; initial begin arr[10] = 10; $display(":assert: (%d == 1)", arr.size); // access nonexistent element $display(":re: BEGIN:ARRAY_NONEXISTENT"); r = arr[9]; $display(":re: END"); end endmodule ================================================ FILE: tests/chapter-7/arrays/associative/other.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-other-types :description: Test associative arrays support :tags: 7.8.1 :unsynthesizable: 1 */ module top (); typedef struct { byte B; int I[*]; } Unpkt; int arr [ Unpkt ]; endmodule ================================================ FILE: tests/chapter-7/arrays/associative/string.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-string :description: Test associative arrays support :tags: 7.8.2 7.8 */ module top (); int arr [ string ]; endmodule ================================================ FILE: tests/chapter-7/arrays/associative/wildcard.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: associative-arrays-wildcard :description: Test associative arrays support :tags: 7.8.1 :unsynthesizable: 1 */ module top (); int arr [*]; endmodule ================================================ FILE: tests/chapter-7/arrays/dynamic/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dyn-arr-basic :description: Test dynamic arrays support :tags: 7.5 */ module top (); bit [7:0] arr[]; endmodule ================================================ FILE: tests/chapter-7/arrays/dynamic/op-delete.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dynamic-arrays-op-delete :description: Test dynamic arrays operator delete support :tags: 7.5.3 :type: simulation elaboration parsing */ module top (); bit [7:0] arr[]; initial begin arr = new [ 16 ]; $display(":assert: (%d == 16)", arr.size); arr.delete; $display(":assert: (%d == 0)", arr.size); end endmodule ================================================ FILE: tests/chapter-7/arrays/dynamic/op-new.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dynamic-arrays-op-new :description: Test dynamic arrays operator new support :tags: 7.5.1 :type: simulation elaboration parsing */ module top (); bit [7:0] arr[]; initial begin arr = new [ 4 ]; arr[ 0 ] = 5; arr[ 1 ] = 6; arr[ 2 ] = 7; arr[ 3 ] = 8; $display(":assert: ((%d == 5) and (%d == 6) and (%d == 7) and (%d == 8))", arr[ 0 ], arr[ 1 ], arr[ 2 ], arr[ 3 ]); end endmodule ================================================ FILE: tests/chapter-7/arrays/dynamic/op-size.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dynamic-arrays-op-size :description: Test dynamic arrays operator size support :tags: 7.5.2 :type: simulation elaboration parsing */ module top (); bit [7:0] arr[]; initial begin arr = new [ 16 ]; $display(":assert: (%d == 16)", arr.size); arr = new [ 8 ]; $display(":assert: (%d == 8)", arr.size); end endmodule ================================================ FILE: tests/chapter-7/arrays/multidimensional/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: multi-dim-basic :description: Test multidimensional arrays :tags: 7.4.5 */ module top (); // 10 elements of 4 8-bit bytes // (each element packed into 32 bits) bit [3:0] [7:0] arr [1:10]; // compatible with memory array bit [7:0] mem [0:255]; // Varies most rapidly: // 1 to 6 // 1 to 5 // 1 to 8 // 1 to 7 // 2 1 4 3 bit [1:5] [1:6] arr2 [1:7] [1:8]; endmodule ================================================ FILE: tests/chapter-7/arrays/multidimensional/copy.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: copy :description: Test multidimensional word copy :tags: 7.4.5 :type: simulation elaboration parsing */ module top (); bit [3:0] [7:0] arr_a [1:10]; bit [3:0] [7:0] arr_b [1:10]; initial begin arr_a[1] = 32'hdeadbeef; $display(":assert: ('%h' == 'deadbeef')", arr_a[1]); arr_b[2] = arr_a[1]; $display(":assert: ('%h' == 'deadbeef')", arr_b[2]); end endmodule ================================================ FILE: tests/chapter-7/arrays/multidimensional/multi.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: multi-declaration :description: Test multidimensional arrays :tags: 7.4.5 */ module top (); // Same packed dimensions bit [7:0] [31:0] arr_a [1:5] [1:10], arr_b [0:255]; endmodule ================================================ FILE: tests/chapter-7/arrays/multidimensional/subarrays.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: subarrays :description: Test multidimensional subarrays assignments :tags: 7.4.5 :type: simulation elaboration parsing */ module top (); int A[2][3][4], B[2][3][4]; initial begin A[0][2][0] = 5; A[0][2][1] = 6; A[0][2][2] = 7; A[0][2][3] = 8; B[1][1] = A[0][2]; $display(":assert: ((%d == 5) and (%d == 6) and (%d == 7) and (%d == 8))", B[1][1][0], B[1][1][1], B[1][1][2], B[1][1][3]); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: basic-packed :description: Test packed arrays support :tags: 7.4.1 7.4 */ module top (); bit [7:0] _bit; logic [7:0] _logic; reg [7:0] _reg; endmodule ================================================ FILE: tests/chapter-7/arrays/packed/equality.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-packed-arrays-equality :description: Test packed arrays operations support (equality) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit [7:0] arr_a; bit [7:0] arr_b; initial begin arr_a = 8'hff; arr_b = 8'hff; $display(":assert: (('%h' == 'ff') and ('%h' == 'ff'))", arr_a, arr_b); $display(":assert: (%d == 1)", (arr_a == arr_b)); $display(":assert: (%d == 0)", (arr_a != arr_b)); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/onebit.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-packed-arrays-one-bit :description: Test packed arrays operations support (one bit) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit [7:0] arr_a; bit [7:0] arr_b; initial begin arr_a = 8'hff; arr_b = 8'h00; $display(":assert: (('%h' == 'ff') and ('%h' == '00'))", arr_a, arr_b); arr_b[5] = arr_a[2]; $display(":assert: ('%b' == '00100000')", arr_b); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/operations.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-packed-arrays-rw :description: Test packed arrays operations support (R & W) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit [7:0] arr; initial begin arr = 8'h00; $display(":assert: ('%h' == '00')", arr); arr = 8'hde; $display(":assert: ('%h' == 'de')", arr); arr = 8'had; $display(":assert: ('%h' == 'ad')", arr); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/querying-functions/dimensions.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-packed-quering-functions-dimensions :description: Test quering functions support on packed arrays :tags: 7.11 7.4.1 :type: simulation elaboration parsing */ module top (); bit [7:0] arr; initial begin $display(":assert: (%d == 1)", $dimensions(arr)); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/querying-functions/high.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-packed-quering-functions-high :description: Test quering functions support on packed arrays :tags: 7.11 7.4.1 :type: simulation elaboration parsing */ module top (); bit [7:0] arr; initial begin $display(":assert: (%d == 7)", $high(arr)); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/querying-functions/increment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-packed-quering-functions-increment :description: Test quering functions support on packed arrays :tags: 7.11 7.4.1 :type: simulation elaboration parsing */ module top (); bit [7:0] arr; initial begin $display(":assert: (%d == 1)", $increment(arr)); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/querying-functions/left.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-packed-quering-functions-left :description: Test quering functions support on packed arrays :tags: 7.11 7.4.1 :type: simulation elaboration parsing */ module top (); bit [7:0] arr; initial begin $display(":assert: (%d == 7)", $left(arr)); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/querying-functions/low.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-packed-quering-functions-low :description: Test quering functions support on packed arrays :tags: 7.11 7.4.1 :type: simulation elaboration parsing */ module top (); bit [7:0] arr; initial begin $display(":assert: (%d == 0)", $low(arr)); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/querying-functions/right.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-packed-quering-functions-right :description: Test quering functions support on packed arrays :tags: 7.11 7.4.1 :type: simulation elaboration parsing */ module top (); bit [7:0] arr; initial begin $display(":assert: (%d == 0)", $right(arr)); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/querying-functions/size.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-packed-quering-functions-size :description: Test quering functions support on packed arrays :tags: 7.11 7.4.1 :type: simulation elaboration parsing */ module top (); bit [7:0] arr; initial begin $display(":assert: (%d == 8)", $size(arr)); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: arrays-packed-quering-functions-unpacked-dimensions :description: Test quering functions support on packed arrays :tags: 7.11 7.4.1 :type: simulation elaboration parsing */ module top (); bit [7:0] arr; initial begin $display(":assert: (%d == 0)", $unpacked_dimensions(arr)); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/slice-equality.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-packed-arrays-slice-equality :description: Test packed arrays operations support (slice equality) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit [7:0] arr_a; bit [7:0] arr_b; initial begin arr_a = 8'hf0; arr_b = 8'h0f; $display(":assert: (('%h' == 'f0') and ('%h' == '0f'))", arr_a, arr_b); $display(":assert: (%d == 1)", (arr_a[7:4] == arr_b[3:0])); $display(":assert: (%d == 0)", (arr_a[7:4] != arr_b[3:0])); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/slice.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-packed-arrays-slice-rw :description: Test packed arrays operations support (R&W slice) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit [7:0] arr_a; bit [7:0] arr_b; initial begin arr_a = 8'hff; arr_b = 8'h00; $display(":assert: (('%h' == 'ff') and ('%h' == '00'))", arr_a, arr_b); arr_b[5:3] = arr_a[2:0]; $display(":assert: ('%b' == '00111000')", arr_b); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/treat-as-integer.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-arrays-treat-as-integer :description: Test packed arrays operations support (treat array as integer) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit [7:0] arr_a; bit [7:0] arr_b; initial begin arr_a = 8'd17; arr_b = (arr_a + 29); $display(":assert: (%d == 46)", arr_b); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/variable-slice-zero.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-arrays-variable-slice-zero-rw :description: Test packed arrays operations support (Variable slice) :should_fail_because: slicing array with zero part width :tags: 7.4.3 :type: simulation elaboration */ module top (); bit [7:0] arr_a; bit [7:0] arr_b; // TODO: Not sure if that should fail. // TODO: Icarus fails with: // TODO: "error: Indexed part widths must be constant and greater than zero." // TODO: Info in queue section: "Unlike arrays, the empty queue, {}, is a valid queue" // // Found: // The term slice refers to a selection of one or more contiguous elements of an array // so it should fail parameter integer c = 0; initial begin arr_a = 8'hff; arr_b = 8'h00; $display(":assert: (('%h' == 'ff') and ('%h' == '00'))", arr_a, arr_b); arr_b[4+:c] = arr_a[1+:c]; $display(":assert: ('%b' == '00000000')", arr_b); end endmodule ================================================ FILE: tests/chapter-7/arrays/packed/variable-slice.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-packed-arrays-variable-slice-rw :description: Test packed arrays operations support (Variable slice) :tags: 7.4.3 7.4.6 :type: simulation elaboration parsing */ module top (); bit [7:0] arr_a; bit [7:0] arr_b; parameter integer c = 3; initial begin arr_a = 8'hff; arr_b = 8'h00; $display(":assert: (('%h' == 'ff') and ('%h' == '00'))", arr_a, arr_b); arr_b[4+:c] = arr_a[1+:c]; $display(":assert: ('%b' == '01110000')", arr_b); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/assignments.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: array-unpacked-assignments :description: Test unpacked arrays assignments :tags: 7.6 7.4.2 :type: simulation elaboration parsing */ module top (); int A [3:0]; int B [0:3]; initial begin A[0] = 0; A[1] = 1; A[2] = 2; A[3] = 3; B = A; $display(":assert: ((%d == 0) and (%d == 1) and (%d == 2) and (%d == 3))", B[3], B[2], B[1], B[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: basic-unpacked :description: Test unpacked arrays support :tags: 7.4.2 7.4 */ module top (); bit _bit [7:0]; logic _logic [7:0]; reg _reg [7:0]; endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/equality.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-unpacked-arrays-equality :description: Test unpacked arrays operations support (equality) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit arr_a [7:0]; bit arr_b [7:0]; initial begin arr_a = '{1, 1, 1, 0, 0, 1, 1, 1}; arr_b = '{1, 1, 1, 0, 0, 1, 1, 1}; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '1110_0111')", arr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]); $display(":assert: ('%b%b%b%b_%b%b%b%b' == '1110_0111')", arr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]); $display(":assert: (%d == 1)", (arr_a == arr_b)); $display(":assert: (%d == 0)", (arr_a != arr_b)); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/index.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpacked-array-iterator-index-querying :description: Test support of unpacked arrays index querying method :tags: 7.12.4 7.4.2 7.10 7.12.1 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int arr[] = { 0, 1, 3, 3 }; int q[$]; initial begin q = arr.find with ( item == item.index ); $display(":assert: ((%d == 3) and (%d == 0) and (%d == 1) and (%d == 3))", q.size, q[0], q[1], q[2]); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/onebit.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-unpacked-arrays-one-bit :description: Test unpacked arrays operations support (one bit) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit arr_a [7:0]; bit arr_b [7:0]; initial begin arr_a = '{1, 1, 1, 1, 1, 1, 1, 1}; arr_b = '{0, 0, 0, 0, 0, 0, 0, 0}; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '1111_1111')", arr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]); $display(":assert: ('%b%b%b%b_%b%b%b%b' == '0000_0000')", arr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]); arr_b[5] = arr_a[2]; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '0010_0000')", arr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/operations.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-unpacked-arrays-rw :description: Test unpacked arrays operations support (R & W) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit arr [7:0]; initial begin arr = '{0, 0, 0, 0, 0, 0, 0, 0}; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '0000_0000')", arr[7], arr[6], arr[5], arr[4], arr[3], arr[2], arr[1], arr[0]); arr = '{1, 1, 0, 1, 1, 1, 1, 0 }; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '1101_1110')", arr[7], arr[6], arr[5], arr[4], arr[3], arr[2], arr[1], arr[0]); arr = '{1, 0, 1, 0, 1, 1, 0, 1 }; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '1010_1101')", arr[7], arr[6], arr[5], arr[4], arr[3], arr[2], arr[1], arr[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: ordering-methods-reverse :description: Test support of reverse method on unpacked arrays :tags: 7.12.2 7.4.2 :type: simulation elaboration parsing */ module top (); string s[] = { "hello", "sad", "world" }; initial begin $display(":assert: (('%s' == 'hello') and ('%s' == 'sad') and ('%s' == 'world'))", s[0], s[1], s[2]); s.reverse; $display(":assert: (('%s' == 'world') and ('%s' == 'sad') and ('%s' == 'hello'))", s[0], s[1], s[2]); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: ordering-methods-rsort :description: Test support of rsort method on unpacked arrays :tags: 7.12.2 7.4.2 :type: simulation elaboration parsing */ module top (); int ia[] = { 4, 5, 3, 1 }; initial begin $display(":assert: ((%d == 4) and (%d == 5) and (%d == 3) and (%d == 1))", ia[0], ia[1], ia[2], ia[3]); ia.rsort; $display(":assert: ((%d == 5) and (%d == 4) and (%d == 3) and (%d == 1))", ia[0], ia[1], ia[2], ia[3]); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: ordering-methods-shuffle :description: Test support of shuffle method on unpacked arrays :tags: 7.12.2 7.4.2 :type: simulation elaboration parsing */ module top (); int ia[] = { 1, 2, 3, 4, 5 }; initial begin $display(":info: { %d, %d, %d, %d, %d }", ia[0], ia[1], ia[2], ia[3], ia[4]); ia.shuffle; $display(":info: { %d, %d, %d, %d, %d }", ia[0], ia[1], ia[2], ia[3], ia[4]); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: ordering-methods-sort :description: Test support of sort method on unpacked arrays :tags: 7.12.2 7.4.2 :type: simulation elaboration parsing */ module top (); int ia[] = { 4, 5, 3, 1 }; initial begin $display(":assert: ((%d == 4) and (%d == 5) and (%d == 3) and (%d == 1))", ia[0], ia[1], ia[2], ia[3]); ia.sort; $display(":assert: ((%d == 1) and (%d == 3) and (%d == 4) and (%d == 5))", ia[0], ia[1], ia[2], ia[3]); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/reduction-methods/and.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpacked-array-reduction-method-and :description: Test support of unpacked arrays reduction method and :tags: 7.12.3 7.4.2 :type: simulation elaboration parsing */ module top (); byte b[] = { 1, 3, 5, 7 }; int y; initial begin $display(":assert: ((%d == 1) and (%d == 3) and (%d == 5) and (%d == 7))", b[0], b[1], b[2], b[3]); y = b.and; $display(":assert: (%d == 1)", y); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/reduction-methods/or.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpacked-array-reduction-method-or :description: Test support of unpacked arrays reduction method or :tags: 7.12.3 7.4.2 :type: simulation elaboration parsing */ module top (); byte b[] = { 1, 2, 3, 4 }; int y; initial begin $display(":assert: ((%d == 1) and (%d == 2) and (%d == 3) and (%d == 4))", b[0], b[1], b[2], b[3]); y = b.or; $display(":assert: (%d == 7)", y); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/reduction-methods/product.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpacked-array-reduction-method-product :description: Test support of unpacked arrays reduction method product :tags: 7.12.3 7.4.2 :type: simulation elaboration parsing */ module top (); byte b[] = { 1, 2, 3, 4 }; int y; initial begin $display(":assert: ((%d == 1) and (%d == 2) and (%d == 3) and (%d == 4))", b[0], b[1], b[2], b[3]); y = b.product; $display(":assert: (%d == 24)", y); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpacked-array-reduction-method-sum :description: Test support of unpacked arrays reduction method sum :tags: 7.12.3 7.4.2 :type: simulation elaboration parsing */ module top (); byte b[] = { 1, 2, 3, 4 }; int y; initial begin $display(":assert: ((%d == 1) and (%d == 2) and (%d == 3) and (%d == 4))", b[0], b[1], b[2], b[3]); y = b.sum; $display(":assert: (%d == 10)", y); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpacked-array-reduction-method-xor :description: Test support of unpacked arrays reduction method xor :tags: 7.12.3 7.4.2 :type: simulation elaboration parsing */ module top (); byte b[] = { 1, 2, 3, 4 }; int y; initial begin $display(":assert: ((%d == 1) and (%d == 2) and (%d == 3) and (%d == 4))", b[0], b[1], b[2], b[3]); y = b.xor; $display(":assert: (%d == 4)", y); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/slice-equality.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-unpacked-arrays-slice-equality :description: Test unpacked arrays operations support (slice equality) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit arr_a [7:0]; bit arr_b [7:0]; initial begin arr_a = '{1, 1, 1, 1, 0, 0, 0, 0}; arr_b = '{0, 0, 0, 0, 1, 1, 1, 1}; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '1111_0000')", arr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]); $display(":assert: ('%b%b%b%b_%b%b%b%b' == '0000_1111')", arr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]); $display(":assert: (%d == 1)", (arr_a[7:4] == arr_b[3:0])); $display(":assert: (%d == 0)", (arr_a[7:4] != arr_b[3:0])); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/slice.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-unpacked-arrays-slice-rw :description: Test unpacked arrays operations support (R&W slice) :tags: 7.4.3 :type: simulation elaboration parsing */ module top (); bit arr_a [7:0]; bit arr_b [7:0]; initial begin arr_a = '{1, 1, 1, 1, 1, 1, 1, 1}; arr_b = '{0, 0, 0, 0, 0, 0, 0, 0}; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '1111_1111')", arr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]); $display(":assert: ('%b%b%b%b_%b%b%b%b' == '0000_0000')", arr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]); arr_b[5:3] = arr_a[2:0]; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '0011_1000')", arr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/subroutines.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpacked-arrays-as-arguments-to-subroutines :description: Test support of arrays as arugments to subroutines :tags: 7.7 7.4.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); task fun(int a [2:0]); $display(":assert: ((%d == 0) and (%d == 1) and (%d == 2))", a[0], a[1], a[2]); endtask; initial begin int b [2:0]; b[0] = 0; b[1] = 1; b[2] = 2; $display(":assert: ((%d == 0) and (%d == 1) and (%d == 2))", b[0], b[1], b[2]); fun(b); end endmodule ================================================ FILE: tests/chapter-7/arrays/unpacked/variable-slice.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: operations-on-unpacked-arrays-variable-slice-rw :description: Test packed arrays operations support (Variable slice) :tags: 7.4.3 7.4.6 :type: simulation elaboration parsing */ module top (); bit arr_a [7:0]; bit arr_b [7:0]; parameter integer c = 3; initial begin arr_a = '{1, 1, 1, 1, 1, 1, 1, 1}; arr_b = '{0, 0, 0, 0, 0, 0, 0, 0}; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '1111_1111')", arr_a[7], arr_a[6], arr_a[5], arr_a[4], arr_a[3], arr_a[2], arr_a[1], arr_a[0]); $display(":assert: ('%b%b%b%b_%b%b%b%b' == '0000_0000')", arr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]); arr_b[4+:c] = arr_a[1+:c]; $display(":assert: ('%b%b%b%b_%b%b%b%b' == '0111_0000')", arr_b[7], arr_b[6], arr_b[5], arr_b[4], arr_b[3], arr_b[2], arr_b[1], arr_b[0]); end endmodule ================================================ FILE: tests/chapter-7/memories/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: memories-basic :description: Test memories support :tags: 7.4.4 */ module top (); // one-dimensinal array with elements of types // reg, logic, bit logic [7:0] mem [0:255]; endmodule ================================================ FILE: tests/chapter-7/memories/read-write.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: memories-read-write :description: Test memories read-write support :tags: 7.4.4 :type: simulation elaboration parsing */ module top (); // one-dimensinal array with elements of types // reg, logic, bit logic [7:0] mem [0:255]; initial begin mem[5] = 0; $display(":assert: (%d == 0)", mem[5]); mem[5] = 5; $display(":assert: (%d == 5)", mem[5]); end endmodule ================================================ FILE: tests/chapter-7/queues/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: queues-basic :description: Test queues support :tags: 7.10 :unsynthesizable: 1 */ module top (); int q[$]; endmodule ================================================ FILE: tests/chapter-7/queues/bounded.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: bounded-queues :description: Test bounded queues support :tags: 7.10.5 7.10 7.10.2.7 7.10.2.1 :type: simulation elaboration parsing */ module top (); int q[$:2]; // 3 elements initial begin q.push_back(1); q.push_back(2); q.push_back(3); $display(":assert: ((%d == 1) and (%d == 2) and (%d == 3))", q[0], q[1], q[2]); $display(":re: BEGIN:QUEUE_FULL"); // expect warning q.push_back(4); $display(":re: END"); $display(":assert: (%d==3)", q.size); end endmodule ================================================ FILE: tests/chapter-7/queues/delete.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: delete :description: Test queues delete function support :tags: 7.10.2.3 7.10.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; int r; initial begin q.push_back(2); q.push_back(3); q.push_back(4); $display(":assert: (%d == 3)", q.size); q.delete(0); $display(":assert: (%d == 2)", q.size); q.delete; $display(":assert: (%d == 0)", q.size); end endmodule ================================================ FILE: tests/chapter-7/queues/delete_assign.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: delete-assign :description: Update queue by assignment (delete) :tags: 7.10.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; int r; initial begin q.push_back(2); q.push_back(3); q.push_back(4); $display(":assert: (%d == 3)", q.size); q = q[1:$]; // q.delete(0) $display(":assert: (%d == 2)", q.size); q = {}; // q.delete $display(":assert: (%d == 0)", q.size); end endmodule ================================================ FILE: tests/chapter-7/queues/insert.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: insert :description: Test queues insert function support :tags: 7.10.2.2 7.10.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; initial begin q.insert(0, 1); $display(":assert: (%d == 1)", q.size); $display(":assert: (%d == 1)", q[0]); end endmodule ================================================ FILE: tests/chapter-7/queues/insert_assign.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: insert-assign :description: Update queue by assignment (insert) :tags: 7.10.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; initial begin q = { 1, 2, 3, 4 }; q = { q[0:1], 10, q[2:$] }; // q.insert(2, 10) $display(":assert: (%d == 5)", q.size); $display(":assert: (%d == 10)", q[2]); end endmodule ================================================ FILE: tests/chapter-7/queues/max-size.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: max-size :description: Test queues size support :tags: 7.10.1 7.10.2 :type: simulation elaboration parsing */ module top (); int q[$:5]; initial begin q.push_back(0); q.push_back(1); q.push_back(2); q.push_back(3); q.push_back(4); q.push_back(5); $display(":assert: (%d == 6)", q.size); // should issue warning q.push_back(6); $display(":assert: (%d == 6)", q.size); end endmodule ================================================ FILE: tests/chapter-7/queues/persistence.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: queues-elements-persistence :description: Test status of persistence of references to elements of queue :tags: 7.10.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; task automatic fun(ref int e); $display(":assert: (%d == 2)", e); #100 e = 10; $display(":assert: (%d == 10)", e); endtask initial begin q.push_back(1); q.push_back(2); q.push_back(3); $display(":assert: ((%d == 1) and (%d == 2) and (%d == 3))", q[0], q[1], q[2]); fun(q[1]); end initial begin #50 $display(":assert: (%d == 2)", q[1]); q.delete(); #100; $display(":assert: (%d == 0)", q.size); end endmodule ================================================ FILE: tests/chapter-7/queues/pop_back.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pop_back :description: Test queues pop_back function support :tags: 7.10.2.5 7.10.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; int r; initial begin q.push_back(2); q.push_back(3); q.push_back(4); r = q.pop_back; $display(":assert: (%d == 2)", q.size); $display(":assert: (%d == 4)", r); end endmodule ================================================ FILE: tests/chapter-7/queues/pop_back_assing.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pop_back-assign :description: Update queue by assignment (pop_back) :tags: 7.10.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; int r; initial begin q = { 2, 3, 4 }; r = q[$]; q = q[0:$-1]; // void'(q.pop_back()) or q.delete(q.size-1) $display(":assert: (%d == 2)", q.size); $display(":assert: (%d == 4)", r); end endmodule ================================================ FILE: tests/chapter-7/queues/pop_front.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pop_front :description: Test queues pop_front function support :tags: 7.10.2.4 7.10.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; int r; initial begin q.push_back(2); q.push_back(3); q.push_back(4); r = q.pop_front; $display(":assert: (%d == 2)", q.size); $display(":assert: (%d == 2)", r); end endmodule ================================================ FILE: tests/chapter-7/queues/pop_front_assign.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: pop_front-assign :description: Update queue by assignment (pop_front) :tags: 7.10.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; int r; initial begin q.push_back(2); q.push_back(3); q.push_back(4); r = q[0]; q = q[1:$]; $display(":assert: (%d == 2)", q.size); $display(":assert: (%d == 2)", r); $display(":assert: (%d == 3)", q[0]); end endmodule ================================================ FILE: tests/chapter-7/queues/push_back.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: push_back :description: Test queues push_back function support :tags: 7.10.2.7 7.10.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; initial begin q.push_back(4); q.push_back(3); q.push_back(2); $display(":assert: (%d == 3)", q.size); $display(":assert: (%d == 4)", q[0]); end endmodule ================================================ FILE: tests/chapter-7/queues/push_back_assign.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: push_back_assign :description: Update queue by assignment (push_back) :tags: 7.10.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; initial begin q = { q, 4 }; q = { q, 3 }; q = { q, 2 }; $display(":assert: (%d == 3)", q.size); $display(":assert: (%d == 4)", q[0]); end endmodule ================================================ FILE: tests/chapter-7/queues/push_front.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: push_front :description: Test queues push_front function support :tags: 7.10.2.6 7.10.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; initial begin q.push_front(2); q.push_front(3); q.push_front(4); $display(":assert: (%d == 3)", q.size); $display(":assert: (%d == 4)", q[0]); end endmodule ================================================ FILE: tests/chapter-7/queues/push_front_assign.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: push_front_assign :description: Update queue by assignment (push_front) :tags: 7.10.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; initial begin q = { 2, q }; q = { 3, q }; q = { 4, q }; $display(":assert: (%d == 3)", q.size); $display(":assert: (%d == 4)", q[0]); end endmodule ================================================ FILE: tests/chapter-7/queues/size.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: size :description: Test queues size support :tags: 7.10.2.1 7.10.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$]; initial begin $display(":assert: (%d == 0)", q.size); end endmodule ================================================ FILE: tests/chapter-7/queues/slice.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: slice :description: Test queues slice support :tags: 7.10.1 7.10.2 :type: simulation elaboration parsing :unsynthesizable: 1 */ module top (); int q[$:5]; int r[$]; initial begin q.push_back(0); q.push_back(1); q.push_back(2); q.push_back(3); q.push_back(4); q.push_back(5); $display(":assert: (%d == 6)", q.size); r = q[ 2 : 4 ]; $display(":assert: (%d == 3)", r.size); // 4 - 2 + 1 elements // a > b gives empty queue r = q[ 4 : 2 ]; $display(":assert: (%d == 0)", r.size); // a == b gives one element queue r = q[ 2 : 2 ]; $display(":assert: (%d == 1)", r.size); // a < 0 is same as [ 0 : b ] r = q[ -2 : 2 ]; // 2 - 0 + 1 = 3 $display(":assert: (%d == 3)", r.size); // b > $ is same as [ a : $ ] r = q[ 2 : 10 ]; // 5 - 2 + 1 = 4 $display(":assert: (%d == 4)", r.size); // TODO: More invalid index values end endmodule ================================================ FILE: tests/chapter-7/structures/packed/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: basic-packed-structures :description: Test packed structures support :tags: 7.2.1 7.2 7.1 :type: simulation elaboration parsing */ module top (); struct packed { bit [3:0] lo; bit [3:0] hi; } p1; initial begin p1 = 8'h5a; $display(":assert: ('%h' == '5a')", p1); $display(":assert: (('%h' == 'a') and ('%h' == '5'))", p1.hi, p1.lo); end endmodule ================================================ FILE: tests/chapter-7/structures/packed/default-value.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: packed-structures-default-members-value :description: Test packed structures default value support :should_fail_because: members of packed structures shall not be assigned individual default member values. :tags: 7.2.2 :type: simulation elaboration */ module top (); // Members of unpacked structures containing a union // as well as members of packed structures shall not be // assigned individual default member values. parameter c = 4'h5; struct packed { bit [3:0] lo = c; bit [3:0] hi; } p1; endmodule ================================================ FILE: tests/chapter-7/structures/packed/signed.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: packed-and-signed-structures :description: Test packed and signed structures support :tags: 7.2.1 7.2 :type: simulation elaboration parsing */ module top (); struct packed signed { bit [3:0] lo; bit [3:0] hi; } p1; initial begin p1 = 8'd200; $display(":assert: ('%h' == 'c8')", p1); $display(":assert: (%d == -56)", p1); end endmodule ================================================ FILE: tests/chapter-7/structures/packed/unsigned.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: packed-and-unsigned-structures :description: Test packed and unsigned structures support :tags: 7.2.1 7.2 :type: simulation elaboration parsing */ module top (); struct packed unsigned { bit [3:0] lo; bit [3:0] hi; } p1; initial begin p1 = 8'd200; $display(":assert: ('%h' == 'c8')", p1); $display(":assert: (%d == 200)", p1); end endmodule ================================================ FILE: tests/chapter-7/structures/unpacked/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: basic-unpacked-structures :description: Test unpacked structures support :tags: 7.2 7.1 :type: simulation elaboration parsing */ module top (); struct { bit [3:0] lo; bit [3:0] hi; } p1; initial begin p1.lo = 4'h5; p1.hi = 4'ha; $display(":assert: (('%h' == 'a') and ('%h' == '5'))", p1.hi, p1.lo); end endmodule ================================================ FILE: tests/chapter-7/structures/unpacked/default-value.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: unpacked-structures-members-default-value :description: Test unpacked structures members default value support :tags: 7.2.2 :type: simulation elaboration parsing */ module top (); parameter c = 4'h5; struct { bit [3:0] lo = c; bit [3:0] hi; } p1; initial begin p1.hi = 4'ha; $display(":assert: (('%h' == 'a') and ('%h' == '5'))", p1.hi, p1.lo); end endmodule ================================================ FILE: tests/chapter-7/unions/packed/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: basic-packed-unions :description: Test basic union support :tags: 7.3.1 :type: simulation elaboration parsing */ module top (); union packed { bit [7:0] v1; bit [7:0] v2; } un; initial begin un.v1 = 8'd140; $display(":assert: (%d == 140)", un.v1); $display(":assert: (%d == 140)", un.v2); end endmodule ================================================ FILE: tests/chapter-7/unions/tagged/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: basic-tagged-union :description: Test basic tagged union support :tags: 7.3.2 :type: simulation elaboration parsing */ module top (); union tagged { void invalid; bit [3:0] valid; } un; initial begin un = tagged valid (10); $display(":assert: ('%p' == ''{valid:10}')", un); end endmodule ================================================ FILE: tests/chapter-7/unions/tagged/packed.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: basic-tagged-packed-union :description: Test tagged packed union support :tags: 7.3.2 :type: simulation elaboration parsing */ module top (); union tagged packed { bit [6:0] v1; bit [6:0] v2; } un; initial begin un = tagged v2 (10); un = tagged v1 (85); // 101_0101 $display(":assert: ('%b' == '01010101')", un); end endmodule ================================================ FILE: tests/chapter-7/unions/unpacked/basic.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: basic-union :description: Test basic union support :tags: 7.3 :type: simulation elaboration parsing */ module top (); union { bit [7:0] v1; bit [3:0] v2; } un; initial begin un.v1 = 8'd140; $display(":assert: (%d == 140)", un.v1); $display(":assert: (%d == 12)", un.v2); end endmodule ================================================ FILE: tests/chapter-8/8.10--static_methods.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: static_methods :description: static class methods test :tags: 8.10 :unsynthesizable: 1 */ module class_tb (); class test_cls; static int id = 0; static function int next_id(); ++id; next_id = id; endfunction endclass test_cls test_obj0; test_cls test_obj1; initial begin test_obj0 = new; test_obj1 = new; $display(test_obj0.next_id()); $display(test_obj1.next_id()); end endmodule ================================================ FILE: tests/chapter-8/8.11--this.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: this :description: this keyword test :tags: 8.11 :unsynthesizable: 1 */ module class_tb (); class test_cls; int a; task test_method(int a); $display("test_method"); this.a += a; endtask endclass endmodule ================================================ FILE: tests/chapter-8/8.12--assignment.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: assignment :description: object assignment :tags: 8.12 :unsynthesizable: 1 */ module class_tb (); class test_cls; int a; task test_method(int val); $display("test_method"); a += val; endtask endclass test_cls test_obj0; test_cls test_obj1; initial begin test_obj0 = new; test_obj1 = test_obj0; test_obj0.a = 12; $display(test_obj0.a); test_obj0.test_method(9); $display(test_obj1.a); end endmodule ================================================ FILE: tests/chapter-8/8.12--shallow_copy.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: shallow_copy :description: object shallow copy :tags: 8.12 :unsynthesizable: 1 */ module class_tb (); class test_cls; int a; task test_method(int val); $display("test_method"); a += val; endtask endclass test_cls test_obj0; test_cls test_obj1; initial begin test_obj0 = new; test_obj0.a = 12; $display(test_obj0.a); test_obj1 = new test_obj0; test_obj0.test_method(9); $display(test_obj1.a); end endmodule ================================================ FILE: tests/chapter-8/8.13--inheritance.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: inheritance :description: class inheritance test :tags: 8.13 :unsynthesizable: 1 */ module class_tb (); class super_cls; int s = 2; function int incs(); ++s; incs = s; endfunction function new(int def = 3); s = def; endfunction endclass class test_cls extends super_cls; int a; function new(int def = 42); super.new(def + 3); a = def; endfunction endclass test_cls test_obj; initial begin test_obj = new(37); $display(test_obj.incs()); $display(test_obj.s); end endmodule ================================================ FILE: tests/chapter-8/8.14--override_member.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: override_member :description: class member override test :tags: 8.14 :unsynthesizable: 1 */ module class_tb (); class super_cls; int s = 2; function int incs(); ++s; incs = s; endfunction function new(int def = 3); s = def; endfunction endclass class test_cls extends super_cls; int a; function int incs(); s += 2; incs = s; endfunction function new(int def = 42); super.new(def + 3); a = def; endfunction endclass test_cls test_obj; super_cls super_obj; initial begin test_obj = new(37); super_obj = test_obj; $display(test_obj.s); $display(test_obj.incs()); $display(test_obj.s); $display(super_obj.incs()); end endmodule ================================================ FILE: tests/chapter-8/8.15--super-default-new.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: super-def-new :description: Base class has no user-defined constructor, derived class accesses superclass new() :tags: 8.15 :unsynthesizable: 1 */ package test_pkg; virtual class uvm_void; endclass : uvm_void class uvm_object extends uvm_void; virtual function void print (); $display ("Print"); endfunction : print endclass : uvm_object class uvm_report_object extends uvm_object; function new (); super.new (); endfunction : new endclass : uvm_report_object endpackage : test_pkg module m; import test_pkg::*; uvm_object u0; initial begin : test #100; $display ("Hello World"); u0 = new (); u0.print(); end : test endmodule : m ================================================ FILE: tests/chapter-8/8.15--super.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: super :description: accessing superclass methods via super :tags: 8.15 :unsynthesizable: 1 */ module class_tb (); class super_cls; int s = 2; function int incs(); ++s; incs = s; endfunction function new(int def = 3); s = def; endfunction endclass class test_cls extends super_cls; int a; function int incs(); s += 2; incs = super.incs(); endfunction function new(int def = 42); super.new(def + 3); a = def; endfunction endclass test_cls test_obj; super_cls super_obj; initial begin test_obj = new(37); super_obj = test_obj; $display(test_obj.s); $display(test_obj.incs()); end endmodule ================================================ FILE: tests/chapter-8/8.16--cast_func.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cast_func :description: $cast function test :tags: 8.16 :unsynthesizable: 1 */ module class_tb (); typedef enum { aaa, bbb, ccc, ddd, eee } values; initial begin values val; if(!$cast(val, 5)) $display("$cast failed"); $display(val); end endmodule ================================================ FILE: tests/chapter-8/8.17--constructor_const_arg.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constructor_const_arg :description: class inheritance with a constant constructor argument :tags: 8.17 :unsynthesizable: 1 */ module class_tb (); class super_cls; int s = 2; function new(int def = 3); s = def; endfunction endclass class test_cls extends super_cls(5); int a; function new(int def = 42); a = def; endfunction endclass test_cls test_obj; initial begin test_obj = new(37); $display(test_obj.a); $display(test_obj.s); end endmodule ================================================ FILE: tests/chapter-8/8.18--var_local.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: var_local :description: class with local variable :tags: 8.18 */ module class_tb (); class a_cls; local int a_loc = 2; endclass endmodule ================================================ FILE: tests/chapter-8/8.18--var_protected.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: var_protected :description: class with protected variable :tags: 8.18 */ module class_tb (); class a_cls; protected int a_prot = 2; endclass endmodule ================================================ FILE: tests/chapter-8/8.19--global_constant.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: global_constant :description: class with global constant variable :tags: 8.19 */ module class_tb (); class a_cls; const int c = 12; endclass endmodule ================================================ FILE: tests/chapter-8/8.19--instance_constant.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: instance_constant :description: class with instance constant variable :tags: 8.19 :unsynthesizable: 1 */ module class_tb (); class a_cls; const int c; function new(int val); c = 20 * val; endfunction endclass endmodule ================================================ FILE: tests/chapter-8/8.20--virtual_method.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: virtual_method :description: class with virtual methods :tags: 8.20 :unsynthesizable: 1 */ module class_tb (); class super_cls; int a = 1; virtual function void print(); $display("super_cls::a: %d", a); endfunction endclass class test_cls extends super_cls; int a = 2; virtual function void print(); $display("test_cls::a: %d", a); endfunction endclass test_cls test_obj; super_cls super_obj; initial begin test_obj = new; super_obj = new; test_obj.print(); super_obj.print(); super_obj = test_obj; test_obj.print(); super_obj.print(); end endmodule ================================================ FILE: tests/chapter-8/8.21--abstract_class.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: abstract_class :description: class extending abstract class :tags: 8.21 :unsynthesizable: 1 */ module class_tb (); virtual class base_cls; pure virtual function void print(); endclass class test_cls extends base_cls; int a = 2; virtual function void print(); $display(a); endfunction endclass test_cls test_obj; initial begin test_obj = new; test_obj.print(); end endmodule ================================================ FILE: tests/chapter-8/8.21--abstract_class_inst.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: abstract_class_inst :description: instantiating abstract class :should_fail_because: instantiating abstract class :tags: 8.21 :type: simulation elaboration :unsynthesizable: 1 */ module class_tb (); virtual class base_cls; pure virtual function void print(); endclass class test_cls extends base_cls; int a = 2; virtual function void print(); $display(a); endfunction endclass base_cls test_obj; initial begin test_obj = new; test_obj.print(); end endmodule ================================================ FILE: tests/chapter-8/8.22--dynamic_method_lookup.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: dynamic_method_lookup :description: dynamic method selection with abstract base class :tags: 8.22 :unsynthesizable: 1 */ module class_tb (); virtual class base_cls; pure virtual function void print(); endclass class a_cls extends base_cls; virtual function void print(); $display("a"); endfunction endclass class b_cls extends base_cls; virtual function void print(); $display("b"); endfunction endclass class c_cls extends base_cls; virtual function void print(); $display("c"); endfunction endclass base_cls arr[3]; a_cls a; b_cls b; c_cls c; initial begin a = new; b = new; c = new; arr[0] = a; arr[1] = b; arr[2] = c; arr[0].print(); arr[1].print(); arr[2].print(); end endmodule ================================================ FILE: tests/chapter-8/8.23--scope_resolution.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: scope_resolution :description: access static method using scope resolution operator :tags: 8.23 :unsynthesizable: 1 */ module class_tb (); class test_cls; static int id = 0; static function int next_id(); ++id; next_id = id; endfunction endclass initial begin $display(test_cls::next_id()); $display(test_cls::next_id()); end endmodule ================================================ FILE: tests/chapter-8/8.24--out_of_block_methods.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: out_of_block_methods :description: out-of-body method declaration :tags: 8.24 :unsynthesizable: 1 */ module class_tb (); class test_cls; int a; extern function void test_method(int val); endclass function void test_cls::test_method(int val); $display("test_method"); a += val; endfunction test_cls test_obj; initial begin test_obj = new; test_obj.a = 12; $display(test_obj.a); test_obj.test_method(9); $display(test_obj.a); end endmodule ================================================ FILE: tests/chapter-8/8.25--parametrized_class_extend.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parametrized_class_extend :description: parametrized class extending another parametrized class :tags: 8.25 :unsynthesizable: 1 */ module class_tb (); class base_cls #(int b = 20); int a; endclass class ext_cls #(int e = 25) extends base_cls #(5); int c; endclass ext_cls #(15) inst; initial begin inst = new; end endmodule ================================================ FILE: tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parametrized_class_invalid_scope_resolution :description: parametrized class invalid scope resolution :should_fail_because: parametrized class invalid scope resolution :tags: 8.25.1 :type: simulation elaboration :unsynthesizable: 1 */ module class_tb (); class par_cls #(int a = 25); parameter int b = 23; endclass par_cls #(15) inst; initial begin inst = new; $display(par_cls::b); end endmodule ================================================ FILE: tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parametrized_class_scope_resolution :description: parametrized class scope resolution :tags: 8.25.1 :unsynthesizable: 1 */ module class_tb (); class par_cls #(int a = 25); parameter int b = 23; endclass par_cls #(15) inst; initial begin inst = new; $display(par_cls#()::b); end endmodule ================================================ FILE: tests/chapter-8/8.26.2--implements.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implements :description: implements keyword test :tags: 8.26.2 :unsynthesizable: 1 */ module class_tb (); interface class ihello; pure virtual function void hello(); endclass class Hello implements ihello; virtual function void hello(); $display("hello world"); endfunction endclass Hello obj; initial begin obj = new; obj.hello(); end endmodule ================================================ FILE: tests/chapter-8/8.26.2--implements_extends.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implements_extends :description: class both implementing and extending :tags: 8.26.2 :unsynthesizable: 1 */ module class_tb (); interface class ihello; pure virtual function void hello(); endclass interface class itest; pure virtual function void test(); endclass class base; function method(); $display("method"); endfunction endclass class Hello extends base implements ihello, itest; virtual function void hello(); $display("hello world"); endfunction virtual function void test(); $display("test"); endfunction endclass Hello obj; initial begin obj = new; obj.method(); obj.hello(); obj.test(); end endmodule ================================================ FILE: tests/chapter-8/8.26.2--implements_multiple.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implements_multiple :description: class implementing multiple interfaces :tags: 8.26.2 :unsynthesizable: 1 */ module class_tb (); interface class ihello; pure virtual function void hello(); endclass interface class itest; pure virtual function void test(); endclass class Hello implements ihello, itest; virtual function void hello(); $display("hello world"); endfunction virtual function void test(); $display("test"); endfunction endclass Hello obj; initial begin obj = new; obj.hello(); obj.test(); end endmodule ================================================ FILE: tests/chapter-8/8.26.3--type_access_extends.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: type_access_extends :description: accessing types from extended interface class :tags: 8.26.3 */ module class_tb (); interface class ihello; typedef int int_t; pure virtual function void hello(int_t val); endclass interface class ihello_ex extends ihello; pure virtual function void hello_ex(int_t v1, int_t v2); endclass endmodule ================================================ FILE: tests/chapter-8/8.26.3--type_access_implements.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: type_access_implements :description: access interface class type with scope resolution operator :tags: 8.26.3 :type: simulation elaboration parsing :unsynthesizable: 1 */ module class_tb (); interface class ihello; typedef int int_t; pure virtual function void hello(int_t val); endclass class Hello implements ihello; virtual function void hello(ihello::int_t val); $display(":assert:(%d == 12)", val); endfunction endclass Hello obj; initial begin obj = new; obj.hello(12); end endmodule ================================================ FILE: tests/chapter-8/8.26.3--type_access_implements_invalid.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: type_access_implements_invalid :description: access types from implemented class :should_fail_because: typedefs are not inherited by implements operator :tags: 8.26.3 :type: simulation elaboration :unsynthesizable: 1 */ module class_tb (); interface class ihello; typedef int int_t; pure virtual function void hello(int_t val); endclass class Hello implements ihello; virtual function void hello(int_t val); $display("hello world %d", val); endfunction endclass Hello obj; initial begin obj = new; obj.hello(); end endmodule ================================================ FILE: tests/chapter-8/8.26.4--illegal_forward_def_implements.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: illegal_forward_def_implements :description: implementing forward typedef for an interface class should fail :should_fail_because: implementing forward typedef for an interface class should fail :tags: 8.26.4 :type: simulation elaboration :unsynthesizable: 1 */ module class_tb (); typedef interface class ihello; class Hello implements ihello; virtual function void hello(ihello::int_t val); $display("hello world %d", val); endfunction endclass interface class ihello; typedef int int_t; pure virtual function void hello(int_t val); endclass Hello obj; initial begin obj = new; obj.hello(); end endmodule ================================================ FILE: tests/chapter-8/8.26.4--illegal_implements_parameter.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: illegal_implements_parameter :description: implementing parameter that resolves to an interface class is not allowed :should_fail_because: implementing parameter that resolves to an interface class is not allowed :tags: 8.26.4 :type: simulation elaboration :unsynthesizable: 1 */ module class_tb (); interface class ihello; typedef int int_t; pure virtual function void hello(int_t val); endclass class Hello #(type T = ihello) implements T; virtual function void hello(ihello::int_t val); $display("hello world %d", val); endfunction endclass Hello obj; initial begin obj = new; obj.hello(); end endmodule ================================================ FILE: tests/chapter-8/8.26.5--cast_between_interface_classes.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: cast_between_interface_classes :description: it should be possible to cast between implemented interface classes :tags: 8.26.2 :unsynthesizable: 1 */ module class_tb (); interface class ihello; pure virtual function void hello(); endclass interface class itest; pure virtual function void test(); endclass class Hello implements ihello, itest; virtual function void hello(); $display("hello world"); endfunction virtual function void test(); $display("test"); endfunction endclass Hello obj; ihello ih_ref; itest it_ref; initial begin obj = new; ih_ref = obj; $cast(it_ref, ih_ref); end endmodule ================================================ FILE: tests/chapter-8/8.26.5--implemented_class_handle.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: implemented_class_handle :description: it should be possible to assign object handle to a variable of an implemented class type :tags: 8.26.5 :unsynthesizable: 1 */ module class_tb (); interface class ihello; pure virtual function void hello(); endclass class Hello implements ihello; virtual function void hello(); $display("hello world"); endfunction endclass Hello obj; ihello iobj; initial begin obj = new; iobj = obj; end endmodule ================================================ FILE: tests/chapter-8/8.26.5--invalid_interface_instantiation.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: interface_instantiation :description: instantiating an interface class :should_fail_because: instantiating an interface class :tags: 8.26.5 :type: simulation elaboration :unsynthesizable: 1 */ module class_tb (); interface class ihello; pure virtual function void hello(); endclass ihello obj; initial begin obj = new; end endmodule ================================================ FILE: tests/chapter-8/8.26.6.1--name_conflict_resolved.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: name_conflict_resolved :description: resolved interface class method name conflict :tags: 8.26.6.1 :type: simulation elaboration parsing :unsynthesizable: 1 */ module class_tb (); interface class ihello; pure virtual function void hello(); endclass interface class itest; pure virtual function void hello(); endclass class Hello implements ihello, itest; virtual function void hello(); $display(":assert:(True)"); endfunction endclass Hello obj; initial begin obj = new; obj.hello(); end endmodule ================================================ FILE: tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: name_conflict_unresolved :description: unresolved interface class method name conflict :should_fail_because: unresolved interface class method name conflict :tags: 8.26.6.1 :type: simulation elaboration :unsynthesizable: 1 */ module class_tb (); interface class ihello; pure virtual function void hello(); endclass interface class itest; pure virtual function int hello(); endclass class Hello implements ihello, itest; virtual function void hello(); $display("hello world"); endfunction endclass Hello obj; initial begin obj = new; obj.hello(); end endmodule ================================================ FILE: tests/chapter-8/8.26.6.2--parameter_type_conflict.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameter_type_conflict :description: superclass type declaration conflicts must be resolved in subclass :tags: 8.26.6.2 */ module class_tb (); interface class ic1#(type T = logic); pure virtual function void fn1(T a); endclass interface class ic2#(type T = logic); pure virtual function void fn2(T a); endclass interface class ic3#(type TYPE = logic) extends ic1#(TYPE), ic2#(TYPE); typedef TYPE T; endclass endmodule ================================================ FILE: tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameter_type_conflict_unresolved :description: superclass type declaration conflicts must be resolved in subclass :should_fail_because: superclass type declaration conflicts must be resolved in subclass :tags: 8.26.6.2 :type: simulation elaboration */ module class_tb (); interface class ic1#(type T = logic); pure virtual function void fn1(T a); endclass interface class ic2#(type T = logic); pure virtual function void fn2(T a); endclass interface class ic3#(type TYPE = logic) extends ic1#(TYPE), ic2#(TYPE); endclass endmodule ================================================ FILE: tests/chapter-8/8.26.6.3--diamond_relationship.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: diamond_relationship :description: interface class inherited from multiple sources shouldn't create symbol conflicts :tags: 8.26.6.3 */ module class_tb (); interface class ibase; pure virtual function void fn(); endclass interface class ic1 extends ibase; pure virtual function void fn1(); endclass interface class ic2 extends ibase; pure virtual function void fn2(); endclass interface class ic3 extends ic1, ic2; pure virtual function void fn3(); endclass endmodule ================================================ FILE: tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: diamond_relationship_parametrized :description: different specializations of an interface class are treated as unique interface class types :should_fail_because: different specializations of an interface class are treated as unique interface class types :tags: 8.26.6.3 :type: simulation elaboration */ module class_tb (); interface class ibase#(type T = logic); pure virtual function void fn(T val); endclass interface class ic1 extends ibase#(bit); pure virtual function void fn1(); endclass interface class ic2 extends ibase#(string); pure virtual function void fn2(); endclass interface class ic3 extends ic1, ic2; pure virtual function void fn3(); endclass endmodule ================================================ FILE: tests/chapter-8/8.26.7--partial_implementation.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: partial_implementation :description: virtual classes can implement their interfaces partially :tags: 8.26.7 :unsynthesizable: 1 */ module class_tb (); interface class ihello; pure virtual function void hello(); pure virtual function void world(); endclass virtual class vhello implements ihello; virtual function void hello(); $display("hello"); endfunction pure virtual function void world(); endclass class helloworld extends vhello; virtual function void world(); $display("world"); endfunction endclass helloworld obj; initial begin obj = new; obj.hello(); obj.world(); end endmodule ================================================ FILE: tests/chapter-8/8.27--forward_declaration.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: forward_declaration :description: class forward declaration test :tags: 8.27 */ module class_tb (); typedef class C2; class C1; C2 c; endclass class C2; C1 c; endclass endmodule ================================================ FILE: tests/chapter-8/8.4--instantiation.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: instantiation :description: simple class instantiation test :tags: 8.4 :unsynthesizable: 1 */ module class_tb (); class test_cls; int a; endclass test_cls test_obj; initial begin if(test_obj == null) test_obj = new; end endmodule ================================================ FILE: tests/chapter-8/8.5--parameters.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parameters :description: parametrized class test :tags: 8.5 8.25 :type: simulation elaboration parsing :unsynthesizable: 1 */ module class_tb (); class test_cls #(parameter a = 12); endclass test_cls #(34) test_obj; initial begin test_obj = new; $display(":assert:(%d == 34)", test_obj.a); end endmodule ================================================ FILE: tests/chapter-8/8.5--properties.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: properties :description: class properties test :tags: 8.5 :type: simulation elaboration parsing :unsynthesizable: 1 */ module class_tb (); class test_cls; int a; endclass test_cls test_obj; initial begin test_obj = new; test_obj.a = 12; $display(":assert:(%d == 12)", test_obj.a); end endmodule ================================================ FILE: tests/chapter-8/8.5--properties_enum.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: properties_enum :description: enum defined inside class :tags: 8.5 :unsynthesizable: 1 */ module class_tb (); class test_cls; typedef enum {A = 10, B = 20, C = 30, D = 1} e_type; endclass test_cls test_obj; initial begin test_obj = new; $display(test_obj.C); end endmodule ================================================ FILE: tests/chapter-8/8.6--methods.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: methods :description: class method test :tags: 8.6 :unsynthesizable: 1 */ module class_tb (); class test_cls; int a; task test_method(int val); $display("test_method"); a += val; endtask endclass test_cls test_obj; initial begin test_obj = new; test_obj.a = 12; $display(test_obj.a); test_obj.test_method(9); $display(test_obj.a); end endmodule ================================================ FILE: tests/chapter-8/8.7--constructor.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constructor :description: class constructor test :tags: 8.7 :type: simulation elaboration parsing :unsynthesizable: 1 */ module class_tb (); class test_cls; int a; function new(); a = 42; endfunction endclass initial begin test_cls test_obj = new; $display(":assert:(%d == 42)", test_obj.a); end endmodule ================================================ FILE: tests/chapter-8/8.7--constructor_param.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constructor_param :description: class constructor with arguments test :tags: 8.7 :type: simulation elaboration parsing :unsynthesizable: 1 */ module class_tb (); class test_cls; int a; function new(int def = 42); a = def; endfunction endclass initial begin test_cls test_obj = new(37); $display(":assert:(%d == 37)", test_obj.a); end endmodule ================================================ FILE: tests/chapter-8/8.7--constructor_super.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: constructor_super :description: class constructor super test :tags: 8.7 8.17 :unsynthesizable: 1 */ module class_tb (); class super_cls; int s = 2; function new(int def = 3); s = def; endfunction endclass class test_cls extends super_cls; int a; function new(int def = 42); super.new(def + 3); a = def; endfunction endclass test_cls test_obj; initial begin test_obj = new(37); $display(test_obj.a); $display(test_obj.s); end endmodule ================================================ FILE: tests/chapter-8/8.8--typed_constructor.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typed_constructor :description: class typed constructor test :tags: 8.8 :unsynthesizable: 1 */ module class_tb (); class super_cls; int s = 2; function new(int def = 3); s = def; endfunction endclass class test_cls extends super_cls; int a; function new(int def = 42); super.new(def + 3); a = def; endfunction endclass test_cls super_obj; initial begin super_obj = test_cls::new; $display(super_obj.s); end endmodule ================================================ FILE: tests/chapter-8/8.8--typed_constructor_param.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typed_constructor_param :description: typed class constructor with parameters test :tags: 8.8 :unsynthesizable: 1 */ module class_tb (); class super_cls; int s = 2; function new(int def = 3); s = def; endfunction endclass class test_cls #(int t = 12) extends super_cls; int a; function new(int def = 42); super.new(def + 3); a = def - t; endfunction endclass super_cls super_obj; initial begin super_obj = test_cls#(.t(23))::new(.def(41)); $display(super_obj.s); end endmodule ================================================ FILE: tests/chapter-8/8.9--static_properties.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: static_properties :description: static class properties test :tags: 8.9 :unsynthesizable: 1 */ module class_tb (); class test_cls; static int s = 24; endclass test_cls test_obj0; test_cls test_obj1; initial begin test_obj0 = new; test_obj1 = new; test_obj0.s = 12; $display(test_obj0.s); test_obj0.s = 13; $display(test_obj1.s); end endmodule ================================================ FILE: tests/chapter-9/9.2.1--initial.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: initial :description: initial check :tags: 9.2.1 */ module initial_tb (); reg a = 0; initial a = 1; endmodule ================================================ FILE: tests/chapter-9/9.2.2.1--always.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: always :description: always check :tags: 9.2.2.1 9.4.1 */ module always_tb (); logic a = 0; always #5 a = ~a; endmodule ================================================ FILE: tests/chapter-9/9.2.2.2--always_comb.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: always_comb :description: always_comb check :tags: 9.2.2.2 */ module always_tb (); wire a = 0; reg b = 0; always_comb b = ~a; endmodule ================================================ FILE: tests/chapter-9/9.2.2.3--always_latch.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: always_latch_expr :description: always_latch check :tags: 9.2.2.3 */ module always_tb (); wire a = 0; wire b = 0; reg q = 0; always_latch if(a) q <= b; endmodule ================================================ FILE: tests/chapter-9/9.2.2.4--always_ff.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: always_ff :description: always_ff check :tags: 9.2.2.4 */ module always_tb (); wire a = 0; wire b = 0; reg q = 0; always_ff @(posedge a) q <= b; endmodule ================================================ FILE: tests/chapter-9/9.2.3--final.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: final :description: final check :tags: 9.2.3 */ module initial_tb (); reg a = 0; final a = 1; endmodule ================================================ FILE: tests/chapter-9/9.3.1--sequential_block.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sequential_block :description: sequential block check :tags: 9.3.1 */ module sequential_tb (); reg a = 0; reg b = 0; reg c = 0; initial begin a = 1; b = a; c = b; end endmodule ================================================ FILE: tests/chapter-9/9.3.2--parallel_block_join.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parallel_block_join :description: parallel block check :tags: 9.3.2 :unsynthesizable: 1 */ module parallel_tb (); reg a = 0; reg b = 0; reg c = 0; initial fork a = 1; b = 0; c = 1; join endmodule ================================================ FILE: tests/chapter-9/9.3.2--parallel_block_join_any.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parallel_block_join_any :description: parallel block check :tags: 9.3.2 :unsynthesizable: 1 */ module parallel_tb (); reg a = 0; reg b = 0; reg c = 0; initial fork a = 1; b = 0; c = 1; join_any endmodule ================================================ FILE: tests/chapter-9/9.3.2--parallel_block_join_none.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: parallel_block_join_none :description: parallel block check :tags: 9.3.2 :unsynthesizable: 1 */ module parallel_tb (); reg a = 0; reg b = 0; reg c = 0; initial fork a = 1; b = 0; c = 1; join_none endmodule ================================================ FILE: tests/chapter-9/9.3.3--block_start_finish.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: block_start_finish :description: block start finish check :tags: 9.3.3 :unsynthesizable: 1 */ module block_tb (); reg [3:0] a = 0; initial begin fork #200 a = 'h1; #150 a = 'h2; #100 a = 'h3; #50 a = 'h4; join fork #200 a = 'h5; #150 a = 'h6; #100 a = 'h7; #50 a = 'h8; join end endmodule ================================================ FILE: tests/chapter-9/9.3.3--event.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_order :description: event order test :tags: 9.3.3 :unsynthesizable: 1 */ module block_tb (); event ev; reg [3:0] a = 0; initial fork begin a = 'h3; #20; ->ev; end begin @ev a = 'h4; end join endmodule ================================================ FILE: tests/chapter-9/9.3.3--fork_return.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: fork_return :description: illegal return from fork :should_fail_because: illegal return from fork :tags: 9.3.3 :type: simulation elaboration :unsynthesizable: 1 */ module block_tb (); task fork_test; fork #20; return; join_none endtask endmodule ================================================ FILE: tests/chapter-9/9.3.4--block_names_par.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: block_names_par :description: parallel block names check :tags: 9.3.4 :unsynthesizable: 1 */ module block_tb (); reg a = 0; initial fork: name a = 1; join: name endmodule ================================================ FILE: tests/chapter-9/9.3.4--block_names_seq.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: block_names_seq :description: sequential block names check :tags: 9.3.4 */ module block_tb (); reg a = 0; reg b = 0; reg c = 0; initial begin: name a = 1; b = a; c = b; end: name endmodule ================================================ FILE: tests/chapter-9/9.3.5--statement_labels_par.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: statement_labels_par :description: parallel block labels check :tags: 9.3.5 :unsynthesizable: 1 */ module block_tb (); reg a = 0; initial name: fork a = 1; join: name endmodule ================================================ FILE: tests/chapter-9/9.3.5--statement_labels_seq.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: statement_labels_seq :description: sequential block labels check :tags: 9.3.5 */ module block_tb (); reg a = 0; reg b = 0; reg c = 0; initial name: begin a = 1; b = a; c = b; end: name endmodule ================================================ FILE: tests/chapter-9/9.4.1--delay_control-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: delay_control_sim :description: delay control simulation :tags: 9.4.1 :type: simulation elaboration :unsynthesizable: 1 */ module top(); initial begin $display(":assert: (0 == %d)", $time); #10; $display(":assert: (10 == %d)", $time); #10; $display(":assert: (20 == %d)", $time); #10; $display(":assert: (30 == %d)", $time); $finish; end endmodule ================================================ FILE: tests/chapter-9/9.4.1--delay_control-two-blocks-sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: delay_control_two_blocks_sim :description: delay control simulation with two blocks :tags: 9.4.1 :type: simulation elaboration :unsynthesizable: 1 */ module top(); initial begin $display(":assert: (0 == %d)", $time); #10; $display(":assert: (10 == %d)", $time); #10; $display(":assert: (20 == %d)", $time); #10; $display(":assert: (30 == %d)", $time); $finish; end initial begin #5; #10; #10; end endmodule ================================================ FILE: tests/chapter-9/9.4.1--delay_control.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: delay_control :description: delay control :tags: 9.4.1 :unsynthesizable: 1 */ module block_tb (); reg [3:0] a = 0; initial begin #10 a = 'h1; #10 a = 'h2; #10 a = 'h3; #10 a = 'h4; end endmodule ================================================ FILE: tests/chapter-9/9.4.2--event_control_edge.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_control_edge :description: event control :tags: 9.4.2 */ module block_tb (); reg [3:0] a = 0; wire clk = 0; always @(edge clk) a = ~a; endmodule ================================================ FILE: tests/chapter-9/9.4.2--event_control_negedge.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_control_negedge :description: event control :tags: 9.4.2 */ module block_tb (); reg [3:0] a = 0; wire clk = 0; always @(negedge clk) a = ~a; endmodule ================================================ FILE: tests/chapter-9/9.4.2--event_control_posedge.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_control_posedge :description: event control :tags: 9.4.2 */ module block_tb (); reg [3:0] a = 0; wire clk = 0; always @(posedge clk) a = ~a; endmodule ================================================ FILE: tests/chapter-9/9.4.2--event_control_sim.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_control_simulation :description: Test event invocation :tags: 9.4.2 :type: simulation elaboration :unsynthesizable: 1 */ module top(); event e; int i = 0; initial begin // For now increment time and order locally only, do some simple checks #5; i++; $display(":assert: (1 == %d)", i); $display(":assert: (5 == %d)", $time); #5; i++; $display(":assert: (2 == %d)", i); $display(":assert: (10 == %d)", $time); // Run event a, i should be incremented inside that event #2; ->e; // i is not incremented until the next delay $display(":assert: (2 == %d)", i); // but time already is $display(":assert: (12 == %d)", $time); #3; $display(":assert: (3 == %d)", i); $display(":assert: (15 == %d)", $time); $finish; end always @ (e) begin i++; end endmodule ================================================ FILE: tests/chapter-9/9.4.2--event_control_sim_minimal.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_control_simulation_minimal :description: Test event invocation :tags: 9.4.2 :type: simulation elaboration :unsynthesizable: 1 */ module top(); event e; int i = 0; initial begin $display(":assert: (0 == %d)", i); $display(":assert: (0 == %d)", $time); ->e; #5; $display(":assert: (1 == %d)", i); $display(":assert: (5 == %d)", $time); $finish; end always @ (e) begin i++; end endmodule ================================================ FILE: tests/chapter-9/9.4.2.1--event_comma_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_comma_op :description: event comma operator :tags: 9.4.2.1 */ module block_tb (); wire a = 0; wire b = 0; wire c = 0; wire d = 0; reg out; always @(a, b, c, d) out = (a | b) & (c | d); endmodule ================================================ FILE: tests/chapter-9/9.4.2.1--event_or_op.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_or_op :description: event or operator :tags: 9.4.2.1 */ module block_tb (); wire a = 0; wire b = 0; wire c = 0; wire d = 0; reg out; always @(a or b or c or d) out = (a | b) & (c | d); endmodule ================================================ FILE: tests/chapter-9/9.4.2.2--event_implicit.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_implicit :description: event implicit list :tags: 9.4.2.2 */ module block_tb (); wire a = 0; wire b = 0; wire c = 0; wire d = 0; reg out; always @(*) out = (a | b) & (c | d); endmodule ================================================ FILE: tests/chapter-9/9.4.2.3--event_conditional.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_conditional :description: event conditional :tags: 9.4.2.3 */ module block_tb (); wire clk = 0; wire en = 0; wire a = 0; reg y; always @(posedge clk iff en == 1) y <= a; endmodule ================================================ FILE: tests/chapter-9/9.4.2.4--event_sequence.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_sequence :description: sequence event test :tags: 9.4.2.4 :type: simulation elaboration parsing :unsynthesizable: 1 */ module seq_tb (); logic a = 0; logic b = 0; logic c = 0; logic y = 0; logic clk = 0; sequence seq; @(posedge clk) a ##1 b ##1 c; endsequence initial begin fork begin @seq y = 1; $display(":assert:(True)"); end begin a = 1; #10 clk = 1; #10 clk = 0; b = 1; #10 clk = 1; #10 clk = 0; c = 1; #10 clk = 1; #10 clk = 0; end join end endmodule ================================================ FILE: tests/chapter-9/9.4.3--event_sequence_controls.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_sequence_controls :description: event sequence :tags: 9.4.3 :unsynthesizable: 1 */ module block_tb (); reg a = 0; wire b = 1; reg enable = 0; initial begin #10 enable = 1; end initial begin wait (enable) #10 a = b; end endmodule ================================================ FILE: tests/chapter-9/9.4.5--event_blocking_assignment_delay.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_blocking_assignment_delay :description: event blk assignment delay :tags: 9.4.5 */ module block_tb (); reg a = 0; reg b = 1; initial begin a = #10 b; end endmodule ================================================ FILE: tests/chapter-9/9.4.5--event_nonblocking_assignment_delay.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_nonblocking_assignment_delay :description: event non blk assignment delay :tags: 9.4.5 */ module block_tb (); reg a = 0; reg b = 1; initial begin a <= #10 b; end endmodule ================================================ FILE: tests/chapter-9/9.4.5--event_nonblocking_assignment_event.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_nonblocking_assignment_event :description: event non blk assignment event :tags: 9.4.5 :unsynthesizable: 1 */ module block_tb (); reg a = 0; reg b = 1; wire clk = 0; initial begin a = @(posedge clk) b; end endmodule ================================================ FILE: tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_nonblocking_assignment_repeat :description: event non blk assignment repeat :tags: 9.4.5 :unsynthesizable: 1 */ module block_tb (); reg a = 0; reg b = 1; wire clk = 0; initial begin a = repeat(3) @(posedge clk) b; end endmodule ================================================ FILE: tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_nonblocking_assignment_repeat_int :description: event non blk assignment repeat :tags: 9.4.5 :unsynthesizable: 1 */ module block_tb (); reg a = 0; reg b = 1; wire clk = 0; int i = 3; initial begin a = repeat(i) @(posedge clk) b; end endmodule ================================================ FILE: tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int_neg.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_nonblocking_assignment_repeat_int_neg :description: event non blk assignment repeat :tags: 9.4.5 :unsynthesizable: 1 */ module block_tb (); reg a = 0; reg b = 1; wire clk = 0; int i = -3; initial begin a = repeat(i) @(posedge clk) b; end endmodule ================================================ FILE: tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_neg.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: event_nonblocking_assignment_repeat_neg :description: event non blk assignment repeat :tags: 9.4.5 :unsynthesizable: 1 */ module block_tb (); reg a = 0; reg b = 1; wire clk = 0; initial begin a = repeat(-3) @(posedge clk) b; end endmodule ================================================ FILE: tests/chapter-9/9.6.1--wait_fork.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: wait_fork :description: wait fork test :tags: 9.6.1 :unsynthesizable: 1 */ module fork_tb (); reg a = 0; reg b = 0; initial begin fork begin #50 a = 1; #50 a = 0; #50 a = 1; end begin #50 b = 1; #50 b = 0; #50 b = 1; end join_none wait fork; end endmodule ================================================ FILE: tests/chapter-9/9.6.2--disable.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: disable :description: disable block :tags: 9.6.2 */ module fork_tb (); reg a = 0; reg b = 0; initial begin: block a = 1; disable block; b = 1; end endmodule ================================================ FILE: tests/chapter-9/9.6.2--disable_other.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: disable_other :description: disable other task :tags: 9.6.2 :unsynthesizable: 1 */ module fork_tb (); reg a = 0; reg b = 0; reg c = 0; initial fork begin: block #10 a = 1; #10 b = 1; end #15 disable block; join endmodule ================================================ FILE: tests/chapter-9/9.6.3--disable_fork.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: disable_fork :description: disable fork :tags: 9.6.3 :unsynthesizable: 1 */ module fork_tb (); reg a = 0; reg b = 0; reg c = 0; initial begin fork #50 a = 1; #100 b = 1; #150 c = 1; join_any disable fork; end endmodule ================================================ FILE: tests/chapter-9/9.7--process_cls_await.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: process_cls_await :description: process class await method :tags: 9.7 :unsynthesizable: 1 */ module process_tb (); task automatic test (int N); process job[] = new [N]; foreach(job[i]) fork automatic int k = i; begin job[k] = process::self(); $display("process %d", k); end join_none foreach(job[i]) wait(job[i] != null); job[1].await(); endtask initial begin test(8); end endmodule ================================================ FILE: tests/chapter-9/9.7--process_cls_kill.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: process_cls_kill :description: process class kill method :tags: 9.7 :unsynthesizable: 1 */ module process_tb (); task automatic test (int N); process job[] = new [N]; foreach(job[i]) fork automatic int k = i; begin job[k] = process::self(); $display("process %d", k); end join_none foreach(job[i]) wait(job[i] != null); job[1].await(); foreach(job[i]) if(job[i].status != process::FINISHED) job[i].kill(); endtask initial begin test(8); end endmodule ================================================ FILE: tests/chapter-9/9.7--process_cls_self.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: process_cls_self :description: process class self method :tags: 9.7 :unsynthesizable: 1 */ module process_tb (); task automatic test (int N); process job[] = new [N]; foreach(job[i]) fork automatic int k = i; begin job[k] = process::self(); $display("process %d", k); end join_none endtask initial begin test(8); end endmodule ================================================ FILE: tests/chapter-9/9.7--process_cls_suspend_resume.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: process_control :description: process control :tags: 9.7 :unsynthesizable: 1 */ module process_tb (); task automatic test (int N); process job[] = new [N]; foreach(job[i]) fork automatic int k = i; begin job[k] = process::self(); job[k].suspend(); $display("process %d", k); end join_none foreach(job[i]) wait(job[i] != null); foreach(job[i]) job[i].resume(); job[1].await(); foreach(job[i]) if(job[i].status != process::FINISHED) job[i].kill(); endtask initial begin test(8); end endmodule ================================================ FILE: tests/generic/class/class_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_0 :description: Test :tags: 6.15 8.3 */ class semicolon_classy; ; ;;; ; ; ;endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_1 :description: Test :tags: 6.15 8.3 */ class Foo; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_11.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_11 :description: Test :tags: 6.15 8.3 */ class Foo #(int N, int P); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_12.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_12 :description: Test :tags: 6.15 8.3 */ class Bar #(int X=0, int Y=1, int Z=2); endclass localparam x=3, y=4, z=5; class Foo #(int N=1, int P=2) extends Bar #(x,y,z); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_13.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_13 :description: Test :tags: 6.15 8.3 */ class Bar #(int X=0, int Y=1, int Z=2); endclass localparam x=3, y=4, z=5; class Foo #(int W=8, type Int=int) extends Bar #(x,y,z); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_17.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_17 :description: Test :tags: 6.15 8.3 */ class Foo #(type IFType=virtual x_if); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_18.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_18 :description: Test :tags: 6.15 8.3 */ class Foo #(type IFType=virtual interface x_if); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_19.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_19 :description: Test :tags: 6.15 8.3 */ package Package; class Bar #(int X=0, int Y=1, int Z=2); endclass endpackage localparam x=3, y=4, z=5; class Foo extends Package::Bar #(x,y,z); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_21.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_21 :description: Test :tags: 6.15 8.3 */ package Package; class Bar #(int X=0, int Y=1, int Z=2); endclass endpackage localparam x=3, y=4, z=5; class Foo extends Package::Bar #(x,y,z); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_25.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_25 :description: Test :tags: 6.15 8.3 */ package Package; interface class Bar; endclass endpackage class Foo implements Package::Bar; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_26.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_26 :description: Test :tags: 6.15 8.3 */ interface class Bar #(parameter N); endclass parameter int N = 1; class Foo implements Bar#(N); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_27.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_27 :description: Test :tags: 6.15 8.3 */ package Package; interface class Bar #(parameter A, B); endclass endpackage class Foo implements Package::Bar#(1, 2); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_28.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_28 :description: Test :tags: 6.15 8.3 */ class Base; endclass interface class Bar; endclass class Foo extends Base implements Bar; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_29.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_29 :description: Test :tags: 6.15 8.3 */ package Pkg; interface class Bar; endclass endpackage class Base; endclass interface class Baz; endclass class Foo extends Base implements Pkg::Bar, Baz; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_30.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_30 :description: Test :tags: 6.15 8.3 :unsynthesizable: 1 */ class Foo; integer size; function new (integer size); begin this.size = size; end endfunction task print(); begin $write("Hello, world!"); end endtask endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_4 :description: Test :tags: 6.15 8.3 */ virtual class Foo; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_48.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_48 :description: Test :tags: 6.15 8.3 */ class pp_as_class_item; `undef EVIL_MACRO endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_49.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_49 :description: Test :tags: 6.15 8.3 */ package glb; localparam int arr[3] = '{1,2,3}; endpackage function int f(int a); return a; endfunction class params_as_class_item; parameter N = 2; parameter reg P = '1; localparam M = f(glb::arr[N]) + 1; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_51.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_51 :description: Test :tags: 6.15 8.3 */ class how_wide; localparam Max_int = {$bits(int) - 1{1'b1}}; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_52.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_52 :description: Test :tags: 6.15 8.3 :unsynthesizable: 1 */ class uvm_sequence_item; endclass class how_wide #(type DT=int) extends uvm_sequence_item; localparam Max_int = {$bits(DT) - 1{1'b1}}; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_53.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_53 :description: Test :tags: 6.15 8.3 */ package mypkg; typedef int GlueType; class ModuleType #(parameter A); endclass endpackage typedef int BrickType; typedef int Ctype1; typedef int Ctype2; parameter int N = 1; parameter int M = 2; class param_types_as_class_item; parameter type AT = int; parameter type BT = BrickType; parameter type CT1 = Ctype1, CT2 = Ctype2; localparam type GT = mypkg::GlueType, GT2 = int; localparam type HT1 = int, HT2 = mypkg::ModuleType#(N+M); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_54.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_54 :description: Test :tags: 6.15 8.3 :unsynthesizable: 1 */ class event_calendar; event birthday; event first_date, anniversary; event revolution[4:0], independence[2:0]; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_55.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_55 :description: Test :tags: 6.15 8.3 :unsynthesizable: 1 */ class Packet; endclass class Driver; Packet pNP [*]; Packet pNP1 [* ]; Packet pNP2 [ *]; Packet pNP3 [ * ]; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_56.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_56 :description: Test :tags: 6.15 8.3 */ typedef int data_type_or_module_type; class Driver; data_type_or_module_type foo1; data_type_or_module_type foo2 = 1'b1; data_type_or_module_type foo3, foo4; data_type_or_module_type foo5 = 5, foo6 = 6; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_57.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_57 :description: Test :tags: 6.15 8.3 */ typedef int data_type_or_module_type; class fields_with_modifiers; const data_type_or_module_type foo1 = 4'hf; static data_type_or_module_type foo3, foo4; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_58.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_58 :description: Test :tags: 6.15 8.3 */ typedef int data_type_or_module_type; class fields_with_modifiers; const static data_type_or_module_type foo1 = 4'hf; static const data_type_or_module_type foo3 = 1, foo4 = 2; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_59.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_59 :description: Test :tags: 6.15 8.3 */ class pp_class; `ifdef DEBUGGER `endif endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_6.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_6 :description: Test :tags: 6.15 8.3 */ class Bar; endclass class Foo extends Bar; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_60.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_60 :description: Test :tags: 6.15 8.3 */ class pp_class; `ifdef DEBUGGER `ifdef VERBOSE `endif `endif endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_61.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_61 :description: Test :tags: 6.15 8.3 */ class pp_class; `ifndef DEBUGGER `endif endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_62.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_62 :description: Test :tags: 6.15 8.3 */ class pp_class; int num_packets; `ifdef DEBUGGER `endif int router_size; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_63.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_63 :description: Test :tags: 6.15 8.3 */ class pp_class; int num_packets; `ifdef DEBUGGER string source_name; `endif int router_size; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_64.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_64 :description: Test :tags: 6.15 8.3 */ class pp_class; int num_packets; `ifdef DEBUGGER string source_name; string dest_name; `endif int router_size; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_65.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_65 :description: Test :tags: 6.15 8.3 */ class pp_class; int num_packets; `ifdef DEBUGGER string source_name; string dest_name; `else `endif int router_size; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_66.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_66 :description: Test :tags: 6.15 8.3 */ class pp_class; int num_packets; `ifdef DEBUGGER string source_name; string dest_name; `elsif LAZY `endif int router_size; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_67.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_67 :description: Test :tags: 6.15 8.3 */ class pp_class; int num_packets; `ifdef DEBUGGER `elsif LAZY string source_name; string dest_name; `endif int router_size; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_68.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_68 :description: Test :tags: 6.15 8.3 */ class pp_class; int num_packets; `ifdef DEBUGGER `elsif BORED string source_name; string dest_name; `elsif LAZY `endif int router_size; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_69.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_69 :description: Test :tags: 6.15 8.3 */ class pp_class; int num_packets; `ifdef DEBUGGER `elsif BORED `else string source_name; string dest_name; `endif int router_size; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_7.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_7 :description: Test :tags: 6.15 8.3 */ package Package; class Bar; endclass endpackage class Foo extends Package::Bar; endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_8.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_8 :description: Test :tags: 6.15 8.3 */ class Bar #(int X=0, int Y=1, int Z=2); endclass localparam x=3, y=4, z=5; class Foo extends Bar #(x,y,z); endclass module test; endmodule ================================================ FILE: tests/generic/class/class_test_9.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_test_9 :description: Test :tags: 6.15 8.3 */ class Foo #(int N); endclass module test; endmodule ================================================ FILE: tests/generic/desc/desc_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_0 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef DEBUGGER `endif ================================================ FILE: tests/generic/desc/desc_test_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_1 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef DEBUGGER `ifdef VERBOSE `else `endif `endif ================================================ FILE: tests/generic/desc/desc_test_10.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_10 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef FPGA `ifndef DEBUGGER interface myinterface; endinterface `endif `endif ================================================ FILE: tests/generic/desc/desc_test_15.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_15 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef ASIC module module_asic; endmodule `else // ASIC module module_fpga; endmodule `endif // ASIC ================================================ FILE: tests/generic/desc/desc_test_16.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_16 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef ASIC module module_asic; endmodule `elsif FPGA // ASIC module module_fpga; endmodule `endif // ASIC ================================================ FILE: tests/generic/desc/desc_test_17.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_17 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef ASIC_OR_FPGA module module_asic; endmodule module module_fpga; endmodule `else `endif ================================================ FILE: tests/generic/desc/desc_test_18.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_18 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifndef ASIC_OR_FPGA `else module module_asic; endmodule module module_fpga; endmodule `endif ================================================ FILE: tests/generic/desc/desc_test_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_2 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifndef DEBUGGER `endif ================================================ FILE: tests/generic/desc/desc_test_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_3 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef DEBUGGER `else `endif ================================================ FILE: tests/generic/desc/desc_test_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_4 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef DEBUGGER `elsif BORED `else `endif ================================================ FILE: tests/generic/desc/desc_test_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_5 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef DEBUGGER `elsif BORED `elsif MORE_BORED `else `endif ================================================ FILE: tests/generic/desc/desc_test_6.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_6 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef DEBUGGER module mymod; endmodule `endif ================================================ FILE: tests/generic/desc/desc_test_7.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_7 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef DEBUGGER module mymod; endmodule module mymod_different; endmodule `endif ================================================ FILE: tests/generic/desc/desc_test_8.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_8 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef DEBUGGER package mypkg; endpackage `endif ================================================ FILE: tests/generic/desc/desc_test_9.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: desc_test_9 :description: Test :type: preprocessing :tags: 5.6.4 */ `ifdef FPGA `ifdef DEBUGGER module mymod; endmodule `endif `endif ================================================ FILE: tests/generic/empty/empty_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: empty_test_0 :description: Test :type: preprocessing :tags: 5.3 5.4 */ ================================================ FILE: tests/generic/empty/empty_test_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: empty_test_1 :description: Test :type: preprocessing :tags: 5.3 5.4 */ ================================================ FILE: tests/generic/empty/empty_test_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: empty_test_2 :description: Test :type: preprocessing :tags: 5.3 5.4 */ ================================================ FILE: tests/generic/empty/empty_test_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: empty_test_3 :description: Test :type: preprocessing :tags: 5.3 5.4 */ ================================================ FILE: tests/generic/empty/empty_test_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: empty_test_4 :description: Test :type: preprocessing :tags: 5.3 5.4 */ // comment ================================================ FILE: tests/generic/empty/empty_test_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: empty_test_5 :description: Test :type: preprocessing :tags: 5.3 5.4 */ /* comment */ ================================================ FILE: tests/generic/iface/iface_class_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: iface_class_test_0 :description: Test :tags: 8.3 8.26 */ interface class base_ic; endclass module test; endmodule ================================================ FILE: tests/generic/iface/iface_class_test_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: iface_class_test_1 :description: Test :tags: 8.3 8.26 */ interface class base_ic; endclass : base_ic module test; endmodule ================================================ FILE: tests/generic/iface/iface_class_test_10.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: iface_class_test_10 :description: Test :tags: 8.3 8.26 */ interface class base_ic; pure virtual function void pure_task1; pure virtual function string concatenator(string arg); endclass module test; endmodule ================================================ FILE: tests/generic/iface/iface_class_test_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: iface_class_test_2 :description: Test :tags: 8.3 8.26 */ interface class base_ic #(int N = 8, type T = string); endclass module test; endmodule ================================================ FILE: tests/generic/iface/iface_class_test_9.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: iface_class_test_9 :description: Test :tags: 8.3 8.26 */ typedef int arg_type; interface class base_ic; pure virtual task pure_task1; pure virtual task pure_task2(arg_type arg); endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_0 :description: Test :tags: 8.3 */ class myclass; task subtask; endtask endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_10.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_10 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class outerclass; class innerclass; class reallyinnerclass; task subtask; endtask endclass endclass endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_11.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_11 :description: Test :tags: 8.3 */ class myclass; int buzz_count; endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_12.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_12 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class semaphore; local chandle p_handle; endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_14.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_14 :description: Test :tags: 8.3 */ class myclass; function integer subroutine; input a; subroutine = a+42; endfunction endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_15.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_15 :description: Test :tags: 8.3 */ class myclass; extern function void subroutine; endclass function void myclass::subroutine; endfunction module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_18.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_18 :description: Test :tags: 8.3 */ class myclass; typedef logic bool; extern function void subroutine(input bool x); endclass function void myclass::subroutine(input bool x); endfunction module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_19.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_19 :description: Test :tags: 8.3 */ class myclass; typedef logic bool; localparam int N = 2; extern function void subr(bool x[N]); endclass function void myclass::subr(bool x[N]); endfunction module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_2 :description: Test :tags: 8.3 */ class myclass; extern task subtask(int arg); endclass task myclass::subtask(int arg); endtask module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_25.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_25 :description: Test :tags: 8.3 */ class myclass; extern virtual function integer subroutine; endclass function integer myclass::subroutine; endfunction module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_26.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_26 :description: Test :tags: 8.3 */ virtual class myclass; pure virtual function integer subroutine; pure virtual function integer compute(int a, bit b); endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_27.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_27 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class report_server; endclass typedef int uvm_phase; class myclass; virtual function void starter(uvm_phase phase); report_server new_server = new; endfunction : starter endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_3 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class myclass; extern task subtask(int arg); endclass task myclass::subtask(int arg); endtask module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_31.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_31 :description: Test :tags: 8.3 */ class myclass; int dout; int n_bits; function void shifter; for (int shft_idx=0, bit c=1'b1; shft_idx < n_bits; shft_idx++) begin dout = {dout} << 1; end endfunction endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_32.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_32 :description: Test :tags: 8.3 */ class myclass; int dout; int n_bits; function void shifter; for (var int shft_idx=1, bit c=1'b0; shft_idx < n_bits; shft_idx++) begin dout = {dout} << 1; end endfunction endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_39.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_39 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class constructible; function new; endfunction endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_4 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class myclass; extern virtual task subtask(int arg); endclass task myclass::subtask(int arg); endtask module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_40.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_40 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class constructible; function new (); endfunction endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_41.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_41 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class constructible; function new (); endfunction : new endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_5 :description: Test :should_fail_because: pure virtual methods can only be declared in virtual classes :tags: 8.3 :type: elaboration :unsynthesizable: 1 */ class myclass; pure virtual task pure_task1; pure virtual task pure_task2(int arg); endclass module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_6.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_6 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class myclass; extern protected task subtask(int arg); endclass task myclass::subtask(int arg); endtask module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_7.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_7 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class myclass; extern virtual protected task subtask(int arg); endclass task myclass::subtask(int arg); endtask module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_8.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_8 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class myclass; extern protected virtual task subtask(int arg); endclass task myclass::subtask(int arg); endtask module test; endmodule ================================================ FILE: tests/generic/member/class_member_test_9.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: class_member_test_9 :description: Test :tags: 8.3 :unsynthesizable: 1 */ class myclass; typedef int arg_type; extern local static task subtask(arg_type arg); endclass task myclass::subtask(arg_type arg); endtask module test; endmodule ================================================ FILE: tests/generic/number/number_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_0 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter foo = 0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_1 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_10.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_10 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 1'bx; module test; endmodule ================================================ FILE: tests/generic/number/number_test_11.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_11 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 1 'b x; module test; endmodule ================================================ FILE: tests/generic/number/number_test_12.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_12 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 1'bz; module test; endmodule ================================================ FILE: tests/generic/number/number_test_13.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_13 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 4'bxxxx; module test; endmodule ================================================ FILE: tests/generic/number/number_test_14.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_14 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 4'bzzzz; module test; endmodule ================================================ FILE: tests/generic/number/number_test_15.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_15 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 4'sb1111; module test; endmodule ================================================ FILE: tests/generic/number/number_test_16.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_16 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 4'Sb0000; module test; endmodule ================================================ FILE: tests/generic/number/number_test_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_2 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = '0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_24.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_24 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 'd0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_25.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_25 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 'd 0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_26.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_26 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'd1; module test; endmodule ================================================ FILE: tests/generic/number/number_test_27.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_27 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'D1; module test; endmodule ================================================ FILE: tests/generic/number/number_test_28.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_28 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32 'd 1; module test; endmodule ================================================ FILE: tests/generic/number/number_test_29.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_29 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'sd1; module test; endmodule ================================================ FILE: tests/generic/number/number_test_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_3 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = '1; module test; endmodule ================================================ FILE: tests/generic/number/number_test_30.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_30 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'Sd1; module test; endmodule ================================================ FILE: tests/generic/number/number_test_31.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_31 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'dx; module test; endmodule ================================================ FILE: tests/generic/number/number_test_32.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_32 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'dx_; module test; endmodule ================================================ FILE: tests/generic/number/number_test_33.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_33 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'dx__; module test; endmodule ================================================ FILE: tests/generic/number/number_test_34.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_34 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'dX; module test; endmodule ================================================ FILE: tests/generic/number/number_test_35.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_35 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'dz; module test; endmodule ================================================ FILE: tests/generic/number/number_test_36.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_36 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'dZ; module test; endmodule ================================================ FILE: tests/generic/number/number_test_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_4 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 'b0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_42.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_42 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 'o0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_43.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_43 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 'o 0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_44.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_44 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'o7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_45.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_45 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'o7_7_7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_46.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_46 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'O7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_47.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_47 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32 'o 7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_48.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_48 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'so7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_49.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_49 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'So7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_5 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 'b 0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_50.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_50 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'oxxx; module test; endmodule ================================================ FILE: tests/generic/number/number_test_51.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_51 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'oXX; module test; endmodule ================================================ FILE: tests/generic/number/number_test_52.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_52 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'ozz; module test; endmodule ================================================ FILE: tests/generic/number/number_test_53.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_53 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'oZZ; module test; endmodule ================================================ FILE: tests/generic/number/number_test_59.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_59 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 'h0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_6.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_6 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 1'b0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_60.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_60 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 'h 0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_61.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_61 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'h7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_62.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_62 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'H7fFF; module test; endmodule ================================================ FILE: tests/generic/number/number_test_64.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_64 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'hdeadbeef; module test; endmodule ================================================ FILE: tests/generic/number/number_test_65.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_65 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'hFEEDFACE; module test; endmodule ================================================ FILE: tests/generic/number/number_test_66.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_66 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32 'h 7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_67.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_67 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'sh7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_68.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_68 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'Sh7; module test; endmodule ================================================ FILE: tests/generic/number/number_test_69.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_69 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'hxxx; module test; endmodule ================================================ FILE: tests/generic/number/number_test_7.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_7 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 1'B0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_70.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_70 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'hXX; module test; endmodule ================================================ FILE: tests/generic/number/number_test_71.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_71 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'hzz; module test; endmodule ================================================ FILE: tests/generic/number/number_test_72.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_72 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 32'hZZ; module test; endmodule ================================================ FILE: tests/generic/number/number_test_8.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_8 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 1 'b 0; module test; endmodule ================================================ FILE: tests/generic/number/number_test_9.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: number_test_9 :description: Test :tags: 5.6.4 5.7.1 5.7.2 */ parameter int foo = 1'b1; module test; endmodule ================================================ FILE: tests/generic/preproc/preproc_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: preproc_test_0 :description: Test :tags: 5.6.4 :type: preprocessing */ `define TRUTH module test; endmodule ================================================ FILE: tests/generic/preproc/preproc_test_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: preproc_test_2 :description: Test :tags: 5.6.4 :type: preprocessing */ `include "preproc_test_2.svh" `ifndef SUCCESS "Didn't successfully include preproc_test_2.svh!" `endif `ifndef SANITY `define SANITY `endif module test; endmodule ================================================ FILE: tests/generic/preproc/preproc_test_2.svh ================================================ // This file exists for preproc_test_2.sv `define SUCCESS ================================================ FILE: tests/generic/preproc/preproc_test_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: preproc_test_4 :description: Test :tags: 5.6.4 :type: preprocessing */ `ifdef INSANITY `define INSANITY // comment `else `define SANITY 1 `endif module test; endmodule ================================================ FILE: tests/generic/preproc/preproc_test_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: preproc_test_5 :description: Test :tags: 5.6.4 :type: preprocessing */ `define INCEPTION(a, b, c) module test; endmodule ================================================ FILE: tests/generic/preproc/preproc_test_6.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: preproc_test_6 :description: Test :tags: 5.6.4 :type: preprocessing */ `define INCEPTION(a, b, c) (a*b-c) module test; endmodule ================================================ FILE: tests/generic/preproc/preproc_test_7.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: preproc_test_7 :description: Test :tags: 5.6.4 :type: preprocessing */ `define INCEPTION(a, b, c) \ (a*b-c) module test; endmodule ================================================ FILE: tests/generic/preproc/preproc_test_8.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: preproc_test_8 :description: Test :tags: 5.6.4 :type: preprocessing */ `define INCEPTION(xyz) \ `define DEEPER (xyz) module test; endmodule ================================================ FILE: tests/generic/struct/struct_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: struct_test_0 :description: Test :tags: 7.2 */ typedef struct mystruct_fwd; typedef struct { logic a; logic b; } mystruct_fwd; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_0 :description: Test :tags: 6.18 */ typedef i_am_a_type_really; typedef int i_am_a_type_really; // Multiple forward typedefs are allowed. typedef i_am_a_type_really; typedef i_am_a_type_really; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_1.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_1 :description: Test :tags: 6.18 */ typedef reg[3:0] quartet; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_10.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_10 :description: Test :tags: 6.18 */ typedef bit data_t; typedef data_t my_array_t [ * ]; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_11.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_11 :description: Test :tags: 6.18 */ typedef bit data_t; typedef data_t my_array_t [bit]; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_12.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_12 :description: Test :tags: 6.18 */ typedef bit data_t; typedef data_t my_array_t [bit[31:0]]; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_13.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_13 :description: Test :tags: 6.18 */ typedef bit data_t; parameter k = 6; parameter j = 5; parameter l = 2; typedef data_t my_ar_t [bit[31:0][k:0]][bit[j:0][l:0]]; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_14.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_14 :description: Test :tags: 6.18 */ package some_package; typedef bit some_type; endpackage typedef some_package::some_type myalias; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_16.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_16 :description: Test :tags: 6.18 */ typedef struct packed { logic [4:0] some_member; } mystruct_t; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_18.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_18 :description: Test :tags: 6.18 */ parameter K = 9; typedef struct { rand bit i; randc integer b[K:0]; } randstruct; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_19.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_19 :description: Test :tags: 6.18 */ typedef enum { Global = 2, Local = 3 } myenum_fwd; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_2.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_2 :description: Test :tags: 6.18 */ typedef reg quartet[3:0]; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_20.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_20 :description: Test :tags: 6.18 */ typedef enum logic[3:0] { Global = 4'h2, Local = 4'h3 } myenum_fwd; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_21.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_21 :description: Test :tags: 6.18 */ typedef enum bit[3:0] { Global = 4'h2, Local = 4'h3 } myenum_fwd; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_22.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_22 :description: Test :tags: 6.18 */ typedef enum uvec8_t; typedef enum { Global = 2, Local = 3 } uvec8_t; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_23.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_23 :description: Test :tags: 6.18 */ typedef bit[3:0] num_t; typedef enum num_t { Global = 4'h2, Local = 4'h3 } myenum_fwd; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_24.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_24 :description: Test :tags: 6.18 */ typedef struct { int sample; int tile; } tuple_t; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_25.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_25 :description: Test :tags: 6.18 */ parameter A = 5; parameter D = 32; parameter E = 7; parameter M = 4; typedef struct packed { reg [A-1:0] addr; reg [D-1:0] data; `ifndef FOO reg [E-1:0] ecc; `endif // `ifndef FOO reg [M-1:0] mask; reg parity; } req_t; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_25__bad.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_25__bad :description: Test :should_fail_because: Using undefined parameters :tags: 6.18 :type: simulation elaboration */ // A/D/E/M are not defined, so bad test. typedef struct packed { reg [A-1:0] addr; reg [D-1:0] data; `ifndef FOO reg [E-1:0] ecc; `endif // `ifndef FOO reg [M-1:0] mask; reg parity; } req_t; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_26.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_26 :description: Test :tags: 6.18 */ typedef enum { `ifdef TWO Global = 2, `else Global = 1, `endif Local = 3 } myenum_fwd; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_27.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_27 :description: Test :tags: 6.18 */ typedef enum { Global = 2, `ifdef TWO Local = 2 `else Local = 1 `endif } myenum_fwd; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_28__bad.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_28__bad :description: Test :should_fail_because: missing forward typedef declaration, type_identifier does not resolve to a data type. :tags: 6.18 :type: simulation elaboration */ // 6.18 says: // The actual data type definition of a forward typedef declaration shall // be resolved within the same localscope or generate block. It shall be an // error if the type_identifier does not resolve to a data type. typedef missing_forward_typedef; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_3.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_3 :description: Test :tags: 6.18 */ typedef reg[1:0] quartet[1:0]; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_4.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_4 :description: Test :tags: 6.18 */ typedef enum { RED, GREEN, BLUE } colors; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_5.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_5 :description: Test :tags: 6.18 */ typedef union { int i; bit b; } bint; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_6.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_6 :description: Test :tags: 6.18 */ typedef struct { int i; bit b; } mystruct; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_7.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_7 :description: Test :tags: 6.18 */ typedef struct { int i, j, k; bit b, c, d; } mystruct; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_8.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_8 :description: Test :tags: 6.18 */ typedef bit some_other_type; typedef some_other_type myalias; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_8__bad.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_8__bad :description: Test :should_fail_because: defining a type using an undefined type :tags: 6.18 :type: simulation elaboration */ // some_other_type is not defined typedef some_other_type myalias; module test; endmodule ================================================ FILE: tests/generic/typedef/typedef_test_9.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: typedef_test_9 :description: Test :tags: 6.18 */ parameter j = 3; parameter k = 2; typedef bit data_t; typedef data_t my_array_t [k:0][j:0]; module test; endmodule ================================================ FILE: tests/generic/union/union_test_0.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: union_test_0 :description: Test :tags: 7.3 */ typedef union myunion_fwd; typedef union { logic a; logic b; } myunion_fwd; module test; endmodule ================================================ FILE: tests/sanity.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: sanity :description: A simple module that should fail during parsing :should_fail_because: syntax error, fails during parsing :tags: sanity */ module sanity_tb ( clk, out ); input clk; output out; syntaxerror wire clk; reg out; reg [31:0] sum = 0; always @(posedge clk) begin if(sum >= 21) begin out <= 1; sum <= 0; end else begin out <= 0; sum <= sum + 1; end end endmodule ================================================ FILE: tests/testbenches/uvm_agent_active.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_agent_active :description: uvm active agent (agent + monitor + driver + sequencer) test :tags: uvm uvm-agents :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" `define PATTERN 2 interface input_if(input clk); logic [7:0] data; modport port(input clk, data); endinterface interface output_if(input clk); logic [7:0] data; modport port(input clk, output data); endinterface module dut(input_if.port in, output_if.port out); always @(posedge in.clk) out.data <= in.data; endmodule class packet_in extends uvm_sequence_item; logic [7:0] data; `uvm_object_utils_begin(packet_in) `uvm_field_int(data, UVM_ALL_ON|UVM_HEX) `uvm_object_utils_end function new(string name="packet_in"); super.new(name); endfunction: new endclass class monitor extends uvm_monitor; `uvm_component_utils(monitor) virtual input_if vif; packet_in packet; uvm_analysis_port #(packet_in) item_collected_port; function new(string name, uvm_component parent); super.new(name, parent); item_collected_port = new ("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); packet = packet_in::type_id::create("packet", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( "env", "input_if", vif)); endfunction virtual task run_phase(uvm_phase phase); phase.raise_objection(this); fork collect_transactions(phase); join phase.drop_objection(this); endtask virtual task collect_transactions(uvm_phase phase); packet.data = vif.data; item_collected_port.write(packet); endtask endclass class sequence_in extends uvm_sequence #(packet_in); `uvm_object_utils(sequence_in) function new(string name="sequence_in"); super.new(name); endfunction: new task body; packet_in packet; packet = packet_in::type_id::create("packet"); start_item(packet); packet.data = `PATTERN; finish_item(packet); endtask: body endclass class sequencer extends uvm_sequencer #(packet_in); `uvm_component_utils(sequencer) function new (string name = "sequencer", uvm_component parent = null); super.new(name, parent); endfunction endclass class driver extends uvm_driver #(packet_in); `uvm_component_utils(driver) virtual input_if vif; function new(string name = "driver", uvm_component parent = null); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction virtual function void connect_phase(uvm_phase phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( "env", "input_if", vif)); endfunction virtual task run_phase(uvm_phase phase); phase.raise_objection(this); fork get_and_drive(phase); join phase.drop_objection(this); endtask virtual protected task get_and_drive(uvm_phase phase); seq_item_port.get(req); drive_transfer(req); endtask virtual protected task drive_transfer(packet_in packet); vif.data <= packet.data; @(posedge vif.clk); endtask endclass class agent_active extends uvm_agent; sequencer sqr; driver drv; monitor mon; uvm_analysis_port #(packet_in) item_collected_port; `uvm_component_utils(agent_active) function new(string name = "agent_active", uvm_component parent = null); super.new(name, parent); item_collected_port = new("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); mon = monitor::type_id::create("mon", this); sqr = sequencer::type_id::create("sqr", this); drv = driver::type_id::create("drv", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); mon.item_collected_port.connect(item_collected_port); drv.seq_item_port.connect(sqr.seq_item_export); endfunction endclass class env extends uvm_env; agent_active agent; virtual output_if vif; static int data; sequence_in seq; `uvm_component_utils(env) function new(string name, uvm_component parent = null); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); agent = agent_active::type_id::create("agent", this); seq = sequence_in::type_id::create("seq", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual output_if)::read_by_name( get_full_name(), "output_if", vif)); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); seq.start(agent.sqr); repeat(3) @(posedge vif.clk); phase.drop_objection(this); endtask virtual function void report_phase(uvm_phase phase); super.report_phase(phase); data <= vif.data; if(data == `PATTERN) begin `uvm_info("RESULT", $sformatf("Match %d == %d", data, `PATTERN), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("Mismatch %d != %d", data, `PATTERN)); end endfunction endclass module top; logic clk; env environment; input_if in(clk); output_if out(clk); dut d(in, out); always #5 clk = !clk; initial begin environment = new("env"); uvm_resource_db#(virtual input_if)::set("env", "input_if", in); uvm_resource_db#(virtual output_if)::set("env", "output_if", out); clk = 0; run_test(); end endmodule ================================================ FILE: tests/testbenches/uvm_agent_env.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_agent_env :description: uvm agent + env test :tags: uvm uvm-agents :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" `define PATTERN 2 interface input_if(input clk); logic [7:0] data; modport port(input clk, data); endinterface interface output_if(input clk); logic [7:0] data; modport port(input clk, output data); endinterface module dut(input_if.port in, output_if.port out); always @(posedge in.clk) out.data <= in.data; endmodule class agent extends uvm_agent; virtual output_if out_vif; virtual input_if in_vif; `uvm_component_utils(agent) function new(string name = "agent", uvm_component parent = null); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( "env", "input_if", in_vif)); assert(uvm_resource_db#(virtual output_if)::read_by_name( "env", "output_if", out_vif)); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info("RESULT", $sformatf("Writing %0d to input interface", `PATTERN), UVM_LOW); in_vif.data <= `PATTERN; repeat(2) @(posedge out_vif.clk); if(out_vif.data == `PATTERN) begin `uvm_info("RESULT", $sformatf("Match %d == %d", out_vif.data, `PATTERN), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("Mismatch %d != %d", out_vif.data, `PATTERN)); end phase.drop_objection(this); endtask endclass class env extends uvm_env; agent ag; `uvm_component_utils(env) function new(string name, uvm_component parent = null); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); ag = agent::type_id::create("ag", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); endfunction virtual function void report_phase(uvm_phase phase); super.report_phase(phase); endfunction endclass module top; logic clk; env environment; input_if in(clk); output_if out(clk); dut d(in, out); always #5 clk = !clk; initial begin environment = new("env"); uvm_resource_db#(virtual input_if)::set("env", "input_if", in); uvm_resource_db#(virtual output_if)::set("env", "output_if", out); clk = 0; run_test(); end endmodule ================================================ FILE: tests/testbenches/uvm_agent_passive.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_agent_passive :description: passive uvm_agent (agent + monitor + env) test :tags: uvm uvm-agents :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" `define PATTERN 2 interface input_if(input clk); logic [7:0] data; modport port(input clk, data); endinterface interface output_if(input clk); logic [7:0] data; modport port(input clk, output data); endinterface module dut(input_if.port in, output_if.port out); always @(posedge in.clk) out.data <= in.data; endmodule class packet_out extends uvm_sequence_item; logic [7:0] data; `uvm_object_utils_begin(packet_out) `uvm_field_int(data, UVM_ALL_ON|UVM_HEX) `uvm_object_utils_end function new(string name="packet_out"); super.new(name); endfunction: new endclass class monitor extends uvm_monitor; `uvm_component_utils(monitor) virtual output_if vif; packet_out packet; uvm_analysis_port #(packet_out) item_collected_port; function new(string name, uvm_component parent); super.new(name, parent); item_collected_port = new ("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); packet = packet_out::type_id::create("packet", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual output_if)::read_by_name( "env", "output_if", vif)); endfunction virtual task run_phase(uvm_phase phase); super.run_phase(phase); fork collect_transactions(phase); join endtask virtual task collect_transactions(uvm_phase phase); forever begin repeat(2) @(posedge vif.clk); packet.data = vif.data; item_collected_port.write(packet); if(packet.data == `PATTERN) begin `uvm_info("RESULT", $sformatf("Match %d == %d", packet.data, `PATTERN), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("Mismatch %d != %d", packet.data, `PATTERN)); end end endtask endclass class agent_passive extends uvm_agent; monitor mon; uvm_analysis_port #(packet_out) item_collected_port; `uvm_component_utils(agent_passive) function new(string name = "agent_passive", uvm_component parent = null); super.new(name, parent); item_collected_port = new("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); mon = monitor::type_id::create("mon", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); mon.item_collected_port.connect(item_collected_port); endfunction endclass class env extends uvm_env; agent_passive agent; virtual input_if vif; `uvm_component_utils(env) function new(string name, uvm_component parent = null); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); agent = agent_passive::type_id::create("agent", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( get_full_name(), "input_if", vif)); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info("RESULT", $sformatf("Writing %0d to input interface", `PATTERN), UVM_LOW); vif.data <= `PATTERN; repeat(2) @(posedge vif.clk); phase.drop_objection(this); endtask virtual function void report_phase(uvm_phase phase); super.report_phase(phase); endfunction endclass module top; logic clk; env environment; input_if in(clk); output_if out(clk); dut d(in, out); always #5 clk = !clk; initial begin environment = new("env"); uvm_resource_db#(virtual input_if)::set("env", "input_if", in); uvm_resource_db#(virtual output_if)::set("env", "output_if", out); clk = 0; run_test(); end endmodule ================================================ FILE: tests/testbenches/uvm_driver_sequencer_env.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_driver_sequencer_env :description: uvm driver + sequencer + env test :tags: uvm uvm-classes :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" `define PATTERN 2 interface input_if(input clk); logic [7:0] data; modport port(input clk, data); endinterface interface output_if(input clk); logic [7:0] data; modport port(input clk, output data); endinterface module dut(input_if.port in, output_if.port out); always @(posedge in.clk) out.data <= in.data; endmodule class packet_in extends uvm_sequence_item; logic [7:0] data; `uvm_object_utils_begin(packet_in) `uvm_field_int(data, UVM_ALL_ON|UVM_HEX) `uvm_object_utils_end function new(string name="packet_in"); super.new(name); endfunction: new endclass class sequence_in extends uvm_sequence #(packet_in); `uvm_object_utils(sequence_in) function new(string name="sequence_in"); super.new(name); endfunction: new task body; packet_in packet; packet = packet_in::type_id::create("packet"); start_item(packet); packet.data = `PATTERN; finish_item(packet); endtask: body endclass class sequencer extends uvm_sequencer #(packet_in); `uvm_component_utils(sequencer) function new (string name = "sequencer", uvm_component parent = null); super.new(name, parent); endfunction endclass class driver extends uvm_driver #(packet_in); `uvm_component_utils(driver) virtual input_if vif; function new(string name = "driver", uvm_component parent = null); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction virtual function void connect_phase(uvm_phase phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( "env", "input_if", vif)); endfunction virtual task run_phase(uvm_phase phase); phase.raise_objection(this); fork get_and_drive(phase); join phase.drop_objection(this); endtask virtual protected task get_and_drive(uvm_phase phase); seq_item_port.get(req); drive_transfer(req); endtask virtual protected task drive_transfer(packet_in packet); vif.data <= packet.data; endtask endclass class env extends uvm_env; virtual output_if vif; static int data; sequence_in seq; sequencer sqr; driver drv; `uvm_component_utils(env) function new(string name, uvm_component parent = null); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); seq = sequence_in::type_id::create("seq", this); sqr = sequencer::type_id::create("sqr", this); drv = driver::type_id::create("drv", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual output_if)::read_by_name( get_full_name(), "output_if", vif)); drv.seq_item_port.connect(sqr.seq_item_export); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); seq.start(sqr); repeat(3) @(posedge vif.clk); phase.drop_objection(this); endtask virtual function void report_phase(uvm_phase phase); super.report_phase(phase); data <= vif.data; if(data == `PATTERN) begin `uvm_info("RESULT", $sformatf("Match %d == %d", data, `PATTERN), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("Mismatch %d != %d", data, `PATTERN)); end endfunction endclass module top; logic clk; env environment; input_if in(clk); output_if out(clk); dut d(in, out); always #5 clk = !clk; initial begin environment = new("env"); uvm_resource_db#(virtual input_if)::set("env", "input_if", in); uvm_resource_db#(virtual output_if)::set("env", "output_if", out); clk = 0; run_test(); end endmodule ================================================ FILE: tests/testbenches/uvm_monitor_env.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_monitor_env :description: uvm monitor + env test :tags: uvm uvm-classes :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" `define PATTERN 2 interface input_if(input clk); logic [7:0] data; modport port(input clk, data); endinterface interface output_if(input clk); logic [7:0] data; modport port(input clk, output data); endinterface module dut(input_if.port in, output_if.port out); always @(posedge in.clk) out.data <= in.data; endmodule class packet_out extends uvm_sequence_item; logic [7:0] data; `uvm_object_utils_begin(packet_out) `uvm_field_int(data, UVM_ALL_ON|UVM_HEX) `uvm_object_utils_end function new(string name="packet_out"); super.new(name); endfunction: new endclass class monitor extends uvm_monitor; `uvm_component_utils(monitor) virtual output_if vif; packet_out packet; uvm_analysis_port #(packet_out) item_collected_port; function new(string name, uvm_component parent); super.new(name, parent); item_collected_port = new ("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); packet = packet_out::type_id::create("packet", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual output_if)::read_by_name( "env", "output_if", vif)); endfunction virtual task run_phase(uvm_phase phase); super.run_phase(phase); fork collect_transactions(phase); join endtask virtual task collect_transactions(uvm_phase phase); forever begin repeat(2) @(posedge vif.clk); packet.data = vif.data; item_collected_port.write(packet); if(packet.data == `PATTERN) begin `uvm_info("RESULT", $sformatf("Match %d == %d", packet.data, `PATTERN), UVM_LOW); end else begin `uvm_error("RESULT", $sformatf("Mismatch %d != %d", packet.data, `PATTERN)); end end endtask endclass class env extends uvm_env; virtual input_if vif; monitor mon; `uvm_component_utils(env) uvm_analysis_port #(packet_out) item_collected_port; function new(string name, uvm_component parent = null); super.new(name, parent); item_collected_port = new("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); mon = monitor::type_id::create("mon", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( get_full_name(), "input_if", vif)); mon.item_collected_port.connect(item_collected_port); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info("RESULT", $sformatf("Writing %0d to input interface", `PATTERN), UVM_LOW); vif.data <= `PATTERN; repeat(2) @(posedge vif.clk); phase.drop_objection(this); endtask virtual function void report_phase(uvm_phase phase); super.report_phase(phase); endfunction endclass module top; logic clk; env environment; input_if in(clk); output_if out(clk); dut d(in, out); always #5 clk = !clk; initial begin environment = new("env"); uvm_resource_db#(virtual input_if)::set("env", "input_if", in); uvm_resource_db#(virtual output_if)::set("env", "output_if", out); clk = 0; run_test(); end endmodule ================================================ FILE: tests/testbenches/uvm_resource_db_read_by_name.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_resource_db_read_by_name :description: uvm resource_db::read_by_name test :tags: uvm :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class C; endclass class env extends uvm_env; C obj; `uvm_component_utils(env) function new(string name, uvm_component parent = null); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); if(uvm_resource_db#(C)::read_by_name( get_full_name(), "obj", obj)) begin `uvm_info("RESULT", "read_by_name successful", UVM_LOW); end else begin `uvm_error("RESULT", "read_by_name failed"); end endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); phase.drop_objection(this); endtask endclass module top; env environment; C obj; initial begin environment = new("env"); uvm_resource_db#(C)::set("env", "obj", obj); run_test(); end endmodule ================================================ FILE: tests/testbenches/uvm_scoreboard_env.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_scoreboard_env :description: uvm scoreboard + env test :tags: uvm uvm-scoreboards :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" `define PATTERN 2 interface input_if(input clk); logic [7:0] data; modport port(input clk, data); endinterface interface output_if(input clk); logic [7:0] data; modport port(input clk, output data); endinterface module dut(input_if.port in, output_if.port out); always @(posedge in.clk) out.data <= in.data; endmodule class packet_out extends uvm_sequence_item; logic [7:0] data; `uvm_object_utils_begin(packet_out) `uvm_field_int(data, UVM_ALL_ON|UVM_HEX) `uvm_object_utils_end function new(string name="packet_out"); super.new(name); endfunction: new endclass class comparator #(type T = packet_out) extends uvm_scoreboard; typedef comparator #(T) this_type; `uvm_component_param_utils(this_type) int match, mismatch; const static string type_name = "comparator #(T)"; uvm_analysis_imp #(T, this_type) from_dut; typedef uvm_built_in_converter #( T ) convert; event end_of_simulation; function new(string name, uvm_component parent); super.new(name, parent); from_dut = new("from_dut", this); match = 0; mismatch = 0; endfunction virtual function string get_type_name(); return type_name; endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); @(end_of_simulation); phase.drop_objection(this); endtask virtual function void write(T rec); if(rec.data == `PATTERN) begin `uvm_info("RESULT", $sformatf("Comparator match %d == %d", rec.data, `PATTERN), UVM_LOW); match++; end else begin `uvm_error("RESULT", $sformatf("Comparator mismatch %d != %d", rec.data, `PATTERN)); mismatch++; end -> end_of_simulation; endfunction endclass class env extends uvm_env; comparator #(packet_out) comp; virtual input_if in_vif; virtual output_if out_vif; packet_out packet; `uvm_component_utils(env) uvm_analysis_port #(packet_out) item_collected_port; function new(string name, uvm_component parent = null); super.new(name, parent); item_collected_port = new("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); comp = comparator#(packet_out)::type_id::create("comp", this); packet = packet_out::type_id::create("packet", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( get_full_name(), "input_if", in_vif)); assert(uvm_resource_db#(virtual output_if)::read_by_name( get_full_name(), "output_if", out_vif)); item_collected_port.connect(comp.from_dut); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); endfunction task run_phase(uvm_phase phase); `uvm_info("RESULT", $sformatf("Writing %0d to input interface", `PATTERN), UVM_LOW); in_vif.data <= `PATTERN; repeat(2) @(posedge out_vif.clk); packet.data = out_vif.data; item_collected_port.write(packet); endtask virtual function void report_phase(uvm_phase phase); super.report_phase(phase); endfunction endclass module top; logic clk; env environment; input_if in(clk); output_if out(clk); dut d(in, out); always #5 clk = !clk; initial begin environment = new("env"); uvm_resource_db#(virtual input_if)::set("env", "input_if", in); uvm_resource_db#(virtual output_if)::set("env", "output_if", out); clk = 0; run_test(); end endmodule ================================================ FILE: tests/testbenches/uvm_scoreboard_monitor_agent_env.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_scoreboard_monitor_agent_env :description: uvm scoreboard + monitor + agent + env test :tags: uvm uvm-scoreboards :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" `define PATTERN 2 interface input_if(input clk); logic [7:0] data; modport port(input clk, data); endinterface interface output_if(input clk); logic [7:0] data; modport port(input clk, output data); endinterface module dut(input_if.port in, output_if.port out); always @(posedge in.clk) out.data <= in.data; endmodule class packet_out extends uvm_sequence_item; logic [7:0] data; `uvm_object_utils_begin(packet_out) `uvm_field_int(data, UVM_ALL_ON|UVM_HEX) `uvm_object_utils_end function new(string name="packet_out"); super.new(name); endfunction: new endclass class monitor extends uvm_monitor; `uvm_component_utils(monitor) virtual output_if vif; packet_out packet; uvm_analysis_port #(packet_out) item_collected_port; function new(string name, uvm_component parent); super.new(name, parent); item_collected_port = new ("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); packet = packet_out::type_id::create("packet", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual output_if)::read_by_name( "env", "output_if", vif)); endfunction virtual task run_phase(uvm_phase phase); super.run_phase(phase); fork collect_transactions(phase); join endtask virtual task collect_transactions(uvm_phase phase); forever begin repeat(2) @(posedge vif.clk); packet.data = vif.data; item_collected_port.write(packet); end endtask endclass class agent_passive extends uvm_agent; monitor mon; uvm_analysis_port #(packet_out) item_collected_port; `uvm_component_utils(agent_passive) function new(string name = "agent_passive", uvm_component parent = null); super.new(name, parent); item_collected_port = new("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); mon = monitor::type_id::create("mon_out", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); mon.item_collected_port.connect(item_collected_port); endfunction endclass class comparator #(type T = packet_out) extends uvm_scoreboard; typedef comparator #(T) this_type; `uvm_component_param_utils(this_type) int match, mismatch; const static string type_name = "comparator #(T)"; uvm_analysis_imp #(T, this_type) from_dut; typedef uvm_built_in_converter #( T ) convert; event end_of_simulation; function new(string name, uvm_component parent); super.new(name, parent); from_dut = new("from_dut", this); match = 0; mismatch = 0; endfunction virtual function string get_type_name(); return type_name; endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); @(end_of_simulation); phase.drop_objection(this); endtask virtual function void write(T rec); if(rec.data == `PATTERN) begin `uvm_info("RESULT", $sformatf("Comparator match %d == %d", rec.data, `PATTERN), UVM_LOW); match++; end else begin `uvm_error("RESULT", $sformatf("Comparator mismatch %d != %d", rec.data, `PATTERN)); mismatch++; end -> end_of_simulation; endfunction endclass class env extends uvm_env; agent_passive agent; comparator #(packet_out) comp; virtual input_if vif; `uvm_component_utils(env) function new(string name, uvm_component parent = null); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); agent = agent_passive::type_id::create("agent", this); comp = comparator#(packet_out)::type_id::create("comp", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( get_full_name(), "input_if", vif)); agent.item_collected_port.connect(comp.from_dut); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); endfunction task run_phase(uvm_phase phase); `uvm_info("RESULT", $sformatf("Writing %0d to input interface", `PATTERN), UVM_LOW); vif.data <= `PATTERN; endtask virtual function void report_phase(uvm_phase phase); super.report_phase(phase); endfunction endclass module top; logic clk; env environment; input_if in(clk); output_if out(clk); dut d(in, out); always #5 clk = !clk; initial begin environment = new("env"); uvm_resource_db#(virtual input_if)::set("env", "input_if", in); uvm_resource_db#(virtual output_if)::set("env", "output_if", out); clk = 0; run_test(); end endmodule ================================================ FILE: tests/testbenches/uvm_scoreboard_monitor_env.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_scoreboard_monitor_env :description: uvm scoreboard + monitor + env test :tags: uvm uvm-scoreboards :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" `define PATTERN 2 interface input_if(input clk); logic [7:0] data; modport port(input clk, data); endinterface interface output_if(input clk); logic [7:0] data; modport port(input clk, output data); endinterface module dut(input_if.port in, output_if.port out); always @(posedge in.clk) out.data <= in.data; endmodule class packet_out extends uvm_sequence_item; logic [7:0] data; `uvm_object_utils_begin(packet_out) `uvm_field_int(data, UVM_ALL_ON|UVM_HEX) `uvm_object_utils_end function new(string name="packet_out"); super.new(name); endfunction: new endclass class monitor extends uvm_monitor; `uvm_component_utils(monitor) virtual output_if vif; packet_out packet; uvm_analysis_port #(packet_out) item_collected_port; function new(string name, uvm_component parent); super.new(name, parent); item_collected_port = new ("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); packet = packet_out::type_id::create("packet", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual output_if)::read_by_name( "env", "output_if", vif)); endfunction virtual task run_phase(uvm_phase phase); super.run_phase(phase); fork collect_transactions(phase); join endtask virtual task collect_transactions(uvm_phase phase); forever begin repeat(2) @(posedge vif.clk); packet.data = vif.data; item_collected_port.write(packet); end endtask endclass class comparator #(type T = packet_out) extends uvm_scoreboard; typedef comparator #(T) this_type; `uvm_component_param_utils(this_type) int match, mismatch; const static string type_name = "comparator #(T)"; uvm_analysis_imp #(T, this_type) from_dut; typedef uvm_built_in_converter #( T ) convert; event end_of_simulation; function new(string name, uvm_component parent); super.new(name, parent); from_dut = new("from_dut", this); match = 0; mismatch = 0; endfunction virtual function string get_type_name(); return type_name; endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); @(end_of_simulation); phase.drop_objection(this); endtask virtual function void write(T rec); if(rec.data == `PATTERN) begin `uvm_info("RESULT", $sformatf("Comparator match %d == %d", rec.data, `PATTERN), UVM_LOW); match++; end else begin `uvm_error("RESULT", $sformatf("Comparator mismatch %d != %d", rec.data, `PATTERN)); mismatch++; end -> end_of_simulation; endfunction endclass class env extends uvm_env; monitor mon; comparator #(packet_out) comp; virtual input_if vif; `uvm_component_utils(env) uvm_analysis_port #(packet_out) item_collected_port; function new(string name, uvm_component parent = null); super.new(name, parent); item_collected_port = new("item_collected_port", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); comp = comparator#(packet_out)::type_id::create("comp", this); mon = monitor::type_id::create("mon_out", this); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); assert(uvm_resource_db#(virtual input_if)::read_by_name( get_full_name(), "input_if", vif)); item_collected_port.connect(comp.from_dut); mon.item_collected_port.connect(item_collected_port); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); endfunction task run_phase(uvm_phase phase); `uvm_info("RESULT", $sformatf("Writing %0d to input interface", `PATTERN), UVM_LOW); vif.data <= `PATTERN; endtask virtual function void report_phase(uvm_phase phase); super.report_phase(phase); endfunction endclass module top; logic clk; env environment; input_if in(clk); output_if out(clk); dut d(in, out); always #5 clk = !clk; initial begin environment = new("env"); uvm_resource_db#(virtual input_if)::set("env", "input_if", in); uvm_resource_db#(virtual output_if)::set("env", "output_if", out); clk = 0; run_test(); end endmodule ================================================ FILE: tests/testbenches/uvm_sequence.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_sequence :description: uvm_sequence test :tags: uvm uvm-classes :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class C extends uvm_sequence; function new(string name); super.new(name); endfunction virtual task pre_body(); `uvm_info (get_type_name(), "pre_body()", UVM_LOW) endtask virtual task pre_do(bit is_item); `uvm_info (get_type_name(), "pre_do()", UVM_LOW) endtask virtual function void mid_do(uvm_sequence_item this_item); `uvm_info (get_type_name(), "mid_do()", UVM_LOW) endfunction virtual task body(); `uvm_info (get_type_name(), "body()", UVM_LOW) endtask virtual function void post_do(uvm_sequence_item this_item); `uvm_info (get_type_name(), "post_do()", UVM_LOW) endfunction virtual task post_body(); `uvm_info (get_type_name(), "post_body()", UVM_LOW) endtask endclass module top; C obj; initial begin obj = new("C"); end endmodule ================================================ FILE: tests/testbenches/uvm_test_run_test.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_test_run_test :description: test if uvm_test instance can be called by name :tags: uvm uvm-classes :type: simulation elaboration parsing :timeout: 300 :unsynthesizable: 1 */ import uvm_pkg::*; `include "uvm_macros.svh" class simple_test extends uvm_test; `uvm_component_utils(simple_test) function new(string name, uvm_component parent = null); super.new(name, parent); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); `uvm_info("RESULT", "SUCCESS, simple_test called", UVM_LOW); phase.drop_objection(this); endtask endclass module top; initial begin run_test("simple_test"); end endmodule ================================================ FILE: tests/uvm/uvm_files.sv ================================================ // Copyright (C) 2019-2021 The SymbiFlow Authors. // // Use of this source code is governed by a ISC-style // license that can be found in the LICENSE file or at // https://opensource.org/licenses/ISC // // SPDX-License-Identifier: ISC /* :name: uvm_files :description: basic UVM test :tags: uvm :timeout: 300 :unsynthesizable: 1 */ ================================================ FILE: tools/BaseRunner.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import psutil import resource import shutil import signal import subprocess import os import re def kill_child_processes(parent_pid, sig=signal.SIGKILL): try: parent = psutil.Process(parent_pid) except psutil.NoSuchProcess: return children = parent.children(recursive=True) for process in children: process.send_signal(sig) class BaseRunner: """Common base class shared by all runners Each runner must either implement prepare_run_cb or override the run method. prepare_run_cb is responsible for generating command to run and preparing the command working directory if required by the tool. Runners must be located in tools/runners subdirectory to be detected and launched by the Makefile. """ def __init__( self, name, executable=None, supported_features={'preprocessing', 'parsing', 'elaboration'}): """Base runner class constructor Arguments: name -- runner name. executable -- name of an executable used by the particular runner can be omitted if default can_run method isn't used. supported_features -- list of supported test types """ self.name = name self.executable = executable self.supported_features = supported_features self.allowed_extensions = ['.v', '.sv', '.vh', '.svh'] self.url = "https://github.com/symbiflow/sv-tests" self.submodule = "" def get_mode(self, params): """Determine correct run mode or return None when incompatible """ test_features = params['type'].split() compatible_runners = params['compatible-runners'].split() if "all" not in compatible_runners: if self.name not in compatible_runners: return None # select the first mode from the list that matches both the runner and # the test modes_sorted = [ 'simulation', 'simulation_without_run', 'elaboration', 'parsing', 'preprocessing' ] for m in modes_sorted: if m in test_features and m in self.supported_features: return m return None def run(self, tmp_dir, params): """Run the provided test case This method is called by the main runner script (tools/runner). Arguments: tmp_dir -- temporary directory created for this test run. params -- dictionary with all metadata from the test file. All keys are used without colons, ie. :tags: becomes tags. Returns a tuple containing command execution log, return code, user time, system time and ram usage """ result = self.run_subprocess(tmp_dir, params) usage = resource.getrusage(resource.RUSAGE_CHILDREN) profiling_data = (usage.ru_utime, usage.ru_stime, usage.ru_maxrss) return result + profiling_data def run_subprocess(self, tmp_dir, params): """ Run the test case's subprocess This method is called by the run method and is expected to execute the command prepared in `self.cmd`. Subclasses may choose to override this in order to intercept the execution of the subprocess or inject custom return codes. Arguments are the same as for the run method. Returns a tuple containing command execution log and return code. """ self.prepare_run_cb(tmp_dir, params) proc = subprocess.Popen( self.cmd, cwd=tmp_dir, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) timeout = int(params['timeout']) if 'DISABLE_TEST_TIMEOUTS' in os.environ: timeout = None else: try: timeout = int(os.environ['OVERRIDE_TEST_TIMEOUTS']) except KeyError: # continue with timeout from params pass except ValueError: return ("Invalid OVERRIDE_TEST_TIMEOUTS value", 1) try: log, _ = proc.communicate(timeout=timeout) returncode = proc.returncode except subprocess.TimeoutExpired: kill_child_processes(proc.pid) proc.kill() proc.communicate() log = ("Timeout: > " + str(timeout) + "s\n").encode('utf-8') returncode = 71 # 71meout :) - something easy to grep for invocation_log = " ".join(self.cmd) + "\n" return ( invocation_log + self.transform_log(log.decode('utf-8', 'ignore')), returncode) def is_success_returncode(self, rc, params): """ Returns a boolean if the given returncode is considered a success. This function determines if the tool was running successfully. Tools might return more rich return codes, so not all non-zero codes might mean failure. """ return rc == 0 def transform_log(self, output): """ Post-process the output log Subclasses may choose to override this in order to transform the output of the command. """ return output def can_run(self): """Check if runner can be used This method is called by the main runner script (tools/runner) as a sanity check to verify that tool used by the runner is properly installed. Returns True when tool is installed and can be used, False otherwise. """ return shutil.which(self.executable) is not None def get_version_cmd(self): """ Get version command Returns a list containing the command and arguments needed to get the version. """ # assume sane defaults return [self.executable, "--version"] def get_version(self): """Attempt to get the version of the tool Returns a version string """ try: cmd = self.get_version_cmd() proc = subprocess.Popen( cmd, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) log, _ = proc.communicate() if proc.returncode != 0: return self.name return log.decode('utf-8') except (TypeError, NameError, OSError): return self.name def get_commit(self): """Attempt to get the commit hash of the tool. The result is based on the latest commit of its corresponding sumbodule. Returns a hash string """ try: path = "HEAD" if self.submodule: path += ":" + self.submodule cmd = ["git", "rev-parse", path] proc = subprocess.Popen( cmd, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) log, _ = proc.communicate() if proc.returncode != 0: return "HEAD" return log.decode('utf-8').strip() except (TypeError, NameError, OSError): return "HEAD" def get_url(self): """Get the URL to the homepage of the runner Returns a string with the URL """ return self.url def get_top_module_or_guess(self, params): """ Get the top-level module from the params, or guess it """ return params['top_module'] or self.guess_top_module(params) def guess_top_module(self, params): """ Guess the top-level module If the params do not contain a top-level module, check if there is a module called "top". If not, guess the top-level module by grepping for the first module in the first file. This works for most tests since most follow the implied naming convention. """ regex = re.compile(r'module\s+(\w+)\s*[#(;]') for fn in params['files']: with open(fn) as f: try: modules = regex.findall(f.read()) except UnicodeDecodeError: continue if modules: if "top" in modules: return "top" else: modules[0] return None ================================================ FILE: tools/check-runners ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys import argparse import logging from importlib import import_module parser = argparse.ArgumentParser() parser.add_argument("runners", metavar='runner', type=str, nargs='+') parser.add_argument("--filter", type=str, nargs='*') args = parser.parse_args() logger = logging.getLogger() runner_obj = None runners_ok = [] if 'RUNNERS_DIR' in os.environ: sys.path.insert(1, os.path.abspath(os.environ['RUNNERS_DIR'])) if args.filter is not None: runners = set(args.runners) & set(args.filter) else: runners = set(args.runners) runners = list(sorted(runners)) for runner in runners: module = import_module(runner) runner_cls = getattr(module, runner) runner_obj = runner_cls() new_path = [ os.path.abspath(os.environ['OUT_DIR'] + "/runners/bin/"), os.environ['PATH'] ] os.environ['PATH'] = ":".join(new_path) if runner_obj.can_run(): print(runner) else: logger.debug('Runner {} not found'.format(runner)) ================================================ FILE: tools/feature-analyzer ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import re import os import yaml import glob import argparse parser = argparse.ArgumentParser() parser.add_argument("-c", "--confdir") parser.add_argument("-d", "--srcdir") parser.add_argument("-f", "--files", nargs="+") parser.add_argument("-v", "--verbose", action="store_true") args = parser.parse_args() files_using_tags = {} found_keywords = {} keywords = {} exts = ['*.v', '*.sv', '*.vh'] for f in glob.glob(os.path.join(args.confdir, '**', '*.yml'), recursive=True): with open(f) as tag_file: data = yaml.safe_load(tag_file)['tags'] for key in data: try: keywords[key].extend(data[key]) except KeyError: keywords[key] = data[key] if args.files is not None: files = args.files else: files = [] for ext in exts: files.extend( glob.glob(os.path.join(args.srcdir, '**', ext), recursive=True)) for f in files: for tag in keywords: try: with open(os.path.realpath(f)) as src: for line in src: for keyword in keywords[tag]: if re.search(re.escape(keyword), line) is not None: try: found_keywords[tag].add(keyword) except KeyError: found_keywords[tag] = {keyword} try: files_using_tags[tag].add(f) except KeyError: files_using_tags[tag] = {f} except FileNotFoundError: pass print('Detected tags: {}'.format(files_using_tags.keys())) if args.verbose: print('Found keywords:') for tag in found_keywords: print('{}: {}'.format(tag, found_keywords[tag])) for tag in files_using_tags: print( 'Keywords from "{}" were found in the following files:'.format( tag)) for f in files_using_tags[tag]: print(f) ================================================ FILE: tools/history-graph ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import io import os import csv import sys import jinja2 import datetime import argparse import binascii from git import Repo from random import randint from collections import defaultdict parser = argparse.ArgumentParser() data = defaultdict(lambda: defaultdict(lambda: defaultdict(int))) parser.add_argument( '-r', '--results-dir', help='Directory with the test results repository', required=True) parser.add_argument( '-n', '--number-of-commits', help='Number of commits in the history to process', type=int, default=120) parser.add_argument( '--template', help='Path to the html template', default='conf/report/history-graph-template.html') parser.add_argument( '-o', '--out', help='Path to the html file with the history graph', default='out/report/history.html') # parse args args = parser.parse_args() def process_csv_reader(index, reader, data): for r in reader: key = 'pass' if r['Pass'] == 'True' else 'fail' data[r['Tool']][index][key] += 1 def process_csv_from_file(index, csv_file_path, data): with open(csv_file_path) as f: reader = csv.DictReader(f) process_csv_reader(index, reader, data) def process_csv_from_commit(index, csv_file, data): with io.BytesIO(csv_file.data_stream.read()) as f: reader = csv.DictReader(io.StringIO(f.read().decode('utf-8'))) process_csv_reader(index, reader, data) repo = Repo(args.results_dir) main_hash = repo.head.object.hexsha # check if there is new (not yet committed) results file available changed_files = [i.a_path for i in repo.index.diff(None)] append_changed = 'report.csv' in changed_files if append_changed: # process fewer history commits args.number_of_commits -= 1 for i in range(args.number_of_commits - 1, -1, -1): current_hash = f'{main_hash}~{i}' commit = repo.commit(current_hash) print(f'Processing {commit}') date = datetime.datetime.fromtimestamp(commit.committed_date) targetfile = commit.tree / 'report.csv' process_csv_from_commit(date, targetfile, data) if append_changed: date = datetime.datetime.now() print('Processing locally modified results') csv_path = os.path.join(args.results_dir, 'report.csv') process_csv_from_file(date, csv_path, data) datasets = defaultdict(list) # generate a set with all keys in case not all tools contain all keys all_keys = set() for tool in data: all_keys.update(set(data[tool].keys())) for tool in data: for index in sorted(list(all_keys)): if index not in data[tool]: # append 0% if the tool didn't run datasets[tool].append(0) else: bad = data[tool][index]['fail'] good = data[tool][index]['pass'] percent = round(good * 100 / (good + bad), 2) datasets[tool].append(percent) # convert lists to strings labels = ', '.join(f'"{x}"' for x in sorted(list(all_keys))) for tool in datasets: datasets[tool] = ', '.join(str(x) for x in datasets[tool]) # randomize colors colors = dict() for tool in datasets: color = hex(binascii.crc32(tool.encode('utf-8')))[-6:] colors[tool] = f'#{color:0<6.6}' try: with open(args.template) as f: template = jinja2.Template( f.read(), trim_blocks=True, lstrip_blocks=True) except Exception as e: print(f'Unable to read template: {e}') try: with open(args.out, 'w') as f: f.write( template.render(labels=labels, datasets=datasets, colors=colors)) except Exception as e: print(f'Unable to generate history graph: {e}') ================================================ FILE: tools/logparser.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import re def parseLog(log): res = True for line in log.split('\n'): pat = re.search(r':([a-z]+):(.*)', line.strip()) if pat: if pat.group(1) == 'assert': expr = pat.group(2) try: if not eval(expr): res = False except Exception: res = False return res ================================================ FILE: tools/report_analyzer.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import argparse import csv import json import sys import pytablewriter relevant_headers = ["Tool", "TestName", "Pass"] def get_data(csv_path): with open(csv_path, newline="") as csv_file: report = list(csv.DictReader(csv_file)) header = report[0].keys() assert set(relevant_headers).issubset( header), "Lack of crucial headers in CSV report " + csv_path tools = set(row["Tool"] for row in report) sorted_report = {} for tool in tools: sorted_report[tool] = {} for row in report: sorted_report[row["Tool"]][row["TestName"]] = row["Pass"] return sorted_report def check_tool(tool_reportA, tool_reportB, tool_name): results = { "new_passes": [], "new_failures": [], "added": [], "removed": [], "summary": {}, } testsA = set(tool_reportA.keys()) testsB = set(tool_reportB.keys()) tests_added = testsA.difference(testsB) tests_removed = testsB.difference(testsA) tests_comparable = testsA.intersection(testsB) added_cnt = len(tests_added) removed_cnt = len(tests_removed) no_change_cnt = 0 for test in tests_comparable: res = check_test(tool_reportA[test], tool_reportB[test]) if (res == -1): results["new_failures"].append(test) elif (res == 1): results["new_passes"].append(test) else: no_change_cnt += 1 fail_cnt = len(results["new_failures"]) pass_cnt = len(results["new_passes"]) for added_test in tests_added: results["added"].append(added_test) for removed_test in tests_removed: results["removed"].append(removed_test) results["summary"]["new_failures"] = fail_cnt results["summary"]["new_passes"] = pass_cnt results["summary"]["added"] = added_cnt results["summary"]["removed"] = removed_cnt results["summary"]["not_affected"] = no_change_cnt return results def check_test(test_reportA, test_reportB): if (test_reportA == test_reportB): return 0 elif (test_reportA == "True" and test_reportB == "False"): return 1 elif (test_reportA == "False" and test_reportB == "True"): return -1 else: raise ValueError( "unknown test result occured: A -> " + test_reportA + " B -> " + test_reportB) def check_reports(reportA, reportB): summary = { "comparable_tools": {}, "added_tools": [], "removed_tools": [], } toolsA = set(reportA.keys()) toolsB = set(reportB.keys()) tools = toolsA.intersection(toolsB) if (toolsA != toolsB): tools_added = toolsA.difference(toolsB) tools_removed = toolsB.difference(toolsA) summary["added_tools"] = list(tools_added) summary["removed_tools"] = list(tools_removed) for tool in tools: tool_results = check_tool(reportA[tool], reportB[tool], tool) summary["comparable_tools"][tool] = tool_results return summary def prepare_comment(summary, table_path): tools = list(summary["comparable_tools"].keys()) cols = list(summary["comparable_tools"][tools[0]]["summary"].keys()) cols.insert(0, "tool") matrix = [] for tool in tools: vals = list(summary["comparable_tools"][tool]["summary"].values()) vals.insert(0, tool) matrix.append(vals) writer = pytablewriter.MarkdownTableWriter() writer.table_name = "Changes In Tests" pretty_cols = [c.replace("_", " ").title() for c in cols] writer.headers = pretty_cols writer.value_matrix = matrix writer.write_table() with open(table_path, "w") as f: writer.stream = f writer.write_table() def main(): parser = argparse.ArgumentParser() parser.add_argument( "report_compare", help="csv report that will be compared with base report") parser.add_argument( "report_base", help="csv report that will be a base of comparison") parser.add_argument( "-o", "--output", dest="output_path", default="report_summary.json", help="path to output json file, defaults to \"report_summary.json\"") parser.add_argument( "-t", "--table", dest="table_path", default="report_summary.md", help= "path to output md file with summary, defaults to \"report_summary.md\"" ) parser.add_argument( "-c", "--changes", dest="changes_path", default="./out/report", help= "path to output csv file with names of test that changed status, defaults to \"./out/report\"" ) args = parser.parse_args() reportA = get_data(args.report_compare) reportB = get_data(args.report_base) summary = check_reports(reportA, reportB) with open(args.changes_path + "/new_failures.csv", "w") as csv_file: writer = csv.writer(csv_file) for tool in summary["comparable_tools"]: for test in summary["comparable_tools"][tool]["new_failures"]: writer.writerow([tool, test]) with open(args.changes_path + "/new_passes.csv", "w") as csv_file: writer = csv.writer(csv_file) for tool in summary["comparable_tools"]: for test in summary["comparable_tools"][tool]["new_passes"]: writer.writerow([tool, test]) prepare_comment(summary, args.table_path) with open(args.output_path, "w") as json_file: json.dump(summary, json_file, indent=4) if __name__ == "__main__": main() ================================================ FILE: tools/runner ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import re import sys import json import shutil import time import logging import argparse import tempfile from datetime import datetime from importlib import import_module from logparser import parseLog parser = argparse.ArgumentParser() parser.add_argument("-r", "--runner", required=True) action = parser.add_mutually_exclusive_group(required=True) action.add_argument("-t", "--test") action.add_argument("-v", "--version", action="store_true") action.add_argument("-u", "--url", action="store_true") parser.add_argument("-o", "--out", required=True) parser.add_argument("-k", "--keep-tmp", action="store_true") parser.add_argument( "-q", "--quiet", dest='verbosity', action='store_const', const=logging.ERROR, default=logging.DEBUG) args = parser.parse_args() # setup logger logger = logging.getLogger() logger.setLevel(args.verbosity) ch = logging.StreamHandler() ch.setFormatter(logging.Formatter('%(levelname)-8s| %(message)s')) logger.addHandler(ch) runner_obj = None if 'RUNNERS_DIR' in os.environ: sys.path.insert(1, os.path.abspath(os.environ['RUNNERS_DIR'])) try: module = import_module(args.runner) runner_cls = getattr(module, args.runner) runner_obj = runner_cls() except Exception as e: logger.error("Unable to load runner module: {}".format(str(e))) sys.exit(1) dirs = {} try: dirs['out'] = os.environ['OUT_DIR'] dirs['conf'] = os.environ['CONF_DIR'] dirs['tests'] = os.environ['TESTS_DIR'] dirs['runners'] = os.environ['RUNNERS_DIR'] dirs['third_party'] = os.environ['THIRD_PARTY_DIR'] except KeyError as e: logger.error("Required environment variables missing: {}".format(str(e))) sys.exit(1) new_path = [os.path.abspath(dirs['out'] + "/runners/bin/"), os.environ['PATH']] os.environ['PATH'] = ":".join(new_path) runner = os.path.abspath(os.path.join(dirs['runners'], args.runner)) out = os.path.abspath(args.out) os.makedirs(os.path.dirname(out), exist_ok=True) if args.version: version = runner_obj.get_version() with open(out, "w") as f: f.write(version) sys.exit(0) if args.url: url = runner_obj.get_url() with open(out, "w") as f: f.write(url) sys.exit(0) libs_json = os.path.join(dirs['conf'], 'runners', 'libs.json') with open(libs_json, 'r') as jf: try: libs = json.load(jf) except JSONDecodeError as e: libs = {} test = os.path.abspath(os.path.join(dirs['tests'], args.test)) # In addition to these fixed names, "runner__flags" is allowed supported_test_params = [ "name", "tags", "description", "files", "incdirs", "top_module", "timeout", "type", "should_fail", "should_fail_because", "defines", "compatible-runners", "unsynthesizable", "results_group" ] test_params = {} # look for all supported params try: with open(test) as f: for l in f: param = re.search(r"^:([a-zA-Z_-]+):\s*(.+)", l) if param is None: continue param_name = param.group(1).lower() param_value = param.group(2) if param_name not in supported_test_params: if not re.match(r'runner_.*_flags$', param_name): logger.warning( "Unsupported test param found: {} - ignoring".format( param_name)) continue test_params[param_name] = param_value # check all items in the supported_test_params exists in the test_params. if len(set(supported_test_params) - set(test_params.keys())) == 0: # all supported parameters found break else: # set default values for optional metadata entries test_params.setdefault('name', test) test_params.setdefault('files', test) test_params.setdefault('incdirs', os.path.dirname(test)) test_params.setdefault('top_module', '') test_params.setdefault('timeout', "30") test_params.setdefault('type', 'parsing elaboration') test_params.setdefault( 'should_fail', ("0", "1")["should_fail_because" in test_params.keys()]) test_params.setdefault('should_fail_because', "") test_params.setdefault('defines', "") test_params.setdefault('compatible-runners', "all") test_params.setdefault('unsynthesizable', '0') test_params.setdefault('results_group', "") if len(set(supported_test_params) - set(test_params.keys())) != 0: missing = list( set(supported_test_params) - set(test_params.keys())) logger.error( "Required parameters missing ({}) in {}".format( ", ".join(missing), args.test)) sys.exit(1) except Exception as e: logger.error("Unable to parse test file: {}".format(str(e))) sys.exit(1) # if the string is not empty and should_fail is 0 # then set it to 1 and issue a warning if test_params["should_fail"] == "0" and test_params["should_fail_because"]: test_params["should_fail"] = "1" logger.warning("contradictory params should_fail, should_fail_because.") # if string is empty and should_fail is 1 elif test_params[ "should_fail"] == "1" and not test_params["should_fail_because"]: logger.warning( "should_fail tag should be replaced with should_fail_because.") test_params['files'] = test_params['files'].split() test_params['incdirs'] = list( map( lambda x: os.path.abspath(os.path.join(dirs['tests'], x)), test_params['incdirs'].split())) test_params['mode'] = runner_obj.get_mode(test_params) if test_params['mode'] is None: logger.info("Skipping {}/{}".format(args.runner, args.test)) with open(out, "w") as f: f.write("") # runner does not support mode; just mark file as handled. sys.exit(0) for key in libs.keys(): if key in test_params['tags']: test_params['files'] = [ os.path.abspath(os.path.join(dirs['third_party'], p)) for p in libs[key]['files'] ] + test_params['files'] test_params['incdirs'] = [ os.path.abspath(os.path.join(dirs['third_party'], p)) for p in libs[key]['incdirs'] ] + test_params['incdirs'] test_params['defines'] = test_params['defines'].split() # Filter test files based on what the runner claims to support. filtered_files = [] for f in test_params['files']: if os.path.splitext(f)[1] in runner_obj.allowed_extensions: filtered_files.append(f) else: logger.info( "Skipping '{}' with '{}' due to unsupported extension".format( f, args.runner)) test_params['files'] = filtered_files # Keep it simple to avoid problems with escaping. RESULTS_GROUP_PARAM_VALIDATOR_RE = re.compile(r"[a-z0-9_]*") if not RESULTS_GROUP_PARAM_VALIDATOR_RE.fullmatch( test_params["results_group"]): group = test_params["results_group"] fixed_group = re.sub("[^a-z0-9_]", "_", group.lower()) logger.warning( f"results_group '{group}' does not match pattern '[a-z0-9_]*'. Replacing with '{fixed_group}'." ) test_params['results_group'] = fixed_group try: tmp_parent = os.path.join(os.path.abspath(dirs['out']), "tmp") os.makedirs(tmp_parent, exist_ok=True) tmp_dir = tempfile.mkdtemp(dir=tmp_parent) except (PermissionError, FileExistsError) as e: logger.error( "Unable to create a temporary directory for test: {}".format(str(e))) sys.exit(1) try: logger.info("Running {}/{}".format(args.runner, args.test)) start_time = time.time() output, rc, user_time, system_time, ram_usage = runner_obj.run( tmp_dir, test_params) end_time = time.time() tool_success = runner_obj.is_success_returncode(rc, test_params) test_params['rc'] = rc test_params['tool_success'] = "1" if tool_success else "0" test_params['runner'] = runner_obj.name test_params['runner_url'] = runner_obj.url test_params['time_elapsed'] = end_time - start_time test_params['user_time'] = user_time test_params['system_time'] = system_time test_params['ram_usage'] = ram_usage test_params['date_completed'] = datetime.now().strftime( "%Y-%m-%d %H:%M:%S") tool_should_fail = test_params["should_fail"] == "1" tool_failed = not tool_success tool_crashed = rc >= 126 test_passed = not tool_crashed and tool_should_fail == tool_failed if test_passed and test_params['mode'] == 'simulation': test_passed = parseLog(output) if test_passed: logger.info("PASS: {}/{}".format(args.runner, args.test)) else: logger.warning("FAIL: {}/{}".format(args.runner, args.test)) os.makedirs(os.path.dirname(out), exist_ok=True) test_params['files'] = ' '.join(test_params['files']) test_params['incdirs'] = ' '.join(test_params['incdirs']) test_params['defines'] = ' '.join(test_params['defines']) with open(out, "w") as log: # start by writing params for p in test_params: log.write("{}: {}\n".format(p, test_params[p])) log.write("\n") log.write(output) except Exception as e: logger.error( "Unable to test {} using {}: {}".format( args.runner, args.test, str(e))) sys.exit(1) finally: if args.keep_tmp: logger.info( "{}/{} work directory was left for inspection {}".format( args.runner, args.test, tmp_dir)) else: shutil.rmtree(tmp_dir) ================================================ FILE: tools/runners/Icarus.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020-2021 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from BaseRunner import BaseRunner import os class Icarus(BaseRunner): def __init__(self): super().__init__( 'icarus', 'iverilog', { 'preprocessing', 'parsing', 'elaboration', 'simulation', 'simulation_without_run' }) self.submodule = "third_party/tools/icarus" self.url = f"https://github.com/steveicarus/iverilog/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): ofile = 'iverilog.out' self.cmd = [self.executable, '-g2012'] self.cmd += ['-o', ofile] if params['mode'] == 'preprocessing': self.cmd.append('-E') elif params['mode'] == 'parsing': self.cmd += ['-t', 'null'] if params['top_module'] != '': self.cmd += ['-s', params['top_module']] for incdir in params['incdirs']: self.cmd.append('-I' + incdir) for define in params['defines']: self.cmd.append('-D' + define) self.cmd += params['files'] if params['mode'] != 'simulation': return # For simulation a wrapper script is created scr = os.path.join(tmp_dir, 'scr.sh') with open(scr, 'w') as f: f.write('set -x\n') f.write('{0} "$@" || exit $?\n'.format(self.cmd[0])) f.write(f'./iverilog.out\n') self.cmd = ['sh', 'scr.sh'] + self.cmd[1:] def get_version_cmd(self): return [self.executable, "-V"] def get_version(self): version = super().get_version() # The full version is the 4th word to the end of 1st line version = version.splitlines()[0].split()[3:] version.insert(0, self.name) return " ".join(version) ================================================ FILE: tools/runners/Odin.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from BaseRunner import BaseRunner class Odin(BaseRunner): def __init__(self): super().__init__("odin", "odin_II", {"preprocessing", "parsing"}) self.submodule = "third_party/tools/odin_ii" self.url = f"https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): self.cmd = [self.executable, '--permissive', '-o odin.blif', '-V'] # odin doesn't seem to support include directories # and thus only list of files is provided to it if params['top_module'] != '': self.cmd.append('--top_module ' + params['top_module']) self.cmd += params['files'] def get_version_cmd(self): # get it from the help return [self.executable, "-h"] def get_version(self): version = super().get_version() # The version is the 6th word in the 2nd line version = version.splitlines()[1].split()[5] return " ".join([self.name, version]) ================================================ FILE: tools/runners/Slang.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from BaseRunner import BaseRunner class Slang(BaseRunner): def __init__( self, name="slang", supported_features={'preprocessing', 'parsing', 'elaboration'}): super().__init__( name, executable="slang-driver", supported_features=supported_features) self.submodule = "third_party/tools/slang" self.url = f"https://github.com/MikePopoloski/slang/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): mode = params['mode'] self.cmd = [self.executable] if mode == 'preprocessing': self.cmd += ['-E'] elif mode == "parsing": self.cmd.append("--parse-only") # Some tests expect that all input files will be concatenated into # a single compilation unit, so ask slang to do that. self.cmd += ['--single-unit'] # Set a default timescale so we don't get errors about some # modules not having one. self.cmd += ['--timescale=1ns/1ns'] top = params['top_module'].strip() if top: self.cmd.append('--top=' + top) for incdir in params['incdirs']: self.cmd.extend(['-I', incdir]) for define in params['defines']: self.cmd.extend(['-D', define]) # Some tests access array elements out of bounds. Make that not an error. self.cmd.append("-Wno-error=index-oob") self.cmd.append("-Wno-error=range-oob") self.cmd.append("-Wno-error=range-width-oob") tags = params["tags"] # The Ariane and Ibex cores have duplicate definitions. if "ariane" in tags or "ibex" in tags: self.cmd.append("-Wno-duplicate-definition") # Ibex includes files that try to instantiate Xilinx-specific modules if "ibex" in tags: self.cmd.append("--ignore-unknown-modules") # The Ariane core has syntax errors with stream concat operators. if "ariane" in tags: self.cmd.append("--allow-self-determined-stream-concat") # black-parrot has syntax errors where variables are used before they are declared. # This is being fixed upstream, but it might take a long time to make it to master # so this works around the problem in the meantime. if "black-parrot" in tags and mode != "parsing": self.cmd.append("--allow-use-before-declare") # These tests simply cannot be elaborated because they target # modules that have invalid parameter values for a top-level module, # or have an invalid configuration that results in $fatal calls. name = params["name"] if 'bp_lce' in name or 'bp_uce' or 'bp_multicore' in name: self.cmd.append("--parse-only") # These cores use a non-standard extension to write to the same variable # from multiple procedures. if "fx68k" in tags: self.cmd.append("--allow-dup-initial-drivers") self.cmd += params['files'] def get_version(self): version = super().get_version() return " ".join([self.name, version.split()[2]]) ================================================ FILE: tools/runners/Slang_parse.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from runners.Slang import Slang class Slang_parse(Slang): def __init__(self): super().__init__( "slang-parse", supported_features={'preprocessing', 'parsing'}) ================================================ FILE: tools/runners/Surelog.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from BaseRunner import BaseRunner from distutils.util import strtobool class Surelog(BaseRunner): def __init__(self): super().__init__("Surelog", "surelog") self.submodule = "third_party/tools/Surelog" self.url = f"https://github.com/chipsalliance/Surelog/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): self.cmd = [self.executable, '-nopython', '-parse'] if params['mode'] in ["parsing", "preprocessing"]: self.cmd.append('-noelab') # silence surelog self.cmd.append("-nonote") self.cmd.append("-noinfo") self.cmd.append("-nowarning") # force sverilog mode for .v files if "black-parrot" in params["tags"]: self.cmd.append('-sverilog') if "basejump" in params["tags"]: self.cmd.append('-sverilog') if "ivtest" in params["tags"]: self.cmd.append('-sverilog') top = params['top_module'].strip() if top: self.cmd.append('--top-module ' + top) # lowmem option if "black-parrot" in params["tags"]: self.cmd.append('-lowmem') for define in params['defines']: self.cmd.append('-D' + define) # regular options for incdir in params['incdirs']: self.cmd.append('-I' + incdir) self.cmd += params['files'] def is_success_returncode(self, rc, params): # We're only interested in # syntax, fatal and errors. return rc & 0x07 == 0 ================================================ FILE: tools/runners/Sv2v_zachjs.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from BaseRunner import BaseRunner class Sv2v_zachjs(BaseRunner): def __init__(self): super().__init__( "zachjs-sv2v", "zachjs-sv2v", {"preprocessing", "parsing", "elaboration"}) self.submodule = "third_party/tools/zachjs-sv2v" self.url = f"https://github.com/zachjs/sv2v/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): self.cmd = [self.executable] for incdir in params['incdirs']: self.cmd.append('-I' + incdir) for define in params['defines']: self.cmd.append('-D' + define) self.cmd += params['files'] def get_version(self): version = super().get_version() # return it with our custom prefix and without the trailing newline return "zachjs-" + version.rstrip() ================================================ FILE: tools/runners/SynligYosys.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys from BaseRunner import BaseRunner class SynligYosys(BaseRunner): def __init__(self): super().__init__( "yosys-synlig", "yosys-synlig", {"preprocessing", "parsing", "elaboration"}) self.submodule = "third_party/tools/synlig" self.url = f"https://github.com/chipsalliance/synlig/tree/{self.get_commit()}" def get_mode(self, params): unsynthesizable = int(params['unsynthesizable']) if unsynthesizable: return None return super().get_mode(params) def prepare_run_cb(self, tmp_dir, params): runner_scr = os.path.join(tmp_dir, "scr.sh") yosys_scr = os.path.join(tmp_dir, "yosys-script") mode = params['mode'] top = params['top_module'] or None # generate yosys script with open(yosys_scr, "w") as f: f.write("plugin -i systemverilog\n") f.write( "read_systemverilog -nopython -parse -sverilog -nonote -noinfo -nowarning -DSYNTHESIS" ) if mode != "elaboration": f.write(" -parse-only") if top is not None: f.write(f' --top-module {top}') if mode in ["parsing", "preprocessing"]: f.write(' -noelab') for i in params["incdirs"]: f.write(f" -I{i}") for d in params["defines"]: f.write(f" -D{d}") for fn in params["files"]: f.write(f" {fn}") f.write("\n") if mode == "elaboration": # prep (without optimizations) if top is not None: f.write(f"hierarchy -top \\{top}\n") else: f.write("hierarchy -auto-top\n") f.write( "proc\n" "check\n" "memory_dff\n" "memory_collect\n" "stat\n" "check\n") # generate runner script with open(runner_scr, "w") as f: f.write("set -e\n") f.write("set -x\n") f.write(f"cat {yosys_scr}\n") f.write(f"{self.executable} -s {yosys_scr}\n") self.cmd = ["sh", runner_scr] ================================================ FILE: tools/runners/Verible.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from BaseRunner import BaseRunner class Verible(BaseRunner): def __init__(self): super().__init__("verible", "verible-verilog-syntax", {"parsing"}) self.submodule = "third_party/tools/verible" self.url = f"https://github.com/chipsalliance/verible/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): self.cmd = [self.executable] self.cmd += params['files'] ================================================ FILE: tools/runners/VeribleExtractor.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from BaseRunner import BaseRunner import os import shlex class VeribleExtractor(BaseRunner): def __init__(self): super().__init__( "verible_extractor", "verible-verilog-kythe-extractor", {"parsing"}) self.submodule = "third_party/tools/verible" self.url = f"https://github.com/google/verible/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): src_list_path = os.path.join(tmp_dir, "src_list") script_path = os.path.join(tmp_dir, "run.sh") with open(src_list_path, "w") as src_list: files = [os.path.abspath(f) for f in params.get("files", [])] print("\n".join(files), file=src_list) inc_dirs = ",".join(params.get("incdirs", [])) with open(script_path, "w") as script: command = ( '{executable}' ' --file_list_root "/"' ' --include_dir_paths {inc_dirs}' ' --file_list_path {src_list_path}').format( executable=self.executable, inc_dirs=shlex.quote(inc_dirs), src_list_path=shlex.quote(src_list_path)) s = ( 'echo "#" {command_str}\n' 'log="$( {command} 2>&1 1>/dev/null )"\n' 'rc=$?\n' 'echo "stderr:"\n' 'echo "$log"\n' 'if [ $rc -eq 0 ]; then\n' # Use the log output as an information that something failed. # Ignore warnings about re-defining macros, and empty lines. ' ! echo "$log" | grep -v -e "^I .*] Re-defining macro.*" -e "^$" -q\n' ' rc=$?\n' 'fi\n' 'exit $rc\n').format( command_str=shlex.quote(command), command=command) script.write(s) self.cmd = ['sh', script_path] ================================================ FILE: tools/runners/Verilator.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import shutil import shlex from BaseRunner import BaseRunner class Verilator(BaseRunner): def __init__(self): super().__init__( "verilator", "verilator", { "preprocessing", "parsing", "elaboration", "simulation", "simulation_without_run" }) self.c_extensions = ['.cc', '.c', '.cpp', '.h', '.hpp'] self.allowed_extensions.extend(['.vlt'] + self.c_extensions) self.submodule = "third_party/tools/verilator" self.url = f"https://github.com/verilator/verilator/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): mode = params['mode'] conf = os.environ['CONF_DIR'] scr = os.path.join(tmp_dir, 'scr.sh') # verilator executable is a script but it doesn't # have shell shebang on the first line self.cmd = ['sh', 'scr.sh'] # Enable timing control support: self.cmd.append('--timing') if mode in ['simulation', 'simulation_without_run']: self.cmd += ['--binary'] elif mode == 'preprocessing': self.cmd += ['-P', '-E'] else: # parsing and elaboration self.cmd += ['--lint-only'] # Allow UVM builds within reasonable timeout self.cmd += ['--build-jobs', '0'] # Disable compiler optimization as build time exceeds test runtime self.cmd += ['-CFLAGS', '-O0'] self.cmd += ['-Wno-fatal', '-Wno-UNOPTFLAT', '-Wno-BLKANDNBLK'] # Flags for compliance testing: self.cmd += ['-Wpedantic', '-Wno-context'] if params['top_module'] != '': self.cmd += ['--top-module', params['top_module']] top = params['top_module'] else: top = 'top' # top is None only if the test contains no module # if that test would be run with simulation related options # Verilator throws error on that test before the build stage build_name = f'V{top}' build_dir = 'vbuild' for incdir in params['incdirs']: self.cmd.append('-I' + incdir) # No tests require UVM DPI, and we don't currently have a nice # way of knowing when it is needed to put it on the command line. # Also avoids compile time of the DPI C code. self.cmd.append('-DUVM_NO_DPI') if mode in ['simulation', 'simulation_without_run']: self.cmd += [ '--Mdir', build_dir, '--prefix', build_name, '-o', build_name ] if 'runner_verilator_flags' in params: self.cmd += shlex.split(params['runner_verilator_flags']) for define in params['defines']: self.cmd.append('-D' + define) self.cmd += params['files'] with open(scr, 'w') as f: f.write('set -x\n') f.write('{0} "$@" || exit $?\n'.format(self.executable)) if mode == 'simulation': f.write(f'./{build_dir}/{build_name}\n') ================================================ FILE: tools/runners/Yosys.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os from BaseRunner import BaseRunner class Yosys(BaseRunner): def __init__(self): super().__init__( "yosys", "yosys", { "preprocessing", "parsing", "elaboration", "simulation", "simulation_without_run" }) self.submodule = "third_party/tools/yosys" self.url = f"https://github.com/YosysHQ/yosys/tree/{self.get_commit()}" def get_mode(self, params): unsynthesizable = int(params['unsynthesizable']) if unsynthesizable: return None return super().get_mode(params) def prepare_run_cb(self, tmp_dir, params): run = os.path.join(tmp_dir, "run.sh") scr = os.path.join(tmp_dir, 'scr.ys') mode = params['mode'] defer = "" if mode in ["preprocessing", "parsing"]: defer = "-defer" nodisplay = "" if mode in ["simulation", "simulation_without_run"]: nodisplay = "-nodisplay" top = params['top_module'] or None if (top is not None): top_opt = "-top \\{top}" else: top_opt = "-auto-top" inc = "" for incdir in params['incdirs']: inc += f' -I {incdir}' defs = "" for define in params['defines']: defs += f' -D {define}' # prepare yosys script with open(scr, 'w') as f: for svf in params['files']: f.write( f'read_verilog {defer} -sv {nodisplay} {inc} {defs} {svf}\n' ) if mode not in ["preprocessing", "parsing"]: # prep (without optimizations) f.write( f"hierarchy {top_opt}\n" "proc\n" "check\n" "clean\n" "memory_dff\n" "memory_collect\n" "stat\n" "check\n") if mode in ['simulation', 'simulation_without_run']: f.write("sim -assert\n") # prepare wrapper script with open(run, 'w') as f: f.write('set -x\n') f.write(f'cat {scr}\n') f.write(f'{self.executable} -Q -T {scr}\n') self.cmd = ['sh', run] def get_version_cmd(self): return [self.executable, "-V"] def get_version(self): version = super().get_version() return " ".join([self.name, version.split()[1]]) ================================================ FILE: tools/runners/circt_verilog.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from BaseRunner import BaseRunner class circt_verilog(BaseRunner): def __init__( self, name="circt-verilog", supported_features={"preprocessing", "parsing", "elaboration"}, ): super().__init__( name, executable="circt-verilog", supported_features=supported_features) self.submodule = "third_party/tools/circt-verilog" self.url = f"https://github.com/llvm/circt/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): self.cmd = [self.executable] mode = params["mode"] # To process the input: The preprocessor indicates only run and print preprocessed files; # parsing means only lint the input, without elaboration and mapping to CIRCT IR. if mode == "preprocessing": self.cmd += ["-E"] elif mode == "parsing": self.cmd += ["--parse-only"] # The following options are mostly borrowed from the Slang runner, since circt-verilog # uses Slang as its Verilog frontend. # Setting for additional include search paths. for incdir in params["incdirs"]: self.cmd.extend(["-I", incdir]) # Setting for macro or value defines in all source files. for define in params["defines"]: self.cmd.extend(["-D", define]) # Borrow from slang config for some modules which get errors without a default timescale. self.cmd += ["--timescale=1ns/1ns"] # Combine all input files for the tests that need a single compilation unit. self.cmd += ["--single-unit"] # Disable certain warnings to make the output less noisy. self.cmd += ["-Wno-implicit-conv"] # Some tests access array elements out of bounds. Make that not an error. self.cmd += [ "-Wno-error=index-oob", "-Wno-error=range-oob", "-Wno-error=range-width-oob", ] top = self.get_top_module_or_guess(params) if top is not None: self.cmd += ["--top=" + top] tags = params["tags"] # The Ariane and Ibex cores have duplicate definitions. if "ariane" in tags or "ibex" in tags: self.cmd += ["-Wno-duplicate-definition"] # The Ariane core has syntax errors with stream concat operators. if "ariane" in tags: self.cmd += ["-Xslang=--allow-self-determined-stream-concat"] # black-parrot has syntax errors where variables are used before they are declared. # This is being fixed upstream, but it might take a long time to make it to master # so this works around the problem in the meantime. if "black-parrot" in tags and mode != "parsing": self.cmd += ["--allow-use-before-declare"] # These tests simply cannot be elaborated because they target # modules that have invalid parameter values for a top-level module, # or have an invalid configuration that results in $fatal calls. name = params["name"] if 'bp_lce' in name or 'bp_uce' or 'bp_multicore' in name: self.cmd += ["--parse-only"] # These cores use a non-standard extension to write to the same variable # from multiple procedures. if "fx68k" in tags: self.cmd += ["--allow-dup-initial-drivers"] self.cmd += params["files"] ================================================ FILE: tools/runners/moore.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import re from BaseRunner import BaseRunner class moore(BaseRunner): def __init__( self, name="moore", supported_features={'preprocessing', 'parsing'}): super().__init__( name, executable="moore", supported_features=supported_features) self.submodule = "third_party/tools/moore" self.url = f"https://github.com/fabianschuiki/moore/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): self.cmd = [self.executable] for incdir in params['incdirs']: self.cmd.append('-I') self.cmd.append(incdir) tl = self.get_top_module_or_guess(params) if tl: self.cmd.append('-e') self.cmd.append(tl) self.cmd += params['files'] def run_subprocess(self, tmp_dir, params): # Immediately fail some tests which otherwise completely break the # compiler. # TODO: Remove once #378 lands. blacklist = [ "std2017/p220.sv", "std2017/p221.sv", "std2017/p745.sv", "std2017/p341.sv", "std2017/p371.sv", "std2017/p759.sv", "std2017/p773.sv", ] for arg in params['files']: for bl in blacklist: if bl in arg: return ("Skipping blacklisted " + arg, 1) return super().run_subprocess(tmp_dir, params) def transform_log(self, log): # Strip away terminal escape codes. Moore does not yet check if the # stdout is a tty that supports colorization. log = re.sub(r'\x1B\[[0-?]*[ -/]*[@-~]', '', log) return log ================================================ FILE: tools/runners/moore_parse.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from runners.moore import moore class moore_parse(moore): def __init__(self): super().__init__("moore-parse", supported_features={'parsing'}) def prepare_run_cb(self, tmp_dir, params): self.cmd = [self.executable, '--syntax'] for incdir in params['incdirs']: self.cmd.append('-I') self.cmd.append(incdir) self.cmd += params['files'] ================================================ FILE: tools/runners/sv_parser.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from BaseRunner import BaseRunner class sv_parser(BaseRunner): def __init__(self): super().__init__("sv-parser", "parse_sv", {"preprocessing", "parsing"}) self.submodule = "third_party/tools/sv-parser" self.url = f"https://github.com/dalance/sv-parser/tree/{self.get_commit()}" def prepare_run_cb(self, tmp_dir, params): self.cmd = [self.executable] for incdir in params['incdirs']: self.cmd.append('--include') self.cmd.append(incdir) for define in params['defines']: self.cmd.append('--define') self.cmd.append(define) self.cmd += params['files'] ================================================ FILE: tools/runners/tree_sitter_systemverilog.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import shutil from BaseRunner import BaseRunner class tree_sitter_systemverilog(BaseRunner): def __init__(self): super().__init__( "tree-sitter-systemverilog", "tree-sitter", {"parsing"}) self.submodule = "third_party/tools/tree-sitter-systemverilog" self.url = f"https://github.com/gmlarumbe/tree-sitter-systemverilog/tree/{self.get_commit()}" self.parser_dir = os.path.abspath( os.environ['TREE_SITTER_SVERILOG_PARSER_DIR']) def prepare_run_cb(self, tmp_dir, params): # Tree‑sitter expects the grammar.json in $CWD/src/grammar.json, # so we symlink the parser directory. symlink_path = os.path.join(tmp_dir, 'src') if os.path.exists(symlink_path) is False: os.symlink(self.parser_dir, symlink_path, True) self.cmd = [self.executable, 'parse', '--quiet'] self.cmd += params['files'] def can_run(self): parser_c_path = os.path.join(self.parser_dir, 'parser.c') return os.path.exists(parser_c_path) and super().can_run() ================================================ FILE: tools/runners/tree_sitter_verilog.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import shutil from BaseRunner import BaseRunner class tree_sitter_verilog(BaseRunner): def __init__(self): super().__init__("tree-sitter-verilog", "tree-sitter", {"parsing"}) self.submodule = "third_party/tools/tree-sitter-verilog" self.url = f"https://github.com/tree-sitter/tree-sitter-verilog/tree/{self.get_commit()}" self.parser_dir = os.path.abspath( os.environ['TREE_SITTER_VERILOG_PARSER_DIR']) def prepare_run_cb(self, tmp_dir, params): # Tree‑sitter expects the grammar.json in $CWD/src/grammar.json, # so we symlink the parser directory. symlink_path = os.path.join(tmp_dir, 'src') if os.path.exists(symlink_path) is False: os.symlink(self.parser_dir, symlink_path, True) self.cmd = [self.executable, 'parse', '--quiet'] self.cmd += params['files'] def can_run(self): parser_c_path = os.path.join(self.parser_dir, 'parser.c') return os.path.exists(parser_c_path) and super().can_run() ================================================ FILE: tools/runners/yosys_slang.py ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC import os import sys from BaseRunner import BaseRunner class yosys_slang(BaseRunner): def __init__(self): super().__init__("yosys-slang", "yosys-slang", {"elaboration"}) self.submodule = "third_party/tools/yosys-slang" self.url = f"https://github.com/povik/yosys-slang/tree/{self.get_commit()}" def get_mode(self, params): unsynthesizable = int(params['unsynthesizable']) if unsynthesizable: return None # These tests simply cannot be elaborated because they target # modules that have invalid parameter values for a top-level module, # or have an invalid configuration that results in $fatal calls. name = params["name"] tags = params["tags"] if "black-parrot" in tags and ('bp_lce' in name or 'bp_uce' or 'bp_multicore' in name): return None return super().get_mode(params) def prepare_run_cb(self, tmp_dir, params): yosys_scr = os.path.join(tmp_dir, "yosys-script") mode = params['mode'] slang_cmd = ['-DSYNTHESIS'] # Ignore content which is unsynthesizable or likely irrelevant for synthesis. The inclusion # of `--ignore-initial` is objectionable as it means the frontend won't pick up memory # initialization. slang_cmd += [ '--ignore-timing', '--ignore-initial', '--ignore-assertions' ] # Some tests expect that all input files will be concatenated into # a single compilation unit, so ask slang to do that. slang_cmd += ['--single-unit'] # Set a default timescale so we don't get errors about some # modules not having one. slang_cmd += ['--timescale=1ns/1ns'] top = params['top_module'].strip() or None if top: slang_cmd.append('--top=' + top) for incdir in params['incdirs']: slang_cmd.extend(['-I', incdir]) for define in params['defines']: slang_cmd.extend(['-D', define]) # Some tests access array elements out of bounds. Make that not an error. slang_cmd.append("-Wno-error=index-oob") slang_cmd.append("-Wno-error=range-oob") slang_cmd.append("-Wno-error=range-width-oob") tags = params["tags"] # The Ariane core does not build correctly if VERILATOR is not defined -- it will attempt # to reference nonexistent modules, for example. if "ariane" in tags: slang_cmd.append("-DVERILATOR") # black-parrot has syntax errors where variables are used before they are declared. # This is being fixed upstream, but it might take a long time to make it to master # so this works around the problem in the meantime. if "black-parrot" in tags: slang_cmd.append("--allow-use-before-declare") # These cores use a non-standard extension to write to the same variable # from multiple procedures. if "fx68k" in tags: slang_cmd.append("--allow-dup-initial-drivers") slang_cmd += params['files'] # generate yosys script with open(yosys_scr, "w") as f: f.write("plugin -i slang\n") f.write(f"read_slang {' '.join(slang_cmd)}\n") # prep (without optimizations) if top is not None: f.write(f"hierarchy -top \\{top}\n") else: f.write("hierarchy -auto-top\n") f.write( "proc\n" "check\n" "memory_dff\n" "memory_collect\n" "stat\n" "check\n") self.cmd = [self.executable, "-s", yosys_scr] ================================================ FILE: tools/runners.mk ================================================ # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC INSTALL_DIR := $(abspath $(OUT_DIR)/runners/) RDIR := $(abspath third_party/tools) TDIR := $(abspath tools) CDIR := $(abspath conf) TREE_SITTER_SVERILOG_PARSER_DIR := $(abspath $(OUT_DIR)/tmp/tree-sitter-systemverilog/parser) TREE_SITTER_VERILOG_PARSER_DIR := $(abspath $(OUT_DIR)/tmp/tree-sitter-verilog/parser) export TREE_SITTER_SVERILOG_PARSER_DIR export TREE_SITTER_VERILOG_PARSER_DIR .PHONY: runners runners: # odin odin: $(INSTALL_DIR)/bin/odin_II $(INSTALL_DIR)/bin/odin_II: $(MAKE) -C $(RDIR)/odin_ii/ODIN_II/ build install -D $(RDIR)/odin_ii/ODIN_II/odin_II $@ # yosys yosys: $(INSTALL_DIR)/bin/yosys $(INSTALL_DIR)/bin/yosys: $(MAKE) -C $(RDIR)/yosys CONFIG=gcc PREFIX=$(INSTALL_DIR) install # icarus icarus: $(INSTALL_DIR)/bin/iverilog $(INSTALL_DIR)/bin/iverilog: cd $(RDIR)/icarus && autoconf cd $(RDIR)/icarus && ./configure --prefix=$(abspath $(INSTALL_DIR))/ $(MAKE) -C $(RDIR)/icarus $(MAKE) -C $(RDIR)/icarus installdirs $(MAKE) -C $(RDIR)/icarus install # verilator verilator: $(INSTALL_DIR)/bin/verilator $(INSTALL_DIR)/bin/verilator: cd $(RDIR)/verilator && autoconf cd $(RDIR)/verilator && ./configure --prefix=$(abspath $(INSTALL_DIR))/ $(MAKE) -C $(RDIR)/verilator $(MAKE) -C $(RDIR)/verilator install # slang slang: $(INSTALL_DIR)/bin/slang-driver $(INSTALL_DIR)/bin/slang-driver: mkdir -p $(RDIR)/slang/build cd $(RDIR)/slang/build && cmake .. -DSLANG_INCLUDE_TESTS=OFF -DCMAKE_BUILD_TYPE=Release $(MAKE) -C $(RDIR)/slang/build install -D $(RDIR)/slang/build/bin/slang $@ # Surelog surelog: $(INSTALL_DIR)/bin/surelog $(INSTALL_DIR)/bin/surelog: cd $(RDIR)/Surelog ; mkdir -p build/tests dist cd $(RDIR)/Surelog/build && cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$(INSTALL_DIR) ../ $(MAKE) -C $(RDIR)/Surelog/build install # zachjs-sv2v zachjs-sv2v: $(INSTALL_DIR)/bin/zachjs-sv2v $(INSTALL_DIR)/bin/zachjs-sv2v: $(MAKE) -C $(RDIR)/zachjs-sv2v install -D $(RDIR)/zachjs-sv2v/bin/sv2v $@ # tree-sitter-verilog & tree-sitter-systemverilog tree-sitter-systemverilog: $(INSTALL_DIR)/bin/tree-sitter (export PATH=$(INSTALL_DIR)/bin/:${PATH} && \ cd $(RDIR)/tree-sitter-systemverilog && tree-sitter generate) mkdir -p $(abspath $(OUT_DIR)/tmp/tree-sitter-systemverilog) mv $(RDIR)/tree-sitter-systemverilog/src $(TREE_SITTER_SVERILOG_PARSER_DIR) tree-sitter-verilog: $(INSTALL_DIR)/bin/tree-sitter (export PATH=$(INSTALL_DIR)/bin/:${PATH} && \ cd $(RDIR)/tree-sitter-verilog && tree-sitter generate) mkdir -p $(abspath $(OUT_DIR)/tmp/tree-sitter-verilog) mv $(RDIR)/tree-sitter-verilog/src $(TREE_SITTER_VERILOG_PARSER_DIR) $(INSTALL_DIR)/bin/tree-sitter: wget https://github.com/tree-sitter/tree-sitter/releases/download/v0.25.3/tree-sitter-linux-x64.gz gunzip tree-sitter-linux-x64.gz install -D tree-sitter-linux-x64 $@ rm tree-sitter-linux-x64 # yosys-synlig yosys-synlig: $(INSTALL_DIR)/bin/yosys-synlig $(INSTALL_DIR)/bin/yosys-synlig: mkdir -p $(INSTALL_DIR) (export PATH=$(INSTALL_DIR)/bin/:${PATH} && \ cd $(RDIR)/synlig && \ $(MAKE) -rR -Oline install CFG_OUT_DIR=$(INSTALL_DIR)/) mv $(INSTALL_DIR)/bin/yosys $(INSTALL_DIR)/bin/yosys-synlig # sv-parser sv-parser: $(INSTALL_DIR)/bin/parse_sv $(INSTALL_DIR)/bin/parse_sv: cd $(RDIR)/sv-parser && cargo build --release --example parse_sv install -D $(RDIR)/sv-parser/target/release/examples/parse_sv $@ # moore moore: $(INSTALL_DIR)/bin/moore $(INSTALL_DIR)/bin/moore: $(RDIR)/moore/Cargo.lock (export CARGO_NET_GIT_FETCH_WITH_CLI=true && \ cargo install --locked --path $(RDIR)/moore --root $(INSTALL_DIR) --bin moore) $(RDIR)/moore/Cargo.lock: $(CDIR)/runners/Cargo.lock cp -f $(CDIR)/runners/Cargo.lock $(RDIR)/moore/Cargo.lock # verible verible: cd $(RDIR)/verible/ && bazel build :install-binaries --noshow_progress --//bazel:use_local_flex_bison -c opt cd $(RDIR)/verible/ && .github/bin/simple-install.sh $(INSTALL_DIR)/bin cd $(RDIR)/verible/ && bazel shutdown $(INSTALL_DIR)/bin/verible-verilog-kythe-extractor: verible $(INSTALL_DIR)/bin/verilog_syntax: verible # yosys-slang yosys-slang: $(INSTALL_DIR)/bin/yosys-slang $(INSTALL_DIR)/bin/slang-yosys $(INSTALL_DIR)/bin/slang-yosys-config: $(MAKE) -C $(RDIR)/yosys CONFIG=gcc CXXSTD=c++20 ENABLE_ABC=0 \ PROGRAM_PREFIX=slang- PREFIX=$(INSTALL_DIR) install $(INSTALL_DIR)/bin/yosys-slang: $(INSTALL_DIR)/bin/slang-yosys-config mkdir -p $(INSTALL_DIR) (export PATH=$(INSTALL_DIR)/bin/:${PATH} && \ cd $(RDIR)/yosys-slang && \ TARGET=$(INSTALL_DIR)/share/slang-yosys/plugins/slang.so YOSYS_PREFIX=slang- ./build.sh) # copy slang-yosys, which was the result of compiling yosys with PROGRAM_PREFIX=slang-, # to yosys-slang, which is the executable registered in tools/runners/yosys_slang.py cp $(INSTALL_DIR)/bin/slang-yosys $(INSTALL_DIR)/bin/yosys-slang # circt-verilog circt-verilog: $(INSTALL_DIR)/bin/circt-verilog $(INSTALL_DIR)/bin/circt-verilog: cd $(RDIR)/circt-verilog && cmake llvm/llvm -B build \ -DCMAKE_INSTALL_PREFIX=$(INSTALL_DIR) \ -DCMAKE_BUILD_TYPE=Release \ -DLLVM_TARGETS_TO_BUILD=host \ -DLLVM_ENABLE_PROJECTS=mlir \ -DLLVM_EXTERNAL_PROJECTS=circt \ -DLLVM_EXTERNAL_CIRCT_SOURCE_DIR=$(RDIR)/circt-verilog \ -DCIRCT_SLANG_FRONTEND_ENABLED=ON $(MAKE) -C $(RDIR)/circt-verilog/build install-circt-verilog # setup the dependencies RUNNERS_TARGETS := odin yosys icarus verilator slang zachjs-sv2v tree-sitter-systemverilog tree-sitter-verilog sv-parser moore verible surelog yosys-synlig circt-verilog .PHONY: $(RUNNERS_TARGETS) runners: $(RUNNERS_TARGETS) ================================================ FILE: tools/sv-report ================================================ #!/usr/bin/env python3 # -*- coding: utf-8 -*- # # Copyright (C) 2020 The SymbiFlow Authors. # # Use of this source code is governed by a ISC-style # license that can be found in the LICENSE file or at # https://opensource.org/licenses/ISC # # SPDX-License-Identifier: ISC from pygments.formatters import HtmlFormatter from pygments import lexers, highlight import multiprocessing from glob import glob from logparser import parseLog import argparse import logging import jinja2 import markupsafe import csv import datetime import sys import os import re import html import urllib.parse import dataclasses import enum from typing import Dict, Any, List, Set, Iterable import json import itertools from typing import Match # portable type alias # We only consider tests with minimum this size for the throughput # calculation, so that we skip the super-tiny few-line tests that are # not a true reflection of a common usage. _minimum_throughput_file_size = 1024 # Regexp for matching file paths with optional line and column number # separated with ":". # The patch must contain at least one "/". Designed for finding references to # input files in tools' output. # Captures 3 groups: # 1: file path # 2: matched text following file path (i.e. ":row:column") # 3: row number # Example inputs: # /some/file.sv # relative/file/name.v:12 <- group(2): ":12", group(3): "12" # /some/file.svh:12:35 <- group(2): ":12:35", group(3): "12" _PATH_WITH_LINE_NO_MATCHER = re.compile( r"([^\s:\"'`/]*/[^\s:\"'`]+\.\w+)(:(\d+)(?::\d+)?)?") # CamelCase or undscore_separator csv headers ? # We use CamelCase so that gnuplot getting header from CSV displays them # as-is and doesn't print the post-underscore letter a subscript. _csv_header = [ 'TestName', 'Tool', # Parser/Compiler/Tool processing it 'Group', 'Pass', # result. True if we got expected result. 'ExitCode', # Actual tool exit code 'Tags', 'InputBytes', # test facts 'AllowedTimeout', # Some measurements 'TimeUser', 'TimeSystem', 'TimeWall', 'RamUsageMiB' ] # Global state for worker threads. Initialized once per process using # init_globals. _logger = None _log_template_file = None _log_template = None _logs_dir = None _out_dir = None _top_dir = None _logs_out_dir = None _src_template = None _src_template_file = None _meta_tags = None def init_logger(quiet: bool, verbose: bool): global _logger if _logger is not None: return _logger = logging.getLogger() _logger.setLevel(logging.DEBUG) ch = logging.StreamHandler() ch.setFormatter(logging.Formatter('%(levelname)-8s| %(message)s')) _logger.addHandler(ch) if quiet: _logger.setLevel(logging.ERROR) elif verbose: _logger.setLevel(logging.DEBUG) else: _logger.setLevel(logging.INFO) return _logger def init_templates(log_template_file, src_template_file): global _log_template global _log_template_file global _src_template global _src_template_file template_dir = os.path.dirname(log_template_file) jinja2env = ReportJinja2Env(template_dir) if _log_template_file is None: _log_template_file = log_template_file with open(_log_template_file, "r") as templ: _log_template = jinja2env.from_string(templ.read()) if _src_template_file is None: _src_template_file = src_template_file with open(_src_template_file, "r") as templ: _src_template = jinja2env.from_string(templ.read()) def init_dirs(logs_dir, out_dir, top_dir, logs_out_dir): global _logs_dir global _out_dir global _top_dir global _logs_out_dir if _logs_dir is None: _logs_dir = logs_dir if _out_dir is None: _out_dir = out_dir if _top_dir is None: _top_dir = top_dir if _logs_out_dir is None: _logs_out_dir = logs_out_dir def init_meta_tags(meta_tags): global _meta_tags if _meta_tags is None: _meta_tags = meta_tags def init_globals( log_template_file, src_template_file, logs_dir: str, out_dir, top_dir, logs_out_dir, quiet: bool, verbose: bool, meta_tags): init_logger(quiet, verbose) init_templates(log_template_file, src_template_file) init_dirs(logs_dir, out_dir, top_dir, logs_out_dir) init_meta_tags(meta_tags) # NOTE: this works correctly only with numbers shorter than 10 digits def numericSortKey(s: str): # prepend all number occurences with the length of the number r = re.sub(r"\d+", lambda m: str(len(m.group(0))) + m.group(0), s).lower() return r class ReportJinja2Env(jinja2.Environment): def __init__(self, include_dir: str): super().__init__( trim_blocks=True, lstrip_blocks=True, loader=jinja2.FileSystemLoader(include_dir)) self.filters["escape_attr"] = ReportJinja2Env.escapeXmlAttribute self.filters["escape_js_str"] = ReportJinja2Env.escapeJsString self.filters["quote"] = ReportJinja2Env.surroundWithQuotes self.filters["numeric_sort"] = ReportJinja2Env.numericSort self.filters["numeric_dictsort"] = ReportJinja2Env.numericDictSort self.filters["tag_dictsort"] = ReportJinja2Env.tagDictSort @staticmethod def escapeXmlAttribute(value: str): return str(markupsafe.escape(value)).replace("\n", " ") @staticmethod def escapeJsString(value: str): def esc(match: Match): return rf"\x{ord(match.group(0)):02x}" return re.sub(r"[\x00-\x1F\x7F'\"]", esc, value) @staticmethod def surroundWithQuotes(value: str, quot='"'): return quot + str(value) + quot @staticmethod def numericSort(l: List[str]): return sorted(l, key=numericSortKey) @staticmethod def numericDictSort(d: Dict[str, Any]): return sorted(d.items(), key=lambda kv: numericSortKey(kv[0])) # Like numericDictSort, but entries starting with a letter are placed before # entries starting with a digit. @staticmethod def tagDictSort(d: Dict[str, Any]): def tagSortKey(s: str): if len(s) > 0 and s[0].isdigit(): return numericSortKey(s) else: return " " + numericSortKey(s) return sorted(d.items(), key=lambda kv: tagSortKey(kv[0])) def exists_and_is_newer_than(target: str, sources: List[str]): if not os.path.exists(target): return False for s in sources: if (not os.path.exists(s) or os.path.getctime(s) > os.path.getctime(target)): return False return True def totalSize(files): size = 0 for f in files: try: size += os.path.getsize(f) except FileNotFoundError: pass return size def criticalError(msg): _logger.critical(msg) sys.exit(1) def readConfig(filename): config = {} urls = {} try: with open(filename) as f: for l in f: ls = l.strip() # skip lines with comments if re.search(r"^\s*#.*", ls) is not None: continue entry = ls.split("\t") if not 2 <= len(entry) <= 3: raise KeyError("Invalid entry: " + ls) config[entry[0]] = entry[1] # check if we if len(entry) == 3: urls[entry[0]] = entry[2] except (OSError, FileNotFoundError, KeyError) as e: criticalError(f"Unable to parse {config} file - {str(e)}") return config, urls @enum.unique class TestStatus(enum.Enum): NA = "test-na" PASSED = "test-passed" FAILED = "test-failed" VARIED = "test-varied" def __str__(self): return self.value @dataclasses.dataclass class TestResult: log_html_file: str = "" name: str = "" tags: Set[str] = dataclasses.field(default_factory=set) types: Set[str] = dataclasses.field(default_factory=set) results_group: str = "" unsynthesizable: str = "" input_files: List[str] = dataclasses.field(default_factory=list) # Unit: bytes total_input_files_size: int = 0 status: TestStatus = TestStatus.NA exit_code: int = 0 # Unit: seconds timeout: int = 0 # Unit: seconds total_time: float = 0 user_time: float = 0 system_time: float = 0 # Unit: KB ram_usage: float = 0 @dataclasses.dataclass class TagInfo: description: str = "" url: str = "" @dataclasses.dataclass class ToolInfo: # Tool name should be used only for display purposes. Always use a key # from `tools` in `ReportResults` (or another dict where tool ID is # the key) as a runner/tool ID. name: str = "" version: str = "" url: str = "" @dataclasses.dataclass class TagToolResult: tests: List[TestResult] = dataclasses.field(default_factory=list) types: Set[str] = dataclasses.field(default_factory=set) passed_tests: int = 0 @property def total_tests(self): return len(self.tests) @property def status(self) -> TestStatus: if (self.total_tests == 0): return TestStatus.NA elif (self.passed_tests == 0): return TestStatus.FAILED elif (self.passed_tests == self.total_tests): return TestStatus.PASSED return TestStatus.VARIED @dataclasses.dataclass class ToolSummary: # Unit: seconds total_time: float = 0 user_time: float = 0 system_time: float = 0 # Unit: MB max_ram_usage: float = 0 # Unit: KiB/s passed_throughput: float = 0 total_passed_tests: int = 0 total_tests: int = 0 total_passed_tags: int = 0 total_tested_tags: int = 0 @dataclasses.dataclass class GroupData: # key 1 = tag id; key 2 = runner name = runner class name tags_tools: Dict[str, Dict[str, TagToolResult]] = dataclasses.field( default_factory=dict) # key = runner name = runner class name summaries: Dict[str, ToolSummary] = dataclasses.field(default_factory=dict) # key = runner name = runner class name tests: Dict[str, List[TestResult]] = dataclasses.field(default_factory=dict) # GroupData equivalent for data from a single tool @dataclasses.dataclass class PartialGroupData: # key 1 = tag id tags: Dict[str, TagToolResult] = dataclasses.field(default_factory=dict) summary: ToolSummary = dataclasses.field(default_factory=ToolSummary) tests: List[TestResult] = dataclasses.field(default_factory=list) @dataclasses.dataclass class ReportResults: # Results groups (key = results group id) groups: Dict[str, GroupData] = dataclasses.field(default_factory=dict) # key = runner name = runner class name tools: Dict[str, ToolInfo] = dataclasses.field(default_factory=dict) # Tags used in the report. Keys are tag IDs. tags: Dict[str, TagInfo] = dataclasses.field(default_factory=dict) def convertPathsToRelativeLinks(text: str, relative_to: str): """Replaces paths to existing files in "text" with HTML links to them. The matched paths can optionally contain row and column number separated with ":". The generated links are relative to "relative_to" and their target (frame in which they open) is "file-frame". Designed for finding references to input files in tools' output. Args: text: Escaped (for use in HTML) text. relative_to: Directory to which the generated urls will be relative. Returns: Text in which paths are replaced with HTML links. """ def convertPath(match: Match): path: str = html.unescape(match.group(1)) if not os.path.exists(path): return match.group(0) if path.startswith(_top_dir): path = path[len(_top_dir) + 1:] elif path.startswith("/"): return match.group(0) url = os.path.join(_out_dir, path + ".html") url = os.path.relpath(url, relative_to) url = urllib.parse.quote(url) esc_match = str(markupsafe.escape(path)) line_no = match.group(3) if line_no is not None: url = f"{url}#l-{line_no}" esc_match = esc_match + (match.group(2) or "") return f'{esc_match}' return _PATH_WITH_LINE_NO_MATCHER.sub(convertPath, text) def renderLogToHTMLFile( log_template, out_dir: str, log_html_path: str, test_result: TestResult, test_log: Dict[str, str], log_content: str): files_map: Dict[str, str] = {} log_html_dir = os.path.dirname(log_html_path) for input_file in test_result.input_files: # Absolute path: input_file_html = os.path.join(_out_dir, input_file + ".html") # Path relative to rendered log: input_file_html = os.path.relpath(input_file_html, log_html_dir) files_map[input_file] = urllib.parse.quote(input_file_html) log_content = convertPathsToRelativeLinks( str(markupsafe.escape(log_content)), log_html_dir) csspath = os.path.join(_out_dir, "log.css") csspath = os.path.relpath(csspath, os.path.dirname(log_html_path)) os.makedirs(os.path.dirname(log_html_path), exist_ok=True) with open(log_html_path, 'w') as f: f.write( log_template.render( input_files_map=files_map, result=test_result, log=test_log, content=log_content, csspath=csspath)) def renderInputFileToHTMLFile( out_dir: str, html_path: str, input_file_path: str, lex): formatter = HtmlFormatter( full=False, linenos=True, anchorlinenos=True, lineanchors='l') os.makedirs(os.path.dirname(html_path), exist_ok=True) raw_code = "" try: with open(input_file_path, 'rb') as f: raw_code = f.read() except IOError: _logger.warning(f"Error when opening file {input_file_path}") try: with open(html_path, 'w') as out: out.write('Error when opening file ' + input_file_path) except IOError: pass return code = highlight(raw_code, lex, formatter) csspath = os.path.join(_out_dir, "code.css") csspath = os.path.relpath(csspath, os.path.dirname(html_path)) with open(html_path, 'w') as out: out.write( _src_template.render( csspath=csspath, filename=input_file_path, code=code)) def renderTagResultsConfig( js_path: str, tool: str, tag: str, test_results: Iterable[TestResult]): tool = tool.lower() tag = tag.lower() js_global_variable_name = f"config_loader_data['{tool}/{tag}']" # Order of values in each entry: # [group, name, status, log_html_path, first_input_file_html_path] config = [] for test_result in test_results: name = test_result.name status = int(test_result.status == TestStatus.PASSED) log_html_file = test_result.log_html_file first_input_html = test_result.input_files[0] + ".html" first_input_html = urllib.parse.quote(first_input_html) group = test_result.results_group config.append([group, name, status, log_html_file, first_input_html]) js_data = json.dumps(config, separators=(",", ":")) code = f"{js_global_variable_name} = {js_data}" os.makedirs(os.path.dirname(js_path), exist_ok=True) with open(js_path, "w") as f: f.write(code) def collect_logs(runner_name: str): @dataclasses.dataclass class LocalPartialGroupData: group: PartialGroupData = dataclasses.field( default_factory=PartialGroupData) # Values used to calculate throughput. Totals are collected only for # files with size > _minimum_throughput_file_size passed_tests_time: float = 0.0 passed_tests_input_files_size: float = 0.0 local_groups: Dict[str, LocalPartialGroupData] = {} tool_info: ToolInfo = ToolInfo() rendered_count = 0 tests_count = 0 for log_file in glob(os.path.join(_logs_dir, runner_name, "**/*.log"), recursive=True): # Strip f"{_logs_dir}/" prefix from log file path t_id = log_file[len(_logs_dir) + 1:] _logger.debug("Found log: " + t_id) # Tests that have not run will have an existing, but empty logfile. if os.path.getsize(log_file) == 0: continue test_result = TestResult() remaining_parameters = { "name", "tags", "should_fail", "rc", "date_completed", "description", "files", "incdirs", "top_module", "runner", "runner_url", "time_elapsed", "type", "mode", "timeout", "user_time", "system_time", "ram_usage", "tool_success", "should_fail_because", "defines", "compatible-runners", "unsynthesizable", "results_group" } test_log_data: Dict[str, Any] = {} log_content = "" with open(log_file, "r") as f: try: for l in f: attr = re.search(r"^([a-zA-Z_-]+):(.+)", l) if attr is None: raise KeyError( "Could not find parameters: {}".format( ", ".join(remaining_parameters))) param = attr.group(1).lower() value = attr.group(2).strip() if param not in remaining_parameters: _logger.warning( "Skipping unknown parameter: {} in {}".format( param, log_file)) continue if param in test_log_data: _logger.warning( "Skipping duplicated parameter: {} in {}".format( param, log_file)) continue test_log_data[param] = value remaining_parameters.remove(param) if len(remaining_parameters) == 0: # found all tags break except Exception as e: _logger.warning( "Skipping {} on {}: {}".format( log_file, runner_name, str(e))) continue log_content = f.read() # Test Result test_result.name = test_log_data["name"] test_result.unsynthesizable = test_log_data["unsynthesizable"] test_result.results_group = test_log_data["results_group"] # Convert splitted "tags" to set() and append all meta-tags test_result.tags = set(test_log_data["tags"].split()) for meta_tag, dependency_tags in _meta_tags.items(): dependency_tags = set(dependency_tags.split()) if not dependency_tags.isdisjoint(test_result.tags): test_result.tags.add(meta_tag) test_result.input_files = [ os.path.relpath(f, _top_dir) for f in test_log_data["files"].split() ] test_result.types = test_log_data["type"].split() test_result.total_input_files_size = totalSize(test_result.input_files) test_result.exit_code = int(test_log_data["rc"]) # Determine test status tool_should_fail = test_log_data["should_fail"] == "1" tool_crashed = test_result.exit_code >= 126 tool_failed = test_log_data["tool_success"] == "0" if tool_crashed or tool_should_fail != tool_failed: test_result.status = TestStatus.FAILED elif (test_log_data["mode"] == "simulation" and not parseLog(log_content)): test_result.status = TestStatus.FAILED else: test_result.status = TestStatus.PASSED test_result.timeout = int(test_log_data["timeout"]) test_result.total_time = float(test_log_data["time_elapsed"]) test_result.user_time = float(test_log_data["user_time"]) test_result.system_time = float(test_log_data["system_time"]) test_result.ram_usage = float(test_log_data["ram_usage"]) # KB log_html = os.path.join(_logs_out_dir, t_id + ".html") test_result.log_html_file = os.path.relpath(log_html, _out_dir) # Render the log if needed if not exists_and_is_newer_than( log_html, [log_file, _log_template_file, __file__]): rendered_count += 1 renderLogToHTMLFile( _log_template, _out_dir, log_html, test_result, test_log_data, log_content) tests_count += 1 # Group local_group = local_groups.setdefault( test_result.results_group, LocalPartialGroupData()) group = local_group.group group.tests.append(test_result) # (tag, tool) results for tag in test_result.tags: tag_data = group.tags.setdefault(tag, TagToolResult()) tag_data.tests.append(test_result) tag_data.types.update(test_result.types) if test_result.status == TestStatus.PASSED: tag_data.passed_tests += 1 # Summary if test_result.status == TestStatus.PASSED: input_files_size = test_result.total_input_files_size if input_files_size > _minimum_throughput_file_size: local_group.passed_tests_input_files_size += input_files_size local_group.passed_tests_time += test_result.total_time summary = group.summary summary.total_time += test_result.total_time summary.user_time += test_result.user_time summary.system_time += test_result.system_time ram_usage_mb = test_result.ram_usage / 1000 if summary.max_ram_usage < ram_usage_mb: summary.max_ram_usage = ram_usage_mb summary.total_tests += 1 if test_result.status == TestStatus.PASSED: summary.total_passed_tests += 1 if tool_info.name == "": tool_info.name = test_log_data["runner"] _logger.info( f"{runner_name}: (Re)generated {rendered_count}/{tests_count} rendered log files." ) all_used_tags: Set[str] = set() for group_id, local_group in local_groups.items(): group = local_group.group all_used_tags.update(group.tags.keys()) for tag_id, tag_tool_result in group.tags.items(): if tag_tool_result.status != TestStatus.NA: group.summary.total_tested_tags += 1 if tag_tool_result.status == TestStatus.PASSED: group.summary.total_passed_tags += 1 tag_tool_result.tests.sort(key=lambda t: numericSortKey(t.name)) time = local_group.passed_tests_time size = local_group.passed_tests_input_files_size if time == 0: group.summary.passed_throughput = 0 else: group.summary.passed_throughput = size / time / 1024 for tag_id in all_used_tags: # List of tag's test lists from all groups tests_lists = [ lg.group.tags[tag_id].tests for lg in local_groups.values() if tag_id in lg.group.tags ] config_js = os.path.join( _out_dir, "results", runner_name.lower(), tag_id.lower() + ".config.js") # Render the config renderTagResultsConfig( config_js, runner_name, tag_id, itertools.chain.from_iterable(tests_lists)) try: with open(os.path.join(_logs_dir, runner_name, "version")) as f: tool_info.version = f.read().strip() except IOError: pass try: with open(os.path.join(_logs_dir, runner_name, "url")) as f: tool_info.url = f.read().strip() except IOError: pass groups: Dict[str, PartialGroupData] = { id: lg.group for id, lg in local_groups.items() } return { "tool_info": tool_info, "partial_groups": groups, } def render_batch(input_files): lex = lexers.get_lexer_by_name("systemverilog") batch_rendered_count = 0 for input_file in input_files: input_file_html = os.path.join(_out_dir, input_file + ".html") if exists_and_is_newer_than( input_file_html, [input_file, _src_template_file, __file__]): continue batch_rendered_count += 1 renderInputFileToHTMLFile(_out_dir, input_file_html, input_file, lex) return batch_rendered_count def main(): parser = argparse.ArgumentParser() logger_args = parser.add_mutually_exclusive_group() logger_args.add_argument( "-q", "--quiet", action="store_true", help="Disable all logs") logger_args.add_argument( "-v", "--verbose", action="store_true", help="Verbose logging") parser.add_argument( "-i", "--input", help="Input database/LRM", default="conf/lrm.conf") parser.add_argument( "-m", "--meta-tags", help="Meta-tags config file", default="conf/meta-tags.conf") parser.add_argument( "-l", "--logs", help="Directory with all the individual test results", default="out/logs") parser.add_argument( "--template", help="Path to the html report template", default="conf/report/report-template.html") parser.add_argument( "--navbar", help="Path to the html navbar template", default="conf/report/navbar-template.html") parser.add_argument( "--code-template", help="Path to the html code preview template", default="conf/report/code-template.html") parser.add_argument( "--log-template", help="Path to the html log template", default="conf/report/log-template.html") parser.add_argument( "-o", "--out", help="Path to the html file with the report", default="out/report/index.html") parser.add_argument( "-c", "--csv", help="Path to the csv file with the report", default="out/report/report.csv") parser.add_argument( "-r", "--revision", help="Report revision", default="unknown") # parse args args = parser.parse_args() init_logger(args.quiet, args.verbose) # Common paths out_dir = os.path.dirname(os.path.abspath(args.out)) top_dir = os.path.abspath(os.curdir) logs_out_dir = os.path.join(out_dir, "logs") # read meta-tags configuration meta_tags, meta_urls = readConfig(args.meta_tags) # generate input database first database, urls = readConfig(args.input) urls = {**urls, **meta_urls} runner_names = [] for r in [os.path.dirname(r) for r in glob(args.logs + "/*/")]: runner_name = os.path.basename(r) _logger.debug("Found Runner: " + runner_name) runner_names.append(runner_name) _logger.info( "Generating {} from log files in '{}'".format(args.out, args.logs)) process_initargs = [ args.log_template, args.code_template, args.logs, out_dir, top_dir, logs_out_dir, args.quiet, args.verbose, meta_tags, ] results = None with multiprocessing.Pool(initializer=init_globals, initargs=process_initargs) as pool: results = pool.map(collect_logs, runner_names) # Input files (.sv) path relative to repository's toplevel directory all_input_files: Set[str] = set() csv_output = {} # Data passed to report template report_data = ReportResults() for tool_name, tool_results in zip(runner_names, results): report_data.tools[tool_name] = tool_results["tool_info"] partial_groups: Dict[str, PartialGroupData] = tool_results["partial_groups"] for group_id, partial_group in partial_groups.items(): group = report_data.groups.setdefault(group_id, GroupData()) group.tests[tool_name] = partial_group.tests group.summaries[tool_name] = partial_group.summary for tag_id, tool_data in partial_group.tags.items(): tools = group.tags_tools.setdefault(tag_id, {}) tools[tool_name] = tool_data if tag_id not in database and tag_id not in report_data.tags: _logger.warning( "Tag not present in the database: " + tag_id) report_data.tags.setdefault( tag_id, TagInfo( description=database.get(tag_id, ""), url=urls.get(tag_id, ""))) for test_result in partial_group.tests: all_input_files.update(test_result.input_files) unique_row = test_result.name + ":" + tool_name csv_output[unique_row] = { "TestName": test_result.name, "Tool": tool_name, "Group": test_result.results_group, "Pass": test_result.status == TestStatus.PASSED, "ExitCode": test_result.exit_code, "Tags": " ".join(test_result.tags), "InputBytes": test_result.total_input_files_size, "AllowedTimeout": test_result.timeout, "TimeUser": round(test_result.user_time, 6), "TimeSystem": round(test_result.system_time, 6), "TimeWall": round(test_result.total_time, 6), "RamUsageMiB": round(test_result.ram_usage / 1024, 3), } ncpu = multiprocessing.cpu_count() batch_size = int(len(all_input_files) / ncpu) + 1 file_batches = [] for i in range(0, len(all_input_files), batch_size): file_batches.append(list(all_input_files)[i:i + batch_size]) # Render input files rendered_count = 0 with multiprocessing.Pool(initializer=init_globals, initargs=process_initargs) as pool: rendered_count = sum(pool.map(render_batch, file_batches)) _logger.info( f"(Re)generated {rendered_count}/{len(all_input_files)} rendered input files." ) try: template_dir = os.path.dirname(args.log_template) jinja2env = ReportJinja2Env(template_dir) with open(args.template, "r") as f: report = jinja2env.from_string(f.read()) build_id = os.environ.get('GITHUB_RUN_ID', 'local') build_datetime = datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S") with open(args.out, 'w') as f: f.write( report.render( report=report_data, revision=args.revision, build_id=build_id, datetime=build_datetime)) with open(args.csv, 'w', newline='') as csvfile: writer = csv.DictWriter(csvfile, fieldnames=_csv_header) writer.writeheader() for test in csv_output: writer.writerow(csv_output[test]) except KeyError: _logger.critical("Unable to generate report, not enough logs") except Exception as e: _logger.critical("Unable to generate report: " + str(e)) if __name__ == "__main__": main()