[
  {
    "path": ".github/workflows/ci.yml",
    "content": "name: ci\non:\n  push:\n  pull_request:\n  workflow_dispatch:\n  schedule:\n    - cron: '30 1 * * *'\n\njobs:\n  build:\n    runs-on: ubuntu-latest\n\n    steps:\n      - uses: actions/checkout@v3\n      - uses: YosysHQ/setup-oss-cad-suite@v2\n        with:\n          github-token: ${{ secrets.GITHUB_TOKEN }}\n      - name: Run checks\n        run: |\n          cd cores/nerv\n          make check -j$(nproc)\n          cd ../picorv32\n          wget -O picorv32.v https://raw.githubusercontent.com/YosysHQ/picorv32/master/picorv32.v\n          python3 ../../checks/genchecks.py\n          make -C checks -j$(nproc)\n"
  },
  {
    "path": ".gitignore",
    "content": "/cores/.gitignore\n"
  },
  {
    "path": "COPYING",
    "content": "Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n"
  },
  {
    "path": "CodeOfConduct",
    "content": "Contributor Covenant Code of Conduct\n\nOur Pledge\n\nIn the interest of fostering an open and welcoming environment, we as\ncontributors and maintainers pledge to making participation in our project and\nour community a harassment-free experience for everyone, regardless of age, body\nsize, disability, ethnicity, gender identity and expression, level of experience,\nnationality, personal appearance, race, religion, or sexual identity and\norientation.\n\nOur Standards\n\nExamples of behavior that contributes to creating a positive environment\ninclude:\n\n* Using welcoming and inclusive language\n* Being respectful of differing viewpoints and experiences\n* Gracefully accepting constructive criticism\n* Focusing on what is best for the community\n* Showing empathy towards other community members\n\nExamples of unacceptable behavior by participants include:\n\n* The use of sexualized language or imagery and unwelcome sexual attention or\n  advances\n* Trolling, insulting/derogatory comments, and personal or political attacks\n* Public or private harassment\n* Publishing others' private information, such as a physical or electronic\n  address, without explicit permission\n* Other conduct which could reasonably be considered inappropriate in a\n  professional setting\n\nOur Responsibilities\n\nProject maintainers are responsible for clarifying the standards of acceptable\nbehavior and are expected to take appropriate and fair corrective action in\nresponse to any instances of unacceptable behavior.\n\nProject maintainers have the right and responsibility to remove, edit, or\nreject comments, commits, code, wiki edits, issues, and other contributions\nthat are not aligned to this Code of Conduct, or to ban temporarily or\npermanently any contributor for other behaviors that they deem inappropriate,\nthreatening, offensive, or harmful.\n\nScope\n\nThis Code of Conduct applies both within project spaces and in public spaces\nwhen an individual is representing the project or its community. Examples of\nrepresenting a project or community include using an official project e-mail\naddress, posting via an official social media account, or acting as an appointed\nrepresentative at an online or offline event. Representation of a project may be\nfurther defined and clarified by project maintainers.\n\nEnforcement\n\nInstances of abusive, harassing, or otherwise unacceptable behavior may be\nreported by contacting the project team at contact@yosyshq.com. All complaints\nwill be reviewed and investigated and will result in a response that is deemed\nnecessary and appropriate to the circumstances. The project team is obligated\nto maintain confidentiality with regard to the reporter of an incident.\nFurther details of specific enforcement policies may be posted separately.\n\nProject maintainers who do not follow or enforce the Code of Conduct in good\nfaith may face temporary or permanent repercussions as determined by other\nmembers of the project's leadership.\n\nAttribution\n\nThis Code of Conduct is adapted from the Contributor Covenant, version 1.4,\navailable at http://contributor-covenant.org/version/1/4/\n"
  },
  {
    "path": "README.md",
    "content": "\nRISC-V Formal Verification Framework\n====================================\n\n**This is work in progress. The interfaces described here are likely to change as the project matures.**\n\nAbout\n-----\n\n`riscv-formal` is a framework for formal verification of RISC-V processors.\n\nIt consists of the following components:\n- A processor-independent formal description of the RISC-V ISA\n- A set of formal testbenches for each processor supported by the framework\n- The specification for the [RISC-V Formal Interface (RVFI)](docs/rvfi.md) that must be implemented by a processor core to interface with `riscv-formal`.\n- Some auxiliary proofs and scripts, for example to prove correctness of the ISA spec agains riscv-isa-sim.\n\nSee [cores/picorv32/](cores/picorv32/) for example bindings for the PicoRV32 processor core.\n\nA processor core usually will implement RVFI as an optional feature that is only enabled for verification. Sequential equivalence check can be used to prove equivalence of the processor versions with and without RVFI.\n\nThe current focus is on implementing formal models of all instructions from the RISC-V RV32I and RV64I ISAs, and formally verifying those models against the models used in the RISC-V \"Spike\" ISA simulator.\n\n`riscv-formal` uses the FOSS SymbiYosys formal verification flow. All properties are expressed using immediate assertions/assumptions for maximal compatibility with other tools.\n\nTable of contents\n-----------------\n\n- [Quickstart Guide](docs/quickstart.md)\n- [The RVFI Interface Specification](docs/rvfi.md)\n- [RISC-V Formal CSR Sematics](docs/csrs.md)\n- [Configuration macros used by riscv-formal](docs/config.md)\n- [The riscv-formal Verification Procedure](docs/procedure.md)\n- [Examples of bugs found with riscv-formal](docs/examplebugs.md)\n- [References and related work](docs/references.md)\n\nConfiguring a new RISC-V processor\n----------------------------------\n\n1. Create a `riscv-formal/cores/<core-name>/` directory\n2. Write a wrapper module that instantiates the core under test and abstracts models of necessary\n   peripherals (usually just memory)\n   - Use the [RVFI helper macros](docs/config.md#rvfi_wires-rvfi_outputs-rvfi_inputs-rvfi_conn)\n     `RVFI_OUTPUTS` and `RVFI_CONN` for quickly defining wrapper connections\n   - See [picorv32/wrapper.sv](cores/picorv32/wrapper.sv) for a simple example wrapper\n3. Write a `checks.cfg` config file for the new core\n   - See [nerv/checks.cfg](cores/nerv/checks.cfg) for an example utilising most of the checks\n   - Refer to [The riscv-formal Verification Procedure](docs/procedure.md) for a complete guide on\n     available checks, and a more detailed view of using `genchecks.py`\n4. Generate checks with `python3 ../../checks/genchecks.py` from the `<core-name>` directory\n   - Checks are generated in `riscv-formal/cores/<core-name>/checks`\n5. Run checks with `make -C checks j$(nproc)`\n\n### Notes\n\n- The [quickstart guide](docs/quickstart.md) goes through the process of running riscv-formal with\n  some of the included cores.  It is recommended to follow this guide before adding a new core.\n- See [picorv32/Makefile](cores/picorv32/Makefile) for an example makefile to manage generation and\n  execution of checks.\n- Out of tree generation with `genchecks.py` is not currently supported.\n- Refer to [docs/config.md](docs/config.md) and [docs/procedure.md](docs/procedure.md) for a\n  breakdown of how to use riscv-formal checks without using `genchecks.py`.\n- The [cover check](docs/procedure.md#cover) can be used to help determine the depth needed for the\n  core to reach certain states as needed for other checks.\n"
  },
  {
    "path": "bus/rvfi_bus_axi4.sv",
    "content": "// RVFI_BUS observer for AXI4 interfaces\n//\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n\n// NOTE: When a W transfer happens before the corresponding AW transfer, the\n// data appears on the RVFI_BUS signals starting with the cycle of that AW\n// transfer, processing at most one W transfer per cycle. This can cause the\n// whole burst to be delayed, potentially also delaying the processing of a\n// following burst's W transfers even when that burst's AW transfer arrived for\n// the first W transfer.\n//\n// An alternative that could process the W transfers before the AW transfers\n// would have to let the solver guess the write addresses. This could cause\n// spurious writes to appear that cause an assertion violation in a cycle\n// before the actual AW transfer arrives that would constrain the guessed write\n// address to be correctly guessed, as the AW transfer cycle is never\n// considered by the solver due to the assertion being violated prior to\n// reaching that.\n//\n// Hence, delaying the processing of W transfers until the corresponding AW\n// transfer happens is less likely to cause false positives for most reasonable\n// properties to check. In any case, writes appear on the RVFI_BUS signals in\n// the exact same order as they appear on the AXI bus. When all AW transfers\n// are guaranteed to arrive in time for their their first W transfer, the\n// writes also appear on the same cycle as the W transfers carrying the data.\n\nmodule rvfi_bus_axi4_observer_write #(\n    parameter AXI_DATA_WIDTH = 32,\n    parameter AXI_ADDRESS_WIDTH = 32,\n    parameter AXI_ID_WIDTH = 1,\n    parameter AXI_AWUSER_WIDTH = 1,\n    parameter AXI_WUSER_WIDTH = 1,\n    parameter AXI_BUSER_WIDTH = 1,\n\n    parameter AXI_ID_MASK = 0,\n    parameter AXI_ID = 0,\n\n    parameter IGNORE_PROT_DATA_INSN = 0,\n\n    parameter DEPTH = 2,\n\n    localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8\n) (\n    input         clock,\n    input         reset,\n\n    // Write Address Channel (AW)\n    input [AXI_ID_WIDTH-1:0]       axi_awid,\n    input [AXI_ADDRESS_WIDTH-1:0]  axi_awaddr,\n    input [3:0]                    axi_awregion,\n    input [7:0]                    axi_awlen,\n    input [2:0]                    axi_awsize,\n    input [1:0]                    axi_awburst,\n    input                          axi_awlock,\n    input [3:0]                    axi_awcache,\n    input [2:0]                    axi_awprot,\n    input [3:0]                    axi_awqos,\n    input [AXI_AWUSER_WIDTH-1:0]   axi_awuser,\n    input                          axi_awvalid,\n    input                          axi_awready,\n    // Write Data Channel (W)\n    input [AXI_DATA_WIDTH-1:0]     axi_wdata,\n    input [AXI_STRB_WIDTH-1:0]     axi_wstrb,\n    input                          axi_wlast,\n    input [AXI_WUSER_WIDTH-1:0]    axi_wuser,\n    input                          axi_wvalid,\n    input                          axi_wready,\n    // Write Response Channel (B)\n    input [AXI_ID_WIDTH-1:0]       axi_bid,\n    input [1:0]                    axi_bresp,\n    input [AXI_BUSER_WIDTH-1:0]    axi_buser,\n    input                          axi_bvalid,\n    input                          axi_bready\n\n    `RVFI_BUS_CHANNEL_OUTPUTS\n);\n\n    wire aw_transfer = axi_awvalid && axi_awready;\n    wire w_transfer = axi_wvalid && axi_wready;\n    wire b_transfer = axi_bvalid && axi_bready;\n\n    wire [AXI_ID_WIDTH-1:0]       out_awid;\n    wire [AXI_ADDRESS_WIDTH-1:0]  out_awaddr;\n    wire [7:0]                    out_awlen;\n    wire [2:0]                    out_awsize;\n    wire [1:0]                    out_awburst;\n    wire [2:0]                    out_awprot;\n\n    wire [AXI_DATA_WIDTH-1:0]     out_wdata;\n    wire [AXI_STRB_WIDTH-1:0]     out_wstrb;\n    wire                          out_wlast;\n\n    wire aw_fifo_in_ready, aw_fifo_out_valid;\n    wire w_fifo_in_ready, w_fifo_out_valid;\n    wire fut_b_fifo_in_ready, fut_b_fifo_out_valid;\n\n    `rvformal_rand_reg [1:0] rand_bresp;\n    wire [1:0] out_aw_bresp;\n    wire [1:0] out_bresp;\n\n    rvfi_bus_util_fifo #(\n        .DEPTH(DEPTH),\n        .WIDTH(AXI_ID_WIDTH + AXI_ADDRESS_WIDTH + 8 + 3 + 2 + 3 + 2)\n    ) aw_fifo (\n        .clock(clock),\n        .reset(reset),\n\n        .in_data( {axi_awid, axi_awaddr, axi_awlen, axi_awsize, axi_awburst, axi_awprot, rand_bresp}),\n        .out_data({out_awid, out_awaddr, out_awlen, out_awsize, out_awburst, out_awprot, out_aw_bresp}),\n\n        .in_valid(aw_transfer),\n        .in_ready(aw_fifo_in_ready),\n        .out_ready(w_fifo_out_valid && out_wlast),\n        .out_valid(aw_fifo_out_valid)\n    );\n\n    rvfi_bus_util_fifo #(\n        .DEPTH(DEPTH),\n        .WIDTH(AXI_DATA_WIDTH + AXI_STRB_WIDTH + 1)\n    ) w_fifo (\n        .clock(clock),\n        .reset(reset),\n\n        .in_data( {axi_wdata, axi_wstrb, axi_wlast}),\n        .out_data({out_wdata, out_wstrb, out_wlast}),\n\n        .in_valid(w_transfer),\n        .in_ready(w_fifo_in_ready),\n        .out_ready(aw_fifo_out_valid),\n        .out_valid(w_fifo_out_valid)\n    );\n\n    // We enqueue a guessed bresp value when we see an AW transfer and dequeue\n    // it when we see a B transfer, then assuming we made a  correct guess.\n    // This doesn't have the same problem described in the note above, as the B\n    // channel is read by the AXI manager and any reasonable property of the\n    // AXI manager regarding the B response cannot fail before the AXI manager\n    // actually reads that response.\n    rvfi_bus_util_fifo #(\n        .DEPTH(DEPTH),\n        .WIDTH(2)\n    ) fut_b_fifo (\n        .clock(clock),\n        .reset(reset),\n\n        .in_data( {rand_bresp}),\n        .out_data({out_bresp}),\n\n        .in_valid(aw_transfer),\n        .in_ready(fut_b_fifo_in_ready),\n        .out_ready(b_transfer),\n        .out_valid(fut_b_fifo_out_valid)\n    );\n\n    always @(posedge clock) begin\n        if (!reset) begin\n            if (aw_transfer)\n                DEPTH_too_small_AW: assert (aw_fifo_in_ready);\n            if (aw_transfer)\n                DEPTH_too_small_B: assert (fut_b_fifo_in_ready);\n            if (w_transfer)\n                DEPTH_too_small_W: assert (w_fifo_in_ready);\n        end\n    end\n\n    reg [7:0] burst_counter;\n    reg [AXI_ADDRESS_WIDTH-1:0] burst_offset;\n\n    always @(posedge clock) begin\n        if (w_fifo_out_valid && aw_fifo_out_valid) begin\n            if (!reset)\n                assert (out_wlast == (burst_counter == out_awlen));\n            if (out_wlast) begin\n                burst_counter <= 0;\n                burst_offset <= 0;\n            end else begin\n                burst_counter <= burst_counter + 1'b1;\n                burst_offset <= burst_offset + (1'b1 << out_awsize);\n            end\n        end\n        if (reset) begin\n            burst_counter <= 0;\n            burst_offset <= 0;\n        end\n    end\n\n    // Mask of address bits that can change between transfers of the same burst\n    // given the current burst type. This is used to compute the unaligned\n    // transfer address.\n    reg [AXI_ADDRESS_WIDTH-1:0] burst_mask;\n\n    // Log2 of the burst length, used to compute the burst mask for the WRAP\n    // burst type.\n    reg [2:0] burst_len_log2;\n\n    // Current transfer address, not aligned.\n    //\n    // When unaligned, it stays unaligned for the entire burst and always\n    // increments by the burst size. This means that transfers past the initial\n    // can include bytes below this address down to the next size aligned\n    // address.\n    wire [AXI_ADDRESS_WIDTH-1:0] unaligned_addr =\n        ( burst_mask & (out_awaddr + burst_offset)) |\n        (~burst_mask & out_awaddr);\n\n    // Current transfer address, aligned to the burst size.\n    wire [AXI_ADDRESS_WIDTH-1:0] size_aligned_addr =\n        unaligned_addr & ('1 << out_awsize);\n\n    // Current transfer address, aligned to the bus width.\n    wire [AXI_ADDRESS_WIDTH-1:0] bus_aligned_addr =\n        unaligned_addr & ~(AXI_DATA_WIDTH/8 - 1);\n\n    // Mask of data bytes/strobe bits that are active given the current\n    // transfer address and burst size.\n    wire [AXI_DATA_WIDTH/8-1:0] size_mask =\n        (~('1 << (1 << out_awsize))) << (size_aligned_addr ^ bus_aligned_addr);\n\n    // Mask of data bytes/strobe bits that are active given the current\n    // misalignment (subset of size_mask). After the initial transfer in a\n    // burst, this is always the same as size_mask, as the transfer includes\n    // the remaining bytes that did not fit into the previous transfer.\n    wire [AXI_DATA_WIDTH/8-1:0] alignment_mask =\n        burst_counter ? size_mask : size_mask & (size_mask << (unaligned_addr ^ size_aligned_addr));\n\n    always @* begin\n        case (out_awlen)\n            8'h00: burst_len_log2 = 0;\n            8'h01: burst_len_log2 = 1;\n            8'h03: burst_len_log2 = 2;\n            8'h07: burst_len_log2 = 3;\n            8'h0f: burst_len_log2 = 4;\n            default: begin\n                burst_len_log2 = 0;\n                AWLEN_invalid_for_AWBURST: assert (reset || !aw_fifo_out_valid || out_awburst != 2'b10);\n            end\n        endcase\n        case (out_awburst)\n            // FIXED\n            2'b00: burst_mask = '0;\n            // INCR\n            2'b01: burst_mask = '1;\n            // WRAP\n            2'b10: burst_mask = ~('1 << (out_awsize + burst_len_log2));\n            // reserved\n            default: begin\n                burst_mask = '0;\n                AWBURST_invalid: assert (reset || !aw_fifo_out_valid);\n            end\n        endcase\n    end\n\n    // The AXI spec says that the wstrb bits are restricted by the burst size\n    // and alignment.\n    //\n    // Choosing to pass on invalid wstrb bits or to implicitly clear them could\n    // hide bugs in designs that do produce such invalid strobe bits, so we are\n    // checking this here.\n    always @(posedge clock) begin\n        if (!reset && rvfi_bus_valid)\n            WSTRB_invalid: assert (!(out_wstrb & ~alignment_mask));\n    end\n\n    always @(posedge clock) begin\n        if (!reset) begin\n            if (b_transfer) begin\n                unexpected_B_transfer: assert (fut_b_fifo_out_valid);\n\n                // Only assume this when we can actually pull a not-yet\n                // constrained value from the FIFO, so that this assumption\n                // cannot hide any AXI signalling errors.\n                assume ((out_bresp == axi_bresp) || !fut_b_fifo_out_valid);\n            end\n        end\n    end\n\n`ifdef RISCV_FORMAL_BUS\n    initial begin\n        BUSLEN_too_small: assert (AXI_DATA_WIDTH <= `RISCV_FORMAL_BUSLEN);\n        XLEN_too_small: assert (AXI_ADDRESS_WIDTH <= `RISCV_FORMAL_XLEN);\n    end\n`endif\n\n    assign rvfi_bus_rdata = '0;\n    assign rvfi_bus_wdata = out_wdata;\n    assign rvfi_bus_wmask = out_wstrb;\n    assign rvfi_bus_addr = bus_aligned_addr;\n\n    assign rvfi_bus_insn = !IGNORE_PROT_DATA_INSN && out_awprot[2];\n    assign rvfi_bus_data = IGNORE_PROT_DATA_INSN || !out_awprot[2];\n\n    assign rvfi_bus_rmask = 0;\n    assign rvfi_bus_fault = out_aw_bresp[1];\n    assign rvfi_bus_valid = w_fifo_out_valid && aw_fifo_out_valid && ((out_awid & AXI_ID_MASK) == AXI_ID);\nendmodule\n\nmodule rvfi_bus_axi4_observer_read #(\n    parameter AXI_DATA_WIDTH = 32,\n    parameter AXI_ADDRESS_WIDTH = 32,\n    parameter AXI_ID_WIDTH = 1,\n    parameter AXI_ARUSER_WIDTH = 1,\n    parameter AXI_RUSER_WIDTH = 1,\n\n    parameter AXI_ID_MASK = 0,\n    parameter AXI_ID = 0,\n\n    parameter DEPTH = 2,\n\n    parameter IGNORE_PROT_DATA_INSN = 0\n) (\n    input         clock,\n    input         reset,\n\n    // Read Address Channel (AR)\n    input [AXI_ID_WIDTH-1:0]       axi_arid,\n    input [AXI_ADDRESS_WIDTH-1:0]  axi_araddr,\n    input [3:0]                    axi_arregion,\n    input [7:0]                    axi_arlen,\n    input [2:0]                    axi_arsize,\n    input [1:0]                    axi_arburst,\n    input                          axi_arlock,\n    input [3:0]                    axi_arcache,\n    input [2:0]                    axi_arprot,\n    input [3:0]                    axi_arqos,\n    input [AXI_ARUSER_WIDTH-1:0]   axi_aruser,\n    input                          axi_arvalid,\n    input                          axi_arready,\n    // Read Data Channel (R)\n    input [AXI_ID_WIDTH-1:0]       axi_rid,\n    input [AXI_DATA_WIDTH-1:0]     axi_rdata,\n    input [1:0]                    axi_rresp,\n    input                          axi_rlast,\n    input [AXI_RUSER_WIDTH-1:0]    axi_ruser,\n    input                          axi_rvalid,\n    input                          axi_rready\n\n    `RVFI_BUS_CHANNEL_OUTPUTS\n);\n\n    wire ar_transfer = axi_arvalid && axi_arready;\n    wire r_transfer = axi_rvalid && axi_rready;\n\n    wire ar_transfer_match = ar_transfer && ((axi_arid & AXI_ID_MASK) == AXI_ID);\n    wire r_transfer_match = r_transfer && ((axi_rid & AXI_ID_MASK) == AXI_ID);\n\n    wire [AXI_ADDRESS_WIDTH-1:0]  out_araddr;\n    wire [7:0]                    out_arlen;\n    wire [2:0]                    out_arsize;\n    wire [1:0]                    out_arburst;\n    wire [2:0]                    out_arprot;\n\n    wire fifo_in_ready, fifo_out_valid;\n\n    rvfi_bus_util_fifo #(\n        .DEPTH(DEPTH),\n        .WIDTH(AXI_ADDRESS_WIDTH + 8 + 3 + 2 + 3)\n    ) aw_fifo (\n        .clock(clock),\n        .reset(reset),\n\n        .in_data( {axi_araddr, axi_arlen, axi_arsize, axi_arburst, axi_arprot}),\n        .out_data({out_araddr, out_arlen, out_arsize, out_arburst, out_arprot}),\n\n        .in_valid(ar_transfer_match),\n        .in_ready(fifo_in_ready),\n        .out_ready(r_transfer_match && axi_rlast),\n        .out_valid(fifo_out_valid)\n    );\n\n    always @(posedge clock) begin\n        if (!reset) begin\n            if (ar_transfer_match)\n                DEPTH_too_small: assert (fifo_in_ready);\n            if (r_transfer_match)\n                unexpected_R_transfer: assert (fifo_out_valid);\n        end\n    end\n\n    reg [7:0] burst_counter;\n    reg [AXI_ADDRESS_WIDTH-1:0] burst_offset;\n\n    always @(posedge clock) begin\n        if (r_transfer_match) begin\n            if (!reset)\n                RLAST_invalid: assert (axi_rlast == (burst_counter == out_arlen));\n\n            if (axi_rlast) begin\n                burst_counter <= 0;\n                burst_offset <= 0;\n            end else begin\n                burst_counter <= burst_counter + 1'b1;\n                burst_offset <= burst_offset + (1 << out_arsize);\n            end\n        end\n        if (reset) begin\n            burst_counter <= 0;\n            burst_offset <= 0;\n        end\n    end\n\n    // Mask of address bits that can change between transfers of the same burst\n    // given the current burst type. This is used to compute the unaligned\n    // transfer address.\n    reg [AXI_ADDRESS_WIDTH-1:0] burst_mask;\n\n    // Log2 of the burst length, used to compute the burst mask for the WRAP\n    // burst type.\n    reg [2:0] burst_len_log2;\n\n    // Current transfer address, not aligned.\n    //\n    // When unaligned, it stays unaligned for the entire burst and always\n    // increments by the burst size. This means that transfers past the initial\n    // can include bytes below this address down to the next size aligned\n    // address.\n    wire [AXI_ADDRESS_WIDTH-1:0] unaligned_addr =\n        ( burst_mask & (out_araddr + burst_offset)) |\n        (~burst_mask & out_araddr);\n\n    // Current transfer address, aligned to the burst size.\n    wire [AXI_ADDRESS_WIDTH-1:0] size_aligned_addr =\n        unaligned_addr & ('1 << out_arsize);\n\n    // Current transfer address, aligned to the bus width.\n    wire [AXI_ADDRESS_WIDTH-1:0] bus_aligned_addr =\n        unaligned_addr & ~(AXI_DATA_WIDTH/8 - 1);\n\n    // Mask of data bytes/strobe bits that are active given the current\n    // transfer address and burst size.\n    wire [AXI_DATA_WIDTH/8-1:0] size_mask =\n        (~('1 << (1 << out_arsize))) << (size_aligned_addr ^ bus_aligned_addr);\n\n    // Mask of data bytes/strobe bits that are active given the current\n    // misalignment (subset of size_mask). After the initial transfer in a\n    // burst, this is always the same as size_mask, as the transfer includes\n    // the remaining bytes that did not fit into the previous transfer.\n    wire [AXI_DATA_WIDTH/8-1:0] alignment_mask =\n        burst_counter ? size_mask : size_mask & (size_mask << (unaligned_addr ^ size_aligned_addr));\n\n    always @* begin\n        case (out_arlen)\n            8'h00: burst_len_log2 = 0;\n            8'h01: burst_len_log2 = 1;\n            8'h03: burst_len_log2 = 2;\n            8'h07: burst_len_log2 = 3;\n            8'h0f: burst_len_log2 = 4;\n            default: begin\n                burst_len_log2 = 0;\n                ARLEN_invalid_for_ARBURST: assert (reset || !fifo_out_valid || out_arburst != 2'b10);\n            end\n        endcase\n        case (out_arburst)\n            // FIXED\n            2'b00: burst_mask = '0;\n            // INCR\n            2'b01: burst_mask = '1;\n            // WRAP\n            2'b10: burst_mask = ~('1 << (out_arsize + burst_len_log2));\n            // reserved\n            default: begin\n                burst_mask = '0;\n                ARBURST_invalid: assert (reset || !fifo_out_valid);\n            end\n        endcase\n    end\n\n`ifdef RISCV_FORMAL_BUS\n    initial begin\n        BUSLEN_too_small: assert (AXI_DATA_WIDTH <= `RISCV_FORMAL_BUSLEN);\n        XLEN_too_small: assert (AXI_ADDRESS_WIDTH <= `RISCV_FORMAL_XLEN);\n    end\n`endif\n\n    assign rvfi_bus_rdata = axi_rdata;\n    assign rvfi_bus_wdata = '0;\n    assign rvfi_bus_addr = bus_aligned_addr;\n    assign rvfi_bus_rmask = alignment_mask;\n    assign rvfi_bus_insn = IGNORE_PROT_DATA_INSN || out_arprot[2];\n    assign rvfi_bus_data = IGNORE_PROT_DATA_INSN || !out_arprot[2];\n\n    assign rvfi_bus_wmask = 0;\n    assign rvfi_bus_fault = axi_rresp[1];\n    assign rvfi_bus_valid = r_transfer_match;\nendmodule\n\nmodule rvfi_bus_axi4_abstract_read #(\n    parameter AXI_ADDRESS_WIDTH = 32,\n    parameter AXI_DATA_WIDTH = 32,\n    parameter AXI_ID_WIDTH = 1,\n    parameter AXI_ARUSER_WIDTH = 1,\n    parameter AXI_RUSER_WIDTH = 1,\n\n    parameter DEPTH = 2\n) (\n    input wire clock,\n    input wire reset,\n\n    // Read Address Channel (AR)\n    input wire [AXI_ID_WIDTH-1:0]       axi_arid,\n    input wire [AXI_ADDRESS_WIDTH-1:0]  axi_araddr,\n    input wire [3:0]                    axi_arregion,\n    input wire [7:0]                    axi_arlen,\n    input wire [2:0]                    axi_arsize,\n    input wire [1:0]                    axi_arburst,\n    input wire                          axi_arlock,\n    input wire [3:0]                    axi_arcache,\n    input wire [2:0]                    axi_arprot,\n    input wire [3:0]                    axi_arqos,\n    input wire [AXI_ARUSER_WIDTH-1:0]   axi_aruser,\n    input wire                          axi_arvalid,\n    output var                          axi_arready,\n    // Read Data Channel (R)\n    output var [AXI_ID_WIDTH-1:0]       axi_rid,\n    output var [AXI_DATA_WIDTH-1:0]     axi_rdata,\n    output var [1:0]                    axi_rresp,\n    output var                          axi_rlast,\n    output var [AXI_RUSER_WIDTH-1:0]    axi_ruser,\n    output var                          axi_rvalid,\n    input wire                          axi_rready\n);\n\n    `rvformal_rand_reg                       rand_arready;\n    `rvformal_rand_reg [AXI_ID_WIDTH-1:0]    rand_rid;\n    `rvformal_rand_reg [AXI_DATA_WIDTH-1:0]  rand_rdata;\n    `rvformal_rand_reg [1:0]                 rand_rresp;\n    `rvformal_rand_reg                       rand_rlast;\n    `rvformal_rand_reg [AXI_RUSER_WIDTH-1:0] rand_ruser;\n    `rvformal_rand_reg                       rand_rvalid;\n\n    logic reset_q;\n\n    // Read Address Channel (AR)\n    logic [AXI_ID_WIDTH-1:0]       axi_arid_q;\n    logic [AXI_ADDRESS_WIDTH-1:0]  axi_araddr_q;\n    logic [3:0]                    axi_arregion_q;\n    logic [7:0]                    axi_arlen_q;\n    logic [2:0]                    axi_arsize_q;\n    logic [1:0]                    axi_arburst_q;\n    logic                          axi_arlock_q;\n    logic [3:0]                    axi_arcache_q;\n    logic [2:0]                    axi_arprot_q;\n    logic [3:0]                    axi_arqos_q;\n    logic [AXI_ARUSER_WIDTH-1:0]   axi_aruser_q;\n    logic                          axi_arvalid_q;\n    logic                          axi_arready_q;\n    // Read Data Channel (R)\n    logic [AXI_ID_WIDTH-1:0]       axi_rid_q;\n    logic [AXI_DATA_WIDTH-1:0]     axi_rdata_q;\n    logic [1:0]                    axi_rresp_q;\n    logic                          axi_rlast_q;\n    logic [AXI_RUSER_WIDTH-1:0]    axi_ruser_q;\n    logic                          axi_rvalid_q;\n    logic                          axi_rready_q;\n\n    always @(posedge clock) begin\n        reset_q <= reset;\n        axi_arid_q <= axi_arid;\n        axi_araddr_q <= axi_araddr;\n        axi_arregion_q <= axi_arregion;\n        axi_arlen_q <= axi_arlen;\n        axi_arsize_q <= axi_arsize;\n        axi_arburst_q <= axi_arburst;\n        axi_arlock_q <= axi_arlock;\n        axi_arcache_q <= axi_arcache;\n        axi_arprot_q <= axi_arprot;\n        axi_arqos_q <= axi_arqos;\n        axi_aruser_q <= axi_aruser;\n        axi_arvalid_q <= axi_arvalid;\n        axi_arready_q <= axi_arready;\n        axi_rid_q <= axi_rid;\n        axi_rdata_q <= axi_rdata;\n        axi_rresp_q <= axi_rresp;\n        axi_rlast_q <= axi_rlast;\n        axi_ruser_q <= axi_ruser;\n        axi_rvalid_q <= axi_rvalid;\n        axi_rready_q <= axi_rready;\n    end\n\n    wire logic ar_transfer   = axi_arvalid   && axi_arready;\n    wire logic ar_transfer_q = axi_arvalid_q && axi_arready_q;\n    wire logic r_transfer    = axi_rvalid    && axi_rready;\n    wire logic r_transfer_q  = axi_rvalid_q  && axi_rready_q;\n\n    wire logic r_new = axi_rvalid && (!axi_rvalid_q || axi_rready_q);\n\n    wire logic r_stable = axi_rvalid_q && !axi_rvalid_q;\n\n    assign axi_arready = rand_arready;\n\n    assign axi_rid    = r_stable ? axi_rid_q    : rand_rid;\n    assign axi_rdata  = r_stable ? axi_rdata_q  : rand_rdata;\n    assign axi_rresp  = r_stable ? axi_rresp_q  : rand_rresp;\n    assign axi_rlast  = r_stable ? axi_rlast_q  : rand_rlast;\n    assign axi_ruser  = r_stable ? axi_ruser_q  : rand_ruser;\n    assign axi_rvalid = r_stable ? axi_rvalid_q : rand_rvalid;\n\n    logic [AXI_ID_WIDTH-1:0] read_id [0:DEPTH];\n    logic [AXI_ID_WIDTH-1:0] read_id_q [0:DEPTH];\n    logic [7:0] read_len [0:DEPTH];\n    logic [7:0] read_len_q [0:DEPTH];\n    logic [DEPTH:0] ar_mask;\n    logic [DEPTH:0] ar_mask_q;\n\n    logic matched;\n    logic last_read;\n\n    always @* begin\n        for (int i = 0; i <= DEPTH; i++) begin\n            read_id[i] = read_id_q[i];\n            read_len[i] = read_len_q[i];\n        end\n\n        matched = 0;\n        last_read = 0;\n        ar_mask = 0;\n        if (!reset) begin\n            ar_mask = ar_mask_q;\n\n            if (ar_transfer_q) begin\n                // insert new read burst\n                assume(!ar_mask[0]);\n\n                for (int i = 0; i <= DEPTH; i++) begin\n                    if (!ar_mask[i]) begin\n                        read_id[i] = axi_arid_q;\n                        read_len[i] = axi_arlen_q;\n                    end\n                end\n\n                ar_mask = (ar_mask << 1) | 1'b1;\n            end\n\n            if (r_new) begin\n                // update oldest read burst with a matching id, removing it\n                // when it is completed\n                for (int i = DEPTH; i >= 0; i--) begin\n                    if (!matched && ar_mask[i] && read_id[i] == axi_rid) begin\n                        matched = 1;\n                        if (read_len[i] > 0) begin\n                            read_len[i] -= 1;\n                        end else begin\n                            last_read = 1;\n                        end\n                    end\n\n                    if (last_read) begin\n                        if (i > 0) begin\n                            read_len[i] = read_len[i - 1];\n                        end\n                    end\n                end\n\n                assume (matched);\n                assume (axi_rlast == last_read);\n\n                if (last_read) begin\n                    ar_mask >>= 1;\n                end\n            end\n        end\n    end\n\n    always @(posedge clock) begin\n        for (int i = 0; i <= DEPTH; i++) begin\n            read_id_q[i] <= read_id[i];\n            read_len_q[i] <= read_len[i];\n        end\n        ar_mask_q <= ar_mask;\n    end\nendmodule\n\nmodule rvfi_bus_axi4_abstract_write #(\n    parameter AXI_ADDRESS_WIDTH = 32,\n    parameter AXI_DATA_WIDTH = 32,\n    parameter AXI_ID_WIDTH = 1,\n    parameter AXI_AWUSER_WIDTH = 1,\n    parameter AXI_WUSER_WIDTH = 1,\n    parameter AXI_BUSER_WIDTH = 1,\n\n    parameter DEPTH = 2,\n\n    localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8\n) (\n    input wire clock,\n    input wire reset,\n\n    // Write Address Channel (AW)\n    input wire [AXI_ID_WIDTH-1:0]       axi_awid,\n    input wire [AXI_ADDRESS_WIDTH-1:0]  axi_awaddr,\n    input wire [3:0]                    axi_awregion,\n    input wire [7:0]                    axi_awlen,\n    input wire [2:0]                    axi_awsize,\n    input wire [1:0]                    axi_awburst,\n    input wire                          axi_awlock,\n    input wire [3:0]                    axi_awcache,\n    input wire [2:0]                    axi_awprot,\n    input wire [3:0]                    axi_awqos,\n    input wire [AXI_AWUSER_WIDTH-1:0]   axi_awuser,\n    input wire                          axi_awvalid,\n    output var                          axi_awready,\n    // Write Data Channel (W)\n    input wire [AXI_DATA_WIDTH-1:0]     axi_wdata,\n    input wire [AXI_STRB_WIDTH-1:0]     axi_wstrb,\n    input wire                          axi_wlast,\n    input wire [AXI_WUSER_WIDTH-1:0]    axi_wuser,\n    input wire                          axi_wvalid,\n    output var                          axi_wready,\n    // Write Response Channel (B)\n    output var [AXI_ID_WIDTH-1:0]       axi_bid,\n    output var [1:0]                    axi_bresp,\n    output var [AXI_BUSER_WIDTH-1:0]    axi_buser,\n    output var                          axi_bvalid,\n    input wire                          axi_bready\n);\n\n    `rvformal_rand_reg                       rand_awready;\n    `rvformal_rand_reg                       rand_wready;\n    `rvformal_rand_reg [AXI_ID_WIDTH-1:0]    rand_bid;\n    `rvformal_rand_reg [1:0]                 rand_bresp;\n    `rvformal_rand_reg [AXI_BUSER_WIDTH-1:0] rand_buser;\n    `rvformal_rand_reg                       rand_bvalid;\n\n    logic reset_q;\n\n    // Write Address Channel (AW)\n    logic [AXI_ID_WIDTH-1:0]       axi_awid_q;\n    logic [AXI_ADDRESS_WIDTH-1:0]  axi_awaddr_q;\n    logic [3:0]                    axi_awregion_q;\n    logic [7:0]                    axi_awlen_q;\n    logic [2:0]                    axi_awsize_q;\n    logic [1:0]                    axi_awburst_q;\n    logic                          axi_awlock_q;\n    logic [3:0]                    axi_awcache_q;\n    logic [2:0]                    axi_awprot_q;\n    logic [3:0]                    axi_awqos_q;\n    logic [AXI_AWUSER_WIDTH-1:0]   axi_awuser_q;\n    logic                          axi_awvalid_q;\n    logic                          axi_awready_q;\n    // Write Data Channel (W)\n    logic [AXI_DATA_WIDTH-1:0]     axi_wdata_q;\n    logic [AXI_STRB_WIDTH-1:0]     axi_wstrb_q;\n    logic                          axi_wlast_q;\n    logic [AXI_WUSER_WIDTH-1:0]    axi_wuser_q;\n    logic                          axi_wvalid_q;\n    logic                          axi_wready_q;\n    // Write Response Channel (B)\n    logic [AXI_ID_WIDTH-1:0]       axi_bid_q;\n    logic [1:0]                    axi_bresp_q;\n    logic [AXI_BUSER_WIDTH-1:0]    axi_buser_q;\n    logic                          axi_bvalid_q;\n    logic                          axi_bready_q;\n\n    always @(posedge clock) begin\n        reset_q <= reset;\n        axi_awid_q <= axi_awid;\n        axi_awaddr_q <= axi_awaddr;\n        axi_awregion_q <= axi_awregion;\n        axi_awlen_q <= axi_awlen;\n        axi_awsize_q <= axi_awsize;\n        axi_awburst_q <= axi_awburst;\n        axi_awlock_q <= axi_awlock;\n        axi_awcache_q <= axi_awcache;\n        axi_awprot_q <= axi_awprot;\n        axi_awqos_q <= axi_awqos;\n        axi_awuser_q <= axi_awuser;\n        axi_awvalid_q <= axi_awvalid;\n        axi_awready_q <= axi_awready;\n        axi_wdata_q <= axi_wdata;\n        axi_wstrb_q <= axi_wstrb;\n        axi_wlast_q <= axi_wlast;\n        axi_wuser_q <= axi_wuser;\n        axi_wvalid_q <= axi_wvalid;\n        axi_wready_q <= axi_wready;\n        axi_bid_q <= axi_bid;\n        axi_bresp_q <= axi_bresp;\n        axi_buser_q <= axi_buser;\n        axi_bvalid_q <= axi_bvalid;\n        axi_bready_q <= axi_bready;\n    end\n\n    wire logic aw_transfer   = axi_awvalid   && axi_awready;\n    wire logic aw_transfer_q = axi_awvalid_q && axi_awready_q;\n    wire logic w_transfer    = axi_wvalid    && axi_wready;\n    wire logic w_transfer_q  = axi_wvalid_q  && axi_wready_q;\n    wire logic b_transfer    = axi_bvalid    && axi_bready;\n    wire logic b_transfer_q  = axi_bvalid_q  && axi_bready_q;\n\n    wire logic b_stable = axi_bvalid_q && !axi_bready_q;\n\n    wire logic b_new = axi_bvalid && (!axi_bvalid_q || axi_bready_q);\n\n    assign axi_awready = rand_awready;\n    assign axi_wready  = rand_wready;\n\n    assign axi_bid    = b_stable ? axi_bid_q    : rand_bid;\n    assign axi_bresp  = b_stable ? axi_bresp_q  : rand_bresp;\n    assign axi_buser  = b_stable ? axi_buser_q  : rand_buser;\n    assign axi_bvalid = b_stable ? axi_bvalid_q : rand_bvalid;\n\n    logic [AXI_ID_WIDTH-1:0] write_id [0:DEPTH];\n    logic [AXI_ID_WIDTH-1:0] write_id_q [0:DEPTH];\n\n    logic [DEPTH:0] aw_mask;\n    logic [DEPTH:0] aw_mask_q;\n\n    logic [DEPTH:0] wlast_mask;\n    logic [DEPTH:0] wlast_mask_q;\n\n    logic matched;\n\n    always @* begin\n        for (int i = 0; i <= DEPTH; i++) begin\n            write_id[i] = write_id_q[i];\n        end\n\n        aw_mask = 0;\n        wlast_mask = 0;\n        matched = 0;\n\n        if (!reset) begin\n            aw_mask = aw_mask_q;\n            wlast_mask = wlast_mask_q;\n\n            if (aw_transfer_q) begin\n                assume (!aw_mask[0]);\n\n                for (int i = 0; i <= DEPTH; i++) begin\n                    if (!aw_mask[i]) begin\n                        write_id[i] = axi_awid_q;\n                    end\n                end\n                aw_mask = (aw_mask << 1) | 1'b1;\n            end\n\n            if (w_transfer_q && axi_wlast_q) begin\n                assume (wlast_mask[0] == 0);\n                wlast_mask = (wlast_mask << 1) | 1'b1;\n            end\n\n            if (b_new) begin\n                for (int i = DEPTH; i >= 0; i--) begin\n                    if (!matched && aw_mask[i] && wlast_mask[i] && write_id[i] == axi_bid) begin\n                        matched = 1;\n                    end\n\n                    if (matched) begin\n                        if (i > 0) begin\n                           write_id[i] = write_id[i-1];\n                        end\n                    end\n                end\n                assume (matched);\n\n                aw_mask = aw_mask >> 1;\n                wlast_mask = wlast_mask >> 1;\n            end\n        end\n    end\n\n    always @(posedge clock) begin\n        aw_mask_q <= aw_mask;\n        wlast_mask_q <= wlast_mask;\n\n        for (int i = 0; i <= DEPTH; i++) begin\n            write_id_q[i] <= write_id[i];\n        end\n    end\n\nendmodule\n"
  },
  {
    "path": "bus/rvfi_bus_util.sv",
    "content": "// Utility code for RVFI_BUS observers\n//\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_bus_util_fifo_stage #(\n\tparameter WIDTH = 8\n) (\n\tinput clock,\n\tinput reset,\n\n\tinput              in_valid,\n\toutput             in_ready,\n\tinput  [WIDTH-1:0] in_data,\n\n\toutput             out_valid,\n\tinput              out_ready,\n\toutput [WIDTH-1:0] out_data\n);\n\n\treg [WIDTH-1:0] buffered;\n\treg buffer_valid;\n\n\twire in_txn = in_valid && in_ready;\n\twire out_txn = out_valid && out_ready;\n\n\tassign out_data = buffer_valid ? buffered : in_data;\n\tassign in_ready = out_ready || !buffer_valid;\n\tassign out_valid = in_valid || buffer_valid;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tbuffer_valid <= 0;\n\t\tend else begin\n\t\t\tif (in_txn != out_txn)\n\t\t\t\tbuffer_valid <= in_txn;\n\t\tend\n\t\tif (in_txn)\n\t\t\tbuffered <= in_data;\n\tend\n\nendmodule\n\nmodule rvfi_bus_util_fifo #(\n\tparameter WIDTH = 8,\n\tparameter DEPTH = 3\n) (\n\tinput clock,\n\tinput reset,\n\n\tinput              in_valid,\n\toutput             in_ready,\n\tinput  [WIDTH-1:0] in_data,\n\n\toutput             out_valid,\n\tinput              out_ready,\n\toutput [WIDTH-1:0] out_data\n);\n\n\twire [WIDTH-1:0] stage_data [0:DEPTH];\n\twire [DEPTH:0] stage_valid;\n\twire [DEPTH:0] stage_ready;\n\n\tgenvar i;\n\tgenerate for (i = 0; i < DEPTH; i = i + 1) begin\n\t\trvfi_bus_util_fifo_stage #(.WIDTH(WIDTH)) stage (\n\t\t\t.clock(clock),\n\t\t\t.reset(reset),\n\t\t\t.in_data(stage_data[i]),\n\t\t\t.out_data(stage_data[i+1]),\n\t\t\t.in_valid(stage_valid[i]),\n\t\t\t.out_valid(stage_valid[i+1]),\n\t\t\t.in_ready(stage_ready[i]),\n\t\t\t.out_ready(stage_ready[i+1])\n\t\t);\n\tend endgenerate\n\n\tassign stage_valid[0] = in_valid;\n\tassign stage_data[0] = in_data;\n\tassign in_ready = stage_ready[0];\n\n\tassign out_valid = stage_valid[DEPTH];\n\tassign stage_ready[DEPTH] = out_ready;\n\tassign out_data = stage_data[DEPTH];\nendmodule\n"
  },
  {
    "path": "checks/genchecks.py",
    "content": "#!/usr/bin/env python3\n#\n# Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n#\n# Permission to use, copy, modify, and/or distribute this software for any\n# purpose with or without fee is hereby granted, provided that the above\n# copyright notice and this permission notice appear in all copies.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nimport os, sys, shutil, re\nfrom functools import reduce\n\nnret = 1\nisa = \"rv32i\"\nilen = 32\nxlen = 32\nbuslen = 32\nnbus = 1\ncsrs = set()\ncustom_csrs = set()\nillegal_csrs = set()\ncsr_tests = {}\ncsr_spec = None\ncompr = False\n\ndepths = list()\ngroups = [None]\nblackbox = False\n\ncfgname = \"checks\"\nbasedir = f\"{os.getcwd()}/../..\"\ncorename = os.getcwd().split(\"/\")[-1]\nsolver = \"boolector\"\ndumpsmt2 = False\nabspath = False\nsbycmd = \"sby\"\nconfig = dict()\nmode = \"bmc\"\n\nif len(sys.argv) > 1:\n    assert len(sys.argv) == 2\n    cfgname = sys.argv[1]\n\nprint(f\"Reading {cfgname}.cfg.\")\nwith open(f\"{cfgname}.cfg\", \"r\") as f:\n    cfgsection = None\n    cfgsubsection = None\n    for line in f:\n        line = line.strip()\n\n        if line.startswith(\"#\"):\n            continue\n\n        if line.startswith(\"[\") and line.endswith(\"]\"):\n            cfgsection = line.lstrip(\"[\").rstrip(\"]\")\n            cfgsubsection = None\n            if cfgsection.startswith(\"assume \") or cfgsection == \"assume\":\n                cfgsubsection = cfgsection.split()[1:]\n                cfgsection = \"assume\"\n            continue\n\n        if cfgsection is not None:\n            if cfgsubsection is None:\n                if cfgsection not in config:\n                    config[cfgsection] = \"\"\n                config[cfgsection] += f\"{line}\\n\"\n            else:\n                if cfgsection not in config:\n                    config[cfgsection] = []\n                config[cfgsection].append((cfgsubsection, line))\n\nif \"options\" in config:\n    for line in config[\"options\"].split(\"\\n\"):\n        line = line.split()\n\n        if len(line) == 0:\n            continue\n\n        elif line[0] == \"nret\":\n            assert len(line) == 2\n            nret = int(line[1])\n\n        elif line[0] == \"isa\":\n            assert len(line) == 2\n            isa = line[1]\n\n        elif line[0] == \"blackbox\":\n            assert len(line) == 1\n            blackbox = True\n\n        elif line[0] == \"solver\":\n            assert len(line) == 2\n            solver = line[1]\n\n        elif line[0] == \"dumpsmt2\":\n            assert len(line) == 1\n            dumpsmt2 = True\n\n        elif line[0] == \"abspath\":\n            assert len(line) == 1\n            abspath = True\n\n        elif line[0] == \"mode\":\n            assert len(line) == 2\n            assert(line[1] in (\"bmc\", \"prove\", \"cover\"))\n            mode = line[1]\n\n        elif line[0] == \"buslen\":\n            assert len(line) == 2\n            buslen = int(line[1])\n\n        elif line[0] == \"nbus\":\n            assert len(line) == 2\n            nbus = int(line[1])\n\n        elif line[0] == \"csr_spec\":\n            assert len(line) == 2\n            csr_spec = line[1]\n\n        else:\n            print(line)\n            assert 0\n\nif \"64\" in isa:\n    xlen = 64\n\nif \"c\" in isa:\n    compr = True\n\ndef add_csr_tests(name, test_str):\n    # use regex to split by spaces, unless those spaces are inside quotation marks\n    # e.g. const=\"32'h dead_beef\" is one match not two\n    #      const=\"32'h 0\"_mask=\"32'h dead_beef\" is also one match\n    tests = re.findall(\"((?:\\S*?\\\"[^\\\"]*\\\")+|\\S+)\", test_str)\n    csr_tests[name] = tests\n\ndef add_csr(csr_str):\n    try:\n        (name, tests) = csr_str.split(maxsplit=1)\n        add_csr_tests(name, tests)\n    except ValueError: # no tests\n        name = csr_str.strip()\n    csrs.add(name)\n    return name\n\ndef mask_bits(test: str, bits: \"list[int]\", mask_len: int, invert=False):\n    mask = reduce(lambda x, y: x | 1<<y, bits, 0)\n    fstring = f\"{test}_mask={'~' if invert else ''}{mask_len}'b{{:0{mask_len}b}}\"\n    return fstring.format(mask)\n\nif csr_spec == \"1.12\":\n    spec_csrs = {\n        \"mvendorid\"     : [\"const\"],\n        \"marchid\"       : [\"const\"],\n        \"mimpid\"        : [\"const\"],\n        \"mhartid\"       : [\"const\"],\n        \"mconfigptr\"    : [\"const\"],\n        # All reserved bits should be 0\n        \"mstatus\"       : [mask_bits(\"zero\", \n                                     [0, 2, 4, *range(23, 31)] + ([31, *range(38, 63)] if xlen==64 else []), \n                                     xlen)],\n        \"misa\"          : [mask_bits(\"zero\", \n                                     [6, 10, 11, 14, 17, 19, 22, 24, 25, *range(26, xlen-2)], \n                                     xlen)],\n        \"mie\"           : None,\n        \"mtvec\"         : None,\n        \"mscratch\"      : [\"any\"],\n        \"mepc\"          : None,\n        \"mcause\"        : None,\n        \"mtval\"         : None,\n        \"mip\"           : None,\n        \"mcycle\"        : [\"inc\"],\n        \"minstret\"      : [\"inc\"],\n    }\n    spec_csrs.update({f\"mhpmcounter{i}\" : None for i in range(3, 32)})\n    spec_csrs.update({f\"mhpmevent{i}\" : None for i in range(3, 32)})\n\n    restricted_csrs = {\n        \"medeleg\"       : (\"s\",  \"302\", None),\n        \"mideleg\"       : (\"s\",  \"303\", None),\n        \"mcounteren\"    : (\"u\",  \"306\", None),\n        \"mstatush\"      : (\"32\", \"310\", [mask_bits(\"zero\", [4, 5], xlen, invert=True)]),\n        \"mtinst\"        : (\"h\",  \"34A\", None),\n        \"mtval2\"        : (\"h\",  \"34B\", None),\n        \"menvcfg\"       : (\"u\",  \"30A\", None),\n        \"menvcfgh\"      : (\"u\",  \"31A\", None),  # u-mode only *and* 32bit only\n    }\n    for (name, data) in restricted_csrs.items():\n        if data[0] in isa:\n            spec_csrs[name] = data[2]\n        else:\n            illegal_csrs.add(\n                (data[1], \"m\", \"rw\"),\n            )\n\n    for (name, tests) in spec_csrs.items():\n        csrs.add(name)\n        if tests:\n            csr_tests[name] = tests\n\nif \"csrs\" in config:\n    for line in config[\"csrs\"].split(\"\\n\"):\n        if line:\n            add_csr(line)\n\nif \"custom_csrs\" in config:\n    for line in config[\"custom_csrs\"].split(\"\\n\"):\n        try:\n            (addr, levels, csr_str) = line.split(maxsplit=2)\n        except ValueError: # no csr\n            continue\n        name = add_csr(csr_str)\n        custom_csrs.add((name, int(addr, base=16), levels))\n\nif \"illegal_csrs\" in config:\n    for line in config[\"illegal_csrs\"].split(\"\\n\"):\n        line = tuple(line.split())\n\n        if len(line) == 0:\n            continue\n\n        assert len(line) == 3\n        illegal_csrs.add(line)\n\nif \"groups\" in config:\n    groups += config[\"groups\"].split()\n\nprint(f\"Creating {cfgname} directory.\")\nshutil.rmtree(cfgname, ignore_errors=True)\nos.mkdir(cfgname)\n\ndef hfmt(text, **kwargs):\n    lines = []\n    for line in text.split(\"\\n\"):\n        match = re.match(r\"^\\s*: ?(.*)\", line)\n        if match:\n            line = match.group(1)\n        elif line.strip() == \"\":\n            continue\n        lines.append(re.sub(r\"@([a-zA-Z0-9_]+)@\",\n                lambda match: str(kwargs[match.group(1)]), line))\n    return lines\n\ndef print_hfmt(f, text, **kwargs):\n    for line in hfmt(text, **kwargs):\n        print(line, file=f)\n\nhargs = dict()\nhargs[\"basedir\"] = basedir\nhargs[\"core\"] = corename\nhargs[\"nret\"] = nret\nhargs[\"xlen\"] = xlen\nhargs[\"ilen\"] = ilen\nhargs[\"buslen\"] = buslen\nhargs[\"nbus\"] = nbus\nhargs[\"append\"] = 0\nhargs[\"mode\"] = mode\n\nif \"cover\" in config:\n    hargs[\"cover\"] = config[\"cover\"]\n\ninstruction_checks = set()\nconsistency_checks = set()\n\nif solver == \"bmc3\":\n    hargs[\"engine\"] = \"abc bmc3\"\n    hargs[\"ilang_file\"] = f\"{corename}-gates.il\"\nelif solver == \"btormc\":\n    hargs[\"engine\"] = \"btor btormc\"\n    hargs[\"ilang_file\"] = f\"{corename}-hier.il\"\nelse:\n    hargs[\"engine\"] = f\"smtbmc {'--dumpsmt2 ' if dumpsmt2 else ''}{solver}\"\n    hargs[\"ilang_file\"] = f\"{corename}-hier.il\"\n\ndef test_disabled(check):\n    if \"filter-checks\" in config:\n        for line in config[\"filter-checks\"].split(\"\\n\"):\n            line = line.strip().split()\n            if len(line) == 0: continue\n            assert len(line) == 2 and line[0] in [\"-\", \"+\"]\n            if re.match(line[1], check):\n                return line[0] == \"-\"\n    return False\n\ndef get_depth_cfg(patterns):\n    ret = None\n    if \"depth\" in config:\n        for line in config[\"depth\"].split(\"\\n\"):\n            line = line.strip().split()\n            if len(line) == 0:\n                continue\n            for pat in patterns:\n                if re.fullmatch(line[0], pat):\n                    ret = [int(s) for s in line[1:]]\n    return ret\n\ndef print_custom_csrs(sby_file):\n    fstrings = {\n        \"inputs\": \"  ,input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_{csr}_{signal} \\\\\",\n        \"wires\": \"  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_{csr}_{signal}; \\\\\",\n        \"conn\": \"  ,.rvfi_csr_{csr}_{signal} (rvfi_csr_{csr}_{signal}) \\\\\",\n        \"channel\": \"  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_{csr}_{signal} = rvfi_csr_{csr}_{signal} [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\\\",\n        \"signals\": \"`RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_{csr}_{signal}) \\\\\",\n        \"outputs\": \"  ,output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_{csr}_{signal} \\\\\",\n        \"indices\": \"  localparam [11:0] csr_{level}index_{name} = 12'h{index:03X}; \\\\\"\n    }\n    for (macro, fstring) in fstrings.items():\n        if macro == \"channel\":\n            print(f\"`define RISCV_FORMAL_CUSTOM_CSR_{macro.upper()}(_idx) \\\\\" , file=sby_file)\n        else:\n            print(f\"`define RISCV_FORMAL_CUSTOM_CSR_{macro.upper()} \\\\\", file=sby_file)\n        for custom_csr in custom_csrs:\n            name = custom_csr[0]\n            addr = custom_csr[1]\n            levels = custom_csr[2]\n            if macro == \"indices\":\n                for level in [\"m\", \"s\", \"u\"]:\n                    if level in levels:\n                        macro_string = fstring.format(level=level, name=name, index=addr)\n                    else:\n                        macro_string = fstring.format(level=level, name=name, index=0xfff)\n                    print(macro_string, file=sby_file)\n            else:\n                for signal in [\"rmask\", \"wmask\", \"rdata\", \"wdata\"]:\n                    macro_string = fstring.format(csr=name, signal=signal)\n                    print(macro_string, file=sby_file)\n        print(\"\", file=sby_file)\n\n# ------------------------------ Instruction Checkers ------------------------------\n\ndef check_insn(grp, insn, chanidx, csr_mode=False, illegal_csr=False):\n    pf = \"\" if grp is None else grp+\"_\"\n    if illegal_csr:\n        (ill_addr, ill_modes, ill_rw) = insn\n        insn = f\"12'h{int(ill_addr, base=16):03X}\"\n        check = f\"{pf}csr_ill_{ill_addr}_ch{chanidx:d}\"\n        depth_cfg = get_depth_cfg([f\"{pf}csr_ill\", f\"{pf}csr_ill_ch{chanidx:d}\", f\"{pf}csr_ill_{ill_addr}\", f\"{pf}csr_ill_{ill_addr}_ch{chanidx:d}\"])\n    else:\n        if csr_mode:\n            check = \"csrw\"\n        else:\n            check = \"insn\"\n        depth_cfg = get_depth_cfg([f\"{pf}{check}\", f\"{pf}{check}_ch{chanidx:d}\", f\"{pf}{check}_{insn}\", f\"{pf}{check}_{insn}_ch{chanidx:d}\"])\n        check = f\"{pf}{check}_{insn}_ch{chanidx:d}\"\n\n    if depth_cfg is None: return\n    assert len(depth_cfg) == 1\n\n    if test_disabled(check): return\n    instruction_checks.add(check)\n\n    hargs[\"insn\"] = insn\n    hargs[\"checkch\"] = check\n    hargs[\"channel\"] = f\"{chanidx:d}\"\n    hargs[\"depth\"] = depth_cfg[0]\n    hargs[\"depth_plus\"] = depth_cfg[0] + 1\n    hargs[\"skip\"] = depth_cfg[0]\n\n    with open(f\"{cfgname}/{check}.sby\", \"w\") as sby_file:\n        print_hfmt(sby_file, \"\"\"\n                : [options]\n                : mode @mode@\n                : expect pass,fail\n                : append @append@\n                : depth @depth_plus@\n                : skip @skip@\n                :\n                : [engines]\n                : @engine@\n                :\n                : [script]\n        \"\"\", **hargs)\n\n        if \"script-defines\" in config:\n            print_hfmt(sby_file, config[\"script-defines\"], **hargs)\n\n        sv_files = [f\"{check}.sv\"]\n        if \"verilog-files\" in config:\n            sv_files += hfmt(config[\"verilog-files\"], **hargs)\n\n        vhdl_files = []\n        if \"vhdl-files\" in config:\n            vhdl_files += hfmt(config[\"vhdl-files\"], **hargs)\n\n        if len(sv_files):\n            print(f\"read -sv {' '.join(sv_files)}\", file=sby_file)\n\n        if len(vhdl_files):\n            print(f\"read -vhdl {' '.join(vhdl_files)}\", file=sby_file)\n\n        if \"script-sources\" in config:\n            print_hfmt(sby_file, config[\"script-sources\"], **hargs)\n\n        print_hfmt(sby_file, \"\"\"\n                : prep -flatten -nordff -top rvfi_testbench\n        \"\"\", **hargs)\n\n        if \"script-link\" in config:\n            print_hfmt(sby_file, config[\"script-link\"], **hargs)\n\n        print_hfmt(sby_file, \"\"\"\n                : chformal -early\n                :\n                : [files]\n                : @basedir@/checks/rvfi_macros.vh\n                : @basedir@/checks/rvfi_channel.sv\n                : @basedir@/checks/rvfi_testbench.sv\n        \"\"\", **hargs)\n\n        if illegal_csr:\n            print_hfmt(sby_file, \"\"\"\n                    : @basedir@/checks/rvfi_csr_ill_check.sv\n            \"\"\", **hargs)\n        elif csr_mode:\n            print_hfmt(sby_file, \"\"\"\n                    : @basedir@/checks/rvfi_csrw_check.sv\n            \"\"\", **hargs)\n        else:\n            print_hfmt(sby_file, \"\"\"\n                    : @basedir@/checks/rvfi_insn_check.sv\n                    : @basedir@/insns/insn_@insn@.v\n            \"\"\", **hargs)\n\n        print_hfmt(sby_file, \"\"\"\n                :\n                : [file defines.sv]\n                : `define RISCV_FORMAL\n                : `define RISCV_FORMAL_NRET @nret@\n                : `define RISCV_FORMAL_XLEN @xlen@\n                : `define RISCV_FORMAL_ILEN @ilen@\n                : `define RISCV_FORMAL_RESET_CYCLES 1\n                : `define RISCV_FORMAL_CHECK_CYCLE @depth@\n                : `define RISCV_FORMAL_CHANNEL_IDX @channel@\n        \"\"\", **hargs)\n\n        if \"assume\" in config:\n            print(\"`define RISCV_FORMAL_ASSUME\", file=sby_file)\n\n        if mode == \"prove\":\n            print(\"`define RISCV_FORMAL_UNBOUNDED\", file=sby_file)\n\n        for csr in sorted(csrs):\n            print(f\"`define RISCV_FORMAL_CSR_{csr.upper()}\", file=sby_file)\n\n        if csr_mode and insn in (\"mcycle\", \"minstret\"):\n            print(\"`define RISCV_FORMAL_CSRWH\", file=sby_file)\n\n        if illegal_csr:\n            print_hfmt(sby_file, \"\"\"\n                    : `define RISCV_FORMAL_CHECKER rvfi_csr_ill_check\n                    : `define RISCV_FORMAL_ILL_CSR_ADDR @insn@\n            \"\"\", **hargs)\n            if 'm' in ill_modes:\n                print(\"`define RISCV_FORMAL_ILL_MMODE\", file=sby_file)\n            if 's' in ill_modes:\n                print(\"`define RISCV_FORMAL_ILL_SMODE\", file=sby_file)\n            if 'u' in ill_modes:\n                print(\"`define RISCV_FORMAL_ILL_UMODE\", file=sby_file)\n            if 'r' in ill_rw:\n                print(\"`define RISCV_FORMAL_ILL_READ\", file=sby_file)\n            if 'w' in ill_rw:\n                print(\"`define RISCV_FORMAL_ILL_WRITE\", file=sby_file)\n        elif csr_mode:\n            print_hfmt(sby_file, \"\"\"\n                    : `define RISCV_FORMAL_CHECKER rvfi_csrw_check\n                    : `define RISCV_FORMAL_CSRW_NAME @insn@\n            \"\"\", **hargs)\n        else:\n            print_hfmt(sby_file, \"\"\"\n                    : `define RISCV_FORMAL_CHECKER rvfi_insn_check\n                    : `define RISCV_FORMAL_INSN_MODEL rvfi_insn_@insn@\n            \"\"\", **hargs)\n\n        if custom_csrs:\n            print_custom_csrs(sby_file)\n\n        if blackbox:\n            print(\"`define RISCV_FORMAL_BLACKBOX_REGS\", file=sby_file)\n\n        if compr:\n            print(\"`define RISCV_FORMAL_COMPRESSED\", file=sby_file)\n\n        if \"defines\" in config:\n            print_hfmt(sby_file, config[\"defines\"], **hargs)\n\n        print_hfmt(sby_file, \"\"\"\n                : `include \"rvfi_macros.vh\"\n                :\n                : [file @checkch@.sv]\n                : `include \"defines.sv\"\n                : `include \"rvfi_channel.sv\"\n                : `include \"rvfi_testbench.sv\"\n        \"\"\", **hargs)\n\n        if illegal_csr:\n            print_hfmt(sby_file, \"\"\"\n                    : `include \"rvfi_csr_ill_check.sv\"\n            \"\"\", **hargs)\n        elif csr_mode:\n            print_hfmt(sby_file, \"\"\"\n                    : `include \"rvfi_csrw_check.sv\"\n            \"\"\", **hargs)\n        else:\n            print_hfmt(sby_file, \"\"\"\n                    : `include \"rvfi_insn_check.sv\"\n                    : `include \"insn_@insn@.v\"\n            \"\"\", **hargs)\n\n        if \"assume\" in config:\n            print(\"\", file=sby_file)\n            print(\"[file assume_stmts.vh]\", file=sby_file)\n            for pat, line in config[\"assume\"]:\n                enabled = True\n                for p in pat:\n                    if p.startswith(\"!\"):\n                        p = p[1:]\n                        enabled = False\n                    else:\n                        enabled = True\n                    if re.match(p, check):\n                        enabled = not enabled\n                        break\n                if enabled:\n                    print(line, file=sby_file)\n\nfor grp in groups:\n    with open(f\"../../insns/isa_{isa}.txt\") as isa_file:\n        for insn in isa_file:\n            for chanidx in range(nret):\n                check_insn(grp, insn.strip(), chanidx)\n\n    for csr in sorted(csrs):\n        for chanidx in range(nret):\n            check_insn(grp, csr, chanidx, csr_mode=True)\n\n    for ill_csr in sorted(illegal_csrs, key=lambda csr: csr[0]):\n        for chanidx in range(nret):\n            check_insn(grp, ill_csr, chanidx, illegal_csr=True)\n\n# ------------------------------ Consistency Checkers ------------------------------\n\ndef check_cons(grp, check, chanidx=None, start=None, trig=None, depth=None, csr_mode=False, csr_test=None, bus_mode=False):\n    pf = \"\" if grp is None else grp+\"_\"\n    if csr_mode:\n        csr_name = check\n        if csr_test is not None:\n            # Check for provided mask\n            mask_idx = csr_test.find(\"_mask\")\n            if mask_idx >= 0:\n                try:\n                    csr_mask = str(csr_test[mask_idx:]).split('=', maxsplit=1)[1].strip('\"')\n                except IndexError: # no value provided\n                    print(csr_test)\n                    assert 0\n                csr_test = csr_test[:mask_idx]\n            if csr_test.startswith(\"const\"):\n                try:\n                    constval = str(csr_test).split('=', maxsplit=1)[1].strip('\"')\n                except IndexError: # no value provided\n                    constval = \"rdata_shadow\"\n                check = f\"{pf}csrc_const_{csr_name}\"\n                check_name = f\"csrc_const\"\n            elif csr_test.startswith(\"hpm\"):\n                try:\n                    hpmevent = str(csr_test).split('=', maxsplit=1)[1].strip('\"')\n                except IndexError: # no value provided\n                    pass\n                hpmcounter = str(csr_name).replace(\"event\", \"counter\")\n                if hpmcounter not in csrs:\n                    csrs.add(hpmcounter)\n                check = f\"{pf}csrc_hpm_{csr_name}\"\n                check_name = f\"csrc_hpm\"\n            else:\n                check = f\"{pf}csrc_{csr_test}_{csr_name}\"\n                check_name =f\"csrc_{csr_test}\"\n\n        else:\n            check = f\"{pf}csrc_{csr_name}\"\n            check_name = \"csrc\"\n\n        hargs[\"check\"] = check_name\n\n        if chanidx is not None:\n            depth_cfg = get_depth_cfg([f\"{pf}{check_name}\", check, f\"{pf}{check_name}_ch{chanidx:d}\", f\"{check}_ch{chanidx:d}\"])\n            hargs[\"channel\"] = f\"{chanidx:d}\"\n            check = f\"{check}_ch{chanidx:d}\"\n\n        else:\n            depth_cfg = get_depth_cfg([f\"{check_name}\", check])\n    else:\n        hargs[\"check\"] = check\n        check = pf + check\n\n        if chanidx is not None:\n            depth_cfg = get_depth_cfg([check, f\"{check}_ch{chanidx:d}\"])\n            hargs[\"channel\"] = f\"{chanidx:d}\"\n            check = f\"{check}_ch{chanidx:d}\"\n\n        else:\n            depth_cfg = get_depth_cfg([check])\n\n    if depth_cfg is None: return\n\n    if start is not None:\n        start = depth_cfg[start]\n    else:\n        start = 1\n\n    if trig is not None:\n        trig = depth_cfg[trig]\n\n    if depth is not None:\n        depth = depth_cfg[depth]\n\n    hargs[\"start\"] = start\n    hargs[\"depth\"] = depth\n    hargs[\"depth_plus\"] = depth + 1\n    hargs[\"skip\"] = depth\n\n    hargs[\"checkch\"] = check\n\n    hargs[\"xmode\"] = hargs[\"mode\"]\n    if check == \"cover\" or \"csrc_hpm\" in check: hargs[\"xmode\"] = \"cover\"\n\n    if test_disabled(check): return\n    consistency_checks.add(check)\n\n    with open(f\"{cfgname}/{check}.sby\", \"w\") as sby_file:\n        print_hfmt(sby_file, \"\"\"\n                : [options]\n                : mode @xmode@\n                : expect pass,fail\n                : append @append@\n                : depth @depth_plus@\n                : skip @skip@\n                :\n                : [engines]\n                : @engine@\n                :\n                : [script]\n        \"\"\", **hargs)\n\n        if \"script-defines\" in config:\n            print_hfmt(sby_file, config[\"script-defines\"], **hargs)\n\n        if (f\"script-defines {hargs['check']}\") in config:\n            print_hfmt(sby_file, config[f\"script-defines {hargs['check']}\"], **hargs)\n\n        sv_files = [f\"{check}.sv\"]\n        if \"verilog-files\" in config:\n            sv_files += hfmt(config[\"verilog-files\"], **hargs)\n\n        vhdl_files = []\n        if \"vhdl-files\" in config:\n            vhdl_files += hfmt(config[\"vhdl-files\"], **hargs)\n\n        if len(sv_files):\n            print(f\"read -sv {' '.join(sv_files)}\", file=sby_file)\n\n        if len(vhdl_files):\n            print(f\"read -vhdl {' '.join(vhdl_files)}\", file=sby_file)\n\n        if \"script-sources\" in config:\n            print_hfmt(sby_file, config[\"script-sources\"], **hargs)\n\n        print_hfmt(sby_file, \"\"\"\n                : prep -flatten -nordff -top rvfi_testbench\n        \"\"\", **hargs)\n\n        if \"script-link\" in config:\n            print_hfmt(sby_file, config[\"script-link\"], **hargs)\n\n        print_hfmt(sby_file, \"\"\"\n                : chformal -early\n                :\n                : [files]\n                : @basedir@/checks/rvfi_macros.vh\n                : @basedir@/checks/rvfi_channel.sv\n                : @basedir@/checks/rvfi_testbench.sv\n                : @basedir@/checks/rvfi_@check@_check.sv\n                :\n                : [file defines.sv]\n        \"\"\", **hargs)\n\n        print_hfmt(sby_file, \"\"\"\n                : `define RISCV_FORMAL\n                : `define RISCV_FORMAL_NRET @nret@\n                : `define RISCV_FORMAL_XLEN @xlen@\n                : `define RISCV_FORMAL_ILEN @ilen@\n                : `define RISCV_FORMAL_CHECKER rvfi_@check@_check\n                : `define RISCV_FORMAL_RESET_CYCLES @start@\n                : `define RISCV_FORMAL_CHECK_CYCLE @depth@\n        \"\"\", **hargs)\n\n        if \"assume\" in config:\n            print(\"`define RISCV_FORMAL_ASSUME\", file=sby_file)\n\n        if mode == \"prove\":\n            print(\"`define RISCV_FORMAL_UNBOUNDED\", file=sby_file)\n\n        for csr in sorted(csrs):\n            print(f\"`define RISCV_FORMAL_CSR_{csr.upper()}\", file=sby_file)\n\n        if csr_mode:\n            localdict = locals()\n            if \"constval\" in localdict:\n                print(f\"`define RISCV_FORMAL_CSRC_CONSTVAL {constval}\", file=sby_file)\n            if \"hpmevent\" in localdict:\n                print(f\"`define RISCV_FORMAL_CSRC_HPMEVENT {hpmevent}\", file=sby_file)\n            if \"hpmcounter\" in localdict:\n                print(f\"`define RISCV_FORMAL_CSRC_HPMCOUNTER {hpmcounter}\", file=sby_file)\n            if \"csr_mask\" in localdict:\n                print(f\"`define RISCV_FORMAL_CSRC_MASK {csr_mask}\", file=sby_file)\n            print(f\"`define RISCV_FORMAL_CSRC_NAME {csr_name}\", file=sby_file)\n\n        if custom_csrs:\n            print_custom_csrs(sby_file)\n\n        if blackbox and hargs[\"check\"] != \"liveness\":\n            print(\"`define RISCV_FORMAL_BLACKBOX_ALU\", file=sby_file)\n\n        if blackbox and hargs[\"check\"] != \"reg\":\n            print(\"`define RISCV_FORMAL_BLACKBOX_REGS\", file=sby_file)\n\n        if chanidx is not None:\n            print(f\"`define RISCV_FORMAL_CHANNEL_IDX {chanidx:d}\", file=sby_file)\n\n        if trig is not None:\n            print(f\"`define RISCV_FORMAL_TRIG_CYCLE {trig:d}\", file=sby_file)\n\n        if bus_mode:\n            print_hfmt(sby_file, \"\"\"\n                    : `define RISCV_FORMAL_BUS\n                    : `define RISCV_FORMAL_NBUS @nbus@\n                    : `define RISCV_FORMAL_BUSLEN @buslen@\n            \"\"\", **hargs)\n\n        if hargs[\"check\"] in (\"liveness\", \"hang\"):\n            print(\"`define RISCV_FORMAL_FAIRNESS\", file=sby_file)\n\n        if \"defines\" in config:\n            print_hfmt(sby_file, config[\"defines\"], **hargs)\n\n        if (f\"defines {hargs['check']}\") in config:\n            print_hfmt(sby_file, config[f\"defines {hargs['check']}\"], **hargs)\n\n        print_hfmt(sby_file, \"\"\"\n                : `include \"rvfi_macros.vh\"\n                :\n                : [file @checkch@.sv]\n                : `include \"defines.sv\"\n                : `include \"rvfi_channel.sv\"\n                : `include \"rvfi_testbench.sv\"\n                : `include \"rvfi_@check@_check.sv\"\n        \"\"\", **hargs)\n\n        if check == pf+\"cover\":\n            print_hfmt(sby_file, \"\"\"\n                    :\n                    : [file cover_stmts.vh]\n                    : @cover@\n            \"\"\", **hargs)\n\n        if \"assume\" in config:\n            print(\"\", file=sby_file)\n            print(\"[file assume_stmts.vh]\", file=sby_file)\n            for pat, line in config[\"assume\"]:\n                enabled = True\n                for p in pat:\n                    if p.startswith(\"!\"):\n                        p = p[1:]\n                        enabled = False\n                    else:\n                        enabled = True\n                    if re.match(p, check):\n                        enabled = not enabled\n                        break\n                if enabled:\n                    print(line, file=sby_file)\n\nfor grp in groups:\n    for i in range(nret):\n        check_cons(grp, \"reg\", chanidx=i, start=0, depth=1)\n        check_cons(grp, \"pc_fwd\", chanidx=i, start=0, depth=1)\n        check_cons(grp, \"pc_bwd\", chanidx=i, start=0, depth=1)\n        check_cons(grp, \"liveness\", chanidx=i, start=0, trig=1, depth=2)\n        check_cons(grp, \"unique\", chanidx=i, start=0, trig=1, depth=2)\n        check_cons(grp, \"causal\", chanidx=i, start=0, depth=1)\n        check_cons(grp, \"causal_mem\", chanidx=i, start=0, depth=1)\n        check_cons(grp, \"causal_io\", chanidx=i, start=0, depth=1)\n        check_cons(grp, \"ill\", chanidx=i, depth=0)\n        check_cons(grp, \"fault\", chanidx=i, depth=0)\n\n        check_cons(grp, \"bus_imem\", chanidx=i, start=0, depth=1, bus_mode=True)\n        check_cons(grp, \"bus_imem_fault\", chanidx=i, start=0, depth=1, bus_mode=True)\n        check_cons(grp, \"bus_dmem\", chanidx=i, start=0, depth=1, bus_mode=True)\n        check_cons(grp, \"bus_dmem_fault\", chanidx=i, start=0, depth=1, bus_mode=True)\n        check_cons(grp, \"bus_dmem_io_read\", chanidx=i, start=0, depth=1, bus_mode=True)\n        check_cons(grp, \"bus_dmem_io_read_fault\", chanidx=i, start=0, depth=1, bus_mode=True)\n        check_cons(grp, \"bus_dmem_io_write\", chanidx=i, start=0, depth=1, bus_mode=True)\n        check_cons(grp, \"bus_dmem_io_write_fault\", chanidx=i, start=0, depth=1, bus_mode=True)\n        check_cons(grp, \"bus_dmem_io_order\", chanidx=i, start=0, depth=1, bus_mode=True)\n\n    check_cons(grp, \"hang\", start=0, depth=1)\n    check_cons(grp, \"cover\", start=0, depth=1)\n\n    for csr in sorted(csrs):\n        for chanidx in range(nret):\n            for csr_test in csr_tests.get(csr, [None]):\n                check_cons(grp, csr, chanidx, start=0, depth=1, csr_mode=True, csr_test=csr_test)\n\n# ------------------------------ Makefile ------------------------------\n\ndef checks_key(check):\n    if \"sort\" in config:\n        for index, line in enumerate(config[\"sort\"].split(\"\\n\")):\n            if re.fullmatch(line.strip(), check):\n                return f\"{index:04d}-{check}\"\n    if check.startswith(\"insn_\"):\n        return f\"9999-{check}\"\n    return f\"9998-{check}\"\n\nwith open(f\"{cfgname}/makefile\", \"w\") as mkfile:\n    print(\"all:\", end=\"\", file=mkfile)\n\n    checks = list(sorted(consistency_checks | instruction_checks, key=checks_key))\n\n    for check in checks:\n        print(f\" {check}\", end=\"\", file=mkfile)\n    print(file=mkfile)\n\n    for check in checks:\n        print(f\"{check}: {check}/status\", file=mkfile)\n        print(f\"{check}/status:\", file=mkfile)\n        if abspath:\n            print(f\"\\t{sbycmd} $(shell pwd)/{check}.sby\", file=mkfile)\n        else:\n            print(f\"\\t{sbycmd} {check}.sby\", file=mkfile)\n        print(f\".PHONY: {check}\", file=mkfile)\n\nprint(f\"Generated {len(consistency_checks) + len(instruction_checks)} checks.\")\n"
  },
  {
    "path": "checks/rvfi_bus_dmem_check.sv",
    "content": "// external bus: check data reads\n//\n// Note: This only checks the data on the core side, so it is valid even with\n// caches between the checked bus and core. It also checks that the first bus\n// read of the checked data makes it to the core, but does not check that any\n// writes make it to the bus nor that any other bus-side data makes it to the\n// core.\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n`ifndef RISCV_FORMAL_FAULT_WIDTH\n`define RISCV_FORMAL_FAULT_WIDTH 1\n`endif\n\nmodule rvfi_bus_dmem_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n\t`RVFI_BUS_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] dmem_addr;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] dmem_data;\n\n\treg [  `RISCV_FORMAL_XLEN-1:0] dmem_shadow;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] bus_addr;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_rdata;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_wdata;\n\n\treg [`RISCV_FORMAL_XLEN-1:0] bus_shadow;\n\n\tinteger channel_idx, i, j;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tdmem_shadow <= dmem_data;\n\t\t\tbus_shadow <= dmem_data;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin\n\t\t\t\t\tbus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tbus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\t\t\t\t\tbus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin\n\t\t\t\t\t\tfor (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin\n\t\t\t\t\t\t\tif (bus_addr + i == dmem_addr + j) begin\n\t\t\t\t\t\t\t\tif (bus_rmask[i]) begin\n\t\t\t\t\t\t\t\t\tassume (bus_rdata[i*8 +: 8] == bus_shadow[j*8 +: 8]);\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tif (bus_wmask[i]) begin\n\t\t\t\t\t\t\t\t\tbus_shadow[j*8 +: 8] = bus_wdata[i*8 +: 8];\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\n\t\t\t\t\t\t\tif (((bus_addr + i) | (`RISCV_FORMAL_FAULT_WIDTH - 1)) == ((dmem_addr + j) | (`RISCV_FORMAL_FAULT_WIDTH - 1))) begin\n\t\t\t\t\t\t\t\tif (bus_rmask[i] || bus_wmask[i]) begin\n\t\t\t\t\t\t\t\t\tassume (!rvfi_bus_fault[channel_idx]);\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_mem_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN] == dmem_addr && `rvformal_addr_valid(dmem_addr)) begin\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin\n\t\t\t\t\t\tif (channel_idx == `RISCV_FORMAL_CHANNEL_IDX &&\n\t\t\t\t\t\t\tcheck && rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i]\n\t\t\t\t\t\t) begin\n\t\t\t\t\t\t\tcover (1);\n\t\t\t\t\t\t\tassert (dmem_shadow[i*8 +: 8] == rvfi_mem_rdata[i*8 +: 8]);\n\t\t\t\t\t\tend\n\t\t\t\t\t\tif (rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i]) begin\n\t\t\t\t\t\t\tdmem_shadow[i*8 +: 8] = rvfi_mem_wdata[i*8 +: 8];\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n"
  },
  {
    "path": "checks/rvfi_bus_dmem_fault_check.sv",
    "content": "// external bus: check faulting data reads\n//\n// Note: This only checks the data on the core side, so it is valid even with\n// caches between the checked bus and core. It also checks that the first bus\n// read of the checked data makes it to the core, but does not check that any\n// writes make it to the bus nor that any other bus-side data makes it to the\n// core.\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\nmodule rvfi_bus_dmem_fault_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n\t`RVFI_BUS_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] dmem_addr;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] bus_addr;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_rdata;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_wdata;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_addr;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_rdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_wdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask;\n\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_fault_rmask;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_fault_wmask;\n`endif\n\n\tinteger channel_idx, i, j;\n\n\talways @(posedge clock) begin\n\t\tif (!reset) begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin\n\t\t\t\t\tbus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tbus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\t\t\t\t\tbus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin\n\t\t\t\t\t\tfor (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin\n\t\t\t\t\t\t\tif (bus_addr + i == dmem_addr + j) begin\n\t\t\t\t\t\t\t\tif (bus_rmask[i]) begin\n\t\t\t\t\t\t\t\t\tassume (rvfi_bus_fault[channel_idx]);\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t\tif (bus_wmask[i]) begin\n\t\t\t\t\t\t\t\t\tassume (rvfi_bus_fault[channel_idx]);\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\t\tcover (rvfi_bus_fault[channel_idx]);\n\t\t\t\tend\n\t\t\tend\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tmem_addr  = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tmem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\tmem_fault_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tmem_fault_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n`endif\n\n\t\t\t\tif (rvfi_valid[channel_idx] && mem_addr == dmem_addr && `rvformal_addr_valid(dmem_addr)) begin\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin\n\t\t\t\t\t\tif (check && channel_idx == `RISCV_FORMAL_CHANNEL_IDX) begin\n`ifndef RISCV_FORMAL_MEM_FAULT\n\t\t\t\t\t\t\tcover (1);\n`endif\n\n\t\t\t\t\t\t\tassert (!mem_rmask[i]);\n\t\t\t\t\t\t\tassert (!mem_wmask[i]);\n\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\t\t\t\tcover (mem_fault_rmask[i]);\n\t\t\t\t\t\t\tcover (mem_fault_wmask[i]);\n\t\t\t\t\t\t\tif (mem_fault_rmask[i] || mem_fault_wmask[i]) begin\n\t\t\t\t\t\t\t\tassert (rvfi_mem_fault[channel_idx]);\n\t\t\t\t\t\t\tend\n`endif\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n"
  },
  {
    "path": "checks/rvfi_bus_dmem_io_order_check.sv",
    "content": "// external bus: check i/o access ordering\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_bus_dmem_io_order_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n\t`RVFI_BUS_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN   - 1:0] check_addr_0;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN   - 1:0] check_addr_1;\n\t`rvformal_rand_const_reg check_write_0;\n\t`rvformal_rand_const_reg check_fault_0;\n\t`rvformal_rand_const_reg check_write_1;\n\t`rvformal_rand_const_reg check_fault_1;\n\n\t(* keep *) reg bus_0_prev, bus_0_current, bus_1_current, bus_seq_seen;\n\n\t(* keep *) reg [`RISCV_FORMAL_NBUS-1:0] bus_is_io;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] bus_addr;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_rdata;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_wdata;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_addr;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_rdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_wdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask;\n\n\t(* keep *) reg fault;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] prev_addr;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] prev_rdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] prev_rmask;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] prev_wdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] prev_wmask;\n\t(* keep *) reg                                prev_fault;\n\n\t(* keep *) reg core_has_prev;\n\n\t(* keep *) reg core_0_match;\n\t(* keep *) reg core_1_match;\n\n\treg [  `RISCV_FORMAL_XLEN   - 1:0] bus_byte_addr;\n\n\tinteger channel_idx, i, j;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tbus_0_current = 0;\n\t\t\tbus_0_prev = 0;\n\t\t\tbus_1_current = 0;\n\t\t\tbus_seq_seen = 0;\n\n\t\t\tcore_has_prev = 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin\n\t\t\t\t\tbus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tbus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\t\t\t\t\tbus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\n\t\t\t\t\tbus_is_io[channel_idx] = 0;\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin\n\t\t\t\t\t\tbus_byte_addr = bus_addr + i;\n\t\t\t\t\t\tif (`rvformal_addr_io(bus_byte_addr) && (bus_rmask[i] || bus_wmask[i])) begin\n\t\t\t\t\t\t\tbus_is_io[channel_idx] = 1;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\t\tif (bus_is_io[channel_idx]) begin\n\t\t\t\t\t\tbus_1_current = 0;\n\t\t\t\t\t\tbus_0_prev = bus_0_current;\n\t\t\t\t\t\tbus_0_current = 0;\n\n\t\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin\n\t\t\t\t\t\t\tif ((bus_addr + i == check_addr_0) && (check_fault_0 == rvfi_bus_fault[channel_idx]) && (check_write_0 ? bus_wmask[i] : bus_rmask[i])) begin\n\t\t\t\t\t\t\t\tbus_0_current = 1;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tif ((bus_addr + i == check_addr_1) && (check_fault_1 == rvfi_bus_fault[channel_idx]) && (check_write_1 ? bus_wmask[i] : bus_rmask[i])) begin\n\t\t\t\t\t\t\t\tbus_1_current = 1;\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\n\t\t\t\t\t\tif (bus_1_current && bus_0_prev) begin\n\t\t\t\t\t\t\tbus_seq_seen = 1;\n\t\t\t\t\t\t\tcover (1);\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\tend\n\t\t\tend\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tmem_addr  = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tmem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\tfault = rvfi_mem_fault[channel_idx];\n\t\t\t\tif (fault) begin\n\t\t\t\t\tmem_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\t\tmem_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tend\n`else\n\t\t\t\tfault = 0;\n`endif\n\t\t\t\tcore_0_match = 0;\n\t\t\t\tcore_1_match = 0;\n\n\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i=i+1) begin\n\t\t\t\t\tif ((prev_addr + i == check_addr_0) && (check_fault_0 == prev_fault) && (check_write_0 ? prev_wmask[i] : prev_rmask[i])) begin\n\t\t\t\t\t\tcore_0_match = core_has_prev;\n\t\t\t\t\tend\n\t\t\t\t\tif ((mem_addr + i == check_addr_1) && (check_fault_1 == fault) && (check_write_1 ? mem_wmask[i] : mem_rmask[i])) begin\n\t\t\t\t\t\tcore_1_match = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tif (\n\t\t\t\t\tcheck && rvfi_valid[channel_idx] &&\n\t\t\t\t\tchannel_idx == `RISCV_FORMAL_CHANNEL_IDX &&\n\t\t\t\t\t`rvformal_addr_io(mem_addr) &&\n\t\t\t\t\tcore_0_match && core_1_match\n\t\t\t\t) begin\n\t\t\t\t\tcover (1);\n\t\t\t\t\tassert (bus_seq_seen);\n\n\t\t\t\tend\n\n\t\t\t\tif (rvfi_valid[channel_idx] && `rvformal_addr_io(mem_addr) && (mem_rmask || mem_wmask)) begin\n\t\t\t\t\t// This check would need to be extended to handle potential instructions that\n\t\t\t\t\t// simultaneously read and write. This assertion makes sure this check doesn't\n\t\t\t\t\t// silently miss any issues should such instructions be added.\n\t\t\t\t\tassert (!(mem_rmask && mem_wmask));\n\t\t\t\t\tcore_has_prev = 1;\n\t\t\t\t\tprev_addr = mem_addr;\n\t\t\t\t\tprev_rdata = mem_rdata;\n\t\t\t\t\tprev_rmask = mem_rmask;\n\t\t\t\t\tprev_wdata = mem_wdata;\n\t\t\t\t\tprev_wmask = mem_wmask;\n\t\t\t\t\tprev_fault = fault;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n"
  },
  {
    "path": "checks/rvfi_bus_dmem_io_read_check.sv",
    "content": "// external bus: check i/o reads\n//\n// This checks that a retired non-faulting load is contained in a single read\n// transaction on the external bus. It doesn't check any relationships bitween\n// multiple instructions or bus transactions. See the inline comment for\n// details on loads that are not as wide as the bus.\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_bus_dmem_io_read_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n\t`RVFI_BUS_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN   - 1:0] check_addr;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN   - 1:0] check_rdata;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_rmask;\n\n\treg bus_read_seen, bus_read_matches;\n\treg core_read_matches;\n\n\treg [`RISCV_FORMAL_XLEN/8 - 1:0] check_match_mask;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] bus_addr;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_rdata;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_addr;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_rdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask;\n\n\tinteger channel_idx, i, j;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tbus_read_seen <= 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin\n\t\t\t\t\tbus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tbus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\n\t\t\t\t\t// This allows the read to appear anywhere in the bus data as long as it fits\n\t\t\t\t\t// into a single transaction. It also allows reading adjacent bytes in the same\n\t\t\t\t\t// transaction. Different busses handle narrow reads differently, so as a\n\t\t\t\t\t// generic check we don't prescribe any particular behavior.\n\n\t\t\t\t\tcheck_match_mask = 0;\n\t\t\t\t\tbus_read_matches = 1;\n\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin\n\t\t\t\t\t\tfor (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin\n\t\t\t\t\t\t\tif (bus_addr + i == check_addr + j && check_rmask[i]) begin\n\t\t\t\t\t\t\t\tif (bus_rmask[i] && bus_rdata[i*8 +: 8] == check_rdata[j*8 +: 8]) begin\n\t\t\t\t\t\t\t\t\tcheck_match_mask[j] = 1;\n\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\tbus_read_matches = 0;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\t\tif (bus_read_matches && check_match_mask == check_rmask && !rvfi_bus_fault[channel_idx]) begin\n\t\t\t\t\t\tbus_read_seen = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tmem_addr  = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tcore_read_matches = check_rmask && mem_addr == check_addr && mem_rmask == check_rmask\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\t\t&& !rvfi_mem_fault[channel_idx]\n`endif\n\t\t\t\t;\n\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i=i+1) begin\n\t\t\t\t\tif (mem_rmask[i] && mem_rdata[i*8 +: 8] != check_rdata[i*8 +: 8]) begin\n\t\t\t\t\t\tcore_read_matches = 0;\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tif (check && rvfi_valid[channel_idx] && core_read_matches && `rvformal_addr_io(check_addr)) begin\n\t\t\t\t\tcover (1);\n\t\t\t\t\tassert (bus_read_seen);\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n"
  },
  {
    "path": "checks/rvfi_bus_dmem_io_read_fault_check.sv",
    "content": "// external bus: check i/o read faults\n//\n// This checks that a retired faulting load is contained in a single read\n// transaction on the external bus. It doesn't check any relationships bitween\n// multiple instructions or bus transactions. See the inline comment for\n// details on loads that are not as wide as the bus.\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_bus_dmem_io_read_fault_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n\t`RVFI_BUS_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN   - 1:0] check_addr;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_rmask;\n\n\treg bus_read_seen, bus_read_matches;\n\treg core_read_matches;\n\n\treg [`RISCV_FORMAL_XLEN/8 - 1:0] check_match_mask;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] bus_addr;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_rdata;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_addr;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_rdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask;\n\n\tinteger channel_idx, i, j;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tbus_read_seen <= 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin\n\t\t\t\t\tbus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tbus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\n\t\t\t\t\t// This allows the read to appear anywhere in the bus data as long as it fits\n\t\t\t\t\t// into a single transaction. It also allows reading adjacent bytes in the same\n\t\t\t\t\t// transaction. Different busses handle narrow reads differently, so as a\n\t\t\t\t\t// generic check we don't prescribe any particular behavior.\n\n\t\t\t\t\tcheck_match_mask = 0;\n\t\t\t\t\tbus_read_matches = 1;\n\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin\n\t\t\t\t\t\tfor (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin\n\t\t\t\t\t\t\tif (bus_addr + i == check_addr + j && check_rmask[i]) begin\n\t\t\t\t\t\t\t\tif (bus_rmask[i]) begin\n\t\t\t\t\t\t\t\t\tcheck_match_mask[j] = 1;\n\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\tbus_read_matches = 0;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\t\tif (bus_read_matches && check_match_mask == check_rmask && rvfi_bus_fault[channel_idx]) begin\n\t\t\t\t\t\tbus_read_seen = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tmem_addr  = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tcore_read_matches = check_rmask && mem_addr == check_addr && mem_rmask == check_rmask && rvfi_mem_fault[channel_idx];\n\n\t\t\t\tif (check && rvfi_valid[channel_idx] && core_read_matches && `rvformal_addr_io(check_addr)) begin\n\t\t\t\t\tcover (1);\n\t\t\t\t\tassert (bus_read_seen);\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n"
  },
  {
    "path": "checks/rvfi_bus_dmem_io_write_check.sv",
    "content": "// external bus: check i/o writes\n//\n// This checks that a retired non-faulting store is contained in a single read\n// transaction on the external bus. It doesn't check any relationships bitween\n// multiple instructions or bus transactions. See the inline comment for\n// details on stores that are not as wide as the bus.\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_bus_dmem_io_write_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n\t`RVFI_BUS_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN   - 1:0] check_addr;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN   - 1:0] check_wdata;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_wmask;\n\n\treg bus_write_seen, bus_write_matches;\n\treg core_write_matches;\n\n\treg [`RISCV_FORMAL_XLEN/8 - 1:0] check_match_mask;\n\treg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_match_mask;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] bus_addr;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_wdata;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_addr;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_wdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask;\n\n\tinteger channel_idx, i, j;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tbus_write_seen <= 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin\n\t\t\t\t\tbus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tbus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\n\t\t\t\t\t// This allows the write to appear anywhere in the bus data as long as it fits\n\t\t\t\t\t// into a single transaction. Unlike for reads, we don't allow writing\n\t\t\t\t\t// additional adjacent bytes.\n\n\t\t\t\t\tcheck_match_mask = 0;\n\t\t\t\t\tbus_match_mask = 0;\n\t\t\t\t\tbus_write_matches = 1;\n\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin\n\t\t\t\t\t\tfor (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin\n\t\t\t\t\t\t\tif (bus_addr + i == check_addr + j && check_wmask[i]) begin\n\t\t\t\t\t\t\t\tif (bus_wmask[i] && bus_wdata[i*8 +: 8] == check_wdata[j*8 +: 8]) begin\n\t\t\t\t\t\t\t\t\tcheck_match_mask[j] = 1;\n\t\t\t\t\t\t\t\t\tbus_match_mask[i] = 1;\n\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\tbus_write_matches = 0;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\t\tif (bus_write_matches && bus_match_mask == bus_wmask && check_match_mask == check_wmask && !rvfi_bus_fault[channel_idx]) begin\n\t\t\t\t\t\tbus_write_seen = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tmem_addr  = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tcore_write_matches = check_wmask && mem_addr == check_addr && mem_wmask == check_wmask\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\t\t&& !rvfi_mem_fault[channel_idx]\n`endif\n\t\t\t\t;\n\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i=i+1) begin\n\t\t\t\t\tif (mem_wmask[i] && mem_wdata[i*8 +: 8] != check_wdata[i*8 +: 8]) begin\n\t\t\t\t\t\tcore_write_matches = 0;\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tif (check && rvfi_valid[channel_idx] && core_write_matches && `rvformal_addr_io(check_addr)) begin\n\t\t\t\t\tcover (1);\n\t\t\t\t\tassert (bus_write_seen);\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n"
  },
  {
    "path": "checks/rvfi_bus_dmem_io_write_fault_check.sv",
    "content": "// external bus: check i/o write faults\n//\n// This checks that a retired faulting store is contained in a single read\n// transaction on the external bus. It doesn't check any relationships bitween\n// multiple instructions or bus transactions. See the inline comment for\n// details on stores that are not as wide as the bus.\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_bus_dmem_io_write_fault_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n\t`RVFI_BUS_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN   - 1:0] check_addr;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN   - 1:0] check_wdata;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN/8 - 1:0] check_wmask;\n\n\treg bus_write_seen, bus_write_matches;\n\treg core_write_matches;\n\n\treg [`RISCV_FORMAL_XLEN/8 - 1:0] check_match_mask;\n\treg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_match_mask;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] bus_addr;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_wmask;\n\t(* keep *) reg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_wdata;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_addr;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_wdata;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask;\n\n\tinteger channel_idx, i, j;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tbus_write_seen <= 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_bus_valid[channel_idx] && rvfi_bus_data[channel_idx]) begin\n\t\t\t\t\tbus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tbus_wmask = rvfi_bus_wmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_wdata = rvfi_bus_wdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\n\t\t\t\t\t// This allows the write to appear anywhere in the bus data as long as it fits\n\t\t\t\t\t// into a single transaction. Unlike for reads, we don't allow writing\n\t\t\t\t\t// additional adjacent bytes.\n\n\t\t\t\t\tcheck_match_mask = 0;\n\t\t\t\t\tbus_match_mask = 0;\n\t\t\t\t\tbus_write_matches = 1;\n\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1) begin\n\t\t\t\t\t\tfor (j = 0; j < `RISCV_FORMAL_XLEN/8; j=j+1) begin\n\t\t\t\t\t\t\tif (bus_addr + i == check_addr + j && check_wmask[i]) begin\n\t\t\t\t\t\t\t\tif (bus_wmask[i] && bus_wdata[i*8 +: 8] == check_wdata[j*8 +: 8]) begin\n\t\t\t\t\t\t\t\t\tcheck_match_mask[j] = 1;\n\t\t\t\t\t\t\t\t\tbus_match_mask[i] = 1;\n\t\t\t\t\t\t\t\tend else begin\n\t\t\t\t\t\t\t\t\tbus_write_matches = 0;\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\t\tif (bus_write_matches && bus_match_mask == bus_wmask && check_match_mask == check_wmask && rvfi_bus_fault[channel_idx]) begin\n\t\t\t\t\t\tbus_write_seen = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tmem_addr  = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tcore_write_matches = check_wmask && mem_addr == check_addr && mem_wmask == check_wmask && rvfi_mem_fault[channel_idx];\n\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i=i+1) begin\n\t\t\t\t\tif (mem_wmask[i] && mem_wdata[i*8 +: 8] != check_wdata[i*8 +: 8]) begin\n\t\t\t\t\t\tcore_write_matches = 0;\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tif (check && rvfi_valid[channel_idx] && core_write_matches && `rvformal_addr_io(check_addr)) begin\n\t\t\t\t\tcover (1);\n\t\t\t\t\tassert (bus_write_seen);\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n"
  },
  {
    "path": "checks/rvfi_bus_imem_check.sv",
    "content": "// external bus: check instruction memory reads\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n`ifndef RISCV_FORMAL_FAULT_WIDTH\n`define RISCV_FORMAL_FAULT_WIDTH 1\n`endif\n\n\nmodule rvfi_bus_imem_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n\t`RVFI_BUS_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] imem_addr;\n\t`rvformal_rand_const_reg [15:0] imem_data;\n\n\treg [`RISCV_FORMAL_XLEN-1:0] pc;\n\treg [`RISCV_FORMAL_ILEN-1:0] insn;\n\n\treg [  `RISCV_FORMAL_XLEN   - 1:0] bus_addr;\n\treg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask;\n\treg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_rdata;\n\n\tinteger channel_idx, i, j;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_bus_valid[channel_idx] && rvfi_bus_insn[channel_idx]) begin\n\t\t\t\t\tbus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tbus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1)\n\t\t\t\t\tfor (j = 0; j < 2; j=j+1) begin\n\t\t\t\t\t\tif (bus_rmask[i] && bus_addr + i == imem_addr + j) begin\n\t\t\t\t\t\t\tassume (imem_data[j*8 +: 8] == bus_rdata[i*8 +: 8]);\n\t\t\t\t\t\tend\n\n\t\t\t\t\t\tif (bus_rmask[i] && ((bus_addr + i) | (`RISCV_FORMAL_FAULT_WIDTH - 1)) == ((imem_addr + j) | (`RISCV_FORMAL_FAULT_WIDTH - 1))) begin\n\t\t\t\t\t\t\tassume (!rvfi_bus_fault[channel_idx]);\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tif (check) begin\n\t\t\t\tif (rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]) begin\n\t\t\t\t\tpc = rvfi_pc_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tinsn = rvfi_insn[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN];\n\n\t\t\t\t\tif (`rvformal_addr_valid(pc) && pc == imem_addr) begin\n\t\t\t\t\t\tcover (1);\n\t\t\t\t\t\tassert (insn[15:0] == imem_data);\n\t\t\t\t\tend;\n\n\t\t\t\t\tif (insn[1:0] == 2'b11 && `rvformal_addr_valid(pc+2) && pc+2 == imem_addr) begin\n\t\t\t\t\t\tcover (1);\n\t\t\t\t\t\tassert (insn[31:16] == imem_data);\n\t\t\t\t\tend;\n\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n"
  },
  {
    "path": "checks/rvfi_bus_imem_fault_check.sv",
    "content": "// external bus: check faulting instruction memory reads\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\nmodule rvfi_bus_imem_fault_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n\t`RVFI_BUS_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] imem_addr;\n\n\treg [`RISCV_FORMAL_XLEN-1:0] pc;\n\treg [`RISCV_FORMAL_ILEN-1:0] insn;\n\n\treg [  `RISCV_FORMAL_XLEN   - 1:0] bus_addr;\n\treg [`RISCV_FORMAL_BUSLEN/8 - 1:0] bus_rmask;\n\treg [`RISCV_FORMAL_BUSLEN   - 1:0] bus_rdata;\n\n\tinteger channel_idx, i, j;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NBUS; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_bus_valid[channel_idx] && rvfi_bus_insn[channel_idx]) begin\n\t\t\t\t\tbus_addr = rvfi_bus_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tbus_rmask = rvfi_bus_rmask[channel_idx*`RISCV_FORMAL_BUSLEN/8 +: `RISCV_FORMAL_BUSLEN/8];\n\t\t\t\t\tbus_rdata = rvfi_bus_rdata[channel_idx*`RISCV_FORMAL_BUSLEN +: `RISCV_FORMAL_BUSLEN];\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_BUSLEN/8; i=i+1)\n\t\t\t\t\tfor (j = 0; j < 2; j=j+1) begin\n\t\t\t\t\t\tif (bus_rmask[i] && bus_addr + i == imem_addr + j) begin\n\t\t\t\t\t\t\tassume (rvfi_bus_fault[channel_idx]);\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\t\tcover (rvfi_bus_fault[channel_idx]);\n\t\t\t\tend\n\t\t\tend\n\n\t\t\tif (check) begin\n\t\t\t\tif (rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]) begin\n\t\t\t\t\tpc = rvfi_pc_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tinsn = rvfi_insn[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN];\n\n\t\t\t\t\tif (`rvformal_addr_valid(pc) && pc == imem_addr) begin\n\t\t\t\t\t\tcover (1);\n\t\t\t\t\t\tassert (rvfi_trap[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\t\t\tassert (insn == 0);\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\t\t\tassert (rvfi_mem_fault[`RISCV_FORMAL_CHANNEL_IDX]);\n`endif\n\t\t\t\t\tend;\n\n\t\t\t\t\tif (`rvformal_addr_valid(pc+2) && pc+2 == imem_addr) begin\n\t\t\t\t\t\tcover (1);\n\t\t\t\t\t\tassert (rvfi_trap[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\t\t\tassert (insn == 0);\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\t\t\tassert (rvfi_mem_fault[`RISCV_FORMAL_CHANNEL_IDX]);\n`endif\n\t\t\t\t\tend;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n"
  },
  {
    "path": "checks/rvfi_causal_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_causal_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\t`rvformal_rand_const_reg [4:0] register_index;\n\treg found_non_causal = 0;\n\n\tinteger channel_idx;\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tfound_non_causal = 0;\n\t\tend else begin\n\t\t\tif (check) begin\n\t\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin\n\t\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order &&\n\t\t\t\t\t\t\t(register_index == rvfi_rs1_addr[channel_idx*5 +: 5] ||\n\t\t\t\t\t\t\tregister_index == rvfi_rs2_addr[channel_idx*5 +: 5])) begin\n\t\t\t\t\t\tfound_non_causal = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\t\tassume(register_index != 0);\n\t\t\t\tassume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\tassume((register_index == rvfi_rd_addr[`RISCV_FORMAL_CHANNEL_IDX*5 +: 5]));\n\t\t\t\tassume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]);\n\t\t\t\tassert(!found_non_causal);\n\t\t\tend else begin\n\t\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order &&\n\t\t\t\t\t\t\t(register_index == rvfi_rs1_addr[channel_idx*5 +: 5] ||\n\t\t\t\t\t\t\tregister_index == rvfi_rs2_addr[channel_idx*5 +: 5])) begin\n\t\t\t\t\t\tfound_non_causal = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_causal_io_check.sv",
    "content": "// check that no i/o memory accesses are retired in a non-causal order\n//\n// This checks that no i/o memory accesses are retired out of order. It uses\n// the RISCV_FORMAL_IOADDR(addr) macro to determine whether a memory location\n// is considered to be an i/o address.\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_causal_io_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_addr;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask;\n\n\treg found_non_causal = 0;\n\treg performs_io = 0;\n\n\treg [  `RISCV_FORMAL_XLEN   - 1:0] byte_addr;\n\n\tinteger channel_idx;\n\tinteger i;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tfound_non_causal = 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tmem_addr = rvfi_mem_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tmem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\tif (rvfi_mem_fault[channel_idx]) begin\n\t\t\t\t\tmem_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\t\tmem_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tend\n`endif\n\n\t\t\t\tperforms_io = 0;\n\n\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin\n\t\t\t\t\tbyte_addr = mem_addr + i;\n\t\t\t\t\tif (`rvformal_addr_io(byte_addr)) begin\n\t\t\t\t\t\tperforms_io |= mem_rmask[i] | mem_wmask[i];\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tif (check && channel_idx == `RISCV_FORMAL_CHANNEL_IDX) begin\n\t\t\t\t\tassume (rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\t\tassume (performs_io);\n\t\t\t\t\tassume (insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]);\n\t\t\t\t\tcover (1);\n\t\t\t\t\tassert (!found_non_causal);\n\t\t\t\tend\n\n\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order && performs_io) begin\n\t\t\t\t\tfound_non_causal = 1;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_causal_mem_check.sv",
    "content": "// check that no memory accesses are retired in a non-causal order\n//\n// This checks that no read of a memory location is retired before the write of\n// the to-be-read value.\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_causal_mem_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] check_addr;\n\n\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN   - 1:0] mem_addr;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_rmask;\n\t(* keep *) reg [  `RISCV_FORMAL_XLEN/8 - 1:0] mem_wmask;\n\n\treg found_non_causal = 0;\n\treg reads_check_addr;\n\treg writes_check_addr;\n\n\tinteger channel_idx;\n\tinteger i;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tfound_non_causal = 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tmem_addr = rvfi_mem_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\tmem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tmem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\tif (rvfi_mem_fault[channel_idx]) begin\n\t\t\t\t\tmem_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\t\tmem_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t\t\tend\n`endif\n\n\t\t\t\treads_check_addr = 0;\n\t\t\t\twrites_check_addr = 0;\n\n\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin\n\t\t\t\t\tif (mem_addr + i == check_addr) begin\n\t\t\t\t\t\treads_check_addr |= mem_rmask[i];\n\t\t\t\t\t\twrites_check_addr |= mem_wmask[i];\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tif (check && channel_idx == `RISCV_FORMAL_CHANNEL_IDX) begin\n\t\t\t\t\tassume (rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\t\tassume (writes_check_addr);\n\t\t\t\t\tassume (insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]);\n\t\t\t\t\tcover (1);\n\t\t\t\t\tassert (!found_non_causal);\n\t\t\t\tend\n\n\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order && reads_check_addr) begin\n\t\t\t\t\tfound_non_causal = 1;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_channel.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_channel (\n\t`RVFI_INPUTS\n);\n\tparameter CHANNEL_IDX = 0;\n\n\t(* keep *) wire                                valid     = rvfi_valid    [CHANNEL_IDX];\n\t(* keep *) wire [                      63 : 0] order     = rvfi_order    [CHANNEL_IDX*64                   +:  64];\n\t(* keep *) wire [`RISCV_FORMAL_ILEN   - 1 : 0] insn      = rvfi_insn     [CHANNEL_IDX*`RISCV_FORMAL_ILEN   +: `RISCV_FORMAL_ILEN];\n\t(* keep *) wire                                trap      = rvfi_trap     [CHANNEL_IDX];\n\t(* keep *) wire                                halt      = rvfi_halt     [CHANNEL_IDX];\n\t(* keep *) wire                                intr      = rvfi_intr     [CHANNEL_IDX];\n\t(* keep *) wire [                       1 : 0] mode      = rvfi_mode     [CHANNEL_IDX*2                    +:  2];\n\t(* keep *) wire [                       1 : 0] ixl       = rvfi_ixl      [CHANNEL_IDX*2                    +:  2];\n\n\t(* keep *) wire [                       4 : 0] rs1_addr  = rvfi_rs1_addr [CHANNEL_IDX*5                    +:  5];\n\t(* keep *) wire [                       4 : 0] rs2_addr  = rvfi_rs2_addr [CHANNEL_IDX*5                    +:  5];\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs1_rdata = rvfi_rs1_rdata[CHANNEL_IDX*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs2_rdata = rvfi_rs2_rdata[CHANNEL_IDX*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t(* keep *) wire [                       4 : 0] rd_addr   = rvfi_rd_addr  [CHANNEL_IDX*5                    +:  5];\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rd_wdata  = rvfi_rd_wdata [CHANNEL_IDX*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_rdata  = rvfi_pc_rdata [CHANNEL_IDX*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_wdata  = rvfi_pc_wdata [CHANNEL_IDX*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_addr  = rvfi_mem_addr [CHANNEL_IDX*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask[CHANNEL_IDX*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask[CHANNEL_IDX*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_rdata = rvfi_mem_rdata[CHANNEL_IDX*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_wdata = rvfi_mem_wdata[CHANNEL_IDX*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\nendmodule\n"
  },
  {
    "path": "checks/rvfi_cover_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_cover_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n`ifdef RISCV_FORMAL_ROLLBACK\n\t(* keep *) integer cnt_rollback;\n\tinteger cnt_rollback_q;\n\n\talways @(posedge clock) begin\n\t\tcnt_rollback_q <= cnt_rollback;\n\tend\n\n\talways @* begin\n\t\tif (reset)\n\t\t\tcnt_rollback = 0;\n\t\telse\n\t\t\tcnt_rollback = cnt_rollback_q + rvfi_rollback_valid;\n\tend\n`endif\n\n\tgenvar channel_idx;\n\tgenerate for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin:channel\n\t\t`RVFI_GETCHANNEL(channel_idx)\n\n\t\t(* keep *) integer cnt_insns;\n\t\t(* keep *) integer cnt_trap_insns;\n\t\t(* keep *) integer cnt_intr_insns;\n\t\t(* keep *) integer cnt_norm_insns;\n\n`ifdef RISCV_FORMAL_ROLLBACK\n\t\t// \"arb\" = after rollback\n\t\t(* keep *) integer arb_cnt_insns;\n\t\t(* keep *) integer arb_cnt_trap_insns;\n\t\t(* keep *) integer arb_cnt_intr_insns;\n\t\t(* keep *) integer arb_cnt_norm_insns;\n`endif\n\n\t\tinteger cnt_insns_q;\n\t\tinteger cnt_trap_insns_q;\n\t\tinteger cnt_intr_insns_q;\n\t\tinteger cnt_norm_insns_q;\n\n`ifdef RISCV_FORMAL_ROLLBACK\n\t\tinteger arb_cnt_insns_q;\n\t\tinteger arb_cnt_trap_insns_q;\n\t\tinteger arb_cnt_intr_insns_q;\n\t\tinteger arb_cnt_norm_insns_q;\n`endif\n\n\t\talways @(posedge clock) begin\n\t\t\tcnt_insns_q <= cnt_insns;\n\t\t\tcnt_trap_insns_q <= cnt_trap_insns;\n\t\t\tcnt_intr_insns_q <= cnt_intr_insns;\n\t\t\tcnt_norm_insns_q <= cnt_norm_insns;\n\n`ifdef RISCV_FORMAL_ROLLBACK\n\t\t\tarb_cnt_insns_q <= arb_cnt_insns;\n\t\t\tarb_cnt_trap_insns_q <= arb_cnt_trap_insns;\n\t\t\tarb_cnt_intr_insns_q <= arb_cnt_intr_insns;\n\t\t\tarb_cnt_norm_insns_q <= arb_cnt_norm_insns;\n`endif\n\t\tend\n\n\t\talways @* begin\n\t\t\tif (reset) begin\n\t\t\t\tcnt_insns = 0;\n\t\t\t\tcnt_trap_insns = 0;\n\t\t\t\tcnt_intr_insns = 0;\n\t\t\t\tcnt_norm_insns = 0;\n\n`ifdef RISCV_FORMAL_ROLLBACK\n\t\t\t\tarb_cnt_insns = 0;\n\t\t\t\tarb_cnt_trap_insns = 0;\n\t\t\t\tarb_cnt_intr_insns = 0;\n\t\t\t\tarb_cnt_norm_insns = 0;\n`endif\n\t\t\tend else begin\n\t\t\t\tcnt_insns = cnt_insns_q + valid;\n\t\t\t\tcnt_trap_insns = cnt_trap_insns_q + (valid && trap);\n\t\t\t\tcnt_intr_insns = cnt_intr_insns_q + (valid && intr);\n\t\t\t\tcnt_norm_insns = cnt_norm_insns_q + (valid && !{trap,intr});\n\n`ifdef RISCV_FORMAL_ROLLBACK\n\t\t\t\tarb_cnt_insns = arb_cnt_insns_q + (valid && cnt_rollback);\n\t\t\t\tarb_cnt_trap_insns = arb_cnt_trap_insns_q + (valid && cnt_rollback && trap);\n\t\t\t\tarb_cnt_intr_insns = arb_cnt_intr_insns_q + (valid && cnt_rollback && intr);\n\t\t\t\tarb_cnt_norm_insns = arb_cnt_norm_insns_q + (valid && cnt_rollback && !{trap,intr});\n`endif\n\t\t\tend\n\t\tend\n\tend endgenerate\n\n`include \"cover_stmts.vh\"\nendmodule\n"
  },
  {
    "path": "checks/rvfi_csr_ill_check.sv",
    "content": "// Copyright (C) 2023  Krystine Dawn Sherwin <krystinedawn@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_csr_ill_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t`RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX)\n\n\twire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0);\n\twire [11:0] csr_insn_addr = rvfi.insn[31:20];\n\n\twire csr_write = !rvfi.insn[13] || rvfi.insn[19:15];\n\twire csr_read = rvfi.insn[11:7] != 0;\n\n\talways @* begin\n\t\tif (!reset && check) begin\n\t\t\tassume (csr_insn_valid);\n\t\t\tassume (csr_insn_addr == `RISCV_FORMAL_ILL_CSR_ADDR);\n\t\t\tif ( (0\n\t\t\t\t`ifdef RISCV_FORMAL_ILL_MMODE\n\t\t\t\t\t|| rvfi.mode == 3\n\t\t\t\t\t\n\t\t\t\t`endif\n\t\t\t\t`ifdef RISCV_FORMAL_ILL_SMODE\n\t\t\t\t\t|| rvfi.mode == 1\n\t\t\t\t\t\n\t\t\t\t`endif\n\t\t\t\t`ifdef RISCV_FORMAL_ILL_UMODE\n\t\t\t\t\t|| rvfi.mode == 0\n\t\t\t\t\t\n\t\t\t\t`endif\n\t\t\t) && (0\n\t\t\t\t`ifdef RISCV_FORMAL_ILL_WRITE\n\t\t\t\t\t|| csr_write\n\t\t\t\t\t\n\t\t\t\t`endif\n\t\t\t\t`ifdef RISCV_FORMAL_ILL_READ\n\t\t\t\t\t|| csr_read\n\t\t\t\t\t\n\t\t\t\t`endif\n\t\t\t) ) begin\n\t\t\t\tassert (rvfi.trap);\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_csrc_any_check.sv",
    "content": "// Copyright (C) 2023  Krystine Dawn Sherwin <krystinedawn@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_csrc_any_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t// Setup for csrs\n\t`RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX)\n\n\tlocalparam [11:0] csr_none = 12'hFFF;\n\t`RVFI_INDICES\n\n\t`define quoted(txt) txt\n\t`define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type)\n\t`define csr_mindex(_name) csr_mindex_``_name\n\t`define csr_sindex(_name) csr_sindex_``_name\n\t`define csr_uindex(_name) csr_uindex_``_name\n\t`define csr_mindexh(_name) csr_mindex_``_name```quoted(h)\n\t`define csr_sindexh(_name) csr_sindex_``_name```quoted(h)\n\t`define csr_uindexh(_name) csr_uindex_``_name```quoted(h)\n\n\twire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0);\n\twire [11:0] csr_insn_addr = rvfi.insn[31:20];\n\twire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`ifdef RISCV_FORMAL_SMODE\n\t\t\t|| csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t\t`ifdef RISCV_FORMAL_UMODE\n\t\t\t|| csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t);\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask);\n\t`ifdef RISCV_FORMAL_CSRC_MASK\n\t\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata) & `RISCV_FORMAL_CSRC_MASK;\n\t\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata) & `RISCV_FORMAL_CSRC_MASK;\n\t`else\n\t\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata);\n\t\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata);\n\t`endif //RISCV_FORMAL_CSRC_MASK\n\n\twire csr_write = !rvfi.insn[13] || rvfi.insn[19:15];\n\twire csr_read = rvfi.insn[11:7] != 0;\n\twire csr_write_valid = csr_write && csr_insn_valid;\n\twire csr_read_valid = csr_read && csr_insn_valid;\n\twire [1:0] csr_mode = rvfi.insn[13:12];\n\twire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata;\n\n\t// Setup for reg testing\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\treg [`RISCV_FORMAL_XLEN-1:0] rsval_shadow = 0;\n\treg [`RISCV_FORMAL_XLEN-1:0] wdata_shadow = 0;\n\treg csr_written = 0;\n\treg [1:0] csr_mode_shadow = 0;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\trsval_shadow = 0;\n\t\t\twdata_shadow = 0;\n\t\t\tcsr_written = 0;\n\t\t\tcsr_mode_shadow = 0;\n\t\tend else begin\n\t\t\tif (check) begin\n\t\t\t\t`ifdef RISCV_FORMAL_CSRC_MASK\n\t\t\t\t\tassume ((rsval_shadow & `RISCV_FORMAL_CSRC_MASK) == rsval_shadow);\n\t\t\t\t`endif\n\t\t\t\tif (csr_written && csr_read_valid && csr_insn_under_test) begin\n\t\t\t\t\tcase (csr_mode_shadow)\n\t\t\t\t\t\t2'b 00 /* None */,\n\t\t\t\t\t\t2'b 01 /* RW   */: begin\n\t\t\t\t\t\t\tassert(rsval_shadow == csr_insn_rdata || csr_insn_rdata == wdata_shadow);\n\t\t\t\t\t\t\tassert(rsval_shadow == wdata_shadow);\n\t\t\t\t\t\tend\n\t\t\t\t\t\t// Currently not testing set/clear from rsval\n\t\t\t\t\t\t2'b 10 /* RS   */,\n\t\t\t\t\t\t2'b 11 /* RC   */: begin assert(csr_insn_rdata == wdata_shadow); end\n\t\t\t\t\tendcase\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tif (csr_write_valid && csr_insn_under_test) begin\n\t\t\t\t\trsval_shadow = csr_rsval;\n\t\t\t\t\twdata_shadow = csr_insn_wdata;\n\t\t\t\t\tcsr_written = 1;\n\t\t\t\t\tcsr_mode_shadow = csr_mode;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_csrc_const_check.sv",
    "content": "// Copyright (C) 2023  Krystine Dawn Sherwin <krystinedawn@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_csrc_const_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t// Setup for csrs\n\t`RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX)\n\n\tlocalparam [11:0] csr_none = 12'hFFF;\n\t`RVFI_INDICES\n\n\t`define quoted(txt) txt\n\t`define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type)\n\t`define csr_mindex(_name) csr_mindex_``_name\n\t`define csr_sindex(_name) csr_sindex_``_name\n\t`define csr_uindex(_name) csr_uindex_``_name\n\t`define csr_mindexh(_name) csr_mindex_``_name```quoted(h)\n\t`define csr_sindexh(_name) csr_sindex_``_name```quoted(h)\n\t`define csr_uindexh(_name) csr_uindex_``_name```quoted(h)\n\n\twire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0);\n\twire [11:0] csr_insn_addr = rvfi.insn[31:20];\n\twire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`ifdef RISCV_FORMAL_SMODE\n\t\t\t|| csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t\t`ifdef RISCV_FORMAL_UMODE\n\t\t\t|| csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t);\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata);\n\t`ifdef RISCV_FORMAL_CSRC_MASK\n\t\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata) & `RISCV_FORMAL_CSRC_MASK;\n\t`else\n\t\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata);\n\t`endif //RISCV_FORMAL_CSRC_MASK\n\n\twire csr_write = !rvfi.insn[13] || rvfi.insn[19:15];\n\twire csr_read = rvfi.insn[11:7] != 0;\n\twire csr_write_valid = csr_write && csr_insn_valid;\n\twire csr_read_valid = csr_read && csr_insn_valid;\n\twire [1:0] csr_mode = rvfi.insn[13:12];\n\n\t// Setup for reg testing\n\treg [`RISCV_FORMAL_XLEN-1:0] wdata_shadow = 0;\n\treg [`RISCV_FORMAL_XLEN-1:0] rdata_shadow = 0;\n\treg csr_written = 0;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\twdata_shadow = 0;\n\t\t\tcsr_written = 0;\n\t\tend else begin\n\t\t\tif (check) begin\n\t\t\t\tif (csr_written && csr_read_valid && csr_insn_under_test) begin\n\t\t\t\t\tassert(csr_insn_rdata == `RISCV_FORMAL_CSRC_CONSTVAL);\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tif (csr_write_valid && csr_insn_under_test) begin\n\t\t\t\t\trdata_shadow = csr_insn_rdata;\n\t\t\t\t\twdata_shadow = csr_insn_wdata;\n\t\t\t\t\tcsr_written = 1;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_csrc_hpm_check.sv",
    "content": "// Copyright (C) 2023  Krystine Dawn Sherwin <krystinedawn@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_csrc_hpm_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t// Setup for csrs\n\t`RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX)\n\n\tlocalparam [11:0] csr_none = 12'hFFF;\n\t`RVFI_INDICES\n\n\t`define quoted(txt) txt\n\t`define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type)\n\t`define csr_mindex(_name) csr_mindex_``_name\n\t`define csr_sindex(_name) csr_sindex_``_name\n\t`define csr_uindex(_name) csr_uindex_``_name\n\t`define csr_mindexh(_name) csr_mindex_``_name```quoted(h)\n\t`define csr_sindexh(_name) csr_sindex_``_name```quoted(h)\n\t`define csr_uindexh(_name) csr_uindex_``_name```quoted(h)\n\n\twire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0);\n\twire [11:0] csr_insn_addr = rvfi.insn[31:20];\n\twire csr_hpmcounter_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_HPMCOUNTER)\n\t\t|| csr_insn_addr == `csr_mindexh(`RISCV_FORMAL_CSRC_HPMCOUNTER));\n\twire csr_hpmevent_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME));\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata);\n\twire [`RISCV_FORMAL_XLEN-1:0] hpmcounter_rdata = `csrget(`RISCV_FORMAL_CSRC_HPMCOUNTER, rdata);\n\n\twire csr_write = !rvfi.insn[13] || rvfi.insn[19:15];\n\twire csr_read = rvfi.insn[11:7] != 0;\n\twire csr_write_valid = csr_write && csr_insn_valid;\n\twire csr_read_valid = csr_read && csr_insn_valid;\n\twire [1:0] csr_mode = rvfi.insn[13:12];\n\twire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata;\n\n\t// Setup for reg testing\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\treg [31:0] csr_hpmcounter_shadow = 0;\n\treg csr_hpmevent_written;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tcsr_hpmcounter_shadow = 0;\n\t\t\tcsr_hpmevent_written = 0;\n\t\tend else begin\n\t\t\t// No writes of CSR under test allowed\n\t\t\tassume (!(csr_write_valid && csr_hpmcounter_under_test));\n\t\t\tif (csr_hpmevent_written) begin\n\t\t\t\t// event CSR should hold the desired event \n\t\t\t\tassume (csr_insn_rdata == `RISCV_FORMAL_CSRC_HPMEVENT);\n\t\t\t\t// counter CSR should eventually increase\n\t\t\t\tcover (hpmcounter_rdata > csr_hpmcounter_shadow);\n\t\t\tend\n\t\t\tif (csr_write_valid && csr_hpmevent_under_test) begin\n\t\t\t\tcsr_hpmcounter_shadow = hpmcounter_rdata;\n\t\t\t\tcsr_hpmevent_written = 1;\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_csrc_inc_check.sv",
    "content": "// Copyright (C) 2023  Krystine Dawn Sherwin <krystinedawn@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_csrc_inc_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t// Setup for csrs\n\t`RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX)\n\n\tlocalparam [11:0] csr_none = 12'hFFF;\n\t`RVFI_INDICES\n\n\t`define quoted(txt) txt\n\t`define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type)\n\t`define csr_mindex(_name) csr_mindex_``_name\n\t`define csr_sindex(_name) csr_sindex_``_name\n\t`define csr_uindex(_name) csr_uindex_``_name\n\t`define csr_mindexh(_name) csr_mindex_``_name```quoted(h)\n\t`define csr_sindexh(_name) csr_sindex_``_name```quoted(h)\n\t`define csr_uindexh(_name) csr_uindex_``_name```quoted(h)\n\n\twire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0);\n\twire [11:0] csr_insn_addr = rvfi.insn[31:20];\n\twire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`ifdef RISCV_FORMAL_SMODE\n\t\t\t|| csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t\t`ifdef RISCV_FORMAL_UMODE\n\t\t\t|| csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t);\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata);\n\n\twire csr_write = !rvfi.insn[13] || rvfi.insn[19:15];\n\twire csr_read = rvfi.insn[11:7] != 0;\n\twire csr_write_valid = csr_write && csr_insn_valid;\n\twire csr_read_valid = csr_read && csr_insn_valid;\n\twire [1:0] csr_mode = rvfi.insn[13:12];\n\twire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata;\n\n\t// Setup for reg testing\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\treg [`RISCV_FORMAL_XLEN-1:0] wdata_shadow = 0;\n\treg [`RISCV_FORMAL_XLEN-1:0] rdata_shadow = 0;\n\treg csr_written = 0;\n\treg csr_read_shadowed = 0;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\twdata_shadow = 0;\n\t\t\trdata_shadow = 0;\n\t\t\tcsr_written = 0;\n\t\t\tcsr_read_shadowed = 0;\n\t\tend else begin\n\t\t\t// no writes without read that could decrease the value manually\n\t\t\tif (csr_write_valid) assume(csr_read_valid);\n\t\t\tif (check) begin\n\t\t\t\tassume(csr_read_shadowed);\n\t\t\t\tif (csr_read_shadowed && csr_read_valid && csr_insn_under_test) begin\n\t\t\t\t\tassert(csr_insn_rdata >= rdata_shadow || (csr_written && csr_insn_rdata >= wdata_shadow));\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tcsr_written = 0;\n\t\t\t\tif (csr_read_valid && csr_insn_under_test) begin\n\t\t\t\t\tif (csr_write_valid) begin\n\t\t\t\t\t\tassume(csr_insn_wdata[`RISCV_FORMAL_XLEN-1] == 0);\n\t\t\t\t\t\twdata_shadow = csr_insn_wdata;\n\t\t\t\t\t\tcsr_written = 1;\n\t\t\t\t\tend\n\t\t\t\t\trdata_shadow = csr_insn_rdata;\n\t\t\t\t\tcsr_read_shadowed = 1;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_csrc_upcnt_check.sv",
    "content": "// Copyright (C) 2023  Krystine Dawn Sherwin <krystinedawn@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_csrc_upcnt_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t// Setup for csrs\n\t`RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX)\n\n\tlocalparam [11:0] csr_none = 12'hFFF;\n\t`RVFI_INDICES\n\n\t`define quoted(txt) txt\n\t`define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type)\n\t`define csr_mindex(_name) csr_mindex_``_name\n\t`define csr_sindex(_name) csr_sindex_``_name\n\t`define csr_uindex(_name) csr_uindex_``_name\n\t`define csr_mindexh(_name) csr_mindex_``_name```quoted(h)\n\t`define csr_sindexh(_name) csr_sindex_``_name```quoted(h)\n\t`define csr_uindexh(_name) csr_uindex_``_name```quoted(h)\n\n\twire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0);\n\twire [11:0] csr_insn_addr = rvfi.insn[31:20];\n\twire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`ifdef RISCV_FORMAL_SMODE\n\t\t\t|| csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t\t`ifdef RISCV_FORMAL_UMODE\n\t\t\t|| csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t);\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata);\n\n\twire csr_write = !rvfi.insn[13] || rvfi.insn[19:15];\n\twire csr_read = rvfi.insn[11:7] != 0;\n\twire csr_write_valid = csr_write && csr_insn_valid;\n\twire csr_read_valid = csr_read && csr_insn_valid;\n\twire [1:0] csr_mode = rvfi.insn[13:12];\n\twire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata;\n\n\t// Setup for reg testing\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\treg [`RISCV_FORMAL_XLEN-1:0] rdata_shadow = 0;\n\treg csr_event_written = 0;\n\treg csr_read_shadowed = 0;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\trdata_shadow = 0;\n\t\t\tcsr_event_written = 0;\n\t\t\tcsr_read_shadowed = 0;\n\t\tend else begin\n\t\t\t// No writes of CSR under test allowed\n\t\t\tassume (!(csr_write_valid && csr_insn_under_test));\n\t\t\tif (check) begin\n\t\t\t\tassume(csr_read_shadowed);\n\t\t\t\tif (csr_read_valid && csr_insn_under_test) begin\n\t\t\t\t\tassert(csr_insn_rdata > rdata_shadow);\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tif (csr_read_valid && csr_insn_under_test) begin\n\t\t\t\t\tassume(csr_insn_rdata[31:0] < 'h F000_0000); // no overflow\n\t\t\t\t\trdata_shadow = csr_insn_rdata;\n\t\t\t\t\tcsr_read_shadowed = 1;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_csrc_zero_check.sv",
    "content": "// Copyright (C) 2023  Krystine Dawn Sherwin <krystinedawn@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_csrc_zero_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t// Setup for csrs\n\t`RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX)\n\n\tlocalparam [11:0] csr_none = 12'hFFF;\n\t`RVFI_INDICES\n\n\t`define quoted(txt) txt\n\t`define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type)\n\t`define csr_mindex(_name) csr_mindex_``_name\n\t`define csr_sindex(_name) csr_sindex_``_name\n\t`define csr_uindex(_name) csr_uindex_``_name\n\t`define csr_mindexh(_name) csr_mindex_``_name```quoted(h)\n\t`define csr_sindexh(_name) csr_sindex_``_name```quoted(h)\n\t`define csr_uindexh(_name) csr_uindex_``_name```quoted(h)\n\n\twire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0);\n\twire [11:0] csr_insn_addr = rvfi.insn[31:20];\n\twire csr_insn_under_test = (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`ifdef RISCV_FORMAL_SMODE\n\t\t\t|| csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t\t`ifdef RISCV_FORMAL_UMODE\n\t\t\t|| csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRC_NAME)\n\t\t`endif\n\t);\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRC_NAME, rmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRC_NAME, wmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRC_NAME, wdata);\n\t`ifdef RISCV_FORMAL_CSRC_MASK\n\t\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata) & `RISCV_FORMAL_CSRC_MASK;\n\t`else\n\t\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRC_NAME, rdata);\n\t`endif //RISCV_FORMAL_CSRC_MASK\n\n\twire csr_write = !rvfi.insn[13] || rvfi.insn[19:15];\n\twire csr_read = rvfi.insn[11:7] != 0;\n\twire csr_write_valid = csr_write && csr_insn_valid;\n\twire csr_read_valid = csr_read && csr_insn_valid;\n\twire [1:0] csr_mode = rvfi.insn[13:12];\n\twire [31:0] csr_rsval = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata;\n\n\t// Setup for reg testing\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\treg [`RISCV_FORMAL_XLEN-1:0] wdata_shadow = 0;\n\treg csr_written = 0;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\twdata_shadow = 0;\n\t\t\tcsr_written = 0;\n\t\tend else begin\n\t\t\tif (check) begin\n\t\t\t\tif (csr_written && csr_read_valid && csr_insn_under_test) begin\n\t\t\t\t\tassert(csr_insn_rdata == 0);\n\t\t\t\t\tassume(wdata_shadow != 0);\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tif (csr_write_valid && csr_insn_under_test) begin\n\t\t\t\t\t// simplify things by only testing reg write, and not set/clear\n\t\t\t\t\tassume(csr_mode == 0 || csr_mode == 1);\n\t\t\t\t\twdata_shadow = csr_insn_wdata;\n\t\t\t\t\tcsr_written = 1;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_csrw_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_csrw_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t`RVFI_CHANNEL(rvfi, `RISCV_FORMAL_CHANNEL_IDX)\n\n\tlocalparam [11:0] csr_none = 12'hFFF;\n\t`RVFI_INDICES\n\n\t`define quoted(txt) txt\n\t`define csrget(_name, _type) rvfi.csr_``_name```quoted(_``_type)\n\t`define csr_mindex(_name) csr_mindex_``_name\n\t`define csr_sindex(_name) csr_sindex_``_name\n\t`define csr_uindex(_name) csr_uindex_``_name\n\t`define csr_mindexh(_name) csr_mindex_``_name```quoted(h)\n\t`define csr_sindexh(_name) csr_sindex_``_name```quoted(h)\n\t`define csr_uindexh(_name) csr_uindex_``_name```quoted(h)\n\n\twire csr_insn_valid = rvfi.valid && (rvfi.insn[6:0] == 7'b 1110011) && (rvfi.insn[13:12] != 0) && ((rvfi.insn >> 16 >> 16) == 0);\n\twire [11:0] csr_insn_addr = rvfi.insn[31:20];\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_arg = rvfi.insn[14] ? rvfi.insn[19:15] : rvfi.rs1_rdata;\n\n`ifdef RISCV_FORMAL_CSRWH\n\twire csr_hi = rvfi.ixl == 1 && (csr_insn_addr == `csr_mindexh(`RISCV_FORMAL_CSRW_NAME)\n\t\t`ifdef RISCV_FORMAL_SMODE\n\t\t\t|| csr_insn_addr == `csr_sindexh(`RISCV_FORMAL_CSRW_NAME)\n\t\t`endif\n\t\t`ifdef RISCV_FORMAL_UMODE\n\t\t\t|| csr_insn_addr == `csr_uindexh(`RISCV_FORMAL_CSRW_NAME)\n\t\t`endif\n\t);\n\n\twire [63:0] csr_insn_rmask_full = `csrget(`RISCV_FORMAL_CSRW_NAME, rmask);\n\twire [63:0] csr_insn_wmask_full = `csrget(`RISCV_FORMAL_CSRW_NAME, wmask);\n\twire [63:0] csr_insn_rdata_full = `csrget(`RISCV_FORMAL_CSRW_NAME, rdata);\n\twire [63:0] csr_insn_wdata_full = `csrget(`RISCV_FORMAL_CSRW_NAME, wdata);\n\n\twire [63:0] csr_insn_changed_full = csr_insn_wmask_full & (~csr_insn_rmask_full | (csr_insn_rmask_full & (csr_insn_rdata_full ^ csr_insn_wdata_full)));\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = (csr_hi ? csr_insn_rmask_full >> 32 : csr_insn_rmask_full) & (rvfi.ixl == 1 ? 'h FFFF_FFFF : -1);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = (csr_hi ? csr_insn_wmask_full >> 32 : csr_insn_wmask_full) & (rvfi.ixl == 1 ? 'h FFFF_FFFF : -1);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = (csr_hi ? csr_insn_rdata_full >> 32 : csr_insn_rdata_full) & (rvfi.ixl == 1 ? 'h FFFF_FFFF : -1);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = (csr_hi ? csr_insn_wdata_full >> 32 : csr_insn_wdata_full) & (rvfi.ixl == 1 ? 'h FFFF_FFFF : -1);\n`else\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rmask = `csrget(`RISCV_FORMAL_CSRW_NAME, rmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wmask = `csrget(`RISCV_FORMAL_CSRW_NAME, wmask);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_rdata = `csrget(`RISCV_FORMAL_CSRW_NAME, rdata);\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_wdata = `csrget(`RISCV_FORMAL_CSRW_NAME, wdata);\n`endif\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_smask =\n\t\t/* CSRRW, CSRRWI */ (rvfi.insn[13:12] == 1) ? csr_insn_arg :\n\t\t/* CSRRS, CSRRSI */ (rvfi.insn[13:12] == 2) ? csr_insn_arg : 0;\n\n\twire [`RISCV_FORMAL_XLEN-1:0] csr_insn_cmask =\n\t\t/* CSRRW, CSRRWI */ (rvfi.insn[13:12] == 1) ? ~csr_insn_arg :\n\t\t/* CSRCS, CSRRCI */ (rvfi.insn[13:12] == 3) ? csr_insn_arg : 0;\n\n\twire csr_write = !rvfi.insn[13] || rvfi.insn[19:15];\n\twire csr_read = rvfi.insn[11:7] != 0;\n\treg csr_illacc;\n\n\talways @* begin\n\t\tcsr_illacc = 0;\n\t\tcase (csr_insn_addr[11:8])\n\t\t\t/* User CSRs */\n\t\t\t4'b 00_00, 4'b 01_00, 4'b 10_00: begin // read/write\n\t\t\tend\n\t\t\t4'b 11_00: begin // read-only\n\t\t\t\tif (csr_write) csr_illacc = 1;\n\t\t\tend\n\n\t\t\t/* Supervisor CSRs */\n\t\t\t4'b 00_01, 4'b 01_01, 4'b 10_01: begin // read/write\n\t\t\t\tif (rvfi.mode < 1) csr_illacc = 1;\n\t\t\tend\n\t\t\t4'b 11_01: begin // read-only\n\t\t\t\tif (rvfi.mode < 1) csr_illacc = 1;\n\t\t\t\tif (csr_write) csr_illacc = 1;\n\t\t\tend\n\n\t\t\t/* Reserved CSRs */\n\t\t\t4'b 00_10, 4'b 01_10, 4'b 10_10, 4'b 11_10: begin\n\t\t\tend\n\n\t\t\t/* Machine CSRs */\n\t\t\t4'b 00_11, 4'b 01_11, 4'b 10_11: begin // read/write\n\t\t\t\tif (rvfi.mode < 3) csr_illacc = 1;\n\t\t\tend\n\t\t\t4'b 11_11: begin // read-only\n\t\t\t\tif (rvfi.mode < 3) csr_illacc = 1;\n\t\t\t\tif (csr_write) csr_illacc = 1;\n\t\t\tend\n\t\tendcase\n\tend\n\n\twire [`RISCV_FORMAL_XLEN-1:0] effective_csr_insn_wmask = csr_insn_rmask | csr_insn_wmask;\n\twire [`RISCV_FORMAL_XLEN-1:0] effective_csr_insn_wdata = (csr_insn_wdata & csr_insn_wmask) | (csr_insn_rdata & ~csr_insn_wmask);\n\n\twire [`RISCV_FORMAL_XLEN-1:0] spec_pc_wdata = rvfi.pc_rdata + 4;\n\n\twire insn_pma_x;\n\n`ifdef RISCV_FORMAL_PMA_MAP\n\t`RISCV_FORMAL_PMA_MAP insn_pma (\n\t\t.address(rvfi.pc_rdata),\n\t\t.log2len(rvfi.insn[1:0] == 2'b11 ? 2'd2 : 2'd1),\n\t\t.X(insn_pma_x)\n\t);\n`else\n\tassign insn_pma_x = 1;\n`endif\n\n\tinteger i;\n\n\talways @* begin\n\t\tif (!reset && check) begin\n\t\t\tassume (csr_insn_valid);\n\t\t\tassume (csr_insn_addr != csr_none);\n\t\t\tassume (csr_insn_addr == `csr_mindex(`RISCV_FORMAL_CSRW_NAME)\n\t\t\t\t`ifdef RISCV_FORMAL_SMODE\n\t\t\t\t\t|| csr_insn_addr == `csr_sindex(`RISCV_FORMAL_CSRW_NAME)\n\t\t\t\t`endif\n\t\t\t\t`ifdef RISCV_FORMAL_UMODE\n\t\t\t\t\t|| csr_insn_addr == `csr_uindex(`RISCV_FORMAL_CSRW_NAME)\n\t\t\t\t`endif\n\t\t\t\t`ifdef RISCV_FORMAL_CSRWH\n\t\t\t\t\t|| csr_hi\n\t\t\t\t`endif\n\t\t\t);\n\n\t\t\tif (!`rvformal_addr_valid(rvfi.pc_rdata) || !insn_pma_x || csr_illacc) begin\n\t\t\t\tassert (rvfi.trap);\n\t\t\t\tassert (rvfi.rd_addr == 0);\n\t\t\t\tassert (rvfi.rd_wdata == 0);\n\t\t\tend else begin\n\t\t\t\tassert (!rvfi.trap);\n\t\t\t\tassert (rvfi.rd_addr == rvfi.insn[11:7]);\n\t\t\t\tassert (`rvformal_addr_eq(rvfi.pc_wdata, spec_pc_wdata));\n\n\t\t\t\tif (rvfi.rd_addr == 0) begin\n\t\t\t\t\tassert (rvfi.rd_wdata == 0);\n\t\t\t\tend else begin\n\t\t\t\t\tassert (csr_insn_rmask == {`RISCV_FORMAL_XLEN{1'b1}});\n\t\t\t\t\tassert (csr_insn_rdata == rvfi.rd_wdata);\n\t\t\t\tend\n\n\t\t\t\tassert (((csr_insn_smask | csr_insn_cmask) & ~effective_csr_insn_wmask) == 0);\n\t\t\t\tassert ((csr_insn_smask & ~effective_csr_insn_wdata) == 0);\n\t\t\t\tassert ((csr_insn_cmask & effective_csr_insn_wdata) == 0);\n\n`ifdef RISCV_FORMAL_CSRWH\n\t\t\t\tif (csr_hi) begin\n\t\t\t\t\tassert (csr_insn_changed_full[31:0] == 0);\n\t\t\t\tend else if (rvfi.ixl == 1) begin\n\t\t\t\t\tassert (csr_insn_changed_full[63:32] == 0);\n\t\t\t\tend\n`endif\n\t\t\tend\n\n\t\t\tassert (rvfi.mem_wmask == 0);\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_dmem_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_dmem_check (\n\tinput clock, reset, enable,\n\toutput [`RISCV_FORMAL_XLEN-1:0] dmem_addr,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] dmem_addr_randval;\n\tassign dmem_addr = dmem_addr_randval;\n\n\treg [`RISCV_FORMAL_XLEN-1:0] dmem_shadow;\n\treg [`RISCV_FORMAL_XLEN/8-1:0] dmem_written = 0;\n\n\tinteger channel_idx;\n\tinteger i;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tdmem_written <= 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_mem_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN] == dmem_addr && `rvformal_addr_valid(dmem_addr)) begin\n\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin\n\t\t\t\t\t\tif (enable && rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i] && dmem_written[i])\n\t\t\t\t\t\t\tassert(dmem_shadow[i*8 +: 8] == rvfi_mem_rdata[i*8 +: 8]);\n\t\t\t\t\t\tif (rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i]) begin\n\t\t\t\t\t\t\tdmem_shadow[i*8 +: 8] = rvfi_mem_wdata[i*8 +: 8];\n\t\t\t\t\t\t\tdmem_written[i] = 1;\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_fault_check.sv",
    "content": "// check handling of memory faults\n//\n// This checks that a dynamically occuring memory fault causes a trap and that\n// the mcause csr correctly reports the cause of the trap.\n//\n// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_fault_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n`ifdef RISCV_FORMAL_CHANNEL_IDX\n\tlocalparam integer channel_idx = `RISCV_FORMAL_CHANNEL_IDX;\n`else\n\tgenvar channel_idx;\n\tgenerate for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin:channel\n`endif\n\t\t(* keep *) wire valid = !reset && rvfi_valid[channel_idx];\n\t\t(* keep *) wire [`RISCV_FORMAL_ILEN   - 1 : 0] insn      = rvfi_insn     [channel_idx*`RISCV_FORMAL_ILEN   +: `RISCV_FORMAL_ILEN];\n\t\t(* keep *) wire                                trap      = rvfi_trap     [channel_idx];\n\t\t(* keep *) wire                                mem_fault = rvfi_mem_fault[channel_idx];\n\t\t(* keep *) wire                                halt      = rvfi_halt     [channel_idx];\n\t\t(* keep *) wire                                intr      = rvfi_intr     [channel_idx];\n\t\t(* keep *) wire [                       4 : 0] rs1_addr  = rvfi_rs1_addr [channel_idx*5  +:  5];\n\t\t(* keep *) wire [                       4 : 0] rs2_addr  = rvfi_rs2_addr [channel_idx*5  +:  5];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs1_rdata = rvfi_rs1_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs2_rdata = rvfi_rs2_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [                       4 : 0] rd_addr   = rvfi_rd_addr  [channel_idx*5  +:  5];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rd_wdata  = rvfi_rd_wdata [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_rdata  = rvfi_pc_rdata [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_wdata  = rvfi_pc_wdata [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_addr  = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\n`ifdef RISCV_FORMAL_CSR_MCAUSE\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN-1:0] csr_mcause_wmask = rvfi_csr_mcause_wmask[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN-1:0] csr_mcause_wdata = rvfi_csr_mcause_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n`endif\n\n\t\twire rfault = |mem_fault_rmask;\n\t\twire wfault = |mem_fault_wmask;\n\t\twire ifault = !(rfault || wfault);\n\n\t\talways @* begin\n\t\t\tif (!reset && check) begin\n\t\t\t\tassume(valid);\n\t\t\t\tif (mem_fault) begin\n\n\t\t\t\t\tassert (trap);\n\t\t\t\t\tassert (rd_addr == 0);\n\t\t\t\t\tassert (rd_wdata == 0);\n\t\t\t\t\tassert (mem_wmask == 0);\n\n\t\t\t\t\tcover (rfault);\n\t\t\t\t\tcover (wfault);\n\t\t\t\t\tcover (ifault);\n\n\t\t\t\t\tif (ifault) begin\n\t\t\t\t\t\tassert (insn == 0);\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tassert (insn != 0);\n\t\t\t\t\tend\n\n`ifdef RISCV_FORMAL_CSR_MCAUSE\n\t\t\t\t\tif (wfault) begin\n\t\t\t\t\t\tassert (&csr_mcause_wmask);\n\t\t\t\t\t\tassert (csr_mcause_wdata == 7);\n\t\t\t\t\tend else if (rfault) begin\n\t\t\t\t\t\tassert (&csr_mcause_wmask);\n\t\t\t\t\t\tassert (csr_mcause_wdata == 5);\n\t\t\t\t\tend else if (ifault) begin\n\t\t\t\t\t\tassert (&csr_mcause_wmask);\n\t\t\t\t\t\tassert (csr_mcause_wdata == 1);\n\t\t\t\t\tend\n`endif\n\t\t\t\telse begin end\n\t\t\t\tend else begin\n\t\t\t\t\tassert (mem_fault_rmask == 0);\n\t\t\t\t\tassert (mem_fault_wmask == 0);\n\t\t\t\tend\n\t\t\tend\n\t\tend\n`ifndef RISCV_FORMAL_CHANNEL_IDX\n\tend endgenerate\n`endif\nendmodule\n"
  },
  {
    "path": "checks/rvfi_hang_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_hang_check (\n\tinput clock, reset, trig, check,\n\t`RVFI_INPUTS\n);\n\treg okay = 0;\n\n\tinteger channel_idx;\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tokay <= 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_valid[channel_idx])\n\t\t\t\t\tokay <= 1;\n\t\t\tend\n\t\t\tif (check) begin\n\t\t\t\tassert(okay);\n\t\t\tend\n\t\tend\n\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\tif (rvfi_valid[channel_idx]) begin\n\t\t\t\tassume(!rvfi_halt[channel_idx]);\n\t\t\t\tassume(rvfi_insn[(channel_idx+1)*`RISCV_FORMAL_ILEN-1 : channel_idx*`RISCV_FORMAL_ILEN] != 32'b 0001000_00101_00000_000_00000_1110011); // WFI\n`ifdef RISCV_FORMAL_WAITINSN\n\t\t\t\tassume(!(`RISCV_FORMAL_WAITINSN(rvfi_insn[(channel_idx+1)*`RISCV_FORMAL_ILEN-1 : channel_idx*`RISCV_FORMAL_ILEN])));\n`endif\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_ill_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_ill_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n`ifdef RISCV_FORMAL_CHANNEL_IDX\n\tlocalparam integer channel_idx = `RISCV_FORMAL_CHANNEL_IDX;\n`else\n\tgenvar channel_idx;\n\tgenerate for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin:channel\n`endif\n\t\t(* keep *) wire valid = !reset && rvfi_valid[channel_idx];\n\t\t(* keep *) wire [`RISCV_FORMAL_ILEN   - 1 : 0] insn      = rvfi_insn     [channel_idx*`RISCV_FORMAL_ILEN   +: `RISCV_FORMAL_ILEN];\n\t\t(* keep *) wire                                trap      = rvfi_trap     [channel_idx];\n\t\t(* keep *) wire                                halt      = rvfi_halt     [channel_idx];\n\t\t(* keep *) wire                                intr      = rvfi_intr     [channel_idx];\n\t\t(* keep *) wire [                       4 : 0] rs1_addr  = rvfi_rs1_addr [channel_idx*5  +:  5];\n\t\t(* keep *) wire [                       4 : 0] rs2_addr  = rvfi_rs2_addr [channel_idx*5  +:  5];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs1_rdata = rvfi_rs1_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs2_rdata = rvfi_rs2_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [                       4 : 0] rd_addr   = rvfi_rd_addr  [channel_idx*5  +:  5];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rd_wdata  = rvfi_rd_wdata [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_rdata  = rvfi_pc_rdata [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_wdata  = rvfi_pc_wdata [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_addr  = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\n\t\talways @* begin\n\t\t\tcover(!reset && check && valid && insn == 0);\n\t\t\tif (!reset && check) begin\n\t\t\t\tassume(valid);\n\t\t\t\tassume(insn == 0);\n\t\t\t\tassert(trap);\n\t\t\t\tassert(rd_addr == 0);\n\t\t\t\tassert(rd_wdata == 0);\n\t\t\t\tassert(mem_wmask == 0);\n\t\t\tend\n\t\tend\n`ifndef RISCV_FORMAL_CHANNEL_IDX\n\tend endgenerate\n`endif\nendmodule\n"
  },
  {
    "path": "checks/rvfi_imem_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_imem_check (\n\tinput clock, reset, enable,\n\toutput [`RISCV_FORMAL_XLEN-1:0] imem_addr,\n\toutput [15:0] imem_data,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [`RISCV_FORMAL_XLEN-1:0] imem_addr_randval;\n\t`rvformal_rand_const_reg [15:0] imem_data_randval;\n\tassign imem_addr = imem_addr_randval;\n\tassign imem_data = imem_data_randval;\n\n\treg [`RISCV_FORMAL_XLEN-1:0] pc;\n\treg [`RISCV_FORMAL_ILEN-1:0] insn;\n\n\tinteger channel_idx;\n\tinteger i;\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tif (enable && rvfi_valid[channel_idx]) begin\n\t\t\t\t\tpc = rvfi_pc_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\tinsn = rvfi_insn[channel_idx*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN];\n\n\t\t\t\t\tif (`rvformal_addr_valid(pc) && pc == imem_addr)\n\t\t\t\t\t\tassert(insn[15:0] == imem_data);\n\n\t\t\t\t\tif (insn[1:0] == 2'b11 && `rvformal_addr_valid(pc+2) && pc+2 == imem_addr)\n\t\t\t\t\t\tassert(insn[31:16] == imem_data);\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_insn_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_insn_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n`ifdef RISCV_FORMAL_CHANNEL_IDX\n\tlocalparam integer channel_idx = `RISCV_FORMAL_CHANNEL_IDX;\n`else\n\tgenvar channel_idx;\n\tgenerate for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin:channel\n`endif\n\t\t(* keep *) wire valid = !reset && rvfi_valid[channel_idx];\n\t\t(* keep *) wire [`RISCV_FORMAL_ILEN   - 1 : 0] insn      = rvfi_insn     [channel_idx*`RISCV_FORMAL_ILEN   +: `RISCV_FORMAL_ILEN];\n\t\t(* keep *) wire                                trap      = rvfi_trap     [channel_idx];\n\t\t(* keep *) wire                                halt      = rvfi_halt     [channel_idx];\n\t\t(* keep *) wire                                intr      = rvfi_intr     [channel_idx];\n\t\t(* keep *) wire [                       4 : 0] rs1_addr  = rvfi_rs1_addr [channel_idx*5  +:  5];\n\t\t(* keep *) wire [                       4 : 0] rs2_addr  = rvfi_rs2_addr [channel_idx*5  +:  5];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs1_rdata = rvfi_rs1_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs2_rdata = rvfi_rs2_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [                       4 : 0] rd_addr   = rvfi_rd_addr  [channel_idx*5  +:  5];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rd_wdata  = rvfi_rd_wdata [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_rdata  = rvfi_pc_rdata [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_wdata  = rvfi_pc_wdata [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_addr  = rvfi_mem_addr [channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_rdata = rvfi_mem_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_wdata = rvfi_mem_wdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t(* keep *) wire                                mem_fault = rvfi_mem_fault[channel_idx];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_rmask = rvfi_mem_fault_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_wmask = rvfi_mem_fault_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 +: `RISCV_FORMAL_XLEN/8];\n`endif\n\n`ifdef RISCV_FORMAL_CSR_MISA\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] csr_misa_rdata = rvfi_csr_misa_rdata[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] csr_misa_rmask = rvfi_csr_misa_rmask[channel_idx*`RISCV_FORMAL_XLEN   +: `RISCV_FORMAL_XLEN];\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask;\n`endif\n\n\t\t(* keep *) wire                                spec_valid;\n\t\t(* keep *) wire                                spec_trap;\n\t\t(* keep *) wire [                       4 : 0] spec_rs1_addr;\n\t\t(* keep *) wire [                       4 : 0] spec_rs2_addr;\n\t\t(* keep *) wire [                       4 : 0] spec_rd_addr;\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata;\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata;\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr;\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask;\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask;\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata;\n\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs1_rdata_or_zero = spec_rs1_addr != 0 ? rs1_rdata : 0;\n\t\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs2_rdata_or_zero = spec_rs2_addr != 0 ? rs2_rdata : 0;\n\n\t\t`RISCV_FORMAL_INSN_MODEL insn_spec (\n\t\t\t.rvfi_valid          (valid              ),\n\t\t\t.rvfi_insn           (insn               ),\n\t\t\t.rvfi_pc_rdata       (pc_rdata           ),\n\t\t\t.rvfi_rs1_rdata      (rs1_rdata_or_zero  ),\n\t\t\t.rvfi_rs2_rdata      (rs2_rdata_or_zero  ),\n\t\t\t.rvfi_mem_rdata      (mem_rdata          ),\n\n`ifdef RISCV_FORMAL_CSR_MISA\n\t\t\t.rvfi_csr_misa_rdata (csr_misa_rdata     ),\n\t\t\t.spec_csr_misa_rmask (spec_csr_misa_rmask),\n`endif\n\n\t\t\t.spec_valid          (spec_valid         ),\n\t\t\t.spec_trap           (spec_trap          ),\n\t\t\t.spec_rs1_addr       (spec_rs1_addr      ),\n\t\t\t.spec_rs2_addr       (spec_rs2_addr      ),\n\t\t\t.spec_rd_addr        (spec_rd_addr       ),\n\t\t\t.spec_rd_wdata       (spec_rd_wdata      ),\n\t\t\t.spec_pc_wdata       (spec_pc_wdata      ),\n\t\t\t.spec_mem_addr       (spec_mem_addr      ),\n\t\t\t.spec_mem_rmask      (spec_mem_rmask     ),\n\t\t\t.spec_mem_wmask      (spec_mem_wmask     ),\n\t\t\t.spec_mem_wdata      (spec_mem_wdata     )\n\t\t);\n\n\t\twire insn_pma_x, mem_pma_r, mem_pma_w;\n\n\t\twire [1:0] mem_log2len =\n\t\t\t((spec_mem_rmask | spec_mem_wmask) & 8'b 1111_0000) ? 3 :\n\t\t\t((spec_mem_rmask | spec_mem_wmask) & 8'b 0000_1100) ? 2 :\n\t\t\t((spec_mem_rmask | spec_mem_wmask) & 8'b 0000_0010) ? 1 : 0;\n\n`ifdef RISCV_FORMAL_PMA_MAP\n\t\t`RISCV_FORMAL_PMA_MAP insn_pma (\n\t\t\t.address(pc_rdata),\n\t\t\t.log2len(insn[1:0] == 2'b11 ? 2'd2 : 2'd1),\n\t\t\t.X(insn_pma_x)\n\t\t);\n\n\t\t`RISCV_FORMAL_PMA_MAP mem_pma (\n\t\t\t.address(spec_mem_addr),\n\t\t\t.log2len(mem_log2len),\n\t\t\t.R(mem_pma_r),\n\t\t\t.W(mem_pma_w)\n\t\t);\n`else\n\t\tassign insn_pma_x = 1;\n\t\tassign mem_pma_r = 1;\n\t\tassign mem_pma_w = 1;\n`endif\n\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\twire mem_access_fault = mem_fault ||\n`else\n\t\twire mem_access_fault =\n`endif\n\t\t\t\t(spec_mem_rmask && !mem_pma_r) || (spec_mem_wmask && !mem_pma_w) ||\n\t\t\t\t((spec_mem_rmask || spec_mem_wmask) && !`rvformal_addr_valid(spec_mem_addr));\n\n\t\tinteger i;\n\n\t\talways @* begin\n\t\t\tif (!reset) begin\n\t\t\t\tcover(spec_valid);\n\t\t\t\tcover(spec_valid && !trap);\n\t\t\t\tcover(check && spec_valid);\n\t\t\t\tcover(check && spec_valid && !trap);\n\t\t\tend\n\t\t\tif (!reset && check) begin\n\t\t\t\tassume(spec_valid);\n\n\t\t\t\tif (!`rvformal_addr_valid(pc_rdata) || !insn_pma_x || mem_access_fault) begin\n\t\t\t\t\tassert(trap);\n\t\t\t\t\tassert(rd_addr == 0);\n\t\t\t\t\tassert(rd_wdata == 0);\n\t\t\t\t\tassert(mem_wmask == 0);\n`ifdef RISCV_FORMAL_MEM_FAULT\n\t\t\t\t\tif (mem_fault) begin\n\t\t\t\t\t\tassert(mem_rmask == 0);\n\t\t\t\t\t\tassert(spec_mem_wmask || spec_mem_rmask);\n\t\t\t\t\t\tassert(`rvformal_addr_eq(spec_mem_addr, mem_addr));\n\n\t\t\t\t\t\tassert(mem_fault_wmask == spec_mem_wmask);\n\t\t\t\t\t\tassert((mem_fault_rmask & spec_mem_rmask) == spec_mem_rmask);\n\t\t\t\t\tend\n`endif\n\t\t\t\tend else begin\n`ifdef RISCV_FORMAL_CSR_MISA\n\t\t\t\t\tassert((spec_csr_misa_rmask & csr_misa_rmask) == spec_csr_misa_rmask);\n`endif\n\n\t\t\t\t\tif (rs1_addr == 0)\n\t\t\t\t\t\tassert(rs1_rdata == 0);\n\n\t\t\t\t\tif (rs2_addr == 0)\n\t\t\t\t\t\tassert(rs2_rdata == 0);\n\n\t\t\t\t\tif (!spec_trap) begin\n\t\t\t\t\t\tif (spec_rs1_addr != 0)\n\t\t\t\t\t\t\tassert(spec_rs1_addr == rs1_addr);\n\n\t\t\t\t\t\tif (spec_rs2_addr != 0)\n\t\t\t\t\t\t\tassert(spec_rs2_addr == rs2_addr);\n\n\t\t\t\t\t\tassert(spec_rd_addr == rd_addr);\n\t\t\t\t\t\tassert(spec_rd_wdata == rd_wdata);\n\t\t\t\t\t\tassert(`rvformal_addr_eq(spec_pc_wdata, pc_wdata));\n\n\t\t\t\t\t\tif (spec_mem_wmask || spec_mem_rmask) begin\n\t\t\t\t\t\t\tassert(`rvformal_addr_eq(spec_mem_addr, mem_addr));\n\t\t\t\t\t\tend\n\n\t\t\t\t\t\tfor (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin\n\t\t\t\t\t\t\tif (spec_mem_wmask[i]) begin\n\t\t\t\t\t\t\t\tassert(mem_wmask[i]);\n\t\t\t\t\t\t\t\tassert(spec_mem_wdata[i*8 +: 8] == mem_wdata[i*8 +: 8]);\n\t\t\t\t\t\t\tend else if (mem_wmask[i]) begin\n\t\t\t\t\t\t\t\tassert(mem_rmask[i]);\n\t\t\t\t\t\t\t\tassert(mem_rdata[i*8 +: 8] == mem_wdata[i*8 +: 8]);\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tif (spec_mem_rmask[i]) begin\n\t\t\t\t\t\t\t\tassert(mem_rmask[i]);\n\t\t\t\t\t\t\tend\n\t\t\t\t\t\tend\n\t\t\t\t\tend\n\n\t\t\t\t\tassert(spec_trap == trap);\n\t\t\t\tend\n\t\t\tend\n\t\tend\n`ifndef RISCV_FORMAL_CHANNEL_IDX\n\tend endgenerate\n`endif\nendmodule\n"
  },
  {
    "path": "checks/rvfi_liveness_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_liveness_check (\n\tinput clock, reset, trig, check,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\treg found_next_insn = 0;\n\n\tinteger channel_idx;\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tfound_next_insn = 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order+1) begin\n\t\t\t\t\tfound_next_insn = 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tif (trig) begin\n\t\t\t\tassume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\tassume(!rvfi_halt[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\tassume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]);\n\t\t\tend\n\t\t\tif (check) begin\n\t\t\t\tassert(found_next_insn);\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_macros.py",
    "content": "#!/usr/bin/env python3\n#\n# Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n#\n# Permission to use, copy, modify, and/or distribute this software for any\n# purpose with or without fee is hereby granted, provided that the above\n# copyright notice and this permission notice appear in all copies.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\nfrom dataclasses import dataclass, field\nfrom typing import Optional, List, Tuple\n\n@dataclass\nclass Group:\n    name: str\n    signals: List[Tuple[str, str]]\n    channels: Optional[str] = None\n    condition: Optional[str] = None\n    nosep: bool = False\n    csr_conn32: bool = False\n    append: List['Group'] = field(default_factory=list)\n\n    def __post_init__(self):\n        self._cw = max((len(width) for width, name in self.signals), default=0)\n        self._cn = max((len(name) for width, name in self.signals), default=0)\n        self._has_conn32 = self.csr_conn32 or any(g._has_conn32 for g in self.append)\n\n    def bitrange(self, width, no_channel=False):\n        if no_channel or self.channels is None:\n            if str(width).strip() == '1':\n                return f\"[{'':>{self._cw}}   0 : 0]\"\n            else:\n                return f\"[{width:>{self._cw}} - 1 : 0]\"\n        elif str(width).strip() == '1':\n            return f\"[{self.channels}   {'':>{self._cw}} - 1 : 0]\"\n        else:\n            return f\"[{self.channels} * {width:>{self._cw}} - 1 : 0]\"\n\n    def channel_idx(self, width):\n        if str(width).strip() == '1':\n            return f\"[ _idx   {'':>{self._cw}}  +: {width:>{self._cw}}]\"\n        else:\n            return f\"[(_idx)*({width:>{self._cw}}) +: {width:>{self._cw}}]\"\n\n    def macro_name(self, s, extra=\"\"):\n        if self.name.upper() == self.name:\n            if s == \"channel\":\n                return f\"{self.name}_GETCHANNEL{extra.upper()}(_idx)\"\n            elif s == \"channel_conn\":\n                return f\"{self.name}_CHANNEL_CONN{extra.upper()}(_idx)\"\n            else:\n                return f\"{self.name}_{s.upper()}{extra.upper()}\"\n        else:\n            if s == \"channel\":\n                return f\"{self.name}_channel{extra}(_idx)\"\n            elif s == \"channel_conn\":\n                return f\"{self.name}_channel_conn{extra}(_idx)\"\n            else:\n                return f\"{self.name}_{s}{extra}\"\n\n    def macro_name_nosep(self, s):\n        if self.nosep:\n            return self.macro_name(s, extra=\"_nosep\")\n        else:\n            return self.macro_name(s)\n\n    def commas(self, parts, suffix=()):\n        if (self.condition and not self.nosep) or len(parts) < 2:\n            return \" \\\\\\n  \".join([\", \\\\\\n  \".join(parts), *suffix])\n        else:\n            first, *parts = parts\n            return \" \\\\\\n  \".join([first, \", \\\\\\n  \".join(parts), *suffix])\n\n    def high_name(self, name):\n        parts = name.split('_')\n        parts[-2] += 'h'\n        return '_'.join(parts)\n\n    def print_macros(self):\n        if self.condition:\n            print(f\"`ifdef {self.condition}\")\n        print(self.commas([f\"`define {self.macro_name('wires')}\"], [\n            f\"(* keep *) wire {self.bitrange(width)} rvfi_{name:<{self._cn}};\"\n            for width, name in self.signals\n        ] + [\n            \"`\" + group.macro_name('wires') for group in self.append\n        ]))\n        print(self.commas([f\"`define {self.macro_name_nosep('outputs')}\"] + [\n            f\"output {self.bitrange(width)} rvfi_{name:<{self._cn}}\"\n            for width, name in self.signals\n        ], [\n            \"`\" + group.macro_name('outputs') for group in self.append\n        ]))\n        print(self.commas([f\"`define {self.macro_name_nosep('channel_outputs')}\"] + [\n            f\"output {self.bitrange(width, no_channel=True)} rvfi_{name:<{self._cn}}\"\n            for width, name in self.signals\n        ], [\n            \"`\" + group.macro_name('channel_outputs') for group in self.append\n        ]))\n        print(self.commas([f\"`define {self.macro_name_nosep('inputs')}\"] + [\n            f\"input {self.bitrange(width)} rvfi_{name:<{self._cn}}\"\n            for width, name in self.signals\n        ], [\n            \"`\" + group.macro_name('inputs') for group in self.append\n        ]))\n        print(self.commas([f\"`define {self.macro_name_nosep('channel_inputs')}\"] + [\n            f\"input {self.bitrange(width, no_channel=True)} rvfi_{name:<{self._cn}}\"\n            for width, name in self.signals\n        ], [\n            \"`\" + group.macro_name('channel_inputs') for group in self.append\n        ]))\n        print(self.commas([f\"`define {self.macro_name_nosep('conn')}\"] + [\n            f\".rvfi_{name:<{self._cn}} (rvfi_{name:<{self._cn}})\"\n            for width, name in self.signals\n        ], [\n            \"`\" + group.macro_name('conn') for group in self.append\n        ]))\n        print(self.commas([f\"`define {self.macro_name_nosep('channel_conn')}\"] + [\n            f\".rvfi_{name:<{self._cn}} (rvfi_{name:<{self._cn}} {self.channel_idx(width)})\"\n            for width, name in self.signals\n        ], [\n            \"`\" + group.macro_name('channel_conn') for group in self.append\n        ]))\n        if self.csr_conn32:\n            cn = self._cn + self.csr_conn32\n            print(self.commas([f\"`define {self.macro_name_nosep('conn32')}\"] + [\n                f\".rvfi_{name:<{cn}} (rvfi_{name:<{self._cn}}[31: 0])\"\n                for width, name in self.signals\n            ] + [\n                f\".rvfi_{self.high_name(name):<{cn}} (rvfi_{name:<{self._cn}}[63:32])\"\n                for width, name in self.signals\n            ], [\n                \"`\" + group.macro_name('conn32') for group in self.append\n            ]))\n        elif self._has_conn32:\n            print(self.commas([f\"`define {self.macro_name_nosep('conn32')}\"] + [\n                f\".rvfi_{name:<{self._cn}} (rvfi_{name:<{self._cn}})\"\n                for width, name in self.signals\n            ], [\n                \"`\" + group.macro_name('conn32' if group._has_conn32 else 'conn') for group in self.append\n            ]))\n        if self.channels:\n            print(self.commas([f\"`define {self.macro_name('channel')}\"], [\n                f\"wire {self.bitrange(width, True)} {name:<{self._cn}} = \"\n                f\"rvfi_{name:<{self._cn}} {self.channel_idx(width)};\"\n                for width, name in self.signals\n            ] + [\n                \"`\" + group.macro_name('channel') for group in self.append if group.channels\n            ]))\n            print(self.commas([f\"`define {self.macro_name('signals')}\"], [\n                f\"`RISCV_FORMAL_CHANNEL_SIGNAL({self.channels}, {width:>{self._cw}}, {name:<{self._cn}})\"\n                for width, name in self.signals\n            ] + [\n                \"`\" + group.macro_name('signals') for group in self.append if group.channels\n            ]))\n\n        if self.nosep:\n            print(f\"`define {self.macro_name('outputs')} , `{self.macro_name_nosep('outputs')}\")\n            print(f\"`define {self.macro_name('inputs')} , `{self.macro_name_nosep('inputs')}\")\n            print(f\"`define {self.macro_name('conn')}  , `{self.macro_name_nosep('conn')}\")\n            print(f\"`define {self.macro_name('channel_outputs')} , `{self.macro_name_nosep('channel_outputs')}\")\n            print(f\"`define {self.macro_name('channel_inputs')} , `{self.macro_name_nosep('channel_inputs')}\")\n            print(f\"`define {self.macro_name('channel_conn')}  , `{self.macro_name_nosep('channel_conn')}\")\n            if self._has_conn32:\n                print(f\"`define {self.macro_name('conn32')}\")\n\n\n        if self.condition:\n            print(\"`else\")\n            print(f\"`define {self.macro_name('wires')}\")\n            print(f\"`define {self.macro_name('outputs')}\")\n            print(f\"`define {self.macro_name('inputs')}\")\n            print(f\"`define {self.macro_name('conn')}\")\n            if self._has_conn32:\n                print(f\"`define {self.macro_name('conn32')}\")\n            if self.channels:\n                print(f\"`define {self.macro_name('channel')}\")\n            print(\"`endif\")\n\n\n        if self.name.upper() == self.name:\n            print(\"\")\n            print(f\"`define {self.name}_CHANNEL(_name, _idx) \\\\\")\n            print(\"generate if(1) begin:_name \\\\\")\n            print(f\"  `{self.name}_GETCHANNEL(_idx) \\\\\")\n            print(\"end endgenerate\")\n\n        return self\n\n\n@dataclass\nclass Csr:\n    len: str\n    name: str\n    mindex: Optional[int] = None\n    sindex: Optional[int] = None\n    uindex: Optional[int] = None\n\n    hmindex: Optional[int] = None\n    hsindex: Optional[int] = None\n    huindex: Optional[int] = None\n\n\ncsrs = [\n    Csr(\"xlen\", \"fflags\",             None,  None,  None),\n    Csr(\"xlen\", \"frm\",                None,  None,  None),\n    Csr(\"xlen\", \"fcsr\",               None,  None,  None),\n    Csr(\"xlen\", \"mvendorid\",         0xF11,  None,  None),\n    Csr(\"xlen\", \"marchid\",           0xF12,  None,  None),\n    Csr(\"xlen\", \"mimpid\",            0xF13,  None,  None),\n    Csr(\"xlen\", \"mhartid\",           0xF14,  None,  None),\n    Csr(\"xlen\", \"mconfigptr\",        0xF15,  None,  None),\n    Csr(\"xlen\", \"mstatus\",           0x300,  None,  None),\n    Csr(\"xlen\", \"mstatush\",          0x310,  None,  None),\n    Csr(\"xlen\", \"misa\",              0x301,  None,  None),\n    Csr(\"xlen\", \"medeleg\",           0x302,  None,  None),\n    Csr(\"xlen\", \"mideleg\",           0x303,  None,  None),\n    Csr(\"xlen\", \"mie\",               0x304,  None,  None),\n    Csr(\"xlen\", \"mtvec\",             0x305,  None,  None),\n    Csr(\"xlen\", \"mcounteren\",        0x306,  None,  None),\n    Csr(\"xlen\", \"mscratch\",          0x340,  None,  None),\n    Csr(\"xlen\", \"mepc\",              0x341,  None,  None),\n    Csr(\"xlen\", \"mcause\",            0x342,  None,  None),\n    Csr(\"xlen\", \"mtval\",             0x343,  None,  None),\n    Csr(\"xlen\", \"mip\",               0x344,  None,  None),\n    Csr(\"xlen\", \"mtinst\",            0x34A,  None,  None),\n    Csr(\"xlen\", \"mtval2\",            0x34B,  None,  None),\n    Csr(\"xlen\", \"mcountinhibit\",     0x320,  None,  None),\n    Csr(\"xlen\", \"menvcfg\",           0x30A,  None,  None),\n    Csr(\"xlen\", \"menvcfgh\",          0x31A,  None,  None),\n    *(\n        Csr(\"xlen\", f\"pmpcfg{i}\",    0x3A0 + i,  None,  None)\n        for i in range(16)\n    ),\n    *(\n        Csr(\"xlen\", f\"pmpaddr{i}\",   0x3B0 + i,  None,  None)\n        for i in range(64)\n    ),\n    *(\n        Csr(\"xlen\", f\"mhpmevent{i}\",  0x320 + i,  None,  None)\n        for i in range(3, 32)\n    ),\n    Csr(\"64\",   \"mcycle\",            0xB00,  None, 0xC00,\n                                     0xB80,  None, 0xC80),\n    Csr(\"64\",   \"time\",               None,  None, 0xC01,\n                                      None,  None, 0xC01),\n    Csr(\"64\",   \"minstret\",          0xB02,  None, 0xC02,\n                                     0xB82,  None, 0xC82),\n    *(\n        Csr(\"64\", f\"mhpmcounter{i}\", 0xB00 + i, None, 0xC00 + i,\n                                     0xB80 + i, None, 0xC80 + i)\n        for i in range(3, 32)\n    ),\n]\n\nprint(\"// Generated by rvfi_macros.py\")\nprint(\"\")\nprint(\"`ifdef YOSYS\")\nprint(\"`define rvformal_rand_reg rand reg\")\nprint(\"`define rvformal_rand_const_reg rand const reg\")\nprint(\"`else\")\nprint(\"`ifdef SIMULATION\")\nprint(\"`define rvformal_rand_reg reg\")\nprint(\"`define rvformal_rand_const_reg reg\")\nprint(\"`else\")\nprint(\"`define rvformal_rand_reg wire\")\nprint(\"`define rvformal_rand_const_reg reg\")\nprint(\"`endif\")\nprint(\"`endif\")\nprint(\"\")\nprint(\"`ifndef RISCV_FORMAL_VALIDADDR\")\nprint(\"`define RISCV_FORMAL_VALIDADDR(addr) 1\")\nprint(\"`endif\")\nprint(\"\")\nprint(\"`ifndef RISCV_FORMAL_IOADDR\")\nprint(\"`define RISCV_FORMAL_IOADDR(addr) 1\")\nprint(\"`endif\")\nprint(\"\")\nprint(\"`define rvformal_addr_valid(a) (`RISCV_FORMAL_VALIDADDR(a))\")\nprint(\"`define rvformal_addr_io(a) (`rvformal_addr_valid(a) && (`RISCV_FORMAL_IOADDR(a)))\")\nprint(\"`define rvformal_addr_eq(a, b) ((`rvformal_addr_valid(a) == `rvformal_addr_valid(b)) && (!`rvformal_addr_valid(a) || (a == b)))\")\nprint(\"`define rvformal_addr_eq_io(a, b) (`rvformal_addr_io(a) ? `rvformal_addr_io(b) : `rvformal_addr_eq(a, b))\")\nprint(\"\")\n\ncsr_groups = []\n\ndef csr_index(index):\n    if index is None:\n        return \"12'hFFF\"\n    else:\n        return f\"12'h{index:03X}\"\n\nfor csr in csrs:\n    width = {\"64\": \"64\", \"xlen\": \"`RISCV_FORMAL_XLEN\"}[csr.len]\n    csr_groups.append(Group(\n        condition=f\"RISCV_FORMAL_CSR_{csr.name.upper()}\",\n        name=f\"rvformal_csr_{csr.name}\",\n        channels=\"`RISCV_FORMAL_NRET\",\n        csr_conn32=csr.len == \"64\",\n        signals=[\n            (width, f\"csr_{csr.name}_rmask\"),\n            (width, f\"csr_{csr.name}_wmask\"),\n            (width, f\"csr_{csr.name}_rdata\"),\n            (width, f\"csr_{csr.name}_wdata\"),\n        ]\n    ).print_macros())\n\n    print(f\"`define rvformal_csr_{csr.name}_indices \\\\\")\n    print(f\"localparam [11:0] csr_mindex_{csr.name} = {csr_index(csr.mindex)}; \\\\\")\n    print(f\"localparam [11:0] csr_sindex_{csr.name} = {csr_index(csr.sindex)}; \\\\\")\n    print(f\"localparam [11:0] csr_uindex_{csr.name} = {csr_index(csr.uindex)}; \\\\\")\n    if csr.len == \"64\":\n        print(f\"localparam [11:0] csr_mindex_{csr.name}h = {csr_index(csr.hmindex)}; \\\\\")\n        print(f\"localparam [11:0] csr_sindex_{csr.name}h = {csr_index(csr.hsindex)}; \\\\\")\n        print(f\"localparam [11:0] csr_uindex_{csr.name}h = {csr_index(csr.huindex)}; \\\\\")\n    print()\n\nprint(\"`define RVFI_INDICES \\\\\")\nfor csr in csrs:\n    print(f\"`rvformal_csr_{csr.name}_indices \\\\\")\nprint(\"`rvformal_custom_csr_indices\")\nprint()\n\n# Do not print this group, we'll use user macros when defined instead\ncustom_csr = Group(name=\"rvformal_custom_csr\", signals=[], channels=\"`RISCV_FORMAL_NRET\",)\n\nfor macro in [\"inputs\", \"wires\", \"conn\", \"channel\", \"signals\", \"outputs\", \"indices\"]:\n    print(f\"`ifdef RISCV_FORMAL_CUSTOM_CSR_{macro.upper()}\")\n    if (macro == \"channel\"):\n        print(f\"`define rvformal_custom_csr_{macro}(_idx) `RISCV_FORMAL_CUSTOM_CSR_{macro.upper()}(_idx)\")\n        print(f\"`else\")\n        print(f\"`define rvformal_custom_csr_{macro}(_idx)\")\n    else:\n        print(f\"`define rvformal_custom_csr_{macro} `RISCV_FORMAL_CUSTOM_CSR_{macro.upper()}\")\n        print(f\"`else\")\n        print(f\"`define rvformal_custom_csr_{macro}\")\n    print(f\"`endif\")\n\ngroup_rollback = Group(\n    condition=\"RISCV_FORMAL_ROLLBACK\",\n    name=\"rvformal_rollback\",\n    signals=[\n        (\" 1\", \"rollback_valid\"),\n        (\"64\", \"rollback_order\"),\n    ]\n).print_macros()\n\ngroup_extamo = Group(\n    condition=\"RISCV_FORMAL_EXTAMO\",\n    name=\"rvformal_extamo\",\n    channels=\"`RISCV_FORMAL_NRET\",\n    signals=[\n        (\"1\", \"mem_extamo\"),\n    ]\n).print_macros()\n\ngroup_fault = Group(\n    condition=\"RISCV_FORMAL_MEM_FAULT\",\n    name=\"rvformal_mem_fault\",\n    channels=\"`RISCV_FORMAL_NRET\",\n    signals=[\n        (\"                 1  \", \"mem_fault\"),\n        (\"`RISCV_FORMAL_XLEN/8\", \"mem_fault_rmask\"),\n        (\"`RISCV_FORMAL_XLEN/8\", \"mem_fault_wmask\"),\n    ]\n).print_macros()\n\nrvfi = Group(\n    name=\"RVFI\",\n    channels=\"`RISCV_FORMAL_NRET\",\n    signals=[\n        (\"                 1  \", \"valid    \"),\n        (\"                64  \", \"order    \"),\n        (\"`RISCV_FORMAL_ILEN  \", \"insn     \"),\n        (\"                 1  \", \"trap     \"),\n        (\"                 1  \", \"halt     \"),\n        (\"                 1  \", \"intr     \"),\n        (\"                 2  \", \"mode     \"),\n        (\"                 2  \", \"ixl      \"),\n        (\"                 5  \", \"rs1_addr \"),\n        (\"                 5  \", \"rs2_addr \"),\n        (\"`RISCV_FORMAL_XLEN  \", \"rs1_rdata\"),\n        (\"`RISCV_FORMAL_XLEN  \", \"rs2_rdata\"),\n        (\"                 5  \", \"rd_addr  \"),\n        (\"`RISCV_FORMAL_XLEN  \", \"rd_wdata \"),\n        (\"`RISCV_FORMAL_XLEN  \", \"pc_rdata \"),\n        (\"`RISCV_FORMAL_XLEN  \", \"pc_wdata \"),\n        (\"`RISCV_FORMAL_XLEN  \", \"mem_addr \"),\n        (\"`RISCV_FORMAL_XLEN/8\", \"mem_rmask\"),\n        (\"`RISCV_FORMAL_XLEN/8\", \"mem_wmask\"),\n        (\"`RISCV_FORMAL_XLEN  \", \"mem_rdata\"),\n        (\"`RISCV_FORMAL_XLEN  \", \"mem_wdata\"),\n    ],\n    append = [group_extamo, group_rollback, group_fault, *csr_groups, custom_csr]\n).print_macros()\n\nrvfi = Group(\n    condition=\"RISCV_FORMAL_BUS\",\n    name=\"RVFI_BUS\",\n    channels=\"`RISCV_FORMAL_NBUS\",\n    nosep=True,\n    signals=[\n        (\"                   1  \", \"bus_valid\"),\n        (\"                   1  \", \"bus_insn \"),\n        (\"                   1  \", \"bus_data \"),\n        (\"                   1  \", \"bus_fault\"),\n        (\"  `RISCV_FORMAL_XLEN  \", \"bus_addr \"),\n        (\"`RISCV_FORMAL_BUSLEN/8\", \"bus_rmask\"),\n        (\"`RISCV_FORMAL_BUSLEN/8\", \"bus_wmask\"),\n        (\"`RISCV_FORMAL_BUSLEN  \", \"bus_rdata\"),\n        (\"`RISCV_FORMAL_BUSLEN  \", \"bus_wdata\"),\n    ],\n).print_macros()\n"
  },
  {
    "path": "checks/rvfi_macros.vh",
    "content": "// Generated by rvfi_macros.py\n\n`ifdef YOSYS\n`define rvformal_rand_reg rand reg\n`define rvformal_rand_const_reg rand const reg\n`else\n`ifdef SIMULATION\n`define rvformal_rand_reg reg\n`define rvformal_rand_const_reg reg\n`else\n`define rvformal_rand_reg wire\n`define rvformal_rand_const_reg reg\n`endif\n`endif\n\n`ifndef RISCV_FORMAL_VALIDADDR\n`define RISCV_FORMAL_VALIDADDR(addr) 1\n`endif\n\n`ifndef RISCV_FORMAL_IOADDR\n`define RISCV_FORMAL_IOADDR(addr) 1\n`endif\n\n`define rvformal_addr_valid(a) (`RISCV_FORMAL_VALIDADDR(a))\n`define rvformal_addr_io(a) (`rvformal_addr_valid(a) && (`RISCV_FORMAL_IOADDR(a)))\n`define rvformal_addr_eq(a, b) ((`rvformal_addr_valid(a) == `rvformal_addr_valid(b)) && (!`rvformal_addr_valid(a) || (a == b)))\n`define rvformal_addr_eq_io(a, b) (`rvformal_addr_io(a) ? `rvformal_addr_io(b) : `rvformal_addr_eq(a, b))\n\n`ifdef RISCV_FORMAL_CSR_FFLAGS\n`define rvformal_csr_fflags_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata;\n`define rvformal_csr_fflags_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata\n`define rvformal_csr_fflags_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata\n`define rvformal_csr_fflags_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata\n`define rvformal_csr_fflags_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fflags_wdata\n`define rvformal_csr_fflags_conn, \\\n  .rvfi_csr_fflags_rmask (rvfi_csr_fflags_rmask), \\\n  .rvfi_csr_fflags_wmask (rvfi_csr_fflags_wmask), \\\n  .rvfi_csr_fflags_rdata (rvfi_csr_fflags_rdata), \\\n  .rvfi_csr_fflags_wdata (rvfi_csr_fflags_wdata)\n`define rvformal_csr_fflags_channel_conn(_idx), \\\n  .rvfi_csr_fflags_rmask (rvfi_csr_fflags_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_fflags_wmask (rvfi_csr_fflags_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_fflags_rdata (rvfi_csr_fflags_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_fflags_wdata (rvfi_csr_fflags_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_fflags_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fflags_rmask = rvfi_csr_fflags_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fflags_wmask = rvfi_csr_fflags_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fflags_rdata = rvfi_csr_fflags_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fflags_wdata = rvfi_csr_fflags_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_fflags_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fflags_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fflags_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fflags_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fflags_wdata)\n`else\n`define rvformal_csr_fflags_wires\n`define rvformal_csr_fflags_outputs\n`define rvformal_csr_fflags_inputs\n`define rvformal_csr_fflags_conn\n`define rvformal_csr_fflags_channel(_idx)\n`endif\n`define rvformal_csr_fflags_indices \\\nlocalparam [11:0] csr_mindex_fflags = 12'hFFF; \\\nlocalparam [11:0] csr_sindex_fflags = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_fflags = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_FRM\n`define rvformal_csr_frm_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata;\n`define rvformal_csr_frm_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata\n`define rvformal_csr_frm_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata\n`define rvformal_csr_frm_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata\n`define rvformal_csr_frm_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_frm_wdata\n`define rvformal_csr_frm_conn, \\\n  .rvfi_csr_frm_rmask (rvfi_csr_frm_rmask), \\\n  .rvfi_csr_frm_wmask (rvfi_csr_frm_wmask), \\\n  .rvfi_csr_frm_rdata (rvfi_csr_frm_rdata), \\\n  .rvfi_csr_frm_wdata (rvfi_csr_frm_wdata)\n`define rvformal_csr_frm_channel_conn(_idx), \\\n  .rvfi_csr_frm_rmask (rvfi_csr_frm_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_frm_wmask (rvfi_csr_frm_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_frm_rdata (rvfi_csr_frm_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_frm_wdata (rvfi_csr_frm_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_frm_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_frm_rmask = rvfi_csr_frm_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_frm_wmask = rvfi_csr_frm_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_frm_rdata = rvfi_csr_frm_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_frm_wdata = rvfi_csr_frm_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_frm_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_frm_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_frm_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_frm_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_frm_wdata)\n`else\n`define rvformal_csr_frm_wires\n`define rvformal_csr_frm_outputs\n`define rvformal_csr_frm_inputs\n`define rvformal_csr_frm_conn\n`define rvformal_csr_frm_channel(_idx)\n`endif\n`define rvformal_csr_frm_indices \\\nlocalparam [11:0] csr_mindex_frm = 12'hFFF; \\\nlocalparam [11:0] csr_sindex_frm = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_frm = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_FCSR\n`define rvformal_csr_fcsr_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata;\n`define rvformal_csr_fcsr_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata\n`define rvformal_csr_fcsr_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata\n`define rvformal_csr_fcsr_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata\n`define rvformal_csr_fcsr_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_fcsr_wdata\n`define rvformal_csr_fcsr_conn, \\\n  .rvfi_csr_fcsr_rmask (rvfi_csr_fcsr_rmask), \\\n  .rvfi_csr_fcsr_wmask (rvfi_csr_fcsr_wmask), \\\n  .rvfi_csr_fcsr_rdata (rvfi_csr_fcsr_rdata), \\\n  .rvfi_csr_fcsr_wdata (rvfi_csr_fcsr_wdata)\n`define rvformal_csr_fcsr_channel_conn(_idx), \\\n  .rvfi_csr_fcsr_rmask (rvfi_csr_fcsr_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_fcsr_wmask (rvfi_csr_fcsr_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_fcsr_rdata (rvfi_csr_fcsr_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_fcsr_wdata (rvfi_csr_fcsr_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_fcsr_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fcsr_rmask = rvfi_csr_fcsr_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fcsr_wmask = rvfi_csr_fcsr_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fcsr_rdata = rvfi_csr_fcsr_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_fcsr_wdata = rvfi_csr_fcsr_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_fcsr_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fcsr_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fcsr_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fcsr_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_fcsr_wdata)\n`else\n`define rvformal_csr_fcsr_wires\n`define rvformal_csr_fcsr_outputs\n`define rvformal_csr_fcsr_inputs\n`define rvformal_csr_fcsr_conn\n`define rvformal_csr_fcsr_channel(_idx)\n`endif\n`define rvformal_csr_fcsr_indices \\\nlocalparam [11:0] csr_mindex_fcsr = 12'hFFF; \\\nlocalparam [11:0] csr_sindex_fcsr = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_fcsr = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MVENDORID\n`define rvformal_csr_mvendorid_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata;\n`define rvformal_csr_mvendorid_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata\n`define rvformal_csr_mvendorid_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata\n`define rvformal_csr_mvendorid_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata\n`define rvformal_csr_mvendorid_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mvendorid_wdata\n`define rvformal_csr_mvendorid_conn, \\\n  .rvfi_csr_mvendorid_rmask (rvfi_csr_mvendorid_rmask), \\\n  .rvfi_csr_mvendorid_wmask (rvfi_csr_mvendorid_wmask), \\\n  .rvfi_csr_mvendorid_rdata (rvfi_csr_mvendorid_rdata), \\\n  .rvfi_csr_mvendorid_wdata (rvfi_csr_mvendorid_wdata)\n`define rvformal_csr_mvendorid_channel_conn(_idx), \\\n  .rvfi_csr_mvendorid_rmask (rvfi_csr_mvendorid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mvendorid_wmask (rvfi_csr_mvendorid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mvendorid_rdata (rvfi_csr_mvendorid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mvendorid_wdata (rvfi_csr_mvendorid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mvendorid_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mvendorid_rmask = rvfi_csr_mvendorid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mvendorid_wmask = rvfi_csr_mvendorid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mvendorid_rdata = rvfi_csr_mvendorid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mvendorid_wdata = rvfi_csr_mvendorid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mvendorid_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mvendorid_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mvendorid_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mvendorid_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mvendorid_wdata)\n`else\n`define rvformal_csr_mvendorid_wires\n`define rvformal_csr_mvendorid_outputs\n`define rvformal_csr_mvendorid_inputs\n`define rvformal_csr_mvendorid_conn\n`define rvformal_csr_mvendorid_channel(_idx)\n`endif\n`define rvformal_csr_mvendorid_indices \\\nlocalparam [11:0] csr_mindex_mvendorid = 12'hF11; \\\nlocalparam [11:0] csr_sindex_mvendorid = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mvendorid = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MARCHID\n`define rvformal_csr_marchid_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata;\n`define rvformal_csr_marchid_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata\n`define rvformal_csr_marchid_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata\n`define rvformal_csr_marchid_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata\n`define rvformal_csr_marchid_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_marchid_wdata\n`define rvformal_csr_marchid_conn, \\\n  .rvfi_csr_marchid_rmask (rvfi_csr_marchid_rmask), \\\n  .rvfi_csr_marchid_wmask (rvfi_csr_marchid_wmask), \\\n  .rvfi_csr_marchid_rdata (rvfi_csr_marchid_rdata), \\\n  .rvfi_csr_marchid_wdata (rvfi_csr_marchid_wdata)\n`define rvformal_csr_marchid_channel_conn(_idx), \\\n  .rvfi_csr_marchid_rmask (rvfi_csr_marchid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_marchid_wmask (rvfi_csr_marchid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_marchid_rdata (rvfi_csr_marchid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_marchid_wdata (rvfi_csr_marchid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_marchid_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_marchid_rmask = rvfi_csr_marchid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_marchid_wmask = rvfi_csr_marchid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_marchid_rdata = rvfi_csr_marchid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_marchid_wdata = rvfi_csr_marchid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_marchid_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_marchid_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_marchid_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_marchid_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_marchid_wdata)\n`else\n`define rvformal_csr_marchid_wires\n`define rvformal_csr_marchid_outputs\n`define rvformal_csr_marchid_inputs\n`define rvformal_csr_marchid_conn\n`define rvformal_csr_marchid_channel(_idx)\n`endif\n`define rvformal_csr_marchid_indices \\\nlocalparam [11:0] csr_mindex_marchid = 12'hF12; \\\nlocalparam [11:0] csr_sindex_marchid = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_marchid = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MIMPID\n`define rvformal_csr_mimpid_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata;\n`define rvformal_csr_mimpid_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata\n`define rvformal_csr_mimpid_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata\n`define rvformal_csr_mimpid_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata\n`define rvformal_csr_mimpid_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mimpid_wdata\n`define rvformal_csr_mimpid_conn, \\\n  .rvfi_csr_mimpid_rmask (rvfi_csr_mimpid_rmask), \\\n  .rvfi_csr_mimpid_wmask (rvfi_csr_mimpid_wmask), \\\n  .rvfi_csr_mimpid_rdata (rvfi_csr_mimpid_rdata), \\\n  .rvfi_csr_mimpid_wdata (rvfi_csr_mimpid_wdata)\n`define rvformal_csr_mimpid_channel_conn(_idx), \\\n  .rvfi_csr_mimpid_rmask (rvfi_csr_mimpid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mimpid_wmask (rvfi_csr_mimpid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mimpid_rdata (rvfi_csr_mimpid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mimpid_wdata (rvfi_csr_mimpid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mimpid_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mimpid_rmask = rvfi_csr_mimpid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mimpid_wmask = rvfi_csr_mimpid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mimpid_rdata = rvfi_csr_mimpid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mimpid_wdata = rvfi_csr_mimpid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mimpid_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mimpid_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mimpid_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mimpid_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mimpid_wdata)\n`else\n`define rvformal_csr_mimpid_wires\n`define rvformal_csr_mimpid_outputs\n`define rvformal_csr_mimpid_inputs\n`define rvformal_csr_mimpid_conn\n`define rvformal_csr_mimpid_channel(_idx)\n`endif\n`define rvformal_csr_mimpid_indices \\\nlocalparam [11:0] csr_mindex_mimpid = 12'hF13; \\\nlocalparam [11:0] csr_sindex_mimpid = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mimpid = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHARTID\n`define rvformal_csr_mhartid_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata;\n`define rvformal_csr_mhartid_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata\n`define rvformal_csr_mhartid_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata\n`define rvformal_csr_mhartid_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata\n`define rvformal_csr_mhartid_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhartid_wdata\n`define rvformal_csr_mhartid_conn, \\\n  .rvfi_csr_mhartid_rmask (rvfi_csr_mhartid_rmask), \\\n  .rvfi_csr_mhartid_wmask (rvfi_csr_mhartid_wmask), \\\n  .rvfi_csr_mhartid_rdata (rvfi_csr_mhartid_rdata), \\\n  .rvfi_csr_mhartid_wdata (rvfi_csr_mhartid_wdata)\n`define rvformal_csr_mhartid_channel_conn(_idx), \\\n  .rvfi_csr_mhartid_rmask (rvfi_csr_mhartid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhartid_wmask (rvfi_csr_mhartid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhartid_rdata (rvfi_csr_mhartid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhartid_wdata (rvfi_csr_mhartid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhartid_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhartid_rmask = rvfi_csr_mhartid_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhartid_wmask = rvfi_csr_mhartid_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhartid_rdata = rvfi_csr_mhartid_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhartid_wdata = rvfi_csr_mhartid_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhartid_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhartid_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhartid_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhartid_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhartid_wdata)\n`else\n`define rvformal_csr_mhartid_wires\n`define rvformal_csr_mhartid_outputs\n`define rvformal_csr_mhartid_inputs\n`define rvformal_csr_mhartid_conn\n`define rvformal_csr_mhartid_channel(_idx)\n`endif\n`define rvformal_csr_mhartid_indices \\\nlocalparam [11:0] csr_mindex_mhartid = 12'hF14; \\\nlocalparam [11:0] csr_sindex_mhartid = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhartid = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MCONFIGPTR\n`define rvformal_csr_mconfigptr_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata;\n`define rvformal_csr_mconfigptr_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata\n`define rvformal_csr_mconfigptr_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata\n`define rvformal_csr_mconfigptr_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata\n`define rvformal_csr_mconfigptr_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mconfigptr_wdata\n`define rvformal_csr_mconfigptr_conn, \\\n  .rvfi_csr_mconfigptr_rmask (rvfi_csr_mconfigptr_rmask), \\\n  .rvfi_csr_mconfigptr_wmask (rvfi_csr_mconfigptr_wmask), \\\n  .rvfi_csr_mconfigptr_rdata (rvfi_csr_mconfigptr_rdata), \\\n  .rvfi_csr_mconfigptr_wdata (rvfi_csr_mconfigptr_wdata)\n`define rvformal_csr_mconfigptr_channel_conn(_idx), \\\n  .rvfi_csr_mconfigptr_rmask (rvfi_csr_mconfigptr_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mconfigptr_wmask (rvfi_csr_mconfigptr_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mconfigptr_rdata (rvfi_csr_mconfigptr_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mconfigptr_wdata (rvfi_csr_mconfigptr_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mconfigptr_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mconfigptr_rmask = rvfi_csr_mconfigptr_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mconfigptr_wmask = rvfi_csr_mconfigptr_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mconfigptr_rdata = rvfi_csr_mconfigptr_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mconfigptr_wdata = rvfi_csr_mconfigptr_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mconfigptr_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mconfigptr_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mconfigptr_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mconfigptr_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mconfigptr_wdata)\n`else\n`define rvformal_csr_mconfigptr_wires\n`define rvformal_csr_mconfigptr_outputs\n`define rvformal_csr_mconfigptr_inputs\n`define rvformal_csr_mconfigptr_conn\n`define rvformal_csr_mconfigptr_channel(_idx)\n`endif\n`define rvformal_csr_mconfigptr_indices \\\nlocalparam [11:0] csr_mindex_mconfigptr = 12'hF15; \\\nlocalparam [11:0] csr_sindex_mconfigptr = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mconfigptr = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MSTATUS\n`define rvformal_csr_mstatus_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata;\n`define rvformal_csr_mstatus_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata\n`define rvformal_csr_mstatus_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata\n`define rvformal_csr_mstatus_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata\n`define rvformal_csr_mstatus_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatus_wdata\n`define rvformal_csr_mstatus_conn, \\\n  .rvfi_csr_mstatus_rmask (rvfi_csr_mstatus_rmask), \\\n  .rvfi_csr_mstatus_wmask (rvfi_csr_mstatus_wmask), \\\n  .rvfi_csr_mstatus_rdata (rvfi_csr_mstatus_rdata), \\\n  .rvfi_csr_mstatus_wdata (rvfi_csr_mstatus_wdata)\n`define rvformal_csr_mstatus_channel_conn(_idx), \\\n  .rvfi_csr_mstatus_rmask (rvfi_csr_mstatus_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mstatus_wmask (rvfi_csr_mstatus_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mstatus_rdata (rvfi_csr_mstatus_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mstatus_wdata (rvfi_csr_mstatus_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mstatus_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatus_rmask = rvfi_csr_mstatus_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatus_wmask = rvfi_csr_mstatus_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatus_rdata = rvfi_csr_mstatus_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatus_wdata = rvfi_csr_mstatus_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mstatus_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatus_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatus_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatus_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatus_wdata)\n`else\n`define rvformal_csr_mstatus_wires\n`define rvformal_csr_mstatus_outputs\n`define rvformal_csr_mstatus_inputs\n`define rvformal_csr_mstatus_conn\n`define rvformal_csr_mstatus_channel(_idx)\n`endif\n`define rvformal_csr_mstatus_indices \\\nlocalparam [11:0] csr_mindex_mstatus = 12'h300; \\\nlocalparam [11:0] csr_sindex_mstatus = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mstatus = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MSTATUSH\n`define rvformal_csr_mstatush_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata;\n`define rvformal_csr_mstatush_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata\n`define rvformal_csr_mstatush_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata\n`define rvformal_csr_mstatush_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata\n`define rvformal_csr_mstatush_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mstatush_wdata\n`define rvformal_csr_mstatush_conn, \\\n  .rvfi_csr_mstatush_rmask (rvfi_csr_mstatush_rmask), \\\n  .rvfi_csr_mstatush_wmask (rvfi_csr_mstatush_wmask), \\\n  .rvfi_csr_mstatush_rdata (rvfi_csr_mstatush_rdata), \\\n  .rvfi_csr_mstatush_wdata (rvfi_csr_mstatush_wdata)\n`define rvformal_csr_mstatush_channel_conn(_idx), \\\n  .rvfi_csr_mstatush_rmask (rvfi_csr_mstatush_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mstatush_wmask (rvfi_csr_mstatush_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mstatush_rdata (rvfi_csr_mstatush_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mstatush_wdata (rvfi_csr_mstatush_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mstatush_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatush_rmask = rvfi_csr_mstatush_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatush_wmask = rvfi_csr_mstatush_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatush_rdata = rvfi_csr_mstatush_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mstatush_wdata = rvfi_csr_mstatush_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mstatush_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatush_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatush_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatush_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mstatush_wdata)\n`else\n`define rvformal_csr_mstatush_wires\n`define rvformal_csr_mstatush_outputs\n`define rvformal_csr_mstatush_inputs\n`define rvformal_csr_mstatush_conn\n`define rvformal_csr_mstatush_channel(_idx)\n`endif\n`define rvformal_csr_mstatush_indices \\\nlocalparam [11:0] csr_mindex_mstatush = 12'h310; \\\nlocalparam [11:0] csr_sindex_mstatush = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mstatush = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MISA\n`define rvformal_csr_misa_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata;\n`define rvformal_csr_misa_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata\n`define rvformal_csr_misa_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata\n`define rvformal_csr_misa_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata\n`define rvformal_csr_misa_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_wdata\n`define rvformal_csr_misa_conn, \\\n  .rvfi_csr_misa_rmask (rvfi_csr_misa_rmask), \\\n  .rvfi_csr_misa_wmask (rvfi_csr_misa_wmask), \\\n  .rvfi_csr_misa_rdata (rvfi_csr_misa_rdata), \\\n  .rvfi_csr_misa_wdata (rvfi_csr_misa_wdata)\n`define rvformal_csr_misa_channel_conn(_idx), \\\n  .rvfi_csr_misa_rmask (rvfi_csr_misa_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_misa_wmask (rvfi_csr_misa_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_misa_rdata (rvfi_csr_misa_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_misa_wdata (rvfi_csr_misa_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_misa_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_rmask = rvfi_csr_misa_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_wmask = rvfi_csr_misa_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_rdata = rvfi_csr_misa_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_misa_wdata = rvfi_csr_misa_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_misa_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_misa_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_misa_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_misa_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_misa_wdata)\n`else\n`define rvformal_csr_misa_wires\n`define rvformal_csr_misa_outputs\n`define rvformal_csr_misa_inputs\n`define rvformal_csr_misa_conn\n`define rvformal_csr_misa_channel(_idx)\n`endif\n`define rvformal_csr_misa_indices \\\nlocalparam [11:0] csr_mindex_misa = 12'h301; \\\nlocalparam [11:0] csr_sindex_misa = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_misa = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MEDELEG\n`define rvformal_csr_medeleg_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata;\n`define rvformal_csr_medeleg_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata\n`define rvformal_csr_medeleg_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata\n`define rvformal_csr_medeleg_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata\n`define rvformal_csr_medeleg_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_medeleg_wdata\n`define rvformal_csr_medeleg_conn, \\\n  .rvfi_csr_medeleg_rmask (rvfi_csr_medeleg_rmask), \\\n  .rvfi_csr_medeleg_wmask (rvfi_csr_medeleg_wmask), \\\n  .rvfi_csr_medeleg_rdata (rvfi_csr_medeleg_rdata), \\\n  .rvfi_csr_medeleg_wdata (rvfi_csr_medeleg_wdata)\n`define rvformal_csr_medeleg_channel_conn(_idx), \\\n  .rvfi_csr_medeleg_rmask (rvfi_csr_medeleg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_medeleg_wmask (rvfi_csr_medeleg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_medeleg_rdata (rvfi_csr_medeleg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_medeleg_wdata (rvfi_csr_medeleg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_medeleg_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_medeleg_rmask = rvfi_csr_medeleg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_medeleg_wmask = rvfi_csr_medeleg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_medeleg_rdata = rvfi_csr_medeleg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_medeleg_wdata = rvfi_csr_medeleg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_medeleg_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_medeleg_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_medeleg_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_medeleg_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_medeleg_wdata)\n`else\n`define rvformal_csr_medeleg_wires\n`define rvformal_csr_medeleg_outputs\n`define rvformal_csr_medeleg_inputs\n`define rvformal_csr_medeleg_conn\n`define rvformal_csr_medeleg_channel(_idx)\n`endif\n`define rvformal_csr_medeleg_indices \\\nlocalparam [11:0] csr_mindex_medeleg = 12'h302; \\\nlocalparam [11:0] csr_sindex_medeleg = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_medeleg = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MIDELEG\n`define rvformal_csr_mideleg_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata;\n`define rvformal_csr_mideleg_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata\n`define rvformal_csr_mideleg_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata\n`define rvformal_csr_mideleg_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata\n`define rvformal_csr_mideleg_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mideleg_wdata\n`define rvformal_csr_mideleg_conn, \\\n  .rvfi_csr_mideleg_rmask (rvfi_csr_mideleg_rmask), \\\n  .rvfi_csr_mideleg_wmask (rvfi_csr_mideleg_wmask), \\\n  .rvfi_csr_mideleg_rdata (rvfi_csr_mideleg_rdata), \\\n  .rvfi_csr_mideleg_wdata (rvfi_csr_mideleg_wdata)\n`define rvformal_csr_mideleg_channel_conn(_idx), \\\n  .rvfi_csr_mideleg_rmask (rvfi_csr_mideleg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mideleg_wmask (rvfi_csr_mideleg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mideleg_rdata (rvfi_csr_mideleg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mideleg_wdata (rvfi_csr_mideleg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mideleg_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mideleg_rmask = rvfi_csr_mideleg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mideleg_wmask = rvfi_csr_mideleg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mideleg_rdata = rvfi_csr_mideleg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mideleg_wdata = rvfi_csr_mideleg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mideleg_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mideleg_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mideleg_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mideleg_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mideleg_wdata)\n`else\n`define rvformal_csr_mideleg_wires\n`define rvformal_csr_mideleg_outputs\n`define rvformal_csr_mideleg_inputs\n`define rvformal_csr_mideleg_conn\n`define rvformal_csr_mideleg_channel(_idx)\n`endif\n`define rvformal_csr_mideleg_indices \\\nlocalparam [11:0] csr_mindex_mideleg = 12'h303; \\\nlocalparam [11:0] csr_sindex_mideleg = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mideleg = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MIE\n`define rvformal_csr_mie_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata;\n`define rvformal_csr_mie_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata\n`define rvformal_csr_mie_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata\n`define rvformal_csr_mie_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata\n`define rvformal_csr_mie_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mie_wdata\n`define rvformal_csr_mie_conn, \\\n  .rvfi_csr_mie_rmask (rvfi_csr_mie_rmask), \\\n  .rvfi_csr_mie_wmask (rvfi_csr_mie_wmask), \\\n  .rvfi_csr_mie_rdata (rvfi_csr_mie_rdata), \\\n  .rvfi_csr_mie_wdata (rvfi_csr_mie_wdata)\n`define rvformal_csr_mie_channel_conn(_idx), \\\n  .rvfi_csr_mie_rmask (rvfi_csr_mie_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mie_wmask (rvfi_csr_mie_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mie_rdata (rvfi_csr_mie_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mie_wdata (rvfi_csr_mie_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mie_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mie_rmask = rvfi_csr_mie_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mie_wmask = rvfi_csr_mie_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mie_rdata = rvfi_csr_mie_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mie_wdata = rvfi_csr_mie_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mie_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mie_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mie_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mie_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mie_wdata)\n`else\n`define rvformal_csr_mie_wires\n`define rvformal_csr_mie_outputs\n`define rvformal_csr_mie_inputs\n`define rvformal_csr_mie_conn\n`define rvformal_csr_mie_channel(_idx)\n`endif\n`define rvformal_csr_mie_indices \\\nlocalparam [11:0] csr_mindex_mie = 12'h304; \\\nlocalparam [11:0] csr_sindex_mie = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mie = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MTVEC\n`define rvformal_csr_mtvec_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata;\n`define rvformal_csr_mtvec_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata\n`define rvformal_csr_mtvec_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata\n`define rvformal_csr_mtvec_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata\n`define rvformal_csr_mtvec_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtvec_wdata\n`define rvformal_csr_mtvec_conn, \\\n  .rvfi_csr_mtvec_rmask (rvfi_csr_mtvec_rmask), \\\n  .rvfi_csr_mtvec_wmask (rvfi_csr_mtvec_wmask), \\\n  .rvfi_csr_mtvec_rdata (rvfi_csr_mtvec_rdata), \\\n  .rvfi_csr_mtvec_wdata (rvfi_csr_mtvec_wdata)\n`define rvformal_csr_mtvec_channel_conn(_idx), \\\n  .rvfi_csr_mtvec_rmask (rvfi_csr_mtvec_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtvec_wmask (rvfi_csr_mtvec_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtvec_rdata (rvfi_csr_mtvec_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtvec_wdata (rvfi_csr_mtvec_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mtvec_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtvec_rmask = rvfi_csr_mtvec_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtvec_wmask = rvfi_csr_mtvec_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtvec_rdata = rvfi_csr_mtvec_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtvec_wdata = rvfi_csr_mtvec_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mtvec_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtvec_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtvec_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtvec_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtvec_wdata)\n`else\n`define rvformal_csr_mtvec_wires\n`define rvformal_csr_mtvec_outputs\n`define rvformal_csr_mtvec_inputs\n`define rvformal_csr_mtvec_conn\n`define rvformal_csr_mtvec_channel(_idx)\n`endif\n`define rvformal_csr_mtvec_indices \\\nlocalparam [11:0] csr_mindex_mtvec = 12'h305; \\\nlocalparam [11:0] csr_sindex_mtvec = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mtvec = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MCOUNTEREN\n`define rvformal_csr_mcounteren_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata;\n`define rvformal_csr_mcounteren_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata\n`define rvformal_csr_mcounteren_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata\n`define rvformal_csr_mcounteren_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata\n`define rvformal_csr_mcounteren_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcounteren_wdata\n`define rvformal_csr_mcounteren_conn, \\\n  .rvfi_csr_mcounteren_rmask (rvfi_csr_mcounteren_rmask), \\\n  .rvfi_csr_mcounteren_wmask (rvfi_csr_mcounteren_wmask), \\\n  .rvfi_csr_mcounteren_rdata (rvfi_csr_mcounteren_rdata), \\\n  .rvfi_csr_mcounteren_wdata (rvfi_csr_mcounteren_wdata)\n`define rvformal_csr_mcounteren_channel_conn(_idx), \\\n  .rvfi_csr_mcounteren_rmask (rvfi_csr_mcounteren_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mcounteren_wmask (rvfi_csr_mcounteren_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mcounteren_rdata (rvfi_csr_mcounteren_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mcounteren_wdata (rvfi_csr_mcounteren_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mcounteren_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcounteren_rmask = rvfi_csr_mcounteren_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcounteren_wmask = rvfi_csr_mcounteren_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcounteren_rdata = rvfi_csr_mcounteren_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcounteren_wdata = rvfi_csr_mcounteren_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mcounteren_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcounteren_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcounteren_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcounteren_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcounteren_wdata)\n`else\n`define rvformal_csr_mcounteren_wires\n`define rvformal_csr_mcounteren_outputs\n`define rvformal_csr_mcounteren_inputs\n`define rvformal_csr_mcounteren_conn\n`define rvformal_csr_mcounteren_channel(_idx)\n`endif\n`define rvformal_csr_mcounteren_indices \\\nlocalparam [11:0] csr_mindex_mcounteren = 12'h306; \\\nlocalparam [11:0] csr_sindex_mcounteren = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mcounteren = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MSCRATCH\n`define rvformal_csr_mscratch_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata;\n`define rvformal_csr_mscratch_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata\n`define rvformal_csr_mscratch_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata\n`define rvformal_csr_mscratch_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata\n`define rvformal_csr_mscratch_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mscratch_wdata\n`define rvformal_csr_mscratch_conn, \\\n  .rvfi_csr_mscratch_rmask (rvfi_csr_mscratch_rmask), \\\n  .rvfi_csr_mscratch_wmask (rvfi_csr_mscratch_wmask), \\\n  .rvfi_csr_mscratch_rdata (rvfi_csr_mscratch_rdata), \\\n  .rvfi_csr_mscratch_wdata (rvfi_csr_mscratch_wdata)\n`define rvformal_csr_mscratch_channel_conn(_idx), \\\n  .rvfi_csr_mscratch_rmask (rvfi_csr_mscratch_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mscratch_wmask (rvfi_csr_mscratch_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mscratch_rdata (rvfi_csr_mscratch_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mscratch_wdata (rvfi_csr_mscratch_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mscratch_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mscratch_rmask = rvfi_csr_mscratch_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mscratch_wmask = rvfi_csr_mscratch_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mscratch_rdata = rvfi_csr_mscratch_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mscratch_wdata = rvfi_csr_mscratch_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mscratch_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mscratch_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mscratch_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mscratch_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mscratch_wdata)\n`else\n`define rvformal_csr_mscratch_wires\n`define rvformal_csr_mscratch_outputs\n`define rvformal_csr_mscratch_inputs\n`define rvformal_csr_mscratch_conn\n`define rvformal_csr_mscratch_channel(_idx)\n`endif\n`define rvformal_csr_mscratch_indices \\\nlocalparam [11:0] csr_mindex_mscratch = 12'h340; \\\nlocalparam [11:0] csr_sindex_mscratch = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mscratch = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MEPC\n`define rvformal_csr_mepc_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata;\n`define rvformal_csr_mepc_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata\n`define rvformal_csr_mepc_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata\n`define rvformal_csr_mepc_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata\n`define rvformal_csr_mepc_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mepc_wdata\n`define rvformal_csr_mepc_conn, \\\n  .rvfi_csr_mepc_rmask (rvfi_csr_mepc_rmask), \\\n  .rvfi_csr_mepc_wmask (rvfi_csr_mepc_wmask), \\\n  .rvfi_csr_mepc_rdata (rvfi_csr_mepc_rdata), \\\n  .rvfi_csr_mepc_wdata (rvfi_csr_mepc_wdata)\n`define rvformal_csr_mepc_channel_conn(_idx), \\\n  .rvfi_csr_mepc_rmask (rvfi_csr_mepc_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mepc_wmask (rvfi_csr_mepc_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mepc_rdata (rvfi_csr_mepc_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mepc_wdata (rvfi_csr_mepc_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mepc_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mepc_rmask = rvfi_csr_mepc_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mepc_wmask = rvfi_csr_mepc_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mepc_rdata = rvfi_csr_mepc_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mepc_wdata = rvfi_csr_mepc_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mepc_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mepc_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mepc_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mepc_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mepc_wdata)\n`else\n`define rvformal_csr_mepc_wires\n`define rvformal_csr_mepc_outputs\n`define rvformal_csr_mepc_inputs\n`define rvformal_csr_mepc_conn\n`define rvformal_csr_mepc_channel(_idx)\n`endif\n`define rvformal_csr_mepc_indices \\\nlocalparam [11:0] csr_mindex_mepc = 12'h341; \\\nlocalparam [11:0] csr_sindex_mepc = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mepc = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MCAUSE\n`define rvformal_csr_mcause_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata;\n`define rvformal_csr_mcause_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata\n`define rvformal_csr_mcause_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata\n`define rvformal_csr_mcause_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata\n`define rvformal_csr_mcause_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcause_wdata\n`define rvformal_csr_mcause_conn, \\\n  .rvfi_csr_mcause_rmask (rvfi_csr_mcause_rmask), \\\n  .rvfi_csr_mcause_wmask (rvfi_csr_mcause_wmask), \\\n  .rvfi_csr_mcause_rdata (rvfi_csr_mcause_rdata), \\\n  .rvfi_csr_mcause_wdata (rvfi_csr_mcause_wdata)\n`define rvformal_csr_mcause_channel_conn(_idx), \\\n  .rvfi_csr_mcause_rmask (rvfi_csr_mcause_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mcause_wmask (rvfi_csr_mcause_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mcause_rdata (rvfi_csr_mcause_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mcause_wdata (rvfi_csr_mcause_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mcause_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcause_rmask = rvfi_csr_mcause_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcause_wmask = rvfi_csr_mcause_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcause_rdata = rvfi_csr_mcause_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcause_wdata = rvfi_csr_mcause_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mcause_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcause_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcause_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcause_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcause_wdata)\n`else\n`define rvformal_csr_mcause_wires\n`define rvformal_csr_mcause_outputs\n`define rvformal_csr_mcause_inputs\n`define rvformal_csr_mcause_conn\n`define rvformal_csr_mcause_channel(_idx)\n`endif\n`define rvformal_csr_mcause_indices \\\nlocalparam [11:0] csr_mindex_mcause = 12'h342; \\\nlocalparam [11:0] csr_sindex_mcause = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mcause = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MTVAL\n`define rvformal_csr_mtval_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata;\n`define rvformal_csr_mtval_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata\n`define rvformal_csr_mtval_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata\n`define rvformal_csr_mtval_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata\n`define rvformal_csr_mtval_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval_wdata\n`define rvformal_csr_mtval_conn, \\\n  .rvfi_csr_mtval_rmask (rvfi_csr_mtval_rmask), \\\n  .rvfi_csr_mtval_wmask (rvfi_csr_mtval_wmask), \\\n  .rvfi_csr_mtval_rdata (rvfi_csr_mtval_rdata), \\\n  .rvfi_csr_mtval_wdata (rvfi_csr_mtval_wdata)\n`define rvformal_csr_mtval_channel_conn(_idx), \\\n  .rvfi_csr_mtval_rmask (rvfi_csr_mtval_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtval_wmask (rvfi_csr_mtval_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtval_rdata (rvfi_csr_mtval_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtval_wdata (rvfi_csr_mtval_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mtval_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval_rmask = rvfi_csr_mtval_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval_wmask = rvfi_csr_mtval_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval_rdata = rvfi_csr_mtval_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval_wdata = rvfi_csr_mtval_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mtval_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval_wdata)\n`else\n`define rvformal_csr_mtval_wires\n`define rvformal_csr_mtval_outputs\n`define rvformal_csr_mtval_inputs\n`define rvformal_csr_mtval_conn\n`define rvformal_csr_mtval_channel(_idx)\n`endif\n`define rvformal_csr_mtval_indices \\\nlocalparam [11:0] csr_mindex_mtval = 12'h343; \\\nlocalparam [11:0] csr_sindex_mtval = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mtval = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MIP\n`define rvformal_csr_mip_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata;\n`define rvformal_csr_mip_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata\n`define rvformal_csr_mip_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata\n`define rvformal_csr_mip_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata\n`define rvformal_csr_mip_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mip_wdata\n`define rvformal_csr_mip_conn, \\\n  .rvfi_csr_mip_rmask (rvfi_csr_mip_rmask), \\\n  .rvfi_csr_mip_wmask (rvfi_csr_mip_wmask), \\\n  .rvfi_csr_mip_rdata (rvfi_csr_mip_rdata), \\\n  .rvfi_csr_mip_wdata (rvfi_csr_mip_wdata)\n`define rvformal_csr_mip_channel_conn(_idx), \\\n  .rvfi_csr_mip_rmask (rvfi_csr_mip_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mip_wmask (rvfi_csr_mip_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mip_rdata (rvfi_csr_mip_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mip_wdata (rvfi_csr_mip_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mip_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mip_rmask = rvfi_csr_mip_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mip_wmask = rvfi_csr_mip_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mip_rdata = rvfi_csr_mip_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mip_wdata = rvfi_csr_mip_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mip_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mip_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mip_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mip_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mip_wdata)\n`else\n`define rvformal_csr_mip_wires\n`define rvformal_csr_mip_outputs\n`define rvformal_csr_mip_inputs\n`define rvformal_csr_mip_conn\n`define rvformal_csr_mip_channel(_idx)\n`endif\n`define rvformal_csr_mip_indices \\\nlocalparam [11:0] csr_mindex_mip = 12'h344; \\\nlocalparam [11:0] csr_sindex_mip = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mip = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MTINST\n`define rvformal_csr_mtinst_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata;\n`define rvformal_csr_mtinst_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata\n`define rvformal_csr_mtinst_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata\n`define rvformal_csr_mtinst_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata\n`define rvformal_csr_mtinst_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtinst_wdata\n`define rvformal_csr_mtinst_conn, \\\n  .rvfi_csr_mtinst_rmask (rvfi_csr_mtinst_rmask), \\\n  .rvfi_csr_mtinst_wmask (rvfi_csr_mtinst_wmask), \\\n  .rvfi_csr_mtinst_rdata (rvfi_csr_mtinst_rdata), \\\n  .rvfi_csr_mtinst_wdata (rvfi_csr_mtinst_wdata)\n`define rvformal_csr_mtinst_channel_conn(_idx), \\\n  .rvfi_csr_mtinst_rmask (rvfi_csr_mtinst_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtinst_wmask (rvfi_csr_mtinst_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtinst_rdata (rvfi_csr_mtinst_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtinst_wdata (rvfi_csr_mtinst_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mtinst_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtinst_rmask = rvfi_csr_mtinst_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtinst_wmask = rvfi_csr_mtinst_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtinst_rdata = rvfi_csr_mtinst_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtinst_wdata = rvfi_csr_mtinst_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mtinst_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtinst_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtinst_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtinst_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtinst_wdata)\n`else\n`define rvformal_csr_mtinst_wires\n`define rvformal_csr_mtinst_outputs\n`define rvformal_csr_mtinst_inputs\n`define rvformal_csr_mtinst_conn\n`define rvformal_csr_mtinst_channel(_idx)\n`endif\n`define rvformal_csr_mtinst_indices \\\nlocalparam [11:0] csr_mindex_mtinst = 12'h34A; \\\nlocalparam [11:0] csr_sindex_mtinst = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mtinst = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MTVAL2\n`define rvformal_csr_mtval2_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata;\n`define rvformal_csr_mtval2_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata\n`define rvformal_csr_mtval2_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata\n`define rvformal_csr_mtval2_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata\n`define rvformal_csr_mtval2_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mtval2_wdata\n`define rvformal_csr_mtval2_conn, \\\n  .rvfi_csr_mtval2_rmask (rvfi_csr_mtval2_rmask), \\\n  .rvfi_csr_mtval2_wmask (rvfi_csr_mtval2_wmask), \\\n  .rvfi_csr_mtval2_rdata (rvfi_csr_mtval2_rdata), \\\n  .rvfi_csr_mtval2_wdata (rvfi_csr_mtval2_wdata)\n`define rvformal_csr_mtval2_channel_conn(_idx), \\\n  .rvfi_csr_mtval2_rmask (rvfi_csr_mtval2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtval2_wmask (rvfi_csr_mtval2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtval2_rdata (rvfi_csr_mtval2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mtval2_wdata (rvfi_csr_mtval2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mtval2_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval2_rmask = rvfi_csr_mtval2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval2_wmask = rvfi_csr_mtval2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval2_rdata = rvfi_csr_mtval2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mtval2_wdata = rvfi_csr_mtval2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mtval2_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval2_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval2_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval2_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mtval2_wdata)\n`else\n`define rvformal_csr_mtval2_wires\n`define rvformal_csr_mtval2_outputs\n`define rvformal_csr_mtval2_inputs\n`define rvformal_csr_mtval2_conn\n`define rvformal_csr_mtval2_channel(_idx)\n`endif\n`define rvformal_csr_mtval2_indices \\\nlocalparam [11:0] csr_mindex_mtval2 = 12'h34B; \\\nlocalparam [11:0] csr_sindex_mtval2 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mtval2 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MCOUNTINHIBIT\n`define rvformal_csr_mcountinhibit_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata;\n`define rvformal_csr_mcountinhibit_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata\n`define rvformal_csr_mcountinhibit_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata\n`define rvformal_csr_mcountinhibit_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata\n`define rvformal_csr_mcountinhibit_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mcountinhibit_wdata\n`define rvformal_csr_mcountinhibit_conn, \\\n  .rvfi_csr_mcountinhibit_rmask (rvfi_csr_mcountinhibit_rmask), \\\n  .rvfi_csr_mcountinhibit_wmask (rvfi_csr_mcountinhibit_wmask), \\\n  .rvfi_csr_mcountinhibit_rdata (rvfi_csr_mcountinhibit_rdata), \\\n  .rvfi_csr_mcountinhibit_wdata (rvfi_csr_mcountinhibit_wdata)\n`define rvformal_csr_mcountinhibit_channel_conn(_idx), \\\n  .rvfi_csr_mcountinhibit_rmask (rvfi_csr_mcountinhibit_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mcountinhibit_wmask (rvfi_csr_mcountinhibit_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mcountinhibit_rdata (rvfi_csr_mcountinhibit_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mcountinhibit_wdata (rvfi_csr_mcountinhibit_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mcountinhibit_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcountinhibit_rmask = rvfi_csr_mcountinhibit_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcountinhibit_wmask = rvfi_csr_mcountinhibit_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcountinhibit_rdata = rvfi_csr_mcountinhibit_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mcountinhibit_wdata = rvfi_csr_mcountinhibit_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mcountinhibit_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcountinhibit_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcountinhibit_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcountinhibit_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mcountinhibit_wdata)\n`else\n`define rvformal_csr_mcountinhibit_wires\n`define rvformal_csr_mcountinhibit_outputs\n`define rvformal_csr_mcountinhibit_inputs\n`define rvformal_csr_mcountinhibit_conn\n`define rvformal_csr_mcountinhibit_channel(_idx)\n`endif\n`define rvformal_csr_mcountinhibit_indices \\\nlocalparam [11:0] csr_mindex_mcountinhibit = 12'h320; \\\nlocalparam [11:0] csr_sindex_mcountinhibit = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mcountinhibit = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MENVCFG\n`define rvformal_csr_menvcfg_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata;\n`define rvformal_csr_menvcfg_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata\n`define rvformal_csr_menvcfg_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata\n`define rvformal_csr_menvcfg_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata\n`define rvformal_csr_menvcfg_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfg_wdata\n`define rvformal_csr_menvcfg_conn, \\\n  .rvfi_csr_menvcfg_rmask (rvfi_csr_menvcfg_rmask), \\\n  .rvfi_csr_menvcfg_wmask (rvfi_csr_menvcfg_wmask), \\\n  .rvfi_csr_menvcfg_rdata (rvfi_csr_menvcfg_rdata), \\\n  .rvfi_csr_menvcfg_wdata (rvfi_csr_menvcfg_wdata)\n`define rvformal_csr_menvcfg_channel_conn(_idx), \\\n  .rvfi_csr_menvcfg_rmask (rvfi_csr_menvcfg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_menvcfg_wmask (rvfi_csr_menvcfg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_menvcfg_rdata (rvfi_csr_menvcfg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_menvcfg_wdata (rvfi_csr_menvcfg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_menvcfg_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfg_rmask = rvfi_csr_menvcfg_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfg_wmask = rvfi_csr_menvcfg_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfg_rdata = rvfi_csr_menvcfg_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfg_wdata = rvfi_csr_menvcfg_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_menvcfg_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfg_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfg_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfg_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfg_wdata)\n`else\n`define rvformal_csr_menvcfg_wires\n`define rvformal_csr_menvcfg_outputs\n`define rvformal_csr_menvcfg_inputs\n`define rvformal_csr_menvcfg_conn\n`define rvformal_csr_menvcfg_channel(_idx)\n`endif\n`define rvformal_csr_menvcfg_indices \\\nlocalparam [11:0] csr_mindex_menvcfg = 12'h30A; \\\nlocalparam [11:0] csr_sindex_menvcfg = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_menvcfg = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MENVCFGH\n`define rvformal_csr_menvcfgh_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata;\n`define rvformal_csr_menvcfgh_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata\n`define rvformal_csr_menvcfgh_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata\n`define rvformal_csr_menvcfgh_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata\n`define rvformal_csr_menvcfgh_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_menvcfgh_wdata\n`define rvformal_csr_menvcfgh_conn, \\\n  .rvfi_csr_menvcfgh_rmask (rvfi_csr_menvcfgh_rmask), \\\n  .rvfi_csr_menvcfgh_wmask (rvfi_csr_menvcfgh_wmask), \\\n  .rvfi_csr_menvcfgh_rdata (rvfi_csr_menvcfgh_rdata), \\\n  .rvfi_csr_menvcfgh_wdata (rvfi_csr_menvcfgh_wdata)\n`define rvformal_csr_menvcfgh_channel_conn(_idx), \\\n  .rvfi_csr_menvcfgh_rmask (rvfi_csr_menvcfgh_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_menvcfgh_wmask (rvfi_csr_menvcfgh_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_menvcfgh_rdata (rvfi_csr_menvcfgh_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_menvcfgh_wdata (rvfi_csr_menvcfgh_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_menvcfgh_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfgh_rmask = rvfi_csr_menvcfgh_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfgh_wmask = rvfi_csr_menvcfgh_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfgh_rdata = rvfi_csr_menvcfgh_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_menvcfgh_wdata = rvfi_csr_menvcfgh_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_menvcfgh_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfgh_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfgh_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfgh_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_menvcfgh_wdata)\n`else\n`define rvformal_csr_menvcfgh_wires\n`define rvformal_csr_menvcfgh_outputs\n`define rvformal_csr_menvcfgh_inputs\n`define rvformal_csr_menvcfgh_conn\n`define rvformal_csr_menvcfgh_channel(_idx)\n`endif\n`define rvformal_csr_menvcfgh_indices \\\nlocalparam [11:0] csr_mindex_menvcfgh = 12'h31A; \\\nlocalparam [11:0] csr_sindex_menvcfgh = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_menvcfgh = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG0\n`define rvformal_csr_pmpcfg0_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata;\n`define rvformal_csr_pmpcfg0_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata\n`define rvformal_csr_pmpcfg0_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata\n`define rvformal_csr_pmpcfg0_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata\n`define rvformal_csr_pmpcfg0_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg0_wdata\n`define rvformal_csr_pmpcfg0_conn, \\\n  .rvfi_csr_pmpcfg0_rmask (rvfi_csr_pmpcfg0_rmask), \\\n  .rvfi_csr_pmpcfg0_wmask (rvfi_csr_pmpcfg0_wmask), \\\n  .rvfi_csr_pmpcfg0_rdata (rvfi_csr_pmpcfg0_rdata), \\\n  .rvfi_csr_pmpcfg0_wdata (rvfi_csr_pmpcfg0_wdata)\n`define rvformal_csr_pmpcfg0_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg0_rmask (rvfi_csr_pmpcfg0_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg0_wmask (rvfi_csr_pmpcfg0_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg0_rdata (rvfi_csr_pmpcfg0_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg0_wdata (rvfi_csr_pmpcfg0_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg0_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg0_rmask = rvfi_csr_pmpcfg0_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg0_wmask = rvfi_csr_pmpcfg0_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg0_rdata = rvfi_csr_pmpcfg0_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg0_wdata = rvfi_csr_pmpcfg0_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg0_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg0_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg0_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg0_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg0_wdata)\n`else\n`define rvformal_csr_pmpcfg0_wires\n`define rvformal_csr_pmpcfg0_outputs\n`define rvformal_csr_pmpcfg0_inputs\n`define rvformal_csr_pmpcfg0_conn\n`define rvformal_csr_pmpcfg0_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg0_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg0 = 12'h3A0; \\\nlocalparam [11:0] csr_sindex_pmpcfg0 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg0 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG1\n`define rvformal_csr_pmpcfg1_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata;\n`define rvformal_csr_pmpcfg1_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata\n`define rvformal_csr_pmpcfg1_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata\n`define rvformal_csr_pmpcfg1_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata\n`define rvformal_csr_pmpcfg1_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg1_wdata\n`define rvformal_csr_pmpcfg1_conn, \\\n  .rvfi_csr_pmpcfg1_rmask (rvfi_csr_pmpcfg1_rmask), \\\n  .rvfi_csr_pmpcfg1_wmask (rvfi_csr_pmpcfg1_wmask), \\\n  .rvfi_csr_pmpcfg1_rdata (rvfi_csr_pmpcfg1_rdata), \\\n  .rvfi_csr_pmpcfg1_wdata (rvfi_csr_pmpcfg1_wdata)\n`define rvformal_csr_pmpcfg1_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg1_rmask (rvfi_csr_pmpcfg1_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg1_wmask (rvfi_csr_pmpcfg1_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg1_rdata (rvfi_csr_pmpcfg1_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg1_wdata (rvfi_csr_pmpcfg1_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg1_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg1_rmask = rvfi_csr_pmpcfg1_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg1_wmask = rvfi_csr_pmpcfg1_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg1_rdata = rvfi_csr_pmpcfg1_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg1_wdata = rvfi_csr_pmpcfg1_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg1_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg1_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg1_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg1_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg1_wdata)\n`else\n`define rvformal_csr_pmpcfg1_wires\n`define rvformal_csr_pmpcfg1_outputs\n`define rvformal_csr_pmpcfg1_inputs\n`define rvformal_csr_pmpcfg1_conn\n`define rvformal_csr_pmpcfg1_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg1_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg1 = 12'h3A1; \\\nlocalparam [11:0] csr_sindex_pmpcfg1 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg1 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG2\n`define rvformal_csr_pmpcfg2_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata;\n`define rvformal_csr_pmpcfg2_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata\n`define rvformal_csr_pmpcfg2_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata\n`define rvformal_csr_pmpcfg2_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata\n`define rvformal_csr_pmpcfg2_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg2_wdata\n`define rvformal_csr_pmpcfg2_conn, \\\n  .rvfi_csr_pmpcfg2_rmask (rvfi_csr_pmpcfg2_rmask), \\\n  .rvfi_csr_pmpcfg2_wmask (rvfi_csr_pmpcfg2_wmask), \\\n  .rvfi_csr_pmpcfg2_rdata (rvfi_csr_pmpcfg2_rdata), \\\n  .rvfi_csr_pmpcfg2_wdata (rvfi_csr_pmpcfg2_wdata)\n`define rvformal_csr_pmpcfg2_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg2_rmask (rvfi_csr_pmpcfg2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg2_wmask (rvfi_csr_pmpcfg2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg2_rdata (rvfi_csr_pmpcfg2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg2_wdata (rvfi_csr_pmpcfg2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg2_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg2_rmask = rvfi_csr_pmpcfg2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg2_wmask = rvfi_csr_pmpcfg2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg2_rdata = rvfi_csr_pmpcfg2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg2_wdata = rvfi_csr_pmpcfg2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg2_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg2_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg2_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg2_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg2_wdata)\n`else\n`define rvformal_csr_pmpcfg2_wires\n`define rvformal_csr_pmpcfg2_outputs\n`define rvformal_csr_pmpcfg2_inputs\n`define rvformal_csr_pmpcfg2_conn\n`define rvformal_csr_pmpcfg2_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg2_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg2 = 12'h3A2; \\\nlocalparam [11:0] csr_sindex_pmpcfg2 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg2 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG3\n`define rvformal_csr_pmpcfg3_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata;\n`define rvformal_csr_pmpcfg3_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata\n`define rvformal_csr_pmpcfg3_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata\n`define rvformal_csr_pmpcfg3_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata\n`define rvformal_csr_pmpcfg3_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg3_wdata\n`define rvformal_csr_pmpcfg3_conn, \\\n  .rvfi_csr_pmpcfg3_rmask (rvfi_csr_pmpcfg3_rmask), \\\n  .rvfi_csr_pmpcfg3_wmask (rvfi_csr_pmpcfg3_wmask), \\\n  .rvfi_csr_pmpcfg3_rdata (rvfi_csr_pmpcfg3_rdata), \\\n  .rvfi_csr_pmpcfg3_wdata (rvfi_csr_pmpcfg3_wdata)\n`define rvformal_csr_pmpcfg3_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg3_rmask (rvfi_csr_pmpcfg3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg3_wmask (rvfi_csr_pmpcfg3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg3_rdata (rvfi_csr_pmpcfg3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg3_wdata (rvfi_csr_pmpcfg3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg3_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg3_rmask = rvfi_csr_pmpcfg3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg3_wmask = rvfi_csr_pmpcfg3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg3_rdata = rvfi_csr_pmpcfg3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg3_wdata = rvfi_csr_pmpcfg3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg3_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg3_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg3_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg3_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg3_wdata)\n`else\n`define rvformal_csr_pmpcfg3_wires\n`define rvformal_csr_pmpcfg3_outputs\n`define rvformal_csr_pmpcfg3_inputs\n`define rvformal_csr_pmpcfg3_conn\n`define rvformal_csr_pmpcfg3_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg3_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg3 = 12'h3A3; \\\nlocalparam [11:0] csr_sindex_pmpcfg3 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg3 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG4\n`define rvformal_csr_pmpcfg4_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata;\n`define rvformal_csr_pmpcfg4_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata\n`define rvformal_csr_pmpcfg4_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata\n`define rvformal_csr_pmpcfg4_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata\n`define rvformal_csr_pmpcfg4_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg4_wdata\n`define rvformal_csr_pmpcfg4_conn, \\\n  .rvfi_csr_pmpcfg4_rmask (rvfi_csr_pmpcfg4_rmask), \\\n  .rvfi_csr_pmpcfg4_wmask (rvfi_csr_pmpcfg4_wmask), \\\n  .rvfi_csr_pmpcfg4_rdata (rvfi_csr_pmpcfg4_rdata), \\\n  .rvfi_csr_pmpcfg4_wdata (rvfi_csr_pmpcfg4_wdata)\n`define rvformal_csr_pmpcfg4_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg4_rmask (rvfi_csr_pmpcfg4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg4_wmask (rvfi_csr_pmpcfg4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg4_rdata (rvfi_csr_pmpcfg4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg4_wdata (rvfi_csr_pmpcfg4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg4_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg4_rmask = rvfi_csr_pmpcfg4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg4_wmask = rvfi_csr_pmpcfg4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg4_rdata = rvfi_csr_pmpcfg4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg4_wdata = rvfi_csr_pmpcfg4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg4_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg4_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg4_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg4_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg4_wdata)\n`else\n`define rvformal_csr_pmpcfg4_wires\n`define rvformal_csr_pmpcfg4_outputs\n`define rvformal_csr_pmpcfg4_inputs\n`define rvformal_csr_pmpcfg4_conn\n`define rvformal_csr_pmpcfg4_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg4_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg4 = 12'h3A4; \\\nlocalparam [11:0] csr_sindex_pmpcfg4 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg4 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG5\n`define rvformal_csr_pmpcfg5_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata;\n`define rvformal_csr_pmpcfg5_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata\n`define rvformal_csr_pmpcfg5_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata\n`define rvformal_csr_pmpcfg5_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata\n`define rvformal_csr_pmpcfg5_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg5_wdata\n`define rvformal_csr_pmpcfg5_conn, \\\n  .rvfi_csr_pmpcfg5_rmask (rvfi_csr_pmpcfg5_rmask), \\\n  .rvfi_csr_pmpcfg5_wmask (rvfi_csr_pmpcfg5_wmask), \\\n  .rvfi_csr_pmpcfg5_rdata (rvfi_csr_pmpcfg5_rdata), \\\n  .rvfi_csr_pmpcfg5_wdata (rvfi_csr_pmpcfg5_wdata)\n`define rvformal_csr_pmpcfg5_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg5_rmask (rvfi_csr_pmpcfg5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg5_wmask (rvfi_csr_pmpcfg5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg5_rdata (rvfi_csr_pmpcfg5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg5_wdata (rvfi_csr_pmpcfg5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg5_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg5_rmask = rvfi_csr_pmpcfg5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg5_wmask = rvfi_csr_pmpcfg5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg5_rdata = rvfi_csr_pmpcfg5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg5_wdata = rvfi_csr_pmpcfg5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg5_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg5_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg5_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg5_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg5_wdata)\n`else\n`define rvformal_csr_pmpcfg5_wires\n`define rvformal_csr_pmpcfg5_outputs\n`define rvformal_csr_pmpcfg5_inputs\n`define rvformal_csr_pmpcfg5_conn\n`define rvformal_csr_pmpcfg5_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg5_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg5 = 12'h3A5; \\\nlocalparam [11:0] csr_sindex_pmpcfg5 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg5 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG6\n`define rvformal_csr_pmpcfg6_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata;\n`define rvformal_csr_pmpcfg6_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata\n`define rvformal_csr_pmpcfg6_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata\n`define rvformal_csr_pmpcfg6_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata\n`define rvformal_csr_pmpcfg6_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg6_wdata\n`define rvformal_csr_pmpcfg6_conn, \\\n  .rvfi_csr_pmpcfg6_rmask (rvfi_csr_pmpcfg6_rmask), \\\n  .rvfi_csr_pmpcfg6_wmask (rvfi_csr_pmpcfg6_wmask), \\\n  .rvfi_csr_pmpcfg6_rdata (rvfi_csr_pmpcfg6_rdata), \\\n  .rvfi_csr_pmpcfg6_wdata (rvfi_csr_pmpcfg6_wdata)\n`define rvformal_csr_pmpcfg6_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg6_rmask (rvfi_csr_pmpcfg6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg6_wmask (rvfi_csr_pmpcfg6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg6_rdata (rvfi_csr_pmpcfg6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg6_wdata (rvfi_csr_pmpcfg6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg6_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg6_rmask = rvfi_csr_pmpcfg6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg6_wmask = rvfi_csr_pmpcfg6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg6_rdata = rvfi_csr_pmpcfg6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg6_wdata = rvfi_csr_pmpcfg6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg6_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg6_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg6_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg6_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg6_wdata)\n`else\n`define rvformal_csr_pmpcfg6_wires\n`define rvformal_csr_pmpcfg6_outputs\n`define rvformal_csr_pmpcfg6_inputs\n`define rvformal_csr_pmpcfg6_conn\n`define rvformal_csr_pmpcfg6_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg6_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg6 = 12'h3A6; \\\nlocalparam [11:0] csr_sindex_pmpcfg6 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg6 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG7\n`define rvformal_csr_pmpcfg7_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata;\n`define rvformal_csr_pmpcfg7_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata\n`define rvformal_csr_pmpcfg7_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata\n`define rvformal_csr_pmpcfg7_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata\n`define rvformal_csr_pmpcfg7_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg7_wdata\n`define rvformal_csr_pmpcfg7_conn, \\\n  .rvfi_csr_pmpcfg7_rmask (rvfi_csr_pmpcfg7_rmask), \\\n  .rvfi_csr_pmpcfg7_wmask (rvfi_csr_pmpcfg7_wmask), \\\n  .rvfi_csr_pmpcfg7_rdata (rvfi_csr_pmpcfg7_rdata), \\\n  .rvfi_csr_pmpcfg7_wdata (rvfi_csr_pmpcfg7_wdata)\n`define rvformal_csr_pmpcfg7_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg7_rmask (rvfi_csr_pmpcfg7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg7_wmask (rvfi_csr_pmpcfg7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg7_rdata (rvfi_csr_pmpcfg7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg7_wdata (rvfi_csr_pmpcfg7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg7_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg7_rmask = rvfi_csr_pmpcfg7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg7_wmask = rvfi_csr_pmpcfg7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg7_rdata = rvfi_csr_pmpcfg7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg7_wdata = rvfi_csr_pmpcfg7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg7_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg7_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg7_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg7_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg7_wdata)\n`else\n`define rvformal_csr_pmpcfg7_wires\n`define rvformal_csr_pmpcfg7_outputs\n`define rvformal_csr_pmpcfg7_inputs\n`define rvformal_csr_pmpcfg7_conn\n`define rvformal_csr_pmpcfg7_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg7_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg7 = 12'h3A7; \\\nlocalparam [11:0] csr_sindex_pmpcfg7 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg7 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG8\n`define rvformal_csr_pmpcfg8_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata;\n`define rvformal_csr_pmpcfg8_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata\n`define rvformal_csr_pmpcfg8_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata\n`define rvformal_csr_pmpcfg8_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata\n`define rvformal_csr_pmpcfg8_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg8_wdata\n`define rvformal_csr_pmpcfg8_conn, \\\n  .rvfi_csr_pmpcfg8_rmask (rvfi_csr_pmpcfg8_rmask), \\\n  .rvfi_csr_pmpcfg8_wmask (rvfi_csr_pmpcfg8_wmask), \\\n  .rvfi_csr_pmpcfg8_rdata (rvfi_csr_pmpcfg8_rdata), \\\n  .rvfi_csr_pmpcfg8_wdata (rvfi_csr_pmpcfg8_wdata)\n`define rvformal_csr_pmpcfg8_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg8_rmask (rvfi_csr_pmpcfg8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg8_wmask (rvfi_csr_pmpcfg8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg8_rdata (rvfi_csr_pmpcfg8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg8_wdata (rvfi_csr_pmpcfg8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg8_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg8_rmask = rvfi_csr_pmpcfg8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg8_wmask = rvfi_csr_pmpcfg8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg8_rdata = rvfi_csr_pmpcfg8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg8_wdata = rvfi_csr_pmpcfg8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg8_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg8_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg8_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg8_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg8_wdata)\n`else\n`define rvformal_csr_pmpcfg8_wires\n`define rvformal_csr_pmpcfg8_outputs\n`define rvformal_csr_pmpcfg8_inputs\n`define rvformal_csr_pmpcfg8_conn\n`define rvformal_csr_pmpcfg8_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg8_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg8 = 12'h3A8; \\\nlocalparam [11:0] csr_sindex_pmpcfg8 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg8 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG9\n`define rvformal_csr_pmpcfg9_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata;\n`define rvformal_csr_pmpcfg9_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata\n`define rvformal_csr_pmpcfg9_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata\n`define rvformal_csr_pmpcfg9_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata\n`define rvformal_csr_pmpcfg9_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg9_wdata\n`define rvformal_csr_pmpcfg9_conn, \\\n  .rvfi_csr_pmpcfg9_rmask (rvfi_csr_pmpcfg9_rmask), \\\n  .rvfi_csr_pmpcfg9_wmask (rvfi_csr_pmpcfg9_wmask), \\\n  .rvfi_csr_pmpcfg9_rdata (rvfi_csr_pmpcfg9_rdata), \\\n  .rvfi_csr_pmpcfg9_wdata (rvfi_csr_pmpcfg9_wdata)\n`define rvformal_csr_pmpcfg9_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg9_rmask (rvfi_csr_pmpcfg9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg9_wmask (rvfi_csr_pmpcfg9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg9_rdata (rvfi_csr_pmpcfg9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg9_wdata (rvfi_csr_pmpcfg9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg9_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg9_rmask = rvfi_csr_pmpcfg9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg9_wmask = rvfi_csr_pmpcfg9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg9_rdata = rvfi_csr_pmpcfg9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg9_wdata = rvfi_csr_pmpcfg9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg9_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg9_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg9_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg9_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg9_wdata)\n`else\n`define rvformal_csr_pmpcfg9_wires\n`define rvformal_csr_pmpcfg9_outputs\n`define rvformal_csr_pmpcfg9_inputs\n`define rvformal_csr_pmpcfg9_conn\n`define rvformal_csr_pmpcfg9_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg9_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg9 = 12'h3A9; \\\nlocalparam [11:0] csr_sindex_pmpcfg9 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg9 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG10\n`define rvformal_csr_pmpcfg10_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata;\n`define rvformal_csr_pmpcfg10_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata\n`define rvformal_csr_pmpcfg10_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata\n`define rvformal_csr_pmpcfg10_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata\n`define rvformal_csr_pmpcfg10_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg10_wdata\n`define rvformal_csr_pmpcfg10_conn, \\\n  .rvfi_csr_pmpcfg10_rmask (rvfi_csr_pmpcfg10_rmask), \\\n  .rvfi_csr_pmpcfg10_wmask (rvfi_csr_pmpcfg10_wmask), \\\n  .rvfi_csr_pmpcfg10_rdata (rvfi_csr_pmpcfg10_rdata), \\\n  .rvfi_csr_pmpcfg10_wdata (rvfi_csr_pmpcfg10_wdata)\n`define rvformal_csr_pmpcfg10_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg10_rmask (rvfi_csr_pmpcfg10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg10_wmask (rvfi_csr_pmpcfg10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg10_rdata (rvfi_csr_pmpcfg10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg10_wdata (rvfi_csr_pmpcfg10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg10_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg10_rmask = rvfi_csr_pmpcfg10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg10_wmask = rvfi_csr_pmpcfg10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg10_rdata = rvfi_csr_pmpcfg10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg10_wdata = rvfi_csr_pmpcfg10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg10_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg10_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg10_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg10_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg10_wdata)\n`else\n`define rvformal_csr_pmpcfg10_wires\n`define rvformal_csr_pmpcfg10_outputs\n`define rvformal_csr_pmpcfg10_inputs\n`define rvformal_csr_pmpcfg10_conn\n`define rvformal_csr_pmpcfg10_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg10_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg10 = 12'h3AA; \\\nlocalparam [11:0] csr_sindex_pmpcfg10 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg10 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG11\n`define rvformal_csr_pmpcfg11_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata;\n`define rvformal_csr_pmpcfg11_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata\n`define rvformal_csr_pmpcfg11_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata\n`define rvformal_csr_pmpcfg11_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata\n`define rvformal_csr_pmpcfg11_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg11_wdata\n`define rvformal_csr_pmpcfg11_conn, \\\n  .rvfi_csr_pmpcfg11_rmask (rvfi_csr_pmpcfg11_rmask), \\\n  .rvfi_csr_pmpcfg11_wmask (rvfi_csr_pmpcfg11_wmask), \\\n  .rvfi_csr_pmpcfg11_rdata (rvfi_csr_pmpcfg11_rdata), \\\n  .rvfi_csr_pmpcfg11_wdata (rvfi_csr_pmpcfg11_wdata)\n`define rvformal_csr_pmpcfg11_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg11_rmask (rvfi_csr_pmpcfg11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg11_wmask (rvfi_csr_pmpcfg11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg11_rdata (rvfi_csr_pmpcfg11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg11_wdata (rvfi_csr_pmpcfg11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg11_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg11_rmask = rvfi_csr_pmpcfg11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg11_wmask = rvfi_csr_pmpcfg11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg11_rdata = rvfi_csr_pmpcfg11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg11_wdata = rvfi_csr_pmpcfg11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg11_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg11_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg11_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg11_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg11_wdata)\n`else\n`define rvformal_csr_pmpcfg11_wires\n`define rvformal_csr_pmpcfg11_outputs\n`define rvformal_csr_pmpcfg11_inputs\n`define rvformal_csr_pmpcfg11_conn\n`define rvformal_csr_pmpcfg11_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg11_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg11 = 12'h3AB; \\\nlocalparam [11:0] csr_sindex_pmpcfg11 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg11 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG12\n`define rvformal_csr_pmpcfg12_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata;\n`define rvformal_csr_pmpcfg12_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata\n`define rvformal_csr_pmpcfg12_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata\n`define rvformal_csr_pmpcfg12_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata\n`define rvformal_csr_pmpcfg12_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg12_wdata\n`define rvformal_csr_pmpcfg12_conn, \\\n  .rvfi_csr_pmpcfg12_rmask (rvfi_csr_pmpcfg12_rmask), \\\n  .rvfi_csr_pmpcfg12_wmask (rvfi_csr_pmpcfg12_wmask), \\\n  .rvfi_csr_pmpcfg12_rdata (rvfi_csr_pmpcfg12_rdata), \\\n  .rvfi_csr_pmpcfg12_wdata (rvfi_csr_pmpcfg12_wdata)\n`define rvformal_csr_pmpcfg12_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg12_rmask (rvfi_csr_pmpcfg12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg12_wmask (rvfi_csr_pmpcfg12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg12_rdata (rvfi_csr_pmpcfg12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg12_wdata (rvfi_csr_pmpcfg12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg12_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg12_rmask = rvfi_csr_pmpcfg12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg12_wmask = rvfi_csr_pmpcfg12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg12_rdata = rvfi_csr_pmpcfg12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg12_wdata = rvfi_csr_pmpcfg12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg12_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg12_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg12_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg12_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg12_wdata)\n`else\n`define rvformal_csr_pmpcfg12_wires\n`define rvformal_csr_pmpcfg12_outputs\n`define rvformal_csr_pmpcfg12_inputs\n`define rvformal_csr_pmpcfg12_conn\n`define rvformal_csr_pmpcfg12_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg12_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg12 = 12'h3AC; \\\nlocalparam [11:0] csr_sindex_pmpcfg12 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg12 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG13\n`define rvformal_csr_pmpcfg13_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata;\n`define rvformal_csr_pmpcfg13_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata\n`define rvformal_csr_pmpcfg13_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata\n`define rvformal_csr_pmpcfg13_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata\n`define rvformal_csr_pmpcfg13_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg13_wdata\n`define rvformal_csr_pmpcfg13_conn, \\\n  .rvfi_csr_pmpcfg13_rmask (rvfi_csr_pmpcfg13_rmask), \\\n  .rvfi_csr_pmpcfg13_wmask (rvfi_csr_pmpcfg13_wmask), \\\n  .rvfi_csr_pmpcfg13_rdata (rvfi_csr_pmpcfg13_rdata), \\\n  .rvfi_csr_pmpcfg13_wdata (rvfi_csr_pmpcfg13_wdata)\n`define rvformal_csr_pmpcfg13_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg13_rmask (rvfi_csr_pmpcfg13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg13_wmask (rvfi_csr_pmpcfg13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg13_rdata (rvfi_csr_pmpcfg13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg13_wdata (rvfi_csr_pmpcfg13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg13_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg13_rmask = rvfi_csr_pmpcfg13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg13_wmask = rvfi_csr_pmpcfg13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg13_rdata = rvfi_csr_pmpcfg13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg13_wdata = rvfi_csr_pmpcfg13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg13_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg13_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg13_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg13_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg13_wdata)\n`else\n`define rvformal_csr_pmpcfg13_wires\n`define rvformal_csr_pmpcfg13_outputs\n`define rvformal_csr_pmpcfg13_inputs\n`define rvformal_csr_pmpcfg13_conn\n`define rvformal_csr_pmpcfg13_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg13_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg13 = 12'h3AD; \\\nlocalparam [11:0] csr_sindex_pmpcfg13 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg13 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG14\n`define rvformal_csr_pmpcfg14_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata;\n`define rvformal_csr_pmpcfg14_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata\n`define rvformal_csr_pmpcfg14_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata\n`define rvformal_csr_pmpcfg14_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata\n`define rvformal_csr_pmpcfg14_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg14_wdata\n`define rvformal_csr_pmpcfg14_conn, \\\n  .rvfi_csr_pmpcfg14_rmask (rvfi_csr_pmpcfg14_rmask), \\\n  .rvfi_csr_pmpcfg14_wmask (rvfi_csr_pmpcfg14_wmask), \\\n  .rvfi_csr_pmpcfg14_rdata (rvfi_csr_pmpcfg14_rdata), \\\n  .rvfi_csr_pmpcfg14_wdata (rvfi_csr_pmpcfg14_wdata)\n`define rvformal_csr_pmpcfg14_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg14_rmask (rvfi_csr_pmpcfg14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg14_wmask (rvfi_csr_pmpcfg14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg14_rdata (rvfi_csr_pmpcfg14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg14_wdata (rvfi_csr_pmpcfg14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg14_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg14_rmask = rvfi_csr_pmpcfg14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg14_wmask = rvfi_csr_pmpcfg14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg14_rdata = rvfi_csr_pmpcfg14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg14_wdata = rvfi_csr_pmpcfg14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg14_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg14_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg14_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg14_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg14_wdata)\n`else\n`define rvformal_csr_pmpcfg14_wires\n`define rvformal_csr_pmpcfg14_outputs\n`define rvformal_csr_pmpcfg14_inputs\n`define rvformal_csr_pmpcfg14_conn\n`define rvformal_csr_pmpcfg14_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg14_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg14 = 12'h3AE; \\\nlocalparam [11:0] csr_sindex_pmpcfg14 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg14 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPCFG15\n`define rvformal_csr_pmpcfg15_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata;\n`define rvformal_csr_pmpcfg15_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata\n`define rvformal_csr_pmpcfg15_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata\n`define rvformal_csr_pmpcfg15_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata\n`define rvformal_csr_pmpcfg15_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpcfg15_wdata\n`define rvformal_csr_pmpcfg15_conn, \\\n  .rvfi_csr_pmpcfg15_rmask (rvfi_csr_pmpcfg15_rmask), \\\n  .rvfi_csr_pmpcfg15_wmask (rvfi_csr_pmpcfg15_wmask), \\\n  .rvfi_csr_pmpcfg15_rdata (rvfi_csr_pmpcfg15_rdata), \\\n  .rvfi_csr_pmpcfg15_wdata (rvfi_csr_pmpcfg15_wdata)\n`define rvformal_csr_pmpcfg15_channel_conn(_idx), \\\n  .rvfi_csr_pmpcfg15_rmask (rvfi_csr_pmpcfg15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg15_wmask (rvfi_csr_pmpcfg15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg15_rdata (rvfi_csr_pmpcfg15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpcfg15_wdata (rvfi_csr_pmpcfg15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpcfg15_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg15_rmask = rvfi_csr_pmpcfg15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg15_wmask = rvfi_csr_pmpcfg15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg15_rdata = rvfi_csr_pmpcfg15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpcfg15_wdata = rvfi_csr_pmpcfg15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpcfg15_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg15_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg15_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg15_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpcfg15_wdata)\n`else\n`define rvformal_csr_pmpcfg15_wires\n`define rvformal_csr_pmpcfg15_outputs\n`define rvformal_csr_pmpcfg15_inputs\n`define rvformal_csr_pmpcfg15_conn\n`define rvformal_csr_pmpcfg15_channel(_idx)\n`endif\n`define rvformal_csr_pmpcfg15_indices \\\nlocalparam [11:0] csr_mindex_pmpcfg15 = 12'h3AF; \\\nlocalparam [11:0] csr_sindex_pmpcfg15 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpcfg15 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR0\n`define rvformal_csr_pmpaddr0_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata;\n`define rvformal_csr_pmpaddr0_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata\n`define rvformal_csr_pmpaddr0_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata\n`define rvformal_csr_pmpaddr0_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata\n`define rvformal_csr_pmpaddr0_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr0_wdata\n`define rvformal_csr_pmpaddr0_conn, \\\n  .rvfi_csr_pmpaddr0_rmask (rvfi_csr_pmpaddr0_rmask), \\\n  .rvfi_csr_pmpaddr0_wmask (rvfi_csr_pmpaddr0_wmask), \\\n  .rvfi_csr_pmpaddr0_rdata (rvfi_csr_pmpaddr0_rdata), \\\n  .rvfi_csr_pmpaddr0_wdata (rvfi_csr_pmpaddr0_wdata)\n`define rvformal_csr_pmpaddr0_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr0_rmask (rvfi_csr_pmpaddr0_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr0_wmask (rvfi_csr_pmpaddr0_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr0_rdata (rvfi_csr_pmpaddr0_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr0_wdata (rvfi_csr_pmpaddr0_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr0_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr0_rmask = rvfi_csr_pmpaddr0_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr0_wmask = rvfi_csr_pmpaddr0_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr0_rdata = rvfi_csr_pmpaddr0_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr0_wdata = rvfi_csr_pmpaddr0_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr0_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr0_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr0_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr0_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr0_wdata)\n`else\n`define rvformal_csr_pmpaddr0_wires\n`define rvformal_csr_pmpaddr0_outputs\n`define rvformal_csr_pmpaddr0_inputs\n`define rvformal_csr_pmpaddr0_conn\n`define rvformal_csr_pmpaddr0_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr0_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr0 = 12'h3B0; \\\nlocalparam [11:0] csr_sindex_pmpaddr0 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr0 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR1\n`define rvformal_csr_pmpaddr1_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata;\n`define rvformal_csr_pmpaddr1_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata\n`define rvformal_csr_pmpaddr1_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata\n`define rvformal_csr_pmpaddr1_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata\n`define rvformal_csr_pmpaddr1_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr1_wdata\n`define rvformal_csr_pmpaddr1_conn, \\\n  .rvfi_csr_pmpaddr1_rmask (rvfi_csr_pmpaddr1_rmask), \\\n  .rvfi_csr_pmpaddr1_wmask (rvfi_csr_pmpaddr1_wmask), \\\n  .rvfi_csr_pmpaddr1_rdata (rvfi_csr_pmpaddr1_rdata), \\\n  .rvfi_csr_pmpaddr1_wdata (rvfi_csr_pmpaddr1_wdata)\n`define rvformal_csr_pmpaddr1_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr1_rmask (rvfi_csr_pmpaddr1_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr1_wmask (rvfi_csr_pmpaddr1_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr1_rdata (rvfi_csr_pmpaddr1_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr1_wdata (rvfi_csr_pmpaddr1_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr1_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr1_rmask = rvfi_csr_pmpaddr1_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr1_wmask = rvfi_csr_pmpaddr1_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr1_rdata = rvfi_csr_pmpaddr1_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr1_wdata = rvfi_csr_pmpaddr1_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr1_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr1_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr1_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr1_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr1_wdata)\n`else\n`define rvformal_csr_pmpaddr1_wires\n`define rvformal_csr_pmpaddr1_outputs\n`define rvformal_csr_pmpaddr1_inputs\n`define rvformal_csr_pmpaddr1_conn\n`define rvformal_csr_pmpaddr1_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr1_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr1 = 12'h3B1; \\\nlocalparam [11:0] csr_sindex_pmpaddr1 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr1 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR2\n`define rvformal_csr_pmpaddr2_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata;\n`define rvformal_csr_pmpaddr2_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata\n`define rvformal_csr_pmpaddr2_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata\n`define rvformal_csr_pmpaddr2_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata\n`define rvformal_csr_pmpaddr2_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr2_wdata\n`define rvformal_csr_pmpaddr2_conn, \\\n  .rvfi_csr_pmpaddr2_rmask (rvfi_csr_pmpaddr2_rmask), \\\n  .rvfi_csr_pmpaddr2_wmask (rvfi_csr_pmpaddr2_wmask), \\\n  .rvfi_csr_pmpaddr2_rdata (rvfi_csr_pmpaddr2_rdata), \\\n  .rvfi_csr_pmpaddr2_wdata (rvfi_csr_pmpaddr2_wdata)\n`define rvformal_csr_pmpaddr2_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr2_rmask (rvfi_csr_pmpaddr2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr2_wmask (rvfi_csr_pmpaddr2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr2_rdata (rvfi_csr_pmpaddr2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr2_wdata (rvfi_csr_pmpaddr2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr2_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr2_rmask = rvfi_csr_pmpaddr2_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr2_wmask = rvfi_csr_pmpaddr2_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr2_rdata = rvfi_csr_pmpaddr2_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr2_wdata = rvfi_csr_pmpaddr2_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr2_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr2_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr2_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr2_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr2_wdata)\n`else\n`define rvformal_csr_pmpaddr2_wires\n`define rvformal_csr_pmpaddr2_outputs\n`define rvformal_csr_pmpaddr2_inputs\n`define rvformal_csr_pmpaddr2_conn\n`define rvformal_csr_pmpaddr2_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr2_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr2 = 12'h3B2; \\\nlocalparam [11:0] csr_sindex_pmpaddr2 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr2 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR3\n`define rvformal_csr_pmpaddr3_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata;\n`define rvformal_csr_pmpaddr3_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata\n`define rvformal_csr_pmpaddr3_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata\n`define rvformal_csr_pmpaddr3_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata\n`define rvformal_csr_pmpaddr3_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr3_wdata\n`define rvformal_csr_pmpaddr3_conn, \\\n  .rvfi_csr_pmpaddr3_rmask (rvfi_csr_pmpaddr3_rmask), \\\n  .rvfi_csr_pmpaddr3_wmask (rvfi_csr_pmpaddr3_wmask), \\\n  .rvfi_csr_pmpaddr3_rdata (rvfi_csr_pmpaddr3_rdata), \\\n  .rvfi_csr_pmpaddr3_wdata (rvfi_csr_pmpaddr3_wdata)\n`define rvformal_csr_pmpaddr3_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr3_rmask (rvfi_csr_pmpaddr3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr3_wmask (rvfi_csr_pmpaddr3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr3_rdata (rvfi_csr_pmpaddr3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr3_wdata (rvfi_csr_pmpaddr3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr3_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr3_rmask = rvfi_csr_pmpaddr3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr3_wmask = rvfi_csr_pmpaddr3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr3_rdata = rvfi_csr_pmpaddr3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr3_wdata = rvfi_csr_pmpaddr3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr3_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr3_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr3_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr3_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr3_wdata)\n`else\n`define rvformal_csr_pmpaddr3_wires\n`define rvformal_csr_pmpaddr3_outputs\n`define rvformal_csr_pmpaddr3_inputs\n`define rvformal_csr_pmpaddr3_conn\n`define rvformal_csr_pmpaddr3_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr3_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr3 = 12'h3B3; \\\nlocalparam [11:0] csr_sindex_pmpaddr3 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr3 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR4\n`define rvformal_csr_pmpaddr4_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata;\n`define rvformal_csr_pmpaddr4_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata\n`define rvformal_csr_pmpaddr4_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata\n`define rvformal_csr_pmpaddr4_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata\n`define rvformal_csr_pmpaddr4_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr4_wdata\n`define rvformal_csr_pmpaddr4_conn, \\\n  .rvfi_csr_pmpaddr4_rmask (rvfi_csr_pmpaddr4_rmask), \\\n  .rvfi_csr_pmpaddr4_wmask (rvfi_csr_pmpaddr4_wmask), \\\n  .rvfi_csr_pmpaddr4_rdata (rvfi_csr_pmpaddr4_rdata), \\\n  .rvfi_csr_pmpaddr4_wdata (rvfi_csr_pmpaddr4_wdata)\n`define rvformal_csr_pmpaddr4_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr4_rmask (rvfi_csr_pmpaddr4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr4_wmask (rvfi_csr_pmpaddr4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr4_rdata (rvfi_csr_pmpaddr4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr4_wdata (rvfi_csr_pmpaddr4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr4_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr4_rmask = rvfi_csr_pmpaddr4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr4_wmask = rvfi_csr_pmpaddr4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr4_rdata = rvfi_csr_pmpaddr4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr4_wdata = rvfi_csr_pmpaddr4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr4_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr4_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr4_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr4_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr4_wdata)\n`else\n`define rvformal_csr_pmpaddr4_wires\n`define rvformal_csr_pmpaddr4_outputs\n`define rvformal_csr_pmpaddr4_inputs\n`define rvformal_csr_pmpaddr4_conn\n`define rvformal_csr_pmpaddr4_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr4_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr4 = 12'h3B4; \\\nlocalparam [11:0] csr_sindex_pmpaddr4 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr4 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR5\n`define rvformal_csr_pmpaddr5_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata;\n`define rvformal_csr_pmpaddr5_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata\n`define rvformal_csr_pmpaddr5_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata\n`define rvformal_csr_pmpaddr5_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata\n`define rvformal_csr_pmpaddr5_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr5_wdata\n`define rvformal_csr_pmpaddr5_conn, \\\n  .rvfi_csr_pmpaddr5_rmask (rvfi_csr_pmpaddr5_rmask), \\\n  .rvfi_csr_pmpaddr5_wmask (rvfi_csr_pmpaddr5_wmask), \\\n  .rvfi_csr_pmpaddr5_rdata (rvfi_csr_pmpaddr5_rdata), \\\n  .rvfi_csr_pmpaddr5_wdata (rvfi_csr_pmpaddr5_wdata)\n`define rvformal_csr_pmpaddr5_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr5_rmask (rvfi_csr_pmpaddr5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr5_wmask (rvfi_csr_pmpaddr5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr5_rdata (rvfi_csr_pmpaddr5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr5_wdata (rvfi_csr_pmpaddr5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr5_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr5_rmask = rvfi_csr_pmpaddr5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr5_wmask = rvfi_csr_pmpaddr5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr5_rdata = rvfi_csr_pmpaddr5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr5_wdata = rvfi_csr_pmpaddr5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr5_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr5_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr5_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr5_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr5_wdata)\n`else\n`define rvformal_csr_pmpaddr5_wires\n`define rvformal_csr_pmpaddr5_outputs\n`define rvformal_csr_pmpaddr5_inputs\n`define rvformal_csr_pmpaddr5_conn\n`define rvformal_csr_pmpaddr5_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr5_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr5 = 12'h3B5; \\\nlocalparam [11:0] csr_sindex_pmpaddr5 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr5 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR6\n`define rvformal_csr_pmpaddr6_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata;\n`define rvformal_csr_pmpaddr6_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata\n`define rvformal_csr_pmpaddr6_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata\n`define rvformal_csr_pmpaddr6_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata\n`define rvformal_csr_pmpaddr6_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr6_wdata\n`define rvformal_csr_pmpaddr6_conn, \\\n  .rvfi_csr_pmpaddr6_rmask (rvfi_csr_pmpaddr6_rmask), \\\n  .rvfi_csr_pmpaddr6_wmask (rvfi_csr_pmpaddr6_wmask), \\\n  .rvfi_csr_pmpaddr6_rdata (rvfi_csr_pmpaddr6_rdata), \\\n  .rvfi_csr_pmpaddr6_wdata (rvfi_csr_pmpaddr6_wdata)\n`define rvformal_csr_pmpaddr6_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr6_rmask (rvfi_csr_pmpaddr6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr6_wmask (rvfi_csr_pmpaddr6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr6_rdata (rvfi_csr_pmpaddr6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr6_wdata (rvfi_csr_pmpaddr6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr6_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr6_rmask = rvfi_csr_pmpaddr6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr6_wmask = rvfi_csr_pmpaddr6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr6_rdata = rvfi_csr_pmpaddr6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr6_wdata = rvfi_csr_pmpaddr6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr6_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr6_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr6_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr6_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr6_wdata)\n`else\n`define rvformal_csr_pmpaddr6_wires\n`define rvformal_csr_pmpaddr6_outputs\n`define rvformal_csr_pmpaddr6_inputs\n`define rvformal_csr_pmpaddr6_conn\n`define rvformal_csr_pmpaddr6_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr6_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr6 = 12'h3B6; \\\nlocalparam [11:0] csr_sindex_pmpaddr6 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr6 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR7\n`define rvformal_csr_pmpaddr7_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata;\n`define rvformal_csr_pmpaddr7_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata\n`define rvformal_csr_pmpaddr7_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata\n`define rvformal_csr_pmpaddr7_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata\n`define rvformal_csr_pmpaddr7_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr7_wdata\n`define rvformal_csr_pmpaddr7_conn, \\\n  .rvfi_csr_pmpaddr7_rmask (rvfi_csr_pmpaddr7_rmask), \\\n  .rvfi_csr_pmpaddr7_wmask (rvfi_csr_pmpaddr7_wmask), \\\n  .rvfi_csr_pmpaddr7_rdata (rvfi_csr_pmpaddr7_rdata), \\\n  .rvfi_csr_pmpaddr7_wdata (rvfi_csr_pmpaddr7_wdata)\n`define rvformal_csr_pmpaddr7_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr7_rmask (rvfi_csr_pmpaddr7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr7_wmask (rvfi_csr_pmpaddr7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr7_rdata (rvfi_csr_pmpaddr7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr7_wdata (rvfi_csr_pmpaddr7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr7_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr7_rmask = rvfi_csr_pmpaddr7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr7_wmask = rvfi_csr_pmpaddr7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr7_rdata = rvfi_csr_pmpaddr7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr7_wdata = rvfi_csr_pmpaddr7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr7_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr7_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr7_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr7_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr7_wdata)\n`else\n`define rvformal_csr_pmpaddr7_wires\n`define rvformal_csr_pmpaddr7_outputs\n`define rvformal_csr_pmpaddr7_inputs\n`define rvformal_csr_pmpaddr7_conn\n`define rvformal_csr_pmpaddr7_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr7_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr7 = 12'h3B7; \\\nlocalparam [11:0] csr_sindex_pmpaddr7 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr7 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR8\n`define rvformal_csr_pmpaddr8_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata;\n`define rvformal_csr_pmpaddr8_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata\n`define rvformal_csr_pmpaddr8_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata\n`define rvformal_csr_pmpaddr8_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata\n`define rvformal_csr_pmpaddr8_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr8_wdata\n`define rvformal_csr_pmpaddr8_conn, \\\n  .rvfi_csr_pmpaddr8_rmask (rvfi_csr_pmpaddr8_rmask), \\\n  .rvfi_csr_pmpaddr8_wmask (rvfi_csr_pmpaddr8_wmask), \\\n  .rvfi_csr_pmpaddr8_rdata (rvfi_csr_pmpaddr8_rdata), \\\n  .rvfi_csr_pmpaddr8_wdata (rvfi_csr_pmpaddr8_wdata)\n`define rvformal_csr_pmpaddr8_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr8_rmask (rvfi_csr_pmpaddr8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr8_wmask (rvfi_csr_pmpaddr8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr8_rdata (rvfi_csr_pmpaddr8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr8_wdata (rvfi_csr_pmpaddr8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr8_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr8_rmask = rvfi_csr_pmpaddr8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr8_wmask = rvfi_csr_pmpaddr8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr8_rdata = rvfi_csr_pmpaddr8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr8_wdata = rvfi_csr_pmpaddr8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr8_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr8_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr8_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr8_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr8_wdata)\n`else\n`define rvformal_csr_pmpaddr8_wires\n`define rvformal_csr_pmpaddr8_outputs\n`define rvformal_csr_pmpaddr8_inputs\n`define rvformal_csr_pmpaddr8_conn\n`define rvformal_csr_pmpaddr8_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr8_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr8 = 12'h3B8; \\\nlocalparam [11:0] csr_sindex_pmpaddr8 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr8 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR9\n`define rvformal_csr_pmpaddr9_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata;\n`define rvformal_csr_pmpaddr9_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata\n`define rvformal_csr_pmpaddr9_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata\n`define rvformal_csr_pmpaddr9_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata\n`define rvformal_csr_pmpaddr9_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr9_wdata\n`define rvformal_csr_pmpaddr9_conn, \\\n  .rvfi_csr_pmpaddr9_rmask (rvfi_csr_pmpaddr9_rmask), \\\n  .rvfi_csr_pmpaddr9_wmask (rvfi_csr_pmpaddr9_wmask), \\\n  .rvfi_csr_pmpaddr9_rdata (rvfi_csr_pmpaddr9_rdata), \\\n  .rvfi_csr_pmpaddr9_wdata (rvfi_csr_pmpaddr9_wdata)\n`define rvformal_csr_pmpaddr9_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr9_rmask (rvfi_csr_pmpaddr9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr9_wmask (rvfi_csr_pmpaddr9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr9_rdata (rvfi_csr_pmpaddr9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr9_wdata (rvfi_csr_pmpaddr9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr9_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr9_rmask = rvfi_csr_pmpaddr9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr9_wmask = rvfi_csr_pmpaddr9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr9_rdata = rvfi_csr_pmpaddr9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr9_wdata = rvfi_csr_pmpaddr9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr9_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr9_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr9_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr9_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr9_wdata)\n`else\n`define rvformal_csr_pmpaddr9_wires\n`define rvformal_csr_pmpaddr9_outputs\n`define rvformal_csr_pmpaddr9_inputs\n`define rvformal_csr_pmpaddr9_conn\n`define rvformal_csr_pmpaddr9_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr9_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr9 = 12'h3B9; \\\nlocalparam [11:0] csr_sindex_pmpaddr9 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr9 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR10\n`define rvformal_csr_pmpaddr10_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata;\n`define rvformal_csr_pmpaddr10_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata\n`define rvformal_csr_pmpaddr10_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata\n`define rvformal_csr_pmpaddr10_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata\n`define rvformal_csr_pmpaddr10_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr10_wdata\n`define rvformal_csr_pmpaddr10_conn, \\\n  .rvfi_csr_pmpaddr10_rmask (rvfi_csr_pmpaddr10_rmask), \\\n  .rvfi_csr_pmpaddr10_wmask (rvfi_csr_pmpaddr10_wmask), \\\n  .rvfi_csr_pmpaddr10_rdata (rvfi_csr_pmpaddr10_rdata), \\\n  .rvfi_csr_pmpaddr10_wdata (rvfi_csr_pmpaddr10_wdata)\n`define rvformal_csr_pmpaddr10_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr10_rmask (rvfi_csr_pmpaddr10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr10_wmask (rvfi_csr_pmpaddr10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr10_rdata (rvfi_csr_pmpaddr10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr10_wdata (rvfi_csr_pmpaddr10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr10_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr10_rmask = rvfi_csr_pmpaddr10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr10_wmask = rvfi_csr_pmpaddr10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr10_rdata = rvfi_csr_pmpaddr10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr10_wdata = rvfi_csr_pmpaddr10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr10_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr10_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr10_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr10_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr10_wdata)\n`else\n`define rvformal_csr_pmpaddr10_wires\n`define rvformal_csr_pmpaddr10_outputs\n`define rvformal_csr_pmpaddr10_inputs\n`define rvformal_csr_pmpaddr10_conn\n`define rvformal_csr_pmpaddr10_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr10_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr10 = 12'h3BA; \\\nlocalparam [11:0] csr_sindex_pmpaddr10 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr10 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR11\n`define rvformal_csr_pmpaddr11_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata;\n`define rvformal_csr_pmpaddr11_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata\n`define rvformal_csr_pmpaddr11_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata\n`define rvformal_csr_pmpaddr11_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata\n`define rvformal_csr_pmpaddr11_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr11_wdata\n`define rvformal_csr_pmpaddr11_conn, \\\n  .rvfi_csr_pmpaddr11_rmask (rvfi_csr_pmpaddr11_rmask), \\\n  .rvfi_csr_pmpaddr11_wmask (rvfi_csr_pmpaddr11_wmask), \\\n  .rvfi_csr_pmpaddr11_rdata (rvfi_csr_pmpaddr11_rdata), \\\n  .rvfi_csr_pmpaddr11_wdata (rvfi_csr_pmpaddr11_wdata)\n`define rvformal_csr_pmpaddr11_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr11_rmask (rvfi_csr_pmpaddr11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr11_wmask (rvfi_csr_pmpaddr11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr11_rdata (rvfi_csr_pmpaddr11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr11_wdata (rvfi_csr_pmpaddr11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr11_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr11_rmask = rvfi_csr_pmpaddr11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr11_wmask = rvfi_csr_pmpaddr11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr11_rdata = rvfi_csr_pmpaddr11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr11_wdata = rvfi_csr_pmpaddr11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr11_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr11_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr11_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr11_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr11_wdata)\n`else\n`define rvformal_csr_pmpaddr11_wires\n`define rvformal_csr_pmpaddr11_outputs\n`define rvformal_csr_pmpaddr11_inputs\n`define rvformal_csr_pmpaddr11_conn\n`define rvformal_csr_pmpaddr11_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr11_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr11 = 12'h3BB; \\\nlocalparam [11:0] csr_sindex_pmpaddr11 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr11 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR12\n`define rvformal_csr_pmpaddr12_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata;\n`define rvformal_csr_pmpaddr12_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata\n`define rvformal_csr_pmpaddr12_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata\n`define rvformal_csr_pmpaddr12_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata\n`define rvformal_csr_pmpaddr12_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr12_wdata\n`define rvformal_csr_pmpaddr12_conn, \\\n  .rvfi_csr_pmpaddr12_rmask (rvfi_csr_pmpaddr12_rmask), \\\n  .rvfi_csr_pmpaddr12_wmask (rvfi_csr_pmpaddr12_wmask), \\\n  .rvfi_csr_pmpaddr12_rdata (rvfi_csr_pmpaddr12_rdata), \\\n  .rvfi_csr_pmpaddr12_wdata (rvfi_csr_pmpaddr12_wdata)\n`define rvformal_csr_pmpaddr12_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr12_rmask (rvfi_csr_pmpaddr12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr12_wmask (rvfi_csr_pmpaddr12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr12_rdata (rvfi_csr_pmpaddr12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr12_wdata (rvfi_csr_pmpaddr12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr12_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr12_rmask = rvfi_csr_pmpaddr12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr12_wmask = rvfi_csr_pmpaddr12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr12_rdata = rvfi_csr_pmpaddr12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr12_wdata = rvfi_csr_pmpaddr12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr12_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr12_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr12_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr12_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr12_wdata)\n`else\n`define rvformal_csr_pmpaddr12_wires\n`define rvformal_csr_pmpaddr12_outputs\n`define rvformal_csr_pmpaddr12_inputs\n`define rvformal_csr_pmpaddr12_conn\n`define rvformal_csr_pmpaddr12_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr12_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr12 = 12'h3BC; \\\nlocalparam [11:0] csr_sindex_pmpaddr12 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr12 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR13\n`define rvformal_csr_pmpaddr13_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata;\n`define rvformal_csr_pmpaddr13_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata\n`define rvformal_csr_pmpaddr13_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata\n`define rvformal_csr_pmpaddr13_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata\n`define rvformal_csr_pmpaddr13_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr13_wdata\n`define rvformal_csr_pmpaddr13_conn, \\\n  .rvfi_csr_pmpaddr13_rmask (rvfi_csr_pmpaddr13_rmask), \\\n  .rvfi_csr_pmpaddr13_wmask (rvfi_csr_pmpaddr13_wmask), \\\n  .rvfi_csr_pmpaddr13_rdata (rvfi_csr_pmpaddr13_rdata), \\\n  .rvfi_csr_pmpaddr13_wdata (rvfi_csr_pmpaddr13_wdata)\n`define rvformal_csr_pmpaddr13_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr13_rmask (rvfi_csr_pmpaddr13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr13_wmask (rvfi_csr_pmpaddr13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr13_rdata (rvfi_csr_pmpaddr13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr13_wdata (rvfi_csr_pmpaddr13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr13_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr13_rmask = rvfi_csr_pmpaddr13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr13_wmask = rvfi_csr_pmpaddr13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr13_rdata = rvfi_csr_pmpaddr13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr13_wdata = rvfi_csr_pmpaddr13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr13_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr13_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr13_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr13_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr13_wdata)\n`else\n`define rvformal_csr_pmpaddr13_wires\n`define rvformal_csr_pmpaddr13_outputs\n`define rvformal_csr_pmpaddr13_inputs\n`define rvformal_csr_pmpaddr13_conn\n`define rvformal_csr_pmpaddr13_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr13_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr13 = 12'h3BD; \\\nlocalparam [11:0] csr_sindex_pmpaddr13 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr13 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR14\n`define rvformal_csr_pmpaddr14_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata;\n`define rvformal_csr_pmpaddr14_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata\n`define rvformal_csr_pmpaddr14_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata\n`define rvformal_csr_pmpaddr14_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata\n`define rvformal_csr_pmpaddr14_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr14_wdata\n`define rvformal_csr_pmpaddr14_conn, \\\n  .rvfi_csr_pmpaddr14_rmask (rvfi_csr_pmpaddr14_rmask), \\\n  .rvfi_csr_pmpaddr14_wmask (rvfi_csr_pmpaddr14_wmask), \\\n  .rvfi_csr_pmpaddr14_rdata (rvfi_csr_pmpaddr14_rdata), \\\n  .rvfi_csr_pmpaddr14_wdata (rvfi_csr_pmpaddr14_wdata)\n`define rvformal_csr_pmpaddr14_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr14_rmask (rvfi_csr_pmpaddr14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr14_wmask (rvfi_csr_pmpaddr14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr14_rdata (rvfi_csr_pmpaddr14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr14_wdata (rvfi_csr_pmpaddr14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr14_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr14_rmask = rvfi_csr_pmpaddr14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr14_wmask = rvfi_csr_pmpaddr14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr14_rdata = rvfi_csr_pmpaddr14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr14_wdata = rvfi_csr_pmpaddr14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr14_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr14_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr14_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr14_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr14_wdata)\n`else\n`define rvformal_csr_pmpaddr14_wires\n`define rvformal_csr_pmpaddr14_outputs\n`define rvformal_csr_pmpaddr14_inputs\n`define rvformal_csr_pmpaddr14_conn\n`define rvformal_csr_pmpaddr14_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr14_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr14 = 12'h3BE; \\\nlocalparam [11:0] csr_sindex_pmpaddr14 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr14 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR15\n`define rvformal_csr_pmpaddr15_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata;\n`define rvformal_csr_pmpaddr15_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata\n`define rvformal_csr_pmpaddr15_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata\n`define rvformal_csr_pmpaddr15_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata\n`define rvformal_csr_pmpaddr15_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr15_wdata\n`define rvformal_csr_pmpaddr15_conn, \\\n  .rvfi_csr_pmpaddr15_rmask (rvfi_csr_pmpaddr15_rmask), \\\n  .rvfi_csr_pmpaddr15_wmask (rvfi_csr_pmpaddr15_wmask), \\\n  .rvfi_csr_pmpaddr15_rdata (rvfi_csr_pmpaddr15_rdata), \\\n  .rvfi_csr_pmpaddr15_wdata (rvfi_csr_pmpaddr15_wdata)\n`define rvformal_csr_pmpaddr15_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr15_rmask (rvfi_csr_pmpaddr15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr15_wmask (rvfi_csr_pmpaddr15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr15_rdata (rvfi_csr_pmpaddr15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr15_wdata (rvfi_csr_pmpaddr15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr15_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr15_rmask = rvfi_csr_pmpaddr15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr15_wmask = rvfi_csr_pmpaddr15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr15_rdata = rvfi_csr_pmpaddr15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr15_wdata = rvfi_csr_pmpaddr15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr15_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr15_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr15_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr15_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr15_wdata)\n`else\n`define rvformal_csr_pmpaddr15_wires\n`define rvformal_csr_pmpaddr15_outputs\n`define rvformal_csr_pmpaddr15_inputs\n`define rvformal_csr_pmpaddr15_conn\n`define rvformal_csr_pmpaddr15_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr15_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr15 = 12'h3BF; \\\nlocalparam [11:0] csr_sindex_pmpaddr15 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr15 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR16\n`define rvformal_csr_pmpaddr16_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata;\n`define rvformal_csr_pmpaddr16_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata\n`define rvformal_csr_pmpaddr16_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata\n`define rvformal_csr_pmpaddr16_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata\n`define rvformal_csr_pmpaddr16_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr16_wdata\n`define rvformal_csr_pmpaddr16_conn, \\\n  .rvfi_csr_pmpaddr16_rmask (rvfi_csr_pmpaddr16_rmask), \\\n  .rvfi_csr_pmpaddr16_wmask (rvfi_csr_pmpaddr16_wmask), \\\n  .rvfi_csr_pmpaddr16_rdata (rvfi_csr_pmpaddr16_rdata), \\\n  .rvfi_csr_pmpaddr16_wdata (rvfi_csr_pmpaddr16_wdata)\n`define rvformal_csr_pmpaddr16_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr16_rmask (rvfi_csr_pmpaddr16_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr16_wmask (rvfi_csr_pmpaddr16_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr16_rdata (rvfi_csr_pmpaddr16_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr16_wdata (rvfi_csr_pmpaddr16_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr16_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr16_rmask = rvfi_csr_pmpaddr16_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr16_wmask = rvfi_csr_pmpaddr16_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr16_rdata = rvfi_csr_pmpaddr16_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr16_wdata = rvfi_csr_pmpaddr16_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr16_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr16_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr16_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr16_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr16_wdata)\n`else\n`define rvformal_csr_pmpaddr16_wires\n`define rvformal_csr_pmpaddr16_outputs\n`define rvformal_csr_pmpaddr16_inputs\n`define rvformal_csr_pmpaddr16_conn\n`define rvformal_csr_pmpaddr16_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr16_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr16 = 12'h3C0; \\\nlocalparam [11:0] csr_sindex_pmpaddr16 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr16 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR17\n`define rvformal_csr_pmpaddr17_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata;\n`define rvformal_csr_pmpaddr17_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata\n`define rvformal_csr_pmpaddr17_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata\n`define rvformal_csr_pmpaddr17_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata\n`define rvformal_csr_pmpaddr17_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr17_wdata\n`define rvformal_csr_pmpaddr17_conn, \\\n  .rvfi_csr_pmpaddr17_rmask (rvfi_csr_pmpaddr17_rmask), \\\n  .rvfi_csr_pmpaddr17_wmask (rvfi_csr_pmpaddr17_wmask), \\\n  .rvfi_csr_pmpaddr17_rdata (rvfi_csr_pmpaddr17_rdata), \\\n  .rvfi_csr_pmpaddr17_wdata (rvfi_csr_pmpaddr17_wdata)\n`define rvformal_csr_pmpaddr17_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr17_rmask (rvfi_csr_pmpaddr17_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr17_wmask (rvfi_csr_pmpaddr17_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr17_rdata (rvfi_csr_pmpaddr17_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr17_wdata (rvfi_csr_pmpaddr17_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr17_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr17_rmask = rvfi_csr_pmpaddr17_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr17_wmask = rvfi_csr_pmpaddr17_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr17_rdata = rvfi_csr_pmpaddr17_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr17_wdata = rvfi_csr_pmpaddr17_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr17_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr17_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr17_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr17_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr17_wdata)\n`else\n`define rvformal_csr_pmpaddr17_wires\n`define rvformal_csr_pmpaddr17_outputs\n`define rvformal_csr_pmpaddr17_inputs\n`define rvformal_csr_pmpaddr17_conn\n`define rvformal_csr_pmpaddr17_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr17_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr17 = 12'h3C1; \\\nlocalparam [11:0] csr_sindex_pmpaddr17 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr17 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR18\n`define rvformal_csr_pmpaddr18_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata;\n`define rvformal_csr_pmpaddr18_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata\n`define rvformal_csr_pmpaddr18_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata\n`define rvformal_csr_pmpaddr18_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata\n`define rvformal_csr_pmpaddr18_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr18_wdata\n`define rvformal_csr_pmpaddr18_conn, \\\n  .rvfi_csr_pmpaddr18_rmask (rvfi_csr_pmpaddr18_rmask), \\\n  .rvfi_csr_pmpaddr18_wmask (rvfi_csr_pmpaddr18_wmask), \\\n  .rvfi_csr_pmpaddr18_rdata (rvfi_csr_pmpaddr18_rdata), \\\n  .rvfi_csr_pmpaddr18_wdata (rvfi_csr_pmpaddr18_wdata)\n`define rvformal_csr_pmpaddr18_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr18_rmask (rvfi_csr_pmpaddr18_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr18_wmask (rvfi_csr_pmpaddr18_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr18_rdata (rvfi_csr_pmpaddr18_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr18_wdata (rvfi_csr_pmpaddr18_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr18_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr18_rmask = rvfi_csr_pmpaddr18_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr18_wmask = rvfi_csr_pmpaddr18_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr18_rdata = rvfi_csr_pmpaddr18_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr18_wdata = rvfi_csr_pmpaddr18_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr18_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr18_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr18_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr18_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr18_wdata)\n`else\n`define rvformal_csr_pmpaddr18_wires\n`define rvformal_csr_pmpaddr18_outputs\n`define rvformal_csr_pmpaddr18_inputs\n`define rvformal_csr_pmpaddr18_conn\n`define rvformal_csr_pmpaddr18_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr18_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr18 = 12'h3C2; \\\nlocalparam [11:0] csr_sindex_pmpaddr18 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr18 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR19\n`define rvformal_csr_pmpaddr19_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata;\n`define rvformal_csr_pmpaddr19_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata\n`define rvformal_csr_pmpaddr19_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata\n`define rvformal_csr_pmpaddr19_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata\n`define rvformal_csr_pmpaddr19_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr19_wdata\n`define rvformal_csr_pmpaddr19_conn, \\\n  .rvfi_csr_pmpaddr19_rmask (rvfi_csr_pmpaddr19_rmask), \\\n  .rvfi_csr_pmpaddr19_wmask (rvfi_csr_pmpaddr19_wmask), \\\n  .rvfi_csr_pmpaddr19_rdata (rvfi_csr_pmpaddr19_rdata), \\\n  .rvfi_csr_pmpaddr19_wdata (rvfi_csr_pmpaddr19_wdata)\n`define rvformal_csr_pmpaddr19_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr19_rmask (rvfi_csr_pmpaddr19_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr19_wmask (rvfi_csr_pmpaddr19_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr19_rdata (rvfi_csr_pmpaddr19_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr19_wdata (rvfi_csr_pmpaddr19_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr19_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr19_rmask = rvfi_csr_pmpaddr19_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr19_wmask = rvfi_csr_pmpaddr19_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr19_rdata = rvfi_csr_pmpaddr19_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr19_wdata = rvfi_csr_pmpaddr19_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr19_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr19_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr19_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr19_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr19_wdata)\n`else\n`define rvformal_csr_pmpaddr19_wires\n`define rvformal_csr_pmpaddr19_outputs\n`define rvformal_csr_pmpaddr19_inputs\n`define rvformal_csr_pmpaddr19_conn\n`define rvformal_csr_pmpaddr19_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr19_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr19 = 12'h3C3; \\\nlocalparam [11:0] csr_sindex_pmpaddr19 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr19 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR20\n`define rvformal_csr_pmpaddr20_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata;\n`define rvformal_csr_pmpaddr20_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata\n`define rvformal_csr_pmpaddr20_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata\n`define rvformal_csr_pmpaddr20_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata\n`define rvformal_csr_pmpaddr20_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr20_wdata\n`define rvformal_csr_pmpaddr20_conn, \\\n  .rvfi_csr_pmpaddr20_rmask (rvfi_csr_pmpaddr20_rmask), \\\n  .rvfi_csr_pmpaddr20_wmask (rvfi_csr_pmpaddr20_wmask), \\\n  .rvfi_csr_pmpaddr20_rdata (rvfi_csr_pmpaddr20_rdata), \\\n  .rvfi_csr_pmpaddr20_wdata (rvfi_csr_pmpaddr20_wdata)\n`define rvformal_csr_pmpaddr20_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr20_rmask (rvfi_csr_pmpaddr20_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr20_wmask (rvfi_csr_pmpaddr20_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr20_rdata (rvfi_csr_pmpaddr20_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr20_wdata (rvfi_csr_pmpaddr20_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr20_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr20_rmask = rvfi_csr_pmpaddr20_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr20_wmask = rvfi_csr_pmpaddr20_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr20_rdata = rvfi_csr_pmpaddr20_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr20_wdata = rvfi_csr_pmpaddr20_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr20_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr20_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr20_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr20_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr20_wdata)\n`else\n`define rvformal_csr_pmpaddr20_wires\n`define rvformal_csr_pmpaddr20_outputs\n`define rvformal_csr_pmpaddr20_inputs\n`define rvformal_csr_pmpaddr20_conn\n`define rvformal_csr_pmpaddr20_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr20_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr20 = 12'h3C4; \\\nlocalparam [11:0] csr_sindex_pmpaddr20 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr20 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR21\n`define rvformal_csr_pmpaddr21_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata;\n`define rvformal_csr_pmpaddr21_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata\n`define rvformal_csr_pmpaddr21_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata\n`define rvformal_csr_pmpaddr21_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata\n`define rvformal_csr_pmpaddr21_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr21_wdata\n`define rvformal_csr_pmpaddr21_conn, \\\n  .rvfi_csr_pmpaddr21_rmask (rvfi_csr_pmpaddr21_rmask), \\\n  .rvfi_csr_pmpaddr21_wmask (rvfi_csr_pmpaddr21_wmask), \\\n  .rvfi_csr_pmpaddr21_rdata (rvfi_csr_pmpaddr21_rdata), \\\n  .rvfi_csr_pmpaddr21_wdata (rvfi_csr_pmpaddr21_wdata)\n`define rvformal_csr_pmpaddr21_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr21_rmask (rvfi_csr_pmpaddr21_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr21_wmask (rvfi_csr_pmpaddr21_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr21_rdata (rvfi_csr_pmpaddr21_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr21_wdata (rvfi_csr_pmpaddr21_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr21_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr21_rmask = rvfi_csr_pmpaddr21_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr21_wmask = rvfi_csr_pmpaddr21_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr21_rdata = rvfi_csr_pmpaddr21_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr21_wdata = rvfi_csr_pmpaddr21_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr21_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr21_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr21_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr21_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr21_wdata)\n`else\n`define rvformal_csr_pmpaddr21_wires\n`define rvformal_csr_pmpaddr21_outputs\n`define rvformal_csr_pmpaddr21_inputs\n`define rvformal_csr_pmpaddr21_conn\n`define rvformal_csr_pmpaddr21_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr21_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr21 = 12'h3C5; \\\nlocalparam [11:0] csr_sindex_pmpaddr21 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr21 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR22\n`define rvformal_csr_pmpaddr22_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata;\n`define rvformal_csr_pmpaddr22_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata\n`define rvformal_csr_pmpaddr22_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata\n`define rvformal_csr_pmpaddr22_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata\n`define rvformal_csr_pmpaddr22_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr22_wdata\n`define rvformal_csr_pmpaddr22_conn, \\\n  .rvfi_csr_pmpaddr22_rmask (rvfi_csr_pmpaddr22_rmask), \\\n  .rvfi_csr_pmpaddr22_wmask (rvfi_csr_pmpaddr22_wmask), \\\n  .rvfi_csr_pmpaddr22_rdata (rvfi_csr_pmpaddr22_rdata), \\\n  .rvfi_csr_pmpaddr22_wdata (rvfi_csr_pmpaddr22_wdata)\n`define rvformal_csr_pmpaddr22_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr22_rmask (rvfi_csr_pmpaddr22_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr22_wmask (rvfi_csr_pmpaddr22_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr22_rdata (rvfi_csr_pmpaddr22_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr22_wdata (rvfi_csr_pmpaddr22_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr22_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr22_rmask = rvfi_csr_pmpaddr22_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr22_wmask = rvfi_csr_pmpaddr22_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr22_rdata = rvfi_csr_pmpaddr22_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr22_wdata = rvfi_csr_pmpaddr22_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr22_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr22_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr22_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr22_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr22_wdata)\n`else\n`define rvformal_csr_pmpaddr22_wires\n`define rvformal_csr_pmpaddr22_outputs\n`define rvformal_csr_pmpaddr22_inputs\n`define rvformal_csr_pmpaddr22_conn\n`define rvformal_csr_pmpaddr22_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr22_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr22 = 12'h3C6; \\\nlocalparam [11:0] csr_sindex_pmpaddr22 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr22 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR23\n`define rvformal_csr_pmpaddr23_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata;\n`define rvformal_csr_pmpaddr23_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata\n`define rvformal_csr_pmpaddr23_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata\n`define rvformal_csr_pmpaddr23_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata\n`define rvformal_csr_pmpaddr23_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr23_wdata\n`define rvformal_csr_pmpaddr23_conn, \\\n  .rvfi_csr_pmpaddr23_rmask (rvfi_csr_pmpaddr23_rmask), \\\n  .rvfi_csr_pmpaddr23_wmask (rvfi_csr_pmpaddr23_wmask), \\\n  .rvfi_csr_pmpaddr23_rdata (rvfi_csr_pmpaddr23_rdata), \\\n  .rvfi_csr_pmpaddr23_wdata (rvfi_csr_pmpaddr23_wdata)\n`define rvformal_csr_pmpaddr23_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr23_rmask (rvfi_csr_pmpaddr23_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr23_wmask (rvfi_csr_pmpaddr23_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr23_rdata (rvfi_csr_pmpaddr23_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr23_wdata (rvfi_csr_pmpaddr23_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr23_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr23_rmask = rvfi_csr_pmpaddr23_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr23_wmask = rvfi_csr_pmpaddr23_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr23_rdata = rvfi_csr_pmpaddr23_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr23_wdata = rvfi_csr_pmpaddr23_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr23_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr23_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr23_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr23_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr23_wdata)\n`else\n`define rvformal_csr_pmpaddr23_wires\n`define rvformal_csr_pmpaddr23_outputs\n`define rvformal_csr_pmpaddr23_inputs\n`define rvformal_csr_pmpaddr23_conn\n`define rvformal_csr_pmpaddr23_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr23_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr23 = 12'h3C7; \\\nlocalparam [11:0] csr_sindex_pmpaddr23 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr23 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR24\n`define rvformal_csr_pmpaddr24_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata;\n`define rvformal_csr_pmpaddr24_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata\n`define rvformal_csr_pmpaddr24_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata\n`define rvformal_csr_pmpaddr24_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata\n`define rvformal_csr_pmpaddr24_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr24_wdata\n`define rvformal_csr_pmpaddr24_conn, \\\n  .rvfi_csr_pmpaddr24_rmask (rvfi_csr_pmpaddr24_rmask), \\\n  .rvfi_csr_pmpaddr24_wmask (rvfi_csr_pmpaddr24_wmask), \\\n  .rvfi_csr_pmpaddr24_rdata (rvfi_csr_pmpaddr24_rdata), \\\n  .rvfi_csr_pmpaddr24_wdata (rvfi_csr_pmpaddr24_wdata)\n`define rvformal_csr_pmpaddr24_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr24_rmask (rvfi_csr_pmpaddr24_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr24_wmask (rvfi_csr_pmpaddr24_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr24_rdata (rvfi_csr_pmpaddr24_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr24_wdata (rvfi_csr_pmpaddr24_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr24_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr24_rmask = rvfi_csr_pmpaddr24_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr24_wmask = rvfi_csr_pmpaddr24_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr24_rdata = rvfi_csr_pmpaddr24_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr24_wdata = rvfi_csr_pmpaddr24_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr24_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr24_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr24_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr24_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr24_wdata)\n`else\n`define rvformal_csr_pmpaddr24_wires\n`define rvformal_csr_pmpaddr24_outputs\n`define rvformal_csr_pmpaddr24_inputs\n`define rvformal_csr_pmpaddr24_conn\n`define rvformal_csr_pmpaddr24_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr24_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr24 = 12'h3C8; \\\nlocalparam [11:0] csr_sindex_pmpaddr24 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr24 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR25\n`define rvformal_csr_pmpaddr25_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata;\n`define rvformal_csr_pmpaddr25_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata\n`define rvformal_csr_pmpaddr25_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata\n`define rvformal_csr_pmpaddr25_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata\n`define rvformal_csr_pmpaddr25_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr25_wdata\n`define rvformal_csr_pmpaddr25_conn, \\\n  .rvfi_csr_pmpaddr25_rmask (rvfi_csr_pmpaddr25_rmask), \\\n  .rvfi_csr_pmpaddr25_wmask (rvfi_csr_pmpaddr25_wmask), \\\n  .rvfi_csr_pmpaddr25_rdata (rvfi_csr_pmpaddr25_rdata), \\\n  .rvfi_csr_pmpaddr25_wdata (rvfi_csr_pmpaddr25_wdata)\n`define rvformal_csr_pmpaddr25_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr25_rmask (rvfi_csr_pmpaddr25_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr25_wmask (rvfi_csr_pmpaddr25_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr25_rdata (rvfi_csr_pmpaddr25_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr25_wdata (rvfi_csr_pmpaddr25_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr25_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr25_rmask = rvfi_csr_pmpaddr25_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr25_wmask = rvfi_csr_pmpaddr25_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr25_rdata = rvfi_csr_pmpaddr25_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr25_wdata = rvfi_csr_pmpaddr25_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr25_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr25_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr25_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr25_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr25_wdata)\n`else\n`define rvformal_csr_pmpaddr25_wires\n`define rvformal_csr_pmpaddr25_outputs\n`define rvformal_csr_pmpaddr25_inputs\n`define rvformal_csr_pmpaddr25_conn\n`define rvformal_csr_pmpaddr25_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr25_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr25 = 12'h3C9; \\\nlocalparam [11:0] csr_sindex_pmpaddr25 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr25 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR26\n`define rvformal_csr_pmpaddr26_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata;\n`define rvformal_csr_pmpaddr26_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata\n`define rvformal_csr_pmpaddr26_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata\n`define rvformal_csr_pmpaddr26_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata\n`define rvformal_csr_pmpaddr26_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr26_wdata\n`define rvformal_csr_pmpaddr26_conn, \\\n  .rvfi_csr_pmpaddr26_rmask (rvfi_csr_pmpaddr26_rmask), \\\n  .rvfi_csr_pmpaddr26_wmask (rvfi_csr_pmpaddr26_wmask), \\\n  .rvfi_csr_pmpaddr26_rdata (rvfi_csr_pmpaddr26_rdata), \\\n  .rvfi_csr_pmpaddr26_wdata (rvfi_csr_pmpaddr26_wdata)\n`define rvformal_csr_pmpaddr26_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr26_rmask (rvfi_csr_pmpaddr26_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr26_wmask (rvfi_csr_pmpaddr26_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr26_rdata (rvfi_csr_pmpaddr26_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr26_wdata (rvfi_csr_pmpaddr26_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr26_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr26_rmask = rvfi_csr_pmpaddr26_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr26_wmask = rvfi_csr_pmpaddr26_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr26_rdata = rvfi_csr_pmpaddr26_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr26_wdata = rvfi_csr_pmpaddr26_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr26_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr26_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr26_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr26_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr26_wdata)\n`else\n`define rvformal_csr_pmpaddr26_wires\n`define rvformal_csr_pmpaddr26_outputs\n`define rvformal_csr_pmpaddr26_inputs\n`define rvformal_csr_pmpaddr26_conn\n`define rvformal_csr_pmpaddr26_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr26_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr26 = 12'h3CA; \\\nlocalparam [11:0] csr_sindex_pmpaddr26 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr26 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR27\n`define rvformal_csr_pmpaddr27_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata;\n`define rvformal_csr_pmpaddr27_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata\n`define rvformal_csr_pmpaddr27_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata\n`define rvformal_csr_pmpaddr27_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata\n`define rvformal_csr_pmpaddr27_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr27_wdata\n`define rvformal_csr_pmpaddr27_conn, \\\n  .rvfi_csr_pmpaddr27_rmask (rvfi_csr_pmpaddr27_rmask), \\\n  .rvfi_csr_pmpaddr27_wmask (rvfi_csr_pmpaddr27_wmask), \\\n  .rvfi_csr_pmpaddr27_rdata (rvfi_csr_pmpaddr27_rdata), \\\n  .rvfi_csr_pmpaddr27_wdata (rvfi_csr_pmpaddr27_wdata)\n`define rvformal_csr_pmpaddr27_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr27_rmask (rvfi_csr_pmpaddr27_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr27_wmask (rvfi_csr_pmpaddr27_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr27_rdata (rvfi_csr_pmpaddr27_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr27_wdata (rvfi_csr_pmpaddr27_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr27_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr27_rmask = rvfi_csr_pmpaddr27_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr27_wmask = rvfi_csr_pmpaddr27_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr27_rdata = rvfi_csr_pmpaddr27_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr27_wdata = rvfi_csr_pmpaddr27_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr27_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr27_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr27_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr27_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr27_wdata)\n`else\n`define rvformal_csr_pmpaddr27_wires\n`define rvformal_csr_pmpaddr27_outputs\n`define rvformal_csr_pmpaddr27_inputs\n`define rvformal_csr_pmpaddr27_conn\n`define rvformal_csr_pmpaddr27_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr27_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr27 = 12'h3CB; \\\nlocalparam [11:0] csr_sindex_pmpaddr27 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr27 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR28\n`define rvformal_csr_pmpaddr28_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata;\n`define rvformal_csr_pmpaddr28_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata\n`define rvformal_csr_pmpaddr28_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata\n`define rvformal_csr_pmpaddr28_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata\n`define rvformal_csr_pmpaddr28_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr28_wdata\n`define rvformal_csr_pmpaddr28_conn, \\\n  .rvfi_csr_pmpaddr28_rmask (rvfi_csr_pmpaddr28_rmask), \\\n  .rvfi_csr_pmpaddr28_wmask (rvfi_csr_pmpaddr28_wmask), \\\n  .rvfi_csr_pmpaddr28_rdata (rvfi_csr_pmpaddr28_rdata), \\\n  .rvfi_csr_pmpaddr28_wdata (rvfi_csr_pmpaddr28_wdata)\n`define rvformal_csr_pmpaddr28_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr28_rmask (rvfi_csr_pmpaddr28_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr28_wmask (rvfi_csr_pmpaddr28_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr28_rdata (rvfi_csr_pmpaddr28_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr28_wdata (rvfi_csr_pmpaddr28_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr28_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr28_rmask = rvfi_csr_pmpaddr28_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr28_wmask = rvfi_csr_pmpaddr28_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr28_rdata = rvfi_csr_pmpaddr28_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr28_wdata = rvfi_csr_pmpaddr28_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr28_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr28_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr28_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr28_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr28_wdata)\n`else\n`define rvformal_csr_pmpaddr28_wires\n`define rvformal_csr_pmpaddr28_outputs\n`define rvformal_csr_pmpaddr28_inputs\n`define rvformal_csr_pmpaddr28_conn\n`define rvformal_csr_pmpaddr28_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr28_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr28 = 12'h3CC; \\\nlocalparam [11:0] csr_sindex_pmpaddr28 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr28 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR29\n`define rvformal_csr_pmpaddr29_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata;\n`define rvformal_csr_pmpaddr29_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata\n`define rvformal_csr_pmpaddr29_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata\n`define rvformal_csr_pmpaddr29_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata\n`define rvformal_csr_pmpaddr29_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr29_wdata\n`define rvformal_csr_pmpaddr29_conn, \\\n  .rvfi_csr_pmpaddr29_rmask (rvfi_csr_pmpaddr29_rmask), \\\n  .rvfi_csr_pmpaddr29_wmask (rvfi_csr_pmpaddr29_wmask), \\\n  .rvfi_csr_pmpaddr29_rdata (rvfi_csr_pmpaddr29_rdata), \\\n  .rvfi_csr_pmpaddr29_wdata (rvfi_csr_pmpaddr29_wdata)\n`define rvformal_csr_pmpaddr29_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr29_rmask (rvfi_csr_pmpaddr29_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr29_wmask (rvfi_csr_pmpaddr29_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr29_rdata (rvfi_csr_pmpaddr29_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr29_wdata (rvfi_csr_pmpaddr29_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr29_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr29_rmask = rvfi_csr_pmpaddr29_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr29_wmask = rvfi_csr_pmpaddr29_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr29_rdata = rvfi_csr_pmpaddr29_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr29_wdata = rvfi_csr_pmpaddr29_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr29_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr29_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr29_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr29_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr29_wdata)\n`else\n`define rvformal_csr_pmpaddr29_wires\n`define rvformal_csr_pmpaddr29_outputs\n`define rvformal_csr_pmpaddr29_inputs\n`define rvformal_csr_pmpaddr29_conn\n`define rvformal_csr_pmpaddr29_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr29_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr29 = 12'h3CD; \\\nlocalparam [11:0] csr_sindex_pmpaddr29 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr29 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR30\n`define rvformal_csr_pmpaddr30_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata;\n`define rvformal_csr_pmpaddr30_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata\n`define rvformal_csr_pmpaddr30_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata\n`define rvformal_csr_pmpaddr30_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata\n`define rvformal_csr_pmpaddr30_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr30_wdata\n`define rvformal_csr_pmpaddr30_conn, \\\n  .rvfi_csr_pmpaddr30_rmask (rvfi_csr_pmpaddr30_rmask), \\\n  .rvfi_csr_pmpaddr30_wmask (rvfi_csr_pmpaddr30_wmask), \\\n  .rvfi_csr_pmpaddr30_rdata (rvfi_csr_pmpaddr30_rdata), \\\n  .rvfi_csr_pmpaddr30_wdata (rvfi_csr_pmpaddr30_wdata)\n`define rvformal_csr_pmpaddr30_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr30_rmask (rvfi_csr_pmpaddr30_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr30_wmask (rvfi_csr_pmpaddr30_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr30_rdata (rvfi_csr_pmpaddr30_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr30_wdata (rvfi_csr_pmpaddr30_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr30_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr30_rmask = rvfi_csr_pmpaddr30_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr30_wmask = rvfi_csr_pmpaddr30_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr30_rdata = rvfi_csr_pmpaddr30_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr30_wdata = rvfi_csr_pmpaddr30_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr30_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr30_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr30_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr30_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr30_wdata)\n`else\n`define rvformal_csr_pmpaddr30_wires\n`define rvformal_csr_pmpaddr30_outputs\n`define rvformal_csr_pmpaddr30_inputs\n`define rvformal_csr_pmpaddr30_conn\n`define rvformal_csr_pmpaddr30_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr30_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr30 = 12'h3CE; \\\nlocalparam [11:0] csr_sindex_pmpaddr30 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr30 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR31\n`define rvformal_csr_pmpaddr31_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata;\n`define rvformal_csr_pmpaddr31_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata\n`define rvformal_csr_pmpaddr31_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata\n`define rvformal_csr_pmpaddr31_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata\n`define rvformal_csr_pmpaddr31_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr31_wdata\n`define rvformal_csr_pmpaddr31_conn, \\\n  .rvfi_csr_pmpaddr31_rmask (rvfi_csr_pmpaddr31_rmask), \\\n  .rvfi_csr_pmpaddr31_wmask (rvfi_csr_pmpaddr31_wmask), \\\n  .rvfi_csr_pmpaddr31_rdata (rvfi_csr_pmpaddr31_rdata), \\\n  .rvfi_csr_pmpaddr31_wdata (rvfi_csr_pmpaddr31_wdata)\n`define rvformal_csr_pmpaddr31_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr31_rmask (rvfi_csr_pmpaddr31_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr31_wmask (rvfi_csr_pmpaddr31_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr31_rdata (rvfi_csr_pmpaddr31_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr31_wdata (rvfi_csr_pmpaddr31_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr31_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr31_rmask = rvfi_csr_pmpaddr31_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr31_wmask = rvfi_csr_pmpaddr31_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr31_rdata = rvfi_csr_pmpaddr31_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr31_wdata = rvfi_csr_pmpaddr31_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr31_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr31_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr31_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr31_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr31_wdata)\n`else\n`define rvformal_csr_pmpaddr31_wires\n`define rvformal_csr_pmpaddr31_outputs\n`define rvformal_csr_pmpaddr31_inputs\n`define rvformal_csr_pmpaddr31_conn\n`define rvformal_csr_pmpaddr31_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr31_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr31 = 12'h3CF; \\\nlocalparam [11:0] csr_sindex_pmpaddr31 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr31 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR32\n`define rvformal_csr_pmpaddr32_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata;\n`define rvformal_csr_pmpaddr32_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata\n`define rvformal_csr_pmpaddr32_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata\n`define rvformal_csr_pmpaddr32_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata\n`define rvformal_csr_pmpaddr32_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr32_wdata\n`define rvformal_csr_pmpaddr32_conn, \\\n  .rvfi_csr_pmpaddr32_rmask (rvfi_csr_pmpaddr32_rmask), \\\n  .rvfi_csr_pmpaddr32_wmask (rvfi_csr_pmpaddr32_wmask), \\\n  .rvfi_csr_pmpaddr32_rdata (rvfi_csr_pmpaddr32_rdata), \\\n  .rvfi_csr_pmpaddr32_wdata (rvfi_csr_pmpaddr32_wdata)\n`define rvformal_csr_pmpaddr32_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr32_rmask (rvfi_csr_pmpaddr32_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr32_wmask (rvfi_csr_pmpaddr32_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr32_rdata (rvfi_csr_pmpaddr32_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr32_wdata (rvfi_csr_pmpaddr32_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr32_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr32_rmask = rvfi_csr_pmpaddr32_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr32_wmask = rvfi_csr_pmpaddr32_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr32_rdata = rvfi_csr_pmpaddr32_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr32_wdata = rvfi_csr_pmpaddr32_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr32_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr32_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr32_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr32_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr32_wdata)\n`else\n`define rvformal_csr_pmpaddr32_wires\n`define rvformal_csr_pmpaddr32_outputs\n`define rvformal_csr_pmpaddr32_inputs\n`define rvformal_csr_pmpaddr32_conn\n`define rvformal_csr_pmpaddr32_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr32_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr32 = 12'h3D0; \\\nlocalparam [11:0] csr_sindex_pmpaddr32 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr32 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR33\n`define rvformal_csr_pmpaddr33_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata;\n`define rvformal_csr_pmpaddr33_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata\n`define rvformal_csr_pmpaddr33_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata\n`define rvformal_csr_pmpaddr33_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata\n`define rvformal_csr_pmpaddr33_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr33_wdata\n`define rvformal_csr_pmpaddr33_conn, \\\n  .rvfi_csr_pmpaddr33_rmask (rvfi_csr_pmpaddr33_rmask), \\\n  .rvfi_csr_pmpaddr33_wmask (rvfi_csr_pmpaddr33_wmask), \\\n  .rvfi_csr_pmpaddr33_rdata (rvfi_csr_pmpaddr33_rdata), \\\n  .rvfi_csr_pmpaddr33_wdata (rvfi_csr_pmpaddr33_wdata)\n`define rvformal_csr_pmpaddr33_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr33_rmask (rvfi_csr_pmpaddr33_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr33_wmask (rvfi_csr_pmpaddr33_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr33_rdata (rvfi_csr_pmpaddr33_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr33_wdata (rvfi_csr_pmpaddr33_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr33_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr33_rmask = rvfi_csr_pmpaddr33_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr33_wmask = rvfi_csr_pmpaddr33_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr33_rdata = rvfi_csr_pmpaddr33_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr33_wdata = rvfi_csr_pmpaddr33_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr33_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr33_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr33_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr33_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr33_wdata)\n`else\n`define rvformal_csr_pmpaddr33_wires\n`define rvformal_csr_pmpaddr33_outputs\n`define rvformal_csr_pmpaddr33_inputs\n`define rvformal_csr_pmpaddr33_conn\n`define rvformal_csr_pmpaddr33_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr33_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr33 = 12'h3D1; \\\nlocalparam [11:0] csr_sindex_pmpaddr33 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr33 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR34\n`define rvformal_csr_pmpaddr34_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata;\n`define rvformal_csr_pmpaddr34_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata\n`define rvformal_csr_pmpaddr34_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata\n`define rvformal_csr_pmpaddr34_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata\n`define rvformal_csr_pmpaddr34_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr34_wdata\n`define rvformal_csr_pmpaddr34_conn, \\\n  .rvfi_csr_pmpaddr34_rmask (rvfi_csr_pmpaddr34_rmask), \\\n  .rvfi_csr_pmpaddr34_wmask (rvfi_csr_pmpaddr34_wmask), \\\n  .rvfi_csr_pmpaddr34_rdata (rvfi_csr_pmpaddr34_rdata), \\\n  .rvfi_csr_pmpaddr34_wdata (rvfi_csr_pmpaddr34_wdata)\n`define rvformal_csr_pmpaddr34_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr34_rmask (rvfi_csr_pmpaddr34_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr34_wmask (rvfi_csr_pmpaddr34_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr34_rdata (rvfi_csr_pmpaddr34_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr34_wdata (rvfi_csr_pmpaddr34_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr34_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr34_rmask = rvfi_csr_pmpaddr34_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr34_wmask = rvfi_csr_pmpaddr34_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr34_rdata = rvfi_csr_pmpaddr34_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr34_wdata = rvfi_csr_pmpaddr34_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr34_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr34_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr34_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr34_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr34_wdata)\n`else\n`define rvformal_csr_pmpaddr34_wires\n`define rvformal_csr_pmpaddr34_outputs\n`define rvformal_csr_pmpaddr34_inputs\n`define rvformal_csr_pmpaddr34_conn\n`define rvformal_csr_pmpaddr34_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr34_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr34 = 12'h3D2; \\\nlocalparam [11:0] csr_sindex_pmpaddr34 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr34 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR35\n`define rvformal_csr_pmpaddr35_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata;\n`define rvformal_csr_pmpaddr35_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata\n`define rvformal_csr_pmpaddr35_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata\n`define rvformal_csr_pmpaddr35_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata\n`define rvformal_csr_pmpaddr35_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr35_wdata\n`define rvformal_csr_pmpaddr35_conn, \\\n  .rvfi_csr_pmpaddr35_rmask (rvfi_csr_pmpaddr35_rmask), \\\n  .rvfi_csr_pmpaddr35_wmask (rvfi_csr_pmpaddr35_wmask), \\\n  .rvfi_csr_pmpaddr35_rdata (rvfi_csr_pmpaddr35_rdata), \\\n  .rvfi_csr_pmpaddr35_wdata (rvfi_csr_pmpaddr35_wdata)\n`define rvformal_csr_pmpaddr35_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr35_rmask (rvfi_csr_pmpaddr35_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr35_wmask (rvfi_csr_pmpaddr35_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr35_rdata (rvfi_csr_pmpaddr35_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr35_wdata (rvfi_csr_pmpaddr35_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr35_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr35_rmask = rvfi_csr_pmpaddr35_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr35_wmask = rvfi_csr_pmpaddr35_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr35_rdata = rvfi_csr_pmpaddr35_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr35_wdata = rvfi_csr_pmpaddr35_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr35_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr35_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr35_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr35_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr35_wdata)\n`else\n`define rvformal_csr_pmpaddr35_wires\n`define rvformal_csr_pmpaddr35_outputs\n`define rvformal_csr_pmpaddr35_inputs\n`define rvformal_csr_pmpaddr35_conn\n`define rvformal_csr_pmpaddr35_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr35_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr35 = 12'h3D3; \\\nlocalparam [11:0] csr_sindex_pmpaddr35 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr35 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR36\n`define rvformal_csr_pmpaddr36_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata;\n`define rvformal_csr_pmpaddr36_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata\n`define rvformal_csr_pmpaddr36_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata\n`define rvformal_csr_pmpaddr36_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata\n`define rvformal_csr_pmpaddr36_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr36_wdata\n`define rvformal_csr_pmpaddr36_conn, \\\n  .rvfi_csr_pmpaddr36_rmask (rvfi_csr_pmpaddr36_rmask), \\\n  .rvfi_csr_pmpaddr36_wmask (rvfi_csr_pmpaddr36_wmask), \\\n  .rvfi_csr_pmpaddr36_rdata (rvfi_csr_pmpaddr36_rdata), \\\n  .rvfi_csr_pmpaddr36_wdata (rvfi_csr_pmpaddr36_wdata)\n`define rvformal_csr_pmpaddr36_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr36_rmask (rvfi_csr_pmpaddr36_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr36_wmask (rvfi_csr_pmpaddr36_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr36_rdata (rvfi_csr_pmpaddr36_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr36_wdata (rvfi_csr_pmpaddr36_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr36_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr36_rmask = rvfi_csr_pmpaddr36_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr36_wmask = rvfi_csr_pmpaddr36_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr36_rdata = rvfi_csr_pmpaddr36_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr36_wdata = rvfi_csr_pmpaddr36_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr36_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr36_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr36_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr36_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr36_wdata)\n`else\n`define rvformal_csr_pmpaddr36_wires\n`define rvformal_csr_pmpaddr36_outputs\n`define rvformal_csr_pmpaddr36_inputs\n`define rvformal_csr_pmpaddr36_conn\n`define rvformal_csr_pmpaddr36_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr36_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr36 = 12'h3D4; \\\nlocalparam [11:0] csr_sindex_pmpaddr36 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr36 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR37\n`define rvformal_csr_pmpaddr37_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata;\n`define rvformal_csr_pmpaddr37_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata\n`define rvformal_csr_pmpaddr37_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata\n`define rvformal_csr_pmpaddr37_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata\n`define rvformal_csr_pmpaddr37_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr37_wdata\n`define rvformal_csr_pmpaddr37_conn, \\\n  .rvfi_csr_pmpaddr37_rmask (rvfi_csr_pmpaddr37_rmask), \\\n  .rvfi_csr_pmpaddr37_wmask (rvfi_csr_pmpaddr37_wmask), \\\n  .rvfi_csr_pmpaddr37_rdata (rvfi_csr_pmpaddr37_rdata), \\\n  .rvfi_csr_pmpaddr37_wdata (rvfi_csr_pmpaddr37_wdata)\n`define rvformal_csr_pmpaddr37_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr37_rmask (rvfi_csr_pmpaddr37_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr37_wmask (rvfi_csr_pmpaddr37_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr37_rdata (rvfi_csr_pmpaddr37_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr37_wdata (rvfi_csr_pmpaddr37_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr37_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr37_rmask = rvfi_csr_pmpaddr37_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr37_wmask = rvfi_csr_pmpaddr37_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr37_rdata = rvfi_csr_pmpaddr37_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr37_wdata = rvfi_csr_pmpaddr37_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr37_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr37_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr37_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr37_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr37_wdata)\n`else\n`define rvformal_csr_pmpaddr37_wires\n`define rvformal_csr_pmpaddr37_outputs\n`define rvformal_csr_pmpaddr37_inputs\n`define rvformal_csr_pmpaddr37_conn\n`define rvformal_csr_pmpaddr37_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr37_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr37 = 12'h3D5; \\\nlocalparam [11:0] csr_sindex_pmpaddr37 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr37 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR38\n`define rvformal_csr_pmpaddr38_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata;\n`define rvformal_csr_pmpaddr38_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata\n`define rvformal_csr_pmpaddr38_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata\n`define rvformal_csr_pmpaddr38_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata\n`define rvformal_csr_pmpaddr38_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr38_wdata\n`define rvformal_csr_pmpaddr38_conn, \\\n  .rvfi_csr_pmpaddr38_rmask (rvfi_csr_pmpaddr38_rmask), \\\n  .rvfi_csr_pmpaddr38_wmask (rvfi_csr_pmpaddr38_wmask), \\\n  .rvfi_csr_pmpaddr38_rdata (rvfi_csr_pmpaddr38_rdata), \\\n  .rvfi_csr_pmpaddr38_wdata (rvfi_csr_pmpaddr38_wdata)\n`define rvformal_csr_pmpaddr38_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr38_rmask (rvfi_csr_pmpaddr38_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr38_wmask (rvfi_csr_pmpaddr38_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr38_rdata (rvfi_csr_pmpaddr38_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr38_wdata (rvfi_csr_pmpaddr38_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr38_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr38_rmask = rvfi_csr_pmpaddr38_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr38_wmask = rvfi_csr_pmpaddr38_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr38_rdata = rvfi_csr_pmpaddr38_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr38_wdata = rvfi_csr_pmpaddr38_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr38_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr38_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr38_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr38_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr38_wdata)\n`else\n`define rvformal_csr_pmpaddr38_wires\n`define rvformal_csr_pmpaddr38_outputs\n`define rvformal_csr_pmpaddr38_inputs\n`define rvformal_csr_pmpaddr38_conn\n`define rvformal_csr_pmpaddr38_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr38_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr38 = 12'h3D6; \\\nlocalparam [11:0] csr_sindex_pmpaddr38 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr38 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR39\n`define rvformal_csr_pmpaddr39_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata;\n`define rvformal_csr_pmpaddr39_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata\n`define rvformal_csr_pmpaddr39_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata\n`define rvformal_csr_pmpaddr39_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata\n`define rvformal_csr_pmpaddr39_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr39_wdata\n`define rvformal_csr_pmpaddr39_conn, \\\n  .rvfi_csr_pmpaddr39_rmask (rvfi_csr_pmpaddr39_rmask), \\\n  .rvfi_csr_pmpaddr39_wmask (rvfi_csr_pmpaddr39_wmask), \\\n  .rvfi_csr_pmpaddr39_rdata (rvfi_csr_pmpaddr39_rdata), \\\n  .rvfi_csr_pmpaddr39_wdata (rvfi_csr_pmpaddr39_wdata)\n`define rvformal_csr_pmpaddr39_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr39_rmask (rvfi_csr_pmpaddr39_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr39_wmask (rvfi_csr_pmpaddr39_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr39_rdata (rvfi_csr_pmpaddr39_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr39_wdata (rvfi_csr_pmpaddr39_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr39_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr39_rmask = rvfi_csr_pmpaddr39_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr39_wmask = rvfi_csr_pmpaddr39_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr39_rdata = rvfi_csr_pmpaddr39_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr39_wdata = rvfi_csr_pmpaddr39_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr39_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr39_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr39_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr39_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr39_wdata)\n`else\n`define rvformal_csr_pmpaddr39_wires\n`define rvformal_csr_pmpaddr39_outputs\n`define rvformal_csr_pmpaddr39_inputs\n`define rvformal_csr_pmpaddr39_conn\n`define rvformal_csr_pmpaddr39_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr39_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr39 = 12'h3D7; \\\nlocalparam [11:0] csr_sindex_pmpaddr39 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr39 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR40\n`define rvformal_csr_pmpaddr40_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata;\n`define rvformal_csr_pmpaddr40_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata\n`define rvformal_csr_pmpaddr40_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata\n`define rvformal_csr_pmpaddr40_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata\n`define rvformal_csr_pmpaddr40_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr40_wdata\n`define rvformal_csr_pmpaddr40_conn, \\\n  .rvfi_csr_pmpaddr40_rmask (rvfi_csr_pmpaddr40_rmask), \\\n  .rvfi_csr_pmpaddr40_wmask (rvfi_csr_pmpaddr40_wmask), \\\n  .rvfi_csr_pmpaddr40_rdata (rvfi_csr_pmpaddr40_rdata), \\\n  .rvfi_csr_pmpaddr40_wdata (rvfi_csr_pmpaddr40_wdata)\n`define rvformal_csr_pmpaddr40_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr40_rmask (rvfi_csr_pmpaddr40_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr40_wmask (rvfi_csr_pmpaddr40_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr40_rdata (rvfi_csr_pmpaddr40_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr40_wdata (rvfi_csr_pmpaddr40_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr40_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr40_rmask = rvfi_csr_pmpaddr40_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr40_wmask = rvfi_csr_pmpaddr40_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr40_rdata = rvfi_csr_pmpaddr40_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr40_wdata = rvfi_csr_pmpaddr40_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr40_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr40_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr40_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr40_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr40_wdata)\n`else\n`define rvformal_csr_pmpaddr40_wires\n`define rvformal_csr_pmpaddr40_outputs\n`define rvformal_csr_pmpaddr40_inputs\n`define rvformal_csr_pmpaddr40_conn\n`define rvformal_csr_pmpaddr40_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr40_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr40 = 12'h3D8; \\\nlocalparam [11:0] csr_sindex_pmpaddr40 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr40 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR41\n`define rvformal_csr_pmpaddr41_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata;\n`define rvformal_csr_pmpaddr41_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata\n`define rvformal_csr_pmpaddr41_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata\n`define rvformal_csr_pmpaddr41_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata\n`define rvformal_csr_pmpaddr41_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr41_wdata\n`define rvformal_csr_pmpaddr41_conn, \\\n  .rvfi_csr_pmpaddr41_rmask (rvfi_csr_pmpaddr41_rmask), \\\n  .rvfi_csr_pmpaddr41_wmask (rvfi_csr_pmpaddr41_wmask), \\\n  .rvfi_csr_pmpaddr41_rdata (rvfi_csr_pmpaddr41_rdata), \\\n  .rvfi_csr_pmpaddr41_wdata (rvfi_csr_pmpaddr41_wdata)\n`define rvformal_csr_pmpaddr41_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr41_rmask (rvfi_csr_pmpaddr41_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr41_wmask (rvfi_csr_pmpaddr41_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr41_rdata (rvfi_csr_pmpaddr41_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr41_wdata (rvfi_csr_pmpaddr41_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr41_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr41_rmask = rvfi_csr_pmpaddr41_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr41_wmask = rvfi_csr_pmpaddr41_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr41_rdata = rvfi_csr_pmpaddr41_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr41_wdata = rvfi_csr_pmpaddr41_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr41_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr41_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr41_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr41_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr41_wdata)\n`else\n`define rvformal_csr_pmpaddr41_wires\n`define rvformal_csr_pmpaddr41_outputs\n`define rvformal_csr_pmpaddr41_inputs\n`define rvformal_csr_pmpaddr41_conn\n`define rvformal_csr_pmpaddr41_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr41_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr41 = 12'h3D9; \\\nlocalparam [11:0] csr_sindex_pmpaddr41 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr41 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR42\n`define rvformal_csr_pmpaddr42_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata;\n`define rvformal_csr_pmpaddr42_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata\n`define rvformal_csr_pmpaddr42_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata\n`define rvformal_csr_pmpaddr42_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata\n`define rvformal_csr_pmpaddr42_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr42_wdata\n`define rvformal_csr_pmpaddr42_conn, \\\n  .rvfi_csr_pmpaddr42_rmask (rvfi_csr_pmpaddr42_rmask), \\\n  .rvfi_csr_pmpaddr42_wmask (rvfi_csr_pmpaddr42_wmask), \\\n  .rvfi_csr_pmpaddr42_rdata (rvfi_csr_pmpaddr42_rdata), \\\n  .rvfi_csr_pmpaddr42_wdata (rvfi_csr_pmpaddr42_wdata)\n`define rvformal_csr_pmpaddr42_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr42_rmask (rvfi_csr_pmpaddr42_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr42_wmask (rvfi_csr_pmpaddr42_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr42_rdata (rvfi_csr_pmpaddr42_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr42_wdata (rvfi_csr_pmpaddr42_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr42_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr42_rmask = rvfi_csr_pmpaddr42_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr42_wmask = rvfi_csr_pmpaddr42_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr42_rdata = rvfi_csr_pmpaddr42_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr42_wdata = rvfi_csr_pmpaddr42_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr42_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr42_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr42_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr42_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr42_wdata)\n`else\n`define rvformal_csr_pmpaddr42_wires\n`define rvformal_csr_pmpaddr42_outputs\n`define rvformal_csr_pmpaddr42_inputs\n`define rvformal_csr_pmpaddr42_conn\n`define rvformal_csr_pmpaddr42_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr42_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr42 = 12'h3DA; \\\nlocalparam [11:0] csr_sindex_pmpaddr42 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr42 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR43\n`define rvformal_csr_pmpaddr43_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata;\n`define rvformal_csr_pmpaddr43_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata\n`define rvformal_csr_pmpaddr43_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata\n`define rvformal_csr_pmpaddr43_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata\n`define rvformal_csr_pmpaddr43_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr43_wdata\n`define rvformal_csr_pmpaddr43_conn, \\\n  .rvfi_csr_pmpaddr43_rmask (rvfi_csr_pmpaddr43_rmask), \\\n  .rvfi_csr_pmpaddr43_wmask (rvfi_csr_pmpaddr43_wmask), \\\n  .rvfi_csr_pmpaddr43_rdata (rvfi_csr_pmpaddr43_rdata), \\\n  .rvfi_csr_pmpaddr43_wdata (rvfi_csr_pmpaddr43_wdata)\n`define rvformal_csr_pmpaddr43_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr43_rmask (rvfi_csr_pmpaddr43_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr43_wmask (rvfi_csr_pmpaddr43_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr43_rdata (rvfi_csr_pmpaddr43_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr43_wdata (rvfi_csr_pmpaddr43_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr43_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr43_rmask = rvfi_csr_pmpaddr43_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr43_wmask = rvfi_csr_pmpaddr43_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr43_rdata = rvfi_csr_pmpaddr43_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr43_wdata = rvfi_csr_pmpaddr43_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr43_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr43_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr43_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr43_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr43_wdata)\n`else\n`define rvformal_csr_pmpaddr43_wires\n`define rvformal_csr_pmpaddr43_outputs\n`define rvformal_csr_pmpaddr43_inputs\n`define rvformal_csr_pmpaddr43_conn\n`define rvformal_csr_pmpaddr43_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr43_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr43 = 12'h3DB; \\\nlocalparam [11:0] csr_sindex_pmpaddr43 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr43 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR44\n`define rvformal_csr_pmpaddr44_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata;\n`define rvformal_csr_pmpaddr44_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata\n`define rvformal_csr_pmpaddr44_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata\n`define rvformal_csr_pmpaddr44_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata\n`define rvformal_csr_pmpaddr44_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr44_wdata\n`define rvformal_csr_pmpaddr44_conn, \\\n  .rvfi_csr_pmpaddr44_rmask (rvfi_csr_pmpaddr44_rmask), \\\n  .rvfi_csr_pmpaddr44_wmask (rvfi_csr_pmpaddr44_wmask), \\\n  .rvfi_csr_pmpaddr44_rdata (rvfi_csr_pmpaddr44_rdata), \\\n  .rvfi_csr_pmpaddr44_wdata (rvfi_csr_pmpaddr44_wdata)\n`define rvformal_csr_pmpaddr44_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr44_rmask (rvfi_csr_pmpaddr44_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr44_wmask (rvfi_csr_pmpaddr44_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr44_rdata (rvfi_csr_pmpaddr44_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr44_wdata (rvfi_csr_pmpaddr44_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr44_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr44_rmask = rvfi_csr_pmpaddr44_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr44_wmask = rvfi_csr_pmpaddr44_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr44_rdata = rvfi_csr_pmpaddr44_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr44_wdata = rvfi_csr_pmpaddr44_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr44_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr44_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr44_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr44_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr44_wdata)\n`else\n`define rvformal_csr_pmpaddr44_wires\n`define rvformal_csr_pmpaddr44_outputs\n`define rvformal_csr_pmpaddr44_inputs\n`define rvformal_csr_pmpaddr44_conn\n`define rvformal_csr_pmpaddr44_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr44_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr44 = 12'h3DC; \\\nlocalparam [11:0] csr_sindex_pmpaddr44 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr44 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR45\n`define rvformal_csr_pmpaddr45_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata;\n`define rvformal_csr_pmpaddr45_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata\n`define rvformal_csr_pmpaddr45_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata\n`define rvformal_csr_pmpaddr45_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata\n`define rvformal_csr_pmpaddr45_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr45_wdata\n`define rvformal_csr_pmpaddr45_conn, \\\n  .rvfi_csr_pmpaddr45_rmask (rvfi_csr_pmpaddr45_rmask), \\\n  .rvfi_csr_pmpaddr45_wmask (rvfi_csr_pmpaddr45_wmask), \\\n  .rvfi_csr_pmpaddr45_rdata (rvfi_csr_pmpaddr45_rdata), \\\n  .rvfi_csr_pmpaddr45_wdata (rvfi_csr_pmpaddr45_wdata)\n`define rvformal_csr_pmpaddr45_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr45_rmask (rvfi_csr_pmpaddr45_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr45_wmask (rvfi_csr_pmpaddr45_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr45_rdata (rvfi_csr_pmpaddr45_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr45_wdata (rvfi_csr_pmpaddr45_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr45_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr45_rmask = rvfi_csr_pmpaddr45_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr45_wmask = rvfi_csr_pmpaddr45_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr45_rdata = rvfi_csr_pmpaddr45_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr45_wdata = rvfi_csr_pmpaddr45_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr45_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr45_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr45_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr45_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr45_wdata)\n`else\n`define rvformal_csr_pmpaddr45_wires\n`define rvformal_csr_pmpaddr45_outputs\n`define rvformal_csr_pmpaddr45_inputs\n`define rvformal_csr_pmpaddr45_conn\n`define rvformal_csr_pmpaddr45_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr45_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr45 = 12'h3DD; \\\nlocalparam [11:0] csr_sindex_pmpaddr45 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr45 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR46\n`define rvformal_csr_pmpaddr46_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata;\n`define rvformal_csr_pmpaddr46_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata\n`define rvformal_csr_pmpaddr46_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata\n`define rvformal_csr_pmpaddr46_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata\n`define rvformal_csr_pmpaddr46_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr46_wdata\n`define rvformal_csr_pmpaddr46_conn, \\\n  .rvfi_csr_pmpaddr46_rmask (rvfi_csr_pmpaddr46_rmask), \\\n  .rvfi_csr_pmpaddr46_wmask (rvfi_csr_pmpaddr46_wmask), \\\n  .rvfi_csr_pmpaddr46_rdata (rvfi_csr_pmpaddr46_rdata), \\\n  .rvfi_csr_pmpaddr46_wdata (rvfi_csr_pmpaddr46_wdata)\n`define rvformal_csr_pmpaddr46_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr46_rmask (rvfi_csr_pmpaddr46_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr46_wmask (rvfi_csr_pmpaddr46_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr46_rdata (rvfi_csr_pmpaddr46_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr46_wdata (rvfi_csr_pmpaddr46_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr46_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr46_rmask = rvfi_csr_pmpaddr46_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr46_wmask = rvfi_csr_pmpaddr46_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr46_rdata = rvfi_csr_pmpaddr46_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr46_wdata = rvfi_csr_pmpaddr46_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr46_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr46_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr46_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr46_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr46_wdata)\n`else\n`define rvformal_csr_pmpaddr46_wires\n`define rvformal_csr_pmpaddr46_outputs\n`define rvformal_csr_pmpaddr46_inputs\n`define rvformal_csr_pmpaddr46_conn\n`define rvformal_csr_pmpaddr46_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr46_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr46 = 12'h3DE; \\\nlocalparam [11:0] csr_sindex_pmpaddr46 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr46 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR47\n`define rvformal_csr_pmpaddr47_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata;\n`define rvformal_csr_pmpaddr47_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata\n`define rvformal_csr_pmpaddr47_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata\n`define rvformal_csr_pmpaddr47_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata\n`define rvformal_csr_pmpaddr47_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr47_wdata\n`define rvformal_csr_pmpaddr47_conn, \\\n  .rvfi_csr_pmpaddr47_rmask (rvfi_csr_pmpaddr47_rmask), \\\n  .rvfi_csr_pmpaddr47_wmask (rvfi_csr_pmpaddr47_wmask), \\\n  .rvfi_csr_pmpaddr47_rdata (rvfi_csr_pmpaddr47_rdata), \\\n  .rvfi_csr_pmpaddr47_wdata (rvfi_csr_pmpaddr47_wdata)\n`define rvformal_csr_pmpaddr47_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr47_rmask (rvfi_csr_pmpaddr47_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr47_wmask (rvfi_csr_pmpaddr47_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr47_rdata (rvfi_csr_pmpaddr47_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr47_wdata (rvfi_csr_pmpaddr47_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr47_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr47_rmask = rvfi_csr_pmpaddr47_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr47_wmask = rvfi_csr_pmpaddr47_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr47_rdata = rvfi_csr_pmpaddr47_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr47_wdata = rvfi_csr_pmpaddr47_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr47_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr47_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr47_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr47_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr47_wdata)\n`else\n`define rvformal_csr_pmpaddr47_wires\n`define rvformal_csr_pmpaddr47_outputs\n`define rvformal_csr_pmpaddr47_inputs\n`define rvformal_csr_pmpaddr47_conn\n`define rvformal_csr_pmpaddr47_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr47_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr47 = 12'h3DF; \\\nlocalparam [11:0] csr_sindex_pmpaddr47 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr47 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR48\n`define rvformal_csr_pmpaddr48_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata;\n`define rvformal_csr_pmpaddr48_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata\n`define rvformal_csr_pmpaddr48_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata\n`define rvformal_csr_pmpaddr48_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata\n`define rvformal_csr_pmpaddr48_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr48_wdata\n`define rvformal_csr_pmpaddr48_conn, \\\n  .rvfi_csr_pmpaddr48_rmask (rvfi_csr_pmpaddr48_rmask), \\\n  .rvfi_csr_pmpaddr48_wmask (rvfi_csr_pmpaddr48_wmask), \\\n  .rvfi_csr_pmpaddr48_rdata (rvfi_csr_pmpaddr48_rdata), \\\n  .rvfi_csr_pmpaddr48_wdata (rvfi_csr_pmpaddr48_wdata)\n`define rvformal_csr_pmpaddr48_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr48_rmask (rvfi_csr_pmpaddr48_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr48_wmask (rvfi_csr_pmpaddr48_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr48_rdata (rvfi_csr_pmpaddr48_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr48_wdata (rvfi_csr_pmpaddr48_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr48_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr48_rmask = rvfi_csr_pmpaddr48_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr48_wmask = rvfi_csr_pmpaddr48_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr48_rdata = rvfi_csr_pmpaddr48_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr48_wdata = rvfi_csr_pmpaddr48_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr48_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr48_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr48_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr48_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr48_wdata)\n`else\n`define rvformal_csr_pmpaddr48_wires\n`define rvformal_csr_pmpaddr48_outputs\n`define rvformal_csr_pmpaddr48_inputs\n`define rvformal_csr_pmpaddr48_conn\n`define rvformal_csr_pmpaddr48_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr48_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr48 = 12'h3E0; \\\nlocalparam [11:0] csr_sindex_pmpaddr48 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr48 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR49\n`define rvformal_csr_pmpaddr49_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata;\n`define rvformal_csr_pmpaddr49_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata\n`define rvformal_csr_pmpaddr49_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata\n`define rvformal_csr_pmpaddr49_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata\n`define rvformal_csr_pmpaddr49_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr49_wdata\n`define rvformal_csr_pmpaddr49_conn, \\\n  .rvfi_csr_pmpaddr49_rmask (rvfi_csr_pmpaddr49_rmask), \\\n  .rvfi_csr_pmpaddr49_wmask (rvfi_csr_pmpaddr49_wmask), \\\n  .rvfi_csr_pmpaddr49_rdata (rvfi_csr_pmpaddr49_rdata), \\\n  .rvfi_csr_pmpaddr49_wdata (rvfi_csr_pmpaddr49_wdata)\n`define rvformal_csr_pmpaddr49_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr49_rmask (rvfi_csr_pmpaddr49_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr49_wmask (rvfi_csr_pmpaddr49_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr49_rdata (rvfi_csr_pmpaddr49_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr49_wdata (rvfi_csr_pmpaddr49_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr49_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr49_rmask = rvfi_csr_pmpaddr49_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr49_wmask = rvfi_csr_pmpaddr49_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr49_rdata = rvfi_csr_pmpaddr49_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr49_wdata = rvfi_csr_pmpaddr49_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr49_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr49_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr49_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr49_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr49_wdata)\n`else\n`define rvformal_csr_pmpaddr49_wires\n`define rvformal_csr_pmpaddr49_outputs\n`define rvformal_csr_pmpaddr49_inputs\n`define rvformal_csr_pmpaddr49_conn\n`define rvformal_csr_pmpaddr49_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr49_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr49 = 12'h3E1; \\\nlocalparam [11:0] csr_sindex_pmpaddr49 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr49 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR50\n`define rvformal_csr_pmpaddr50_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata;\n`define rvformal_csr_pmpaddr50_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata\n`define rvformal_csr_pmpaddr50_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata\n`define rvformal_csr_pmpaddr50_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata\n`define rvformal_csr_pmpaddr50_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr50_wdata\n`define rvformal_csr_pmpaddr50_conn, \\\n  .rvfi_csr_pmpaddr50_rmask (rvfi_csr_pmpaddr50_rmask), \\\n  .rvfi_csr_pmpaddr50_wmask (rvfi_csr_pmpaddr50_wmask), \\\n  .rvfi_csr_pmpaddr50_rdata (rvfi_csr_pmpaddr50_rdata), \\\n  .rvfi_csr_pmpaddr50_wdata (rvfi_csr_pmpaddr50_wdata)\n`define rvformal_csr_pmpaddr50_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr50_rmask (rvfi_csr_pmpaddr50_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr50_wmask (rvfi_csr_pmpaddr50_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr50_rdata (rvfi_csr_pmpaddr50_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr50_wdata (rvfi_csr_pmpaddr50_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr50_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr50_rmask = rvfi_csr_pmpaddr50_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr50_wmask = rvfi_csr_pmpaddr50_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr50_rdata = rvfi_csr_pmpaddr50_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr50_wdata = rvfi_csr_pmpaddr50_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr50_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr50_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr50_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr50_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr50_wdata)\n`else\n`define rvformal_csr_pmpaddr50_wires\n`define rvformal_csr_pmpaddr50_outputs\n`define rvformal_csr_pmpaddr50_inputs\n`define rvformal_csr_pmpaddr50_conn\n`define rvformal_csr_pmpaddr50_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr50_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr50 = 12'h3E2; \\\nlocalparam [11:0] csr_sindex_pmpaddr50 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr50 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR51\n`define rvformal_csr_pmpaddr51_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata;\n`define rvformal_csr_pmpaddr51_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata\n`define rvformal_csr_pmpaddr51_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata\n`define rvformal_csr_pmpaddr51_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata\n`define rvformal_csr_pmpaddr51_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr51_wdata\n`define rvformal_csr_pmpaddr51_conn, \\\n  .rvfi_csr_pmpaddr51_rmask (rvfi_csr_pmpaddr51_rmask), \\\n  .rvfi_csr_pmpaddr51_wmask (rvfi_csr_pmpaddr51_wmask), \\\n  .rvfi_csr_pmpaddr51_rdata (rvfi_csr_pmpaddr51_rdata), \\\n  .rvfi_csr_pmpaddr51_wdata (rvfi_csr_pmpaddr51_wdata)\n`define rvformal_csr_pmpaddr51_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr51_rmask (rvfi_csr_pmpaddr51_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr51_wmask (rvfi_csr_pmpaddr51_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr51_rdata (rvfi_csr_pmpaddr51_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr51_wdata (rvfi_csr_pmpaddr51_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr51_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr51_rmask = rvfi_csr_pmpaddr51_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr51_wmask = rvfi_csr_pmpaddr51_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr51_rdata = rvfi_csr_pmpaddr51_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr51_wdata = rvfi_csr_pmpaddr51_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr51_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr51_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr51_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr51_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr51_wdata)\n`else\n`define rvformal_csr_pmpaddr51_wires\n`define rvformal_csr_pmpaddr51_outputs\n`define rvformal_csr_pmpaddr51_inputs\n`define rvformal_csr_pmpaddr51_conn\n`define rvformal_csr_pmpaddr51_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr51_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr51 = 12'h3E3; \\\nlocalparam [11:0] csr_sindex_pmpaddr51 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr51 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR52\n`define rvformal_csr_pmpaddr52_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata;\n`define rvformal_csr_pmpaddr52_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata\n`define rvformal_csr_pmpaddr52_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata\n`define rvformal_csr_pmpaddr52_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata\n`define rvformal_csr_pmpaddr52_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr52_wdata\n`define rvformal_csr_pmpaddr52_conn, \\\n  .rvfi_csr_pmpaddr52_rmask (rvfi_csr_pmpaddr52_rmask), \\\n  .rvfi_csr_pmpaddr52_wmask (rvfi_csr_pmpaddr52_wmask), \\\n  .rvfi_csr_pmpaddr52_rdata (rvfi_csr_pmpaddr52_rdata), \\\n  .rvfi_csr_pmpaddr52_wdata (rvfi_csr_pmpaddr52_wdata)\n`define rvformal_csr_pmpaddr52_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr52_rmask (rvfi_csr_pmpaddr52_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr52_wmask (rvfi_csr_pmpaddr52_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr52_rdata (rvfi_csr_pmpaddr52_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr52_wdata (rvfi_csr_pmpaddr52_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr52_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr52_rmask = rvfi_csr_pmpaddr52_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr52_wmask = rvfi_csr_pmpaddr52_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr52_rdata = rvfi_csr_pmpaddr52_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr52_wdata = rvfi_csr_pmpaddr52_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr52_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr52_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr52_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr52_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr52_wdata)\n`else\n`define rvformal_csr_pmpaddr52_wires\n`define rvformal_csr_pmpaddr52_outputs\n`define rvformal_csr_pmpaddr52_inputs\n`define rvformal_csr_pmpaddr52_conn\n`define rvformal_csr_pmpaddr52_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr52_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr52 = 12'h3E4; \\\nlocalparam [11:0] csr_sindex_pmpaddr52 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr52 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR53\n`define rvformal_csr_pmpaddr53_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata;\n`define rvformal_csr_pmpaddr53_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata\n`define rvformal_csr_pmpaddr53_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata\n`define rvformal_csr_pmpaddr53_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata\n`define rvformal_csr_pmpaddr53_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr53_wdata\n`define rvformal_csr_pmpaddr53_conn, \\\n  .rvfi_csr_pmpaddr53_rmask (rvfi_csr_pmpaddr53_rmask), \\\n  .rvfi_csr_pmpaddr53_wmask (rvfi_csr_pmpaddr53_wmask), \\\n  .rvfi_csr_pmpaddr53_rdata (rvfi_csr_pmpaddr53_rdata), \\\n  .rvfi_csr_pmpaddr53_wdata (rvfi_csr_pmpaddr53_wdata)\n`define rvformal_csr_pmpaddr53_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr53_rmask (rvfi_csr_pmpaddr53_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr53_wmask (rvfi_csr_pmpaddr53_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr53_rdata (rvfi_csr_pmpaddr53_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr53_wdata (rvfi_csr_pmpaddr53_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr53_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr53_rmask = rvfi_csr_pmpaddr53_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr53_wmask = rvfi_csr_pmpaddr53_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr53_rdata = rvfi_csr_pmpaddr53_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr53_wdata = rvfi_csr_pmpaddr53_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr53_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr53_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr53_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr53_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr53_wdata)\n`else\n`define rvformal_csr_pmpaddr53_wires\n`define rvformal_csr_pmpaddr53_outputs\n`define rvformal_csr_pmpaddr53_inputs\n`define rvformal_csr_pmpaddr53_conn\n`define rvformal_csr_pmpaddr53_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr53_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr53 = 12'h3E5; \\\nlocalparam [11:0] csr_sindex_pmpaddr53 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr53 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR54\n`define rvformal_csr_pmpaddr54_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata;\n`define rvformal_csr_pmpaddr54_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata\n`define rvformal_csr_pmpaddr54_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata\n`define rvformal_csr_pmpaddr54_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata\n`define rvformal_csr_pmpaddr54_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr54_wdata\n`define rvformal_csr_pmpaddr54_conn, \\\n  .rvfi_csr_pmpaddr54_rmask (rvfi_csr_pmpaddr54_rmask), \\\n  .rvfi_csr_pmpaddr54_wmask (rvfi_csr_pmpaddr54_wmask), \\\n  .rvfi_csr_pmpaddr54_rdata (rvfi_csr_pmpaddr54_rdata), \\\n  .rvfi_csr_pmpaddr54_wdata (rvfi_csr_pmpaddr54_wdata)\n`define rvformal_csr_pmpaddr54_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr54_rmask (rvfi_csr_pmpaddr54_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr54_wmask (rvfi_csr_pmpaddr54_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr54_rdata (rvfi_csr_pmpaddr54_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr54_wdata (rvfi_csr_pmpaddr54_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr54_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr54_rmask = rvfi_csr_pmpaddr54_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr54_wmask = rvfi_csr_pmpaddr54_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr54_rdata = rvfi_csr_pmpaddr54_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr54_wdata = rvfi_csr_pmpaddr54_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr54_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr54_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr54_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr54_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr54_wdata)\n`else\n`define rvformal_csr_pmpaddr54_wires\n`define rvformal_csr_pmpaddr54_outputs\n`define rvformal_csr_pmpaddr54_inputs\n`define rvformal_csr_pmpaddr54_conn\n`define rvformal_csr_pmpaddr54_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr54_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr54 = 12'h3E6; \\\nlocalparam [11:0] csr_sindex_pmpaddr54 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr54 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR55\n`define rvformal_csr_pmpaddr55_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata;\n`define rvformal_csr_pmpaddr55_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata\n`define rvformal_csr_pmpaddr55_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata\n`define rvformal_csr_pmpaddr55_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata\n`define rvformal_csr_pmpaddr55_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr55_wdata\n`define rvformal_csr_pmpaddr55_conn, \\\n  .rvfi_csr_pmpaddr55_rmask (rvfi_csr_pmpaddr55_rmask), \\\n  .rvfi_csr_pmpaddr55_wmask (rvfi_csr_pmpaddr55_wmask), \\\n  .rvfi_csr_pmpaddr55_rdata (rvfi_csr_pmpaddr55_rdata), \\\n  .rvfi_csr_pmpaddr55_wdata (rvfi_csr_pmpaddr55_wdata)\n`define rvformal_csr_pmpaddr55_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr55_rmask (rvfi_csr_pmpaddr55_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr55_wmask (rvfi_csr_pmpaddr55_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr55_rdata (rvfi_csr_pmpaddr55_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr55_wdata (rvfi_csr_pmpaddr55_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr55_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr55_rmask = rvfi_csr_pmpaddr55_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr55_wmask = rvfi_csr_pmpaddr55_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr55_rdata = rvfi_csr_pmpaddr55_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr55_wdata = rvfi_csr_pmpaddr55_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr55_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr55_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr55_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr55_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr55_wdata)\n`else\n`define rvformal_csr_pmpaddr55_wires\n`define rvformal_csr_pmpaddr55_outputs\n`define rvformal_csr_pmpaddr55_inputs\n`define rvformal_csr_pmpaddr55_conn\n`define rvformal_csr_pmpaddr55_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr55_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr55 = 12'h3E7; \\\nlocalparam [11:0] csr_sindex_pmpaddr55 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr55 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR56\n`define rvformal_csr_pmpaddr56_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata;\n`define rvformal_csr_pmpaddr56_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata\n`define rvformal_csr_pmpaddr56_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata\n`define rvformal_csr_pmpaddr56_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata\n`define rvformal_csr_pmpaddr56_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr56_wdata\n`define rvformal_csr_pmpaddr56_conn, \\\n  .rvfi_csr_pmpaddr56_rmask (rvfi_csr_pmpaddr56_rmask), \\\n  .rvfi_csr_pmpaddr56_wmask (rvfi_csr_pmpaddr56_wmask), \\\n  .rvfi_csr_pmpaddr56_rdata (rvfi_csr_pmpaddr56_rdata), \\\n  .rvfi_csr_pmpaddr56_wdata (rvfi_csr_pmpaddr56_wdata)\n`define rvformal_csr_pmpaddr56_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr56_rmask (rvfi_csr_pmpaddr56_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr56_wmask (rvfi_csr_pmpaddr56_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr56_rdata (rvfi_csr_pmpaddr56_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr56_wdata (rvfi_csr_pmpaddr56_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr56_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr56_rmask = rvfi_csr_pmpaddr56_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr56_wmask = rvfi_csr_pmpaddr56_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr56_rdata = rvfi_csr_pmpaddr56_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr56_wdata = rvfi_csr_pmpaddr56_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr56_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr56_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr56_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr56_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr56_wdata)\n`else\n`define rvformal_csr_pmpaddr56_wires\n`define rvformal_csr_pmpaddr56_outputs\n`define rvformal_csr_pmpaddr56_inputs\n`define rvformal_csr_pmpaddr56_conn\n`define rvformal_csr_pmpaddr56_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr56_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr56 = 12'h3E8; \\\nlocalparam [11:0] csr_sindex_pmpaddr56 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr56 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR57\n`define rvformal_csr_pmpaddr57_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata;\n`define rvformal_csr_pmpaddr57_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata\n`define rvformal_csr_pmpaddr57_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata\n`define rvformal_csr_pmpaddr57_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata\n`define rvformal_csr_pmpaddr57_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr57_wdata\n`define rvformal_csr_pmpaddr57_conn, \\\n  .rvfi_csr_pmpaddr57_rmask (rvfi_csr_pmpaddr57_rmask), \\\n  .rvfi_csr_pmpaddr57_wmask (rvfi_csr_pmpaddr57_wmask), \\\n  .rvfi_csr_pmpaddr57_rdata (rvfi_csr_pmpaddr57_rdata), \\\n  .rvfi_csr_pmpaddr57_wdata (rvfi_csr_pmpaddr57_wdata)\n`define rvformal_csr_pmpaddr57_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr57_rmask (rvfi_csr_pmpaddr57_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr57_wmask (rvfi_csr_pmpaddr57_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr57_rdata (rvfi_csr_pmpaddr57_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr57_wdata (rvfi_csr_pmpaddr57_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr57_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr57_rmask = rvfi_csr_pmpaddr57_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr57_wmask = rvfi_csr_pmpaddr57_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr57_rdata = rvfi_csr_pmpaddr57_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr57_wdata = rvfi_csr_pmpaddr57_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr57_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr57_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr57_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr57_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr57_wdata)\n`else\n`define rvformal_csr_pmpaddr57_wires\n`define rvformal_csr_pmpaddr57_outputs\n`define rvformal_csr_pmpaddr57_inputs\n`define rvformal_csr_pmpaddr57_conn\n`define rvformal_csr_pmpaddr57_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr57_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr57 = 12'h3E9; \\\nlocalparam [11:0] csr_sindex_pmpaddr57 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr57 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR58\n`define rvformal_csr_pmpaddr58_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata;\n`define rvformal_csr_pmpaddr58_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata\n`define rvformal_csr_pmpaddr58_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata\n`define rvformal_csr_pmpaddr58_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata\n`define rvformal_csr_pmpaddr58_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr58_wdata\n`define rvformal_csr_pmpaddr58_conn, \\\n  .rvfi_csr_pmpaddr58_rmask (rvfi_csr_pmpaddr58_rmask), \\\n  .rvfi_csr_pmpaddr58_wmask (rvfi_csr_pmpaddr58_wmask), \\\n  .rvfi_csr_pmpaddr58_rdata (rvfi_csr_pmpaddr58_rdata), \\\n  .rvfi_csr_pmpaddr58_wdata (rvfi_csr_pmpaddr58_wdata)\n`define rvformal_csr_pmpaddr58_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr58_rmask (rvfi_csr_pmpaddr58_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr58_wmask (rvfi_csr_pmpaddr58_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr58_rdata (rvfi_csr_pmpaddr58_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr58_wdata (rvfi_csr_pmpaddr58_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr58_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr58_rmask = rvfi_csr_pmpaddr58_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr58_wmask = rvfi_csr_pmpaddr58_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr58_rdata = rvfi_csr_pmpaddr58_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr58_wdata = rvfi_csr_pmpaddr58_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr58_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr58_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr58_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr58_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr58_wdata)\n`else\n`define rvformal_csr_pmpaddr58_wires\n`define rvformal_csr_pmpaddr58_outputs\n`define rvformal_csr_pmpaddr58_inputs\n`define rvformal_csr_pmpaddr58_conn\n`define rvformal_csr_pmpaddr58_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr58_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr58 = 12'h3EA; \\\nlocalparam [11:0] csr_sindex_pmpaddr58 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr58 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR59\n`define rvformal_csr_pmpaddr59_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata;\n`define rvformal_csr_pmpaddr59_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata\n`define rvformal_csr_pmpaddr59_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata\n`define rvformal_csr_pmpaddr59_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata\n`define rvformal_csr_pmpaddr59_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr59_wdata\n`define rvformal_csr_pmpaddr59_conn, \\\n  .rvfi_csr_pmpaddr59_rmask (rvfi_csr_pmpaddr59_rmask), \\\n  .rvfi_csr_pmpaddr59_wmask (rvfi_csr_pmpaddr59_wmask), \\\n  .rvfi_csr_pmpaddr59_rdata (rvfi_csr_pmpaddr59_rdata), \\\n  .rvfi_csr_pmpaddr59_wdata (rvfi_csr_pmpaddr59_wdata)\n`define rvformal_csr_pmpaddr59_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr59_rmask (rvfi_csr_pmpaddr59_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr59_wmask (rvfi_csr_pmpaddr59_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr59_rdata (rvfi_csr_pmpaddr59_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr59_wdata (rvfi_csr_pmpaddr59_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr59_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr59_rmask = rvfi_csr_pmpaddr59_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr59_wmask = rvfi_csr_pmpaddr59_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr59_rdata = rvfi_csr_pmpaddr59_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr59_wdata = rvfi_csr_pmpaddr59_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr59_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr59_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr59_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr59_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr59_wdata)\n`else\n`define rvformal_csr_pmpaddr59_wires\n`define rvformal_csr_pmpaddr59_outputs\n`define rvformal_csr_pmpaddr59_inputs\n`define rvformal_csr_pmpaddr59_conn\n`define rvformal_csr_pmpaddr59_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr59_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr59 = 12'h3EB; \\\nlocalparam [11:0] csr_sindex_pmpaddr59 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr59 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR60\n`define rvformal_csr_pmpaddr60_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata;\n`define rvformal_csr_pmpaddr60_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata\n`define rvformal_csr_pmpaddr60_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata\n`define rvformal_csr_pmpaddr60_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata\n`define rvformal_csr_pmpaddr60_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr60_wdata\n`define rvformal_csr_pmpaddr60_conn, \\\n  .rvfi_csr_pmpaddr60_rmask (rvfi_csr_pmpaddr60_rmask), \\\n  .rvfi_csr_pmpaddr60_wmask (rvfi_csr_pmpaddr60_wmask), \\\n  .rvfi_csr_pmpaddr60_rdata (rvfi_csr_pmpaddr60_rdata), \\\n  .rvfi_csr_pmpaddr60_wdata (rvfi_csr_pmpaddr60_wdata)\n`define rvformal_csr_pmpaddr60_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr60_rmask (rvfi_csr_pmpaddr60_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr60_wmask (rvfi_csr_pmpaddr60_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr60_rdata (rvfi_csr_pmpaddr60_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr60_wdata (rvfi_csr_pmpaddr60_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr60_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr60_rmask = rvfi_csr_pmpaddr60_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr60_wmask = rvfi_csr_pmpaddr60_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr60_rdata = rvfi_csr_pmpaddr60_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr60_wdata = rvfi_csr_pmpaddr60_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr60_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr60_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr60_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr60_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr60_wdata)\n`else\n`define rvformal_csr_pmpaddr60_wires\n`define rvformal_csr_pmpaddr60_outputs\n`define rvformal_csr_pmpaddr60_inputs\n`define rvformal_csr_pmpaddr60_conn\n`define rvformal_csr_pmpaddr60_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr60_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr60 = 12'h3EC; \\\nlocalparam [11:0] csr_sindex_pmpaddr60 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr60 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR61\n`define rvformal_csr_pmpaddr61_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata;\n`define rvformal_csr_pmpaddr61_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata\n`define rvformal_csr_pmpaddr61_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata\n`define rvformal_csr_pmpaddr61_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata\n`define rvformal_csr_pmpaddr61_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr61_wdata\n`define rvformal_csr_pmpaddr61_conn, \\\n  .rvfi_csr_pmpaddr61_rmask (rvfi_csr_pmpaddr61_rmask), \\\n  .rvfi_csr_pmpaddr61_wmask (rvfi_csr_pmpaddr61_wmask), \\\n  .rvfi_csr_pmpaddr61_rdata (rvfi_csr_pmpaddr61_rdata), \\\n  .rvfi_csr_pmpaddr61_wdata (rvfi_csr_pmpaddr61_wdata)\n`define rvformal_csr_pmpaddr61_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr61_rmask (rvfi_csr_pmpaddr61_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr61_wmask (rvfi_csr_pmpaddr61_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr61_rdata (rvfi_csr_pmpaddr61_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr61_wdata (rvfi_csr_pmpaddr61_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr61_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr61_rmask = rvfi_csr_pmpaddr61_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr61_wmask = rvfi_csr_pmpaddr61_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr61_rdata = rvfi_csr_pmpaddr61_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr61_wdata = rvfi_csr_pmpaddr61_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr61_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr61_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr61_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr61_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr61_wdata)\n`else\n`define rvformal_csr_pmpaddr61_wires\n`define rvformal_csr_pmpaddr61_outputs\n`define rvformal_csr_pmpaddr61_inputs\n`define rvformal_csr_pmpaddr61_conn\n`define rvformal_csr_pmpaddr61_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr61_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr61 = 12'h3ED; \\\nlocalparam [11:0] csr_sindex_pmpaddr61 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr61 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR62\n`define rvformal_csr_pmpaddr62_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata;\n`define rvformal_csr_pmpaddr62_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata\n`define rvformal_csr_pmpaddr62_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata\n`define rvformal_csr_pmpaddr62_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata\n`define rvformal_csr_pmpaddr62_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr62_wdata\n`define rvformal_csr_pmpaddr62_conn, \\\n  .rvfi_csr_pmpaddr62_rmask (rvfi_csr_pmpaddr62_rmask), \\\n  .rvfi_csr_pmpaddr62_wmask (rvfi_csr_pmpaddr62_wmask), \\\n  .rvfi_csr_pmpaddr62_rdata (rvfi_csr_pmpaddr62_rdata), \\\n  .rvfi_csr_pmpaddr62_wdata (rvfi_csr_pmpaddr62_wdata)\n`define rvformal_csr_pmpaddr62_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr62_rmask (rvfi_csr_pmpaddr62_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr62_wmask (rvfi_csr_pmpaddr62_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr62_rdata (rvfi_csr_pmpaddr62_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr62_wdata (rvfi_csr_pmpaddr62_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr62_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr62_rmask = rvfi_csr_pmpaddr62_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr62_wmask = rvfi_csr_pmpaddr62_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr62_rdata = rvfi_csr_pmpaddr62_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr62_wdata = rvfi_csr_pmpaddr62_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr62_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr62_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr62_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr62_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr62_wdata)\n`else\n`define rvformal_csr_pmpaddr62_wires\n`define rvformal_csr_pmpaddr62_outputs\n`define rvformal_csr_pmpaddr62_inputs\n`define rvformal_csr_pmpaddr62_conn\n`define rvformal_csr_pmpaddr62_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr62_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr62 = 12'h3EE; \\\nlocalparam [11:0] csr_sindex_pmpaddr62 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr62 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_PMPADDR63\n`define rvformal_csr_pmpaddr63_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata;\n`define rvformal_csr_pmpaddr63_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata\n`define rvformal_csr_pmpaddr63_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata\n`define rvformal_csr_pmpaddr63_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata\n`define rvformal_csr_pmpaddr63_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_pmpaddr63_wdata\n`define rvformal_csr_pmpaddr63_conn, \\\n  .rvfi_csr_pmpaddr63_rmask (rvfi_csr_pmpaddr63_rmask), \\\n  .rvfi_csr_pmpaddr63_wmask (rvfi_csr_pmpaddr63_wmask), \\\n  .rvfi_csr_pmpaddr63_rdata (rvfi_csr_pmpaddr63_rdata), \\\n  .rvfi_csr_pmpaddr63_wdata (rvfi_csr_pmpaddr63_wdata)\n`define rvformal_csr_pmpaddr63_channel_conn(_idx), \\\n  .rvfi_csr_pmpaddr63_rmask (rvfi_csr_pmpaddr63_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr63_wmask (rvfi_csr_pmpaddr63_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr63_rdata (rvfi_csr_pmpaddr63_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_pmpaddr63_wdata (rvfi_csr_pmpaddr63_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_pmpaddr63_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr63_rmask = rvfi_csr_pmpaddr63_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr63_wmask = rvfi_csr_pmpaddr63_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr63_rdata = rvfi_csr_pmpaddr63_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_pmpaddr63_wdata = rvfi_csr_pmpaddr63_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_pmpaddr63_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr63_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr63_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr63_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_pmpaddr63_wdata)\n`else\n`define rvformal_csr_pmpaddr63_wires\n`define rvformal_csr_pmpaddr63_outputs\n`define rvformal_csr_pmpaddr63_inputs\n`define rvformal_csr_pmpaddr63_conn\n`define rvformal_csr_pmpaddr63_channel(_idx)\n`endif\n`define rvformal_csr_pmpaddr63_indices \\\nlocalparam [11:0] csr_mindex_pmpaddr63 = 12'h3EF; \\\nlocalparam [11:0] csr_sindex_pmpaddr63 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_pmpaddr63 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT3\n`define rvformal_csr_mhpmevent3_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata;\n`define rvformal_csr_mhpmevent3_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata\n`define rvformal_csr_mhpmevent3_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata\n`define rvformal_csr_mhpmevent3_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata\n`define rvformal_csr_mhpmevent3_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent3_wdata\n`define rvformal_csr_mhpmevent3_conn, \\\n  .rvfi_csr_mhpmevent3_rmask (rvfi_csr_mhpmevent3_rmask), \\\n  .rvfi_csr_mhpmevent3_wmask (rvfi_csr_mhpmevent3_wmask), \\\n  .rvfi_csr_mhpmevent3_rdata (rvfi_csr_mhpmevent3_rdata), \\\n  .rvfi_csr_mhpmevent3_wdata (rvfi_csr_mhpmevent3_wdata)\n`define rvformal_csr_mhpmevent3_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent3_rmask (rvfi_csr_mhpmevent3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent3_wmask (rvfi_csr_mhpmevent3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent3_rdata (rvfi_csr_mhpmevent3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent3_wdata (rvfi_csr_mhpmevent3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent3_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent3_rmask = rvfi_csr_mhpmevent3_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent3_wmask = rvfi_csr_mhpmevent3_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent3_rdata = rvfi_csr_mhpmevent3_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent3_wdata = rvfi_csr_mhpmevent3_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent3_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent3_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent3_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent3_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent3_wdata)\n`else\n`define rvformal_csr_mhpmevent3_wires\n`define rvformal_csr_mhpmevent3_outputs\n`define rvformal_csr_mhpmevent3_inputs\n`define rvformal_csr_mhpmevent3_conn\n`define rvformal_csr_mhpmevent3_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent3_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent3 = 12'h323; \\\nlocalparam [11:0] csr_sindex_mhpmevent3 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent3 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT4\n`define rvformal_csr_mhpmevent4_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata;\n`define rvformal_csr_mhpmevent4_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata\n`define rvformal_csr_mhpmevent4_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata\n`define rvformal_csr_mhpmevent4_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata\n`define rvformal_csr_mhpmevent4_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent4_wdata\n`define rvformal_csr_mhpmevent4_conn, \\\n  .rvfi_csr_mhpmevent4_rmask (rvfi_csr_mhpmevent4_rmask), \\\n  .rvfi_csr_mhpmevent4_wmask (rvfi_csr_mhpmevent4_wmask), \\\n  .rvfi_csr_mhpmevent4_rdata (rvfi_csr_mhpmevent4_rdata), \\\n  .rvfi_csr_mhpmevent4_wdata (rvfi_csr_mhpmevent4_wdata)\n`define rvformal_csr_mhpmevent4_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent4_rmask (rvfi_csr_mhpmevent4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent4_wmask (rvfi_csr_mhpmevent4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent4_rdata (rvfi_csr_mhpmevent4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent4_wdata (rvfi_csr_mhpmevent4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent4_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent4_rmask = rvfi_csr_mhpmevent4_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent4_wmask = rvfi_csr_mhpmevent4_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent4_rdata = rvfi_csr_mhpmevent4_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent4_wdata = rvfi_csr_mhpmevent4_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent4_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent4_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent4_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent4_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent4_wdata)\n`else\n`define rvformal_csr_mhpmevent4_wires\n`define rvformal_csr_mhpmevent4_outputs\n`define rvformal_csr_mhpmevent4_inputs\n`define rvformal_csr_mhpmevent4_conn\n`define rvformal_csr_mhpmevent4_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent4_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent4 = 12'h324; \\\nlocalparam [11:0] csr_sindex_mhpmevent4 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent4 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT5\n`define rvformal_csr_mhpmevent5_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata;\n`define rvformal_csr_mhpmevent5_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata\n`define rvformal_csr_mhpmevent5_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata\n`define rvformal_csr_mhpmevent5_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata\n`define rvformal_csr_mhpmevent5_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent5_wdata\n`define rvformal_csr_mhpmevent5_conn, \\\n  .rvfi_csr_mhpmevent5_rmask (rvfi_csr_mhpmevent5_rmask), \\\n  .rvfi_csr_mhpmevent5_wmask (rvfi_csr_mhpmevent5_wmask), \\\n  .rvfi_csr_mhpmevent5_rdata (rvfi_csr_mhpmevent5_rdata), \\\n  .rvfi_csr_mhpmevent5_wdata (rvfi_csr_mhpmevent5_wdata)\n`define rvformal_csr_mhpmevent5_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent5_rmask (rvfi_csr_mhpmevent5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent5_wmask (rvfi_csr_mhpmevent5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent5_rdata (rvfi_csr_mhpmevent5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent5_wdata (rvfi_csr_mhpmevent5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent5_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent5_rmask = rvfi_csr_mhpmevent5_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent5_wmask = rvfi_csr_mhpmevent5_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent5_rdata = rvfi_csr_mhpmevent5_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent5_wdata = rvfi_csr_mhpmevent5_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent5_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent5_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent5_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent5_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent5_wdata)\n`else\n`define rvformal_csr_mhpmevent5_wires\n`define rvformal_csr_mhpmevent5_outputs\n`define rvformal_csr_mhpmevent5_inputs\n`define rvformal_csr_mhpmevent5_conn\n`define rvformal_csr_mhpmevent5_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent5_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent5 = 12'h325; \\\nlocalparam [11:0] csr_sindex_mhpmevent5 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent5 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT6\n`define rvformal_csr_mhpmevent6_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata;\n`define rvformal_csr_mhpmevent6_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata\n`define rvformal_csr_mhpmevent6_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata\n`define rvformal_csr_mhpmevent6_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata\n`define rvformal_csr_mhpmevent6_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent6_wdata\n`define rvformal_csr_mhpmevent6_conn, \\\n  .rvfi_csr_mhpmevent6_rmask (rvfi_csr_mhpmevent6_rmask), \\\n  .rvfi_csr_mhpmevent6_wmask (rvfi_csr_mhpmevent6_wmask), \\\n  .rvfi_csr_mhpmevent6_rdata (rvfi_csr_mhpmevent6_rdata), \\\n  .rvfi_csr_mhpmevent6_wdata (rvfi_csr_mhpmevent6_wdata)\n`define rvformal_csr_mhpmevent6_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent6_rmask (rvfi_csr_mhpmevent6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent6_wmask (rvfi_csr_mhpmevent6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent6_rdata (rvfi_csr_mhpmevent6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent6_wdata (rvfi_csr_mhpmevent6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent6_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent6_rmask = rvfi_csr_mhpmevent6_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent6_wmask = rvfi_csr_mhpmevent6_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent6_rdata = rvfi_csr_mhpmevent6_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent6_wdata = rvfi_csr_mhpmevent6_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent6_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent6_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent6_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent6_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent6_wdata)\n`else\n`define rvformal_csr_mhpmevent6_wires\n`define rvformal_csr_mhpmevent6_outputs\n`define rvformal_csr_mhpmevent6_inputs\n`define rvformal_csr_mhpmevent6_conn\n`define rvformal_csr_mhpmevent6_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent6_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent6 = 12'h326; \\\nlocalparam [11:0] csr_sindex_mhpmevent6 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent6 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT7\n`define rvformal_csr_mhpmevent7_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata;\n`define rvformal_csr_mhpmevent7_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata\n`define rvformal_csr_mhpmevent7_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata\n`define rvformal_csr_mhpmevent7_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata\n`define rvformal_csr_mhpmevent7_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent7_wdata\n`define rvformal_csr_mhpmevent7_conn, \\\n  .rvfi_csr_mhpmevent7_rmask (rvfi_csr_mhpmevent7_rmask), \\\n  .rvfi_csr_mhpmevent7_wmask (rvfi_csr_mhpmevent7_wmask), \\\n  .rvfi_csr_mhpmevent7_rdata (rvfi_csr_mhpmevent7_rdata), \\\n  .rvfi_csr_mhpmevent7_wdata (rvfi_csr_mhpmevent7_wdata)\n`define rvformal_csr_mhpmevent7_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent7_rmask (rvfi_csr_mhpmevent7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent7_wmask (rvfi_csr_mhpmevent7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent7_rdata (rvfi_csr_mhpmevent7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent7_wdata (rvfi_csr_mhpmevent7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent7_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent7_rmask = rvfi_csr_mhpmevent7_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent7_wmask = rvfi_csr_mhpmevent7_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent7_rdata = rvfi_csr_mhpmevent7_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent7_wdata = rvfi_csr_mhpmevent7_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent7_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent7_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent7_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent7_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent7_wdata)\n`else\n`define rvformal_csr_mhpmevent7_wires\n`define rvformal_csr_mhpmevent7_outputs\n`define rvformal_csr_mhpmevent7_inputs\n`define rvformal_csr_mhpmevent7_conn\n`define rvformal_csr_mhpmevent7_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent7_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent7 = 12'h327; \\\nlocalparam [11:0] csr_sindex_mhpmevent7 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent7 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT8\n`define rvformal_csr_mhpmevent8_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata;\n`define rvformal_csr_mhpmevent8_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata\n`define rvformal_csr_mhpmevent8_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata\n`define rvformal_csr_mhpmevent8_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata\n`define rvformal_csr_mhpmevent8_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent8_wdata\n`define rvformal_csr_mhpmevent8_conn, \\\n  .rvfi_csr_mhpmevent8_rmask (rvfi_csr_mhpmevent8_rmask), \\\n  .rvfi_csr_mhpmevent8_wmask (rvfi_csr_mhpmevent8_wmask), \\\n  .rvfi_csr_mhpmevent8_rdata (rvfi_csr_mhpmevent8_rdata), \\\n  .rvfi_csr_mhpmevent8_wdata (rvfi_csr_mhpmevent8_wdata)\n`define rvformal_csr_mhpmevent8_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent8_rmask (rvfi_csr_mhpmevent8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent8_wmask (rvfi_csr_mhpmevent8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent8_rdata (rvfi_csr_mhpmevent8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent8_wdata (rvfi_csr_mhpmevent8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent8_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent8_rmask = rvfi_csr_mhpmevent8_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent8_wmask = rvfi_csr_mhpmevent8_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent8_rdata = rvfi_csr_mhpmevent8_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent8_wdata = rvfi_csr_mhpmevent8_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent8_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent8_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent8_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent8_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent8_wdata)\n`else\n`define rvformal_csr_mhpmevent8_wires\n`define rvformal_csr_mhpmevent8_outputs\n`define rvformal_csr_mhpmevent8_inputs\n`define rvformal_csr_mhpmevent8_conn\n`define rvformal_csr_mhpmevent8_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent8_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent8 = 12'h328; \\\nlocalparam [11:0] csr_sindex_mhpmevent8 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent8 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT9\n`define rvformal_csr_mhpmevent9_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata;\n`define rvformal_csr_mhpmevent9_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata\n`define rvformal_csr_mhpmevent9_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata\n`define rvformal_csr_mhpmevent9_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata\n`define rvformal_csr_mhpmevent9_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent9_wdata\n`define rvformal_csr_mhpmevent9_conn, \\\n  .rvfi_csr_mhpmevent9_rmask (rvfi_csr_mhpmevent9_rmask), \\\n  .rvfi_csr_mhpmevent9_wmask (rvfi_csr_mhpmevent9_wmask), \\\n  .rvfi_csr_mhpmevent9_rdata (rvfi_csr_mhpmevent9_rdata), \\\n  .rvfi_csr_mhpmevent9_wdata (rvfi_csr_mhpmevent9_wdata)\n`define rvformal_csr_mhpmevent9_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent9_rmask (rvfi_csr_mhpmevent9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent9_wmask (rvfi_csr_mhpmevent9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent9_rdata (rvfi_csr_mhpmevent9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent9_wdata (rvfi_csr_mhpmevent9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent9_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent9_rmask = rvfi_csr_mhpmevent9_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent9_wmask = rvfi_csr_mhpmevent9_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent9_rdata = rvfi_csr_mhpmevent9_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent9_wdata = rvfi_csr_mhpmevent9_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent9_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent9_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent9_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent9_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent9_wdata)\n`else\n`define rvformal_csr_mhpmevent9_wires\n`define rvformal_csr_mhpmevent9_outputs\n`define rvformal_csr_mhpmevent9_inputs\n`define rvformal_csr_mhpmevent9_conn\n`define rvformal_csr_mhpmevent9_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent9_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent9 = 12'h329; \\\nlocalparam [11:0] csr_sindex_mhpmevent9 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent9 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT10\n`define rvformal_csr_mhpmevent10_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata;\n`define rvformal_csr_mhpmevent10_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata\n`define rvformal_csr_mhpmevent10_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata\n`define rvformal_csr_mhpmevent10_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata\n`define rvformal_csr_mhpmevent10_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent10_wdata\n`define rvformal_csr_mhpmevent10_conn, \\\n  .rvfi_csr_mhpmevent10_rmask (rvfi_csr_mhpmevent10_rmask), \\\n  .rvfi_csr_mhpmevent10_wmask (rvfi_csr_mhpmevent10_wmask), \\\n  .rvfi_csr_mhpmevent10_rdata (rvfi_csr_mhpmevent10_rdata), \\\n  .rvfi_csr_mhpmevent10_wdata (rvfi_csr_mhpmevent10_wdata)\n`define rvformal_csr_mhpmevent10_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent10_rmask (rvfi_csr_mhpmevent10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent10_wmask (rvfi_csr_mhpmevent10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent10_rdata (rvfi_csr_mhpmevent10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent10_wdata (rvfi_csr_mhpmevent10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent10_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent10_rmask = rvfi_csr_mhpmevent10_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent10_wmask = rvfi_csr_mhpmevent10_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent10_rdata = rvfi_csr_mhpmevent10_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent10_wdata = rvfi_csr_mhpmevent10_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent10_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent10_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent10_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent10_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent10_wdata)\n`else\n`define rvformal_csr_mhpmevent10_wires\n`define rvformal_csr_mhpmevent10_outputs\n`define rvformal_csr_mhpmevent10_inputs\n`define rvformal_csr_mhpmevent10_conn\n`define rvformal_csr_mhpmevent10_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent10_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent10 = 12'h32A; \\\nlocalparam [11:0] csr_sindex_mhpmevent10 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent10 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT11\n`define rvformal_csr_mhpmevent11_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata;\n`define rvformal_csr_mhpmevent11_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata\n`define rvformal_csr_mhpmevent11_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata\n`define rvformal_csr_mhpmevent11_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata\n`define rvformal_csr_mhpmevent11_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent11_wdata\n`define rvformal_csr_mhpmevent11_conn, \\\n  .rvfi_csr_mhpmevent11_rmask (rvfi_csr_mhpmevent11_rmask), \\\n  .rvfi_csr_mhpmevent11_wmask (rvfi_csr_mhpmevent11_wmask), \\\n  .rvfi_csr_mhpmevent11_rdata (rvfi_csr_mhpmevent11_rdata), \\\n  .rvfi_csr_mhpmevent11_wdata (rvfi_csr_mhpmevent11_wdata)\n`define rvformal_csr_mhpmevent11_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent11_rmask (rvfi_csr_mhpmevent11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent11_wmask (rvfi_csr_mhpmevent11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent11_rdata (rvfi_csr_mhpmevent11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent11_wdata (rvfi_csr_mhpmevent11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent11_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent11_rmask = rvfi_csr_mhpmevent11_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent11_wmask = rvfi_csr_mhpmevent11_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent11_rdata = rvfi_csr_mhpmevent11_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent11_wdata = rvfi_csr_mhpmevent11_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent11_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent11_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent11_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent11_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent11_wdata)\n`else\n`define rvformal_csr_mhpmevent11_wires\n`define rvformal_csr_mhpmevent11_outputs\n`define rvformal_csr_mhpmevent11_inputs\n`define rvformal_csr_mhpmevent11_conn\n`define rvformal_csr_mhpmevent11_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent11_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent11 = 12'h32B; \\\nlocalparam [11:0] csr_sindex_mhpmevent11 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent11 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT12\n`define rvformal_csr_mhpmevent12_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata;\n`define rvformal_csr_mhpmevent12_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata\n`define rvformal_csr_mhpmevent12_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata\n`define rvformal_csr_mhpmevent12_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata\n`define rvformal_csr_mhpmevent12_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent12_wdata\n`define rvformal_csr_mhpmevent12_conn, \\\n  .rvfi_csr_mhpmevent12_rmask (rvfi_csr_mhpmevent12_rmask), \\\n  .rvfi_csr_mhpmevent12_wmask (rvfi_csr_mhpmevent12_wmask), \\\n  .rvfi_csr_mhpmevent12_rdata (rvfi_csr_mhpmevent12_rdata), \\\n  .rvfi_csr_mhpmevent12_wdata (rvfi_csr_mhpmevent12_wdata)\n`define rvformal_csr_mhpmevent12_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent12_rmask (rvfi_csr_mhpmevent12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent12_wmask (rvfi_csr_mhpmevent12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent12_rdata (rvfi_csr_mhpmevent12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent12_wdata (rvfi_csr_mhpmevent12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent12_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent12_rmask = rvfi_csr_mhpmevent12_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent12_wmask = rvfi_csr_mhpmevent12_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent12_rdata = rvfi_csr_mhpmevent12_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent12_wdata = rvfi_csr_mhpmevent12_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent12_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent12_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent12_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent12_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent12_wdata)\n`else\n`define rvformal_csr_mhpmevent12_wires\n`define rvformal_csr_mhpmevent12_outputs\n`define rvformal_csr_mhpmevent12_inputs\n`define rvformal_csr_mhpmevent12_conn\n`define rvformal_csr_mhpmevent12_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent12_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent12 = 12'h32C; \\\nlocalparam [11:0] csr_sindex_mhpmevent12 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent12 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT13\n`define rvformal_csr_mhpmevent13_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata;\n`define rvformal_csr_mhpmevent13_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata\n`define rvformal_csr_mhpmevent13_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata\n`define rvformal_csr_mhpmevent13_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata\n`define rvformal_csr_mhpmevent13_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent13_wdata\n`define rvformal_csr_mhpmevent13_conn, \\\n  .rvfi_csr_mhpmevent13_rmask (rvfi_csr_mhpmevent13_rmask), \\\n  .rvfi_csr_mhpmevent13_wmask (rvfi_csr_mhpmevent13_wmask), \\\n  .rvfi_csr_mhpmevent13_rdata (rvfi_csr_mhpmevent13_rdata), \\\n  .rvfi_csr_mhpmevent13_wdata (rvfi_csr_mhpmevent13_wdata)\n`define rvformal_csr_mhpmevent13_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent13_rmask (rvfi_csr_mhpmevent13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent13_wmask (rvfi_csr_mhpmevent13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent13_rdata (rvfi_csr_mhpmevent13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent13_wdata (rvfi_csr_mhpmevent13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent13_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent13_rmask = rvfi_csr_mhpmevent13_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent13_wmask = rvfi_csr_mhpmevent13_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent13_rdata = rvfi_csr_mhpmevent13_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent13_wdata = rvfi_csr_mhpmevent13_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent13_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent13_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent13_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent13_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent13_wdata)\n`else\n`define rvformal_csr_mhpmevent13_wires\n`define rvformal_csr_mhpmevent13_outputs\n`define rvformal_csr_mhpmevent13_inputs\n`define rvformal_csr_mhpmevent13_conn\n`define rvformal_csr_mhpmevent13_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent13_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent13 = 12'h32D; \\\nlocalparam [11:0] csr_sindex_mhpmevent13 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent13 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT14\n`define rvformal_csr_mhpmevent14_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata;\n`define rvformal_csr_mhpmevent14_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata\n`define rvformal_csr_mhpmevent14_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata\n`define rvformal_csr_mhpmevent14_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata\n`define rvformal_csr_mhpmevent14_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent14_wdata\n`define rvformal_csr_mhpmevent14_conn, \\\n  .rvfi_csr_mhpmevent14_rmask (rvfi_csr_mhpmevent14_rmask), \\\n  .rvfi_csr_mhpmevent14_wmask (rvfi_csr_mhpmevent14_wmask), \\\n  .rvfi_csr_mhpmevent14_rdata (rvfi_csr_mhpmevent14_rdata), \\\n  .rvfi_csr_mhpmevent14_wdata (rvfi_csr_mhpmevent14_wdata)\n`define rvformal_csr_mhpmevent14_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent14_rmask (rvfi_csr_mhpmevent14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent14_wmask (rvfi_csr_mhpmevent14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent14_rdata (rvfi_csr_mhpmevent14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent14_wdata (rvfi_csr_mhpmevent14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent14_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent14_rmask = rvfi_csr_mhpmevent14_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent14_wmask = rvfi_csr_mhpmevent14_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent14_rdata = rvfi_csr_mhpmevent14_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent14_wdata = rvfi_csr_mhpmevent14_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent14_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent14_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent14_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent14_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent14_wdata)\n`else\n`define rvformal_csr_mhpmevent14_wires\n`define rvformal_csr_mhpmevent14_outputs\n`define rvformal_csr_mhpmevent14_inputs\n`define rvformal_csr_mhpmevent14_conn\n`define rvformal_csr_mhpmevent14_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent14_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent14 = 12'h32E; \\\nlocalparam [11:0] csr_sindex_mhpmevent14 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent14 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT15\n`define rvformal_csr_mhpmevent15_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata;\n`define rvformal_csr_mhpmevent15_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata\n`define rvformal_csr_mhpmevent15_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata\n`define rvformal_csr_mhpmevent15_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata\n`define rvformal_csr_mhpmevent15_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent15_wdata\n`define rvformal_csr_mhpmevent15_conn, \\\n  .rvfi_csr_mhpmevent15_rmask (rvfi_csr_mhpmevent15_rmask), \\\n  .rvfi_csr_mhpmevent15_wmask (rvfi_csr_mhpmevent15_wmask), \\\n  .rvfi_csr_mhpmevent15_rdata (rvfi_csr_mhpmevent15_rdata), \\\n  .rvfi_csr_mhpmevent15_wdata (rvfi_csr_mhpmevent15_wdata)\n`define rvformal_csr_mhpmevent15_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent15_rmask (rvfi_csr_mhpmevent15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent15_wmask (rvfi_csr_mhpmevent15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent15_rdata (rvfi_csr_mhpmevent15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent15_wdata (rvfi_csr_mhpmevent15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent15_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent15_rmask = rvfi_csr_mhpmevent15_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent15_wmask = rvfi_csr_mhpmevent15_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent15_rdata = rvfi_csr_mhpmevent15_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent15_wdata = rvfi_csr_mhpmevent15_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent15_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent15_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent15_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent15_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent15_wdata)\n`else\n`define rvformal_csr_mhpmevent15_wires\n`define rvformal_csr_mhpmevent15_outputs\n`define rvformal_csr_mhpmevent15_inputs\n`define rvformal_csr_mhpmevent15_conn\n`define rvformal_csr_mhpmevent15_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent15_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent15 = 12'h32F; \\\nlocalparam [11:0] csr_sindex_mhpmevent15 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent15 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT16\n`define rvformal_csr_mhpmevent16_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata;\n`define rvformal_csr_mhpmevent16_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata\n`define rvformal_csr_mhpmevent16_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata\n`define rvformal_csr_mhpmevent16_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata\n`define rvformal_csr_mhpmevent16_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent16_wdata\n`define rvformal_csr_mhpmevent16_conn, \\\n  .rvfi_csr_mhpmevent16_rmask (rvfi_csr_mhpmevent16_rmask), \\\n  .rvfi_csr_mhpmevent16_wmask (rvfi_csr_mhpmevent16_wmask), \\\n  .rvfi_csr_mhpmevent16_rdata (rvfi_csr_mhpmevent16_rdata), \\\n  .rvfi_csr_mhpmevent16_wdata (rvfi_csr_mhpmevent16_wdata)\n`define rvformal_csr_mhpmevent16_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent16_rmask (rvfi_csr_mhpmevent16_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent16_wmask (rvfi_csr_mhpmevent16_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent16_rdata (rvfi_csr_mhpmevent16_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent16_wdata (rvfi_csr_mhpmevent16_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent16_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent16_rmask = rvfi_csr_mhpmevent16_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent16_wmask = rvfi_csr_mhpmevent16_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent16_rdata = rvfi_csr_mhpmevent16_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent16_wdata = rvfi_csr_mhpmevent16_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent16_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent16_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent16_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent16_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent16_wdata)\n`else\n`define rvformal_csr_mhpmevent16_wires\n`define rvformal_csr_mhpmevent16_outputs\n`define rvformal_csr_mhpmevent16_inputs\n`define rvformal_csr_mhpmevent16_conn\n`define rvformal_csr_mhpmevent16_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent16_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent16 = 12'h330; \\\nlocalparam [11:0] csr_sindex_mhpmevent16 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent16 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT17\n`define rvformal_csr_mhpmevent17_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata;\n`define rvformal_csr_mhpmevent17_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata\n`define rvformal_csr_mhpmevent17_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata\n`define rvformal_csr_mhpmevent17_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata\n`define rvformal_csr_mhpmevent17_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent17_wdata\n`define rvformal_csr_mhpmevent17_conn, \\\n  .rvfi_csr_mhpmevent17_rmask (rvfi_csr_mhpmevent17_rmask), \\\n  .rvfi_csr_mhpmevent17_wmask (rvfi_csr_mhpmevent17_wmask), \\\n  .rvfi_csr_mhpmevent17_rdata (rvfi_csr_mhpmevent17_rdata), \\\n  .rvfi_csr_mhpmevent17_wdata (rvfi_csr_mhpmevent17_wdata)\n`define rvformal_csr_mhpmevent17_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent17_rmask (rvfi_csr_mhpmevent17_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent17_wmask (rvfi_csr_mhpmevent17_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent17_rdata (rvfi_csr_mhpmevent17_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent17_wdata (rvfi_csr_mhpmevent17_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent17_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent17_rmask = rvfi_csr_mhpmevent17_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent17_wmask = rvfi_csr_mhpmevent17_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent17_rdata = rvfi_csr_mhpmevent17_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent17_wdata = rvfi_csr_mhpmevent17_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent17_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent17_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent17_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent17_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent17_wdata)\n`else\n`define rvformal_csr_mhpmevent17_wires\n`define rvformal_csr_mhpmevent17_outputs\n`define rvformal_csr_mhpmevent17_inputs\n`define rvformal_csr_mhpmevent17_conn\n`define rvformal_csr_mhpmevent17_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent17_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent17 = 12'h331; \\\nlocalparam [11:0] csr_sindex_mhpmevent17 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent17 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT18\n`define rvformal_csr_mhpmevent18_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata;\n`define rvformal_csr_mhpmevent18_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata\n`define rvformal_csr_mhpmevent18_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata\n`define rvformal_csr_mhpmevent18_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata\n`define rvformal_csr_mhpmevent18_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent18_wdata\n`define rvformal_csr_mhpmevent18_conn, \\\n  .rvfi_csr_mhpmevent18_rmask (rvfi_csr_mhpmevent18_rmask), \\\n  .rvfi_csr_mhpmevent18_wmask (rvfi_csr_mhpmevent18_wmask), \\\n  .rvfi_csr_mhpmevent18_rdata (rvfi_csr_mhpmevent18_rdata), \\\n  .rvfi_csr_mhpmevent18_wdata (rvfi_csr_mhpmevent18_wdata)\n`define rvformal_csr_mhpmevent18_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent18_rmask (rvfi_csr_mhpmevent18_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent18_wmask (rvfi_csr_mhpmevent18_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent18_rdata (rvfi_csr_mhpmevent18_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent18_wdata (rvfi_csr_mhpmevent18_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent18_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent18_rmask = rvfi_csr_mhpmevent18_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent18_wmask = rvfi_csr_mhpmevent18_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent18_rdata = rvfi_csr_mhpmevent18_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent18_wdata = rvfi_csr_mhpmevent18_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent18_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent18_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent18_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent18_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent18_wdata)\n`else\n`define rvformal_csr_mhpmevent18_wires\n`define rvformal_csr_mhpmevent18_outputs\n`define rvformal_csr_mhpmevent18_inputs\n`define rvformal_csr_mhpmevent18_conn\n`define rvformal_csr_mhpmevent18_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent18_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent18 = 12'h332; \\\nlocalparam [11:0] csr_sindex_mhpmevent18 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent18 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT19\n`define rvformal_csr_mhpmevent19_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata;\n`define rvformal_csr_mhpmevent19_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata\n`define rvformal_csr_mhpmevent19_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata\n`define rvformal_csr_mhpmevent19_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata\n`define rvformal_csr_mhpmevent19_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent19_wdata\n`define rvformal_csr_mhpmevent19_conn, \\\n  .rvfi_csr_mhpmevent19_rmask (rvfi_csr_mhpmevent19_rmask), \\\n  .rvfi_csr_mhpmevent19_wmask (rvfi_csr_mhpmevent19_wmask), \\\n  .rvfi_csr_mhpmevent19_rdata (rvfi_csr_mhpmevent19_rdata), \\\n  .rvfi_csr_mhpmevent19_wdata (rvfi_csr_mhpmevent19_wdata)\n`define rvformal_csr_mhpmevent19_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent19_rmask (rvfi_csr_mhpmevent19_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent19_wmask (rvfi_csr_mhpmevent19_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent19_rdata (rvfi_csr_mhpmevent19_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent19_wdata (rvfi_csr_mhpmevent19_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent19_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent19_rmask = rvfi_csr_mhpmevent19_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent19_wmask = rvfi_csr_mhpmevent19_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent19_rdata = rvfi_csr_mhpmevent19_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent19_wdata = rvfi_csr_mhpmevent19_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent19_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent19_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent19_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent19_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent19_wdata)\n`else\n`define rvformal_csr_mhpmevent19_wires\n`define rvformal_csr_mhpmevent19_outputs\n`define rvformal_csr_mhpmevent19_inputs\n`define rvformal_csr_mhpmevent19_conn\n`define rvformal_csr_mhpmevent19_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent19_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent19 = 12'h333; \\\nlocalparam [11:0] csr_sindex_mhpmevent19 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent19 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT20\n`define rvformal_csr_mhpmevent20_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata;\n`define rvformal_csr_mhpmevent20_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata\n`define rvformal_csr_mhpmevent20_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata\n`define rvformal_csr_mhpmevent20_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata\n`define rvformal_csr_mhpmevent20_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent20_wdata\n`define rvformal_csr_mhpmevent20_conn, \\\n  .rvfi_csr_mhpmevent20_rmask (rvfi_csr_mhpmevent20_rmask), \\\n  .rvfi_csr_mhpmevent20_wmask (rvfi_csr_mhpmevent20_wmask), \\\n  .rvfi_csr_mhpmevent20_rdata (rvfi_csr_mhpmevent20_rdata), \\\n  .rvfi_csr_mhpmevent20_wdata (rvfi_csr_mhpmevent20_wdata)\n`define rvformal_csr_mhpmevent20_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent20_rmask (rvfi_csr_mhpmevent20_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent20_wmask (rvfi_csr_mhpmevent20_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent20_rdata (rvfi_csr_mhpmevent20_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent20_wdata (rvfi_csr_mhpmevent20_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent20_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent20_rmask = rvfi_csr_mhpmevent20_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent20_wmask = rvfi_csr_mhpmevent20_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent20_rdata = rvfi_csr_mhpmevent20_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent20_wdata = rvfi_csr_mhpmevent20_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent20_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent20_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent20_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent20_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent20_wdata)\n`else\n`define rvformal_csr_mhpmevent20_wires\n`define rvformal_csr_mhpmevent20_outputs\n`define rvformal_csr_mhpmevent20_inputs\n`define rvformal_csr_mhpmevent20_conn\n`define rvformal_csr_mhpmevent20_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent20_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent20 = 12'h334; \\\nlocalparam [11:0] csr_sindex_mhpmevent20 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent20 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT21\n`define rvformal_csr_mhpmevent21_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata;\n`define rvformal_csr_mhpmevent21_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata\n`define rvformal_csr_mhpmevent21_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata\n`define rvformal_csr_mhpmevent21_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata\n`define rvformal_csr_mhpmevent21_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent21_wdata\n`define rvformal_csr_mhpmevent21_conn, \\\n  .rvfi_csr_mhpmevent21_rmask (rvfi_csr_mhpmevent21_rmask), \\\n  .rvfi_csr_mhpmevent21_wmask (rvfi_csr_mhpmevent21_wmask), \\\n  .rvfi_csr_mhpmevent21_rdata (rvfi_csr_mhpmevent21_rdata), \\\n  .rvfi_csr_mhpmevent21_wdata (rvfi_csr_mhpmevent21_wdata)\n`define rvformal_csr_mhpmevent21_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent21_rmask (rvfi_csr_mhpmevent21_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent21_wmask (rvfi_csr_mhpmevent21_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent21_rdata (rvfi_csr_mhpmevent21_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent21_wdata (rvfi_csr_mhpmevent21_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent21_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent21_rmask = rvfi_csr_mhpmevent21_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent21_wmask = rvfi_csr_mhpmevent21_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent21_rdata = rvfi_csr_mhpmevent21_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent21_wdata = rvfi_csr_mhpmevent21_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent21_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent21_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent21_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent21_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent21_wdata)\n`else\n`define rvformal_csr_mhpmevent21_wires\n`define rvformal_csr_mhpmevent21_outputs\n`define rvformal_csr_mhpmevent21_inputs\n`define rvformal_csr_mhpmevent21_conn\n`define rvformal_csr_mhpmevent21_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent21_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent21 = 12'h335; \\\nlocalparam [11:0] csr_sindex_mhpmevent21 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent21 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT22\n`define rvformal_csr_mhpmevent22_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata;\n`define rvformal_csr_mhpmevent22_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata\n`define rvformal_csr_mhpmevent22_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata\n`define rvformal_csr_mhpmevent22_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata\n`define rvformal_csr_mhpmevent22_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent22_wdata\n`define rvformal_csr_mhpmevent22_conn, \\\n  .rvfi_csr_mhpmevent22_rmask (rvfi_csr_mhpmevent22_rmask), \\\n  .rvfi_csr_mhpmevent22_wmask (rvfi_csr_mhpmevent22_wmask), \\\n  .rvfi_csr_mhpmevent22_rdata (rvfi_csr_mhpmevent22_rdata), \\\n  .rvfi_csr_mhpmevent22_wdata (rvfi_csr_mhpmevent22_wdata)\n`define rvformal_csr_mhpmevent22_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent22_rmask (rvfi_csr_mhpmevent22_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent22_wmask (rvfi_csr_mhpmevent22_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent22_rdata (rvfi_csr_mhpmevent22_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent22_wdata (rvfi_csr_mhpmevent22_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent22_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent22_rmask = rvfi_csr_mhpmevent22_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent22_wmask = rvfi_csr_mhpmevent22_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent22_rdata = rvfi_csr_mhpmevent22_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent22_wdata = rvfi_csr_mhpmevent22_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent22_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent22_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent22_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent22_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent22_wdata)\n`else\n`define rvformal_csr_mhpmevent22_wires\n`define rvformal_csr_mhpmevent22_outputs\n`define rvformal_csr_mhpmevent22_inputs\n`define rvformal_csr_mhpmevent22_conn\n`define rvformal_csr_mhpmevent22_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent22_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent22 = 12'h336; \\\nlocalparam [11:0] csr_sindex_mhpmevent22 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent22 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT23\n`define rvformal_csr_mhpmevent23_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata;\n`define rvformal_csr_mhpmevent23_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata\n`define rvformal_csr_mhpmevent23_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata\n`define rvformal_csr_mhpmevent23_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata\n`define rvformal_csr_mhpmevent23_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent23_wdata\n`define rvformal_csr_mhpmevent23_conn, \\\n  .rvfi_csr_mhpmevent23_rmask (rvfi_csr_mhpmevent23_rmask), \\\n  .rvfi_csr_mhpmevent23_wmask (rvfi_csr_mhpmevent23_wmask), \\\n  .rvfi_csr_mhpmevent23_rdata (rvfi_csr_mhpmevent23_rdata), \\\n  .rvfi_csr_mhpmevent23_wdata (rvfi_csr_mhpmevent23_wdata)\n`define rvformal_csr_mhpmevent23_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent23_rmask (rvfi_csr_mhpmevent23_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent23_wmask (rvfi_csr_mhpmevent23_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent23_rdata (rvfi_csr_mhpmevent23_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent23_wdata (rvfi_csr_mhpmevent23_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent23_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent23_rmask = rvfi_csr_mhpmevent23_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent23_wmask = rvfi_csr_mhpmevent23_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent23_rdata = rvfi_csr_mhpmevent23_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent23_wdata = rvfi_csr_mhpmevent23_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent23_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent23_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent23_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent23_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent23_wdata)\n`else\n`define rvformal_csr_mhpmevent23_wires\n`define rvformal_csr_mhpmevent23_outputs\n`define rvformal_csr_mhpmevent23_inputs\n`define rvformal_csr_mhpmevent23_conn\n`define rvformal_csr_mhpmevent23_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent23_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent23 = 12'h337; \\\nlocalparam [11:0] csr_sindex_mhpmevent23 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent23 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT24\n`define rvformal_csr_mhpmevent24_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata;\n`define rvformal_csr_mhpmevent24_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata\n`define rvformal_csr_mhpmevent24_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata\n`define rvformal_csr_mhpmevent24_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata\n`define rvformal_csr_mhpmevent24_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent24_wdata\n`define rvformal_csr_mhpmevent24_conn, \\\n  .rvfi_csr_mhpmevent24_rmask (rvfi_csr_mhpmevent24_rmask), \\\n  .rvfi_csr_mhpmevent24_wmask (rvfi_csr_mhpmevent24_wmask), \\\n  .rvfi_csr_mhpmevent24_rdata (rvfi_csr_mhpmevent24_rdata), \\\n  .rvfi_csr_mhpmevent24_wdata (rvfi_csr_mhpmevent24_wdata)\n`define rvformal_csr_mhpmevent24_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent24_rmask (rvfi_csr_mhpmevent24_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent24_wmask (rvfi_csr_mhpmevent24_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent24_rdata (rvfi_csr_mhpmevent24_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent24_wdata (rvfi_csr_mhpmevent24_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent24_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent24_rmask = rvfi_csr_mhpmevent24_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent24_wmask = rvfi_csr_mhpmevent24_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent24_rdata = rvfi_csr_mhpmevent24_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent24_wdata = rvfi_csr_mhpmevent24_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent24_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent24_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent24_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent24_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent24_wdata)\n`else\n`define rvformal_csr_mhpmevent24_wires\n`define rvformal_csr_mhpmevent24_outputs\n`define rvformal_csr_mhpmevent24_inputs\n`define rvformal_csr_mhpmevent24_conn\n`define rvformal_csr_mhpmevent24_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent24_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent24 = 12'h338; \\\nlocalparam [11:0] csr_sindex_mhpmevent24 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent24 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT25\n`define rvformal_csr_mhpmevent25_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata;\n`define rvformal_csr_mhpmevent25_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata\n`define rvformal_csr_mhpmevent25_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata\n`define rvformal_csr_mhpmevent25_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata\n`define rvformal_csr_mhpmevent25_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent25_wdata\n`define rvformal_csr_mhpmevent25_conn, \\\n  .rvfi_csr_mhpmevent25_rmask (rvfi_csr_mhpmevent25_rmask), \\\n  .rvfi_csr_mhpmevent25_wmask (rvfi_csr_mhpmevent25_wmask), \\\n  .rvfi_csr_mhpmevent25_rdata (rvfi_csr_mhpmevent25_rdata), \\\n  .rvfi_csr_mhpmevent25_wdata (rvfi_csr_mhpmevent25_wdata)\n`define rvformal_csr_mhpmevent25_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent25_rmask (rvfi_csr_mhpmevent25_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent25_wmask (rvfi_csr_mhpmevent25_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent25_rdata (rvfi_csr_mhpmevent25_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent25_wdata (rvfi_csr_mhpmevent25_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent25_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent25_rmask = rvfi_csr_mhpmevent25_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent25_wmask = rvfi_csr_mhpmevent25_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent25_rdata = rvfi_csr_mhpmevent25_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent25_wdata = rvfi_csr_mhpmevent25_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent25_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent25_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent25_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent25_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent25_wdata)\n`else\n`define rvformal_csr_mhpmevent25_wires\n`define rvformal_csr_mhpmevent25_outputs\n`define rvformal_csr_mhpmevent25_inputs\n`define rvformal_csr_mhpmevent25_conn\n`define rvformal_csr_mhpmevent25_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent25_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent25 = 12'h339; \\\nlocalparam [11:0] csr_sindex_mhpmevent25 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent25 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT26\n`define rvformal_csr_mhpmevent26_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata;\n`define rvformal_csr_mhpmevent26_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata\n`define rvformal_csr_mhpmevent26_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata\n`define rvformal_csr_mhpmevent26_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata\n`define rvformal_csr_mhpmevent26_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent26_wdata\n`define rvformal_csr_mhpmevent26_conn, \\\n  .rvfi_csr_mhpmevent26_rmask (rvfi_csr_mhpmevent26_rmask), \\\n  .rvfi_csr_mhpmevent26_wmask (rvfi_csr_mhpmevent26_wmask), \\\n  .rvfi_csr_mhpmevent26_rdata (rvfi_csr_mhpmevent26_rdata), \\\n  .rvfi_csr_mhpmevent26_wdata (rvfi_csr_mhpmevent26_wdata)\n`define rvformal_csr_mhpmevent26_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent26_rmask (rvfi_csr_mhpmevent26_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent26_wmask (rvfi_csr_mhpmevent26_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent26_rdata (rvfi_csr_mhpmevent26_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent26_wdata (rvfi_csr_mhpmevent26_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent26_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent26_rmask = rvfi_csr_mhpmevent26_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent26_wmask = rvfi_csr_mhpmevent26_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent26_rdata = rvfi_csr_mhpmevent26_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent26_wdata = rvfi_csr_mhpmevent26_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent26_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent26_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent26_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent26_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent26_wdata)\n`else\n`define rvformal_csr_mhpmevent26_wires\n`define rvformal_csr_mhpmevent26_outputs\n`define rvformal_csr_mhpmevent26_inputs\n`define rvformal_csr_mhpmevent26_conn\n`define rvformal_csr_mhpmevent26_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent26_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent26 = 12'h33A; \\\nlocalparam [11:0] csr_sindex_mhpmevent26 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent26 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT27\n`define rvformal_csr_mhpmevent27_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata;\n`define rvformal_csr_mhpmevent27_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata\n`define rvformal_csr_mhpmevent27_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata\n`define rvformal_csr_mhpmevent27_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata\n`define rvformal_csr_mhpmevent27_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent27_wdata\n`define rvformal_csr_mhpmevent27_conn, \\\n  .rvfi_csr_mhpmevent27_rmask (rvfi_csr_mhpmevent27_rmask), \\\n  .rvfi_csr_mhpmevent27_wmask (rvfi_csr_mhpmevent27_wmask), \\\n  .rvfi_csr_mhpmevent27_rdata (rvfi_csr_mhpmevent27_rdata), \\\n  .rvfi_csr_mhpmevent27_wdata (rvfi_csr_mhpmevent27_wdata)\n`define rvformal_csr_mhpmevent27_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent27_rmask (rvfi_csr_mhpmevent27_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent27_wmask (rvfi_csr_mhpmevent27_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent27_rdata (rvfi_csr_mhpmevent27_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent27_wdata (rvfi_csr_mhpmevent27_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent27_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent27_rmask = rvfi_csr_mhpmevent27_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent27_wmask = rvfi_csr_mhpmevent27_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent27_rdata = rvfi_csr_mhpmevent27_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent27_wdata = rvfi_csr_mhpmevent27_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent27_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent27_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent27_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent27_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent27_wdata)\n`else\n`define rvformal_csr_mhpmevent27_wires\n`define rvformal_csr_mhpmevent27_outputs\n`define rvformal_csr_mhpmevent27_inputs\n`define rvformal_csr_mhpmevent27_conn\n`define rvformal_csr_mhpmevent27_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent27_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent27 = 12'h33B; \\\nlocalparam [11:0] csr_sindex_mhpmevent27 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent27 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT28\n`define rvformal_csr_mhpmevent28_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata;\n`define rvformal_csr_mhpmevent28_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata\n`define rvformal_csr_mhpmevent28_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata\n`define rvformal_csr_mhpmevent28_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata\n`define rvformal_csr_mhpmevent28_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent28_wdata\n`define rvformal_csr_mhpmevent28_conn, \\\n  .rvfi_csr_mhpmevent28_rmask (rvfi_csr_mhpmevent28_rmask), \\\n  .rvfi_csr_mhpmevent28_wmask (rvfi_csr_mhpmevent28_wmask), \\\n  .rvfi_csr_mhpmevent28_rdata (rvfi_csr_mhpmevent28_rdata), \\\n  .rvfi_csr_mhpmevent28_wdata (rvfi_csr_mhpmevent28_wdata)\n`define rvformal_csr_mhpmevent28_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent28_rmask (rvfi_csr_mhpmevent28_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent28_wmask (rvfi_csr_mhpmevent28_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent28_rdata (rvfi_csr_mhpmevent28_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent28_wdata (rvfi_csr_mhpmevent28_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent28_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent28_rmask = rvfi_csr_mhpmevent28_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent28_wmask = rvfi_csr_mhpmevent28_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent28_rdata = rvfi_csr_mhpmevent28_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent28_wdata = rvfi_csr_mhpmevent28_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent28_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent28_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent28_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent28_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent28_wdata)\n`else\n`define rvformal_csr_mhpmevent28_wires\n`define rvformal_csr_mhpmevent28_outputs\n`define rvformal_csr_mhpmevent28_inputs\n`define rvformal_csr_mhpmevent28_conn\n`define rvformal_csr_mhpmevent28_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent28_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent28 = 12'h33C; \\\nlocalparam [11:0] csr_sindex_mhpmevent28 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent28 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT29\n`define rvformal_csr_mhpmevent29_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata;\n`define rvformal_csr_mhpmevent29_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata\n`define rvformal_csr_mhpmevent29_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata\n`define rvformal_csr_mhpmevent29_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata\n`define rvformal_csr_mhpmevent29_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent29_wdata\n`define rvformal_csr_mhpmevent29_conn, \\\n  .rvfi_csr_mhpmevent29_rmask (rvfi_csr_mhpmevent29_rmask), \\\n  .rvfi_csr_mhpmevent29_wmask (rvfi_csr_mhpmevent29_wmask), \\\n  .rvfi_csr_mhpmevent29_rdata (rvfi_csr_mhpmevent29_rdata), \\\n  .rvfi_csr_mhpmevent29_wdata (rvfi_csr_mhpmevent29_wdata)\n`define rvformal_csr_mhpmevent29_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent29_rmask (rvfi_csr_mhpmevent29_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent29_wmask (rvfi_csr_mhpmevent29_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent29_rdata (rvfi_csr_mhpmevent29_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent29_wdata (rvfi_csr_mhpmevent29_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent29_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent29_rmask = rvfi_csr_mhpmevent29_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent29_wmask = rvfi_csr_mhpmevent29_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent29_rdata = rvfi_csr_mhpmevent29_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent29_wdata = rvfi_csr_mhpmevent29_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent29_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent29_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent29_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent29_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent29_wdata)\n`else\n`define rvformal_csr_mhpmevent29_wires\n`define rvformal_csr_mhpmevent29_outputs\n`define rvformal_csr_mhpmevent29_inputs\n`define rvformal_csr_mhpmevent29_conn\n`define rvformal_csr_mhpmevent29_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent29_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent29 = 12'h33D; \\\nlocalparam [11:0] csr_sindex_mhpmevent29 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent29 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT30\n`define rvformal_csr_mhpmevent30_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata;\n`define rvformal_csr_mhpmevent30_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata\n`define rvformal_csr_mhpmevent30_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata\n`define rvformal_csr_mhpmevent30_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata\n`define rvformal_csr_mhpmevent30_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent30_wdata\n`define rvformal_csr_mhpmevent30_conn, \\\n  .rvfi_csr_mhpmevent30_rmask (rvfi_csr_mhpmevent30_rmask), \\\n  .rvfi_csr_mhpmevent30_wmask (rvfi_csr_mhpmevent30_wmask), \\\n  .rvfi_csr_mhpmevent30_rdata (rvfi_csr_mhpmevent30_rdata), \\\n  .rvfi_csr_mhpmevent30_wdata (rvfi_csr_mhpmevent30_wdata)\n`define rvformal_csr_mhpmevent30_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent30_rmask (rvfi_csr_mhpmevent30_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent30_wmask (rvfi_csr_mhpmevent30_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent30_rdata (rvfi_csr_mhpmevent30_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent30_wdata (rvfi_csr_mhpmevent30_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent30_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent30_rmask = rvfi_csr_mhpmevent30_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent30_wmask = rvfi_csr_mhpmevent30_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent30_rdata = rvfi_csr_mhpmevent30_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent30_wdata = rvfi_csr_mhpmevent30_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent30_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent30_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent30_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent30_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent30_wdata)\n`else\n`define rvformal_csr_mhpmevent30_wires\n`define rvformal_csr_mhpmevent30_outputs\n`define rvformal_csr_mhpmevent30_inputs\n`define rvformal_csr_mhpmevent30_conn\n`define rvformal_csr_mhpmevent30_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent30_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent30 = 12'h33E; \\\nlocalparam [11:0] csr_sindex_mhpmevent30 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent30 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMEVENT31\n`define rvformal_csr_mhpmevent31_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata;\n`define rvformal_csr_mhpmevent31_outputs, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata\n`define rvformal_csr_mhpmevent31_channel_outputs, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata, \\\n  output [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata\n`define rvformal_csr_mhpmevent31_inputs, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata\n`define rvformal_csr_mhpmevent31_channel_inputs, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wmask, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_rdata, \\\n  input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_mhpmevent31_wdata\n`define rvformal_csr_mhpmevent31_conn, \\\n  .rvfi_csr_mhpmevent31_rmask (rvfi_csr_mhpmevent31_rmask), \\\n  .rvfi_csr_mhpmevent31_wmask (rvfi_csr_mhpmevent31_wmask), \\\n  .rvfi_csr_mhpmevent31_rdata (rvfi_csr_mhpmevent31_rdata), \\\n  .rvfi_csr_mhpmevent31_wdata (rvfi_csr_mhpmevent31_wdata)\n`define rvformal_csr_mhpmevent31_channel_conn(_idx), \\\n  .rvfi_csr_mhpmevent31_rmask (rvfi_csr_mhpmevent31_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent31_wmask (rvfi_csr_mhpmevent31_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent31_rdata (rvfi_csr_mhpmevent31_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]), \\\n  .rvfi_csr_mhpmevent31_wdata (rvfi_csr_mhpmevent31_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN])\n`define rvformal_csr_mhpmevent31_channel(_idx) \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent31_rmask = rvfi_csr_mhpmevent31_rmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent31_wmask = rvfi_csr_mhpmevent31_wmask [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent31_rdata = rvfi_csr_mhpmevent31_rdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN]; \\\n  wire [`RISCV_FORMAL_XLEN - 1 : 0] csr_mhpmevent31_wdata = rvfi_csr_mhpmevent31_wdata [(_idx)*(`RISCV_FORMAL_XLEN) +: `RISCV_FORMAL_XLEN];\n`define rvformal_csr_mhpmevent31_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent31_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent31_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent31_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN, csr_mhpmevent31_wdata)\n`else\n`define rvformal_csr_mhpmevent31_wires\n`define rvformal_csr_mhpmevent31_outputs\n`define rvformal_csr_mhpmevent31_inputs\n`define rvformal_csr_mhpmevent31_conn\n`define rvformal_csr_mhpmevent31_channel(_idx)\n`endif\n`define rvformal_csr_mhpmevent31_indices \\\nlocalparam [11:0] csr_mindex_mhpmevent31 = 12'h33F; \\\nlocalparam [11:0] csr_sindex_mhpmevent31 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmevent31 = 12'hFFF; \\\n\n`ifdef RISCV_FORMAL_CSR_MCYCLE\n`define rvformal_csr_mcycle_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wdata;\n`define rvformal_csr_mcycle_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wdata\n`define rvformal_csr_mcycle_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mcycle_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mcycle_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mcycle_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mcycle_wdata\n`define rvformal_csr_mcycle_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mcycle_wdata\n`define rvformal_csr_mcycle_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mcycle_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mcycle_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mcycle_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mcycle_wdata\n`define rvformal_csr_mcycle_conn, \\\n  .rvfi_csr_mcycle_rmask (rvfi_csr_mcycle_rmask), \\\n  .rvfi_csr_mcycle_wmask (rvfi_csr_mcycle_wmask), \\\n  .rvfi_csr_mcycle_rdata (rvfi_csr_mcycle_rdata), \\\n  .rvfi_csr_mcycle_wdata (rvfi_csr_mcycle_wdata)\n`define rvformal_csr_mcycle_channel_conn(_idx), \\\n  .rvfi_csr_mcycle_rmask (rvfi_csr_mcycle_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mcycle_wmask (rvfi_csr_mcycle_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mcycle_rdata (rvfi_csr_mcycle_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mcycle_wdata (rvfi_csr_mcycle_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mcycle_conn32, \\\n  .rvfi_csr_mcycle_rmask  (rvfi_csr_mcycle_rmask[31: 0]), \\\n  .rvfi_csr_mcycle_wmask  (rvfi_csr_mcycle_wmask[31: 0]), \\\n  .rvfi_csr_mcycle_rdata  (rvfi_csr_mcycle_rdata[31: 0]), \\\n  .rvfi_csr_mcycle_wdata  (rvfi_csr_mcycle_wdata[31: 0]), \\\n  .rvfi_csr_mcycleh_rmask (rvfi_csr_mcycle_rmask[63:32]), \\\n  .rvfi_csr_mcycleh_wmask (rvfi_csr_mcycle_wmask[63:32]), \\\n  .rvfi_csr_mcycleh_rdata (rvfi_csr_mcycle_rdata[63:32]), \\\n  .rvfi_csr_mcycleh_wdata (rvfi_csr_mcycle_wdata[63:32])\n`define rvformal_csr_mcycle_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mcycle_rmask = rvfi_csr_mcycle_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mcycle_wmask = rvfi_csr_mcycle_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mcycle_rdata = rvfi_csr_mcycle_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mcycle_wdata = rvfi_csr_mcycle_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mcycle_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mcycle_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mcycle_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mcycle_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mcycle_wdata)\n`else\n`define rvformal_csr_mcycle_wires\n`define rvformal_csr_mcycle_outputs\n`define rvformal_csr_mcycle_inputs\n`define rvformal_csr_mcycle_conn\n`define rvformal_csr_mcycle_conn32\n`define rvformal_csr_mcycle_channel(_idx)\n`endif\n`define rvformal_csr_mcycle_indices \\\nlocalparam [11:0] csr_mindex_mcycle = 12'hB00; \\\nlocalparam [11:0] csr_sindex_mcycle = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mcycle = 12'hC00; \\\nlocalparam [11:0] csr_mindex_mcycleh = 12'hB80; \\\nlocalparam [11:0] csr_sindex_mcycleh = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mcycleh = 12'hC80; \\\n\n`ifdef RISCV_FORMAL_CSR_TIME\n`define rvformal_csr_time_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wdata;\n`define rvformal_csr_time_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wdata\n`define rvformal_csr_time_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_time_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_time_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_time_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_time_wdata\n`define rvformal_csr_time_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_time_wdata\n`define rvformal_csr_time_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_time_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_time_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_time_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_time_wdata\n`define rvformal_csr_time_conn, \\\n  .rvfi_csr_time_rmask (rvfi_csr_time_rmask), \\\n  .rvfi_csr_time_wmask (rvfi_csr_time_wmask), \\\n  .rvfi_csr_time_rdata (rvfi_csr_time_rdata), \\\n  .rvfi_csr_time_wdata (rvfi_csr_time_wdata)\n`define rvformal_csr_time_channel_conn(_idx), \\\n  .rvfi_csr_time_rmask (rvfi_csr_time_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_time_wmask (rvfi_csr_time_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_time_rdata (rvfi_csr_time_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_time_wdata (rvfi_csr_time_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_time_conn32, \\\n  .rvfi_csr_time_rmask  (rvfi_csr_time_rmask[31: 0]), \\\n  .rvfi_csr_time_wmask  (rvfi_csr_time_wmask[31: 0]), \\\n  .rvfi_csr_time_rdata  (rvfi_csr_time_rdata[31: 0]), \\\n  .rvfi_csr_time_wdata  (rvfi_csr_time_wdata[31: 0]), \\\n  .rvfi_csr_timeh_rmask (rvfi_csr_time_rmask[63:32]), \\\n  .rvfi_csr_timeh_wmask (rvfi_csr_time_wmask[63:32]), \\\n  .rvfi_csr_timeh_rdata (rvfi_csr_time_rdata[63:32]), \\\n  .rvfi_csr_timeh_wdata (rvfi_csr_time_wdata[63:32])\n`define rvformal_csr_time_channel(_idx) \\\n  wire [64 - 1 : 0] csr_time_rmask = rvfi_csr_time_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_time_wmask = rvfi_csr_time_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_time_rdata = rvfi_csr_time_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_time_wdata = rvfi_csr_time_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_time_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_time_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_time_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_time_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_time_wdata)\n`else\n`define rvformal_csr_time_wires\n`define rvformal_csr_time_outputs\n`define rvformal_csr_time_inputs\n`define rvformal_csr_time_conn\n`define rvformal_csr_time_conn32\n`define rvformal_csr_time_channel(_idx)\n`endif\n`define rvformal_csr_time_indices \\\nlocalparam [11:0] csr_mindex_time = 12'hFFF; \\\nlocalparam [11:0] csr_sindex_time = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_time = 12'hC01; \\\nlocalparam [11:0] csr_mindex_timeh = 12'hFFF; \\\nlocalparam [11:0] csr_sindex_timeh = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_timeh = 12'hC01; \\\n\n`ifdef RISCV_FORMAL_CSR_MINSTRET\n`define rvformal_csr_minstret_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wdata;\n`define rvformal_csr_minstret_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wdata\n`define rvformal_csr_minstret_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_minstret_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_minstret_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_minstret_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_minstret_wdata\n`define rvformal_csr_minstret_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_minstret_wdata\n`define rvformal_csr_minstret_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_minstret_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_minstret_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_minstret_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_minstret_wdata\n`define rvformal_csr_minstret_conn, \\\n  .rvfi_csr_minstret_rmask (rvfi_csr_minstret_rmask), \\\n  .rvfi_csr_minstret_wmask (rvfi_csr_minstret_wmask), \\\n  .rvfi_csr_minstret_rdata (rvfi_csr_minstret_rdata), \\\n  .rvfi_csr_minstret_wdata (rvfi_csr_minstret_wdata)\n`define rvformal_csr_minstret_channel_conn(_idx), \\\n  .rvfi_csr_minstret_rmask (rvfi_csr_minstret_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_minstret_wmask (rvfi_csr_minstret_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_minstret_rdata (rvfi_csr_minstret_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_minstret_wdata (rvfi_csr_minstret_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_minstret_conn32, \\\n  .rvfi_csr_minstret_rmask  (rvfi_csr_minstret_rmask[31: 0]), \\\n  .rvfi_csr_minstret_wmask  (rvfi_csr_minstret_wmask[31: 0]), \\\n  .rvfi_csr_minstret_rdata  (rvfi_csr_minstret_rdata[31: 0]), \\\n  .rvfi_csr_minstret_wdata  (rvfi_csr_minstret_wdata[31: 0]), \\\n  .rvfi_csr_minstreth_rmask (rvfi_csr_minstret_rmask[63:32]), \\\n  .rvfi_csr_minstreth_wmask (rvfi_csr_minstret_wmask[63:32]), \\\n  .rvfi_csr_minstreth_rdata (rvfi_csr_minstret_rdata[63:32]), \\\n  .rvfi_csr_minstreth_wdata (rvfi_csr_minstret_wdata[63:32])\n`define rvformal_csr_minstret_channel(_idx) \\\n  wire [64 - 1 : 0] csr_minstret_rmask = rvfi_csr_minstret_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_minstret_wmask = rvfi_csr_minstret_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_minstret_rdata = rvfi_csr_minstret_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_minstret_wdata = rvfi_csr_minstret_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_minstret_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_minstret_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_minstret_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_minstret_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_minstret_wdata)\n`else\n`define rvformal_csr_minstret_wires\n`define rvformal_csr_minstret_outputs\n`define rvformal_csr_minstret_inputs\n`define rvformal_csr_minstret_conn\n`define rvformal_csr_minstret_conn32\n`define rvformal_csr_minstret_channel(_idx)\n`endif\n`define rvformal_csr_minstret_indices \\\nlocalparam [11:0] csr_mindex_minstret = 12'hB02; \\\nlocalparam [11:0] csr_sindex_minstret = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_minstret = 12'hC02; \\\nlocalparam [11:0] csr_mindex_minstreth = 12'hB82; \\\nlocalparam [11:0] csr_sindex_minstreth = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_minstreth = 12'hC82; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER3\n`define rvformal_csr_mhpmcounter3_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata;\n`define rvformal_csr_mhpmcounter3_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata\n`define rvformal_csr_mhpmcounter3_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata\n`define rvformal_csr_mhpmcounter3_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata\n`define rvformal_csr_mhpmcounter3_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter3_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter3_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter3_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter3_wdata\n`define rvformal_csr_mhpmcounter3_conn, \\\n  .rvfi_csr_mhpmcounter3_rmask (rvfi_csr_mhpmcounter3_rmask), \\\n  .rvfi_csr_mhpmcounter3_wmask (rvfi_csr_mhpmcounter3_wmask), \\\n  .rvfi_csr_mhpmcounter3_rdata (rvfi_csr_mhpmcounter3_rdata), \\\n  .rvfi_csr_mhpmcounter3_wdata (rvfi_csr_mhpmcounter3_wdata)\n`define rvformal_csr_mhpmcounter3_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter3_rmask (rvfi_csr_mhpmcounter3_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter3_wmask (rvfi_csr_mhpmcounter3_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter3_rdata (rvfi_csr_mhpmcounter3_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter3_wdata (rvfi_csr_mhpmcounter3_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter3_conn32, \\\n  .rvfi_csr_mhpmcounter3_rmask  (rvfi_csr_mhpmcounter3_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter3_wmask  (rvfi_csr_mhpmcounter3_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter3_rdata  (rvfi_csr_mhpmcounter3_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter3_wdata  (rvfi_csr_mhpmcounter3_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter3h_rmask (rvfi_csr_mhpmcounter3_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter3h_wmask (rvfi_csr_mhpmcounter3_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter3h_rdata (rvfi_csr_mhpmcounter3_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter3h_wdata (rvfi_csr_mhpmcounter3_wdata[63:32])\n`define rvformal_csr_mhpmcounter3_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter3_rmask = rvfi_csr_mhpmcounter3_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter3_wmask = rvfi_csr_mhpmcounter3_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter3_rdata = rvfi_csr_mhpmcounter3_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter3_wdata = rvfi_csr_mhpmcounter3_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter3_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter3_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter3_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter3_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter3_wdata)\n`else\n`define rvformal_csr_mhpmcounter3_wires\n`define rvformal_csr_mhpmcounter3_outputs\n`define rvformal_csr_mhpmcounter3_inputs\n`define rvformal_csr_mhpmcounter3_conn\n`define rvformal_csr_mhpmcounter3_conn32\n`define rvformal_csr_mhpmcounter3_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter3_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter3 = 12'hB03; \\\nlocalparam [11:0] csr_sindex_mhpmcounter3 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter3 = 12'hC03; \\\nlocalparam [11:0] csr_mindex_mhpmcounter3h = 12'hB83; \\\nlocalparam [11:0] csr_sindex_mhpmcounter3h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter3h = 12'hC83; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER4\n`define rvformal_csr_mhpmcounter4_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata;\n`define rvformal_csr_mhpmcounter4_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata\n`define rvformal_csr_mhpmcounter4_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata\n`define rvformal_csr_mhpmcounter4_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata\n`define rvformal_csr_mhpmcounter4_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter4_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter4_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter4_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter4_wdata\n`define rvformal_csr_mhpmcounter4_conn, \\\n  .rvfi_csr_mhpmcounter4_rmask (rvfi_csr_mhpmcounter4_rmask), \\\n  .rvfi_csr_mhpmcounter4_wmask (rvfi_csr_mhpmcounter4_wmask), \\\n  .rvfi_csr_mhpmcounter4_rdata (rvfi_csr_mhpmcounter4_rdata), \\\n  .rvfi_csr_mhpmcounter4_wdata (rvfi_csr_mhpmcounter4_wdata)\n`define rvformal_csr_mhpmcounter4_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter4_rmask (rvfi_csr_mhpmcounter4_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter4_wmask (rvfi_csr_mhpmcounter4_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter4_rdata (rvfi_csr_mhpmcounter4_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter4_wdata (rvfi_csr_mhpmcounter4_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter4_conn32, \\\n  .rvfi_csr_mhpmcounter4_rmask  (rvfi_csr_mhpmcounter4_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter4_wmask  (rvfi_csr_mhpmcounter4_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter4_rdata  (rvfi_csr_mhpmcounter4_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter4_wdata  (rvfi_csr_mhpmcounter4_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter4h_rmask (rvfi_csr_mhpmcounter4_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter4h_wmask (rvfi_csr_mhpmcounter4_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter4h_rdata (rvfi_csr_mhpmcounter4_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter4h_wdata (rvfi_csr_mhpmcounter4_wdata[63:32])\n`define rvformal_csr_mhpmcounter4_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter4_rmask = rvfi_csr_mhpmcounter4_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter4_wmask = rvfi_csr_mhpmcounter4_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter4_rdata = rvfi_csr_mhpmcounter4_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter4_wdata = rvfi_csr_mhpmcounter4_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter4_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter4_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter4_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter4_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter4_wdata)\n`else\n`define rvformal_csr_mhpmcounter4_wires\n`define rvformal_csr_mhpmcounter4_outputs\n`define rvformal_csr_mhpmcounter4_inputs\n`define rvformal_csr_mhpmcounter4_conn\n`define rvformal_csr_mhpmcounter4_conn32\n`define rvformal_csr_mhpmcounter4_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter4_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter4 = 12'hB04; \\\nlocalparam [11:0] csr_sindex_mhpmcounter4 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter4 = 12'hC04; \\\nlocalparam [11:0] csr_mindex_mhpmcounter4h = 12'hB84; \\\nlocalparam [11:0] csr_sindex_mhpmcounter4h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter4h = 12'hC84; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER5\n`define rvformal_csr_mhpmcounter5_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata;\n`define rvformal_csr_mhpmcounter5_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata\n`define rvformal_csr_mhpmcounter5_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata\n`define rvformal_csr_mhpmcounter5_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata\n`define rvformal_csr_mhpmcounter5_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter5_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter5_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter5_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter5_wdata\n`define rvformal_csr_mhpmcounter5_conn, \\\n  .rvfi_csr_mhpmcounter5_rmask (rvfi_csr_mhpmcounter5_rmask), \\\n  .rvfi_csr_mhpmcounter5_wmask (rvfi_csr_mhpmcounter5_wmask), \\\n  .rvfi_csr_mhpmcounter5_rdata (rvfi_csr_mhpmcounter5_rdata), \\\n  .rvfi_csr_mhpmcounter5_wdata (rvfi_csr_mhpmcounter5_wdata)\n`define rvformal_csr_mhpmcounter5_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter5_rmask (rvfi_csr_mhpmcounter5_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter5_wmask (rvfi_csr_mhpmcounter5_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter5_rdata (rvfi_csr_mhpmcounter5_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter5_wdata (rvfi_csr_mhpmcounter5_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter5_conn32, \\\n  .rvfi_csr_mhpmcounter5_rmask  (rvfi_csr_mhpmcounter5_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter5_wmask  (rvfi_csr_mhpmcounter5_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter5_rdata  (rvfi_csr_mhpmcounter5_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter5_wdata  (rvfi_csr_mhpmcounter5_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter5h_rmask (rvfi_csr_mhpmcounter5_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter5h_wmask (rvfi_csr_mhpmcounter5_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter5h_rdata (rvfi_csr_mhpmcounter5_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter5h_wdata (rvfi_csr_mhpmcounter5_wdata[63:32])\n`define rvformal_csr_mhpmcounter5_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter5_rmask = rvfi_csr_mhpmcounter5_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter5_wmask = rvfi_csr_mhpmcounter5_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter5_rdata = rvfi_csr_mhpmcounter5_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter5_wdata = rvfi_csr_mhpmcounter5_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter5_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter5_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter5_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter5_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter5_wdata)\n`else\n`define rvformal_csr_mhpmcounter5_wires\n`define rvformal_csr_mhpmcounter5_outputs\n`define rvformal_csr_mhpmcounter5_inputs\n`define rvformal_csr_mhpmcounter5_conn\n`define rvformal_csr_mhpmcounter5_conn32\n`define rvformal_csr_mhpmcounter5_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter5_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter5 = 12'hB05; \\\nlocalparam [11:0] csr_sindex_mhpmcounter5 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter5 = 12'hC05; \\\nlocalparam [11:0] csr_mindex_mhpmcounter5h = 12'hB85; \\\nlocalparam [11:0] csr_sindex_mhpmcounter5h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter5h = 12'hC85; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER6\n`define rvformal_csr_mhpmcounter6_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata;\n`define rvformal_csr_mhpmcounter6_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata\n`define rvformal_csr_mhpmcounter6_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata\n`define rvformal_csr_mhpmcounter6_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata\n`define rvformal_csr_mhpmcounter6_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter6_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter6_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter6_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter6_wdata\n`define rvformal_csr_mhpmcounter6_conn, \\\n  .rvfi_csr_mhpmcounter6_rmask (rvfi_csr_mhpmcounter6_rmask), \\\n  .rvfi_csr_mhpmcounter6_wmask (rvfi_csr_mhpmcounter6_wmask), \\\n  .rvfi_csr_mhpmcounter6_rdata (rvfi_csr_mhpmcounter6_rdata), \\\n  .rvfi_csr_mhpmcounter6_wdata (rvfi_csr_mhpmcounter6_wdata)\n`define rvformal_csr_mhpmcounter6_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter6_rmask (rvfi_csr_mhpmcounter6_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter6_wmask (rvfi_csr_mhpmcounter6_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter6_rdata (rvfi_csr_mhpmcounter6_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter6_wdata (rvfi_csr_mhpmcounter6_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter6_conn32, \\\n  .rvfi_csr_mhpmcounter6_rmask  (rvfi_csr_mhpmcounter6_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter6_wmask  (rvfi_csr_mhpmcounter6_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter6_rdata  (rvfi_csr_mhpmcounter6_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter6_wdata  (rvfi_csr_mhpmcounter6_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter6h_rmask (rvfi_csr_mhpmcounter6_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter6h_wmask (rvfi_csr_mhpmcounter6_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter6h_rdata (rvfi_csr_mhpmcounter6_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter6h_wdata (rvfi_csr_mhpmcounter6_wdata[63:32])\n`define rvformal_csr_mhpmcounter6_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter6_rmask = rvfi_csr_mhpmcounter6_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter6_wmask = rvfi_csr_mhpmcounter6_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter6_rdata = rvfi_csr_mhpmcounter6_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter6_wdata = rvfi_csr_mhpmcounter6_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter6_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter6_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter6_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter6_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter6_wdata)\n`else\n`define rvformal_csr_mhpmcounter6_wires\n`define rvformal_csr_mhpmcounter6_outputs\n`define rvformal_csr_mhpmcounter6_inputs\n`define rvformal_csr_mhpmcounter6_conn\n`define rvformal_csr_mhpmcounter6_conn32\n`define rvformal_csr_mhpmcounter6_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter6_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter6 = 12'hB06; \\\nlocalparam [11:0] csr_sindex_mhpmcounter6 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter6 = 12'hC06; \\\nlocalparam [11:0] csr_mindex_mhpmcounter6h = 12'hB86; \\\nlocalparam [11:0] csr_sindex_mhpmcounter6h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter6h = 12'hC86; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER7\n`define rvformal_csr_mhpmcounter7_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata;\n`define rvformal_csr_mhpmcounter7_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata\n`define rvformal_csr_mhpmcounter7_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata\n`define rvformal_csr_mhpmcounter7_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata\n`define rvformal_csr_mhpmcounter7_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter7_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter7_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter7_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter7_wdata\n`define rvformal_csr_mhpmcounter7_conn, \\\n  .rvfi_csr_mhpmcounter7_rmask (rvfi_csr_mhpmcounter7_rmask), \\\n  .rvfi_csr_mhpmcounter7_wmask (rvfi_csr_mhpmcounter7_wmask), \\\n  .rvfi_csr_mhpmcounter7_rdata (rvfi_csr_mhpmcounter7_rdata), \\\n  .rvfi_csr_mhpmcounter7_wdata (rvfi_csr_mhpmcounter7_wdata)\n`define rvformal_csr_mhpmcounter7_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter7_rmask (rvfi_csr_mhpmcounter7_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter7_wmask (rvfi_csr_mhpmcounter7_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter7_rdata (rvfi_csr_mhpmcounter7_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter7_wdata (rvfi_csr_mhpmcounter7_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter7_conn32, \\\n  .rvfi_csr_mhpmcounter7_rmask  (rvfi_csr_mhpmcounter7_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter7_wmask  (rvfi_csr_mhpmcounter7_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter7_rdata  (rvfi_csr_mhpmcounter7_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter7_wdata  (rvfi_csr_mhpmcounter7_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter7h_rmask (rvfi_csr_mhpmcounter7_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter7h_wmask (rvfi_csr_mhpmcounter7_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter7h_rdata (rvfi_csr_mhpmcounter7_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter7h_wdata (rvfi_csr_mhpmcounter7_wdata[63:32])\n`define rvformal_csr_mhpmcounter7_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter7_rmask = rvfi_csr_mhpmcounter7_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter7_wmask = rvfi_csr_mhpmcounter7_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter7_rdata = rvfi_csr_mhpmcounter7_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter7_wdata = rvfi_csr_mhpmcounter7_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter7_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter7_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter7_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter7_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter7_wdata)\n`else\n`define rvformal_csr_mhpmcounter7_wires\n`define rvformal_csr_mhpmcounter7_outputs\n`define rvformal_csr_mhpmcounter7_inputs\n`define rvformal_csr_mhpmcounter7_conn\n`define rvformal_csr_mhpmcounter7_conn32\n`define rvformal_csr_mhpmcounter7_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter7_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter7 = 12'hB07; \\\nlocalparam [11:0] csr_sindex_mhpmcounter7 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter7 = 12'hC07; \\\nlocalparam [11:0] csr_mindex_mhpmcounter7h = 12'hB87; \\\nlocalparam [11:0] csr_sindex_mhpmcounter7h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter7h = 12'hC87; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER8\n`define rvformal_csr_mhpmcounter8_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata;\n`define rvformal_csr_mhpmcounter8_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata\n`define rvformal_csr_mhpmcounter8_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata\n`define rvformal_csr_mhpmcounter8_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata\n`define rvformal_csr_mhpmcounter8_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter8_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter8_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter8_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter8_wdata\n`define rvformal_csr_mhpmcounter8_conn, \\\n  .rvfi_csr_mhpmcounter8_rmask (rvfi_csr_mhpmcounter8_rmask), \\\n  .rvfi_csr_mhpmcounter8_wmask (rvfi_csr_mhpmcounter8_wmask), \\\n  .rvfi_csr_mhpmcounter8_rdata (rvfi_csr_mhpmcounter8_rdata), \\\n  .rvfi_csr_mhpmcounter8_wdata (rvfi_csr_mhpmcounter8_wdata)\n`define rvformal_csr_mhpmcounter8_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter8_rmask (rvfi_csr_mhpmcounter8_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter8_wmask (rvfi_csr_mhpmcounter8_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter8_rdata (rvfi_csr_mhpmcounter8_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter8_wdata (rvfi_csr_mhpmcounter8_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter8_conn32, \\\n  .rvfi_csr_mhpmcounter8_rmask  (rvfi_csr_mhpmcounter8_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter8_wmask  (rvfi_csr_mhpmcounter8_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter8_rdata  (rvfi_csr_mhpmcounter8_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter8_wdata  (rvfi_csr_mhpmcounter8_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter8h_rmask (rvfi_csr_mhpmcounter8_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter8h_wmask (rvfi_csr_mhpmcounter8_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter8h_rdata (rvfi_csr_mhpmcounter8_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter8h_wdata (rvfi_csr_mhpmcounter8_wdata[63:32])\n`define rvformal_csr_mhpmcounter8_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter8_rmask = rvfi_csr_mhpmcounter8_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter8_wmask = rvfi_csr_mhpmcounter8_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter8_rdata = rvfi_csr_mhpmcounter8_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter8_wdata = rvfi_csr_mhpmcounter8_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter8_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter8_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter8_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter8_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter8_wdata)\n`else\n`define rvformal_csr_mhpmcounter8_wires\n`define rvformal_csr_mhpmcounter8_outputs\n`define rvformal_csr_mhpmcounter8_inputs\n`define rvformal_csr_mhpmcounter8_conn\n`define rvformal_csr_mhpmcounter8_conn32\n`define rvformal_csr_mhpmcounter8_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter8_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter8 = 12'hB08; \\\nlocalparam [11:0] csr_sindex_mhpmcounter8 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter8 = 12'hC08; \\\nlocalparam [11:0] csr_mindex_mhpmcounter8h = 12'hB88; \\\nlocalparam [11:0] csr_sindex_mhpmcounter8h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter8h = 12'hC88; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER9\n`define rvformal_csr_mhpmcounter9_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata;\n`define rvformal_csr_mhpmcounter9_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata\n`define rvformal_csr_mhpmcounter9_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata\n`define rvformal_csr_mhpmcounter9_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata\n`define rvformal_csr_mhpmcounter9_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter9_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter9_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter9_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter9_wdata\n`define rvformal_csr_mhpmcounter9_conn, \\\n  .rvfi_csr_mhpmcounter9_rmask (rvfi_csr_mhpmcounter9_rmask), \\\n  .rvfi_csr_mhpmcounter9_wmask (rvfi_csr_mhpmcounter9_wmask), \\\n  .rvfi_csr_mhpmcounter9_rdata (rvfi_csr_mhpmcounter9_rdata), \\\n  .rvfi_csr_mhpmcounter9_wdata (rvfi_csr_mhpmcounter9_wdata)\n`define rvformal_csr_mhpmcounter9_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter9_rmask (rvfi_csr_mhpmcounter9_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter9_wmask (rvfi_csr_mhpmcounter9_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter9_rdata (rvfi_csr_mhpmcounter9_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter9_wdata (rvfi_csr_mhpmcounter9_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter9_conn32, \\\n  .rvfi_csr_mhpmcounter9_rmask  (rvfi_csr_mhpmcounter9_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter9_wmask  (rvfi_csr_mhpmcounter9_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter9_rdata  (rvfi_csr_mhpmcounter9_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter9_wdata  (rvfi_csr_mhpmcounter9_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter9h_rmask (rvfi_csr_mhpmcounter9_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter9h_wmask (rvfi_csr_mhpmcounter9_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter9h_rdata (rvfi_csr_mhpmcounter9_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter9h_wdata (rvfi_csr_mhpmcounter9_wdata[63:32])\n`define rvformal_csr_mhpmcounter9_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter9_rmask = rvfi_csr_mhpmcounter9_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter9_wmask = rvfi_csr_mhpmcounter9_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter9_rdata = rvfi_csr_mhpmcounter9_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter9_wdata = rvfi_csr_mhpmcounter9_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter9_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter9_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter9_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter9_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter9_wdata)\n`else\n`define rvformal_csr_mhpmcounter9_wires\n`define rvformal_csr_mhpmcounter9_outputs\n`define rvformal_csr_mhpmcounter9_inputs\n`define rvformal_csr_mhpmcounter9_conn\n`define rvformal_csr_mhpmcounter9_conn32\n`define rvformal_csr_mhpmcounter9_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter9_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter9 = 12'hB09; \\\nlocalparam [11:0] csr_sindex_mhpmcounter9 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter9 = 12'hC09; \\\nlocalparam [11:0] csr_mindex_mhpmcounter9h = 12'hB89; \\\nlocalparam [11:0] csr_sindex_mhpmcounter9h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter9h = 12'hC89; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER10\n`define rvformal_csr_mhpmcounter10_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata;\n`define rvformal_csr_mhpmcounter10_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata\n`define rvformal_csr_mhpmcounter10_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata\n`define rvformal_csr_mhpmcounter10_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata\n`define rvformal_csr_mhpmcounter10_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter10_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter10_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter10_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter10_wdata\n`define rvformal_csr_mhpmcounter10_conn, \\\n  .rvfi_csr_mhpmcounter10_rmask (rvfi_csr_mhpmcounter10_rmask), \\\n  .rvfi_csr_mhpmcounter10_wmask (rvfi_csr_mhpmcounter10_wmask), \\\n  .rvfi_csr_mhpmcounter10_rdata (rvfi_csr_mhpmcounter10_rdata), \\\n  .rvfi_csr_mhpmcounter10_wdata (rvfi_csr_mhpmcounter10_wdata)\n`define rvformal_csr_mhpmcounter10_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter10_rmask (rvfi_csr_mhpmcounter10_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter10_wmask (rvfi_csr_mhpmcounter10_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter10_rdata (rvfi_csr_mhpmcounter10_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter10_wdata (rvfi_csr_mhpmcounter10_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter10_conn32, \\\n  .rvfi_csr_mhpmcounter10_rmask  (rvfi_csr_mhpmcounter10_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter10_wmask  (rvfi_csr_mhpmcounter10_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter10_rdata  (rvfi_csr_mhpmcounter10_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter10_wdata  (rvfi_csr_mhpmcounter10_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter10h_rmask (rvfi_csr_mhpmcounter10_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter10h_wmask (rvfi_csr_mhpmcounter10_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter10h_rdata (rvfi_csr_mhpmcounter10_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter10h_wdata (rvfi_csr_mhpmcounter10_wdata[63:32])\n`define rvformal_csr_mhpmcounter10_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter10_rmask = rvfi_csr_mhpmcounter10_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter10_wmask = rvfi_csr_mhpmcounter10_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter10_rdata = rvfi_csr_mhpmcounter10_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter10_wdata = rvfi_csr_mhpmcounter10_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter10_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter10_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter10_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter10_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter10_wdata)\n`else\n`define rvformal_csr_mhpmcounter10_wires\n`define rvformal_csr_mhpmcounter10_outputs\n`define rvformal_csr_mhpmcounter10_inputs\n`define rvformal_csr_mhpmcounter10_conn\n`define rvformal_csr_mhpmcounter10_conn32\n`define rvformal_csr_mhpmcounter10_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter10_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter10 = 12'hB0A; \\\nlocalparam [11:0] csr_sindex_mhpmcounter10 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter10 = 12'hC0A; \\\nlocalparam [11:0] csr_mindex_mhpmcounter10h = 12'hB8A; \\\nlocalparam [11:0] csr_sindex_mhpmcounter10h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter10h = 12'hC8A; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER11\n`define rvformal_csr_mhpmcounter11_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata;\n`define rvformal_csr_mhpmcounter11_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata\n`define rvformal_csr_mhpmcounter11_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata\n`define rvformal_csr_mhpmcounter11_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata\n`define rvformal_csr_mhpmcounter11_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter11_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter11_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter11_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter11_wdata\n`define rvformal_csr_mhpmcounter11_conn, \\\n  .rvfi_csr_mhpmcounter11_rmask (rvfi_csr_mhpmcounter11_rmask), \\\n  .rvfi_csr_mhpmcounter11_wmask (rvfi_csr_mhpmcounter11_wmask), \\\n  .rvfi_csr_mhpmcounter11_rdata (rvfi_csr_mhpmcounter11_rdata), \\\n  .rvfi_csr_mhpmcounter11_wdata (rvfi_csr_mhpmcounter11_wdata)\n`define rvformal_csr_mhpmcounter11_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter11_rmask (rvfi_csr_mhpmcounter11_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter11_wmask (rvfi_csr_mhpmcounter11_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter11_rdata (rvfi_csr_mhpmcounter11_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter11_wdata (rvfi_csr_mhpmcounter11_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter11_conn32, \\\n  .rvfi_csr_mhpmcounter11_rmask  (rvfi_csr_mhpmcounter11_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter11_wmask  (rvfi_csr_mhpmcounter11_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter11_rdata  (rvfi_csr_mhpmcounter11_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter11_wdata  (rvfi_csr_mhpmcounter11_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter11h_rmask (rvfi_csr_mhpmcounter11_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter11h_wmask (rvfi_csr_mhpmcounter11_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter11h_rdata (rvfi_csr_mhpmcounter11_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter11h_wdata (rvfi_csr_mhpmcounter11_wdata[63:32])\n`define rvformal_csr_mhpmcounter11_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter11_rmask = rvfi_csr_mhpmcounter11_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter11_wmask = rvfi_csr_mhpmcounter11_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter11_rdata = rvfi_csr_mhpmcounter11_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter11_wdata = rvfi_csr_mhpmcounter11_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter11_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter11_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter11_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter11_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter11_wdata)\n`else\n`define rvformal_csr_mhpmcounter11_wires\n`define rvformal_csr_mhpmcounter11_outputs\n`define rvformal_csr_mhpmcounter11_inputs\n`define rvformal_csr_mhpmcounter11_conn\n`define rvformal_csr_mhpmcounter11_conn32\n`define rvformal_csr_mhpmcounter11_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter11_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter11 = 12'hB0B; \\\nlocalparam [11:0] csr_sindex_mhpmcounter11 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter11 = 12'hC0B; \\\nlocalparam [11:0] csr_mindex_mhpmcounter11h = 12'hB8B; \\\nlocalparam [11:0] csr_sindex_mhpmcounter11h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter11h = 12'hC8B; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER12\n`define rvformal_csr_mhpmcounter12_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata;\n`define rvformal_csr_mhpmcounter12_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata\n`define rvformal_csr_mhpmcounter12_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata\n`define rvformal_csr_mhpmcounter12_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata\n`define rvformal_csr_mhpmcounter12_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter12_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter12_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter12_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter12_wdata\n`define rvformal_csr_mhpmcounter12_conn, \\\n  .rvfi_csr_mhpmcounter12_rmask (rvfi_csr_mhpmcounter12_rmask), \\\n  .rvfi_csr_mhpmcounter12_wmask (rvfi_csr_mhpmcounter12_wmask), \\\n  .rvfi_csr_mhpmcounter12_rdata (rvfi_csr_mhpmcounter12_rdata), \\\n  .rvfi_csr_mhpmcounter12_wdata (rvfi_csr_mhpmcounter12_wdata)\n`define rvformal_csr_mhpmcounter12_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter12_rmask (rvfi_csr_mhpmcounter12_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter12_wmask (rvfi_csr_mhpmcounter12_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter12_rdata (rvfi_csr_mhpmcounter12_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter12_wdata (rvfi_csr_mhpmcounter12_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter12_conn32, \\\n  .rvfi_csr_mhpmcounter12_rmask  (rvfi_csr_mhpmcounter12_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter12_wmask  (rvfi_csr_mhpmcounter12_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter12_rdata  (rvfi_csr_mhpmcounter12_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter12_wdata  (rvfi_csr_mhpmcounter12_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter12h_rmask (rvfi_csr_mhpmcounter12_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter12h_wmask (rvfi_csr_mhpmcounter12_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter12h_rdata (rvfi_csr_mhpmcounter12_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter12h_wdata (rvfi_csr_mhpmcounter12_wdata[63:32])\n`define rvformal_csr_mhpmcounter12_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter12_rmask = rvfi_csr_mhpmcounter12_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter12_wmask = rvfi_csr_mhpmcounter12_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter12_rdata = rvfi_csr_mhpmcounter12_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter12_wdata = rvfi_csr_mhpmcounter12_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter12_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter12_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter12_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter12_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter12_wdata)\n`else\n`define rvformal_csr_mhpmcounter12_wires\n`define rvformal_csr_mhpmcounter12_outputs\n`define rvformal_csr_mhpmcounter12_inputs\n`define rvformal_csr_mhpmcounter12_conn\n`define rvformal_csr_mhpmcounter12_conn32\n`define rvformal_csr_mhpmcounter12_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter12_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter12 = 12'hB0C; \\\nlocalparam [11:0] csr_sindex_mhpmcounter12 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter12 = 12'hC0C; \\\nlocalparam [11:0] csr_mindex_mhpmcounter12h = 12'hB8C; \\\nlocalparam [11:0] csr_sindex_mhpmcounter12h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter12h = 12'hC8C; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER13\n`define rvformal_csr_mhpmcounter13_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata;\n`define rvformal_csr_mhpmcounter13_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata\n`define rvformal_csr_mhpmcounter13_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata\n`define rvformal_csr_mhpmcounter13_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata\n`define rvformal_csr_mhpmcounter13_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter13_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter13_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter13_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter13_wdata\n`define rvformal_csr_mhpmcounter13_conn, \\\n  .rvfi_csr_mhpmcounter13_rmask (rvfi_csr_mhpmcounter13_rmask), \\\n  .rvfi_csr_mhpmcounter13_wmask (rvfi_csr_mhpmcounter13_wmask), \\\n  .rvfi_csr_mhpmcounter13_rdata (rvfi_csr_mhpmcounter13_rdata), \\\n  .rvfi_csr_mhpmcounter13_wdata (rvfi_csr_mhpmcounter13_wdata)\n`define rvformal_csr_mhpmcounter13_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter13_rmask (rvfi_csr_mhpmcounter13_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter13_wmask (rvfi_csr_mhpmcounter13_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter13_rdata (rvfi_csr_mhpmcounter13_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter13_wdata (rvfi_csr_mhpmcounter13_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter13_conn32, \\\n  .rvfi_csr_mhpmcounter13_rmask  (rvfi_csr_mhpmcounter13_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter13_wmask  (rvfi_csr_mhpmcounter13_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter13_rdata  (rvfi_csr_mhpmcounter13_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter13_wdata  (rvfi_csr_mhpmcounter13_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter13h_rmask (rvfi_csr_mhpmcounter13_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter13h_wmask (rvfi_csr_mhpmcounter13_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter13h_rdata (rvfi_csr_mhpmcounter13_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter13h_wdata (rvfi_csr_mhpmcounter13_wdata[63:32])\n`define rvformal_csr_mhpmcounter13_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter13_rmask = rvfi_csr_mhpmcounter13_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter13_wmask = rvfi_csr_mhpmcounter13_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter13_rdata = rvfi_csr_mhpmcounter13_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter13_wdata = rvfi_csr_mhpmcounter13_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter13_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter13_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter13_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter13_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter13_wdata)\n`else\n`define rvformal_csr_mhpmcounter13_wires\n`define rvformal_csr_mhpmcounter13_outputs\n`define rvformal_csr_mhpmcounter13_inputs\n`define rvformal_csr_mhpmcounter13_conn\n`define rvformal_csr_mhpmcounter13_conn32\n`define rvformal_csr_mhpmcounter13_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter13_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter13 = 12'hB0D; \\\nlocalparam [11:0] csr_sindex_mhpmcounter13 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter13 = 12'hC0D; \\\nlocalparam [11:0] csr_mindex_mhpmcounter13h = 12'hB8D; \\\nlocalparam [11:0] csr_sindex_mhpmcounter13h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter13h = 12'hC8D; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER14\n`define rvformal_csr_mhpmcounter14_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata;\n`define rvformal_csr_mhpmcounter14_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata\n`define rvformal_csr_mhpmcounter14_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata\n`define rvformal_csr_mhpmcounter14_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata\n`define rvformal_csr_mhpmcounter14_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter14_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter14_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter14_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter14_wdata\n`define rvformal_csr_mhpmcounter14_conn, \\\n  .rvfi_csr_mhpmcounter14_rmask (rvfi_csr_mhpmcounter14_rmask), \\\n  .rvfi_csr_mhpmcounter14_wmask (rvfi_csr_mhpmcounter14_wmask), \\\n  .rvfi_csr_mhpmcounter14_rdata (rvfi_csr_mhpmcounter14_rdata), \\\n  .rvfi_csr_mhpmcounter14_wdata (rvfi_csr_mhpmcounter14_wdata)\n`define rvformal_csr_mhpmcounter14_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter14_rmask (rvfi_csr_mhpmcounter14_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter14_wmask (rvfi_csr_mhpmcounter14_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter14_rdata (rvfi_csr_mhpmcounter14_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter14_wdata (rvfi_csr_mhpmcounter14_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter14_conn32, \\\n  .rvfi_csr_mhpmcounter14_rmask  (rvfi_csr_mhpmcounter14_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter14_wmask  (rvfi_csr_mhpmcounter14_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter14_rdata  (rvfi_csr_mhpmcounter14_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter14_wdata  (rvfi_csr_mhpmcounter14_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter14h_rmask (rvfi_csr_mhpmcounter14_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter14h_wmask (rvfi_csr_mhpmcounter14_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter14h_rdata (rvfi_csr_mhpmcounter14_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter14h_wdata (rvfi_csr_mhpmcounter14_wdata[63:32])\n`define rvformal_csr_mhpmcounter14_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter14_rmask = rvfi_csr_mhpmcounter14_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter14_wmask = rvfi_csr_mhpmcounter14_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter14_rdata = rvfi_csr_mhpmcounter14_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter14_wdata = rvfi_csr_mhpmcounter14_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter14_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter14_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter14_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter14_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter14_wdata)\n`else\n`define rvformal_csr_mhpmcounter14_wires\n`define rvformal_csr_mhpmcounter14_outputs\n`define rvformal_csr_mhpmcounter14_inputs\n`define rvformal_csr_mhpmcounter14_conn\n`define rvformal_csr_mhpmcounter14_conn32\n`define rvformal_csr_mhpmcounter14_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter14_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter14 = 12'hB0E; \\\nlocalparam [11:0] csr_sindex_mhpmcounter14 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter14 = 12'hC0E; \\\nlocalparam [11:0] csr_mindex_mhpmcounter14h = 12'hB8E; \\\nlocalparam [11:0] csr_sindex_mhpmcounter14h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter14h = 12'hC8E; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER15\n`define rvformal_csr_mhpmcounter15_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata;\n`define rvformal_csr_mhpmcounter15_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata\n`define rvformal_csr_mhpmcounter15_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata\n`define rvformal_csr_mhpmcounter15_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata\n`define rvformal_csr_mhpmcounter15_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter15_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter15_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter15_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter15_wdata\n`define rvformal_csr_mhpmcounter15_conn, \\\n  .rvfi_csr_mhpmcounter15_rmask (rvfi_csr_mhpmcounter15_rmask), \\\n  .rvfi_csr_mhpmcounter15_wmask (rvfi_csr_mhpmcounter15_wmask), \\\n  .rvfi_csr_mhpmcounter15_rdata (rvfi_csr_mhpmcounter15_rdata), \\\n  .rvfi_csr_mhpmcounter15_wdata (rvfi_csr_mhpmcounter15_wdata)\n`define rvformal_csr_mhpmcounter15_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter15_rmask (rvfi_csr_mhpmcounter15_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter15_wmask (rvfi_csr_mhpmcounter15_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter15_rdata (rvfi_csr_mhpmcounter15_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter15_wdata (rvfi_csr_mhpmcounter15_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter15_conn32, \\\n  .rvfi_csr_mhpmcounter15_rmask  (rvfi_csr_mhpmcounter15_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter15_wmask  (rvfi_csr_mhpmcounter15_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter15_rdata  (rvfi_csr_mhpmcounter15_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter15_wdata  (rvfi_csr_mhpmcounter15_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter15h_rmask (rvfi_csr_mhpmcounter15_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter15h_wmask (rvfi_csr_mhpmcounter15_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter15h_rdata (rvfi_csr_mhpmcounter15_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter15h_wdata (rvfi_csr_mhpmcounter15_wdata[63:32])\n`define rvformal_csr_mhpmcounter15_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter15_rmask = rvfi_csr_mhpmcounter15_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter15_wmask = rvfi_csr_mhpmcounter15_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter15_rdata = rvfi_csr_mhpmcounter15_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter15_wdata = rvfi_csr_mhpmcounter15_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter15_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter15_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter15_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter15_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter15_wdata)\n`else\n`define rvformal_csr_mhpmcounter15_wires\n`define rvformal_csr_mhpmcounter15_outputs\n`define rvformal_csr_mhpmcounter15_inputs\n`define rvformal_csr_mhpmcounter15_conn\n`define rvformal_csr_mhpmcounter15_conn32\n`define rvformal_csr_mhpmcounter15_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter15_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter15 = 12'hB0F; \\\nlocalparam [11:0] csr_sindex_mhpmcounter15 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter15 = 12'hC0F; \\\nlocalparam [11:0] csr_mindex_mhpmcounter15h = 12'hB8F; \\\nlocalparam [11:0] csr_sindex_mhpmcounter15h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter15h = 12'hC8F; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER16\n`define rvformal_csr_mhpmcounter16_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata;\n`define rvformal_csr_mhpmcounter16_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata\n`define rvformal_csr_mhpmcounter16_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata\n`define rvformal_csr_mhpmcounter16_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata\n`define rvformal_csr_mhpmcounter16_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter16_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter16_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter16_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter16_wdata\n`define rvformal_csr_mhpmcounter16_conn, \\\n  .rvfi_csr_mhpmcounter16_rmask (rvfi_csr_mhpmcounter16_rmask), \\\n  .rvfi_csr_mhpmcounter16_wmask (rvfi_csr_mhpmcounter16_wmask), \\\n  .rvfi_csr_mhpmcounter16_rdata (rvfi_csr_mhpmcounter16_rdata), \\\n  .rvfi_csr_mhpmcounter16_wdata (rvfi_csr_mhpmcounter16_wdata)\n`define rvformal_csr_mhpmcounter16_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter16_rmask (rvfi_csr_mhpmcounter16_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter16_wmask (rvfi_csr_mhpmcounter16_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter16_rdata (rvfi_csr_mhpmcounter16_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter16_wdata (rvfi_csr_mhpmcounter16_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter16_conn32, \\\n  .rvfi_csr_mhpmcounter16_rmask  (rvfi_csr_mhpmcounter16_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter16_wmask  (rvfi_csr_mhpmcounter16_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter16_rdata  (rvfi_csr_mhpmcounter16_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter16_wdata  (rvfi_csr_mhpmcounter16_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter16h_rmask (rvfi_csr_mhpmcounter16_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter16h_wmask (rvfi_csr_mhpmcounter16_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter16h_rdata (rvfi_csr_mhpmcounter16_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter16h_wdata (rvfi_csr_mhpmcounter16_wdata[63:32])\n`define rvformal_csr_mhpmcounter16_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter16_rmask = rvfi_csr_mhpmcounter16_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter16_wmask = rvfi_csr_mhpmcounter16_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter16_rdata = rvfi_csr_mhpmcounter16_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter16_wdata = rvfi_csr_mhpmcounter16_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter16_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter16_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter16_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter16_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter16_wdata)\n`else\n`define rvformal_csr_mhpmcounter16_wires\n`define rvformal_csr_mhpmcounter16_outputs\n`define rvformal_csr_mhpmcounter16_inputs\n`define rvformal_csr_mhpmcounter16_conn\n`define rvformal_csr_mhpmcounter16_conn32\n`define rvformal_csr_mhpmcounter16_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter16_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter16 = 12'hB10; \\\nlocalparam [11:0] csr_sindex_mhpmcounter16 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter16 = 12'hC10; \\\nlocalparam [11:0] csr_mindex_mhpmcounter16h = 12'hB90; \\\nlocalparam [11:0] csr_sindex_mhpmcounter16h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter16h = 12'hC90; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER17\n`define rvformal_csr_mhpmcounter17_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata;\n`define rvformal_csr_mhpmcounter17_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata\n`define rvformal_csr_mhpmcounter17_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata\n`define rvformal_csr_mhpmcounter17_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata\n`define rvformal_csr_mhpmcounter17_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter17_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter17_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter17_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter17_wdata\n`define rvformal_csr_mhpmcounter17_conn, \\\n  .rvfi_csr_mhpmcounter17_rmask (rvfi_csr_mhpmcounter17_rmask), \\\n  .rvfi_csr_mhpmcounter17_wmask (rvfi_csr_mhpmcounter17_wmask), \\\n  .rvfi_csr_mhpmcounter17_rdata (rvfi_csr_mhpmcounter17_rdata), \\\n  .rvfi_csr_mhpmcounter17_wdata (rvfi_csr_mhpmcounter17_wdata)\n`define rvformal_csr_mhpmcounter17_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter17_rmask (rvfi_csr_mhpmcounter17_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter17_wmask (rvfi_csr_mhpmcounter17_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter17_rdata (rvfi_csr_mhpmcounter17_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter17_wdata (rvfi_csr_mhpmcounter17_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter17_conn32, \\\n  .rvfi_csr_mhpmcounter17_rmask  (rvfi_csr_mhpmcounter17_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter17_wmask  (rvfi_csr_mhpmcounter17_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter17_rdata  (rvfi_csr_mhpmcounter17_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter17_wdata  (rvfi_csr_mhpmcounter17_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter17h_rmask (rvfi_csr_mhpmcounter17_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter17h_wmask (rvfi_csr_mhpmcounter17_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter17h_rdata (rvfi_csr_mhpmcounter17_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter17h_wdata (rvfi_csr_mhpmcounter17_wdata[63:32])\n`define rvformal_csr_mhpmcounter17_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter17_rmask = rvfi_csr_mhpmcounter17_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter17_wmask = rvfi_csr_mhpmcounter17_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter17_rdata = rvfi_csr_mhpmcounter17_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter17_wdata = rvfi_csr_mhpmcounter17_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter17_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter17_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter17_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter17_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter17_wdata)\n`else\n`define rvformal_csr_mhpmcounter17_wires\n`define rvformal_csr_mhpmcounter17_outputs\n`define rvformal_csr_mhpmcounter17_inputs\n`define rvformal_csr_mhpmcounter17_conn\n`define rvformal_csr_mhpmcounter17_conn32\n`define rvformal_csr_mhpmcounter17_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter17_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter17 = 12'hB11; \\\nlocalparam [11:0] csr_sindex_mhpmcounter17 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter17 = 12'hC11; \\\nlocalparam [11:0] csr_mindex_mhpmcounter17h = 12'hB91; \\\nlocalparam [11:0] csr_sindex_mhpmcounter17h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter17h = 12'hC91; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER18\n`define rvformal_csr_mhpmcounter18_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata;\n`define rvformal_csr_mhpmcounter18_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata\n`define rvformal_csr_mhpmcounter18_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata\n`define rvformal_csr_mhpmcounter18_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata\n`define rvformal_csr_mhpmcounter18_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter18_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter18_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter18_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter18_wdata\n`define rvformal_csr_mhpmcounter18_conn, \\\n  .rvfi_csr_mhpmcounter18_rmask (rvfi_csr_mhpmcounter18_rmask), \\\n  .rvfi_csr_mhpmcounter18_wmask (rvfi_csr_mhpmcounter18_wmask), \\\n  .rvfi_csr_mhpmcounter18_rdata (rvfi_csr_mhpmcounter18_rdata), \\\n  .rvfi_csr_mhpmcounter18_wdata (rvfi_csr_mhpmcounter18_wdata)\n`define rvformal_csr_mhpmcounter18_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter18_rmask (rvfi_csr_mhpmcounter18_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter18_wmask (rvfi_csr_mhpmcounter18_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter18_rdata (rvfi_csr_mhpmcounter18_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter18_wdata (rvfi_csr_mhpmcounter18_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter18_conn32, \\\n  .rvfi_csr_mhpmcounter18_rmask  (rvfi_csr_mhpmcounter18_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter18_wmask  (rvfi_csr_mhpmcounter18_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter18_rdata  (rvfi_csr_mhpmcounter18_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter18_wdata  (rvfi_csr_mhpmcounter18_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter18h_rmask (rvfi_csr_mhpmcounter18_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter18h_wmask (rvfi_csr_mhpmcounter18_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter18h_rdata (rvfi_csr_mhpmcounter18_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter18h_wdata (rvfi_csr_mhpmcounter18_wdata[63:32])\n`define rvformal_csr_mhpmcounter18_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter18_rmask = rvfi_csr_mhpmcounter18_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter18_wmask = rvfi_csr_mhpmcounter18_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter18_rdata = rvfi_csr_mhpmcounter18_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter18_wdata = rvfi_csr_mhpmcounter18_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter18_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter18_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter18_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter18_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter18_wdata)\n`else\n`define rvformal_csr_mhpmcounter18_wires\n`define rvformal_csr_mhpmcounter18_outputs\n`define rvformal_csr_mhpmcounter18_inputs\n`define rvformal_csr_mhpmcounter18_conn\n`define rvformal_csr_mhpmcounter18_conn32\n`define rvformal_csr_mhpmcounter18_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter18_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter18 = 12'hB12; \\\nlocalparam [11:0] csr_sindex_mhpmcounter18 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter18 = 12'hC12; \\\nlocalparam [11:0] csr_mindex_mhpmcounter18h = 12'hB92; \\\nlocalparam [11:0] csr_sindex_mhpmcounter18h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter18h = 12'hC92; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER19\n`define rvformal_csr_mhpmcounter19_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata;\n`define rvformal_csr_mhpmcounter19_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata\n`define rvformal_csr_mhpmcounter19_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata\n`define rvformal_csr_mhpmcounter19_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata\n`define rvformal_csr_mhpmcounter19_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter19_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter19_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter19_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter19_wdata\n`define rvformal_csr_mhpmcounter19_conn, \\\n  .rvfi_csr_mhpmcounter19_rmask (rvfi_csr_mhpmcounter19_rmask), \\\n  .rvfi_csr_mhpmcounter19_wmask (rvfi_csr_mhpmcounter19_wmask), \\\n  .rvfi_csr_mhpmcounter19_rdata (rvfi_csr_mhpmcounter19_rdata), \\\n  .rvfi_csr_mhpmcounter19_wdata (rvfi_csr_mhpmcounter19_wdata)\n`define rvformal_csr_mhpmcounter19_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter19_rmask (rvfi_csr_mhpmcounter19_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter19_wmask (rvfi_csr_mhpmcounter19_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter19_rdata (rvfi_csr_mhpmcounter19_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter19_wdata (rvfi_csr_mhpmcounter19_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter19_conn32, \\\n  .rvfi_csr_mhpmcounter19_rmask  (rvfi_csr_mhpmcounter19_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter19_wmask  (rvfi_csr_mhpmcounter19_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter19_rdata  (rvfi_csr_mhpmcounter19_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter19_wdata  (rvfi_csr_mhpmcounter19_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter19h_rmask (rvfi_csr_mhpmcounter19_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter19h_wmask (rvfi_csr_mhpmcounter19_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter19h_rdata (rvfi_csr_mhpmcounter19_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter19h_wdata (rvfi_csr_mhpmcounter19_wdata[63:32])\n`define rvformal_csr_mhpmcounter19_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter19_rmask = rvfi_csr_mhpmcounter19_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter19_wmask = rvfi_csr_mhpmcounter19_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter19_rdata = rvfi_csr_mhpmcounter19_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter19_wdata = rvfi_csr_mhpmcounter19_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter19_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter19_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter19_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter19_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter19_wdata)\n`else\n`define rvformal_csr_mhpmcounter19_wires\n`define rvformal_csr_mhpmcounter19_outputs\n`define rvformal_csr_mhpmcounter19_inputs\n`define rvformal_csr_mhpmcounter19_conn\n`define rvformal_csr_mhpmcounter19_conn32\n`define rvformal_csr_mhpmcounter19_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter19_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter19 = 12'hB13; \\\nlocalparam [11:0] csr_sindex_mhpmcounter19 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter19 = 12'hC13; \\\nlocalparam [11:0] csr_mindex_mhpmcounter19h = 12'hB93; \\\nlocalparam [11:0] csr_sindex_mhpmcounter19h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter19h = 12'hC93; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER20\n`define rvformal_csr_mhpmcounter20_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata;\n`define rvformal_csr_mhpmcounter20_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata\n`define rvformal_csr_mhpmcounter20_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata\n`define rvformal_csr_mhpmcounter20_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata\n`define rvformal_csr_mhpmcounter20_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter20_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter20_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter20_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter20_wdata\n`define rvformal_csr_mhpmcounter20_conn, \\\n  .rvfi_csr_mhpmcounter20_rmask (rvfi_csr_mhpmcounter20_rmask), \\\n  .rvfi_csr_mhpmcounter20_wmask (rvfi_csr_mhpmcounter20_wmask), \\\n  .rvfi_csr_mhpmcounter20_rdata (rvfi_csr_mhpmcounter20_rdata), \\\n  .rvfi_csr_mhpmcounter20_wdata (rvfi_csr_mhpmcounter20_wdata)\n`define rvformal_csr_mhpmcounter20_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter20_rmask (rvfi_csr_mhpmcounter20_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter20_wmask (rvfi_csr_mhpmcounter20_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter20_rdata (rvfi_csr_mhpmcounter20_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter20_wdata (rvfi_csr_mhpmcounter20_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter20_conn32, \\\n  .rvfi_csr_mhpmcounter20_rmask  (rvfi_csr_mhpmcounter20_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter20_wmask  (rvfi_csr_mhpmcounter20_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter20_rdata  (rvfi_csr_mhpmcounter20_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter20_wdata  (rvfi_csr_mhpmcounter20_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter20h_rmask (rvfi_csr_mhpmcounter20_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter20h_wmask (rvfi_csr_mhpmcounter20_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter20h_rdata (rvfi_csr_mhpmcounter20_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter20h_wdata (rvfi_csr_mhpmcounter20_wdata[63:32])\n`define rvformal_csr_mhpmcounter20_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter20_rmask = rvfi_csr_mhpmcounter20_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter20_wmask = rvfi_csr_mhpmcounter20_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter20_rdata = rvfi_csr_mhpmcounter20_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter20_wdata = rvfi_csr_mhpmcounter20_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter20_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter20_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter20_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter20_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter20_wdata)\n`else\n`define rvformal_csr_mhpmcounter20_wires\n`define rvformal_csr_mhpmcounter20_outputs\n`define rvformal_csr_mhpmcounter20_inputs\n`define rvformal_csr_mhpmcounter20_conn\n`define rvformal_csr_mhpmcounter20_conn32\n`define rvformal_csr_mhpmcounter20_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter20_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter20 = 12'hB14; \\\nlocalparam [11:0] csr_sindex_mhpmcounter20 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter20 = 12'hC14; \\\nlocalparam [11:0] csr_mindex_mhpmcounter20h = 12'hB94; \\\nlocalparam [11:0] csr_sindex_mhpmcounter20h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter20h = 12'hC94; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER21\n`define rvformal_csr_mhpmcounter21_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata;\n`define rvformal_csr_mhpmcounter21_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata\n`define rvformal_csr_mhpmcounter21_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata\n`define rvformal_csr_mhpmcounter21_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata\n`define rvformal_csr_mhpmcounter21_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter21_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter21_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter21_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter21_wdata\n`define rvformal_csr_mhpmcounter21_conn, \\\n  .rvfi_csr_mhpmcounter21_rmask (rvfi_csr_mhpmcounter21_rmask), \\\n  .rvfi_csr_mhpmcounter21_wmask (rvfi_csr_mhpmcounter21_wmask), \\\n  .rvfi_csr_mhpmcounter21_rdata (rvfi_csr_mhpmcounter21_rdata), \\\n  .rvfi_csr_mhpmcounter21_wdata (rvfi_csr_mhpmcounter21_wdata)\n`define rvformal_csr_mhpmcounter21_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter21_rmask (rvfi_csr_mhpmcounter21_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter21_wmask (rvfi_csr_mhpmcounter21_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter21_rdata (rvfi_csr_mhpmcounter21_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter21_wdata (rvfi_csr_mhpmcounter21_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter21_conn32, \\\n  .rvfi_csr_mhpmcounter21_rmask  (rvfi_csr_mhpmcounter21_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter21_wmask  (rvfi_csr_mhpmcounter21_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter21_rdata  (rvfi_csr_mhpmcounter21_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter21_wdata  (rvfi_csr_mhpmcounter21_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter21h_rmask (rvfi_csr_mhpmcounter21_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter21h_wmask (rvfi_csr_mhpmcounter21_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter21h_rdata (rvfi_csr_mhpmcounter21_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter21h_wdata (rvfi_csr_mhpmcounter21_wdata[63:32])\n`define rvformal_csr_mhpmcounter21_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter21_rmask = rvfi_csr_mhpmcounter21_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter21_wmask = rvfi_csr_mhpmcounter21_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter21_rdata = rvfi_csr_mhpmcounter21_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter21_wdata = rvfi_csr_mhpmcounter21_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter21_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter21_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter21_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter21_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter21_wdata)\n`else\n`define rvformal_csr_mhpmcounter21_wires\n`define rvformal_csr_mhpmcounter21_outputs\n`define rvformal_csr_mhpmcounter21_inputs\n`define rvformal_csr_mhpmcounter21_conn\n`define rvformal_csr_mhpmcounter21_conn32\n`define rvformal_csr_mhpmcounter21_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter21_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter21 = 12'hB15; \\\nlocalparam [11:0] csr_sindex_mhpmcounter21 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter21 = 12'hC15; \\\nlocalparam [11:0] csr_mindex_mhpmcounter21h = 12'hB95; \\\nlocalparam [11:0] csr_sindex_mhpmcounter21h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter21h = 12'hC95; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER22\n`define rvformal_csr_mhpmcounter22_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata;\n`define rvformal_csr_mhpmcounter22_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata\n`define rvformal_csr_mhpmcounter22_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata\n`define rvformal_csr_mhpmcounter22_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata\n`define rvformal_csr_mhpmcounter22_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter22_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter22_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter22_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter22_wdata\n`define rvformal_csr_mhpmcounter22_conn, \\\n  .rvfi_csr_mhpmcounter22_rmask (rvfi_csr_mhpmcounter22_rmask), \\\n  .rvfi_csr_mhpmcounter22_wmask (rvfi_csr_mhpmcounter22_wmask), \\\n  .rvfi_csr_mhpmcounter22_rdata (rvfi_csr_mhpmcounter22_rdata), \\\n  .rvfi_csr_mhpmcounter22_wdata (rvfi_csr_mhpmcounter22_wdata)\n`define rvformal_csr_mhpmcounter22_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter22_rmask (rvfi_csr_mhpmcounter22_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter22_wmask (rvfi_csr_mhpmcounter22_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter22_rdata (rvfi_csr_mhpmcounter22_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter22_wdata (rvfi_csr_mhpmcounter22_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter22_conn32, \\\n  .rvfi_csr_mhpmcounter22_rmask  (rvfi_csr_mhpmcounter22_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter22_wmask  (rvfi_csr_mhpmcounter22_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter22_rdata  (rvfi_csr_mhpmcounter22_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter22_wdata  (rvfi_csr_mhpmcounter22_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter22h_rmask (rvfi_csr_mhpmcounter22_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter22h_wmask (rvfi_csr_mhpmcounter22_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter22h_rdata (rvfi_csr_mhpmcounter22_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter22h_wdata (rvfi_csr_mhpmcounter22_wdata[63:32])\n`define rvformal_csr_mhpmcounter22_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter22_rmask = rvfi_csr_mhpmcounter22_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter22_wmask = rvfi_csr_mhpmcounter22_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter22_rdata = rvfi_csr_mhpmcounter22_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter22_wdata = rvfi_csr_mhpmcounter22_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter22_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter22_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter22_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter22_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter22_wdata)\n`else\n`define rvformal_csr_mhpmcounter22_wires\n`define rvformal_csr_mhpmcounter22_outputs\n`define rvformal_csr_mhpmcounter22_inputs\n`define rvformal_csr_mhpmcounter22_conn\n`define rvformal_csr_mhpmcounter22_conn32\n`define rvformal_csr_mhpmcounter22_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter22_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter22 = 12'hB16; \\\nlocalparam [11:0] csr_sindex_mhpmcounter22 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter22 = 12'hC16; \\\nlocalparam [11:0] csr_mindex_mhpmcounter22h = 12'hB96; \\\nlocalparam [11:0] csr_sindex_mhpmcounter22h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter22h = 12'hC96; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER23\n`define rvformal_csr_mhpmcounter23_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata;\n`define rvformal_csr_mhpmcounter23_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata\n`define rvformal_csr_mhpmcounter23_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata\n`define rvformal_csr_mhpmcounter23_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata\n`define rvformal_csr_mhpmcounter23_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter23_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter23_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter23_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter23_wdata\n`define rvformal_csr_mhpmcounter23_conn, \\\n  .rvfi_csr_mhpmcounter23_rmask (rvfi_csr_mhpmcounter23_rmask), \\\n  .rvfi_csr_mhpmcounter23_wmask (rvfi_csr_mhpmcounter23_wmask), \\\n  .rvfi_csr_mhpmcounter23_rdata (rvfi_csr_mhpmcounter23_rdata), \\\n  .rvfi_csr_mhpmcounter23_wdata (rvfi_csr_mhpmcounter23_wdata)\n`define rvformal_csr_mhpmcounter23_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter23_rmask (rvfi_csr_mhpmcounter23_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter23_wmask (rvfi_csr_mhpmcounter23_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter23_rdata (rvfi_csr_mhpmcounter23_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter23_wdata (rvfi_csr_mhpmcounter23_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter23_conn32, \\\n  .rvfi_csr_mhpmcounter23_rmask  (rvfi_csr_mhpmcounter23_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter23_wmask  (rvfi_csr_mhpmcounter23_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter23_rdata  (rvfi_csr_mhpmcounter23_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter23_wdata  (rvfi_csr_mhpmcounter23_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter23h_rmask (rvfi_csr_mhpmcounter23_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter23h_wmask (rvfi_csr_mhpmcounter23_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter23h_rdata (rvfi_csr_mhpmcounter23_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter23h_wdata (rvfi_csr_mhpmcounter23_wdata[63:32])\n`define rvformal_csr_mhpmcounter23_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter23_rmask = rvfi_csr_mhpmcounter23_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter23_wmask = rvfi_csr_mhpmcounter23_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter23_rdata = rvfi_csr_mhpmcounter23_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter23_wdata = rvfi_csr_mhpmcounter23_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter23_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter23_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter23_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter23_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter23_wdata)\n`else\n`define rvformal_csr_mhpmcounter23_wires\n`define rvformal_csr_mhpmcounter23_outputs\n`define rvformal_csr_mhpmcounter23_inputs\n`define rvformal_csr_mhpmcounter23_conn\n`define rvformal_csr_mhpmcounter23_conn32\n`define rvformal_csr_mhpmcounter23_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter23_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter23 = 12'hB17; \\\nlocalparam [11:0] csr_sindex_mhpmcounter23 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter23 = 12'hC17; \\\nlocalparam [11:0] csr_mindex_mhpmcounter23h = 12'hB97; \\\nlocalparam [11:0] csr_sindex_mhpmcounter23h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter23h = 12'hC97; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER24\n`define rvformal_csr_mhpmcounter24_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata;\n`define rvformal_csr_mhpmcounter24_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata\n`define rvformal_csr_mhpmcounter24_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata\n`define rvformal_csr_mhpmcounter24_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata\n`define rvformal_csr_mhpmcounter24_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter24_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter24_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter24_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter24_wdata\n`define rvformal_csr_mhpmcounter24_conn, \\\n  .rvfi_csr_mhpmcounter24_rmask (rvfi_csr_mhpmcounter24_rmask), \\\n  .rvfi_csr_mhpmcounter24_wmask (rvfi_csr_mhpmcounter24_wmask), \\\n  .rvfi_csr_mhpmcounter24_rdata (rvfi_csr_mhpmcounter24_rdata), \\\n  .rvfi_csr_mhpmcounter24_wdata (rvfi_csr_mhpmcounter24_wdata)\n`define rvformal_csr_mhpmcounter24_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter24_rmask (rvfi_csr_mhpmcounter24_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter24_wmask (rvfi_csr_mhpmcounter24_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter24_rdata (rvfi_csr_mhpmcounter24_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter24_wdata (rvfi_csr_mhpmcounter24_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter24_conn32, \\\n  .rvfi_csr_mhpmcounter24_rmask  (rvfi_csr_mhpmcounter24_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter24_wmask  (rvfi_csr_mhpmcounter24_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter24_rdata  (rvfi_csr_mhpmcounter24_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter24_wdata  (rvfi_csr_mhpmcounter24_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter24h_rmask (rvfi_csr_mhpmcounter24_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter24h_wmask (rvfi_csr_mhpmcounter24_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter24h_rdata (rvfi_csr_mhpmcounter24_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter24h_wdata (rvfi_csr_mhpmcounter24_wdata[63:32])\n`define rvformal_csr_mhpmcounter24_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter24_rmask = rvfi_csr_mhpmcounter24_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter24_wmask = rvfi_csr_mhpmcounter24_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter24_rdata = rvfi_csr_mhpmcounter24_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter24_wdata = rvfi_csr_mhpmcounter24_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter24_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter24_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter24_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter24_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter24_wdata)\n`else\n`define rvformal_csr_mhpmcounter24_wires\n`define rvformal_csr_mhpmcounter24_outputs\n`define rvformal_csr_mhpmcounter24_inputs\n`define rvformal_csr_mhpmcounter24_conn\n`define rvformal_csr_mhpmcounter24_conn32\n`define rvformal_csr_mhpmcounter24_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter24_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter24 = 12'hB18; \\\nlocalparam [11:0] csr_sindex_mhpmcounter24 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter24 = 12'hC18; \\\nlocalparam [11:0] csr_mindex_mhpmcounter24h = 12'hB98; \\\nlocalparam [11:0] csr_sindex_mhpmcounter24h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter24h = 12'hC98; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER25\n`define rvformal_csr_mhpmcounter25_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata;\n`define rvformal_csr_mhpmcounter25_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata\n`define rvformal_csr_mhpmcounter25_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata\n`define rvformal_csr_mhpmcounter25_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata\n`define rvformal_csr_mhpmcounter25_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter25_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter25_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter25_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter25_wdata\n`define rvformal_csr_mhpmcounter25_conn, \\\n  .rvfi_csr_mhpmcounter25_rmask (rvfi_csr_mhpmcounter25_rmask), \\\n  .rvfi_csr_mhpmcounter25_wmask (rvfi_csr_mhpmcounter25_wmask), \\\n  .rvfi_csr_mhpmcounter25_rdata (rvfi_csr_mhpmcounter25_rdata), \\\n  .rvfi_csr_mhpmcounter25_wdata (rvfi_csr_mhpmcounter25_wdata)\n`define rvformal_csr_mhpmcounter25_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter25_rmask (rvfi_csr_mhpmcounter25_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter25_wmask (rvfi_csr_mhpmcounter25_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter25_rdata (rvfi_csr_mhpmcounter25_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter25_wdata (rvfi_csr_mhpmcounter25_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter25_conn32, \\\n  .rvfi_csr_mhpmcounter25_rmask  (rvfi_csr_mhpmcounter25_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter25_wmask  (rvfi_csr_mhpmcounter25_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter25_rdata  (rvfi_csr_mhpmcounter25_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter25_wdata  (rvfi_csr_mhpmcounter25_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter25h_rmask (rvfi_csr_mhpmcounter25_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter25h_wmask (rvfi_csr_mhpmcounter25_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter25h_rdata (rvfi_csr_mhpmcounter25_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter25h_wdata (rvfi_csr_mhpmcounter25_wdata[63:32])\n`define rvformal_csr_mhpmcounter25_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter25_rmask = rvfi_csr_mhpmcounter25_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter25_wmask = rvfi_csr_mhpmcounter25_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter25_rdata = rvfi_csr_mhpmcounter25_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter25_wdata = rvfi_csr_mhpmcounter25_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter25_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter25_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter25_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter25_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter25_wdata)\n`else\n`define rvformal_csr_mhpmcounter25_wires\n`define rvformal_csr_mhpmcounter25_outputs\n`define rvformal_csr_mhpmcounter25_inputs\n`define rvformal_csr_mhpmcounter25_conn\n`define rvformal_csr_mhpmcounter25_conn32\n`define rvformal_csr_mhpmcounter25_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter25_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter25 = 12'hB19; \\\nlocalparam [11:0] csr_sindex_mhpmcounter25 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter25 = 12'hC19; \\\nlocalparam [11:0] csr_mindex_mhpmcounter25h = 12'hB99; \\\nlocalparam [11:0] csr_sindex_mhpmcounter25h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter25h = 12'hC99; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER26\n`define rvformal_csr_mhpmcounter26_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata;\n`define rvformal_csr_mhpmcounter26_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata\n`define rvformal_csr_mhpmcounter26_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata\n`define rvformal_csr_mhpmcounter26_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata\n`define rvformal_csr_mhpmcounter26_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter26_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter26_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter26_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter26_wdata\n`define rvformal_csr_mhpmcounter26_conn, \\\n  .rvfi_csr_mhpmcounter26_rmask (rvfi_csr_mhpmcounter26_rmask), \\\n  .rvfi_csr_mhpmcounter26_wmask (rvfi_csr_mhpmcounter26_wmask), \\\n  .rvfi_csr_mhpmcounter26_rdata (rvfi_csr_mhpmcounter26_rdata), \\\n  .rvfi_csr_mhpmcounter26_wdata (rvfi_csr_mhpmcounter26_wdata)\n`define rvformal_csr_mhpmcounter26_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter26_rmask (rvfi_csr_mhpmcounter26_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter26_wmask (rvfi_csr_mhpmcounter26_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter26_rdata (rvfi_csr_mhpmcounter26_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter26_wdata (rvfi_csr_mhpmcounter26_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter26_conn32, \\\n  .rvfi_csr_mhpmcounter26_rmask  (rvfi_csr_mhpmcounter26_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter26_wmask  (rvfi_csr_mhpmcounter26_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter26_rdata  (rvfi_csr_mhpmcounter26_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter26_wdata  (rvfi_csr_mhpmcounter26_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter26h_rmask (rvfi_csr_mhpmcounter26_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter26h_wmask (rvfi_csr_mhpmcounter26_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter26h_rdata (rvfi_csr_mhpmcounter26_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter26h_wdata (rvfi_csr_mhpmcounter26_wdata[63:32])\n`define rvformal_csr_mhpmcounter26_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter26_rmask = rvfi_csr_mhpmcounter26_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter26_wmask = rvfi_csr_mhpmcounter26_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter26_rdata = rvfi_csr_mhpmcounter26_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter26_wdata = rvfi_csr_mhpmcounter26_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter26_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter26_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter26_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter26_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter26_wdata)\n`else\n`define rvformal_csr_mhpmcounter26_wires\n`define rvformal_csr_mhpmcounter26_outputs\n`define rvformal_csr_mhpmcounter26_inputs\n`define rvformal_csr_mhpmcounter26_conn\n`define rvformal_csr_mhpmcounter26_conn32\n`define rvformal_csr_mhpmcounter26_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter26_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter26 = 12'hB1A; \\\nlocalparam [11:0] csr_sindex_mhpmcounter26 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter26 = 12'hC1A; \\\nlocalparam [11:0] csr_mindex_mhpmcounter26h = 12'hB9A; \\\nlocalparam [11:0] csr_sindex_mhpmcounter26h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter26h = 12'hC9A; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER27\n`define rvformal_csr_mhpmcounter27_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata;\n`define rvformal_csr_mhpmcounter27_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata\n`define rvformal_csr_mhpmcounter27_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata\n`define rvformal_csr_mhpmcounter27_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata\n`define rvformal_csr_mhpmcounter27_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter27_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter27_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter27_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter27_wdata\n`define rvformal_csr_mhpmcounter27_conn, \\\n  .rvfi_csr_mhpmcounter27_rmask (rvfi_csr_mhpmcounter27_rmask), \\\n  .rvfi_csr_mhpmcounter27_wmask (rvfi_csr_mhpmcounter27_wmask), \\\n  .rvfi_csr_mhpmcounter27_rdata (rvfi_csr_mhpmcounter27_rdata), \\\n  .rvfi_csr_mhpmcounter27_wdata (rvfi_csr_mhpmcounter27_wdata)\n`define rvformal_csr_mhpmcounter27_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter27_rmask (rvfi_csr_mhpmcounter27_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter27_wmask (rvfi_csr_mhpmcounter27_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter27_rdata (rvfi_csr_mhpmcounter27_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter27_wdata (rvfi_csr_mhpmcounter27_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter27_conn32, \\\n  .rvfi_csr_mhpmcounter27_rmask  (rvfi_csr_mhpmcounter27_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter27_wmask  (rvfi_csr_mhpmcounter27_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter27_rdata  (rvfi_csr_mhpmcounter27_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter27_wdata  (rvfi_csr_mhpmcounter27_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter27h_rmask (rvfi_csr_mhpmcounter27_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter27h_wmask (rvfi_csr_mhpmcounter27_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter27h_rdata (rvfi_csr_mhpmcounter27_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter27h_wdata (rvfi_csr_mhpmcounter27_wdata[63:32])\n`define rvformal_csr_mhpmcounter27_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter27_rmask = rvfi_csr_mhpmcounter27_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter27_wmask = rvfi_csr_mhpmcounter27_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter27_rdata = rvfi_csr_mhpmcounter27_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter27_wdata = rvfi_csr_mhpmcounter27_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter27_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter27_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter27_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter27_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter27_wdata)\n`else\n`define rvformal_csr_mhpmcounter27_wires\n`define rvformal_csr_mhpmcounter27_outputs\n`define rvformal_csr_mhpmcounter27_inputs\n`define rvformal_csr_mhpmcounter27_conn\n`define rvformal_csr_mhpmcounter27_conn32\n`define rvformal_csr_mhpmcounter27_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter27_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter27 = 12'hB1B; \\\nlocalparam [11:0] csr_sindex_mhpmcounter27 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter27 = 12'hC1B; \\\nlocalparam [11:0] csr_mindex_mhpmcounter27h = 12'hB9B; \\\nlocalparam [11:0] csr_sindex_mhpmcounter27h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter27h = 12'hC9B; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER28\n`define rvformal_csr_mhpmcounter28_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata;\n`define rvformal_csr_mhpmcounter28_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata\n`define rvformal_csr_mhpmcounter28_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata\n`define rvformal_csr_mhpmcounter28_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata\n`define rvformal_csr_mhpmcounter28_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter28_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter28_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter28_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter28_wdata\n`define rvformal_csr_mhpmcounter28_conn, \\\n  .rvfi_csr_mhpmcounter28_rmask (rvfi_csr_mhpmcounter28_rmask), \\\n  .rvfi_csr_mhpmcounter28_wmask (rvfi_csr_mhpmcounter28_wmask), \\\n  .rvfi_csr_mhpmcounter28_rdata (rvfi_csr_mhpmcounter28_rdata), \\\n  .rvfi_csr_mhpmcounter28_wdata (rvfi_csr_mhpmcounter28_wdata)\n`define rvformal_csr_mhpmcounter28_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter28_rmask (rvfi_csr_mhpmcounter28_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter28_wmask (rvfi_csr_mhpmcounter28_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter28_rdata (rvfi_csr_mhpmcounter28_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter28_wdata (rvfi_csr_mhpmcounter28_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter28_conn32, \\\n  .rvfi_csr_mhpmcounter28_rmask  (rvfi_csr_mhpmcounter28_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter28_wmask  (rvfi_csr_mhpmcounter28_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter28_rdata  (rvfi_csr_mhpmcounter28_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter28_wdata  (rvfi_csr_mhpmcounter28_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter28h_rmask (rvfi_csr_mhpmcounter28_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter28h_wmask (rvfi_csr_mhpmcounter28_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter28h_rdata (rvfi_csr_mhpmcounter28_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter28h_wdata (rvfi_csr_mhpmcounter28_wdata[63:32])\n`define rvformal_csr_mhpmcounter28_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter28_rmask = rvfi_csr_mhpmcounter28_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter28_wmask = rvfi_csr_mhpmcounter28_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter28_rdata = rvfi_csr_mhpmcounter28_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter28_wdata = rvfi_csr_mhpmcounter28_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter28_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter28_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter28_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter28_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter28_wdata)\n`else\n`define rvformal_csr_mhpmcounter28_wires\n`define rvformal_csr_mhpmcounter28_outputs\n`define rvformal_csr_mhpmcounter28_inputs\n`define rvformal_csr_mhpmcounter28_conn\n`define rvformal_csr_mhpmcounter28_conn32\n`define rvformal_csr_mhpmcounter28_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter28_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter28 = 12'hB1C; \\\nlocalparam [11:0] csr_sindex_mhpmcounter28 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter28 = 12'hC1C; \\\nlocalparam [11:0] csr_mindex_mhpmcounter28h = 12'hB9C; \\\nlocalparam [11:0] csr_sindex_mhpmcounter28h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter28h = 12'hC9C; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER29\n`define rvformal_csr_mhpmcounter29_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata;\n`define rvformal_csr_mhpmcounter29_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata\n`define rvformal_csr_mhpmcounter29_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata\n`define rvformal_csr_mhpmcounter29_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata\n`define rvformal_csr_mhpmcounter29_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter29_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter29_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter29_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter29_wdata\n`define rvformal_csr_mhpmcounter29_conn, \\\n  .rvfi_csr_mhpmcounter29_rmask (rvfi_csr_mhpmcounter29_rmask), \\\n  .rvfi_csr_mhpmcounter29_wmask (rvfi_csr_mhpmcounter29_wmask), \\\n  .rvfi_csr_mhpmcounter29_rdata (rvfi_csr_mhpmcounter29_rdata), \\\n  .rvfi_csr_mhpmcounter29_wdata (rvfi_csr_mhpmcounter29_wdata)\n`define rvformal_csr_mhpmcounter29_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter29_rmask (rvfi_csr_mhpmcounter29_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter29_wmask (rvfi_csr_mhpmcounter29_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter29_rdata (rvfi_csr_mhpmcounter29_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter29_wdata (rvfi_csr_mhpmcounter29_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter29_conn32, \\\n  .rvfi_csr_mhpmcounter29_rmask  (rvfi_csr_mhpmcounter29_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter29_wmask  (rvfi_csr_mhpmcounter29_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter29_rdata  (rvfi_csr_mhpmcounter29_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter29_wdata  (rvfi_csr_mhpmcounter29_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter29h_rmask (rvfi_csr_mhpmcounter29_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter29h_wmask (rvfi_csr_mhpmcounter29_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter29h_rdata (rvfi_csr_mhpmcounter29_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter29h_wdata (rvfi_csr_mhpmcounter29_wdata[63:32])\n`define rvformal_csr_mhpmcounter29_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter29_rmask = rvfi_csr_mhpmcounter29_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter29_wmask = rvfi_csr_mhpmcounter29_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter29_rdata = rvfi_csr_mhpmcounter29_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter29_wdata = rvfi_csr_mhpmcounter29_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter29_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter29_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter29_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter29_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter29_wdata)\n`else\n`define rvformal_csr_mhpmcounter29_wires\n`define rvformal_csr_mhpmcounter29_outputs\n`define rvformal_csr_mhpmcounter29_inputs\n`define rvformal_csr_mhpmcounter29_conn\n`define rvformal_csr_mhpmcounter29_conn32\n`define rvformal_csr_mhpmcounter29_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter29_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter29 = 12'hB1D; \\\nlocalparam [11:0] csr_sindex_mhpmcounter29 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter29 = 12'hC1D; \\\nlocalparam [11:0] csr_mindex_mhpmcounter29h = 12'hB9D; \\\nlocalparam [11:0] csr_sindex_mhpmcounter29h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter29h = 12'hC9D; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER30\n`define rvformal_csr_mhpmcounter30_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata;\n`define rvformal_csr_mhpmcounter30_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata\n`define rvformal_csr_mhpmcounter30_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata\n`define rvformal_csr_mhpmcounter30_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata\n`define rvformal_csr_mhpmcounter30_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter30_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter30_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter30_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter30_wdata\n`define rvformal_csr_mhpmcounter30_conn, \\\n  .rvfi_csr_mhpmcounter30_rmask (rvfi_csr_mhpmcounter30_rmask), \\\n  .rvfi_csr_mhpmcounter30_wmask (rvfi_csr_mhpmcounter30_wmask), \\\n  .rvfi_csr_mhpmcounter30_rdata (rvfi_csr_mhpmcounter30_rdata), \\\n  .rvfi_csr_mhpmcounter30_wdata (rvfi_csr_mhpmcounter30_wdata)\n`define rvformal_csr_mhpmcounter30_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter30_rmask (rvfi_csr_mhpmcounter30_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter30_wmask (rvfi_csr_mhpmcounter30_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter30_rdata (rvfi_csr_mhpmcounter30_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter30_wdata (rvfi_csr_mhpmcounter30_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter30_conn32, \\\n  .rvfi_csr_mhpmcounter30_rmask  (rvfi_csr_mhpmcounter30_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter30_wmask  (rvfi_csr_mhpmcounter30_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter30_rdata  (rvfi_csr_mhpmcounter30_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter30_wdata  (rvfi_csr_mhpmcounter30_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter30h_rmask (rvfi_csr_mhpmcounter30_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter30h_wmask (rvfi_csr_mhpmcounter30_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter30h_rdata (rvfi_csr_mhpmcounter30_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter30h_wdata (rvfi_csr_mhpmcounter30_wdata[63:32])\n`define rvformal_csr_mhpmcounter30_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter30_rmask = rvfi_csr_mhpmcounter30_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter30_wmask = rvfi_csr_mhpmcounter30_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter30_rdata = rvfi_csr_mhpmcounter30_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter30_wdata = rvfi_csr_mhpmcounter30_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter30_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter30_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter30_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter30_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter30_wdata)\n`else\n`define rvformal_csr_mhpmcounter30_wires\n`define rvformal_csr_mhpmcounter30_outputs\n`define rvformal_csr_mhpmcounter30_inputs\n`define rvformal_csr_mhpmcounter30_conn\n`define rvformal_csr_mhpmcounter30_conn32\n`define rvformal_csr_mhpmcounter30_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter30_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter30 = 12'hB1E; \\\nlocalparam [11:0] csr_sindex_mhpmcounter30 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter30 = 12'hC1E; \\\nlocalparam [11:0] csr_mindex_mhpmcounter30h = 12'hB9E; \\\nlocalparam [11:0] csr_sindex_mhpmcounter30h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter30h = 12'hC9E; \\\n\n`ifdef RISCV_FORMAL_CSR_MHPMCOUNTER31\n`define rvformal_csr_mhpmcounter31_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata;\n`define rvformal_csr_mhpmcounter31_outputs, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata, \\\n  output [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata\n`define rvformal_csr_mhpmcounter31_channel_outputs, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata, \\\n  output [64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata\n`define rvformal_csr_mhpmcounter31_inputs, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata, \\\n  input [`RISCV_FORMAL_NRET * 64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata\n`define rvformal_csr_mhpmcounter31_channel_inputs, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter31_rmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter31_wmask, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter31_rdata, \\\n  input [64 - 1 : 0] rvfi_csr_mhpmcounter31_wdata\n`define rvformal_csr_mhpmcounter31_conn, \\\n  .rvfi_csr_mhpmcounter31_rmask (rvfi_csr_mhpmcounter31_rmask), \\\n  .rvfi_csr_mhpmcounter31_wmask (rvfi_csr_mhpmcounter31_wmask), \\\n  .rvfi_csr_mhpmcounter31_rdata (rvfi_csr_mhpmcounter31_rdata), \\\n  .rvfi_csr_mhpmcounter31_wdata (rvfi_csr_mhpmcounter31_wdata)\n`define rvformal_csr_mhpmcounter31_channel_conn(_idx), \\\n  .rvfi_csr_mhpmcounter31_rmask (rvfi_csr_mhpmcounter31_rmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter31_wmask (rvfi_csr_mhpmcounter31_wmask [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter31_rdata (rvfi_csr_mhpmcounter31_rdata [(_idx)*(64) +: 64]), \\\n  .rvfi_csr_mhpmcounter31_wdata (rvfi_csr_mhpmcounter31_wdata [(_idx)*(64) +: 64])\n`define rvformal_csr_mhpmcounter31_conn32, \\\n  .rvfi_csr_mhpmcounter31_rmask  (rvfi_csr_mhpmcounter31_rmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter31_wmask  (rvfi_csr_mhpmcounter31_wmask[31: 0]), \\\n  .rvfi_csr_mhpmcounter31_rdata  (rvfi_csr_mhpmcounter31_rdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter31_wdata  (rvfi_csr_mhpmcounter31_wdata[31: 0]), \\\n  .rvfi_csr_mhpmcounter31h_rmask (rvfi_csr_mhpmcounter31_rmask[63:32]), \\\n  .rvfi_csr_mhpmcounter31h_wmask (rvfi_csr_mhpmcounter31_wmask[63:32]), \\\n  .rvfi_csr_mhpmcounter31h_rdata (rvfi_csr_mhpmcounter31_rdata[63:32]), \\\n  .rvfi_csr_mhpmcounter31h_wdata (rvfi_csr_mhpmcounter31_wdata[63:32])\n`define rvformal_csr_mhpmcounter31_channel(_idx) \\\n  wire [64 - 1 : 0] csr_mhpmcounter31_rmask = rvfi_csr_mhpmcounter31_rmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter31_wmask = rvfi_csr_mhpmcounter31_wmask [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter31_rdata = rvfi_csr_mhpmcounter31_rdata [(_idx)*(64) +: 64]; \\\n  wire [64 - 1 : 0] csr_mhpmcounter31_wdata = rvfi_csr_mhpmcounter31_wdata [(_idx)*(64) +: 64];\n`define rvformal_csr_mhpmcounter31_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter31_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter31_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter31_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 64, csr_mhpmcounter31_wdata)\n`else\n`define rvformal_csr_mhpmcounter31_wires\n`define rvformal_csr_mhpmcounter31_outputs\n`define rvformal_csr_mhpmcounter31_inputs\n`define rvformal_csr_mhpmcounter31_conn\n`define rvformal_csr_mhpmcounter31_conn32\n`define rvformal_csr_mhpmcounter31_channel(_idx)\n`endif\n`define rvformal_csr_mhpmcounter31_indices \\\nlocalparam [11:0] csr_mindex_mhpmcounter31 = 12'hB1F; \\\nlocalparam [11:0] csr_sindex_mhpmcounter31 = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter31 = 12'hC1F; \\\nlocalparam [11:0] csr_mindex_mhpmcounter31h = 12'hB9F; \\\nlocalparam [11:0] csr_sindex_mhpmcounter31h = 12'hFFF; \\\nlocalparam [11:0] csr_uindex_mhpmcounter31h = 12'hC9F; \\\n\n`define RVFI_INDICES \\\n`rvformal_csr_fflags_indices \\\n`rvformal_csr_frm_indices \\\n`rvformal_csr_fcsr_indices \\\n`rvformal_csr_mvendorid_indices \\\n`rvformal_csr_marchid_indices \\\n`rvformal_csr_mimpid_indices \\\n`rvformal_csr_mhartid_indices \\\n`rvformal_csr_mconfigptr_indices \\\n`rvformal_csr_mstatus_indices \\\n`rvformal_csr_mstatush_indices \\\n`rvformal_csr_misa_indices \\\n`rvformal_csr_medeleg_indices \\\n`rvformal_csr_mideleg_indices \\\n`rvformal_csr_mie_indices \\\n`rvformal_csr_mtvec_indices \\\n`rvformal_csr_mcounteren_indices \\\n`rvformal_csr_mscratch_indices \\\n`rvformal_csr_mepc_indices \\\n`rvformal_csr_mcause_indices \\\n`rvformal_csr_mtval_indices \\\n`rvformal_csr_mip_indices \\\n`rvformal_csr_mtinst_indices \\\n`rvformal_csr_mtval2_indices \\\n`rvformal_csr_mcountinhibit_indices \\\n`rvformal_csr_menvcfg_indices \\\n`rvformal_csr_menvcfgh_indices \\\n`rvformal_csr_pmpcfg0_indices \\\n`rvformal_csr_pmpcfg1_indices \\\n`rvformal_csr_pmpcfg2_indices \\\n`rvformal_csr_pmpcfg3_indices \\\n`rvformal_csr_pmpcfg4_indices \\\n`rvformal_csr_pmpcfg5_indices \\\n`rvformal_csr_pmpcfg6_indices \\\n`rvformal_csr_pmpcfg7_indices \\\n`rvformal_csr_pmpcfg8_indices \\\n`rvformal_csr_pmpcfg9_indices \\\n`rvformal_csr_pmpcfg10_indices \\\n`rvformal_csr_pmpcfg11_indices \\\n`rvformal_csr_pmpcfg12_indices \\\n`rvformal_csr_pmpcfg13_indices \\\n`rvformal_csr_pmpcfg14_indices \\\n`rvformal_csr_pmpcfg15_indices \\\n`rvformal_csr_pmpaddr0_indices \\\n`rvformal_csr_pmpaddr1_indices \\\n`rvformal_csr_pmpaddr2_indices \\\n`rvformal_csr_pmpaddr3_indices \\\n`rvformal_csr_pmpaddr4_indices \\\n`rvformal_csr_pmpaddr5_indices \\\n`rvformal_csr_pmpaddr6_indices \\\n`rvformal_csr_pmpaddr7_indices \\\n`rvformal_csr_pmpaddr8_indices \\\n`rvformal_csr_pmpaddr9_indices \\\n`rvformal_csr_pmpaddr10_indices \\\n`rvformal_csr_pmpaddr11_indices \\\n`rvformal_csr_pmpaddr12_indices \\\n`rvformal_csr_pmpaddr13_indices \\\n`rvformal_csr_pmpaddr14_indices \\\n`rvformal_csr_pmpaddr15_indices \\\n`rvformal_csr_pmpaddr16_indices \\\n`rvformal_csr_pmpaddr17_indices \\\n`rvformal_csr_pmpaddr18_indices \\\n`rvformal_csr_pmpaddr19_indices \\\n`rvformal_csr_pmpaddr20_indices \\\n`rvformal_csr_pmpaddr21_indices \\\n`rvformal_csr_pmpaddr22_indices \\\n`rvformal_csr_pmpaddr23_indices \\\n`rvformal_csr_pmpaddr24_indices \\\n`rvformal_csr_pmpaddr25_indices \\\n`rvformal_csr_pmpaddr26_indices \\\n`rvformal_csr_pmpaddr27_indices \\\n`rvformal_csr_pmpaddr28_indices \\\n`rvformal_csr_pmpaddr29_indices \\\n`rvformal_csr_pmpaddr30_indices \\\n`rvformal_csr_pmpaddr31_indices \\\n`rvformal_csr_pmpaddr32_indices \\\n`rvformal_csr_pmpaddr33_indices \\\n`rvformal_csr_pmpaddr34_indices \\\n`rvformal_csr_pmpaddr35_indices \\\n`rvformal_csr_pmpaddr36_indices \\\n`rvformal_csr_pmpaddr37_indices \\\n`rvformal_csr_pmpaddr38_indices \\\n`rvformal_csr_pmpaddr39_indices \\\n`rvformal_csr_pmpaddr40_indices \\\n`rvformal_csr_pmpaddr41_indices \\\n`rvformal_csr_pmpaddr42_indices \\\n`rvformal_csr_pmpaddr43_indices \\\n`rvformal_csr_pmpaddr44_indices \\\n`rvformal_csr_pmpaddr45_indices \\\n`rvformal_csr_pmpaddr46_indices \\\n`rvformal_csr_pmpaddr47_indices \\\n`rvformal_csr_pmpaddr48_indices \\\n`rvformal_csr_pmpaddr49_indices \\\n`rvformal_csr_pmpaddr50_indices \\\n`rvformal_csr_pmpaddr51_indices \\\n`rvformal_csr_pmpaddr52_indices \\\n`rvformal_csr_pmpaddr53_indices \\\n`rvformal_csr_pmpaddr54_indices \\\n`rvformal_csr_pmpaddr55_indices \\\n`rvformal_csr_pmpaddr56_indices \\\n`rvformal_csr_pmpaddr57_indices \\\n`rvformal_csr_pmpaddr58_indices \\\n`rvformal_csr_pmpaddr59_indices \\\n`rvformal_csr_pmpaddr60_indices \\\n`rvformal_csr_pmpaddr61_indices \\\n`rvformal_csr_pmpaddr62_indices \\\n`rvformal_csr_pmpaddr63_indices \\\n`rvformal_csr_mhpmevent3_indices \\\n`rvformal_csr_mhpmevent4_indices \\\n`rvformal_csr_mhpmevent5_indices \\\n`rvformal_csr_mhpmevent6_indices \\\n`rvformal_csr_mhpmevent7_indices \\\n`rvformal_csr_mhpmevent8_indices \\\n`rvformal_csr_mhpmevent9_indices \\\n`rvformal_csr_mhpmevent10_indices \\\n`rvformal_csr_mhpmevent11_indices \\\n`rvformal_csr_mhpmevent12_indices \\\n`rvformal_csr_mhpmevent13_indices \\\n`rvformal_csr_mhpmevent14_indices \\\n`rvformal_csr_mhpmevent15_indices \\\n`rvformal_csr_mhpmevent16_indices \\\n`rvformal_csr_mhpmevent17_indices \\\n`rvformal_csr_mhpmevent18_indices \\\n`rvformal_csr_mhpmevent19_indices \\\n`rvformal_csr_mhpmevent20_indices \\\n`rvformal_csr_mhpmevent21_indices \\\n`rvformal_csr_mhpmevent22_indices \\\n`rvformal_csr_mhpmevent23_indices \\\n`rvformal_csr_mhpmevent24_indices \\\n`rvformal_csr_mhpmevent25_indices \\\n`rvformal_csr_mhpmevent26_indices \\\n`rvformal_csr_mhpmevent27_indices \\\n`rvformal_csr_mhpmevent28_indices \\\n`rvformal_csr_mhpmevent29_indices \\\n`rvformal_csr_mhpmevent30_indices \\\n`rvformal_csr_mhpmevent31_indices \\\n`rvformal_csr_mcycle_indices \\\n`rvformal_csr_time_indices \\\n`rvformal_csr_minstret_indices \\\n`rvformal_csr_mhpmcounter3_indices \\\n`rvformal_csr_mhpmcounter4_indices \\\n`rvformal_csr_mhpmcounter5_indices \\\n`rvformal_csr_mhpmcounter6_indices \\\n`rvformal_csr_mhpmcounter7_indices \\\n`rvformal_csr_mhpmcounter8_indices \\\n`rvformal_csr_mhpmcounter9_indices \\\n`rvformal_csr_mhpmcounter10_indices \\\n`rvformal_csr_mhpmcounter11_indices \\\n`rvformal_csr_mhpmcounter12_indices \\\n`rvformal_csr_mhpmcounter13_indices \\\n`rvformal_csr_mhpmcounter14_indices \\\n`rvformal_csr_mhpmcounter15_indices \\\n`rvformal_csr_mhpmcounter16_indices \\\n`rvformal_csr_mhpmcounter17_indices \\\n`rvformal_csr_mhpmcounter18_indices \\\n`rvformal_csr_mhpmcounter19_indices \\\n`rvformal_csr_mhpmcounter20_indices \\\n`rvformal_csr_mhpmcounter21_indices \\\n`rvformal_csr_mhpmcounter22_indices \\\n`rvformal_csr_mhpmcounter23_indices \\\n`rvformal_csr_mhpmcounter24_indices \\\n`rvformal_csr_mhpmcounter25_indices \\\n`rvformal_csr_mhpmcounter26_indices \\\n`rvformal_csr_mhpmcounter27_indices \\\n`rvformal_csr_mhpmcounter28_indices \\\n`rvformal_csr_mhpmcounter29_indices \\\n`rvformal_csr_mhpmcounter30_indices \\\n`rvformal_csr_mhpmcounter31_indices \\\n`rvformal_custom_csr_indices\n\n`ifdef RISCV_FORMAL_CUSTOM_CSR_INPUTS\n`define rvformal_custom_csr_inputs `RISCV_FORMAL_CUSTOM_CSR_INPUTS\n`else\n`define rvformal_custom_csr_inputs\n`endif\n`ifdef RISCV_FORMAL_CUSTOM_CSR_WIRES\n`define rvformal_custom_csr_wires `RISCV_FORMAL_CUSTOM_CSR_WIRES\n`else\n`define rvformal_custom_csr_wires\n`endif\n`ifdef RISCV_FORMAL_CUSTOM_CSR_CONN\n`define rvformal_custom_csr_conn `RISCV_FORMAL_CUSTOM_CSR_CONN\n`else\n`define rvformal_custom_csr_conn\n`endif\n`ifdef RISCV_FORMAL_CUSTOM_CSR_CHANNEL\n`define rvformal_custom_csr_channel(_idx) `RISCV_FORMAL_CUSTOM_CSR_CHANNEL(_idx)\n`else\n`define rvformal_custom_csr_channel(_idx)\n`endif\n`ifdef RISCV_FORMAL_CUSTOM_CSR_SIGNALS\n`define rvformal_custom_csr_signals `RISCV_FORMAL_CUSTOM_CSR_SIGNALS\n`else\n`define rvformal_custom_csr_signals\n`endif\n`ifdef RISCV_FORMAL_CUSTOM_CSR_OUTPUTS\n`define rvformal_custom_csr_outputs `RISCV_FORMAL_CUSTOM_CSR_OUTPUTS\n`else\n`define rvformal_custom_csr_outputs\n`endif\n`ifdef RISCV_FORMAL_CUSTOM_CSR_INDICES\n`define rvformal_custom_csr_indices `RISCV_FORMAL_CUSTOM_CSR_INDICES\n`else\n`define rvformal_custom_csr_indices\n`endif\n`ifdef RISCV_FORMAL_ROLLBACK\n`define rvformal_rollback_wires \\\n  (* keep *) wire [     0 : 0] rvfi_rollback_valid; \\\n  (* keep *) wire [64 - 1 : 0] rvfi_rollback_order;\n`define rvformal_rollback_outputs, \\\n  output [     0 : 0] rvfi_rollback_valid, \\\n  output [64 - 1 : 0] rvfi_rollback_order\n`define rvformal_rollback_channel_outputs, \\\n  output [     0 : 0] rvfi_rollback_valid, \\\n  output [64 - 1 : 0] rvfi_rollback_order\n`define rvformal_rollback_inputs, \\\n  input [     0 : 0] rvfi_rollback_valid, \\\n  input [64 - 1 : 0] rvfi_rollback_order\n`define rvformal_rollback_channel_inputs, \\\n  input [     0 : 0] rvfi_rollback_valid, \\\n  input [64 - 1 : 0] rvfi_rollback_order\n`define rvformal_rollback_conn, \\\n  .rvfi_rollback_valid (rvfi_rollback_valid), \\\n  .rvfi_rollback_order (rvfi_rollback_order)\n`define rvformal_rollback_channel_conn(_idx), \\\n  .rvfi_rollback_valid (rvfi_rollback_valid [ _idx       +:  1]), \\\n  .rvfi_rollback_order (rvfi_rollback_order [(_idx)*(64) +: 64])\n`else\n`define rvformal_rollback_wires\n`define rvformal_rollback_outputs\n`define rvformal_rollback_inputs\n`define rvformal_rollback_conn\n`endif\n`ifdef RISCV_FORMAL_EXTAMO\n`define rvformal_extamo_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET     - 1 : 0] rvfi_mem_extamo;\n`define rvformal_extamo_outputs, \\\n  output [`RISCV_FORMAL_NRET     - 1 : 0] rvfi_mem_extamo\n`define rvformal_extamo_channel_outputs, \\\n  output [    0 : 0] rvfi_mem_extamo\n`define rvformal_extamo_inputs, \\\n  input [`RISCV_FORMAL_NRET     - 1 : 0] rvfi_mem_extamo\n`define rvformal_extamo_channel_inputs, \\\n  input [    0 : 0] rvfi_mem_extamo\n`define rvformal_extamo_conn, \\\n  .rvfi_mem_extamo (rvfi_mem_extamo)\n`define rvformal_extamo_channel_conn(_idx), \\\n  .rvfi_mem_extamo (rvfi_mem_extamo [ _idx      +: 1])\n`define rvformal_extamo_channel(_idx) \\\n  wire [    0 : 0] mem_extamo = rvfi_mem_extamo [ _idx      +: 1];\n`define rvformal_extamo_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, 1, mem_extamo)\n`else\n`define rvformal_extamo_wires\n`define rvformal_extamo_outputs\n`define rvformal_extamo_inputs\n`define rvformal_extamo_conn\n`define rvformal_extamo_channel(_idx)\n`endif\n`ifdef RISCV_FORMAL_MEM_FAULT\n`define rvformal_mem_fault_wires \\\n  (* keep *) wire [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_mem_fault      ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask;\n`define rvformal_mem_fault_outputs, \\\n  output [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_mem_fault      , \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask\n`define rvformal_mem_fault_channel_outputs, \\\n  output [                       0 : 0] rvfi_mem_fault      , \\\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask, \\\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask\n`define rvformal_mem_fault_inputs, \\\n  input [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_mem_fault      , \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask\n`define rvformal_mem_fault_channel_inputs, \\\n  input [                       0 : 0] rvfi_mem_fault      , \\\n  input [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_rmask, \\\n  input [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_fault_wmask\n`define rvformal_mem_fault_conn, \\\n  .rvfi_mem_fault       (rvfi_mem_fault      ), \\\n  .rvfi_mem_fault_rmask (rvfi_mem_fault_rmask), \\\n  .rvfi_mem_fault_wmask (rvfi_mem_fault_wmask)\n`define rvformal_mem_fault_channel_conn(_idx), \\\n  .rvfi_mem_fault       (rvfi_mem_fault       [ _idx                         +:                  1  ]), \\\n  .rvfi_mem_fault_rmask (rvfi_mem_fault_rmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]), \\\n  .rvfi_mem_fault_wmask (rvfi_mem_fault_wmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8])\n`define rvformal_mem_fault_channel(_idx) \\\n  wire [                       0 : 0] mem_fault       = rvfi_mem_fault       [ _idx                         +:                  1  ]; \\\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_rmask = rvfi_mem_fault_rmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]; \\\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_fault_wmask = rvfi_mem_fault_wmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8];\n`define rvformal_mem_fault_signals \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  1  , mem_fault      ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN/8, mem_fault_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN/8, mem_fault_wmask)\n`else\n`define rvformal_mem_fault_wires\n`define rvformal_mem_fault_outputs\n`define rvformal_mem_fault_inputs\n`define rvformal_mem_fault_conn\n`define rvformal_mem_fault_channel(_idx)\n`endif\n`define RVFI_WIRES \\\n  (* keep *) wire [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_valid    ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET *                 64   - 1 : 0] rvfi_order    ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn     ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_trap     ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_halt     ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_intr     ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET *                  2   - 1 : 0] rvfi_mode     ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET *                  2   - 1 : 0] rvfi_ixl      ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET *                  5   - 1 : 0] rvfi_rs1_addr ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET *                  5   - 1 : 0] rvfi_rs2_addr ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET *                  5   - 1 : 0] rvfi_rd_addr  ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rd_wdata ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_wdata ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_addr ; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_wdata; \\\n  `rvformal_extamo_wires \\\n  `rvformal_rollback_wires \\\n  `rvformal_mem_fault_wires \\\n  `rvformal_csr_fflags_wires \\\n  `rvformal_csr_frm_wires \\\n  `rvformal_csr_fcsr_wires \\\n  `rvformal_csr_mvendorid_wires \\\n  `rvformal_csr_marchid_wires \\\n  `rvformal_csr_mimpid_wires \\\n  `rvformal_csr_mhartid_wires \\\n  `rvformal_csr_mconfigptr_wires \\\n  `rvformal_csr_mstatus_wires \\\n  `rvformal_csr_mstatush_wires \\\n  `rvformal_csr_misa_wires \\\n  `rvformal_csr_medeleg_wires \\\n  `rvformal_csr_mideleg_wires \\\n  `rvformal_csr_mie_wires \\\n  `rvformal_csr_mtvec_wires \\\n  `rvformal_csr_mcounteren_wires \\\n  `rvformal_csr_mscratch_wires \\\n  `rvformal_csr_mepc_wires \\\n  `rvformal_csr_mcause_wires \\\n  `rvformal_csr_mtval_wires \\\n  `rvformal_csr_mip_wires \\\n  `rvformal_csr_mtinst_wires \\\n  `rvformal_csr_mtval2_wires \\\n  `rvformal_csr_mcountinhibit_wires \\\n  `rvformal_csr_menvcfg_wires \\\n  `rvformal_csr_menvcfgh_wires \\\n  `rvformal_csr_pmpcfg0_wires \\\n  `rvformal_csr_pmpcfg1_wires \\\n  `rvformal_csr_pmpcfg2_wires \\\n  `rvformal_csr_pmpcfg3_wires \\\n  `rvformal_csr_pmpcfg4_wires \\\n  `rvformal_csr_pmpcfg5_wires \\\n  `rvformal_csr_pmpcfg6_wires \\\n  `rvformal_csr_pmpcfg7_wires \\\n  `rvformal_csr_pmpcfg8_wires \\\n  `rvformal_csr_pmpcfg9_wires \\\n  `rvformal_csr_pmpcfg10_wires \\\n  `rvformal_csr_pmpcfg11_wires \\\n  `rvformal_csr_pmpcfg12_wires \\\n  `rvformal_csr_pmpcfg13_wires \\\n  `rvformal_csr_pmpcfg14_wires \\\n  `rvformal_csr_pmpcfg15_wires \\\n  `rvformal_csr_pmpaddr0_wires \\\n  `rvformal_csr_pmpaddr1_wires \\\n  `rvformal_csr_pmpaddr2_wires \\\n  `rvformal_csr_pmpaddr3_wires \\\n  `rvformal_csr_pmpaddr4_wires \\\n  `rvformal_csr_pmpaddr5_wires \\\n  `rvformal_csr_pmpaddr6_wires \\\n  `rvformal_csr_pmpaddr7_wires \\\n  `rvformal_csr_pmpaddr8_wires \\\n  `rvformal_csr_pmpaddr9_wires \\\n  `rvformal_csr_pmpaddr10_wires \\\n  `rvformal_csr_pmpaddr11_wires \\\n  `rvformal_csr_pmpaddr12_wires \\\n  `rvformal_csr_pmpaddr13_wires \\\n  `rvformal_csr_pmpaddr14_wires \\\n  `rvformal_csr_pmpaddr15_wires \\\n  `rvformal_csr_pmpaddr16_wires \\\n  `rvformal_csr_pmpaddr17_wires \\\n  `rvformal_csr_pmpaddr18_wires \\\n  `rvformal_csr_pmpaddr19_wires \\\n  `rvformal_csr_pmpaddr20_wires \\\n  `rvformal_csr_pmpaddr21_wires \\\n  `rvformal_csr_pmpaddr22_wires \\\n  `rvformal_csr_pmpaddr23_wires \\\n  `rvformal_csr_pmpaddr24_wires \\\n  `rvformal_csr_pmpaddr25_wires \\\n  `rvformal_csr_pmpaddr26_wires \\\n  `rvformal_csr_pmpaddr27_wires \\\n  `rvformal_csr_pmpaddr28_wires \\\n  `rvformal_csr_pmpaddr29_wires \\\n  `rvformal_csr_pmpaddr30_wires \\\n  `rvformal_csr_pmpaddr31_wires \\\n  `rvformal_csr_pmpaddr32_wires \\\n  `rvformal_csr_pmpaddr33_wires \\\n  `rvformal_csr_pmpaddr34_wires \\\n  `rvformal_csr_pmpaddr35_wires \\\n  `rvformal_csr_pmpaddr36_wires \\\n  `rvformal_csr_pmpaddr37_wires \\\n  `rvformal_csr_pmpaddr38_wires \\\n  `rvformal_csr_pmpaddr39_wires \\\n  `rvformal_csr_pmpaddr40_wires \\\n  `rvformal_csr_pmpaddr41_wires \\\n  `rvformal_csr_pmpaddr42_wires \\\n  `rvformal_csr_pmpaddr43_wires \\\n  `rvformal_csr_pmpaddr44_wires \\\n  `rvformal_csr_pmpaddr45_wires \\\n  `rvformal_csr_pmpaddr46_wires \\\n  `rvformal_csr_pmpaddr47_wires \\\n  `rvformal_csr_pmpaddr48_wires \\\n  `rvformal_csr_pmpaddr49_wires \\\n  `rvformal_csr_pmpaddr50_wires \\\n  `rvformal_csr_pmpaddr51_wires \\\n  `rvformal_csr_pmpaddr52_wires \\\n  `rvformal_csr_pmpaddr53_wires \\\n  `rvformal_csr_pmpaddr54_wires \\\n  `rvformal_csr_pmpaddr55_wires \\\n  `rvformal_csr_pmpaddr56_wires \\\n  `rvformal_csr_pmpaddr57_wires \\\n  `rvformal_csr_pmpaddr58_wires \\\n  `rvformal_csr_pmpaddr59_wires \\\n  `rvformal_csr_pmpaddr60_wires \\\n  `rvformal_csr_pmpaddr61_wires \\\n  `rvformal_csr_pmpaddr62_wires \\\n  `rvformal_csr_pmpaddr63_wires \\\n  `rvformal_csr_mhpmevent3_wires \\\n  `rvformal_csr_mhpmevent4_wires \\\n  `rvformal_csr_mhpmevent5_wires \\\n  `rvformal_csr_mhpmevent6_wires \\\n  `rvformal_csr_mhpmevent7_wires \\\n  `rvformal_csr_mhpmevent8_wires \\\n  `rvformal_csr_mhpmevent9_wires \\\n  `rvformal_csr_mhpmevent10_wires \\\n  `rvformal_csr_mhpmevent11_wires \\\n  `rvformal_csr_mhpmevent12_wires \\\n  `rvformal_csr_mhpmevent13_wires \\\n  `rvformal_csr_mhpmevent14_wires \\\n  `rvformal_csr_mhpmevent15_wires \\\n  `rvformal_csr_mhpmevent16_wires \\\n  `rvformal_csr_mhpmevent17_wires \\\n  `rvformal_csr_mhpmevent18_wires \\\n  `rvformal_csr_mhpmevent19_wires \\\n  `rvformal_csr_mhpmevent20_wires \\\n  `rvformal_csr_mhpmevent21_wires \\\n  `rvformal_csr_mhpmevent22_wires \\\n  `rvformal_csr_mhpmevent23_wires \\\n  `rvformal_csr_mhpmevent24_wires \\\n  `rvformal_csr_mhpmevent25_wires \\\n  `rvformal_csr_mhpmevent26_wires \\\n  `rvformal_csr_mhpmevent27_wires \\\n  `rvformal_csr_mhpmevent28_wires \\\n  `rvformal_csr_mhpmevent29_wires \\\n  `rvformal_csr_mhpmevent30_wires \\\n  `rvformal_csr_mhpmevent31_wires \\\n  `rvformal_csr_mcycle_wires \\\n  `rvformal_csr_time_wires \\\n  `rvformal_csr_minstret_wires \\\n  `rvformal_csr_mhpmcounter3_wires \\\n  `rvformal_csr_mhpmcounter4_wires \\\n  `rvformal_csr_mhpmcounter5_wires \\\n  `rvformal_csr_mhpmcounter6_wires \\\n  `rvformal_csr_mhpmcounter7_wires \\\n  `rvformal_csr_mhpmcounter8_wires \\\n  `rvformal_csr_mhpmcounter9_wires \\\n  `rvformal_csr_mhpmcounter10_wires \\\n  `rvformal_csr_mhpmcounter11_wires \\\n  `rvformal_csr_mhpmcounter12_wires \\\n  `rvformal_csr_mhpmcounter13_wires \\\n  `rvformal_csr_mhpmcounter14_wires \\\n  `rvformal_csr_mhpmcounter15_wires \\\n  `rvformal_csr_mhpmcounter16_wires \\\n  `rvformal_csr_mhpmcounter17_wires \\\n  `rvformal_csr_mhpmcounter18_wires \\\n  `rvformal_csr_mhpmcounter19_wires \\\n  `rvformal_csr_mhpmcounter20_wires \\\n  `rvformal_csr_mhpmcounter21_wires \\\n  `rvformal_csr_mhpmcounter22_wires \\\n  `rvformal_csr_mhpmcounter23_wires \\\n  `rvformal_csr_mhpmcounter24_wires \\\n  `rvformal_csr_mhpmcounter25_wires \\\n  `rvformal_csr_mhpmcounter26_wires \\\n  `rvformal_csr_mhpmcounter27_wires \\\n  `rvformal_csr_mhpmcounter28_wires \\\n  `rvformal_csr_mhpmcounter29_wires \\\n  `rvformal_csr_mhpmcounter30_wires \\\n  `rvformal_csr_mhpmcounter31_wires \\\n  `rvformal_custom_csr_wires\n`define RVFI_OUTPUTS \\\n  output [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_valid    , \\\n  output [`RISCV_FORMAL_NRET *                 64   - 1 : 0] rvfi_order    , \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn     , \\\n  output [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_trap     , \\\n  output [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_halt     , \\\n  output [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_intr     , \\\n  output [`RISCV_FORMAL_NRET *                  2   - 1 : 0] rvfi_mode     , \\\n  output [`RISCV_FORMAL_NRET *                  2   - 1 : 0] rvfi_ixl      , \\\n  output [`RISCV_FORMAL_NRET *                  5   - 1 : 0] rvfi_rs1_addr , \\\n  output [`RISCV_FORMAL_NRET *                  5   - 1 : 0] rvfi_rs2_addr , \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata, \\\n  output [`RISCV_FORMAL_NRET *                  5   - 1 : 0] rvfi_rd_addr  , \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rd_wdata , \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata , \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_wdata , \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_addr , \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata, \\\n  output [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_wdata \\\n  `rvformal_extamo_outputs \\\n  `rvformal_rollback_outputs \\\n  `rvformal_mem_fault_outputs \\\n  `rvformal_csr_fflags_outputs \\\n  `rvformal_csr_frm_outputs \\\n  `rvformal_csr_fcsr_outputs \\\n  `rvformal_csr_mvendorid_outputs \\\n  `rvformal_csr_marchid_outputs \\\n  `rvformal_csr_mimpid_outputs \\\n  `rvformal_csr_mhartid_outputs \\\n  `rvformal_csr_mconfigptr_outputs \\\n  `rvformal_csr_mstatus_outputs \\\n  `rvformal_csr_mstatush_outputs \\\n  `rvformal_csr_misa_outputs \\\n  `rvformal_csr_medeleg_outputs \\\n  `rvformal_csr_mideleg_outputs \\\n  `rvformal_csr_mie_outputs \\\n  `rvformal_csr_mtvec_outputs \\\n  `rvformal_csr_mcounteren_outputs \\\n  `rvformal_csr_mscratch_outputs \\\n  `rvformal_csr_mepc_outputs \\\n  `rvformal_csr_mcause_outputs \\\n  `rvformal_csr_mtval_outputs \\\n  `rvformal_csr_mip_outputs \\\n  `rvformal_csr_mtinst_outputs \\\n  `rvformal_csr_mtval2_outputs \\\n  `rvformal_csr_mcountinhibit_outputs \\\n  `rvformal_csr_menvcfg_outputs \\\n  `rvformal_csr_menvcfgh_outputs \\\n  `rvformal_csr_pmpcfg0_outputs \\\n  `rvformal_csr_pmpcfg1_outputs \\\n  `rvformal_csr_pmpcfg2_outputs \\\n  `rvformal_csr_pmpcfg3_outputs \\\n  `rvformal_csr_pmpcfg4_outputs \\\n  `rvformal_csr_pmpcfg5_outputs \\\n  `rvformal_csr_pmpcfg6_outputs \\\n  `rvformal_csr_pmpcfg7_outputs \\\n  `rvformal_csr_pmpcfg8_outputs \\\n  `rvformal_csr_pmpcfg9_outputs \\\n  `rvformal_csr_pmpcfg10_outputs \\\n  `rvformal_csr_pmpcfg11_outputs \\\n  `rvformal_csr_pmpcfg12_outputs \\\n  `rvformal_csr_pmpcfg13_outputs \\\n  `rvformal_csr_pmpcfg14_outputs \\\n  `rvformal_csr_pmpcfg15_outputs \\\n  `rvformal_csr_pmpaddr0_outputs \\\n  `rvformal_csr_pmpaddr1_outputs \\\n  `rvformal_csr_pmpaddr2_outputs \\\n  `rvformal_csr_pmpaddr3_outputs \\\n  `rvformal_csr_pmpaddr4_outputs \\\n  `rvformal_csr_pmpaddr5_outputs \\\n  `rvformal_csr_pmpaddr6_outputs \\\n  `rvformal_csr_pmpaddr7_outputs \\\n  `rvformal_csr_pmpaddr8_outputs \\\n  `rvformal_csr_pmpaddr9_outputs \\\n  `rvformal_csr_pmpaddr10_outputs \\\n  `rvformal_csr_pmpaddr11_outputs \\\n  `rvformal_csr_pmpaddr12_outputs \\\n  `rvformal_csr_pmpaddr13_outputs \\\n  `rvformal_csr_pmpaddr14_outputs \\\n  `rvformal_csr_pmpaddr15_outputs \\\n  `rvformal_csr_pmpaddr16_outputs \\\n  `rvformal_csr_pmpaddr17_outputs \\\n  `rvformal_csr_pmpaddr18_outputs \\\n  `rvformal_csr_pmpaddr19_outputs \\\n  `rvformal_csr_pmpaddr20_outputs \\\n  `rvformal_csr_pmpaddr21_outputs \\\n  `rvformal_csr_pmpaddr22_outputs \\\n  `rvformal_csr_pmpaddr23_outputs \\\n  `rvformal_csr_pmpaddr24_outputs \\\n  `rvformal_csr_pmpaddr25_outputs \\\n  `rvformal_csr_pmpaddr26_outputs \\\n  `rvformal_csr_pmpaddr27_outputs \\\n  `rvformal_csr_pmpaddr28_outputs \\\n  `rvformal_csr_pmpaddr29_outputs \\\n  `rvformal_csr_pmpaddr30_outputs \\\n  `rvformal_csr_pmpaddr31_outputs \\\n  `rvformal_csr_pmpaddr32_outputs \\\n  `rvformal_csr_pmpaddr33_outputs \\\n  `rvformal_csr_pmpaddr34_outputs \\\n  `rvformal_csr_pmpaddr35_outputs \\\n  `rvformal_csr_pmpaddr36_outputs \\\n  `rvformal_csr_pmpaddr37_outputs \\\n  `rvformal_csr_pmpaddr38_outputs \\\n  `rvformal_csr_pmpaddr39_outputs \\\n  `rvformal_csr_pmpaddr40_outputs \\\n  `rvformal_csr_pmpaddr41_outputs \\\n  `rvformal_csr_pmpaddr42_outputs \\\n  `rvformal_csr_pmpaddr43_outputs \\\n  `rvformal_csr_pmpaddr44_outputs \\\n  `rvformal_csr_pmpaddr45_outputs \\\n  `rvformal_csr_pmpaddr46_outputs \\\n  `rvformal_csr_pmpaddr47_outputs \\\n  `rvformal_csr_pmpaddr48_outputs \\\n  `rvformal_csr_pmpaddr49_outputs \\\n  `rvformal_csr_pmpaddr50_outputs \\\n  `rvformal_csr_pmpaddr51_outputs \\\n  `rvformal_csr_pmpaddr52_outputs \\\n  `rvformal_csr_pmpaddr53_outputs \\\n  `rvformal_csr_pmpaddr54_outputs \\\n  `rvformal_csr_pmpaddr55_outputs \\\n  `rvformal_csr_pmpaddr56_outputs \\\n  `rvformal_csr_pmpaddr57_outputs \\\n  `rvformal_csr_pmpaddr58_outputs \\\n  `rvformal_csr_pmpaddr59_outputs \\\n  `rvformal_csr_pmpaddr60_outputs \\\n  `rvformal_csr_pmpaddr61_outputs \\\n  `rvformal_csr_pmpaddr62_outputs \\\n  `rvformal_csr_pmpaddr63_outputs \\\n  `rvformal_csr_mhpmevent3_outputs \\\n  `rvformal_csr_mhpmevent4_outputs \\\n  `rvformal_csr_mhpmevent5_outputs \\\n  `rvformal_csr_mhpmevent6_outputs \\\n  `rvformal_csr_mhpmevent7_outputs \\\n  `rvformal_csr_mhpmevent8_outputs \\\n  `rvformal_csr_mhpmevent9_outputs \\\n  `rvformal_csr_mhpmevent10_outputs \\\n  `rvformal_csr_mhpmevent11_outputs \\\n  `rvformal_csr_mhpmevent12_outputs \\\n  `rvformal_csr_mhpmevent13_outputs \\\n  `rvformal_csr_mhpmevent14_outputs \\\n  `rvformal_csr_mhpmevent15_outputs \\\n  `rvformal_csr_mhpmevent16_outputs \\\n  `rvformal_csr_mhpmevent17_outputs \\\n  `rvformal_csr_mhpmevent18_outputs \\\n  `rvformal_csr_mhpmevent19_outputs \\\n  `rvformal_csr_mhpmevent20_outputs \\\n  `rvformal_csr_mhpmevent21_outputs \\\n  `rvformal_csr_mhpmevent22_outputs \\\n  `rvformal_csr_mhpmevent23_outputs \\\n  `rvformal_csr_mhpmevent24_outputs \\\n  `rvformal_csr_mhpmevent25_outputs \\\n  `rvformal_csr_mhpmevent26_outputs \\\n  `rvformal_csr_mhpmevent27_outputs \\\n  `rvformal_csr_mhpmevent28_outputs \\\n  `rvformal_csr_mhpmevent29_outputs \\\n  `rvformal_csr_mhpmevent30_outputs \\\n  `rvformal_csr_mhpmevent31_outputs \\\n  `rvformal_csr_mcycle_outputs \\\n  `rvformal_csr_time_outputs \\\n  `rvformal_csr_minstret_outputs \\\n  `rvformal_csr_mhpmcounter3_outputs \\\n  `rvformal_csr_mhpmcounter4_outputs \\\n  `rvformal_csr_mhpmcounter5_outputs \\\n  `rvformal_csr_mhpmcounter6_outputs \\\n  `rvformal_csr_mhpmcounter7_outputs \\\n  `rvformal_csr_mhpmcounter8_outputs \\\n  `rvformal_csr_mhpmcounter9_outputs \\\n  `rvformal_csr_mhpmcounter10_outputs \\\n  `rvformal_csr_mhpmcounter11_outputs \\\n  `rvformal_csr_mhpmcounter12_outputs \\\n  `rvformal_csr_mhpmcounter13_outputs \\\n  `rvformal_csr_mhpmcounter14_outputs \\\n  `rvformal_csr_mhpmcounter15_outputs \\\n  `rvformal_csr_mhpmcounter16_outputs \\\n  `rvformal_csr_mhpmcounter17_outputs \\\n  `rvformal_csr_mhpmcounter18_outputs \\\n  `rvformal_csr_mhpmcounter19_outputs \\\n  `rvformal_csr_mhpmcounter20_outputs \\\n  `rvformal_csr_mhpmcounter21_outputs \\\n  `rvformal_csr_mhpmcounter22_outputs \\\n  `rvformal_csr_mhpmcounter23_outputs \\\n  `rvformal_csr_mhpmcounter24_outputs \\\n  `rvformal_csr_mhpmcounter25_outputs \\\n  `rvformal_csr_mhpmcounter26_outputs \\\n  `rvformal_csr_mhpmcounter27_outputs \\\n  `rvformal_csr_mhpmcounter28_outputs \\\n  `rvformal_csr_mhpmcounter29_outputs \\\n  `rvformal_csr_mhpmcounter30_outputs \\\n  `rvformal_csr_mhpmcounter31_outputs \\\n  `rvformal_custom_csr_outputs\n`define RVFI_CHANNEL_OUTPUTS \\\n  output [                       0 : 0] rvfi_valid    , \\\n  output [                64   - 1 : 0] rvfi_order    , \\\n  output [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn     , \\\n  output [                       0 : 0] rvfi_trap     , \\\n  output [                       0 : 0] rvfi_halt     , \\\n  output [                       0 : 0] rvfi_intr     , \\\n  output [                 2   - 1 : 0] rvfi_mode     , \\\n  output [                 2   - 1 : 0] rvfi_ixl      , \\\n  output [                 5   - 1 : 0] rvfi_rs1_addr , \\\n  output [                 5   - 1 : 0] rvfi_rs2_addr , \\\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata, \\\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata, \\\n  output [                 5   - 1 : 0] rvfi_rd_addr  , \\\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rd_wdata , \\\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata , \\\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_wdata , \\\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_addr , \\\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask, \\\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask, \\\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata, \\\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_wdata \\\n  `rvformal_extamo_channel_outputs \\\n  `rvformal_rollback_channel_outputs \\\n  `rvformal_mem_fault_channel_outputs \\\n  `rvformal_csr_fflags_channel_outputs \\\n  `rvformal_csr_frm_channel_outputs \\\n  `rvformal_csr_fcsr_channel_outputs \\\n  `rvformal_csr_mvendorid_channel_outputs \\\n  `rvformal_csr_marchid_channel_outputs \\\n  `rvformal_csr_mimpid_channel_outputs \\\n  `rvformal_csr_mhartid_channel_outputs \\\n  `rvformal_csr_mconfigptr_channel_outputs \\\n  `rvformal_csr_mstatus_channel_outputs \\\n  `rvformal_csr_mstatush_channel_outputs \\\n  `rvformal_csr_misa_channel_outputs \\\n  `rvformal_csr_medeleg_channel_outputs \\\n  `rvformal_csr_mideleg_channel_outputs \\\n  `rvformal_csr_mie_channel_outputs \\\n  `rvformal_csr_mtvec_channel_outputs \\\n  `rvformal_csr_mcounteren_channel_outputs \\\n  `rvformal_csr_mscratch_channel_outputs \\\n  `rvformal_csr_mepc_channel_outputs \\\n  `rvformal_csr_mcause_channel_outputs \\\n  `rvformal_csr_mtval_channel_outputs \\\n  `rvformal_csr_mip_channel_outputs \\\n  `rvformal_csr_mtinst_channel_outputs \\\n  `rvformal_csr_mtval2_channel_outputs \\\n  `rvformal_csr_mcountinhibit_channel_outputs \\\n  `rvformal_csr_menvcfg_channel_outputs \\\n  `rvformal_csr_menvcfgh_channel_outputs \\\n  `rvformal_csr_pmpcfg0_channel_outputs \\\n  `rvformal_csr_pmpcfg1_channel_outputs \\\n  `rvformal_csr_pmpcfg2_channel_outputs \\\n  `rvformal_csr_pmpcfg3_channel_outputs \\\n  `rvformal_csr_pmpcfg4_channel_outputs \\\n  `rvformal_csr_pmpcfg5_channel_outputs \\\n  `rvformal_csr_pmpcfg6_channel_outputs \\\n  `rvformal_csr_pmpcfg7_channel_outputs \\\n  `rvformal_csr_pmpcfg8_channel_outputs \\\n  `rvformal_csr_pmpcfg9_channel_outputs \\\n  `rvformal_csr_pmpcfg10_channel_outputs \\\n  `rvformal_csr_pmpcfg11_channel_outputs \\\n  `rvformal_csr_pmpcfg12_channel_outputs \\\n  `rvformal_csr_pmpcfg13_channel_outputs \\\n  `rvformal_csr_pmpcfg14_channel_outputs \\\n  `rvformal_csr_pmpcfg15_channel_outputs \\\n  `rvformal_csr_pmpaddr0_channel_outputs \\\n  `rvformal_csr_pmpaddr1_channel_outputs \\\n  `rvformal_csr_pmpaddr2_channel_outputs \\\n  `rvformal_csr_pmpaddr3_channel_outputs \\\n  `rvformal_csr_pmpaddr4_channel_outputs \\\n  `rvformal_csr_pmpaddr5_channel_outputs \\\n  `rvformal_csr_pmpaddr6_channel_outputs \\\n  `rvformal_csr_pmpaddr7_channel_outputs \\\n  `rvformal_csr_pmpaddr8_channel_outputs \\\n  `rvformal_csr_pmpaddr9_channel_outputs \\\n  `rvformal_csr_pmpaddr10_channel_outputs \\\n  `rvformal_csr_pmpaddr11_channel_outputs \\\n  `rvformal_csr_pmpaddr12_channel_outputs \\\n  `rvformal_csr_pmpaddr13_channel_outputs \\\n  `rvformal_csr_pmpaddr14_channel_outputs \\\n  `rvformal_csr_pmpaddr15_channel_outputs \\\n  `rvformal_csr_pmpaddr16_channel_outputs \\\n  `rvformal_csr_pmpaddr17_channel_outputs \\\n  `rvformal_csr_pmpaddr18_channel_outputs \\\n  `rvformal_csr_pmpaddr19_channel_outputs \\\n  `rvformal_csr_pmpaddr20_channel_outputs \\\n  `rvformal_csr_pmpaddr21_channel_outputs \\\n  `rvformal_csr_pmpaddr22_channel_outputs \\\n  `rvformal_csr_pmpaddr23_channel_outputs \\\n  `rvformal_csr_pmpaddr24_channel_outputs \\\n  `rvformal_csr_pmpaddr25_channel_outputs \\\n  `rvformal_csr_pmpaddr26_channel_outputs \\\n  `rvformal_csr_pmpaddr27_channel_outputs \\\n  `rvformal_csr_pmpaddr28_channel_outputs \\\n  `rvformal_csr_pmpaddr29_channel_outputs \\\n  `rvformal_csr_pmpaddr30_channel_outputs \\\n  `rvformal_csr_pmpaddr31_channel_outputs \\\n  `rvformal_csr_pmpaddr32_channel_outputs \\\n  `rvformal_csr_pmpaddr33_channel_outputs \\\n  `rvformal_csr_pmpaddr34_channel_outputs \\\n  `rvformal_csr_pmpaddr35_channel_outputs \\\n  `rvformal_csr_pmpaddr36_channel_outputs \\\n  `rvformal_csr_pmpaddr37_channel_outputs \\\n  `rvformal_csr_pmpaddr38_channel_outputs \\\n  `rvformal_csr_pmpaddr39_channel_outputs \\\n  `rvformal_csr_pmpaddr40_channel_outputs \\\n  `rvformal_csr_pmpaddr41_channel_outputs \\\n  `rvformal_csr_pmpaddr42_channel_outputs \\\n  `rvformal_csr_pmpaddr43_channel_outputs \\\n  `rvformal_csr_pmpaddr44_channel_outputs \\\n  `rvformal_csr_pmpaddr45_channel_outputs \\\n  `rvformal_csr_pmpaddr46_channel_outputs \\\n  `rvformal_csr_pmpaddr47_channel_outputs \\\n  `rvformal_csr_pmpaddr48_channel_outputs \\\n  `rvformal_csr_pmpaddr49_channel_outputs \\\n  `rvformal_csr_pmpaddr50_channel_outputs \\\n  `rvformal_csr_pmpaddr51_channel_outputs \\\n  `rvformal_csr_pmpaddr52_channel_outputs \\\n  `rvformal_csr_pmpaddr53_channel_outputs \\\n  `rvformal_csr_pmpaddr54_channel_outputs \\\n  `rvformal_csr_pmpaddr55_channel_outputs \\\n  `rvformal_csr_pmpaddr56_channel_outputs \\\n  `rvformal_csr_pmpaddr57_channel_outputs \\\n  `rvformal_csr_pmpaddr58_channel_outputs \\\n  `rvformal_csr_pmpaddr59_channel_outputs \\\n  `rvformal_csr_pmpaddr60_channel_outputs \\\n  `rvformal_csr_pmpaddr61_channel_outputs \\\n  `rvformal_csr_pmpaddr62_channel_outputs \\\n  `rvformal_csr_pmpaddr63_channel_outputs \\\n  `rvformal_csr_mhpmevent3_channel_outputs \\\n  `rvformal_csr_mhpmevent4_channel_outputs \\\n  `rvformal_csr_mhpmevent5_channel_outputs \\\n  `rvformal_csr_mhpmevent6_channel_outputs \\\n  `rvformal_csr_mhpmevent7_channel_outputs \\\n  `rvformal_csr_mhpmevent8_channel_outputs \\\n  `rvformal_csr_mhpmevent9_channel_outputs \\\n  `rvformal_csr_mhpmevent10_channel_outputs \\\n  `rvformal_csr_mhpmevent11_channel_outputs \\\n  `rvformal_csr_mhpmevent12_channel_outputs \\\n  `rvformal_csr_mhpmevent13_channel_outputs \\\n  `rvformal_csr_mhpmevent14_channel_outputs \\\n  `rvformal_csr_mhpmevent15_channel_outputs \\\n  `rvformal_csr_mhpmevent16_channel_outputs \\\n  `rvformal_csr_mhpmevent17_channel_outputs \\\n  `rvformal_csr_mhpmevent18_channel_outputs \\\n  `rvformal_csr_mhpmevent19_channel_outputs \\\n  `rvformal_csr_mhpmevent20_channel_outputs \\\n  `rvformal_csr_mhpmevent21_channel_outputs \\\n  `rvformal_csr_mhpmevent22_channel_outputs \\\n  `rvformal_csr_mhpmevent23_channel_outputs \\\n  `rvformal_csr_mhpmevent24_channel_outputs \\\n  `rvformal_csr_mhpmevent25_channel_outputs \\\n  `rvformal_csr_mhpmevent26_channel_outputs \\\n  `rvformal_csr_mhpmevent27_channel_outputs \\\n  `rvformal_csr_mhpmevent28_channel_outputs \\\n  `rvformal_csr_mhpmevent29_channel_outputs \\\n  `rvformal_csr_mhpmevent30_channel_outputs \\\n  `rvformal_csr_mhpmevent31_channel_outputs \\\n  `rvformal_csr_mcycle_channel_outputs \\\n  `rvformal_csr_time_channel_outputs \\\n  `rvformal_csr_minstret_channel_outputs \\\n  `rvformal_csr_mhpmcounter3_channel_outputs \\\n  `rvformal_csr_mhpmcounter4_channel_outputs \\\n  `rvformal_csr_mhpmcounter5_channel_outputs \\\n  `rvformal_csr_mhpmcounter6_channel_outputs \\\n  `rvformal_csr_mhpmcounter7_channel_outputs \\\n  `rvformal_csr_mhpmcounter8_channel_outputs \\\n  `rvformal_csr_mhpmcounter9_channel_outputs \\\n  `rvformal_csr_mhpmcounter10_channel_outputs \\\n  `rvformal_csr_mhpmcounter11_channel_outputs \\\n  `rvformal_csr_mhpmcounter12_channel_outputs \\\n  `rvformal_csr_mhpmcounter13_channel_outputs \\\n  `rvformal_csr_mhpmcounter14_channel_outputs \\\n  `rvformal_csr_mhpmcounter15_channel_outputs \\\n  `rvformal_csr_mhpmcounter16_channel_outputs \\\n  `rvformal_csr_mhpmcounter17_channel_outputs \\\n  `rvformal_csr_mhpmcounter18_channel_outputs \\\n  `rvformal_csr_mhpmcounter19_channel_outputs \\\n  `rvformal_csr_mhpmcounter20_channel_outputs \\\n  `rvformal_csr_mhpmcounter21_channel_outputs \\\n  `rvformal_csr_mhpmcounter22_channel_outputs \\\n  `rvformal_csr_mhpmcounter23_channel_outputs \\\n  `rvformal_csr_mhpmcounter24_channel_outputs \\\n  `rvformal_csr_mhpmcounter25_channel_outputs \\\n  `rvformal_csr_mhpmcounter26_channel_outputs \\\n  `rvformal_csr_mhpmcounter27_channel_outputs \\\n  `rvformal_csr_mhpmcounter28_channel_outputs \\\n  `rvformal_csr_mhpmcounter29_channel_outputs \\\n  `rvformal_csr_mhpmcounter30_channel_outputs \\\n  `rvformal_csr_mhpmcounter31_channel_outputs \\\n  `rvformal_custom_csr_channel_outputs\n`define RVFI_INPUTS \\\n  input [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_valid    , \\\n  input [`RISCV_FORMAL_NRET *                 64   - 1 : 0] rvfi_order    , \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn     , \\\n  input [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_trap     , \\\n  input [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_halt     , \\\n  input [`RISCV_FORMAL_NRET                        - 1 : 0] rvfi_intr     , \\\n  input [`RISCV_FORMAL_NRET *                  2   - 1 : 0] rvfi_mode     , \\\n  input [`RISCV_FORMAL_NRET *                  2   - 1 : 0] rvfi_ixl      , \\\n  input [`RISCV_FORMAL_NRET *                  5   - 1 : 0] rvfi_rs1_addr , \\\n  input [`RISCV_FORMAL_NRET *                  5   - 1 : 0] rvfi_rs2_addr , \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata, \\\n  input [`RISCV_FORMAL_NRET *                  5   - 1 : 0] rvfi_rd_addr  , \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rd_wdata , \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata , \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_wdata , \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_addr , \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata, \\\n  input [`RISCV_FORMAL_NRET * `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_wdata \\\n  `rvformal_extamo_inputs \\\n  `rvformal_rollback_inputs \\\n  `rvformal_mem_fault_inputs \\\n  `rvformal_csr_fflags_inputs \\\n  `rvformal_csr_frm_inputs \\\n  `rvformal_csr_fcsr_inputs \\\n  `rvformal_csr_mvendorid_inputs \\\n  `rvformal_csr_marchid_inputs \\\n  `rvformal_csr_mimpid_inputs \\\n  `rvformal_csr_mhartid_inputs \\\n  `rvformal_csr_mconfigptr_inputs \\\n  `rvformal_csr_mstatus_inputs \\\n  `rvformal_csr_mstatush_inputs \\\n  `rvformal_csr_misa_inputs \\\n  `rvformal_csr_medeleg_inputs \\\n  `rvformal_csr_mideleg_inputs \\\n  `rvformal_csr_mie_inputs \\\n  `rvformal_csr_mtvec_inputs \\\n  `rvformal_csr_mcounteren_inputs \\\n  `rvformal_csr_mscratch_inputs \\\n  `rvformal_csr_mepc_inputs \\\n  `rvformal_csr_mcause_inputs \\\n  `rvformal_csr_mtval_inputs \\\n  `rvformal_csr_mip_inputs \\\n  `rvformal_csr_mtinst_inputs \\\n  `rvformal_csr_mtval2_inputs \\\n  `rvformal_csr_mcountinhibit_inputs \\\n  `rvformal_csr_menvcfg_inputs \\\n  `rvformal_csr_menvcfgh_inputs \\\n  `rvformal_csr_pmpcfg0_inputs \\\n  `rvformal_csr_pmpcfg1_inputs \\\n  `rvformal_csr_pmpcfg2_inputs \\\n  `rvformal_csr_pmpcfg3_inputs \\\n  `rvformal_csr_pmpcfg4_inputs \\\n  `rvformal_csr_pmpcfg5_inputs \\\n  `rvformal_csr_pmpcfg6_inputs \\\n  `rvformal_csr_pmpcfg7_inputs \\\n  `rvformal_csr_pmpcfg8_inputs \\\n  `rvformal_csr_pmpcfg9_inputs \\\n  `rvformal_csr_pmpcfg10_inputs \\\n  `rvformal_csr_pmpcfg11_inputs \\\n  `rvformal_csr_pmpcfg12_inputs \\\n  `rvformal_csr_pmpcfg13_inputs \\\n  `rvformal_csr_pmpcfg14_inputs \\\n  `rvformal_csr_pmpcfg15_inputs \\\n  `rvformal_csr_pmpaddr0_inputs \\\n  `rvformal_csr_pmpaddr1_inputs \\\n  `rvformal_csr_pmpaddr2_inputs \\\n  `rvformal_csr_pmpaddr3_inputs \\\n  `rvformal_csr_pmpaddr4_inputs \\\n  `rvformal_csr_pmpaddr5_inputs \\\n  `rvformal_csr_pmpaddr6_inputs \\\n  `rvformal_csr_pmpaddr7_inputs \\\n  `rvformal_csr_pmpaddr8_inputs \\\n  `rvformal_csr_pmpaddr9_inputs \\\n  `rvformal_csr_pmpaddr10_inputs \\\n  `rvformal_csr_pmpaddr11_inputs \\\n  `rvformal_csr_pmpaddr12_inputs \\\n  `rvformal_csr_pmpaddr13_inputs \\\n  `rvformal_csr_pmpaddr14_inputs \\\n  `rvformal_csr_pmpaddr15_inputs \\\n  `rvformal_csr_pmpaddr16_inputs \\\n  `rvformal_csr_pmpaddr17_inputs \\\n  `rvformal_csr_pmpaddr18_inputs \\\n  `rvformal_csr_pmpaddr19_inputs \\\n  `rvformal_csr_pmpaddr20_inputs \\\n  `rvformal_csr_pmpaddr21_inputs \\\n  `rvformal_csr_pmpaddr22_inputs \\\n  `rvformal_csr_pmpaddr23_inputs \\\n  `rvformal_csr_pmpaddr24_inputs \\\n  `rvformal_csr_pmpaddr25_inputs \\\n  `rvformal_csr_pmpaddr26_inputs \\\n  `rvformal_csr_pmpaddr27_inputs \\\n  `rvformal_csr_pmpaddr28_inputs \\\n  `rvformal_csr_pmpaddr29_inputs \\\n  `rvformal_csr_pmpaddr30_inputs \\\n  `rvformal_csr_pmpaddr31_inputs \\\n  `rvformal_csr_pmpaddr32_inputs \\\n  `rvformal_csr_pmpaddr33_inputs \\\n  `rvformal_csr_pmpaddr34_inputs \\\n  `rvformal_csr_pmpaddr35_inputs \\\n  `rvformal_csr_pmpaddr36_inputs \\\n  `rvformal_csr_pmpaddr37_inputs \\\n  `rvformal_csr_pmpaddr38_inputs \\\n  `rvformal_csr_pmpaddr39_inputs \\\n  `rvformal_csr_pmpaddr40_inputs \\\n  `rvformal_csr_pmpaddr41_inputs \\\n  `rvformal_csr_pmpaddr42_inputs \\\n  `rvformal_csr_pmpaddr43_inputs \\\n  `rvformal_csr_pmpaddr44_inputs \\\n  `rvformal_csr_pmpaddr45_inputs \\\n  `rvformal_csr_pmpaddr46_inputs \\\n  `rvformal_csr_pmpaddr47_inputs \\\n  `rvformal_csr_pmpaddr48_inputs \\\n  `rvformal_csr_pmpaddr49_inputs \\\n  `rvformal_csr_pmpaddr50_inputs \\\n  `rvformal_csr_pmpaddr51_inputs \\\n  `rvformal_csr_pmpaddr52_inputs \\\n  `rvformal_csr_pmpaddr53_inputs \\\n  `rvformal_csr_pmpaddr54_inputs \\\n  `rvformal_csr_pmpaddr55_inputs \\\n  `rvformal_csr_pmpaddr56_inputs \\\n  `rvformal_csr_pmpaddr57_inputs \\\n  `rvformal_csr_pmpaddr58_inputs \\\n  `rvformal_csr_pmpaddr59_inputs \\\n  `rvformal_csr_pmpaddr60_inputs \\\n  `rvformal_csr_pmpaddr61_inputs \\\n  `rvformal_csr_pmpaddr62_inputs \\\n  `rvformal_csr_pmpaddr63_inputs \\\n  `rvformal_csr_mhpmevent3_inputs \\\n  `rvformal_csr_mhpmevent4_inputs \\\n  `rvformal_csr_mhpmevent5_inputs \\\n  `rvformal_csr_mhpmevent6_inputs \\\n  `rvformal_csr_mhpmevent7_inputs \\\n  `rvformal_csr_mhpmevent8_inputs \\\n  `rvformal_csr_mhpmevent9_inputs \\\n  `rvformal_csr_mhpmevent10_inputs \\\n  `rvformal_csr_mhpmevent11_inputs \\\n  `rvformal_csr_mhpmevent12_inputs \\\n  `rvformal_csr_mhpmevent13_inputs \\\n  `rvformal_csr_mhpmevent14_inputs \\\n  `rvformal_csr_mhpmevent15_inputs \\\n  `rvformal_csr_mhpmevent16_inputs \\\n  `rvformal_csr_mhpmevent17_inputs \\\n  `rvformal_csr_mhpmevent18_inputs \\\n  `rvformal_csr_mhpmevent19_inputs \\\n  `rvformal_csr_mhpmevent20_inputs \\\n  `rvformal_csr_mhpmevent21_inputs \\\n  `rvformal_csr_mhpmevent22_inputs \\\n  `rvformal_csr_mhpmevent23_inputs \\\n  `rvformal_csr_mhpmevent24_inputs \\\n  `rvformal_csr_mhpmevent25_inputs \\\n  `rvformal_csr_mhpmevent26_inputs \\\n  `rvformal_csr_mhpmevent27_inputs \\\n  `rvformal_csr_mhpmevent28_inputs \\\n  `rvformal_csr_mhpmevent29_inputs \\\n  `rvformal_csr_mhpmevent30_inputs \\\n  `rvformal_csr_mhpmevent31_inputs \\\n  `rvformal_csr_mcycle_inputs \\\n  `rvformal_csr_time_inputs \\\n  `rvformal_csr_minstret_inputs \\\n  `rvformal_csr_mhpmcounter3_inputs \\\n  `rvformal_csr_mhpmcounter4_inputs \\\n  `rvformal_csr_mhpmcounter5_inputs \\\n  `rvformal_csr_mhpmcounter6_inputs \\\n  `rvformal_csr_mhpmcounter7_inputs \\\n  `rvformal_csr_mhpmcounter8_inputs \\\n  `rvformal_csr_mhpmcounter9_inputs \\\n  `rvformal_csr_mhpmcounter10_inputs \\\n  `rvformal_csr_mhpmcounter11_inputs \\\n  `rvformal_csr_mhpmcounter12_inputs \\\n  `rvformal_csr_mhpmcounter13_inputs \\\n  `rvformal_csr_mhpmcounter14_inputs \\\n  `rvformal_csr_mhpmcounter15_inputs \\\n  `rvformal_csr_mhpmcounter16_inputs \\\n  `rvformal_csr_mhpmcounter17_inputs \\\n  `rvformal_csr_mhpmcounter18_inputs \\\n  `rvformal_csr_mhpmcounter19_inputs \\\n  `rvformal_csr_mhpmcounter20_inputs \\\n  `rvformal_csr_mhpmcounter21_inputs \\\n  `rvformal_csr_mhpmcounter22_inputs \\\n  `rvformal_csr_mhpmcounter23_inputs \\\n  `rvformal_csr_mhpmcounter24_inputs \\\n  `rvformal_csr_mhpmcounter25_inputs \\\n  `rvformal_csr_mhpmcounter26_inputs \\\n  `rvformal_csr_mhpmcounter27_inputs \\\n  `rvformal_csr_mhpmcounter28_inputs \\\n  `rvformal_csr_mhpmcounter29_inputs \\\n  `rvformal_csr_mhpmcounter30_inputs \\\n  `rvformal_csr_mhpmcounter31_inputs \\\n  `rvformal_custom_csr_inputs\n`define RVFI_CHANNEL_INPUTS \\\n  input [                       0 : 0] rvfi_valid    , \\\n  input [                64   - 1 : 0] rvfi_order    , \\\n  input [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn     , \\\n  input [                       0 : 0] rvfi_trap     , \\\n  input [                       0 : 0] rvfi_halt     , \\\n  input [                       0 : 0] rvfi_intr     , \\\n  input [                 2   - 1 : 0] rvfi_mode     , \\\n  input [                 2   - 1 : 0] rvfi_ixl      , \\\n  input [                 5   - 1 : 0] rvfi_rs1_addr , \\\n  input [                 5   - 1 : 0] rvfi_rs2_addr , \\\n  input [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata, \\\n  input [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata, \\\n  input [                 5   - 1 : 0] rvfi_rd_addr  , \\\n  input [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rd_wdata , \\\n  input [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata , \\\n  input [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_wdata , \\\n  input [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_addr , \\\n  input [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_rmask, \\\n  input [`RISCV_FORMAL_XLEN/8 - 1 : 0] rvfi_mem_wmask, \\\n  input [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata, \\\n  input [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_wdata \\\n  `rvformal_extamo_channel_inputs \\\n  `rvformal_rollback_channel_inputs \\\n  `rvformal_mem_fault_channel_inputs \\\n  `rvformal_csr_fflags_channel_inputs \\\n  `rvformal_csr_frm_channel_inputs \\\n  `rvformal_csr_fcsr_channel_inputs \\\n  `rvformal_csr_mvendorid_channel_inputs \\\n  `rvformal_csr_marchid_channel_inputs \\\n  `rvformal_csr_mimpid_channel_inputs \\\n  `rvformal_csr_mhartid_channel_inputs \\\n  `rvformal_csr_mconfigptr_channel_inputs \\\n  `rvformal_csr_mstatus_channel_inputs \\\n  `rvformal_csr_mstatush_channel_inputs \\\n  `rvformal_csr_misa_channel_inputs \\\n  `rvformal_csr_medeleg_channel_inputs \\\n  `rvformal_csr_mideleg_channel_inputs \\\n  `rvformal_csr_mie_channel_inputs \\\n  `rvformal_csr_mtvec_channel_inputs \\\n  `rvformal_csr_mcounteren_channel_inputs \\\n  `rvformal_csr_mscratch_channel_inputs \\\n  `rvformal_csr_mepc_channel_inputs \\\n  `rvformal_csr_mcause_channel_inputs \\\n  `rvformal_csr_mtval_channel_inputs \\\n  `rvformal_csr_mip_channel_inputs \\\n  `rvformal_csr_mtinst_channel_inputs \\\n  `rvformal_csr_mtval2_channel_inputs \\\n  `rvformal_csr_mcountinhibit_channel_inputs \\\n  `rvformal_csr_menvcfg_channel_inputs \\\n  `rvformal_csr_menvcfgh_channel_inputs \\\n  `rvformal_csr_pmpcfg0_channel_inputs \\\n  `rvformal_csr_pmpcfg1_channel_inputs \\\n  `rvformal_csr_pmpcfg2_channel_inputs \\\n  `rvformal_csr_pmpcfg3_channel_inputs \\\n  `rvformal_csr_pmpcfg4_channel_inputs \\\n  `rvformal_csr_pmpcfg5_channel_inputs \\\n  `rvformal_csr_pmpcfg6_channel_inputs \\\n  `rvformal_csr_pmpcfg7_channel_inputs \\\n  `rvformal_csr_pmpcfg8_channel_inputs \\\n  `rvformal_csr_pmpcfg9_channel_inputs \\\n  `rvformal_csr_pmpcfg10_channel_inputs \\\n  `rvformal_csr_pmpcfg11_channel_inputs \\\n  `rvformal_csr_pmpcfg12_channel_inputs \\\n  `rvformal_csr_pmpcfg13_channel_inputs \\\n  `rvformal_csr_pmpcfg14_channel_inputs \\\n  `rvformal_csr_pmpcfg15_channel_inputs \\\n  `rvformal_csr_pmpaddr0_channel_inputs \\\n  `rvformal_csr_pmpaddr1_channel_inputs \\\n  `rvformal_csr_pmpaddr2_channel_inputs \\\n  `rvformal_csr_pmpaddr3_channel_inputs \\\n  `rvformal_csr_pmpaddr4_channel_inputs \\\n  `rvformal_csr_pmpaddr5_channel_inputs \\\n  `rvformal_csr_pmpaddr6_channel_inputs \\\n  `rvformal_csr_pmpaddr7_channel_inputs \\\n  `rvformal_csr_pmpaddr8_channel_inputs \\\n  `rvformal_csr_pmpaddr9_channel_inputs \\\n  `rvformal_csr_pmpaddr10_channel_inputs \\\n  `rvformal_csr_pmpaddr11_channel_inputs \\\n  `rvformal_csr_pmpaddr12_channel_inputs \\\n  `rvformal_csr_pmpaddr13_channel_inputs \\\n  `rvformal_csr_pmpaddr14_channel_inputs \\\n  `rvformal_csr_pmpaddr15_channel_inputs \\\n  `rvformal_csr_pmpaddr16_channel_inputs \\\n  `rvformal_csr_pmpaddr17_channel_inputs \\\n  `rvformal_csr_pmpaddr18_channel_inputs \\\n  `rvformal_csr_pmpaddr19_channel_inputs \\\n  `rvformal_csr_pmpaddr20_channel_inputs \\\n  `rvformal_csr_pmpaddr21_channel_inputs \\\n  `rvformal_csr_pmpaddr22_channel_inputs \\\n  `rvformal_csr_pmpaddr23_channel_inputs \\\n  `rvformal_csr_pmpaddr24_channel_inputs \\\n  `rvformal_csr_pmpaddr25_channel_inputs \\\n  `rvformal_csr_pmpaddr26_channel_inputs \\\n  `rvformal_csr_pmpaddr27_channel_inputs \\\n  `rvformal_csr_pmpaddr28_channel_inputs \\\n  `rvformal_csr_pmpaddr29_channel_inputs \\\n  `rvformal_csr_pmpaddr30_channel_inputs \\\n  `rvformal_csr_pmpaddr31_channel_inputs \\\n  `rvformal_csr_pmpaddr32_channel_inputs \\\n  `rvformal_csr_pmpaddr33_channel_inputs \\\n  `rvformal_csr_pmpaddr34_channel_inputs \\\n  `rvformal_csr_pmpaddr35_channel_inputs \\\n  `rvformal_csr_pmpaddr36_channel_inputs \\\n  `rvformal_csr_pmpaddr37_channel_inputs \\\n  `rvformal_csr_pmpaddr38_channel_inputs \\\n  `rvformal_csr_pmpaddr39_channel_inputs \\\n  `rvformal_csr_pmpaddr40_channel_inputs \\\n  `rvformal_csr_pmpaddr41_channel_inputs \\\n  `rvformal_csr_pmpaddr42_channel_inputs \\\n  `rvformal_csr_pmpaddr43_channel_inputs \\\n  `rvformal_csr_pmpaddr44_channel_inputs \\\n  `rvformal_csr_pmpaddr45_channel_inputs \\\n  `rvformal_csr_pmpaddr46_channel_inputs \\\n  `rvformal_csr_pmpaddr47_channel_inputs \\\n  `rvformal_csr_pmpaddr48_channel_inputs \\\n  `rvformal_csr_pmpaddr49_channel_inputs \\\n  `rvformal_csr_pmpaddr50_channel_inputs \\\n  `rvformal_csr_pmpaddr51_channel_inputs \\\n  `rvformal_csr_pmpaddr52_channel_inputs \\\n  `rvformal_csr_pmpaddr53_channel_inputs \\\n  `rvformal_csr_pmpaddr54_channel_inputs \\\n  `rvformal_csr_pmpaddr55_channel_inputs \\\n  `rvformal_csr_pmpaddr56_channel_inputs \\\n  `rvformal_csr_pmpaddr57_channel_inputs \\\n  `rvformal_csr_pmpaddr58_channel_inputs \\\n  `rvformal_csr_pmpaddr59_channel_inputs \\\n  `rvformal_csr_pmpaddr60_channel_inputs \\\n  `rvformal_csr_pmpaddr61_channel_inputs \\\n  `rvformal_csr_pmpaddr62_channel_inputs \\\n  `rvformal_csr_pmpaddr63_channel_inputs \\\n  `rvformal_csr_mhpmevent3_channel_inputs \\\n  `rvformal_csr_mhpmevent4_channel_inputs \\\n  `rvformal_csr_mhpmevent5_channel_inputs \\\n  `rvformal_csr_mhpmevent6_channel_inputs \\\n  `rvformal_csr_mhpmevent7_channel_inputs \\\n  `rvformal_csr_mhpmevent8_channel_inputs \\\n  `rvformal_csr_mhpmevent9_channel_inputs \\\n  `rvformal_csr_mhpmevent10_channel_inputs \\\n  `rvformal_csr_mhpmevent11_channel_inputs \\\n  `rvformal_csr_mhpmevent12_channel_inputs \\\n  `rvformal_csr_mhpmevent13_channel_inputs \\\n  `rvformal_csr_mhpmevent14_channel_inputs \\\n  `rvformal_csr_mhpmevent15_channel_inputs \\\n  `rvformal_csr_mhpmevent16_channel_inputs \\\n  `rvformal_csr_mhpmevent17_channel_inputs \\\n  `rvformal_csr_mhpmevent18_channel_inputs \\\n  `rvformal_csr_mhpmevent19_channel_inputs \\\n  `rvformal_csr_mhpmevent20_channel_inputs \\\n  `rvformal_csr_mhpmevent21_channel_inputs \\\n  `rvformal_csr_mhpmevent22_channel_inputs \\\n  `rvformal_csr_mhpmevent23_channel_inputs \\\n  `rvformal_csr_mhpmevent24_channel_inputs \\\n  `rvformal_csr_mhpmevent25_channel_inputs \\\n  `rvformal_csr_mhpmevent26_channel_inputs \\\n  `rvformal_csr_mhpmevent27_channel_inputs \\\n  `rvformal_csr_mhpmevent28_channel_inputs \\\n  `rvformal_csr_mhpmevent29_channel_inputs \\\n  `rvformal_csr_mhpmevent30_channel_inputs \\\n  `rvformal_csr_mhpmevent31_channel_inputs \\\n  `rvformal_csr_mcycle_channel_inputs \\\n  `rvformal_csr_time_channel_inputs \\\n  `rvformal_csr_minstret_channel_inputs \\\n  `rvformal_csr_mhpmcounter3_channel_inputs \\\n  `rvformal_csr_mhpmcounter4_channel_inputs \\\n  `rvformal_csr_mhpmcounter5_channel_inputs \\\n  `rvformal_csr_mhpmcounter6_channel_inputs \\\n  `rvformal_csr_mhpmcounter7_channel_inputs \\\n  `rvformal_csr_mhpmcounter8_channel_inputs \\\n  `rvformal_csr_mhpmcounter9_channel_inputs \\\n  `rvformal_csr_mhpmcounter10_channel_inputs \\\n  `rvformal_csr_mhpmcounter11_channel_inputs \\\n  `rvformal_csr_mhpmcounter12_channel_inputs \\\n  `rvformal_csr_mhpmcounter13_channel_inputs \\\n  `rvformal_csr_mhpmcounter14_channel_inputs \\\n  `rvformal_csr_mhpmcounter15_channel_inputs \\\n  `rvformal_csr_mhpmcounter16_channel_inputs \\\n  `rvformal_csr_mhpmcounter17_channel_inputs \\\n  `rvformal_csr_mhpmcounter18_channel_inputs \\\n  `rvformal_csr_mhpmcounter19_channel_inputs \\\n  `rvformal_csr_mhpmcounter20_channel_inputs \\\n  `rvformal_csr_mhpmcounter21_channel_inputs \\\n  `rvformal_csr_mhpmcounter22_channel_inputs \\\n  `rvformal_csr_mhpmcounter23_channel_inputs \\\n  `rvformal_csr_mhpmcounter24_channel_inputs \\\n  `rvformal_csr_mhpmcounter25_channel_inputs \\\n  `rvformal_csr_mhpmcounter26_channel_inputs \\\n  `rvformal_csr_mhpmcounter27_channel_inputs \\\n  `rvformal_csr_mhpmcounter28_channel_inputs \\\n  `rvformal_csr_mhpmcounter29_channel_inputs \\\n  `rvformal_csr_mhpmcounter30_channel_inputs \\\n  `rvformal_csr_mhpmcounter31_channel_inputs \\\n  `rvformal_custom_csr_channel_inputs\n`define RVFI_CONN \\\n  .rvfi_valid     (rvfi_valid    ), \\\n  .rvfi_order     (rvfi_order    ), \\\n  .rvfi_insn      (rvfi_insn     ), \\\n  .rvfi_trap      (rvfi_trap     ), \\\n  .rvfi_halt      (rvfi_halt     ), \\\n  .rvfi_intr      (rvfi_intr     ), \\\n  .rvfi_mode      (rvfi_mode     ), \\\n  .rvfi_ixl       (rvfi_ixl      ), \\\n  .rvfi_rs1_addr  (rvfi_rs1_addr ), \\\n  .rvfi_rs2_addr  (rvfi_rs2_addr ), \\\n  .rvfi_rs1_rdata (rvfi_rs1_rdata), \\\n  .rvfi_rs2_rdata (rvfi_rs2_rdata), \\\n  .rvfi_rd_addr   (rvfi_rd_addr  ), \\\n  .rvfi_rd_wdata  (rvfi_rd_wdata ), \\\n  .rvfi_pc_rdata  (rvfi_pc_rdata ), \\\n  .rvfi_pc_wdata  (rvfi_pc_wdata ), \\\n  .rvfi_mem_addr  (rvfi_mem_addr ), \\\n  .rvfi_mem_rmask (rvfi_mem_rmask), \\\n  .rvfi_mem_wmask (rvfi_mem_wmask), \\\n  .rvfi_mem_rdata (rvfi_mem_rdata), \\\n  .rvfi_mem_wdata (rvfi_mem_wdata) \\\n  `rvformal_extamo_conn \\\n  `rvformal_rollback_conn \\\n  `rvformal_mem_fault_conn \\\n  `rvformal_csr_fflags_conn \\\n  `rvformal_csr_frm_conn \\\n  `rvformal_csr_fcsr_conn \\\n  `rvformal_csr_mvendorid_conn \\\n  `rvformal_csr_marchid_conn \\\n  `rvformal_csr_mimpid_conn \\\n  `rvformal_csr_mhartid_conn \\\n  `rvformal_csr_mconfigptr_conn \\\n  `rvformal_csr_mstatus_conn \\\n  `rvformal_csr_mstatush_conn \\\n  `rvformal_csr_misa_conn \\\n  `rvformal_csr_medeleg_conn \\\n  `rvformal_csr_mideleg_conn \\\n  `rvformal_csr_mie_conn \\\n  `rvformal_csr_mtvec_conn \\\n  `rvformal_csr_mcounteren_conn \\\n  `rvformal_csr_mscratch_conn \\\n  `rvformal_csr_mepc_conn \\\n  `rvformal_csr_mcause_conn \\\n  `rvformal_csr_mtval_conn \\\n  `rvformal_csr_mip_conn \\\n  `rvformal_csr_mtinst_conn \\\n  `rvformal_csr_mtval2_conn \\\n  `rvformal_csr_mcountinhibit_conn \\\n  `rvformal_csr_menvcfg_conn \\\n  `rvformal_csr_menvcfgh_conn \\\n  `rvformal_csr_pmpcfg0_conn \\\n  `rvformal_csr_pmpcfg1_conn \\\n  `rvformal_csr_pmpcfg2_conn \\\n  `rvformal_csr_pmpcfg3_conn \\\n  `rvformal_csr_pmpcfg4_conn \\\n  `rvformal_csr_pmpcfg5_conn \\\n  `rvformal_csr_pmpcfg6_conn \\\n  `rvformal_csr_pmpcfg7_conn \\\n  `rvformal_csr_pmpcfg8_conn \\\n  `rvformal_csr_pmpcfg9_conn \\\n  `rvformal_csr_pmpcfg10_conn \\\n  `rvformal_csr_pmpcfg11_conn \\\n  `rvformal_csr_pmpcfg12_conn \\\n  `rvformal_csr_pmpcfg13_conn \\\n  `rvformal_csr_pmpcfg14_conn \\\n  `rvformal_csr_pmpcfg15_conn \\\n  `rvformal_csr_pmpaddr0_conn \\\n  `rvformal_csr_pmpaddr1_conn \\\n  `rvformal_csr_pmpaddr2_conn \\\n  `rvformal_csr_pmpaddr3_conn \\\n  `rvformal_csr_pmpaddr4_conn \\\n  `rvformal_csr_pmpaddr5_conn \\\n  `rvformal_csr_pmpaddr6_conn \\\n  `rvformal_csr_pmpaddr7_conn \\\n  `rvformal_csr_pmpaddr8_conn \\\n  `rvformal_csr_pmpaddr9_conn \\\n  `rvformal_csr_pmpaddr10_conn \\\n  `rvformal_csr_pmpaddr11_conn \\\n  `rvformal_csr_pmpaddr12_conn \\\n  `rvformal_csr_pmpaddr13_conn \\\n  `rvformal_csr_pmpaddr14_conn \\\n  `rvformal_csr_pmpaddr15_conn \\\n  `rvformal_csr_pmpaddr16_conn \\\n  `rvformal_csr_pmpaddr17_conn \\\n  `rvformal_csr_pmpaddr18_conn \\\n  `rvformal_csr_pmpaddr19_conn \\\n  `rvformal_csr_pmpaddr20_conn \\\n  `rvformal_csr_pmpaddr21_conn \\\n  `rvformal_csr_pmpaddr22_conn \\\n  `rvformal_csr_pmpaddr23_conn \\\n  `rvformal_csr_pmpaddr24_conn \\\n  `rvformal_csr_pmpaddr25_conn \\\n  `rvformal_csr_pmpaddr26_conn \\\n  `rvformal_csr_pmpaddr27_conn \\\n  `rvformal_csr_pmpaddr28_conn \\\n  `rvformal_csr_pmpaddr29_conn \\\n  `rvformal_csr_pmpaddr30_conn \\\n  `rvformal_csr_pmpaddr31_conn \\\n  `rvformal_csr_pmpaddr32_conn \\\n  `rvformal_csr_pmpaddr33_conn \\\n  `rvformal_csr_pmpaddr34_conn \\\n  `rvformal_csr_pmpaddr35_conn \\\n  `rvformal_csr_pmpaddr36_conn \\\n  `rvformal_csr_pmpaddr37_conn \\\n  `rvformal_csr_pmpaddr38_conn \\\n  `rvformal_csr_pmpaddr39_conn \\\n  `rvformal_csr_pmpaddr40_conn \\\n  `rvformal_csr_pmpaddr41_conn \\\n  `rvformal_csr_pmpaddr42_conn \\\n  `rvformal_csr_pmpaddr43_conn \\\n  `rvformal_csr_pmpaddr44_conn \\\n  `rvformal_csr_pmpaddr45_conn \\\n  `rvformal_csr_pmpaddr46_conn \\\n  `rvformal_csr_pmpaddr47_conn \\\n  `rvformal_csr_pmpaddr48_conn \\\n  `rvformal_csr_pmpaddr49_conn \\\n  `rvformal_csr_pmpaddr50_conn \\\n  `rvformal_csr_pmpaddr51_conn \\\n  `rvformal_csr_pmpaddr52_conn \\\n  `rvformal_csr_pmpaddr53_conn \\\n  `rvformal_csr_pmpaddr54_conn \\\n  `rvformal_csr_pmpaddr55_conn \\\n  `rvformal_csr_pmpaddr56_conn \\\n  `rvformal_csr_pmpaddr57_conn \\\n  `rvformal_csr_pmpaddr58_conn \\\n  `rvformal_csr_pmpaddr59_conn \\\n  `rvformal_csr_pmpaddr60_conn \\\n  `rvformal_csr_pmpaddr61_conn \\\n  `rvformal_csr_pmpaddr62_conn \\\n  `rvformal_csr_pmpaddr63_conn \\\n  `rvformal_csr_mhpmevent3_conn \\\n  `rvformal_csr_mhpmevent4_conn \\\n  `rvformal_csr_mhpmevent5_conn \\\n  `rvformal_csr_mhpmevent6_conn \\\n  `rvformal_csr_mhpmevent7_conn \\\n  `rvformal_csr_mhpmevent8_conn \\\n  `rvformal_csr_mhpmevent9_conn \\\n  `rvformal_csr_mhpmevent10_conn \\\n  `rvformal_csr_mhpmevent11_conn \\\n  `rvformal_csr_mhpmevent12_conn \\\n  `rvformal_csr_mhpmevent13_conn \\\n  `rvformal_csr_mhpmevent14_conn \\\n  `rvformal_csr_mhpmevent15_conn \\\n  `rvformal_csr_mhpmevent16_conn \\\n  `rvformal_csr_mhpmevent17_conn \\\n  `rvformal_csr_mhpmevent18_conn \\\n  `rvformal_csr_mhpmevent19_conn \\\n  `rvformal_csr_mhpmevent20_conn \\\n  `rvformal_csr_mhpmevent21_conn \\\n  `rvformal_csr_mhpmevent22_conn \\\n  `rvformal_csr_mhpmevent23_conn \\\n  `rvformal_csr_mhpmevent24_conn \\\n  `rvformal_csr_mhpmevent25_conn \\\n  `rvformal_csr_mhpmevent26_conn \\\n  `rvformal_csr_mhpmevent27_conn \\\n  `rvformal_csr_mhpmevent28_conn \\\n  `rvformal_csr_mhpmevent29_conn \\\n  `rvformal_csr_mhpmevent30_conn \\\n  `rvformal_csr_mhpmevent31_conn \\\n  `rvformal_csr_mcycle_conn \\\n  `rvformal_csr_time_conn \\\n  `rvformal_csr_minstret_conn \\\n  `rvformal_csr_mhpmcounter3_conn \\\n  `rvformal_csr_mhpmcounter4_conn \\\n  `rvformal_csr_mhpmcounter5_conn \\\n  `rvformal_csr_mhpmcounter6_conn \\\n  `rvformal_csr_mhpmcounter7_conn \\\n  `rvformal_csr_mhpmcounter8_conn \\\n  `rvformal_csr_mhpmcounter9_conn \\\n  `rvformal_csr_mhpmcounter10_conn \\\n  `rvformal_csr_mhpmcounter11_conn \\\n  `rvformal_csr_mhpmcounter12_conn \\\n  `rvformal_csr_mhpmcounter13_conn \\\n  `rvformal_csr_mhpmcounter14_conn \\\n  `rvformal_csr_mhpmcounter15_conn \\\n  `rvformal_csr_mhpmcounter16_conn \\\n  `rvformal_csr_mhpmcounter17_conn \\\n  `rvformal_csr_mhpmcounter18_conn \\\n  `rvformal_csr_mhpmcounter19_conn \\\n  `rvformal_csr_mhpmcounter20_conn \\\n  `rvformal_csr_mhpmcounter21_conn \\\n  `rvformal_csr_mhpmcounter22_conn \\\n  `rvformal_csr_mhpmcounter23_conn \\\n  `rvformal_csr_mhpmcounter24_conn \\\n  `rvformal_csr_mhpmcounter25_conn \\\n  `rvformal_csr_mhpmcounter26_conn \\\n  `rvformal_csr_mhpmcounter27_conn \\\n  `rvformal_csr_mhpmcounter28_conn \\\n  `rvformal_csr_mhpmcounter29_conn \\\n  `rvformal_csr_mhpmcounter30_conn \\\n  `rvformal_csr_mhpmcounter31_conn \\\n  `rvformal_custom_csr_conn\n`define RVFI_CHANNEL_CONN(_idx) \\\n  .rvfi_valid     (rvfi_valid     [ _idx                         +:                  1  ]), \\\n  .rvfi_order     (rvfi_order     [(_idx)*(                64  ) +:                 64  ]), \\\n  .rvfi_insn      (rvfi_insn      [(_idx)*(`RISCV_FORMAL_ILEN  ) +: `RISCV_FORMAL_ILEN  ]), \\\n  .rvfi_trap      (rvfi_trap      [ _idx                         +:                  1  ]), \\\n  .rvfi_halt      (rvfi_halt      [ _idx                         +:                  1  ]), \\\n  .rvfi_intr      (rvfi_intr      [ _idx                         +:                  1  ]), \\\n  .rvfi_mode      (rvfi_mode      [(_idx)*(                 2  ) +:                  2  ]), \\\n  .rvfi_ixl       (rvfi_ixl       [(_idx)*(                 2  ) +:                  2  ]), \\\n  .rvfi_rs1_addr  (rvfi_rs1_addr  [(_idx)*(                 5  ) +:                  5  ]), \\\n  .rvfi_rs2_addr  (rvfi_rs2_addr  [(_idx)*(                 5  ) +:                  5  ]), \\\n  .rvfi_rs1_rdata (rvfi_rs1_rdata [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]), \\\n  .rvfi_rs2_rdata (rvfi_rs2_rdata [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]), \\\n  .rvfi_rd_addr   (rvfi_rd_addr   [(_idx)*(                 5  ) +:                  5  ]), \\\n  .rvfi_rd_wdata  (rvfi_rd_wdata  [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]), \\\n  .rvfi_pc_rdata  (rvfi_pc_rdata  [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]), \\\n  .rvfi_pc_wdata  (rvfi_pc_wdata  [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]), \\\n  .rvfi_mem_addr  (rvfi_mem_addr  [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]), \\\n  .rvfi_mem_rmask (rvfi_mem_rmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]), \\\n  .rvfi_mem_wmask (rvfi_mem_wmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]), \\\n  .rvfi_mem_rdata (rvfi_mem_rdata [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]), \\\n  .rvfi_mem_wdata (rvfi_mem_wdata [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]) \\\n  `rvformal_extamo_channel_conn(_idx) \\\n  `rvformal_rollback_channel_conn(_idx) \\\n  `rvformal_mem_fault_channel_conn(_idx) \\\n  `rvformal_csr_fflags_channel_conn(_idx) \\\n  `rvformal_csr_frm_channel_conn(_idx) \\\n  `rvformal_csr_fcsr_channel_conn(_idx) \\\n  `rvformal_csr_mvendorid_channel_conn(_idx) \\\n  `rvformal_csr_marchid_channel_conn(_idx) \\\n  `rvformal_csr_mimpid_channel_conn(_idx) \\\n  `rvformal_csr_mhartid_channel_conn(_idx) \\\n  `rvformal_csr_mconfigptr_channel_conn(_idx) \\\n  `rvformal_csr_mstatus_channel_conn(_idx) \\\n  `rvformal_csr_mstatush_channel_conn(_idx) \\\n  `rvformal_csr_misa_channel_conn(_idx) \\\n  `rvformal_csr_medeleg_channel_conn(_idx) \\\n  `rvformal_csr_mideleg_channel_conn(_idx) \\\n  `rvformal_csr_mie_channel_conn(_idx) \\\n  `rvformal_csr_mtvec_channel_conn(_idx) \\\n  `rvformal_csr_mcounteren_channel_conn(_idx) \\\n  `rvformal_csr_mscratch_channel_conn(_idx) \\\n  `rvformal_csr_mepc_channel_conn(_idx) \\\n  `rvformal_csr_mcause_channel_conn(_idx) \\\n  `rvformal_csr_mtval_channel_conn(_idx) \\\n  `rvformal_csr_mip_channel_conn(_idx) \\\n  `rvformal_csr_mtinst_channel_conn(_idx) \\\n  `rvformal_csr_mtval2_channel_conn(_idx) \\\n  `rvformal_csr_mcountinhibit_channel_conn(_idx) \\\n  `rvformal_csr_menvcfg_channel_conn(_idx) \\\n  `rvformal_csr_menvcfgh_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg0_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg1_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg2_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg3_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg4_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg5_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg6_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg7_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg8_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg9_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg10_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg11_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg12_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg13_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg14_channel_conn(_idx) \\\n  `rvformal_csr_pmpcfg15_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr0_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr1_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr2_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr3_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr4_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr5_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr6_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr7_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr8_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr9_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr10_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr11_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr12_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr13_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr14_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr15_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr16_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr17_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr18_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr19_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr20_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr21_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr22_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr23_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr24_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr25_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr26_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr27_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr28_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr29_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr30_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr31_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr32_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr33_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr34_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr35_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr36_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr37_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr38_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr39_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr40_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr41_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr42_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr43_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr44_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr45_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr46_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr47_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr48_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr49_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr50_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr51_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr52_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr53_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr54_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr55_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr56_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr57_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr58_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr59_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr60_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr61_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr62_channel_conn(_idx) \\\n  `rvformal_csr_pmpaddr63_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent3_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent4_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent5_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent6_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent7_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent8_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent9_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent10_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent11_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent12_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent13_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent14_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent15_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent16_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent17_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent18_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent19_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent20_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent21_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent22_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent23_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent24_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent25_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent26_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent27_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent28_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent29_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent30_channel_conn(_idx) \\\n  `rvformal_csr_mhpmevent31_channel_conn(_idx) \\\n  `rvformal_csr_mcycle_channel_conn(_idx) \\\n  `rvformal_csr_time_channel_conn(_idx) \\\n  `rvformal_csr_minstret_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter3_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter4_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter5_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter6_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter7_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter8_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter9_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter10_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter11_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter12_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter13_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter14_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter15_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter16_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter17_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter18_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter19_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter20_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter21_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter22_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter23_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter24_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter25_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter26_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter27_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter28_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter29_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter30_channel_conn(_idx) \\\n  `rvformal_csr_mhpmcounter31_channel_conn(_idx) \\\n  `rvformal_custom_csr_channel_conn(_idx)\n`define RVFI_CONN32 \\\n  .rvfi_valid     (rvfi_valid    ), \\\n  .rvfi_order     (rvfi_order    ), \\\n  .rvfi_insn      (rvfi_insn     ), \\\n  .rvfi_trap      (rvfi_trap     ), \\\n  .rvfi_halt      (rvfi_halt     ), \\\n  .rvfi_intr      (rvfi_intr     ), \\\n  .rvfi_mode      (rvfi_mode     ), \\\n  .rvfi_ixl       (rvfi_ixl      ), \\\n  .rvfi_rs1_addr  (rvfi_rs1_addr ), \\\n  .rvfi_rs2_addr  (rvfi_rs2_addr ), \\\n  .rvfi_rs1_rdata (rvfi_rs1_rdata), \\\n  .rvfi_rs2_rdata (rvfi_rs2_rdata), \\\n  .rvfi_rd_addr   (rvfi_rd_addr  ), \\\n  .rvfi_rd_wdata  (rvfi_rd_wdata ), \\\n  .rvfi_pc_rdata  (rvfi_pc_rdata ), \\\n  .rvfi_pc_wdata  (rvfi_pc_wdata ), \\\n  .rvfi_mem_addr  (rvfi_mem_addr ), \\\n  .rvfi_mem_rmask (rvfi_mem_rmask), \\\n  .rvfi_mem_wmask (rvfi_mem_wmask), \\\n  .rvfi_mem_rdata (rvfi_mem_rdata), \\\n  .rvfi_mem_wdata (rvfi_mem_wdata) \\\n  `rvformal_extamo_conn \\\n  `rvformal_rollback_conn \\\n  `rvformal_mem_fault_conn \\\n  `rvformal_csr_fflags_conn \\\n  `rvformal_csr_frm_conn \\\n  `rvformal_csr_fcsr_conn \\\n  `rvformal_csr_mvendorid_conn \\\n  `rvformal_csr_marchid_conn \\\n  `rvformal_csr_mimpid_conn \\\n  `rvformal_csr_mhartid_conn \\\n  `rvformal_csr_mconfigptr_conn \\\n  `rvformal_csr_mstatus_conn \\\n  `rvformal_csr_mstatush_conn \\\n  `rvformal_csr_misa_conn \\\n  `rvformal_csr_medeleg_conn \\\n  `rvformal_csr_mideleg_conn \\\n  `rvformal_csr_mie_conn \\\n  `rvformal_csr_mtvec_conn \\\n  `rvformal_csr_mcounteren_conn \\\n  `rvformal_csr_mscratch_conn \\\n  `rvformal_csr_mepc_conn \\\n  `rvformal_csr_mcause_conn \\\n  `rvformal_csr_mtval_conn \\\n  `rvformal_csr_mip_conn \\\n  `rvformal_csr_mtinst_conn \\\n  `rvformal_csr_mtval2_conn \\\n  `rvformal_csr_mcountinhibit_conn \\\n  `rvformal_csr_menvcfg_conn \\\n  `rvformal_csr_menvcfgh_conn \\\n  `rvformal_csr_pmpcfg0_conn \\\n  `rvformal_csr_pmpcfg1_conn \\\n  `rvformal_csr_pmpcfg2_conn \\\n  `rvformal_csr_pmpcfg3_conn \\\n  `rvformal_csr_pmpcfg4_conn \\\n  `rvformal_csr_pmpcfg5_conn \\\n  `rvformal_csr_pmpcfg6_conn \\\n  `rvformal_csr_pmpcfg7_conn \\\n  `rvformal_csr_pmpcfg8_conn \\\n  `rvformal_csr_pmpcfg9_conn \\\n  `rvformal_csr_pmpcfg10_conn \\\n  `rvformal_csr_pmpcfg11_conn \\\n  `rvformal_csr_pmpcfg12_conn \\\n  `rvformal_csr_pmpcfg13_conn \\\n  `rvformal_csr_pmpcfg14_conn \\\n  `rvformal_csr_pmpcfg15_conn \\\n  `rvformal_csr_pmpaddr0_conn \\\n  `rvformal_csr_pmpaddr1_conn \\\n  `rvformal_csr_pmpaddr2_conn \\\n  `rvformal_csr_pmpaddr3_conn \\\n  `rvformal_csr_pmpaddr4_conn \\\n  `rvformal_csr_pmpaddr5_conn \\\n  `rvformal_csr_pmpaddr6_conn \\\n  `rvformal_csr_pmpaddr7_conn \\\n  `rvformal_csr_pmpaddr8_conn \\\n  `rvformal_csr_pmpaddr9_conn \\\n  `rvformal_csr_pmpaddr10_conn \\\n  `rvformal_csr_pmpaddr11_conn \\\n  `rvformal_csr_pmpaddr12_conn \\\n  `rvformal_csr_pmpaddr13_conn \\\n  `rvformal_csr_pmpaddr14_conn \\\n  `rvformal_csr_pmpaddr15_conn \\\n  `rvformal_csr_pmpaddr16_conn \\\n  `rvformal_csr_pmpaddr17_conn \\\n  `rvformal_csr_pmpaddr18_conn \\\n  `rvformal_csr_pmpaddr19_conn \\\n  `rvformal_csr_pmpaddr20_conn \\\n  `rvformal_csr_pmpaddr21_conn \\\n  `rvformal_csr_pmpaddr22_conn \\\n  `rvformal_csr_pmpaddr23_conn \\\n  `rvformal_csr_pmpaddr24_conn \\\n  `rvformal_csr_pmpaddr25_conn \\\n  `rvformal_csr_pmpaddr26_conn \\\n  `rvformal_csr_pmpaddr27_conn \\\n  `rvformal_csr_pmpaddr28_conn \\\n  `rvformal_csr_pmpaddr29_conn \\\n  `rvformal_csr_pmpaddr30_conn \\\n  `rvformal_csr_pmpaddr31_conn \\\n  `rvformal_csr_pmpaddr32_conn \\\n  `rvformal_csr_pmpaddr33_conn \\\n  `rvformal_csr_pmpaddr34_conn \\\n  `rvformal_csr_pmpaddr35_conn \\\n  `rvformal_csr_pmpaddr36_conn \\\n  `rvformal_csr_pmpaddr37_conn \\\n  `rvformal_csr_pmpaddr38_conn \\\n  `rvformal_csr_pmpaddr39_conn \\\n  `rvformal_csr_pmpaddr40_conn \\\n  `rvformal_csr_pmpaddr41_conn \\\n  `rvformal_csr_pmpaddr42_conn \\\n  `rvformal_csr_pmpaddr43_conn \\\n  `rvformal_csr_pmpaddr44_conn \\\n  `rvformal_csr_pmpaddr45_conn \\\n  `rvformal_csr_pmpaddr46_conn \\\n  `rvformal_csr_pmpaddr47_conn \\\n  `rvformal_csr_pmpaddr48_conn \\\n  `rvformal_csr_pmpaddr49_conn \\\n  `rvformal_csr_pmpaddr50_conn \\\n  `rvformal_csr_pmpaddr51_conn \\\n  `rvformal_csr_pmpaddr52_conn \\\n  `rvformal_csr_pmpaddr53_conn \\\n  `rvformal_csr_pmpaddr54_conn \\\n  `rvformal_csr_pmpaddr55_conn \\\n  `rvformal_csr_pmpaddr56_conn \\\n  `rvformal_csr_pmpaddr57_conn \\\n  `rvformal_csr_pmpaddr58_conn \\\n  `rvformal_csr_pmpaddr59_conn \\\n  `rvformal_csr_pmpaddr60_conn \\\n  `rvformal_csr_pmpaddr61_conn \\\n  `rvformal_csr_pmpaddr62_conn \\\n  `rvformal_csr_pmpaddr63_conn \\\n  `rvformal_csr_mhpmevent3_conn \\\n  `rvformal_csr_mhpmevent4_conn \\\n  `rvformal_csr_mhpmevent5_conn \\\n  `rvformal_csr_mhpmevent6_conn \\\n  `rvformal_csr_mhpmevent7_conn \\\n  `rvformal_csr_mhpmevent8_conn \\\n  `rvformal_csr_mhpmevent9_conn \\\n  `rvformal_csr_mhpmevent10_conn \\\n  `rvformal_csr_mhpmevent11_conn \\\n  `rvformal_csr_mhpmevent12_conn \\\n  `rvformal_csr_mhpmevent13_conn \\\n  `rvformal_csr_mhpmevent14_conn \\\n  `rvformal_csr_mhpmevent15_conn \\\n  `rvformal_csr_mhpmevent16_conn \\\n  `rvformal_csr_mhpmevent17_conn \\\n  `rvformal_csr_mhpmevent18_conn \\\n  `rvformal_csr_mhpmevent19_conn \\\n  `rvformal_csr_mhpmevent20_conn \\\n  `rvformal_csr_mhpmevent21_conn \\\n  `rvformal_csr_mhpmevent22_conn \\\n  `rvformal_csr_mhpmevent23_conn \\\n  `rvformal_csr_mhpmevent24_conn \\\n  `rvformal_csr_mhpmevent25_conn \\\n  `rvformal_csr_mhpmevent26_conn \\\n  `rvformal_csr_mhpmevent27_conn \\\n  `rvformal_csr_mhpmevent28_conn \\\n  `rvformal_csr_mhpmevent29_conn \\\n  `rvformal_csr_mhpmevent30_conn \\\n  `rvformal_csr_mhpmevent31_conn \\\n  `rvformal_csr_mcycle_conn32 \\\n  `rvformal_csr_time_conn32 \\\n  `rvformal_csr_minstret_conn32 \\\n  `rvformal_csr_mhpmcounter3_conn32 \\\n  `rvformal_csr_mhpmcounter4_conn32 \\\n  `rvformal_csr_mhpmcounter5_conn32 \\\n  `rvformal_csr_mhpmcounter6_conn32 \\\n  `rvformal_csr_mhpmcounter7_conn32 \\\n  `rvformal_csr_mhpmcounter8_conn32 \\\n  `rvformal_csr_mhpmcounter9_conn32 \\\n  `rvformal_csr_mhpmcounter10_conn32 \\\n  `rvformal_csr_mhpmcounter11_conn32 \\\n  `rvformal_csr_mhpmcounter12_conn32 \\\n  `rvformal_csr_mhpmcounter13_conn32 \\\n  `rvformal_csr_mhpmcounter14_conn32 \\\n  `rvformal_csr_mhpmcounter15_conn32 \\\n  `rvformal_csr_mhpmcounter16_conn32 \\\n  `rvformal_csr_mhpmcounter17_conn32 \\\n  `rvformal_csr_mhpmcounter18_conn32 \\\n  `rvformal_csr_mhpmcounter19_conn32 \\\n  `rvformal_csr_mhpmcounter20_conn32 \\\n  `rvformal_csr_mhpmcounter21_conn32 \\\n  `rvformal_csr_mhpmcounter22_conn32 \\\n  `rvformal_csr_mhpmcounter23_conn32 \\\n  `rvformal_csr_mhpmcounter24_conn32 \\\n  `rvformal_csr_mhpmcounter25_conn32 \\\n  `rvformal_csr_mhpmcounter26_conn32 \\\n  `rvformal_csr_mhpmcounter27_conn32 \\\n  `rvformal_csr_mhpmcounter28_conn32 \\\n  `rvformal_csr_mhpmcounter29_conn32 \\\n  `rvformal_csr_mhpmcounter30_conn32 \\\n  `rvformal_csr_mhpmcounter31_conn32 \\\n  `rvformal_custom_csr_conn\n`define RVFI_GETCHANNEL(_idx) \\\n  wire [                       0 : 0] valid     = rvfi_valid     [ _idx                         +:                  1  ]; \\\n  wire [                64   - 1 : 0] order     = rvfi_order     [(_idx)*(                64  ) +:                 64  ]; \\\n  wire [`RISCV_FORMAL_ILEN   - 1 : 0] insn      = rvfi_insn      [(_idx)*(`RISCV_FORMAL_ILEN  ) +: `RISCV_FORMAL_ILEN  ]; \\\n  wire [                       0 : 0] trap      = rvfi_trap      [ _idx                         +:                  1  ]; \\\n  wire [                       0 : 0] halt      = rvfi_halt      [ _idx                         +:                  1  ]; \\\n  wire [                       0 : 0] intr      = rvfi_intr      [ _idx                         +:                  1  ]; \\\n  wire [                 2   - 1 : 0] mode      = rvfi_mode      [(_idx)*(                 2  ) +:                  2  ]; \\\n  wire [                 2   - 1 : 0] ixl       = rvfi_ixl       [(_idx)*(                 2  ) +:                  2  ]; \\\n  wire [                 5   - 1 : 0] rs1_addr  = rvfi_rs1_addr  [(_idx)*(                 5  ) +:                  5  ]; \\\n  wire [                 5   - 1 : 0] rs2_addr  = rvfi_rs2_addr  [(_idx)*(                 5  ) +:                  5  ]; \\\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs1_rdata = rvfi_rs1_rdata [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]; \\\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] rs2_rdata = rvfi_rs2_rdata [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]; \\\n  wire [                 5   - 1 : 0] rd_addr   = rvfi_rd_addr   [(_idx)*(                 5  ) +:                  5  ]; \\\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] rd_wdata  = rvfi_rd_wdata  [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]; \\\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_rdata  = rvfi_pc_rdata  [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]; \\\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] pc_wdata  = rvfi_pc_wdata  [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]; \\\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_addr  = rvfi_mem_addr  [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]; \\\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_rmask = rvfi_mem_rmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]; \\\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] mem_wmask = rvfi_mem_wmask [(_idx)*(`RISCV_FORMAL_XLEN/8) +: `RISCV_FORMAL_XLEN/8]; \\\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_rdata = rvfi_mem_rdata [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]; \\\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] mem_wdata = rvfi_mem_wdata [(_idx)*(`RISCV_FORMAL_XLEN  ) +: `RISCV_FORMAL_XLEN  ]; \\\n  `rvformal_extamo_channel(_idx) \\\n  `rvformal_mem_fault_channel(_idx) \\\n  `rvformal_csr_fflags_channel(_idx) \\\n  `rvformal_csr_frm_channel(_idx) \\\n  `rvformal_csr_fcsr_channel(_idx) \\\n  `rvformal_csr_mvendorid_channel(_idx) \\\n  `rvformal_csr_marchid_channel(_idx) \\\n  `rvformal_csr_mimpid_channel(_idx) \\\n  `rvformal_csr_mhartid_channel(_idx) \\\n  `rvformal_csr_mconfigptr_channel(_idx) \\\n  `rvformal_csr_mstatus_channel(_idx) \\\n  `rvformal_csr_mstatush_channel(_idx) \\\n  `rvformal_csr_misa_channel(_idx) \\\n  `rvformal_csr_medeleg_channel(_idx) \\\n  `rvformal_csr_mideleg_channel(_idx) \\\n  `rvformal_csr_mie_channel(_idx) \\\n  `rvformal_csr_mtvec_channel(_idx) \\\n  `rvformal_csr_mcounteren_channel(_idx) \\\n  `rvformal_csr_mscratch_channel(_idx) \\\n  `rvformal_csr_mepc_channel(_idx) \\\n  `rvformal_csr_mcause_channel(_idx) \\\n  `rvformal_csr_mtval_channel(_idx) \\\n  `rvformal_csr_mip_channel(_idx) \\\n  `rvformal_csr_mtinst_channel(_idx) \\\n  `rvformal_csr_mtval2_channel(_idx) \\\n  `rvformal_csr_mcountinhibit_channel(_idx) \\\n  `rvformal_csr_menvcfg_channel(_idx) \\\n  `rvformal_csr_menvcfgh_channel(_idx) \\\n  `rvformal_csr_pmpcfg0_channel(_idx) \\\n  `rvformal_csr_pmpcfg1_channel(_idx) \\\n  `rvformal_csr_pmpcfg2_channel(_idx) \\\n  `rvformal_csr_pmpcfg3_channel(_idx) \\\n  `rvformal_csr_pmpcfg4_channel(_idx) \\\n  `rvformal_csr_pmpcfg5_channel(_idx) \\\n  `rvformal_csr_pmpcfg6_channel(_idx) \\\n  `rvformal_csr_pmpcfg7_channel(_idx) \\\n  `rvformal_csr_pmpcfg8_channel(_idx) \\\n  `rvformal_csr_pmpcfg9_channel(_idx) \\\n  `rvformal_csr_pmpcfg10_channel(_idx) \\\n  `rvformal_csr_pmpcfg11_channel(_idx) \\\n  `rvformal_csr_pmpcfg12_channel(_idx) \\\n  `rvformal_csr_pmpcfg13_channel(_idx) \\\n  `rvformal_csr_pmpcfg14_channel(_idx) \\\n  `rvformal_csr_pmpcfg15_channel(_idx) \\\n  `rvformal_csr_pmpaddr0_channel(_idx) \\\n  `rvformal_csr_pmpaddr1_channel(_idx) \\\n  `rvformal_csr_pmpaddr2_channel(_idx) \\\n  `rvformal_csr_pmpaddr3_channel(_idx) \\\n  `rvformal_csr_pmpaddr4_channel(_idx) \\\n  `rvformal_csr_pmpaddr5_channel(_idx) \\\n  `rvformal_csr_pmpaddr6_channel(_idx) \\\n  `rvformal_csr_pmpaddr7_channel(_idx) \\\n  `rvformal_csr_pmpaddr8_channel(_idx) \\\n  `rvformal_csr_pmpaddr9_channel(_idx) \\\n  `rvformal_csr_pmpaddr10_channel(_idx) \\\n  `rvformal_csr_pmpaddr11_channel(_idx) \\\n  `rvformal_csr_pmpaddr12_channel(_idx) \\\n  `rvformal_csr_pmpaddr13_channel(_idx) \\\n  `rvformal_csr_pmpaddr14_channel(_idx) \\\n  `rvformal_csr_pmpaddr15_channel(_idx) \\\n  `rvformal_csr_pmpaddr16_channel(_idx) \\\n  `rvformal_csr_pmpaddr17_channel(_idx) \\\n  `rvformal_csr_pmpaddr18_channel(_idx) \\\n  `rvformal_csr_pmpaddr19_channel(_idx) \\\n  `rvformal_csr_pmpaddr20_channel(_idx) \\\n  `rvformal_csr_pmpaddr21_channel(_idx) \\\n  `rvformal_csr_pmpaddr22_channel(_idx) \\\n  `rvformal_csr_pmpaddr23_channel(_idx) \\\n  `rvformal_csr_pmpaddr24_channel(_idx) \\\n  `rvformal_csr_pmpaddr25_channel(_idx) \\\n  `rvformal_csr_pmpaddr26_channel(_idx) \\\n  `rvformal_csr_pmpaddr27_channel(_idx) \\\n  `rvformal_csr_pmpaddr28_channel(_idx) \\\n  `rvformal_csr_pmpaddr29_channel(_idx) \\\n  `rvformal_csr_pmpaddr30_channel(_idx) \\\n  `rvformal_csr_pmpaddr31_channel(_idx) \\\n  `rvformal_csr_pmpaddr32_channel(_idx) \\\n  `rvformal_csr_pmpaddr33_channel(_idx) \\\n  `rvformal_csr_pmpaddr34_channel(_idx) \\\n  `rvformal_csr_pmpaddr35_channel(_idx) \\\n  `rvformal_csr_pmpaddr36_channel(_idx) \\\n  `rvformal_csr_pmpaddr37_channel(_idx) \\\n  `rvformal_csr_pmpaddr38_channel(_idx) \\\n  `rvformal_csr_pmpaddr39_channel(_idx) \\\n  `rvformal_csr_pmpaddr40_channel(_idx) \\\n  `rvformal_csr_pmpaddr41_channel(_idx) \\\n  `rvformal_csr_pmpaddr42_channel(_idx) \\\n  `rvformal_csr_pmpaddr43_channel(_idx) \\\n  `rvformal_csr_pmpaddr44_channel(_idx) \\\n  `rvformal_csr_pmpaddr45_channel(_idx) \\\n  `rvformal_csr_pmpaddr46_channel(_idx) \\\n  `rvformal_csr_pmpaddr47_channel(_idx) \\\n  `rvformal_csr_pmpaddr48_channel(_idx) \\\n  `rvformal_csr_pmpaddr49_channel(_idx) \\\n  `rvformal_csr_pmpaddr50_channel(_idx) \\\n  `rvformal_csr_pmpaddr51_channel(_idx) \\\n  `rvformal_csr_pmpaddr52_channel(_idx) \\\n  `rvformal_csr_pmpaddr53_channel(_idx) \\\n  `rvformal_csr_pmpaddr54_channel(_idx) \\\n  `rvformal_csr_pmpaddr55_channel(_idx) \\\n  `rvformal_csr_pmpaddr56_channel(_idx) \\\n  `rvformal_csr_pmpaddr57_channel(_idx) \\\n  `rvformal_csr_pmpaddr58_channel(_idx) \\\n  `rvformal_csr_pmpaddr59_channel(_idx) \\\n  `rvformal_csr_pmpaddr60_channel(_idx) \\\n  `rvformal_csr_pmpaddr61_channel(_idx) \\\n  `rvformal_csr_pmpaddr62_channel(_idx) \\\n  `rvformal_csr_pmpaddr63_channel(_idx) \\\n  `rvformal_csr_mhpmevent3_channel(_idx) \\\n  `rvformal_csr_mhpmevent4_channel(_idx) \\\n  `rvformal_csr_mhpmevent5_channel(_idx) \\\n  `rvformal_csr_mhpmevent6_channel(_idx) \\\n  `rvformal_csr_mhpmevent7_channel(_idx) \\\n  `rvformal_csr_mhpmevent8_channel(_idx) \\\n  `rvformal_csr_mhpmevent9_channel(_idx) \\\n  `rvformal_csr_mhpmevent10_channel(_idx) \\\n  `rvformal_csr_mhpmevent11_channel(_idx) \\\n  `rvformal_csr_mhpmevent12_channel(_idx) \\\n  `rvformal_csr_mhpmevent13_channel(_idx) \\\n  `rvformal_csr_mhpmevent14_channel(_idx) \\\n  `rvformal_csr_mhpmevent15_channel(_idx) \\\n  `rvformal_csr_mhpmevent16_channel(_idx) \\\n  `rvformal_csr_mhpmevent17_channel(_idx) \\\n  `rvformal_csr_mhpmevent18_channel(_idx) \\\n  `rvformal_csr_mhpmevent19_channel(_idx) \\\n  `rvformal_csr_mhpmevent20_channel(_idx) \\\n  `rvformal_csr_mhpmevent21_channel(_idx) \\\n  `rvformal_csr_mhpmevent22_channel(_idx) \\\n  `rvformal_csr_mhpmevent23_channel(_idx) \\\n  `rvformal_csr_mhpmevent24_channel(_idx) \\\n  `rvformal_csr_mhpmevent25_channel(_idx) \\\n  `rvformal_csr_mhpmevent26_channel(_idx) \\\n  `rvformal_csr_mhpmevent27_channel(_idx) \\\n  `rvformal_csr_mhpmevent28_channel(_idx) \\\n  `rvformal_csr_mhpmevent29_channel(_idx) \\\n  `rvformal_csr_mhpmevent30_channel(_idx) \\\n  `rvformal_csr_mhpmevent31_channel(_idx) \\\n  `rvformal_csr_mcycle_channel(_idx) \\\n  `rvformal_csr_time_channel(_idx) \\\n  `rvformal_csr_minstret_channel(_idx) \\\n  `rvformal_csr_mhpmcounter3_channel(_idx) \\\n  `rvformal_csr_mhpmcounter4_channel(_idx) \\\n  `rvformal_csr_mhpmcounter5_channel(_idx) \\\n  `rvformal_csr_mhpmcounter6_channel(_idx) \\\n  `rvformal_csr_mhpmcounter7_channel(_idx) \\\n  `rvformal_csr_mhpmcounter8_channel(_idx) \\\n  `rvformal_csr_mhpmcounter9_channel(_idx) \\\n  `rvformal_csr_mhpmcounter10_channel(_idx) \\\n  `rvformal_csr_mhpmcounter11_channel(_idx) \\\n  `rvformal_csr_mhpmcounter12_channel(_idx) \\\n  `rvformal_csr_mhpmcounter13_channel(_idx) \\\n  `rvformal_csr_mhpmcounter14_channel(_idx) \\\n  `rvformal_csr_mhpmcounter15_channel(_idx) \\\n  `rvformal_csr_mhpmcounter16_channel(_idx) \\\n  `rvformal_csr_mhpmcounter17_channel(_idx) \\\n  `rvformal_csr_mhpmcounter18_channel(_idx) \\\n  `rvformal_csr_mhpmcounter19_channel(_idx) \\\n  `rvformal_csr_mhpmcounter20_channel(_idx) \\\n  `rvformal_csr_mhpmcounter21_channel(_idx) \\\n  `rvformal_csr_mhpmcounter22_channel(_idx) \\\n  `rvformal_csr_mhpmcounter23_channel(_idx) \\\n  `rvformal_csr_mhpmcounter24_channel(_idx) \\\n  `rvformal_csr_mhpmcounter25_channel(_idx) \\\n  `rvformal_csr_mhpmcounter26_channel(_idx) \\\n  `rvformal_csr_mhpmcounter27_channel(_idx) \\\n  `rvformal_csr_mhpmcounter28_channel(_idx) \\\n  `rvformal_csr_mhpmcounter29_channel(_idx) \\\n  `rvformal_csr_mhpmcounter30_channel(_idx) \\\n  `rvformal_csr_mhpmcounter31_channel(_idx) \\\n  `rvformal_custom_csr_channel(_idx)\n`define RVFI_SIGNALS \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  1  , valid    ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                 64  , order    ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_ILEN  , insn     ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  1  , trap     ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  1  , halt     ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  1  , intr     ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  2  , mode     ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  2  , ixl      ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  5  , rs1_addr ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  5  , rs2_addr ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN  , rs1_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN  , rs2_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET,                  5  , rd_addr  ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN  , rd_wdata ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN  , pc_rdata ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN  , pc_wdata ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN  , mem_addr ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN/8, mem_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN/8, mem_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN  , mem_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NRET, `RISCV_FORMAL_XLEN  , mem_wdata) \\\n  `rvformal_extamo_signals \\\n  `rvformal_mem_fault_signals \\\n  `rvformal_csr_fflags_signals \\\n  `rvformal_csr_frm_signals \\\n  `rvformal_csr_fcsr_signals \\\n  `rvformal_csr_mvendorid_signals \\\n  `rvformal_csr_marchid_signals \\\n  `rvformal_csr_mimpid_signals \\\n  `rvformal_csr_mhartid_signals \\\n  `rvformal_csr_mconfigptr_signals \\\n  `rvformal_csr_mstatus_signals \\\n  `rvformal_csr_mstatush_signals \\\n  `rvformal_csr_misa_signals \\\n  `rvformal_csr_medeleg_signals \\\n  `rvformal_csr_mideleg_signals \\\n  `rvformal_csr_mie_signals \\\n  `rvformal_csr_mtvec_signals \\\n  `rvformal_csr_mcounteren_signals \\\n  `rvformal_csr_mscratch_signals \\\n  `rvformal_csr_mepc_signals \\\n  `rvformal_csr_mcause_signals \\\n  `rvformal_csr_mtval_signals \\\n  `rvformal_csr_mip_signals \\\n  `rvformal_csr_mtinst_signals \\\n  `rvformal_csr_mtval2_signals \\\n  `rvformal_csr_mcountinhibit_signals \\\n  `rvformal_csr_menvcfg_signals \\\n  `rvformal_csr_menvcfgh_signals \\\n  `rvformal_csr_pmpcfg0_signals \\\n  `rvformal_csr_pmpcfg1_signals \\\n  `rvformal_csr_pmpcfg2_signals \\\n  `rvformal_csr_pmpcfg3_signals \\\n  `rvformal_csr_pmpcfg4_signals \\\n  `rvformal_csr_pmpcfg5_signals \\\n  `rvformal_csr_pmpcfg6_signals \\\n  `rvformal_csr_pmpcfg7_signals \\\n  `rvformal_csr_pmpcfg8_signals \\\n  `rvformal_csr_pmpcfg9_signals \\\n  `rvformal_csr_pmpcfg10_signals \\\n  `rvformal_csr_pmpcfg11_signals \\\n  `rvformal_csr_pmpcfg12_signals \\\n  `rvformal_csr_pmpcfg13_signals \\\n  `rvformal_csr_pmpcfg14_signals \\\n  `rvformal_csr_pmpcfg15_signals \\\n  `rvformal_csr_pmpaddr0_signals \\\n  `rvformal_csr_pmpaddr1_signals \\\n  `rvformal_csr_pmpaddr2_signals \\\n  `rvformal_csr_pmpaddr3_signals \\\n  `rvformal_csr_pmpaddr4_signals \\\n  `rvformal_csr_pmpaddr5_signals \\\n  `rvformal_csr_pmpaddr6_signals \\\n  `rvformal_csr_pmpaddr7_signals \\\n  `rvformal_csr_pmpaddr8_signals \\\n  `rvformal_csr_pmpaddr9_signals \\\n  `rvformal_csr_pmpaddr10_signals \\\n  `rvformal_csr_pmpaddr11_signals \\\n  `rvformal_csr_pmpaddr12_signals \\\n  `rvformal_csr_pmpaddr13_signals \\\n  `rvformal_csr_pmpaddr14_signals \\\n  `rvformal_csr_pmpaddr15_signals \\\n  `rvformal_csr_pmpaddr16_signals \\\n  `rvformal_csr_pmpaddr17_signals \\\n  `rvformal_csr_pmpaddr18_signals \\\n  `rvformal_csr_pmpaddr19_signals \\\n  `rvformal_csr_pmpaddr20_signals \\\n  `rvformal_csr_pmpaddr21_signals \\\n  `rvformal_csr_pmpaddr22_signals \\\n  `rvformal_csr_pmpaddr23_signals \\\n  `rvformal_csr_pmpaddr24_signals \\\n  `rvformal_csr_pmpaddr25_signals \\\n  `rvformal_csr_pmpaddr26_signals \\\n  `rvformal_csr_pmpaddr27_signals \\\n  `rvformal_csr_pmpaddr28_signals \\\n  `rvformal_csr_pmpaddr29_signals \\\n  `rvformal_csr_pmpaddr30_signals \\\n  `rvformal_csr_pmpaddr31_signals \\\n  `rvformal_csr_pmpaddr32_signals \\\n  `rvformal_csr_pmpaddr33_signals \\\n  `rvformal_csr_pmpaddr34_signals \\\n  `rvformal_csr_pmpaddr35_signals \\\n  `rvformal_csr_pmpaddr36_signals \\\n  `rvformal_csr_pmpaddr37_signals \\\n  `rvformal_csr_pmpaddr38_signals \\\n  `rvformal_csr_pmpaddr39_signals \\\n  `rvformal_csr_pmpaddr40_signals \\\n  `rvformal_csr_pmpaddr41_signals \\\n  `rvformal_csr_pmpaddr42_signals \\\n  `rvformal_csr_pmpaddr43_signals \\\n  `rvformal_csr_pmpaddr44_signals \\\n  `rvformal_csr_pmpaddr45_signals \\\n  `rvformal_csr_pmpaddr46_signals \\\n  `rvformal_csr_pmpaddr47_signals \\\n  `rvformal_csr_pmpaddr48_signals \\\n  `rvformal_csr_pmpaddr49_signals \\\n  `rvformal_csr_pmpaddr50_signals \\\n  `rvformal_csr_pmpaddr51_signals \\\n  `rvformal_csr_pmpaddr52_signals \\\n  `rvformal_csr_pmpaddr53_signals \\\n  `rvformal_csr_pmpaddr54_signals \\\n  `rvformal_csr_pmpaddr55_signals \\\n  `rvformal_csr_pmpaddr56_signals \\\n  `rvformal_csr_pmpaddr57_signals \\\n  `rvformal_csr_pmpaddr58_signals \\\n  `rvformal_csr_pmpaddr59_signals \\\n  `rvformal_csr_pmpaddr60_signals \\\n  `rvformal_csr_pmpaddr61_signals \\\n  `rvformal_csr_pmpaddr62_signals \\\n  `rvformal_csr_pmpaddr63_signals \\\n  `rvformal_csr_mhpmevent3_signals \\\n  `rvformal_csr_mhpmevent4_signals \\\n  `rvformal_csr_mhpmevent5_signals \\\n  `rvformal_csr_mhpmevent6_signals \\\n  `rvformal_csr_mhpmevent7_signals \\\n  `rvformal_csr_mhpmevent8_signals \\\n  `rvformal_csr_mhpmevent9_signals \\\n  `rvformal_csr_mhpmevent10_signals \\\n  `rvformal_csr_mhpmevent11_signals \\\n  `rvformal_csr_mhpmevent12_signals \\\n  `rvformal_csr_mhpmevent13_signals \\\n  `rvformal_csr_mhpmevent14_signals \\\n  `rvformal_csr_mhpmevent15_signals \\\n  `rvformal_csr_mhpmevent16_signals \\\n  `rvformal_csr_mhpmevent17_signals \\\n  `rvformal_csr_mhpmevent18_signals \\\n  `rvformal_csr_mhpmevent19_signals \\\n  `rvformal_csr_mhpmevent20_signals \\\n  `rvformal_csr_mhpmevent21_signals \\\n  `rvformal_csr_mhpmevent22_signals \\\n  `rvformal_csr_mhpmevent23_signals \\\n  `rvformal_csr_mhpmevent24_signals \\\n  `rvformal_csr_mhpmevent25_signals \\\n  `rvformal_csr_mhpmevent26_signals \\\n  `rvformal_csr_mhpmevent27_signals \\\n  `rvformal_csr_mhpmevent28_signals \\\n  `rvformal_csr_mhpmevent29_signals \\\n  `rvformal_csr_mhpmevent30_signals \\\n  `rvformal_csr_mhpmevent31_signals \\\n  `rvformal_csr_mcycle_signals \\\n  `rvformal_csr_time_signals \\\n  `rvformal_csr_minstret_signals \\\n  `rvformal_csr_mhpmcounter3_signals \\\n  `rvformal_csr_mhpmcounter4_signals \\\n  `rvformal_csr_mhpmcounter5_signals \\\n  `rvformal_csr_mhpmcounter6_signals \\\n  `rvformal_csr_mhpmcounter7_signals \\\n  `rvformal_csr_mhpmcounter8_signals \\\n  `rvformal_csr_mhpmcounter9_signals \\\n  `rvformal_csr_mhpmcounter10_signals \\\n  `rvformal_csr_mhpmcounter11_signals \\\n  `rvformal_csr_mhpmcounter12_signals \\\n  `rvformal_csr_mhpmcounter13_signals \\\n  `rvformal_csr_mhpmcounter14_signals \\\n  `rvformal_csr_mhpmcounter15_signals \\\n  `rvformal_csr_mhpmcounter16_signals \\\n  `rvformal_csr_mhpmcounter17_signals \\\n  `rvformal_csr_mhpmcounter18_signals \\\n  `rvformal_csr_mhpmcounter19_signals \\\n  `rvformal_csr_mhpmcounter20_signals \\\n  `rvformal_csr_mhpmcounter21_signals \\\n  `rvformal_csr_mhpmcounter22_signals \\\n  `rvformal_csr_mhpmcounter23_signals \\\n  `rvformal_csr_mhpmcounter24_signals \\\n  `rvformal_csr_mhpmcounter25_signals \\\n  `rvformal_csr_mhpmcounter26_signals \\\n  `rvformal_csr_mhpmcounter27_signals \\\n  `rvformal_csr_mhpmcounter28_signals \\\n  `rvformal_csr_mhpmcounter29_signals \\\n  `rvformal_csr_mhpmcounter30_signals \\\n  `rvformal_csr_mhpmcounter31_signals \\\n  `rvformal_custom_csr_signals\n\n`define RVFI_CHANNEL(_name, _idx) \\\ngenerate if(1) begin:_name \\\n  `RVFI_GETCHANNEL(_idx) \\\nend endgenerate\n`ifdef RISCV_FORMAL_BUS\n`define RVFI_BUS_WIRES \\\n  (* keep *) wire [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_valid; \\\n  (* keep *) wire [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_insn ; \\\n  (* keep *) wire [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_data ; \\\n  (* keep *) wire [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_fault; \\\n  (* keep *) wire [`RISCV_FORMAL_NBUS *   `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_bus_addr ; \\\n  (* keep *) wire [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask; \\\n  (* keep *) wire [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_rdata; \\\n  (* keep *) wire [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_wdata;\n`define RVFI_BUS_OUTPUTS_NOSEP \\\n  output [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_valid, \\\n  output [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_insn , \\\n  output [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_data , \\\n  output [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_fault, \\\n  output [`RISCV_FORMAL_NBUS *   `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_bus_addr , \\\n  output [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask, \\\n  output [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask, \\\n  output [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_rdata, \\\n  output [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_wdata\n`define RVFI_BUS_CHANNEL_OUTPUTS_NOSEP \\\n  output [                         0 : 0] rvfi_bus_valid, \\\n  output [                         0 : 0] rvfi_bus_insn , \\\n  output [                         0 : 0] rvfi_bus_data , \\\n  output [                         0 : 0] rvfi_bus_fault, \\\n  output [  `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_bus_addr , \\\n  output [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask, \\\n  output [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask, \\\n  output [`RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_rdata, \\\n  output [`RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_wdata\n`define RVFI_BUS_INPUTS_NOSEP \\\n  input [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_valid, \\\n  input [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_insn , \\\n  input [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_data , \\\n  input [`RISCV_FORMAL_NBUS                          - 1 : 0] rvfi_bus_fault, \\\n  input [`RISCV_FORMAL_NBUS *   `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_bus_addr , \\\n  input [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask, \\\n  input [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask, \\\n  input [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_rdata, \\\n  input [`RISCV_FORMAL_NBUS * `RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_wdata\n`define RVFI_BUS_CHANNEL_INPUTS_NOSEP \\\n  input [                         0 : 0] rvfi_bus_valid, \\\n  input [                         0 : 0] rvfi_bus_insn , \\\n  input [                         0 : 0] rvfi_bus_data , \\\n  input [                         0 : 0] rvfi_bus_fault, \\\n  input [  `RISCV_FORMAL_XLEN   - 1 : 0] rvfi_bus_addr , \\\n  input [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_rmask, \\\n  input [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] rvfi_bus_wmask, \\\n  input [`RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_rdata, \\\n  input [`RISCV_FORMAL_BUSLEN   - 1 : 0] rvfi_bus_wdata\n`define RVFI_BUS_CONN_NOSEP \\\n  .rvfi_bus_valid (rvfi_bus_valid), \\\n  .rvfi_bus_insn  (rvfi_bus_insn ), \\\n  .rvfi_bus_data  (rvfi_bus_data ), \\\n  .rvfi_bus_fault (rvfi_bus_fault), \\\n  .rvfi_bus_addr  (rvfi_bus_addr ), \\\n  .rvfi_bus_rmask (rvfi_bus_rmask), \\\n  .rvfi_bus_wmask (rvfi_bus_wmask), \\\n  .rvfi_bus_rdata (rvfi_bus_rdata), \\\n  .rvfi_bus_wdata (rvfi_bus_wdata)\n`define RVFI_BUS_CHANNEL_CONN_NOSEP(_idx) \\\n  .rvfi_bus_valid (rvfi_bus_valid [ _idx                           +:                    1  ]), \\\n  .rvfi_bus_insn  (rvfi_bus_insn  [ _idx                           +:                    1  ]), \\\n  .rvfi_bus_data  (rvfi_bus_data  [ _idx                           +:                    1  ]), \\\n  .rvfi_bus_fault (rvfi_bus_fault [ _idx                           +:                    1  ]), \\\n  .rvfi_bus_addr  (rvfi_bus_addr  [(_idx)*(  `RISCV_FORMAL_XLEN  ) +:   `RISCV_FORMAL_XLEN  ]), \\\n  .rvfi_bus_rmask (rvfi_bus_rmask [(_idx)*(`RISCV_FORMAL_BUSLEN/8) +: `RISCV_FORMAL_BUSLEN/8]), \\\n  .rvfi_bus_wmask (rvfi_bus_wmask [(_idx)*(`RISCV_FORMAL_BUSLEN/8) +: `RISCV_FORMAL_BUSLEN/8]), \\\n  .rvfi_bus_rdata (rvfi_bus_rdata [(_idx)*(`RISCV_FORMAL_BUSLEN  ) +: `RISCV_FORMAL_BUSLEN  ]), \\\n  .rvfi_bus_wdata (rvfi_bus_wdata [(_idx)*(`RISCV_FORMAL_BUSLEN  ) +: `RISCV_FORMAL_BUSLEN  ])\n`define RVFI_BUS_GETCHANNEL(_idx) \\\n  wire [                         0 : 0] bus_valid = rvfi_bus_valid [ _idx                           +:                    1  ]; \\\n  wire [                         0 : 0] bus_insn  = rvfi_bus_insn  [ _idx                           +:                    1  ]; \\\n  wire [                         0 : 0] bus_data  = rvfi_bus_data  [ _idx                           +:                    1  ]; \\\n  wire [                         0 : 0] bus_fault = rvfi_bus_fault [ _idx                           +:                    1  ]; \\\n  wire [  `RISCV_FORMAL_XLEN   - 1 : 0] bus_addr  = rvfi_bus_addr  [(_idx)*(  `RISCV_FORMAL_XLEN  ) +:   `RISCV_FORMAL_XLEN  ]; \\\n  wire [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] bus_rmask = rvfi_bus_rmask [(_idx)*(`RISCV_FORMAL_BUSLEN/8) +: `RISCV_FORMAL_BUSLEN/8]; \\\n  wire [`RISCV_FORMAL_BUSLEN/8 - 1 : 0] bus_wmask = rvfi_bus_wmask [(_idx)*(`RISCV_FORMAL_BUSLEN/8) +: `RISCV_FORMAL_BUSLEN/8]; \\\n  wire [`RISCV_FORMAL_BUSLEN   - 1 : 0] bus_rdata = rvfi_bus_rdata [(_idx)*(`RISCV_FORMAL_BUSLEN  ) +: `RISCV_FORMAL_BUSLEN  ]; \\\n  wire [`RISCV_FORMAL_BUSLEN   - 1 : 0] bus_wdata = rvfi_bus_wdata [(_idx)*(`RISCV_FORMAL_BUSLEN  ) +: `RISCV_FORMAL_BUSLEN  ];\n`define RVFI_BUS_SIGNALS \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS,                    1  , bus_valid) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS,                    1  , bus_insn ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS,                    1  , bus_data ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS,                    1  , bus_fault) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS,   `RISCV_FORMAL_XLEN  , bus_addr ) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, `RISCV_FORMAL_BUSLEN/8, bus_rmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, `RISCV_FORMAL_BUSLEN/8, bus_wmask) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, `RISCV_FORMAL_BUSLEN  , bus_rdata) \\\n  `RISCV_FORMAL_CHANNEL_SIGNAL(`RISCV_FORMAL_NBUS, `RISCV_FORMAL_BUSLEN  , bus_wdata)\n`define RVFI_BUS_OUTPUTS , `RVFI_BUS_OUTPUTS_NOSEP\n`define RVFI_BUS_INPUTS , `RVFI_BUS_INPUTS_NOSEP\n`define RVFI_BUS_CONN  , `RVFI_BUS_CONN_NOSEP\n`define RVFI_BUS_CHANNEL_OUTPUTS , `RVFI_BUS_CHANNEL_OUTPUTS_NOSEP\n`define RVFI_BUS_CHANNEL_INPUTS , `RVFI_BUS_CHANNEL_INPUTS_NOSEP\n`define RVFI_BUS_CHANNEL_CONN(_idx)  , `RVFI_BUS_CHANNEL_CONN_NOSEP(_idx)\n`else\n`define RVFI_BUS_WIRES\n`define RVFI_BUS_OUTPUTS\n`define RVFI_BUS_INPUTS\n`define RVFI_BUS_CONN\n`define RVFI_BUS_GETCHANNEL(_idx)\n`endif\n\n`define RVFI_BUS_CHANNEL(_name, _idx) \\\ngenerate if(1) begin:_name \\\n  `RVFI_BUS_GETCHANNEL(_idx) \\\nend endgenerate\n"
  },
  {
    "path": "checks/rvfi_pc_bwd_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_pc_bwd_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\treg [`RISCV_FORMAL_XLEN-1:0] expect_pc;\n\treg expect_pc_valid = 0;\n\n\twire [`RISCV_FORMAL_XLEN-1:0] pc_wdata = rvfi_pc_wdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\n\tinteger channel_idx;\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\texpect_pc_valid = 0;\n\t\tend else begin\n\t\t\tif (check) begin\n\t\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin\n\t\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order+1) begin\n\t\t\t\t\t\texpect_pc = rvfi_pc_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\t\texpect_pc_valid = !rvfi_intr[`RISCV_FORMAL_CHANNEL_IDX];\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tassume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\tassume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]);\n\t\t\t\tif (expect_pc_valid) begin\n\t\t\t\t\tassert(`rvformal_addr_eq(expect_pc, pc_wdata));\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order+1) begin\n\t\t\t\t\t\texpect_pc = rvfi_pc_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\t\texpect_pc_valid = !rvfi_intr[`RISCV_FORMAL_CHANNEL_IDX];\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_pc_fwd_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_pc_fwd_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\treg [`RISCV_FORMAL_XLEN-1:0] expect_pc;\n\treg expect_pc_valid = 0;\n\n\twire [`RISCV_FORMAL_XLEN-1:0] pc_rdata = rvfi_pc_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\n\tinteger channel_idx;\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\texpect_pc_valid = 0;\n\t\tend else begin\n\t\t\tif (check) begin\n\t\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin\n\t\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order-1) begin\n\t\t\t\t\t\texpect_pc = rvfi_pc_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\t\texpect_pc_valid = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tassume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\tassume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]);\n\t\t\t\tif (expect_pc_valid && !rvfi_intr[`RISCV_FORMAL_CHANNEL_IDX]) begin\n\t\t\t\t\tassert(`rvformal_addr_eq(expect_pc, pc_rdata));\n\t\t\t\tend\n\t\t\tend else begin\n\t\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order-1) begin\n\t\t\t\t\t\texpect_pc = rvfi_pc_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\t\texpect_pc_valid = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_reg_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_reg_check (\n\tinput clock, reset, check,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\t`rvformal_rand_const_reg [4:0] register_index;\n\treg [`RISCV_FORMAL_XLEN-1:0] register_shadow = 0;\n\treg register_written = 0;\n\n\tinteger channel_idx;\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tregister_shadow = 0;\n\t\t\tregister_written = 0;\n\t\tend else begin\n\t\t\tif (check) begin\n\t\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin\n\t\t\t\t\tif (rvfi_valid[channel_idx] && !rvfi_trap[channel_idx] && rvfi_order[64*channel_idx +: 64] < insn_order && register_index == rvfi_rd_addr[channel_idx*5 +: 5]) begin\n\t\t\t\t\t\tregister_shadow = rvfi_rd_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\t\tregister_written = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tassume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\tassume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]);\n\n\t\t\t\tif (register_written && register_index == rvfi_rs1_addr[`RISCV_FORMAL_CHANNEL_IDX*5 +: 5])\n\t\t\t\t\tassert(register_shadow == rvfi_rs1_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]);\n\t\t\t\tif (register_written && register_index == rvfi_rs2_addr[`RISCV_FORMAL_CHANNEL_IDX*5 +: 5])\n\t\t\t\t\tassert(register_shadow == rvfi_rs2_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]);\n\t\t\tend else begin\n\t\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\t\tif (rvfi_valid[channel_idx] && !rvfi_trap[channel_idx] && rvfi_order[64*channel_idx +: 64] < insn_order && register_index == rvfi_rd_addr[channel_idx*5 +: 5]) begin\n\t\t\t\t\t\tregister_shadow = rvfi_rd_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN];\n\t\t\t\t\t\tregister_written = 1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "checks/rvfi_testbench.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_testbench (\n\t`ifdef RISCV_FORMAL_UNBOUNDED\n\t`ifdef RISCV_FORMAL_TRIG_CYCLE\n\t\tinput trig,\n\t`endif\n\t`ifdef RISCV_FORMAL_CHECK_CYCLE\n\t\tinput check,\n\t`endif\n\t`endif\n\tinput clock, reset\n);\n\t`RVFI_WIRES\n\t`RVFI_BUS_WIRES\n\n`ifdef YOSYS\n\talways_comb assume (reset == $initstate);\n`endif\n\n\treg [7:0] cycle_reg = 0;\n\twire [7:0] cycle = reset ? 8'd 0 : cycle_reg;\n\n\talways @(posedge clock) begin\n\t\tcycle_reg <= reset ? 8'd 1 : cycle_reg + (cycle_reg != 8'h ff);\n\tend\n\n\t`RISCV_FORMAL_CHECKER checker_inst (\n\t\t.clock  (clock),\n\t\t.reset  (cycle < `RISCV_FORMAL_RESET_CYCLES),\n`ifdef RISCV_FORMAL_TRIG_CYCLE\n`ifdef RISCV_FORMAL_UNBOUNDED\n\t\t.trig   (trig),\n`else\n\t\t.trig   (cycle == `RISCV_FORMAL_TRIG_CYCLE),\n`endif\n`endif\n`ifdef RISCV_FORMAL_CHECK_CYCLE\n`ifdef RISCV_FORMAL_UNBOUNDED\n\t\t.check   (check),\n`else\n\t\t.check  (cycle == `RISCV_FORMAL_CHECK_CYCLE),\n`endif\n`endif\n\t\t`RVFI_CONN\n\t\t`RVFI_BUS_CONN\n\t);\n\n\trvfi_wrapper wrapper (\n\t\t.clock (clock),\n\t\t.reset (reset),\n\t\t`RVFI_CONN\n\t\t`RVFI_BUS_CONN\n\t);\n\n`ifdef RISCV_FORMAL_ASSUME\n`include \"assume_stmts.vh\"\n`endif\nendmodule\n\nmodule rvfi_seq #(\n\tparameter [1023:0] seq = \"\",\n\tparameter integer N = 1\n) (\n\tinput clock,\n\toutput reg [N-1:0] dout,\n\toutput reg en\n);\n\tlocalparam seqlen = $clog2(seq) / 8;\n\n\tinteger cycle = 0;\n\twire [31:0] position = seqlen - cycle;\n\twire [7:0] ch = seq >> (8*position);\n\n\talways @(posedge clock) begin\n\tcycle <= cycle + 1;\n\tend\n\n\talways @* begin\n\t\ten = |ch;\n\t\tdout = 4'b xxxx;\n\t\tcase (ch)\n\t\t\t\"0\", \"_\": dout = 0;\n\t\t\t\"1\": dout = 1;\n\t\t\t\"2\": dout = 2;\n\t\t\t\"3\": dout = 3;\n\t\t\t\"4\": dout = 4;\n\t\t\t\"5\": dout = 5;\n\t\t\t\"6\": dout = 6;\n\t\t\t\"7\": dout = 7;\n\t\t\t\"8\": dout = 8;\n\t\t\t\"9\": dout = 9;\n\t\t\t\"A\", \"a\": dout = 10;\n\t\t\t\"B\", \"b\": dout = 11;\n\t\t\t\"C\", \"c\": dout = 12;\n\t\t\t\"D\", \"d\": dout = 13;\n\t\t\t\"E\", \"e\": dout = 14;\n\t\t\t\"F\", \"f\", \"-\": dout = 15;\n\t\t\t\"X\", \"x\", \" \": begin\n\t\t\t\tdout = 4'b xxxx;\n\t\t\t\ten = 0;\n\t\t\tend\n\t\tendcase\n\tend\nendmodule\n\nmodule rvfi_assume_seq #(\n\tparameter [1023:0] seq = \"\",\n\tparameter integer N = 1\n) (\n\tinput clock,\n\tinput [N-1:0] din\n);\n\twire en;\n\twire [N-1:0] dout;\n\trvfi_seq #(seq, N) seq_inst (clock, dout, en);\n\talways @* if (en) assume (din == dout);\nendmodule\n"
  },
  {
    "path": "checks/rvfi_unique_check.sv",
    "content": "// Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nmodule rvfi_unique_check (\n\tinput clock, reset, trig, check,\n\t`RVFI_INPUTS\n);\n\t`rvformal_rand_const_reg [63:0] insn_order;\n\treg found_other_insn = 0;\n\n\tinteger channel_idx;\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tfound_other_insn = 0;\n\t\tend else begin\n\t\t\tfor (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin\n\t\t\t\tif (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order &&\n\t\t\t\t\t\t(!trig || channel_idx != `RISCV_FORMAL_CHANNEL_IDX)) begin\n\t\t\t\t\tfound_other_insn = 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tif (trig) begin\n\t\t\t\tassume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]);\n\t\t\t\tassume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]);\n\t\t\tend\n\t\t\tif (check) begin\n\t\t\t\tassert(!found_other_insn);\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "cores/VexRiscv/.gitignore",
    "content": "cover\ncomplete\n/checks/\n/dmemcheck/\n/imemcheck/\n/picorv32.v\n/disasm.s\n/disasm.o\n"
  },
  {
    "path": "cores/VexRiscv/README.md",
    "content": "\nriscv-formal proofs for VexRiscv\n================================\n\n### Current state:\nTest a simple VexRiscv configuration (https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/FormalSimple.scala)\n\nAll standards checks are passing\n- Instruction Checks\n- PC Checks\n- Register Checks\n- Causality\n- Liveness\n\nOthers tests passing :\n- Instruction Memory check\n- Data Memory check\n\n### Quickstart guide:\n\nFirst install Yosys, SymbiYosys, and the solvers. See [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing)\nfor instructions.\n\nTo run all standards checks:\n\n```\npython3 ../../checks/genchecks.py\nmake -C checks -j$(nproc)\n```\n\nTo run again a single check which had failed:\n\n```\n#A single time\npython3 ../../checks/genchecks.py\n\n#Each time\nexport test=insn_beq_ch0; rm -r checks/$test; make -C checks -j$(nproc) $test/PASS; python3 disasm.py checks/$test/engine_0/trace.vcd\n```\n\n\nTo run imem/dmem checks checks : \n\n```\nsby -f imemcheck.sby\nsby -f dmemcheck.sby\n```\n\n### Todo:\n- Integrate others VexRiscv configurations into the framework\n- Add Checking for equivalence of core with and without RVFI check\n- Add Complete check\n- Add Cover check\n\n\n\n\n"
  },
  {
    "path": "cores/VexRiscv/VexRiscv.v",
    "content": "// Generator : SpinalHDL v1.6.4    git head : 598c18959149eb18e5eee5b0aa3eef01ecaa41a1\n// Component : VexRiscv\n// Git hash  : e1620c68b2bfcff7ad1bc8ce665cf4ce29452141\n\n`timescale 1ns/1ps \n\nmodule VexRiscv (\n  output reg          rvfi_valid,\n  output     [63:0]   rvfi_order,\n  output     [31:0]   rvfi_insn,\n  output reg          rvfi_trap,\n  output reg          rvfi_halt,\n  output              rvfi_intr,\n  output     [1:0]    rvfi_mode,\n  output     [1:0]    rvfi_ixl,\n  output     [4:0]    rvfi_rs1_addr,\n  output     [31:0]   rvfi_rs1_rdata,\n  output     [4:0]    rvfi_rs2_addr,\n  output     [31:0]   rvfi_rs2_rdata,\n  output     [4:0]    rvfi_rd_addr,\n  output     [31:0]   rvfi_rd_wdata,\n  output     [31:0]   rvfi_pc_rdata,\n  output     [31:0]   rvfi_pc_wdata,\n  output     [31:0]   rvfi_mem_addr,\n  output     [3:0]    rvfi_mem_rmask,\n  output     [3:0]    rvfi_mem_wmask,\n  output     [31:0]   rvfi_mem_rdata,\n  output     [31:0]   rvfi_mem_wdata,\n  output              iBus_cmd_valid,\n  input               iBus_cmd_ready,\n  output     [31:0]   iBus_cmd_payload_pc,\n  input               iBus_rsp_valid,\n  input               iBus_rsp_payload_error,\n  input      [31:0]   iBus_rsp_payload_inst,\n  output              dBus_cmd_valid,\n  input               dBus_cmd_ready,\n  output              dBus_cmd_payload_wr,\n  output     [31:0]   dBus_cmd_payload_address,\n  output     [31:0]   dBus_cmd_payload_data,\n  output     [1:0]    dBus_cmd_payload_size,\n  input               dBus_rsp_ready,\n  input               dBus_rsp_error,\n  input      [31:0]   dBus_rsp_data,\n  input               clk,\n  input               reset\n);\n  localparam ShiftCtrlEnum_DISABLE_1 = 2'd0;\n  localparam ShiftCtrlEnum_SLL_1 = 2'd1;\n  localparam ShiftCtrlEnum_SRL_1 = 2'd2;\n  localparam ShiftCtrlEnum_SRA_1 = 2'd3;\n  localparam BranchCtrlEnum_INC = 2'd0;\n  localparam BranchCtrlEnum_B = 2'd1;\n  localparam BranchCtrlEnum_JAL = 2'd2;\n  localparam BranchCtrlEnum_JALR = 2'd3;\n  localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0;\n  localparam AluBitwiseCtrlEnum_OR_1 = 2'd1;\n  localparam AluBitwiseCtrlEnum_AND_1 = 2'd2;\n  localparam AluCtrlEnum_ADD_SUB = 2'd0;\n  localparam AluCtrlEnum_SLT_SLTU = 2'd1;\n  localparam AluCtrlEnum_BITWISE = 2'd2;\n  localparam Src2CtrlEnum_RS = 2'd0;\n  localparam Src2CtrlEnum_IMI = 2'd1;\n  localparam Src2CtrlEnum_IMS = 2'd2;\n  localparam Src2CtrlEnum_PC = 2'd3;\n  localparam Src1CtrlEnum_RS = 2'd0;\n  localparam Src1CtrlEnum_IMU = 2'd1;\n  localparam Src1CtrlEnum_PC_INCREMENT = 2'd2;\n  localparam Src1CtrlEnum_URS1 = 2'd3;\n\n  wire                IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready;\n  reg        [54:0]   _zz_IBusSimplePlugin_predictor_history_port1;\n  reg        [31:0]   _zz_RegFilePlugin_regFile_port0;\n  reg        [31:0]   _zz_RegFilePlugin_regFile_port1;\n  wire                IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;\n  wire                IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;\n  wire                IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;\n  wire       [31:0]   IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;\n  wire       [0:0]    IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy;\n  wire       [31:0]   _zz_execute_NEXT_PC2;\n  wire       [2:0]    _zz_execute_NEXT_PC2_1;\n  wire       [31:0]   _zz_execute_SHIFT_RIGHT;\n  wire       [32:0]   _zz_execute_SHIFT_RIGHT_1;\n  wire       [32:0]   _zz_execute_SHIFT_RIGHT_2;\n  wire       [31:0]   _zz_decode_LEGAL_INSTRUCTION;\n  wire       [31:0]   _zz_decode_LEGAL_INSTRUCTION_1;\n  wire       [31:0]   _zz_decode_LEGAL_INSTRUCTION_2;\n  wire                _zz_decode_LEGAL_INSTRUCTION_3;\n  wire       [0:0]    _zz_decode_LEGAL_INSTRUCTION_4;\n  wire       [7:0]    _zz_decode_LEGAL_INSTRUCTION_5;\n  wire       [31:0]   _zz_decode_LEGAL_INSTRUCTION_6;\n  wire       [31:0]   _zz_decode_LEGAL_INSTRUCTION_7;\n  wire       [31:0]   _zz_decode_LEGAL_INSTRUCTION_8;\n  wire                _zz_decode_LEGAL_INSTRUCTION_9;\n  wire       [0:0]    _zz_decode_LEGAL_INSTRUCTION_10;\n  wire       [1:0]    _zz_decode_LEGAL_INSTRUCTION_11;\n  wire       [31:0]   _zz_IBusSimplePlugin_fetchPc_pc;\n  wire       [2:0]    _zz_IBusSimplePlugin_fetchPc_pc_1;\n  wire       [31:0]   _zz_IBusSimplePlugin_decodePc_pcPlus;\n  wire       [2:0]    _zz_IBusSimplePlugin_decodePc_pcPlus_1;\n  wire       [31:0]   _zz_IBusSimplePlugin_decompressor_decompressed_27;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_28;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_29;\n  wire       [6:0]    _zz_IBusSimplePlugin_decompressor_decompressed_30;\n  wire       [4:0]    _zz_IBusSimplePlugin_decompressor_decompressed_31;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_32;\n  wire       [4:0]    _zz_IBusSimplePlugin_decompressor_decompressed_33;\n  wire       [11:0]   _zz_IBusSimplePlugin_decompressor_decompressed_34;\n  wire       [11:0]   _zz_IBusSimplePlugin_decompressor_decompressed_35;\n  wire       [31:0]   _zz__zz_decode_FORMAL_PC_NEXT;\n  wire       [2:0]    _zz__zz_decode_FORMAL_PC_NEXT_1;\n  wire       [54:0]   _zz_IBusSimplePlugin_predictor_history_port;\n  wire       [9:0]    _zz_IBusSimplePlugin_predictor_history_port_1;\n  wire       [9:0]    _zz__zz_IBusSimplePlugin_predictor_buffer_line_source_1;\n  wire       [9:0]    _zz_IBusSimplePlugin_predictor_buffer_hazard;\n  wire       [29:0]   _zz_IBusSimplePlugin_predictor_buffer_hazard_1;\n  wire       [19:0]   _zz_IBusSimplePlugin_predictor_hit;\n  wire       [1:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish;\n  wire       [1:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_1;\n  wire       [0:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_2;\n  wire       [1:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_3;\n  wire       [0:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_4;\n  wire       [1:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_5;\n  wire       [1:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_6;\n  wire       [0:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_7;\n  wire       [1:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_8;\n  wire       [0:0]    _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_9;\n  wire       [29:0]   _zz_IBusSimplePlugin_predictor_historyWrite_payload_address;\n  wire       [2:0]    _zz_IBusSimplePlugin_pending_next;\n  wire       [2:0]    _zz_IBusSimplePlugin_pending_next_1;\n  wire       [0:0]    _zz_IBusSimplePlugin_pending_next_2;\n  wire       [2:0]    _zz_IBusSimplePlugin_pending_next_3;\n  wire       [0:0]    _zz_IBusSimplePlugin_pending_next_4;\n  wire       [2:0]    _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter;\n  wire       [0:0]    _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1;\n  wire       [2:0]    _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2;\n  wire       [0:0]    _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3;\n  wire       [2:0]    _zz_DBusSimplePlugin_memoryExceptionPort_payload_code;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_1;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_2;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_3;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_4;\n  wire       [1:0]    _zz__zz_decode_BRANCH_CTRL_2_5;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_6;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_7;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_8;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_9;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_10;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_11;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_12;\n  wire       [16:0]   _zz__zz_decode_BRANCH_CTRL_2_13;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_14;\n  wire       [1:0]    _zz__zz_decode_BRANCH_CTRL_2_15;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_16;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_17;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_18;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_19;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_20;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_21;\n  wire       [12:0]   _zz__zz_decode_BRANCH_CTRL_2_22;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_23;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_24;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_25;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_26;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_27;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_28;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_29;\n  wire       [1:0]    _zz__zz_decode_BRANCH_CTRL_2_30;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_31;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_32;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_33;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_34;\n  wire       [8:0]    _zz__zz_decode_BRANCH_CTRL_2_35;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_36;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_37;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_38;\n  wire       [1:0]    _zz__zz_decode_BRANCH_CTRL_2_39;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_40;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_41;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_42;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_43;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_44;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_45;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_46;\n  wire       [4:0]    _zz__zz_decode_BRANCH_CTRL_2_47;\n  wire       [1:0]    _zz__zz_decode_BRANCH_CTRL_2_48;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_49;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_50;\n  wire       [31:0]   _zz__zz_decode_BRANCH_CTRL_2_51;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_52;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_53;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_54;\n  wire       [0:0]    _zz__zz_decode_BRANCH_CTRL_2_55;\n  wire       [1:0]    _zz__zz_decode_BRANCH_CTRL_2_56;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_57;\n  wire                _zz__zz_decode_BRANCH_CTRL_2_58;\n  wire                _zz_RegFilePlugin_regFile_port;\n  wire                _zz_decode_RegFilePlugin_rs1Data;\n  wire                _zz_RegFilePlugin_regFile_port_1;\n  wire                _zz_decode_RegFilePlugin_rs2Data;\n  wire       [0:0]    _zz__zz_execute_REGFILE_WRITE_DATA;\n  wire       [2:0]    _zz__zz_decode_SRC1_1;\n  wire       [4:0]    _zz__zz_decode_SRC1_1_1;\n  wire       [11:0]   _zz__zz_decode_SRC2_4;\n  wire       [31:0]   _zz_execute_SrcPlugin_addSub;\n  wire       [31:0]   _zz_execute_SrcPlugin_addSub_1;\n  wire       [31:0]   _zz_execute_SrcPlugin_addSub_2;\n  wire       [31:0]   _zz_execute_SrcPlugin_addSub_3;\n  wire       [31:0]   _zz_execute_SrcPlugin_addSub_4;\n  wire       [31:0]   _zz_execute_SrcPlugin_addSub_5;\n  wire       [31:0]   _zz_execute_SrcPlugin_addSub_6;\n  wire       [19:0]   _zz__zz_execute_BRANCH_SRC22;\n  wire       [11:0]   _zz__zz_execute_BRANCH_SRC22_4;\n  wire       [31:0]   writeBack_FORMAL_MEM_RDATA;\n  wire       [31:0]   memory_MEMORY_READ_DATA;\n  wire                execute_TARGET_MISSMATCH2;\n  wire       [31:0]   execute_NEXT_PC2;\n  wire                execute_BRANCH_DO;\n  wire       [31:0]   execute_SHIFT_RIGHT;\n  wire       [31:0]   writeBack_REGFILE_WRITE_DATA;\n  wire       [31:0]   execute_REGFILE_WRITE_DATA;\n  wire       [31:0]   writeBack_FORMAL_MEM_WDATA;\n  wire       [31:0]   memory_FORMAL_MEM_WDATA;\n  wire       [31:0]   execute_FORMAL_MEM_WDATA;\n  wire       [3:0]    writeBack_FORMAL_MEM_RMASK;\n  wire       [3:0]    memory_FORMAL_MEM_RMASK;\n  wire       [3:0]    execute_FORMAL_MEM_RMASK;\n  wire       [3:0]    writeBack_FORMAL_MEM_WMASK;\n  wire       [3:0]    memory_FORMAL_MEM_WMASK;\n  wire       [3:0]    execute_FORMAL_MEM_WMASK;\n  wire       [31:0]   writeBack_FORMAL_MEM_ADDR;\n  wire       [31:0]   memory_FORMAL_MEM_ADDR;\n  wire       [31:0]   execute_FORMAL_MEM_ADDR;\n  wire       [1:0]    memory_MEMORY_ADDRESS_LOW;\n  wire       [1:0]    execute_MEMORY_ADDRESS_LOW;\n  wire       [31:0]   decode_SRC2;\n  wire       [31:0]   decode_SRC1;\n  wire                decode_SRC2_FORCE_ZERO;\n  wire       [31:0]   writeBack_RS2;\n  wire       [31:0]   memory_RS2;\n  wire       [31:0]   decode_RS2;\n  wire       [31:0]   writeBack_RS1;\n  wire       [31:0]   memory_RS1;\n  wire       [31:0]   decode_RS1;\n  wire       [1:0]    decode_BRANCH_CTRL;\n  wire       [1:0]    _zz_decode_BRANCH_CTRL;\n  wire       [1:0]    _zz_decode_to_execute_BRANCH_CTRL;\n  wire       [1:0]    _zz_decode_to_execute_BRANCH_CTRL_1;\n  wire       [1:0]    _zz_execute_to_memory_SHIFT_CTRL;\n  wire       [1:0]    _zz_execute_to_memory_SHIFT_CTRL_1;\n  wire       [1:0]    decode_SHIFT_CTRL;\n  wire       [1:0]    _zz_decode_SHIFT_CTRL;\n  wire       [1:0]    _zz_decode_to_execute_SHIFT_CTRL;\n  wire       [1:0]    _zz_decode_to_execute_SHIFT_CTRL_1;\n  wire       [1:0]    decode_ALU_BITWISE_CTRL;\n  wire       [1:0]    _zz_decode_ALU_BITWISE_CTRL;\n  wire       [1:0]    _zz_decode_to_execute_ALU_BITWISE_CTRL;\n  wire       [1:0]    _zz_decode_to_execute_ALU_BITWISE_CTRL_1;\n  wire                decode_SRC_LESS_UNSIGNED;\n  wire                writeBack_RS2_USE;\n  wire                memory_RS2_USE;\n  wire                execute_RS2_USE;\n  wire                decode_MEMORY_STORE;\n  wire                execute_BYPASSABLE_MEMORY_STAGE;\n  wire                decode_BYPASSABLE_MEMORY_STAGE;\n  wire                decode_BYPASSABLE_EXECUTE_STAGE;\n  wire       [1:0]    decode_ALU_CTRL;\n  wire       [1:0]    _zz_decode_ALU_CTRL;\n  wire       [1:0]    _zz_decode_to_execute_ALU_CTRL;\n  wire       [1:0]    _zz_decode_to_execute_ALU_CTRL_1;\n  wire                writeBack_RS1_USE;\n  wire                memory_RS1_USE;\n  wire                execute_RS1_USE;\n  wire                decode_MEMORY_ENABLE;\n  wire                execute_PREDICTION_CONTEXT_hazard;\n  wire                execute_PREDICTION_CONTEXT_hit;\n  wire       [19:0]   execute_PREDICTION_CONTEXT_line_source;\n  wire       [1:0]    execute_PREDICTION_CONTEXT_line_branchWish;\n  wire                execute_PREDICTION_CONTEXT_line_last2Bytes;\n  wire       [31:0]   execute_PREDICTION_CONTEXT_line_target;\n  wire                decode_PREDICTION_CONTEXT_hazard;\n  wire                decode_PREDICTION_CONTEXT_hit;\n  wire       [19:0]   decode_PREDICTION_CONTEXT_line_source;\n  wire       [1:0]    decode_PREDICTION_CONTEXT_line_branchWish;\n  wire                decode_PREDICTION_CONTEXT_line_last2Bytes;\n  wire       [31:0]   decode_PREDICTION_CONTEXT_line_target;\n  wire       [31:0]   writeBack_FORMAL_PC_NEXT;\n  wire       [31:0]   memory_FORMAL_PC_NEXT;\n  wire       [31:0]   execute_FORMAL_PC_NEXT;\n  wire       [31:0]   decode_FORMAL_PC_NEXT;\n  wire       [31:0]   writeBack_FORMAL_INSTRUCTION;\n  wire       [31:0]   memory_FORMAL_INSTRUCTION;\n  wire       [31:0]   execute_FORMAL_INSTRUCTION;\n  wire       [31:0]   decode_FORMAL_INSTRUCTION;\n  wire                writeBack_FORMAL_HALT;\n  wire                memory_FORMAL_HALT;\n  wire                execute_FORMAL_HALT;\n  wire                decode_FORMAL_HALT;\n  wire       [31:0]   memory_NEXT_PC2;\n  wire       [31:0]   memory_BRANCH_CALC;\n  wire                memory_TARGET_MISSMATCH2;\n  wire                memory_BRANCH_DO;\n  wire       [31:0]   execute_BRANCH_CALC;\n  wire                execute_IS_RVC;\n  wire       [31:0]   execute_BRANCH_SRC22;\n  wire       [31:0]   execute_PC;\n  wire       [31:0]   execute_RS1;\n  wire       [1:0]    execute_BRANCH_CTRL;\n  wire       [1:0]    _zz_execute_BRANCH_CTRL;\n  wire                decode_RS2_USE;\n  wire                decode_RS1_USE;\n  wire                execute_REGFILE_WRITE_VALID;\n  wire                execute_BYPASSABLE_EXECUTE_STAGE;\n  wire                memory_REGFILE_WRITE_VALID;\n  wire       [31:0]   memory_INSTRUCTION;\n  wire                memory_BYPASSABLE_MEMORY_STAGE;\n  wire                writeBack_REGFILE_WRITE_VALID;\n  wire       [31:0]   memory_SHIFT_RIGHT;\n  reg        [31:0]   _zz_memory_to_writeBack_REGFILE_WRITE_DATA;\n  wire       [1:0]    memory_SHIFT_CTRL;\n  wire       [1:0]    _zz_memory_SHIFT_CTRL;\n  wire       [1:0]    execute_SHIFT_CTRL;\n  wire       [1:0]    _zz_execute_SHIFT_CTRL;\n  wire                execute_SRC_LESS_UNSIGNED;\n  wire                execute_SRC2_FORCE_ZERO;\n  wire                execute_SRC_USE_SUB_LESS;\n  wire       [31:0]   _zz_decode_SRC2;\n  wire       [31:0]   _zz_decode_SRC2_1;\n  wire       [1:0]    decode_SRC2_CTRL;\n  wire       [1:0]    _zz_decode_SRC2_CTRL;\n  wire       [31:0]   _zz_decode_SRC1;\n  wire       [1:0]    decode_SRC1_CTRL;\n  wire       [1:0]    _zz_decode_SRC1_CTRL;\n  wire                decode_SRC_USE_SUB_LESS;\n  wire                decode_SRC_ADD_ZERO;\n  wire       [31:0]   execute_SRC_ADD_SUB;\n  wire                execute_SRC_LESS;\n  wire       [1:0]    execute_ALU_CTRL;\n  wire       [1:0]    _zz_execute_ALU_CTRL;\n  wire       [31:0]   execute_SRC2;\n  wire       [31:0]   execute_SRC1;\n  wire       [1:0]    execute_ALU_BITWISE_CTRL;\n  wire       [1:0]    _zz_execute_ALU_BITWISE_CTRL;\n  reg                 _zz_1;\n  wire       [31:0]   decode_INSTRUCTION_ANTICIPATED;\n  reg                 decode_REGFILE_WRITE_VALID;\n  wire                decode_LEGAL_INSTRUCTION;\n  wire       [1:0]    _zz_decode_BRANCH_CTRL_1;\n  wire       [1:0]    _zz_decode_SHIFT_CTRL_1;\n  wire       [1:0]    _zz_decode_ALU_BITWISE_CTRL_1;\n  wire       [1:0]    _zz_decode_SRC2_CTRL_1;\n  wire       [1:0]    _zz_decode_ALU_CTRL_1;\n  wire       [1:0]    _zz_decode_SRC1_CTRL_1;\n  wire                writeBack_MEMORY_ENABLE;\n  wire       [1:0]    writeBack_MEMORY_ADDRESS_LOW;\n  wire       [31:0]   writeBack_MEMORY_READ_DATA;\n  wire                memory_ALIGNEMENT_FAULT;\n  wire       [31:0]   memory_REGFILE_WRITE_DATA;\n  wire                memory_MEMORY_STORE;\n  wire                memory_MEMORY_ENABLE;\n  wire       [31:0]   execute_SRC_ADD;\n  wire       [31:0]   execute_RS2;\n  wire       [31:0]   execute_INSTRUCTION;\n  wire                execute_MEMORY_STORE;\n  wire                execute_MEMORY_ENABLE;\n  wire                execute_ALIGNEMENT_FAULT;\n  wire                memory_IS_RVC;\n  wire       [31:0]   memory_PC;\n  wire                memory_PREDICTION_CONTEXT_hazard;\n  wire                memory_PREDICTION_CONTEXT_hit;\n  wire       [19:0]   memory_PREDICTION_CONTEXT_line_source;\n  wire       [1:0]    memory_PREDICTION_CONTEXT_line_branchWish;\n  wire                memory_PREDICTION_CONTEXT_line_last2Bytes;\n  wire       [31:0]   memory_PREDICTION_CONTEXT_line_target;\n  reg                 _zz_2;\n  reg        [31:0]   _zz_memory_to_writeBack_FORMAL_PC_NEXT;\n  wire       [31:0]   decode_PC;\n  reg        [31:0]   _zz_decode_FORMAL_PC_NEXT;\n  wire       [31:0]   decode_INSTRUCTION;\n  wire                decode_IS_RVC;\n  reg                 _zz_when_FormalPlugin_l114;\n  reg                 _zz_when_FormalPlugin_l114_1;\n  reg                 _zz_when_FormalPlugin_l114_2;\n  reg                 _zz_when_FormalPlugin_l114_3;\n  reg        [31:0]   _zz_rvfi_rd_wdata;\n  wire                _zz_rvfi_rd_addr;\n  wire                _zz_rvfi_rs2_addr;\n  wire       [31:0]   _zz_rvfi_rs1_addr;\n  wire                _zz_rvfi_rs1_addr_1;\n  wire       [31:0]   writeBack_PC;\n  wire       [31:0]   writeBack_INSTRUCTION;\n  reg                 decode_arbitration_haltItself;\n  reg                 decode_arbitration_haltByOther;\n  reg                 decode_arbitration_removeIt;\n  wire                decode_arbitration_flushIt;\n  wire                decode_arbitration_flushNext;\n  wire                decode_arbitration_isValid;\n  wire                decode_arbitration_isStuck;\n  wire                decode_arbitration_isStuckByOthers;\n  wire                decode_arbitration_isFlushed;\n  wire                decode_arbitration_isMoving;\n  wire                decode_arbitration_isFiring;\n  reg                 execute_arbitration_haltItself;\n  wire                execute_arbitration_haltByOther;\n  reg                 execute_arbitration_removeIt;\n  wire                execute_arbitration_flushIt;\n  wire                execute_arbitration_flushNext;\n  reg                 execute_arbitration_isValid;\n  wire                execute_arbitration_isStuck;\n  wire                execute_arbitration_isStuckByOthers;\n  wire                execute_arbitration_isFlushed;\n  wire                execute_arbitration_isMoving;\n  wire                execute_arbitration_isFiring;\n  reg                 memory_arbitration_haltItself;\n  wire                memory_arbitration_haltByOther;\n  reg                 memory_arbitration_removeIt;\n  wire                memory_arbitration_flushIt;\n  reg                 memory_arbitration_flushNext;\n  reg                 memory_arbitration_isValid;\n  wire                memory_arbitration_isStuck;\n  wire                memory_arbitration_isStuckByOthers;\n  wire                memory_arbitration_isFlushed;\n  wire                memory_arbitration_isMoving;\n  wire                memory_arbitration_isFiring;\n  wire                writeBack_arbitration_haltItself;\n  wire                writeBack_arbitration_haltByOther;\n  reg                 writeBack_arbitration_removeIt;\n  wire                writeBack_arbitration_flushIt;\n  wire                writeBack_arbitration_flushNext;\n  reg                 writeBack_arbitration_isValid;\n  wire                writeBack_arbitration_isStuck;\n  wire                writeBack_arbitration_isStuckByOthers;\n  wire                writeBack_arbitration_isFlushed;\n  wire                writeBack_arbitration_isMoving;\n  wire                writeBack_arbitration_isFiring;\n  wire       [31:0]   lastStageInstruction /* verilator public */ ;\n  wire       [31:0]   lastStagePc /* verilator public */ ;\n  wire                lastStageIsValid /* verilator public */ ;\n  wire                lastStageIsFiring /* verilator public */ ;\n  wire                IBusSimplePlugin_fetcherHalt;\n  reg                 IBusSimplePlugin_incomingInstruction;\n  wire                IBusSimplePlugin_fetchPrediction_cmd_hadBranch;\n  wire       [31:0]   IBusSimplePlugin_fetchPrediction_cmd_targetPc;\n  wire                IBusSimplePlugin_fetchPrediction_rsp_wasRight;\n  wire       [31:0]   IBusSimplePlugin_fetchPrediction_rsp_finalPc;\n  wire       [31:0]   IBusSimplePlugin_fetchPrediction_rsp_sourceLastWord;\n  wire                IBusSimplePlugin_pcValids_0;\n  wire                IBusSimplePlugin_pcValids_1;\n  wire                IBusSimplePlugin_pcValids_2;\n  wire                IBusSimplePlugin_pcValids_3;\n  reg                 DBusSimplePlugin_memoryExceptionPort_valid;\n  reg        [3:0]    DBusSimplePlugin_memoryExceptionPort_payload_code;\n  wire       [31:0]   DBusSimplePlugin_memoryExceptionPort_payload_badAddr;\n  wire                decodeExceptionPort_valid;\n  wire       [3:0]    decodeExceptionPort_payload_code;\n  wire       [31:0]   decodeExceptionPort_payload_badAddr;\n  wire                BranchPlugin_jumpInterface_valid;\n  wire       [31:0]   BranchPlugin_jumpInterface_payload;\n  reg        [63:0]   writeBack_FormalPlugin_order;\n  reg                 writeBack_FormalPlugin_haltRequest;\n  wire                when_FormalPlugin_l114;\n  wire                when_FormalPlugin_l115;\n  wire                when_FormalPlugin_l114_1;\n  wire                when_FormalPlugin_l115_1;\n  wire                when_FormalPlugin_l114_2;\n  wire                when_FormalPlugin_l115_2;\n  wire                when_FormalPlugin_l114_3;\n  wire                when_FormalPlugin_l115_3;\n  reg                 writeBack_FormalPlugin_haltRequest_delay_1;\n  reg                 writeBack_FormalPlugin_haltRequest_delay_2;\n  reg                 writeBack_FormalPlugin_haltRequest_delay_3;\n  reg                 writeBack_FormalPlugin_haltRequest_delay_4;\n  reg                 writeBack_FormalPlugin_haltRequest_delay_5;\n  reg                 writeBack_FormalPlugin_haltFired;\n  wire                when_FormalPlugin_l127;\n  wire                when_HaltOnExceptionPlugin_l34;\n  wire                when_HaltOnExceptionPlugin_l34_1;\n  wire                IBusSimplePlugin_externalFlush;\n  wire                IBusSimplePlugin_jump_pcLoad_valid;\n  wire       [31:0]   IBusSimplePlugin_jump_pcLoad_payload;\n  wire                IBusSimplePlugin_fetchPc_output_valid;\n  wire                IBusSimplePlugin_fetchPc_output_ready;\n  wire       [31:0]   IBusSimplePlugin_fetchPc_output_payload;\n  reg        [31:0]   IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ;\n  reg                 IBusSimplePlugin_fetchPc_correction;\n  reg                 IBusSimplePlugin_fetchPc_correctionReg;\n  wire                IBusSimplePlugin_fetchPc_output_fire;\n  wire                IBusSimplePlugin_fetchPc_corrected;\n  wire                IBusSimplePlugin_fetchPc_pcRegPropagate;\n  reg                 IBusSimplePlugin_fetchPc_booted;\n  reg                 IBusSimplePlugin_fetchPc_inc;\n  wire                when_Fetcher_l131;\n  wire                IBusSimplePlugin_fetchPc_output_fire_1;\n  wire                when_Fetcher_l131_1;\n  reg        [31:0]   IBusSimplePlugin_fetchPc_pc;\n  wire                IBusSimplePlugin_fetchPc_predictionPcLoad_valid;\n  wire       [31:0]   IBusSimplePlugin_fetchPc_predictionPcLoad_payload;\n  wire                IBusSimplePlugin_fetchPc_redo_valid;\n  reg        [31:0]   IBusSimplePlugin_fetchPc_redo_payload;\n  reg                 IBusSimplePlugin_fetchPc_flushed;\n  wire                when_Fetcher_l158;\n  reg                 IBusSimplePlugin_decodePc_flushed;\n  reg        [31:0]   IBusSimplePlugin_decodePc_pcReg /* verilator public */ ;\n  wire       [31:0]   IBusSimplePlugin_decodePc_pcPlus;\n  wire                IBusSimplePlugin_decodePc_injectedDecode;\n  wire                when_Fetcher_l180;\n  wire                IBusSimplePlugin_decodePc_predictionPcLoad_valid;\n  wire       [31:0]   IBusSimplePlugin_decodePc_predictionPcLoad_payload;\n  wire                when_Fetcher_l192;\n  reg                 IBusSimplePlugin_iBusRsp_redoFetch;\n  wire                IBusSimplePlugin_iBusRsp_stages_0_input_valid;\n  wire                IBusSimplePlugin_iBusRsp_stages_0_input_ready;\n  wire       [31:0]   IBusSimplePlugin_iBusRsp_stages_0_input_payload;\n  wire                IBusSimplePlugin_iBusRsp_stages_0_output_valid;\n  wire                IBusSimplePlugin_iBusRsp_stages_0_output_ready;\n  wire       [31:0]   IBusSimplePlugin_iBusRsp_stages_0_output_payload;\n  reg                 IBusSimplePlugin_iBusRsp_stages_0_halt;\n  wire                IBusSimplePlugin_iBusRsp_stages_1_input_valid;\n  wire                IBusSimplePlugin_iBusRsp_stages_1_input_ready;\n  wire       [31:0]   IBusSimplePlugin_iBusRsp_stages_1_input_payload;\n  wire                IBusSimplePlugin_iBusRsp_stages_1_output_valid;\n  wire                IBusSimplePlugin_iBusRsp_stages_1_output_ready;\n  wire       [31:0]   IBusSimplePlugin_iBusRsp_stages_1_output_payload;\n  wire                IBusSimplePlugin_iBusRsp_stages_1_halt;\n  wire                _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready;\n  wire                _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready;\n  wire                IBusSimplePlugin_iBusRsp_flush;\n  wire                IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid;\n  wire                IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_ready;\n  wire       [31:0]   IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload;\n  reg                 _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid;\n  reg        [31:0]   _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload;\n  reg                 IBusSimplePlugin_iBusRsp_readyForError;\n  wire                IBusSimplePlugin_iBusRsp_output_valid;\n  wire                IBusSimplePlugin_iBusRsp_output_ready;\n  wire       [31:0]   IBusSimplePlugin_iBusRsp_output_payload_pc;\n  wire                IBusSimplePlugin_iBusRsp_output_payload_rsp_error;\n  wire       [31:0]   IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;\n  wire                IBusSimplePlugin_iBusRsp_output_payload_isRvc;\n  wire                IBusSimplePlugin_decompressor_input_valid;\n  reg                 IBusSimplePlugin_decompressor_input_ready;\n  wire       [31:0]   IBusSimplePlugin_decompressor_input_payload_pc;\n  wire                IBusSimplePlugin_decompressor_input_payload_rsp_error;\n  wire       [31:0]   IBusSimplePlugin_decompressor_input_payload_rsp_inst;\n  wire                IBusSimplePlugin_decompressor_input_payload_isRvc;\n  wire                IBusSimplePlugin_decompressor_output_valid;\n  wire                IBusSimplePlugin_decompressor_output_ready;\n  wire       [31:0]   IBusSimplePlugin_decompressor_output_payload_pc;\n  wire                IBusSimplePlugin_decompressor_output_payload_rsp_error;\n  wire       [31:0]   IBusSimplePlugin_decompressor_output_payload_rsp_inst;\n  wire                IBusSimplePlugin_decompressor_output_payload_isRvc;\n  wire                IBusSimplePlugin_decompressor_flushNext;\n  wire                IBusSimplePlugin_decompressor_consumeCurrent;\n  reg                 IBusSimplePlugin_decompressor_bufferValid;\n  reg        [15:0]   IBusSimplePlugin_decompressor_bufferData;\n  wire                IBusSimplePlugin_decompressor_isInputLowRvc;\n  wire                IBusSimplePlugin_decompressor_isInputHighRvc;\n  reg                 IBusSimplePlugin_decompressor_throw2BytesReg;\n  wire                IBusSimplePlugin_decompressor_throw2Bytes;\n  wire                IBusSimplePlugin_decompressor_unaligned;\n  reg                 IBusSimplePlugin_decompressor_bufferValidLatch;\n  reg                 IBusSimplePlugin_decompressor_throw2BytesLatch;\n  wire                IBusSimplePlugin_decompressor_bufferValidPatched;\n  wire                IBusSimplePlugin_decompressor_throw2BytesPatched;\n  wire       [31:0]   IBusSimplePlugin_decompressor_raw;\n  wire                IBusSimplePlugin_decompressor_isRvc;\n  wire       [15:0]   _zz_IBusSimplePlugin_decompressor_decompressed;\n  reg        [31:0]   IBusSimplePlugin_decompressor_decompressed;\n  wire       [4:0]    _zz_IBusSimplePlugin_decompressor_decompressed_1;\n  wire       [4:0]    _zz_IBusSimplePlugin_decompressor_decompressed_2;\n  wire       [11:0]   _zz_IBusSimplePlugin_decompressor_decompressed_3;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_4;\n  reg        [11:0]   _zz_IBusSimplePlugin_decompressor_decompressed_5;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_6;\n  reg        [9:0]    _zz_IBusSimplePlugin_decompressor_decompressed_7;\n  wire       [20:0]   _zz_IBusSimplePlugin_decompressor_decompressed_8;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_9;\n  reg        [14:0]   _zz_IBusSimplePlugin_decompressor_decompressed_10;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_11;\n  reg        [2:0]    _zz_IBusSimplePlugin_decompressor_decompressed_12;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_13;\n  reg        [9:0]    _zz_IBusSimplePlugin_decompressor_decompressed_14;\n  wire       [20:0]   _zz_IBusSimplePlugin_decompressor_decompressed_15;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_16;\n  reg        [4:0]    _zz_IBusSimplePlugin_decompressor_decompressed_17;\n  wire       [12:0]   _zz_IBusSimplePlugin_decompressor_decompressed_18;\n  wire       [4:0]    _zz_IBusSimplePlugin_decompressor_decompressed_19;\n  wire       [4:0]    _zz_IBusSimplePlugin_decompressor_decompressed_20;\n  wire       [4:0]    _zz_IBusSimplePlugin_decompressor_decompressed_21;\n  wire       [4:0]    switch_Misc_l44;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_22;\n  wire       [1:0]    switch_Misc_l211;\n  wire       [1:0]    switch_Misc_l211_1;\n  reg        [2:0]    _zz_IBusSimplePlugin_decompressor_decompressed_23;\n  reg        [2:0]    _zz_IBusSimplePlugin_decompressor_decompressed_24;\n  wire                _zz_IBusSimplePlugin_decompressor_decompressed_25;\n  reg        [6:0]    _zz_IBusSimplePlugin_decompressor_decompressed_26;\n  wire                IBusSimplePlugin_decompressor_output_fire;\n  wire                IBusSimplePlugin_decompressor_bufferFill;\n  wire                when_Fetcher_l283;\n  wire                when_Fetcher_l286;\n  wire                when_Fetcher_l291;\n  wire                IBusSimplePlugin_injector_decodeInput_valid;\n  wire                IBusSimplePlugin_injector_decodeInput_ready;\n  wire       [31:0]   IBusSimplePlugin_injector_decodeInput_payload_pc;\n  wire                IBusSimplePlugin_injector_decodeInput_payload_rsp_error;\n  wire       [31:0]   IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;\n  wire                IBusSimplePlugin_injector_decodeInput_payload_isRvc;\n  reg                 _zz_IBusSimplePlugin_injector_decodeInput_valid;\n  reg        [31:0]   _zz_IBusSimplePlugin_injector_decodeInput_payload_pc;\n  reg                 _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error;\n  reg        [31:0]   _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;\n  reg                 _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc;\n  reg                 IBusSimplePlugin_injector_nextPcCalc_valids_0;\n  wire                when_Fetcher_l329;\n  reg                 IBusSimplePlugin_injector_nextPcCalc_valids_1;\n  wire                when_Fetcher_l329_1;\n  reg                 IBusSimplePlugin_injector_nextPcCalc_valids_2;\n  wire                when_Fetcher_l329_2;\n  reg                 IBusSimplePlugin_injector_nextPcCalc_valids_3;\n  wire                when_Fetcher_l329_3;\n  reg        [31:0]   IBusSimplePlugin_injector_formal_rawInDecode;\n  wire                IBusSimplePlugin_predictor_historyWriteDelayPatched_valid;\n  wire       [9:0]    IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_address;\n  wire       [19:0]   IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_source;\n  wire       [1:0]    IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_branchWish;\n  wire                IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_last2Bytes;\n  wire       [31:0]   IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_target;\n  reg                 IBusSimplePlugin_predictor_historyWrite_valid;\n  reg        [9:0]    IBusSimplePlugin_predictor_historyWrite_payload_address;\n  wire       [19:0]   IBusSimplePlugin_predictor_historyWrite_payload_data_source;\n  reg        [1:0]    IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish;\n  wire                IBusSimplePlugin_predictor_historyWrite_payload_data_last2Bytes;\n  wire       [31:0]   IBusSimplePlugin_predictor_historyWrite_payload_data_target;\n  reg                 IBusSimplePlugin_predictor_writeLast_valid;\n  reg        [9:0]    IBusSimplePlugin_predictor_writeLast_payload_address;\n  reg        [19:0]   IBusSimplePlugin_predictor_writeLast_payload_data_source;\n  reg        [1:0]    IBusSimplePlugin_predictor_writeLast_payload_data_branchWish;\n  reg                 IBusSimplePlugin_predictor_writeLast_payload_data_last2Bytes;\n  reg        [31:0]   IBusSimplePlugin_predictor_writeLast_payload_data_target;\n  wire       [29:0]   _zz_IBusSimplePlugin_predictor_buffer_line_source;\n  wire       [19:0]   IBusSimplePlugin_predictor_buffer_line_source;\n  wire       [1:0]    IBusSimplePlugin_predictor_buffer_line_branchWish;\n  wire                IBusSimplePlugin_predictor_buffer_line_last2Bytes;\n  wire       [31:0]   IBusSimplePlugin_predictor_buffer_line_target;\n  wire       [54:0]   _zz_IBusSimplePlugin_predictor_buffer_line_source_1;\n  reg                 IBusSimplePlugin_predictor_buffer_pcCorrected;\n  wire                IBusSimplePlugin_predictor_buffer_hazard;\n  reg        [19:0]   IBusSimplePlugin_predictor_line_source;\n  reg        [1:0]    IBusSimplePlugin_predictor_line_branchWish;\n  reg                 IBusSimplePlugin_predictor_line_last2Bytes;\n  reg        [31:0]   IBusSimplePlugin_predictor_line_target;\n  reg                 IBusSimplePlugin_predictor_buffer_hazard_regNextWhen;\n  wire                IBusSimplePlugin_predictor_hazard;\n  reg                 IBusSimplePlugin_predictor_hit;\n  wire                when_Fetcher_l550;\n  wire                IBusSimplePlugin_predictor_fetchContext_hazard;\n  wire                IBusSimplePlugin_predictor_fetchContext_hit;\n  wire       [19:0]   IBusSimplePlugin_predictor_fetchContext_line_source;\n  wire       [1:0]    IBusSimplePlugin_predictor_fetchContext_line_branchWish;\n  wire                IBusSimplePlugin_predictor_fetchContext_line_last2Bytes;\n  wire       [31:0]   IBusSimplePlugin_predictor_fetchContext_line_target;\n  wire                IBusSimplePlugin_predictor_iBusRspContextOutput_hazard;\n  reg                 IBusSimplePlugin_predictor_iBusRspContextOutput_hit;\n  wire       [19:0]   IBusSimplePlugin_predictor_iBusRspContextOutput_line_source;\n  wire       [1:0]    IBusSimplePlugin_predictor_iBusRspContextOutput_line_branchWish;\n  wire                IBusSimplePlugin_predictor_iBusRspContextOutput_line_last2Bytes;\n  wire       [31:0]   IBusSimplePlugin_predictor_iBusRspContextOutput_line_target;\n  reg                 IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hazard;\n  reg                 IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hit;\n  reg        [19:0]   IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_source;\n  reg        [1:0]    IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_branchWish;\n  reg                 IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_last2Bytes;\n  reg        [31:0]   IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_target;\n  wire                IBusSimplePlugin_predictor_injectorContext_hazard;\n  wire                IBusSimplePlugin_predictor_injectorContext_hit;\n  wire       [19:0]   IBusSimplePlugin_predictor_injectorContext_line_source;\n  wire       [1:0]    IBusSimplePlugin_predictor_injectorContext_line_branchWish;\n  wire                IBusSimplePlugin_predictor_injectorContext_line_last2Bytes;\n  wire       [31:0]   IBusSimplePlugin_predictor_injectorContext_line_target;\n  wire                when_Fetcher_l596;\n  wire                IBusSimplePlugin_predictor_compressor_predictionBranch;\n  wire                IBusSimplePlugin_predictor_compressor_unalignedWordIssue;\n  wire                when_Fetcher_l611;\n  wire                IBusSimplePlugin_injector_decodeInput_fire;\n  wire                IBusSimplePlugin_decompressor_output_fire_1;\n  wire                when_Fetcher_l617;\n  wire                IBusSimplePlugin_cmd_valid;\n  wire                IBusSimplePlugin_cmd_ready;\n  wire       [31:0]   IBusSimplePlugin_cmd_payload_pc;\n  wire                IBusSimplePlugin_pending_inc;\n  wire                IBusSimplePlugin_pending_dec;\n  reg        [2:0]    IBusSimplePlugin_pending_value;\n  wire       [2:0]    IBusSimplePlugin_pending_next;\n  wire                IBusSimplePlugin_cmdFork_canEmit;\n  wire                when_IBusSimplePlugin_l305;\n  wire                IBusSimplePlugin_cmd_fire;\n  wire                IBusSimplePlugin_rspJoin_rspBuffer_output_valid;\n  wire                IBusSimplePlugin_rspJoin_rspBuffer_output_ready;\n  wire                IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error;\n  wire       [31:0]   IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst;\n  reg        [2:0]    IBusSimplePlugin_rspJoin_rspBuffer_discardCounter;\n  wire                iBus_rsp_toStream_valid;\n  wire                iBus_rsp_toStream_ready;\n  wire                iBus_rsp_toStream_payload_error;\n  wire       [31:0]   iBus_rsp_toStream_payload_inst;\n  wire                IBusSimplePlugin_rspJoin_rspBuffer_flush;\n  wire                IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire;\n  wire       [31:0]   IBusSimplePlugin_rspJoin_fetchRsp_pc;\n  reg                 IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;\n  wire       [31:0]   IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;\n  wire                IBusSimplePlugin_rspJoin_fetchRsp_isRvc;\n  wire                when_IBusSimplePlugin_l376;\n  wire                IBusSimplePlugin_rspJoin_join_valid;\n  wire                IBusSimplePlugin_rspJoin_join_ready;\n  wire       [31:0]   IBusSimplePlugin_rspJoin_join_payload_pc;\n  wire                IBusSimplePlugin_rspJoin_join_payload_rsp_error;\n  wire       [31:0]   IBusSimplePlugin_rspJoin_join_payload_rsp_inst;\n  wire                IBusSimplePlugin_rspJoin_join_payload_isRvc;\n  wire                IBusSimplePlugin_rspJoin_exceptionDetected;\n  wire                IBusSimplePlugin_rspJoin_join_fire;\n  wire                IBusSimplePlugin_rspJoin_join_fire_1;\n  wire                _zz_IBusSimplePlugin_iBusRsp_output_valid;\n  wire                _zz_dBus_cmd_valid;\n  reg                 execute_DBusSimplePlugin_skipCmd;\n  reg        [31:0]   _zz_dBus_cmd_payload_data;\n  wire                when_DBusSimplePlugin_l428;\n  reg        [3:0]    _zz_execute_DBusSimplePlugin_formalMask;\n  wire       [3:0]    execute_DBusSimplePlugin_formalMask;\n  wire                when_DBusSimplePlugin_l482;\n  wire                when_DBusSimplePlugin_l515;\n  reg        [31:0]   writeBack_DBusSimplePlugin_rspShifted;\n  wire       [1:0]    switch_Misc_l211_2;\n  wire                _zz_writeBack_DBusSimplePlugin_rspFormated;\n  reg        [31:0]   _zz_writeBack_DBusSimplePlugin_rspFormated_1;\n  wire                _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n  reg        [31:0]   _zz_writeBack_DBusSimplePlugin_rspFormated_3;\n  reg        [31:0]   writeBack_DBusSimplePlugin_rspFormated;\n  wire                when_DBusSimplePlugin_l558;\n  wire       [22:0]   _zz_decode_BRANCH_CTRL_2;\n  wire                _zz_decode_BRANCH_CTRL_3;\n  wire                _zz_decode_BRANCH_CTRL_4;\n  wire                _zz_decode_BRANCH_CTRL_5;\n  wire                _zz_decode_BRANCH_CTRL_6;\n  wire       [1:0]    _zz_decode_SRC1_CTRL_2;\n  wire       [1:0]    _zz_decode_ALU_CTRL_2;\n  wire       [1:0]    _zz_decode_SRC2_CTRL_2;\n  wire       [1:0]    _zz_decode_ALU_BITWISE_CTRL_2;\n  wire       [1:0]    _zz_decode_SHIFT_CTRL_2;\n  wire       [1:0]    _zz_decode_BRANCH_CTRL_7;\n  wire                when_RegFilePlugin_l63;\n  wire       [4:0]    decode_RegFilePlugin_regFileReadAddress1;\n  wire       [4:0]    decode_RegFilePlugin_regFileReadAddress2;\n  wire       [31:0]   decode_RegFilePlugin_rs1Data;\n  wire       [31:0]   decode_RegFilePlugin_rs2Data;\n  reg                 lastStageRegFileWrite_valid /* verilator public */ ;\n  reg        [4:0]    lastStageRegFileWrite_payload_address /* verilator public */ ;\n  reg        [31:0]   lastStageRegFileWrite_payload_data /* verilator public */ ;\n  reg                 _zz_3;\n  reg        [31:0]   execute_IntAluPlugin_bitwise;\n  reg        [31:0]   _zz_execute_REGFILE_WRITE_DATA;\n  reg        [31:0]   _zz_decode_SRC1_1;\n  wire                _zz_decode_SRC2_2;\n  reg        [19:0]   _zz_decode_SRC2_3;\n  wire                _zz_decode_SRC2_4;\n  reg        [19:0]   _zz_decode_SRC2_5;\n  reg        [31:0]   _zz_decode_SRC2_6;\n  reg        [31:0]   execute_SrcPlugin_addSub;\n  wire                execute_SrcPlugin_less;\n  wire       [4:0]    execute_FullBarrelShifterPlugin_amplitude;\n  reg        [31:0]   _zz_execute_FullBarrelShifterPlugin_reversed;\n  wire       [31:0]   execute_FullBarrelShifterPlugin_reversed;\n  reg        [31:0]   _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1;\n  reg                 HazardSimplePlugin_src0Hazard;\n  reg                 HazardSimplePlugin_src1Hazard;\n  wire                HazardSimplePlugin_writeBackWrites_valid;\n  wire       [4:0]    HazardSimplePlugin_writeBackWrites_payload_address;\n  wire       [31:0]   HazardSimplePlugin_writeBackWrites_payload_data;\n  reg                 HazardSimplePlugin_writeBackBuffer_valid;\n  reg        [4:0]    HazardSimplePlugin_writeBackBuffer_payload_address;\n  reg        [31:0]   HazardSimplePlugin_writeBackBuffer_payload_data;\n  wire                HazardSimplePlugin_addr0Match;\n  wire                HazardSimplePlugin_addr1Match;\n  wire                when_HazardSimplePlugin_l59;\n  wire                when_HazardSimplePlugin_l62;\n  wire                when_HazardSimplePlugin_l57;\n  wire                when_HazardSimplePlugin_l58;\n  wire                when_HazardSimplePlugin_l59_1;\n  wire                when_HazardSimplePlugin_l62_1;\n  wire                when_HazardSimplePlugin_l57_1;\n  wire                when_HazardSimplePlugin_l58_1;\n  wire                when_HazardSimplePlugin_l59_2;\n  wire                when_HazardSimplePlugin_l62_2;\n  wire                when_HazardSimplePlugin_l57_2;\n  wire                when_HazardSimplePlugin_l58_2;\n  wire                when_HazardSimplePlugin_l105;\n  wire                when_HazardSimplePlugin_l108;\n  wire                when_HazardSimplePlugin_l113;\n  wire                execute_BranchPlugin_eq;\n  wire       [2:0]    switch_Misc_l211_3;\n  reg                 _zz_execute_BRANCH_DO;\n  reg                 _zz_execute_BRANCH_DO_1;\n  wire       [31:0]   execute_BranchPlugin_branch_src1;\n  wire                _zz_execute_BRANCH_SRC22;\n  reg        [10:0]   _zz_execute_BRANCH_SRC22_1;\n  wire                _zz_execute_BRANCH_SRC22_2;\n  reg        [19:0]   _zz_execute_BRANCH_SRC22_3;\n  wire                _zz_execute_BRANCH_SRC22_4;\n  reg        [18:0]   _zz_execute_BRANCH_SRC22_5;\n  reg        [31:0]   _zz_execute_BRANCH_SRC22_6;\n  wire       [31:0]   execute_BranchPlugin_branchAdder;\n  wire                memory_BranchPlugin_predictionMissmatch;\n  wire                when_Pipeline_l124;\n  reg                 decode_to_execute_FORMAL_HALT;\n  wire                when_Pipeline_l124_1;\n  reg                 execute_to_memory_FORMAL_HALT;\n  wire                when_Pipeline_l124_2;\n  reg                 memory_to_writeBack_FORMAL_HALT;\n  wire                when_Pipeline_l124_3;\n  reg        [31:0]   decode_to_execute_PC;\n  wire                when_Pipeline_l124_4;\n  reg        [31:0]   execute_to_memory_PC;\n  wire                when_Pipeline_l124_5;\n  reg        [31:0]   memory_to_writeBack_PC;\n  wire                when_Pipeline_l124_6;\n  reg        [31:0]   decode_to_execute_INSTRUCTION;\n  wire                when_Pipeline_l124_7;\n  reg        [31:0]   execute_to_memory_INSTRUCTION;\n  wire                when_Pipeline_l124_8;\n  reg        [31:0]   memory_to_writeBack_INSTRUCTION;\n  wire                when_Pipeline_l124_9;\n  reg                 decode_to_execute_IS_RVC;\n  wire                when_Pipeline_l124_10;\n  reg                 execute_to_memory_IS_RVC;\n  wire                when_Pipeline_l124_11;\n  reg        [31:0]   decode_to_execute_FORMAL_INSTRUCTION;\n  wire                when_Pipeline_l124_12;\n  reg        [31:0]   execute_to_memory_FORMAL_INSTRUCTION;\n  wire                when_Pipeline_l124_13;\n  reg        [31:0]   memory_to_writeBack_FORMAL_INSTRUCTION;\n  wire                when_Pipeline_l124_14;\n  reg        [31:0]   decode_to_execute_FORMAL_PC_NEXT;\n  wire                when_Pipeline_l124_15;\n  reg        [31:0]   execute_to_memory_FORMAL_PC_NEXT;\n  wire                when_Pipeline_l124_16;\n  reg        [31:0]   memory_to_writeBack_FORMAL_PC_NEXT;\n  wire                when_Pipeline_l124_17;\n  reg                 decode_to_execute_PREDICTION_CONTEXT_hazard;\n  reg                 decode_to_execute_PREDICTION_CONTEXT_hit;\n  reg        [19:0]   decode_to_execute_PREDICTION_CONTEXT_line_source;\n  reg        [1:0]    decode_to_execute_PREDICTION_CONTEXT_line_branchWish;\n  reg                 decode_to_execute_PREDICTION_CONTEXT_line_last2Bytes;\n  reg        [31:0]   decode_to_execute_PREDICTION_CONTEXT_line_target;\n  wire                when_Pipeline_l124_18;\n  reg                 execute_to_memory_PREDICTION_CONTEXT_hazard;\n  reg                 execute_to_memory_PREDICTION_CONTEXT_hit;\n  reg        [19:0]   execute_to_memory_PREDICTION_CONTEXT_line_source;\n  reg        [1:0]    execute_to_memory_PREDICTION_CONTEXT_line_branchWish;\n  reg                 execute_to_memory_PREDICTION_CONTEXT_line_last2Bytes;\n  reg        [31:0]   execute_to_memory_PREDICTION_CONTEXT_line_target;\n  wire                when_Pipeline_l124_19;\n  reg                 decode_to_execute_SRC_USE_SUB_LESS;\n  wire                when_Pipeline_l124_20;\n  reg                 decode_to_execute_MEMORY_ENABLE;\n  wire                when_Pipeline_l124_21;\n  reg                 execute_to_memory_MEMORY_ENABLE;\n  wire                when_Pipeline_l124_22;\n  reg                 memory_to_writeBack_MEMORY_ENABLE;\n  wire                when_Pipeline_l124_23;\n  reg                 decode_to_execute_RS1_USE;\n  wire                when_Pipeline_l124_24;\n  reg                 execute_to_memory_RS1_USE;\n  wire                when_Pipeline_l124_25;\n  reg                 memory_to_writeBack_RS1_USE;\n  wire                when_Pipeline_l124_26;\n  reg        [1:0]    decode_to_execute_ALU_CTRL;\n  wire                when_Pipeline_l124_27;\n  reg                 decode_to_execute_REGFILE_WRITE_VALID;\n  wire                when_Pipeline_l124_28;\n  reg                 execute_to_memory_REGFILE_WRITE_VALID;\n  wire                when_Pipeline_l124_29;\n  reg                 memory_to_writeBack_REGFILE_WRITE_VALID;\n  wire                when_Pipeline_l124_30;\n  reg                 decode_to_execute_BYPASSABLE_EXECUTE_STAGE;\n  wire                when_Pipeline_l124_31;\n  reg                 decode_to_execute_BYPASSABLE_MEMORY_STAGE;\n  wire                when_Pipeline_l124_32;\n  reg                 execute_to_memory_BYPASSABLE_MEMORY_STAGE;\n  wire                when_Pipeline_l124_33;\n  reg                 decode_to_execute_MEMORY_STORE;\n  wire                when_Pipeline_l124_34;\n  reg                 execute_to_memory_MEMORY_STORE;\n  wire                when_Pipeline_l124_35;\n  reg                 decode_to_execute_RS2_USE;\n  wire                when_Pipeline_l124_36;\n  reg                 execute_to_memory_RS2_USE;\n  wire                when_Pipeline_l124_37;\n  reg                 memory_to_writeBack_RS2_USE;\n  wire                when_Pipeline_l124_38;\n  reg                 decode_to_execute_SRC_LESS_UNSIGNED;\n  wire                when_Pipeline_l124_39;\n  reg        [1:0]    decode_to_execute_ALU_BITWISE_CTRL;\n  wire                when_Pipeline_l124_40;\n  reg        [1:0]    decode_to_execute_SHIFT_CTRL;\n  wire                when_Pipeline_l124_41;\n  reg        [1:0]    execute_to_memory_SHIFT_CTRL;\n  wire                when_Pipeline_l124_42;\n  reg        [1:0]    decode_to_execute_BRANCH_CTRL;\n  wire                when_Pipeline_l124_43;\n  reg        [31:0]   decode_to_execute_RS1;\n  wire                when_Pipeline_l124_44;\n  reg        [31:0]   execute_to_memory_RS1;\n  wire                when_Pipeline_l124_45;\n  reg        [31:0]   memory_to_writeBack_RS1;\n  wire                when_Pipeline_l124_46;\n  reg        [31:0]   decode_to_execute_RS2;\n  wire                when_Pipeline_l124_47;\n  reg        [31:0]   execute_to_memory_RS2;\n  wire                when_Pipeline_l124_48;\n  reg        [31:0]   memory_to_writeBack_RS2;\n  wire                when_Pipeline_l124_49;\n  reg                 decode_to_execute_SRC2_FORCE_ZERO;\n  wire                when_Pipeline_l124_50;\n  reg        [31:0]   decode_to_execute_SRC1;\n  wire                when_Pipeline_l124_51;\n  reg        [31:0]   decode_to_execute_SRC2;\n  wire                when_Pipeline_l124_52;\n  reg                 execute_to_memory_ALIGNEMENT_FAULT;\n  wire                when_Pipeline_l124_53;\n  reg        [1:0]    execute_to_memory_MEMORY_ADDRESS_LOW;\n  wire                when_Pipeline_l124_54;\n  reg        [1:0]    memory_to_writeBack_MEMORY_ADDRESS_LOW;\n  wire                when_Pipeline_l124_55;\n  reg        [31:0]   execute_to_memory_FORMAL_MEM_ADDR;\n  wire                when_Pipeline_l124_56;\n  reg        [31:0]   memory_to_writeBack_FORMAL_MEM_ADDR;\n  wire                when_Pipeline_l124_57;\n  reg        [3:0]    execute_to_memory_FORMAL_MEM_WMASK;\n  wire                when_Pipeline_l124_58;\n  reg        [3:0]    memory_to_writeBack_FORMAL_MEM_WMASK;\n  wire                when_Pipeline_l124_59;\n  reg        [3:0]    execute_to_memory_FORMAL_MEM_RMASK;\n  wire                when_Pipeline_l124_60;\n  reg        [3:0]    memory_to_writeBack_FORMAL_MEM_RMASK;\n  wire                when_Pipeline_l124_61;\n  reg        [31:0]   execute_to_memory_FORMAL_MEM_WDATA;\n  wire                when_Pipeline_l124_62;\n  reg        [31:0]   memory_to_writeBack_FORMAL_MEM_WDATA;\n  wire                when_Pipeline_l124_63;\n  reg        [31:0]   execute_to_memory_REGFILE_WRITE_DATA;\n  wire                when_Pipeline_l124_64;\n  reg        [31:0]   memory_to_writeBack_REGFILE_WRITE_DATA;\n  wire                when_Pipeline_l124_65;\n  reg        [31:0]   execute_to_memory_SHIFT_RIGHT;\n  wire                when_Pipeline_l124_66;\n  reg                 execute_to_memory_BRANCH_DO;\n  wire                when_Pipeline_l124_67;\n  reg        [31:0]   execute_to_memory_BRANCH_CALC;\n  wire                when_Pipeline_l124_68;\n  reg        [31:0]   execute_to_memory_NEXT_PC2;\n  wire                when_Pipeline_l124_69;\n  reg                 execute_to_memory_TARGET_MISSMATCH2;\n  wire                when_Pipeline_l124_70;\n  reg        [31:0]   memory_to_writeBack_MEMORY_READ_DATA;\n  wire                when_Pipeline_l151;\n  wire                when_Pipeline_l154;\n  wire                when_Pipeline_l151_1;\n  wire                when_Pipeline_l154_1;\n  wire                when_Pipeline_l151_2;\n  wire                when_Pipeline_l154_2;\n  `ifndef SYNTHESIS\n  reg [31:0] decode_BRANCH_CTRL_string;\n  reg [31:0] _zz_decode_BRANCH_CTRL_string;\n  reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;\n  reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;\n  reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;\n  reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;\n  reg [71:0] decode_SHIFT_CTRL_string;\n  reg [71:0] _zz_decode_SHIFT_CTRL_string;\n  reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;\n  reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;\n  reg [39:0] decode_ALU_BITWISE_CTRL_string;\n  reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;\n  reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;\n  reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;\n  reg [63:0] decode_ALU_CTRL_string;\n  reg [63:0] _zz_decode_ALU_CTRL_string;\n  reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;\n  reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;\n  reg [31:0] execute_BRANCH_CTRL_string;\n  reg [31:0] _zz_execute_BRANCH_CTRL_string;\n  reg [71:0] memory_SHIFT_CTRL_string;\n  reg [71:0] _zz_memory_SHIFT_CTRL_string;\n  reg [71:0] execute_SHIFT_CTRL_string;\n  reg [71:0] _zz_execute_SHIFT_CTRL_string;\n  reg [23:0] decode_SRC2_CTRL_string;\n  reg [23:0] _zz_decode_SRC2_CTRL_string;\n  reg [95:0] decode_SRC1_CTRL_string;\n  reg [95:0] _zz_decode_SRC1_CTRL_string;\n  reg [63:0] execute_ALU_CTRL_string;\n  reg [63:0] _zz_execute_ALU_CTRL_string;\n  reg [39:0] execute_ALU_BITWISE_CTRL_string;\n  reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;\n  reg [31:0] _zz_decode_BRANCH_CTRL_1_string;\n  reg [71:0] _zz_decode_SHIFT_CTRL_1_string;\n  reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;\n  reg [23:0] _zz_decode_SRC2_CTRL_1_string;\n  reg [63:0] _zz_decode_ALU_CTRL_1_string;\n  reg [95:0] _zz_decode_SRC1_CTRL_1_string;\n  reg [95:0] _zz_decode_SRC1_CTRL_2_string;\n  reg [63:0] _zz_decode_ALU_CTRL_2_string;\n  reg [23:0] _zz_decode_SRC2_CTRL_2_string;\n  reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;\n  reg [71:0] _zz_decode_SHIFT_CTRL_2_string;\n  reg [31:0] _zz_decode_BRANCH_CTRL_7_string;\n  reg [63:0] decode_to_execute_ALU_CTRL_string;\n  reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;\n  reg [71:0] decode_to_execute_SHIFT_CTRL_string;\n  reg [71:0] execute_to_memory_SHIFT_CTRL_string;\n  reg [31:0] decode_to_execute_BRANCH_CTRL_string;\n  `endif\n\n  reg [54:0] IBusSimplePlugin_predictor_history [0:1023];\n  reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;\n\n  assign _zz_execute_NEXT_PC2_1 = (execute_IS_RVC ? 3'b010 : 3'b100);\n  assign _zz_execute_NEXT_PC2 = {29'd0, _zz_execute_NEXT_PC2_1};\n  assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);\n  assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];\n  assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};\n  assign _zz_IBusSimplePlugin_fetchPc_pc_1 = {IBusSimplePlugin_fetchPc_inc,2'b00};\n  assign _zz_IBusSimplePlugin_fetchPc_pc = {29'd0, _zz_IBusSimplePlugin_fetchPc_pc_1};\n  assign _zz_IBusSimplePlugin_decodePc_pcPlus_1 = (decode_IS_RVC ? 3'b010 : 3'b100);\n  assign _zz_IBusSimplePlugin_decodePc_pcPlus = {29'd0, _zz_IBusSimplePlugin_decodePc_pcPlus_1};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_27 = {{_zz_IBusSimplePlugin_decompressor_decompressed_10,_zz_IBusSimplePlugin_decompressor_decompressed[6 : 2]},12'h0};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_34 = {{{4'b0000,_zz_IBusSimplePlugin_decompressor_decompressed[8 : 7]},_zz_IBusSimplePlugin_decompressor_decompressed[12 : 9]},2'b00};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_35 = {{{4'b0000,_zz_IBusSimplePlugin_decompressor_decompressed[8 : 7]},_zz_IBusSimplePlugin_decompressor_decompressed[12 : 9]},2'b00};\n  assign _zz__zz_decode_FORMAL_PC_NEXT_1 = (decode_IS_RVC ? 3'b010 : 3'b100);\n  assign _zz__zz_decode_FORMAL_PC_NEXT = {29'd0, _zz__zz_decode_FORMAL_PC_NEXT_1};\n  assign _zz__zz_IBusSimplePlugin_predictor_buffer_line_source_1 = _zz_IBusSimplePlugin_predictor_buffer_line_source[9:0];\n  assign _zz_IBusSimplePlugin_predictor_buffer_hazard_1 = (IBusSimplePlugin_iBusRsp_stages_1_input_payload >>> 2);\n  assign _zz_IBusSimplePlugin_predictor_buffer_hazard = _zz_IBusSimplePlugin_predictor_buffer_hazard_1[9:0];\n  assign _zz_IBusSimplePlugin_predictor_hit = (IBusSimplePlugin_iBusRsp_stages_1_input_payload >>> 12);\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = (memory_PREDICTION_CONTEXT_line_branchWish + _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_1);\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_2 = (memory_PREDICTION_CONTEXT_line_branchWish == 2'b10);\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_1 = {1'd0, _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_2};\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_4 = (memory_PREDICTION_CONTEXT_line_branchWish == 2'b01);\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_3 = {1'd0, _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_4};\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_5 = (memory_PREDICTION_CONTEXT_line_branchWish - _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_6);\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_7 = memory_PREDICTION_CONTEXT_line_branchWish[1];\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_6 = {1'd0, _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_7};\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_9 = (! memory_PREDICTION_CONTEXT_line_branchWish[1]);\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_8 = {1'd0, _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_9};\n  assign _zz_IBusSimplePlugin_predictor_historyWrite_payload_address = (IBusSimplePlugin_iBusRsp_stages_1_input_payload >>> 2);\n  assign _zz_IBusSimplePlugin_pending_next = (IBusSimplePlugin_pending_value + _zz_IBusSimplePlugin_pending_next_1);\n  assign _zz_IBusSimplePlugin_pending_next_2 = IBusSimplePlugin_pending_inc;\n  assign _zz_IBusSimplePlugin_pending_next_1 = {2'd0, _zz_IBusSimplePlugin_pending_next_2};\n  assign _zz_IBusSimplePlugin_pending_next_4 = IBusSimplePlugin_pending_dec;\n  assign _zz_IBusSimplePlugin_pending_next_3 = {2'd0, _zz_IBusSimplePlugin_pending_next_4};\n  assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000));\n  assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1};\n  assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3 = IBusSimplePlugin_pending_dec;\n  assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2 = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3};\n  assign _zz_DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 3'b110 : 3'b100);\n  assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;\n  assign _zz__zz_decode_SRC1_1 = (decode_IS_RVC ? 3'b010 : 3'b100);\n  assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15];\n  assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]};\n  assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));\n  assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));\n  assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;\n  assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);\n  assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);\n  assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;\n  assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;\n  assign _zz__zz_execute_BRANCH_SRC22 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};\n  assign _zz__zz_execute_BRANCH_SRC22_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};\n  assign _zz_IBusSimplePlugin_predictor_history_port = {IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_target,{IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_last2Bytes,{IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_branchWish,IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_source}}};\n  assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;\n  assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;\n  assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000407f;\n  assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f);\n  assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002013;\n  assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023);\n  assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003);\n  assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000505f) == 32'h00000003),{((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h0000000f),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};\n  assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000607f;\n  assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'hfe00007f);\n  assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000033;\n  assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013);\n  assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013);\n  assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033),((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033)};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_28 = (_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10] == 2'b01);\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_29 = ((_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10] == 2'b11) && (_zz_IBusSimplePlugin_decompressor_decompressed[6 : 5] == 2'b00));\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_30 = 7'h0;\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_31 = _zz_IBusSimplePlugin_decompressor_decompressed[6 : 2];\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_32 = _zz_IBusSimplePlugin_decompressor_decompressed[12];\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_33 = _zz_IBusSimplePlugin_decompressor_decompressed[11 : 7];\n  assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c);\n  assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004;\n  assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000048);\n  assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040;\n  assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h00007014) == 32'h00005010);\n  assign _zz__zz_decode_BRANCH_CTRL_2_5 = {((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_6) == 32'h40001010),((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_7) == 32'h00001010)};\n  assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_9) == 32'h00000024));\n  assign _zz__zz_decode_BRANCH_CTRL_2_10 = (|(_zz__zz_decode_BRANCH_CTRL_2_11 == _zz__zz_decode_BRANCH_CTRL_2_12));\n  assign _zz__zz_decode_BRANCH_CTRL_2_13 = {(|_zz__zz_decode_BRANCH_CTRL_2_14),{(|_zz__zz_decode_BRANCH_CTRL_2_15),{_zz__zz_decode_BRANCH_CTRL_2_18,{_zz__zz_decode_BRANCH_CTRL_2_20,_zz__zz_decode_BRANCH_CTRL_2_22}}}};\n  assign _zz__zz_decode_BRANCH_CTRL_2_6 = 32'h40003014;\n  assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h00007014;\n  assign _zz__zz_decode_BRANCH_CTRL_2_9 = 32'h00000064;\n  assign _zz__zz_decode_BRANCH_CTRL_2_11 = (decode_INSTRUCTION & 32'h00001000);\n  assign _zz__zz_decode_BRANCH_CTRL_2_12 = 32'h00001000;\n  assign _zz__zz_decode_BRANCH_CTRL_2_14 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000);\n  assign _zz__zz_decode_BRANCH_CTRL_2_15 = {((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_16) == 32'h00002000),((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_17) == 32'h00001000)};\n  assign _zz__zz_decode_BRANCH_CTRL_2_18 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_19) == 32'h00000020));\n  assign _zz__zz_decode_BRANCH_CTRL_2_20 = (|{_zz__zz_decode_BRANCH_CTRL_2_21,_zz_decode_BRANCH_CTRL_3});\n  assign _zz__zz_decode_BRANCH_CTRL_2_22 = {(|_zz__zz_decode_BRANCH_CTRL_2_23),{(|_zz__zz_decode_BRANCH_CTRL_2_24),{_zz__zz_decode_BRANCH_CTRL_2_25,{_zz__zz_decode_BRANCH_CTRL_2_28,_zz__zz_decode_BRANCH_CTRL_2_35}}}};\n  assign _zz__zz_decode_BRANCH_CTRL_2_16 = 32'h00002010;\n  assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h00005000;\n  assign _zz__zz_decode_BRANCH_CTRL_2_19 = 32'h00000024;\n  assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & 32'h00000040) == 32'h00000040);\n  assign _zz__zz_decode_BRANCH_CTRL_2_23 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020);\n  assign _zz__zz_decode_BRANCH_CTRL_2_24 = _zz_decode_BRANCH_CTRL_6;\n  assign _zz__zz_decode_BRANCH_CTRL_2_25 = (|{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}});\n  assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|{_zz_decode_BRANCH_CTRL_6,{_zz__zz_decode_BRANCH_CTRL_2_29,_zz__zz_decode_BRANCH_CTRL_2_30}});\n  assign _zz__zz_decode_BRANCH_CTRL_2_35 = {(|{_zz__zz_decode_BRANCH_CTRL_2_36,_zz__zz_decode_BRANCH_CTRL_2_37}),{(|_zz__zz_decode_BRANCH_CTRL_2_39),{_zz__zz_decode_BRANCH_CTRL_2_42,{_zz__zz_decode_BRANCH_CTRL_2_45,_zz__zz_decode_BRANCH_CTRL_2_47}}}};\n  assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002010);\n  assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h00001010) == 32'h00000010);\n  assign _zz__zz_decode_BRANCH_CTRL_2_29 = _zz_decode_BRANCH_CTRL_5;\n  assign _zz__zz_decode_BRANCH_CTRL_2_30 = {(_zz__zz_decode_BRANCH_CTRL_2_31 == _zz__zz_decode_BRANCH_CTRL_2_32),(_zz__zz_decode_BRANCH_CTRL_2_33 == _zz__zz_decode_BRANCH_CTRL_2_34)};\n  assign _zz__zz_decode_BRANCH_CTRL_2_36 = _zz_decode_BRANCH_CTRL_4;\n  assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_38) == 32'h00000020);\n  assign _zz__zz_decode_BRANCH_CTRL_2_39 = {_zz_decode_BRANCH_CTRL_4,(_zz__zz_decode_BRANCH_CTRL_2_40 == _zz__zz_decode_BRANCH_CTRL_2_41)};\n  assign _zz__zz_decode_BRANCH_CTRL_2_42 = (|(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44));\n  assign _zz__zz_decode_BRANCH_CTRL_2_45 = (|_zz__zz_decode_BRANCH_CTRL_2_46);\n  assign _zz__zz_decode_BRANCH_CTRL_2_47 = {(|_zz__zz_decode_BRANCH_CTRL_2_48),{_zz__zz_decode_BRANCH_CTRL_2_50,{_zz__zz_decode_BRANCH_CTRL_2_52,_zz__zz_decode_BRANCH_CTRL_2_56}}};\n  assign _zz__zz_decode_BRANCH_CTRL_2_31 = (decode_INSTRUCTION & 32'h0000000c);\n  assign _zz__zz_decode_BRANCH_CTRL_2_32 = 32'h00000004;\n  assign _zz__zz_decode_BRANCH_CTRL_2_33 = (decode_INSTRUCTION & 32'h00000028);\n  assign _zz__zz_decode_BRANCH_CTRL_2_34 = 32'h0;\n  assign _zz__zz_decode_BRANCH_CTRL_2_38 = 32'h00000070;\n  assign _zz__zz_decode_BRANCH_CTRL_2_40 = (decode_INSTRUCTION & 32'h00000020);\n  assign _zz__zz_decode_BRANCH_CTRL_2_41 = 32'h0;\n  assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00004014);\n  assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00004010;\n  assign _zz__zz_decode_BRANCH_CTRL_2_46 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010);\n  assign _zz__zz_decode_BRANCH_CTRL_2_48 = {((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_49) == 32'h0),_zz_decode_BRANCH_CTRL_3};\n  assign _zz__zz_decode_BRANCH_CTRL_2_50 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_51) == 32'h0));\n  assign _zz__zz_decode_BRANCH_CTRL_2_52 = (|{_zz__zz_decode_BRANCH_CTRL_2_53,{_zz__zz_decode_BRANCH_CTRL_2_54,_zz__zz_decode_BRANCH_CTRL_2_55}});\n  assign _zz__zz_decode_BRANCH_CTRL_2_56 = {(|_zz__zz_decode_BRANCH_CTRL_2_57),(|_zz__zz_decode_BRANCH_CTRL_2_58)};\n  assign _zz__zz_decode_BRANCH_CTRL_2_49 = 32'h00000004;\n  assign _zz__zz_decode_BRANCH_CTRL_2_51 = 32'h00000058;\n  assign _zz__zz_decode_BRANCH_CTRL_2_53 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);\n  assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010);\n  assign _zz__zz_decode_BRANCH_CTRL_2_55 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030);\n  assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004);\n  assign _zz__zz_decode_BRANCH_CTRL_2_58 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004);\n  always @(posedge clk) begin\n    if(_zz_2) begin\n      IBusSimplePlugin_predictor_history[IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_address] <= _zz_IBusSimplePlugin_predictor_history_port;\n    end\n  end\n\n  always @(posedge clk) begin\n    if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin\n      _zz_IBusSimplePlugin_predictor_history_port1 <= IBusSimplePlugin_predictor_history[_zz__zz_IBusSimplePlugin_predictor_buffer_line_source_1];\n    end\n  end\n\n  always @(posedge clk) begin\n    if(_zz_decode_RegFilePlugin_rs1Data) begin\n      _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];\n    end\n  end\n\n  always @(posedge clk) begin\n    if(_zz_decode_RegFilePlugin_rs2Data) begin\n      _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];\n    end\n  end\n\n  always @(posedge clk) begin\n    if(_zz_1) begin\n      RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;\n    end\n  end\n\n  StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c (\n    .io_push_valid            (iBus_rsp_toStream_valid                                         ), //i\n    .io_push_ready            (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready              ), //o\n    .io_push_payload_error    (iBus_rsp_toStream_payload_error                                 ), //i\n    .io_push_payload_inst     (iBus_rsp_toStream_payload_inst[31:0]                            ), //i\n    .io_pop_valid             (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid               ), //o\n    .io_pop_ready             (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready               ), //i\n    .io_pop_payload_error     (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error       ), //o\n    .io_pop_payload_inst      (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0]  ), //o\n    .io_flush                 (1'b0                                                            ), //i\n    .io_occupancy             (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy               ), //o\n    .clk                      (clk                                                             ), //i\n    .reset                    (reset                                                           )  //i\n  );\n  `ifndef SYNTHESIS\n  always @(*) begin\n    case(decode_BRANCH_CTRL)\n      BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = \"INC \";\n      BranchCtrlEnum_B : decode_BRANCH_CTRL_string = \"B   \";\n      BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = \"JAL \";\n      BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = \"JALR\";\n      default : decode_BRANCH_CTRL_string = \"????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_BRANCH_CTRL)\n      BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = \"INC \";\n      BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = \"B   \";\n      BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = \"JAL \";\n      BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = \"JALR\";\n      default : _zz_decode_BRANCH_CTRL_string = \"????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_to_execute_BRANCH_CTRL)\n      BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = \"INC \";\n      BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = \"B   \";\n      BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = \"JAL \";\n      BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = \"JALR\";\n      default : _zz_decode_to_execute_BRANCH_CTRL_string = \"????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_to_execute_BRANCH_CTRL_1)\n      BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = \"INC \";\n      BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = \"B   \";\n      BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = \"JAL \";\n      BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = \"JALR\";\n      default : _zz_decode_to_execute_BRANCH_CTRL_1_string = \"????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_execute_to_memory_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = \"SRA_1    \";\n      default : _zz_execute_to_memory_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_execute_to_memory_SHIFT_CTRL_1)\n      ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = \"SRA_1    \";\n      default : _zz_execute_to_memory_SHIFT_CTRL_1_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(decode_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = \"SRA_1    \";\n      default : decode_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = \"SRA_1    \";\n      default : _zz_decode_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_to_execute_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = \"SRA_1    \";\n      default : _zz_decode_to_execute_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_to_execute_SHIFT_CTRL_1)\n      ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = \"SRA_1    \";\n      default : _zz_decode_to_execute_SHIFT_CTRL_1_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(decode_ALU_BITWISE_CTRL)\n      AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = \"XOR_1\";\n      AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = \"OR_1 \";\n      AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = \"AND_1\";\n      default : decode_ALU_BITWISE_CTRL_string = \"?????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_ALU_BITWISE_CTRL)\n      AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = \"XOR_1\";\n      AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = \"OR_1 \";\n      AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = \"AND_1\";\n      default : _zz_decode_ALU_BITWISE_CTRL_string = \"?????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_to_execute_ALU_BITWISE_CTRL)\n      AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = \"XOR_1\";\n      AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = \"OR_1 \";\n      AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = \"AND_1\";\n      default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = \"?????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)\n      AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = \"XOR_1\";\n      AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = \"OR_1 \";\n      AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = \"AND_1\";\n      default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = \"?????\";\n    endcase\n  end\n  always @(*) begin\n    case(decode_ALU_CTRL)\n      AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = \"ADD_SUB \";\n      AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = \"SLT_SLTU\";\n      AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = \"BITWISE \";\n      default : decode_ALU_CTRL_string = \"????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_ALU_CTRL)\n      AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = \"ADD_SUB \";\n      AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = \"SLT_SLTU\";\n      AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = \"BITWISE \";\n      default : _zz_decode_ALU_CTRL_string = \"????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_to_execute_ALU_CTRL)\n      AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = \"ADD_SUB \";\n      AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = \"SLT_SLTU\";\n      AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = \"BITWISE \";\n      default : _zz_decode_to_execute_ALU_CTRL_string = \"????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_to_execute_ALU_CTRL_1)\n      AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = \"ADD_SUB \";\n      AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = \"SLT_SLTU\";\n      AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = \"BITWISE \";\n      default : _zz_decode_to_execute_ALU_CTRL_1_string = \"????????\";\n    endcase\n  end\n  always @(*) begin\n    case(execute_BRANCH_CTRL)\n      BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = \"INC \";\n      BranchCtrlEnum_B : execute_BRANCH_CTRL_string = \"B   \";\n      BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = \"JAL \";\n      BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = \"JALR\";\n      default : execute_BRANCH_CTRL_string = \"????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_execute_BRANCH_CTRL)\n      BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = \"INC \";\n      BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = \"B   \";\n      BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = \"JAL \";\n      BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = \"JALR\";\n      default : _zz_execute_BRANCH_CTRL_string = \"????\";\n    endcase\n  end\n  always @(*) begin\n    case(memory_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = \"SRA_1    \";\n      default : memory_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_memory_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = \"SRA_1    \";\n      default : _zz_memory_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(execute_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = \"SRA_1    \";\n      default : execute_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_execute_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = \"SRA_1    \";\n      default : _zz_execute_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(decode_SRC2_CTRL)\n      Src2CtrlEnum_RS : decode_SRC2_CTRL_string = \"RS \";\n      Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = \"IMI\";\n      Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = \"IMS\";\n      Src2CtrlEnum_PC : decode_SRC2_CTRL_string = \"PC \";\n      default : decode_SRC2_CTRL_string = \"???\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_SRC2_CTRL)\n      Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = \"RS \";\n      Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = \"IMI\";\n      Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = \"IMS\";\n      Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = \"PC \";\n      default : _zz_decode_SRC2_CTRL_string = \"???\";\n    endcase\n  end\n  always @(*) begin\n    case(decode_SRC1_CTRL)\n      Src1CtrlEnum_RS : decode_SRC1_CTRL_string = \"RS          \";\n      Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = \"IMU         \";\n      Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = \"PC_INCREMENT\";\n      Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = \"URS1        \";\n      default : decode_SRC1_CTRL_string = \"????????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_SRC1_CTRL)\n      Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = \"RS          \";\n      Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = \"IMU         \";\n      Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = \"PC_INCREMENT\";\n      Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = \"URS1        \";\n      default : _zz_decode_SRC1_CTRL_string = \"????????????\";\n    endcase\n  end\n  always @(*) begin\n    case(execute_ALU_CTRL)\n      AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = \"ADD_SUB \";\n      AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = \"SLT_SLTU\";\n      AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = \"BITWISE \";\n      default : execute_ALU_CTRL_string = \"????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_execute_ALU_CTRL)\n      AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = \"ADD_SUB \";\n      AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = \"SLT_SLTU\";\n      AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = \"BITWISE \";\n      default : _zz_execute_ALU_CTRL_string = \"????????\";\n    endcase\n  end\n  always @(*) begin\n    case(execute_ALU_BITWISE_CTRL)\n      AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = \"XOR_1\";\n      AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = \"OR_1 \";\n      AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = \"AND_1\";\n      default : execute_ALU_BITWISE_CTRL_string = \"?????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_execute_ALU_BITWISE_CTRL)\n      AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = \"XOR_1\";\n      AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = \"OR_1 \";\n      AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = \"AND_1\";\n      default : _zz_execute_ALU_BITWISE_CTRL_string = \"?????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_BRANCH_CTRL_1)\n      BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = \"INC \";\n      BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = \"B   \";\n      BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = \"JAL \";\n      BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = \"JALR\";\n      default : _zz_decode_BRANCH_CTRL_1_string = \"????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_SHIFT_CTRL_1)\n      ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = \"SRA_1    \";\n      default : _zz_decode_SHIFT_CTRL_1_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_ALU_BITWISE_CTRL_1)\n      AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = \"XOR_1\";\n      AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = \"OR_1 \";\n      AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = \"AND_1\";\n      default : _zz_decode_ALU_BITWISE_CTRL_1_string = \"?????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_SRC2_CTRL_1)\n      Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = \"RS \";\n      Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = \"IMI\";\n      Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = \"IMS\";\n      Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = \"PC \";\n      default : _zz_decode_SRC2_CTRL_1_string = \"???\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_ALU_CTRL_1)\n      AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = \"ADD_SUB \";\n      AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = \"SLT_SLTU\";\n      AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = \"BITWISE \";\n      default : _zz_decode_ALU_CTRL_1_string = \"????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_SRC1_CTRL_1)\n      Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = \"RS          \";\n      Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = \"IMU         \";\n      Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = \"PC_INCREMENT\";\n      Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = \"URS1        \";\n      default : _zz_decode_SRC1_CTRL_1_string = \"????????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_SRC1_CTRL_2)\n      Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = \"RS          \";\n      Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = \"IMU         \";\n      Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = \"PC_INCREMENT\";\n      Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = \"URS1        \";\n      default : _zz_decode_SRC1_CTRL_2_string = \"????????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_ALU_CTRL_2)\n      AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = \"ADD_SUB \";\n      AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = \"SLT_SLTU\";\n      AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = \"BITWISE \";\n      default : _zz_decode_ALU_CTRL_2_string = \"????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_SRC2_CTRL_2)\n      Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = \"RS \";\n      Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = \"IMI\";\n      Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = \"IMS\";\n      Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = \"PC \";\n      default : _zz_decode_SRC2_CTRL_2_string = \"???\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_ALU_BITWISE_CTRL_2)\n      AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = \"XOR_1\";\n      AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = \"OR_1 \";\n      AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = \"AND_1\";\n      default : _zz_decode_ALU_BITWISE_CTRL_2_string = \"?????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_SHIFT_CTRL_2)\n      ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = \"SRA_1    \";\n      default : _zz_decode_SHIFT_CTRL_2_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(_zz_decode_BRANCH_CTRL_7)\n      BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_7_string = \"INC \";\n      BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_7_string = \"B   \";\n      BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_7_string = \"JAL \";\n      BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_7_string = \"JALR\";\n      default : _zz_decode_BRANCH_CTRL_7_string = \"????\";\n    endcase\n  end\n  always @(*) begin\n    case(decode_to_execute_ALU_CTRL)\n      AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = \"ADD_SUB \";\n      AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = \"SLT_SLTU\";\n      AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = \"BITWISE \";\n      default : decode_to_execute_ALU_CTRL_string = \"????????\";\n    endcase\n  end\n  always @(*) begin\n    case(decode_to_execute_ALU_BITWISE_CTRL)\n      AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = \"XOR_1\";\n      AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = \"OR_1 \";\n      AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = \"AND_1\";\n      default : decode_to_execute_ALU_BITWISE_CTRL_string = \"?????\";\n    endcase\n  end\n  always @(*) begin\n    case(decode_to_execute_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = \"SRA_1    \";\n      default : decode_to_execute_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(execute_to_memory_SHIFT_CTRL)\n      ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = \"DISABLE_1\";\n      ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = \"SLL_1    \";\n      ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = \"SRL_1    \";\n      ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = \"SRA_1    \";\n      default : execute_to_memory_SHIFT_CTRL_string = \"?????????\";\n    endcase\n  end\n  always @(*) begin\n    case(decode_to_execute_BRANCH_CTRL)\n      BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = \"INC \";\n      BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = \"B   \";\n      BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = \"JAL \";\n      BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = \"JALR\";\n      default : decode_to_execute_BRANCH_CTRL_string = \"????\";\n    endcase\n  end\n  `endif\n\n  assign writeBack_FORMAL_MEM_RDATA = writeBack_MEMORY_READ_DATA;\n  assign memory_MEMORY_READ_DATA = dBus_rsp_data;\n  assign execute_TARGET_MISSMATCH2 = (decode_PC != execute_BRANCH_CALC);\n  assign execute_NEXT_PC2 = (execute_PC + _zz_execute_NEXT_PC2);\n  assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1;\n  assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;\n  assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;\n  assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;\n  assign writeBack_FORMAL_MEM_WDATA = memory_to_writeBack_FORMAL_MEM_WDATA;\n  assign memory_FORMAL_MEM_WDATA = execute_to_memory_FORMAL_MEM_WDATA;\n  assign execute_FORMAL_MEM_WDATA = dBus_cmd_payload_data;\n  assign writeBack_FORMAL_MEM_RMASK = memory_to_writeBack_FORMAL_MEM_RMASK;\n  assign memory_FORMAL_MEM_RMASK = execute_to_memory_FORMAL_MEM_RMASK;\n  assign execute_FORMAL_MEM_RMASK = ((dBus_cmd_valid && (! dBus_cmd_payload_wr)) ? execute_DBusSimplePlugin_formalMask : 4'b0000);\n  assign writeBack_FORMAL_MEM_WMASK = memory_to_writeBack_FORMAL_MEM_WMASK;\n  assign memory_FORMAL_MEM_WMASK = execute_to_memory_FORMAL_MEM_WMASK;\n  assign execute_FORMAL_MEM_WMASK = ((dBus_cmd_valid && dBus_cmd_payload_wr) ? execute_DBusSimplePlugin_formalMask : 4'b0000);\n  assign writeBack_FORMAL_MEM_ADDR = memory_to_writeBack_FORMAL_MEM_ADDR;\n  assign memory_FORMAL_MEM_ADDR = execute_to_memory_FORMAL_MEM_ADDR;\n  assign execute_FORMAL_MEM_ADDR = (dBus_cmd_payload_address & 32'hfffffffc);\n  assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;\n  assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0];\n  assign decode_SRC2 = _zz_decode_SRC2_6;\n  assign decode_SRC1 = _zz_decode_SRC1_1;\n  assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));\n  assign writeBack_RS2 = memory_to_writeBack_RS2;\n  assign memory_RS2 = execute_to_memory_RS2;\n  assign decode_RS2 = decode_RegFilePlugin_rs2Data;\n  assign writeBack_RS1 = memory_to_writeBack_RS1;\n  assign memory_RS1 = execute_to_memory_RS1;\n  assign decode_RS1 = decode_RegFilePlugin_rs1Data;\n  assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL;\n  assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;\n  assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;\n  assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;\n  assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;\n  assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;\n  assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;\n  assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[15];\n  assign writeBack_RS2_USE = memory_to_writeBack_RS2_USE;\n  assign memory_RS2_USE = execute_to_memory_RS2_USE;\n  assign execute_RS2_USE = decode_to_execute_RS2_USE;\n  assign decode_MEMORY_STORE = _zz_decode_BRANCH_CTRL_2[12];\n  assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;\n  assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[11];\n  assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[10];\n  assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;\n  assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;\n  assign writeBack_RS1_USE = memory_to_writeBack_RS1_USE;\n  assign memory_RS1_USE = execute_to_memory_RS1_USE;\n  assign execute_RS1_USE = decode_to_execute_RS1_USE;\n  assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[3];\n  assign execute_PREDICTION_CONTEXT_hazard = decode_to_execute_PREDICTION_CONTEXT_hazard;\n  assign execute_PREDICTION_CONTEXT_hit = decode_to_execute_PREDICTION_CONTEXT_hit;\n  assign execute_PREDICTION_CONTEXT_line_source = decode_to_execute_PREDICTION_CONTEXT_line_source;\n  assign execute_PREDICTION_CONTEXT_line_branchWish = decode_to_execute_PREDICTION_CONTEXT_line_branchWish;\n  assign execute_PREDICTION_CONTEXT_line_last2Bytes = decode_to_execute_PREDICTION_CONTEXT_line_last2Bytes;\n  assign execute_PREDICTION_CONTEXT_line_target = decode_to_execute_PREDICTION_CONTEXT_line_target;\n  assign decode_PREDICTION_CONTEXT_hazard = IBusSimplePlugin_predictor_injectorContext_hazard;\n  assign decode_PREDICTION_CONTEXT_hit = IBusSimplePlugin_predictor_injectorContext_hit;\n  assign decode_PREDICTION_CONTEXT_line_source = IBusSimplePlugin_predictor_injectorContext_line_source;\n  assign decode_PREDICTION_CONTEXT_line_branchWish = IBusSimplePlugin_predictor_injectorContext_line_branchWish;\n  assign decode_PREDICTION_CONTEXT_line_last2Bytes = IBusSimplePlugin_predictor_injectorContext_line_last2Bytes;\n  assign decode_PREDICTION_CONTEXT_line_target = IBusSimplePlugin_predictor_injectorContext_line_target;\n  assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;\n  assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;\n  assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;\n  assign decode_FORMAL_PC_NEXT = _zz_decode_FORMAL_PC_NEXT;\n  assign writeBack_FORMAL_INSTRUCTION = memory_to_writeBack_FORMAL_INSTRUCTION;\n  assign memory_FORMAL_INSTRUCTION = execute_to_memory_FORMAL_INSTRUCTION;\n  assign execute_FORMAL_INSTRUCTION = decode_to_execute_FORMAL_INSTRUCTION;\n  assign decode_FORMAL_INSTRUCTION = IBusSimplePlugin_injector_formal_rawInDecode;\n  assign writeBack_FORMAL_HALT = memory_to_writeBack_FORMAL_HALT;\n  assign memory_FORMAL_HALT = execute_to_memory_FORMAL_HALT;\n  assign execute_FORMAL_HALT = decode_to_execute_FORMAL_HALT;\n  assign decode_FORMAL_HALT = 1'b0;\n  assign memory_NEXT_PC2 = execute_to_memory_NEXT_PC2;\n  assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC;\n  assign memory_TARGET_MISSMATCH2 = execute_to_memory_TARGET_MISSMATCH2;\n  assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;\n  assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};\n  assign execute_IS_RVC = decode_to_execute_IS_RVC;\n  assign execute_BRANCH_SRC22 = _zz_execute_BRANCH_SRC22_6;\n  assign execute_PC = decode_to_execute_PC;\n  assign execute_RS1 = decode_to_execute_RS1;\n  assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;\n  assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[14];\n  assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[4];\n  assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;\n  assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;\n  assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;\n  assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;\n  assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;\n  assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;\n  assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;\n  always @(*) begin\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA = memory_REGFILE_WRITE_DATA;\n    if(memory_arbitration_isValid) begin\n      case(memory_SHIFT_CTRL)\n        ShiftCtrlEnum_SLL_1 : begin\n          _zz_memory_to_writeBack_REGFILE_WRITE_DATA = _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1;\n        end\n        ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin\n          _zz_memory_to_writeBack_REGFILE_WRITE_DATA = memory_SHIFT_RIGHT;\n        end\n        default : begin\n        end\n      endcase\n    end\n  end\n\n  assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;\n  assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;\n  assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;\n  assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;\n  assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;\n  assign _zz_decode_SRC2 = decode_PC;\n  assign _zz_decode_SRC2_1 = decode_RS2;\n  assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;\n  assign _zz_decode_SRC1 = decode_RS1;\n  assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;\n  assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[2];\n  assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[18];\n  assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;\n  assign execute_SRC_LESS = execute_SrcPlugin_less;\n  assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;\n  assign execute_SRC2 = decode_to_execute_SRC2;\n  assign execute_SRC1 = decode_to_execute_SRC1;\n  assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;\n  always @(*) begin\n    _zz_1 = 1'b0;\n    if(lastStageRegFileWrite_valid) begin\n      _zz_1 = 1'b1;\n    end\n  end\n\n  assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_decompressor_output_payload_rsp_inst);\n  always @(*) begin\n    decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[9];\n    if(when_RegFilePlugin_l63) begin\n      decode_REGFILE_WRITE_VALID = 1'b0;\n    end\n  end\n\n  assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00004063),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}});\n  assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;\n  assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;\n  assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA;\n  assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT;\n  assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;\n  assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE;\n  assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;\n  assign execute_SRC_ADD = execute_SrcPlugin_addSub;\n  assign execute_RS2 = decode_to_execute_RS2;\n  assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;\n  assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;\n  assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;\n  assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0)));\n  assign memory_IS_RVC = execute_to_memory_IS_RVC;\n  assign memory_PC = execute_to_memory_PC;\n  assign memory_PREDICTION_CONTEXT_hazard = execute_to_memory_PREDICTION_CONTEXT_hazard;\n  assign memory_PREDICTION_CONTEXT_hit = execute_to_memory_PREDICTION_CONTEXT_hit;\n  assign memory_PREDICTION_CONTEXT_line_source = execute_to_memory_PREDICTION_CONTEXT_line_source;\n  assign memory_PREDICTION_CONTEXT_line_branchWish = execute_to_memory_PREDICTION_CONTEXT_line_branchWish;\n  assign memory_PREDICTION_CONTEXT_line_last2Bytes = execute_to_memory_PREDICTION_CONTEXT_line_last2Bytes;\n  assign memory_PREDICTION_CONTEXT_line_target = execute_to_memory_PREDICTION_CONTEXT_line_target;\n  always @(*) begin\n    _zz_2 = 1'b0;\n    if(IBusSimplePlugin_predictor_historyWriteDelayPatched_valid) begin\n      _zz_2 = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT;\n    if(BranchPlugin_jumpInterface_valid) begin\n      _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;\n    end\n  end\n\n  assign decode_PC = IBusSimplePlugin_decodePc_pcReg;\n  assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;\n  assign decode_IS_RVC = IBusSimplePlugin_injector_decodeInput_payload_isRvc;\n  always @(*) begin\n    _zz_when_FormalPlugin_l114 = writeBack_FORMAL_HALT;\n    if(writeBack_arbitration_isFlushed) begin\n      _zz_when_FormalPlugin_l114 = 1'b0;\n    end\n    if(writeBack_arbitration_isFlushed) begin\n      _zz_when_FormalPlugin_l114 = 1'b0;\n    end\n  end\n\n  always @(*) begin\n    _zz_when_FormalPlugin_l114_1 = memory_FORMAL_HALT;\n    if(memory_arbitration_isFlushed) begin\n      _zz_when_FormalPlugin_l114_1 = 1'b0;\n    end\n    if(when_HaltOnExceptionPlugin_l34_1) begin\n      _zz_when_FormalPlugin_l114_1 = 1'b1;\n    end\n    if(memory_arbitration_isFlushed) begin\n      _zz_when_FormalPlugin_l114_1 = 1'b0;\n    end\n  end\n\n  always @(*) begin\n    _zz_when_FormalPlugin_l114_2 = execute_FORMAL_HALT;\n    if(execute_arbitration_isFlushed) begin\n      _zz_when_FormalPlugin_l114_2 = 1'b0;\n    end\n    if(execute_arbitration_isFlushed) begin\n      _zz_when_FormalPlugin_l114_2 = 1'b0;\n    end\n  end\n\n  always @(*) begin\n    _zz_when_FormalPlugin_l114_3 = decode_FORMAL_HALT;\n    if(when_HaltOnExceptionPlugin_l34) begin\n      _zz_when_FormalPlugin_l114_3 = 1'b1;\n    end\n    if(decode_arbitration_isFlushed) begin\n      _zz_when_FormalPlugin_l114_3 = 1'b0;\n    end\n    if(decode_arbitration_isFlushed) begin\n      _zz_when_FormalPlugin_l114_3 = 1'b0;\n    end\n  end\n\n  always @(*) begin\n    _zz_rvfi_rd_wdata = writeBack_REGFILE_WRITE_DATA;\n    if(when_DBusSimplePlugin_l558) begin\n      _zz_rvfi_rd_wdata = writeBack_DBusSimplePlugin_rspFormated;\n    end\n  end\n\n  assign _zz_rvfi_rd_addr = writeBack_REGFILE_WRITE_VALID;\n  assign _zz_rvfi_rs2_addr = writeBack_RS2_USE;\n  assign _zz_rvfi_rs1_addr = writeBack_INSTRUCTION;\n  assign _zz_rvfi_rs1_addr_1 = writeBack_RS1_USE;\n  assign writeBack_PC = memory_to_writeBack_PC;\n  assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;\n  always @(*) begin\n    decode_arbitration_haltItself = 1'b0;\n    if(when_HaltOnExceptionPlugin_l34) begin\n      decode_arbitration_haltItself = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    decode_arbitration_haltByOther = 1'b0;\n    if(when_HazardSimplePlugin_l113) begin\n      decode_arbitration_haltByOther = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    decode_arbitration_removeIt = 1'b0;\n    if(decode_arbitration_isFlushed) begin\n      decode_arbitration_removeIt = 1'b1;\n    end\n  end\n\n  assign decode_arbitration_flushIt = 1'b0;\n  assign decode_arbitration_flushNext = 1'b0;\n  always @(*) begin\n    execute_arbitration_haltItself = 1'b0;\n    if(when_DBusSimplePlugin_l428) begin\n      execute_arbitration_haltItself = 1'b1;\n    end\n  end\n\n  assign execute_arbitration_haltByOther = 1'b0;\n  always @(*) begin\n    execute_arbitration_removeIt = 1'b0;\n    if(execute_arbitration_isFlushed) begin\n      execute_arbitration_removeIt = 1'b1;\n    end\n  end\n\n  assign execute_arbitration_flushIt = 1'b0;\n  assign execute_arbitration_flushNext = 1'b0;\n  always @(*) begin\n    memory_arbitration_haltItself = 1'b0;\n    if(when_HaltOnExceptionPlugin_l34_1) begin\n      memory_arbitration_haltItself = 1'b1;\n    end\n    if(when_DBusSimplePlugin_l482) begin\n      memory_arbitration_haltItself = 1'b1;\n    end\n  end\n\n  assign memory_arbitration_haltByOther = 1'b0;\n  always @(*) begin\n    memory_arbitration_removeIt = 1'b0;\n    if(memory_arbitration_isFlushed) begin\n      memory_arbitration_removeIt = 1'b1;\n    end\n  end\n\n  assign memory_arbitration_flushIt = 1'b0;\n  always @(*) begin\n    memory_arbitration_flushNext = 1'b0;\n    if(BranchPlugin_jumpInterface_valid) begin\n      memory_arbitration_flushNext = 1'b1;\n    end\n  end\n\n  assign writeBack_arbitration_haltItself = 1'b0;\n  assign writeBack_arbitration_haltByOther = 1'b0;\n  always @(*) begin\n    writeBack_arbitration_removeIt = 1'b0;\n    if(writeBack_arbitration_isFlushed) begin\n      writeBack_arbitration_removeIt = 1'b1;\n    end\n  end\n\n  assign writeBack_arbitration_flushIt = 1'b0;\n  assign writeBack_arbitration_flushNext = 1'b0;\n  assign lastStageInstruction = writeBack_INSTRUCTION;\n  assign lastStagePc = writeBack_PC;\n  assign lastStageIsValid = writeBack_arbitration_isValid;\n  assign lastStageIsFiring = writeBack_arbitration_isFiring;\n  assign IBusSimplePlugin_fetcherHalt = 1'b0;\n  always @(*) begin\n    IBusSimplePlugin_incomingInstruction = 1'b0;\n    if(IBusSimplePlugin_iBusRsp_stages_1_input_valid) begin\n      IBusSimplePlugin_incomingInstruction = 1'b1;\n    end\n    if(IBusSimplePlugin_injector_decodeInput_valid) begin\n      IBusSimplePlugin_incomingInstruction = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    rvfi_valid = writeBack_arbitration_isFiring;\n    if(writeBack_FormalPlugin_haltRequest_delay_5) begin\n      rvfi_valid = 1'b1;\n    end\n    if(writeBack_FormalPlugin_haltFired) begin\n      rvfi_valid = 1'b0;\n    end\n  end\n\n  assign rvfi_order = writeBack_FormalPlugin_order;\n  assign rvfi_insn = writeBack_FORMAL_INSTRUCTION;\n  always @(*) begin\n    rvfi_trap = 1'b0;\n    if(writeBack_FormalPlugin_haltRequest_delay_5) begin\n      rvfi_trap = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    rvfi_halt = 1'b0;\n    if(writeBack_FormalPlugin_haltRequest_delay_5) begin\n      rvfi_halt = 1'b1;\n    end\n  end\n\n  assign rvfi_intr = 1'b0;\n  assign rvfi_mode = 2'd3;\n  assign rvfi_ixl = 2'd1;\n  assign rvfi_rs1_addr = (_zz_rvfi_rs1_addr_1 ? _zz_rvfi_rs1_addr[19 : 15] : 5'h0);\n  assign rvfi_rs2_addr = (_zz_rvfi_rs2_addr ? _zz_rvfi_rs1_addr[24 : 20] : 5'h0);\n  assign rvfi_rs1_rdata = (_zz_rvfi_rs1_addr_1 ? writeBack_RS1 : 32'h0);\n  assign rvfi_rs2_rdata = (_zz_rvfi_rs2_addr ? writeBack_RS2 : 32'h0);\n  assign rvfi_rd_addr = (_zz_rvfi_rd_addr ? _zz_rvfi_rs1_addr[11 : 7] : 5'h0);\n  assign rvfi_rd_wdata = (_zz_rvfi_rd_addr ? _zz_rvfi_rd_wdata : 32'h0);\n  assign rvfi_pc_rdata = writeBack_PC;\n  assign rvfi_pc_wdata = writeBack_FORMAL_PC_NEXT;\n  assign rvfi_mem_addr = writeBack_FORMAL_MEM_ADDR;\n  assign rvfi_mem_rmask = writeBack_FORMAL_MEM_RMASK;\n  assign rvfi_mem_wmask = writeBack_FORMAL_MEM_WMASK;\n  assign rvfi_mem_rdata = writeBack_FORMAL_MEM_RDATA;\n  assign rvfi_mem_wdata = writeBack_FORMAL_MEM_WDATA;\n  always @(*) begin\n    writeBack_FormalPlugin_haltRequest = 1'b0;\n    if(when_FormalPlugin_l114) begin\n      if(when_FormalPlugin_l115) begin\n        writeBack_FormalPlugin_haltRequest = 1'b1;\n      end\n    end\n    if(when_FormalPlugin_l114_1) begin\n      if(when_FormalPlugin_l115_1) begin\n        writeBack_FormalPlugin_haltRequest = 1'b1;\n      end\n    end\n    if(when_FormalPlugin_l114_2) begin\n      if(when_FormalPlugin_l115_2) begin\n        writeBack_FormalPlugin_haltRequest = 1'b1;\n      end\n    end\n    if(when_FormalPlugin_l114_3) begin\n      if(when_FormalPlugin_l115_3) begin\n        writeBack_FormalPlugin_haltRequest = 1'b1;\n      end\n    end\n  end\n\n  assign when_FormalPlugin_l114 = (decode_arbitration_isValid && _zz_when_FormalPlugin_l114_3);\n  assign when_FormalPlugin_l115 = (((1'b1 && (! execute_arbitration_isValid)) && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid));\n  assign when_FormalPlugin_l114_1 = (execute_arbitration_isValid && _zz_when_FormalPlugin_l114_2);\n  assign when_FormalPlugin_l115_1 = ((1'b1 && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid));\n  assign when_FormalPlugin_l114_2 = (memory_arbitration_isValid && _zz_when_FormalPlugin_l114_1);\n  assign when_FormalPlugin_l115_2 = (1'b1 && (! writeBack_arbitration_isValid));\n  assign when_FormalPlugin_l114_3 = (writeBack_arbitration_isValid && _zz_when_FormalPlugin_l114);\n  assign when_FormalPlugin_l115_3 = 1'b1;\n  assign when_FormalPlugin_l127 = (rvfi_valid && rvfi_halt);\n  assign when_HaltOnExceptionPlugin_l34 = (decodeExceptionPort_valid != 1'b0);\n  assign when_HaltOnExceptionPlugin_l34_1 = (DBusSimplePlugin_memoryExceptionPort_valid != 1'b0);\n  assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);\n  assign IBusSimplePlugin_jump_pcLoad_valid = (BranchPlugin_jumpInterface_valid != 1'b0);\n  assign IBusSimplePlugin_jump_pcLoad_payload = BranchPlugin_jumpInterface_payload;\n  always @(*) begin\n    IBusSimplePlugin_fetchPc_correction = 1'b0;\n    if(IBusSimplePlugin_fetchPc_predictionPcLoad_valid) begin\n      IBusSimplePlugin_fetchPc_correction = 1'b1;\n    end\n    if(IBusSimplePlugin_fetchPc_redo_valid) begin\n      IBusSimplePlugin_fetchPc_correction = 1'b1;\n    end\n    if(IBusSimplePlugin_jump_pcLoad_valid) begin\n      IBusSimplePlugin_fetchPc_correction = 1'b1;\n    end\n  end\n\n  assign IBusSimplePlugin_fetchPc_output_fire = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready);\n  assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg);\n  assign IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0;\n  assign when_Fetcher_l131 = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate);\n  assign IBusSimplePlugin_fetchPc_output_fire_1 = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready);\n  assign when_Fetcher_l131_1 = ((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready);\n  always @(*) begin\n    IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_IBusSimplePlugin_fetchPc_pc);\n    if(IBusSimplePlugin_fetchPc_inc) begin\n      IBusSimplePlugin_fetchPc_pc[1] = 1'b0;\n    end\n    if(IBusSimplePlugin_fetchPc_predictionPcLoad_valid) begin\n      IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_predictionPcLoad_payload;\n    end\n    if(IBusSimplePlugin_fetchPc_redo_valid) begin\n      IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload;\n    end\n    if(IBusSimplePlugin_jump_pcLoad_valid) begin\n      IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload;\n    end\n    IBusSimplePlugin_fetchPc_pc[0] = 1'b0;\n  end\n\n  always @(*) begin\n    IBusSimplePlugin_fetchPc_flushed = 1'b0;\n    if(IBusSimplePlugin_fetchPc_redo_valid) begin\n      IBusSimplePlugin_fetchPc_flushed = 1'b1;\n    end\n    if(IBusSimplePlugin_jump_pcLoad_valid) begin\n      IBusSimplePlugin_fetchPc_flushed = 1'b1;\n    end\n  end\n\n  assign when_Fetcher_l158 = (IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate));\n  assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted);\n  assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc;\n  always @(*) begin\n    IBusSimplePlugin_decodePc_flushed = 1'b0;\n    if(when_Fetcher_l192) begin\n      IBusSimplePlugin_decodePc_flushed = 1'b1;\n    end\n  end\n\n  assign IBusSimplePlugin_decodePc_pcPlus = (IBusSimplePlugin_decodePc_pcReg + _zz_IBusSimplePlugin_decodePc_pcPlus);\n  assign IBusSimplePlugin_decodePc_injectedDecode = 1'b0;\n  assign when_Fetcher_l180 = (decode_arbitration_isFiring && (! IBusSimplePlugin_decodePc_injectedDecode));\n  assign when_Fetcher_l192 = (IBusSimplePlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt));\n  always @(*) begin\n    IBusSimplePlugin_iBusRsp_redoFetch = 1'b0;\n    if(IBusSimplePlugin_predictor_compressor_unalignedWordIssue) begin\n      IBusSimplePlugin_iBusRsp_redoFetch = 1'b1;\n    end\n  end\n\n  assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid;\n  assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready;\n  assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload;\n  always @(*) begin\n    IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0;\n    if(when_IBusSimplePlugin_l305) begin\n      IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1;\n    end\n  end\n\n  assign _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready = (! IBusSimplePlugin_iBusRsp_stages_0_halt);\n  assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready);\n  assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready);\n  assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload;\n  assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0;\n  assign _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready = (! IBusSimplePlugin_iBusRsp_stages_1_halt);\n  assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready);\n  assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready);\n  assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload;\n  assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch;\n  always @(*) begin\n    IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload;\n    if(IBusSimplePlugin_decompressor_throw2BytesReg) begin\n      IBusSimplePlugin_fetchPc_redo_payload[1] = 1'b1;\n    end\n  end\n\n  assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch);\n  assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid)) || IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_ready);\n  assign IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid;\n  assign IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload;\n  assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid;\n  assign IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_ready = IBusSimplePlugin_iBusRsp_stages_1_input_ready;\n  assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload;\n  always @(*) begin\n    IBusSimplePlugin_iBusRsp_readyForError = 1'b1;\n    if(IBusSimplePlugin_injector_decodeInput_valid) begin\n      IBusSimplePlugin_iBusRsp_readyForError = 1'b0;\n    end\n  end\n\n  assign IBusSimplePlugin_decompressor_input_valid = (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_iBusRsp_redoFetch));\n  assign IBusSimplePlugin_decompressor_input_payload_pc = IBusSimplePlugin_iBusRsp_output_payload_pc;\n  assign IBusSimplePlugin_decompressor_input_payload_rsp_error = IBusSimplePlugin_iBusRsp_output_payload_rsp_error;\n  assign IBusSimplePlugin_decompressor_input_payload_rsp_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;\n  assign IBusSimplePlugin_decompressor_input_payload_isRvc = IBusSimplePlugin_iBusRsp_output_payload_isRvc;\n  assign IBusSimplePlugin_iBusRsp_output_ready = IBusSimplePlugin_decompressor_input_ready;\n  assign IBusSimplePlugin_decompressor_flushNext = 1'b0;\n  assign IBusSimplePlugin_decompressor_consumeCurrent = 1'b0;\n  assign IBusSimplePlugin_decompressor_isInputLowRvc = (IBusSimplePlugin_decompressor_input_payload_rsp_inst[1 : 0] != 2'b11);\n  assign IBusSimplePlugin_decompressor_isInputHighRvc = (IBusSimplePlugin_decompressor_input_payload_rsp_inst[17 : 16] != 2'b11);\n  assign IBusSimplePlugin_decompressor_throw2Bytes = (IBusSimplePlugin_decompressor_throw2BytesReg || IBusSimplePlugin_decompressor_input_payload_pc[1]);\n  assign IBusSimplePlugin_decompressor_unaligned = (IBusSimplePlugin_decompressor_throw2Bytes || IBusSimplePlugin_decompressor_bufferValid);\n  assign IBusSimplePlugin_decompressor_bufferValidPatched = (IBusSimplePlugin_decompressor_input_valid ? IBusSimplePlugin_decompressor_bufferValid : IBusSimplePlugin_decompressor_bufferValidLatch);\n  assign IBusSimplePlugin_decompressor_throw2BytesPatched = (IBusSimplePlugin_decompressor_input_valid ? IBusSimplePlugin_decompressor_throw2Bytes : IBusSimplePlugin_decompressor_throw2BytesLatch);\n  assign IBusSimplePlugin_decompressor_raw = (IBusSimplePlugin_decompressor_bufferValidPatched ? {IBusSimplePlugin_decompressor_input_payload_rsp_inst[15 : 0],IBusSimplePlugin_decompressor_bufferData} : {IBusSimplePlugin_decompressor_input_payload_rsp_inst[31 : 16],(IBusSimplePlugin_decompressor_throw2BytesPatched ? IBusSimplePlugin_decompressor_input_payload_rsp_inst[31 : 16] : IBusSimplePlugin_decompressor_input_payload_rsp_inst[15 : 0])});\n  assign IBusSimplePlugin_decompressor_isRvc = (IBusSimplePlugin_decompressor_raw[1 : 0] != 2'b11);\n  assign _zz_IBusSimplePlugin_decompressor_decompressed = IBusSimplePlugin_decompressor_raw[15 : 0];\n  always @(*) begin\n    IBusSimplePlugin_decompressor_decompressed = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;\n    case(switch_Misc_l44)\n      5'h0 : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_IBusSimplePlugin_decompressor_decompressed[10 : 7]},_zz_IBusSimplePlugin_decompressor_decompressed[12 : 11]},_zz_IBusSimplePlugin_decompressor_decompressed[5]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},2'b00},5'h02},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed_2},7'h13};\n      end\n      5'h02 : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{_zz_IBusSimplePlugin_decompressor_decompressed_3,_zz_IBusSimplePlugin_decompressor_decompressed_1},3'b010},_zz_IBusSimplePlugin_decompressor_decompressed_2},7'h03};\n      end\n      5'h06 : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_3[11 : 5],_zz_IBusSimplePlugin_decompressor_decompressed_2},_zz_IBusSimplePlugin_decompressor_decompressed_1},3'b010},_zz_IBusSimplePlugin_decompressor_decompressed_3[4 : 0]},7'h23};\n      end\n      5'h08 : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{_zz_IBusSimplePlugin_decompressor_decompressed_5,_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h13};\n      end\n      5'h09 : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_8[20],_zz_IBusSimplePlugin_decompressor_decompressed_8[10 : 1]},_zz_IBusSimplePlugin_decompressor_decompressed_8[11]},_zz_IBusSimplePlugin_decompressor_decompressed_8[19 : 12]},_zz_IBusSimplePlugin_decompressor_decompressed_20},7'h6f};\n      end\n      5'h0a : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{_zz_IBusSimplePlugin_decompressor_decompressed_5,5'h0},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h13};\n      end\n      5'h0b : begin\n        IBusSimplePlugin_decompressor_decompressed = ((_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7] == 5'h02) ? {{{{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_12,_zz_IBusSimplePlugin_decompressor_decompressed[4 : 3]},_zz_IBusSimplePlugin_decompressor_decompressed[5]},_zz_IBusSimplePlugin_decompressor_decompressed[2]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},4'b0000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h13} : {{_zz_IBusSimplePlugin_decompressor_decompressed_27[31 : 12],_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h37});\n      end\n      5'h0c : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{((_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10] == 2'b10) ? _zz_IBusSimplePlugin_decompressor_decompressed_26 : {{1'b0,(_zz_IBusSimplePlugin_decompressor_decompressed_28 || _zz_IBusSimplePlugin_decompressor_decompressed_29)},5'h0}),(((! _zz_IBusSimplePlugin_decompressor_decompressed[11]) || _zz_IBusSimplePlugin_decompressor_decompressed_22) ? _zz_IBusSimplePlugin_decompressor_decompressed[6 : 2] : _zz_IBusSimplePlugin_decompressor_decompressed_2)},_zz_IBusSimplePlugin_decompressor_decompressed_1},_zz_IBusSimplePlugin_decompressor_decompressed_24},_zz_IBusSimplePlugin_decompressor_decompressed_1},(_zz_IBusSimplePlugin_decompressor_decompressed_22 ? 7'h13 : 7'h33)};\n      end\n      5'h0d : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_15[20],_zz_IBusSimplePlugin_decompressor_decompressed_15[10 : 1]},_zz_IBusSimplePlugin_decompressor_decompressed_15[11]},_zz_IBusSimplePlugin_decompressor_decompressed_15[19 : 12]},_zz_IBusSimplePlugin_decompressor_decompressed_19},7'h6f};\n      end\n      5'h0e : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_18[12],_zz_IBusSimplePlugin_decompressor_decompressed_18[10 : 5]},_zz_IBusSimplePlugin_decompressor_decompressed_19},_zz_IBusSimplePlugin_decompressor_decompressed_1},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed_18[4 : 1]},_zz_IBusSimplePlugin_decompressor_decompressed_18[11]},7'h63};\n      end\n      5'h0f : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_18[12],_zz_IBusSimplePlugin_decompressor_decompressed_18[10 : 5]},_zz_IBusSimplePlugin_decompressor_decompressed_19},_zz_IBusSimplePlugin_decompressor_decompressed_1},3'b001},_zz_IBusSimplePlugin_decompressor_decompressed_18[4 : 1]},_zz_IBusSimplePlugin_decompressor_decompressed_18[11]},7'h63};\n      end\n      5'h10 : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{7'h0,_zz_IBusSimplePlugin_decompressor_decompressed[6 : 2]},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},3'b001},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h13};\n      end\n      5'h12 : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_IBusSimplePlugin_decompressor_decompressed[3 : 2]},_zz_IBusSimplePlugin_decompressor_decompressed[12]},_zz_IBusSimplePlugin_decompressor_decompressed[6 : 4]},2'b00},_zz_IBusSimplePlugin_decompressor_decompressed_21},3'b010},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h03};\n      end\n      5'h14 : begin\n        IBusSimplePlugin_decompressor_decompressed = ((_zz_IBusSimplePlugin_decompressor_decompressed[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_IBusSimplePlugin_decompressor_decompressed[6 : 2] == 5'h0) ? {{{{12'h0,_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},3'b000},(_zz_IBusSimplePlugin_decompressor_decompressed[12] ? _zz_IBusSimplePlugin_decompressor_decompressed_20 : _zz_IBusSimplePlugin_decompressor_decompressed_19)},7'h67} : {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_30,_zz_IBusSimplePlugin_decompressor_decompressed_31},(_zz_IBusSimplePlugin_decompressor_decompressed_32 ? _zz_IBusSimplePlugin_decompressor_decompressed_33 : _zz_IBusSimplePlugin_decompressor_decompressed_19)},3'b000},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 7]},7'h33}));\n      end\n      5'h16 : begin\n        IBusSimplePlugin_decompressor_decompressed = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_34[11 : 5],_zz_IBusSimplePlugin_decompressor_decompressed[6 : 2]},_zz_IBusSimplePlugin_decompressor_decompressed_21},3'b010},_zz_IBusSimplePlugin_decompressor_decompressed_35[4 : 0]},7'h23};\n      end\n      default : begin\n      end\n    endcase\n  end\n\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_1 = {2'b01,_zz_IBusSimplePlugin_decompressor_decompressed[9 : 7]};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_2 = {2'b01,_zz_IBusSimplePlugin_decompressor_decompressed[4 : 2]};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_3 = {{{{5'h0,_zz_IBusSimplePlugin_decompressor_decompressed[5]},_zz_IBusSimplePlugin_decompressor_decompressed[12 : 10]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},2'b00};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_4 = _zz_IBusSimplePlugin_decompressor_decompressed[12];\n  always @(*) begin\n    _zz_IBusSimplePlugin_decompressor_decompressed_5[11] = _zz_IBusSimplePlugin_decompressor_decompressed_4;\n    _zz_IBusSimplePlugin_decompressor_decompressed_5[10] = _zz_IBusSimplePlugin_decompressor_decompressed_4;\n    _zz_IBusSimplePlugin_decompressor_decompressed_5[9] = _zz_IBusSimplePlugin_decompressor_decompressed_4;\n    _zz_IBusSimplePlugin_decompressor_decompressed_5[8] = _zz_IBusSimplePlugin_decompressor_decompressed_4;\n    _zz_IBusSimplePlugin_decompressor_decompressed_5[7] = _zz_IBusSimplePlugin_decompressor_decompressed_4;\n    _zz_IBusSimplePlugin_decompressor_decompressed_5[6] = _zz_IBusSimplePlugin_decompressor_decompressed_4;\n    _zz_IBusSimplePlugin_decompressor_decompressed_5[5] = _zz_IBusSimplePlugin_decompressor_decompressed_4;\n    _zz_IBusSimplePlugin_decompressor_decompressed_5[4 : 0] = _zz_IBusSimplePlugin_decompressor_decompressed[6 : 2];\n  end\n\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_6 = _zz_IBusSimplePlugin_decompressor_decompressed[12];\n  always @(*) begin\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[9] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[8] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[7] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[6] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[5] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[4] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[3] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[2] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[1] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n    _zz_IBusSimplePlugin_decompressor_decompressed_7[0] = _zz_IBusSimplePlugin_decompressor_decompressed_6;\n  end\n\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_8 = {{{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_7,_zz_IBusSimplePlugin_decompressor_decompressed[8]},_zz_IBusSimplePlugin_decompressor_decompressed[10 : 9]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},_zz_IBusSimplePlugin_decompressor_decompressed[7]},_zz_IBusSimplePlugin_decompressor_decompressed[2]},_zz_IBusSimplePlugin_decompressor_decompressed[11]},_zz_IBusSimplePlugin_decompressor_decompressed[5 : 3]},1'b0};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_9 = _zz_IBusSimplePlugin_decompressor_decompressed[12];\n  always @(*) begin\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[14] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[13] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[12] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[11] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[10] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[9] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[8] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[7] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[6] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[5] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[4] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[3] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[2] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[1] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n    _zz_IBusSimplePlugin_decompressor_decompressed_10[0] = _zz_IBusSimplePlugin_decompressor_decompressed_9;\n  end\n\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_11 = _zz_IBusSimplePlugin_decompressor_decompressed[12];\n  always @(*) begin\n    _zz_IBusSimplePlugin_decompressor_decompressed_12[2] = _zz_IBusSimplePlugin_decompressor_decompressed_11;\n    _zz_IBusSimplePlugin_decompressor_decompressed_12[1] = _zz_IBusSimplePlugin_decompressor_decompressed_11;\n    _zz_IBusSimplePlugin_decompressor_decompressed_12[0] = _zz_IBusSimplePlugin_decompressor_decompressed_11;\n  end\n\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_13 = _zz_IBusSimplePlugin_decompressor_decompressed[12];\n  always @(*) begin\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[9] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[8] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[7] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[6] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[5] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[4] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[3] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[2] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[1] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n    _zz_IBusSimplePlugin_decompressor_decompressed_14[0] = _zz_IBusSimplePlugin_decompressor_decompressed_13;\n  end\n\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_15 = {{{{{{{{_zz_IBusSimplePlugin_decompressor_decompressed_14,_zz_IBusSimplePlugin_decompressor_decompressed[8]},_zz_IBusSimplePlugin_decompressor_decompressed[10 : 9]},_zz_IBusSimplePlugin_decompressor_decompressed[6]},_zz_IBusSimplePlugin_decompressor_decompressed[7]},_zz_IBusSimplePlugin_decompressor_decompressed[2]},_zz_IBusSimplePlugin_decompressor_decompressed[11]},_zz_IBusSimplePlugin_decompressor_decompressed[5 : 3]},1'b0};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_16 = _zz_IBusSimplePlugin_decompressor_decompressed[12];\n  always @(*) begin\n    _zz_IBusSimplePlugin_decompressor_decompressed_17[4] = _zz_IBusSimplePlugin_decompressor_decompressed_16;\n    _zz_IBusSimplePlugin_decompressor_decompressed_17[3] = _zz_IBusSimplePlugin_decompressor_decompressed_16;\n    _zz_IBusSimplePlugin_decompressor_decompressed_17[2] = _zz_IBusSimplePlugin_decompressor_decompressed_16;\n    _zz_IBusSimplePlugin_decompressor_decompressed_17[1] = _zz_IBusSimplePlugin_decompressor_decompressed_16;\n    _zz_IBusSimplePlugin_decompressor_decompressed_17[0] = _zz_IBusSimplePlugin_decompressor_decompressed_16;\n  end\n\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_18 = {{{{{_zz_IBusSimplePlugin_decompressor_decompressed_17,_zz_IBusSimplePlugin_decompressor_decompressed[6 : 5]},_zz_IBusSimplePlugin_decompressor_decompressed[2]},_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10]},_zz_IBusSimplePlugin_decompressor_decompressed[4 : 3]},1'b0};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_19 = 5'h0;\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_20 = 5'h01;\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_21 = 5'h02;\n  assign switch_Misc_l44 = {_zz_IBusSimplePlugin_decompressor_decompressed[1 : 0],_zz_IBusSimplePlugin_decompressor_decompressed[15 : 13]};\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_22 = (_zz_IBusSimplePlugin_decompressor_decompressed[11 : 10] != 2'b11);\n  assign switch_Misc_l211 = _zz_IBusSimplePlugin_decompressor_decompressed[11 : 10];\n  assign switch_Misc_l211_1 = _zz_IBusSimplePlugin_decompressor_decompressed[6 : 5];\n  always @(*) begin\n    case(switch_Misc_l211_1)\n      2'b00 : begin\n        _zz_IBusSimplePlugin_decompressor_decompressed_23 = 3'b000;\n      end\n      2'b01 : begin\n        _zz_IBusSimplePlugin_decompressor_decompressed_23 = 3'b100;\n      end\n      2'b10 : begin\n        _zz_IBusSimplePlugin_decompressor_decompressed_23 = 3'b110;\n      end\n      default : begin\n        _zz_IBusSimplePlugin_decompressor_decompressed_23 = 3'b111;\n      end\n    endcase\n  end\n\n  always @(*) begin\n    case(switch_Misc_l211)\n      2'b00 : begin\n        _zz_IBusSimplePlugin_decompressor_decompressed_24 = 3'b101;\n      end\n      2'b01 : begin\n        _zz_IBusSimplePlugin_decompressor_decompressed_24 = 3'b101;\n      end\n      2'b10 : begin\n        _zz_IBusSimplePlugin_decompressor_decompressed_24 = 3'b111;\n      end\n      default : begin\n        _zz_IBusSimplePlugin_decompressor_decompressed_24 = _zz_IBusSimplePlugin_decompressor_decompressed_23;\n      end\n    endcase\n  end\n\n  assign _zz_IBusSimplePlugin_decompressor_decompressed_25 = _zz_IBusSimplePlugin_decompressor_decompressed[12];\n  always @(*) begin\n    _zz_IBusSimplePlugin_decompressor_decompressed_26[6] = _zz_IBusSimplePlugin_decompressor_decompressed_25;\n    _zz_IBusSimplePlugin_decompressor_decompressed_26[5] = _zz_IBusSimplePlugin_decompressor_decompressed_25;\n    _zz_IBusSimplePlugin_decompressor_decompressed_26[4] = _zz_IBusSimplePlugin_decompressor_decompressed_25;\n    _zz_IBusSimplePlugin_decompressor_decompressed_26[3] = _zz_IBusSimplePlugin_decompressor_decompressed_25;\n    _zz_IBusSimplePlugin_decompressor_decompressed_26[2] = _zz_IBusSimplePlugin_decompressor_decompressed_25;\n    _zz_IBusSimplePlugin_decompressor_decompressed_26[1] = _zz_IBusSimplePlugin_decompressor_decompressed_25;\n    _zz_IBusSimplePlugin_decompressor_decompressed_26[0] = _zz_IBusSimplePlugin_decompressor_decompressed_25;\n  end\n\n  assign IBusSimplePlugin_decompressor_output_valid = (IBusSimplePlugin_decompressor_input_valid && (! ((IBusSimplePlugin_decompressor_throw2Bytes && (! IBusSimplePlugin_decompressor_bufferValid)) && (! IBusSimplePlugin_decompressor_isInputHighRvc))));\n  assign IBusSimplePlugin_decompressor_output_payload_pc = IBusSimplePlugin_decompressor_input_payload_pc;\n  assign IBusSimplePlugin_decompressor_output_payload_isRvc = IBusSimplePlugin_decompressor_isRvc;\n  assign IBusSimplePlugin_decompressor_output_payload_rsp_inst = (IBusSimplePlugin_decompressor_isRvc ? IBusSimplePlugin_decompressor_decompressed : IBusSimplePlugin_decompressor_raw);\n  always @(*) begin\n    IBusSimplePlugin_decompressor_input_ready = (IBusSimplePlugin_decompressor_output_ready && (((! IBusSimplePlugin_iBusRsp_stages_1_input_valid) || IBusSimplePlugin_decompressor_flushNext) || ((! (IBusSimplePlugin_decompressor_bufferValid && IBusSimplePlugin_decompressor_isInputHighRvc)) && (! (((! IBusSimplePlugin_decompressor_unaligned) && IBusSimplePlugin_decompressor_isInputLowRvc) && IBusSimplePlugin_decompressor_isInputHighRvc)))));\n    if(when_Fetcher_l617) begin\n      IBusSimplePlugin_decompressor_input_ready = 1'b1;\n    end\n  end\n\n  assign IBusSimplePlugin_decompressor_output_fire = (IBusSimplePlugin_decompressor_output_valid && IBusSimplePlugin_decompressor_output_ready);\n  assign IBusSimplePlugin_decompressor_bufferFill = (((((! IBusSimplePlugin_decompressor_unaligned) && IBusSimplePlugin_decompressor_isInputLowRvc) && (! IBusSimplePlugin_decompressor_isInputHighRvc)) || (IBusSimplePlugin_decompressor_bufferValid && (! IBusSimplePlugin_decompressor_isInputHighRvc))) || ((IBusSimplePlugin_decompressor_throw2Bytes && (! IBusSimplePlugin_decompressor_isRvc)) && (! IBusSimplePlugin_decompressor_isInputHighRvc)));\n  assign when_Fetcher_l283 = (IBusSimplePlugin_decompressor_output_ready && IBusSimplePlugin_decompressor_input_valid);\n  assign when_Fetcher_l286 = (IBusSimplePlugin_decompressor_output_ready && IBusSimplePlugin_decompressor_input_valid);\n  assign when_Fetcher_l291 = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_decompressor_consumeCurrent);\n  assign IBusSimplePlugin_decompressor_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready);\n  assign IBusSimplePlugin_injector_decodeInput_valid = _zz_IBusSimplePlugin_injector_decodeInput_valid;\n  assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_IBusSimplePlugin_injector_decodeInput_payload_pc;\n  assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error;\n  assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;\n  assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc;\n  assign when_Fetcher_l329 = (! 1'b0);\n  assign when_Fetcher_l329_1 = (! execute_arbitration_isStuck);\n  assign when_Fetcher_l329_2 = (! memory_arbitration_isStuck);\n  assign when_Fetcher_l329_3 = (! writeBack_arbitration_isStuck);\n  assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_0;\n  assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_1;\n  assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_2;\n  assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_3;\n  assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck);\n  assign decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid;\n  always @(*) begin\n    _zz_decode_FORMAL_PC_NEXT = (decode_PC + _zz__zz_decode_FORMAL_PC_NEXT);\n    if(IBusSimplePlugin_decodePc_predictionPcLoad_valid) begin\n      _zz_decode_FORMAL_PC_NEXT = IBusSimplePlugin_decodePc_predictionPcLoad_payload;\n    end\n  end\n\n  assign IBusSimplePlugin_predictor_historyWriteDelayPatched_valid = IBusSimplePlugin_predictor_historyWrite_valid;\n  assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_address = (IBusSimplePlugin_predictor_historyWrite_payload_address - 10'h001);\n  assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_source = IBusSimplePlugin_predictor_historyWrite_payload_data_source;\n  assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_branchWish = IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish;\n  assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_last2Bytes = IBusSimplePlugin_predictor_historyWrite_payload_data_last2Bytes;\n  assign IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_target = IBusSimplePlugin_predictor_historyWrite_payload_data_target;\n  assign _zz_IBusSimplePlugin_predictor_buffer_line_source = (IBusSimplePlugin_iBusRsp_stages_0_input_payload >>> 2);\n  assign _zz_IBusSimplePlugin_predictor_buffer_line_source_1 = _zz_IBusSimplePlugin_predictor_history_port1;\n  assign IBusSimplePlugin_predictor_buffer_line_source = _zz_IBusSimplePlugin_predictor_buffer_line_source_1[19 : 0];\n  assign IBusSimplePlugin_predictor_buffer_line_branchWish = _zz_IBusSimplePlugin_predictor_buffer_line_source_1[21 : 20];\n  assign IBusSimplePlugin_predictor_buffer_line_last2Bytes = _zz_IBusSimplePlugin_predictor_buffer_line_source_1[22];\n  assign IBusSimplePlugin_predictor_buffer_line_target = _zz_IBusSimplePlugin_predictor_buffer_line_source_1[54 : 23];\n  assign IBusSimplePlugin_predictor_buffer_hazard = (IBusSimplePlugin_predictor_writeLast_valid && (IBusSimplePlugin_predictor_writeLast_payload_address == _zz_IBusSimplePlugin_predictor_buffer_hazard));\n  assign IBusSimplePlugin_predictor_hazard = (IBusSimplePlugin_predictor_buffer_hazard_regNextWhen || IBusSimplePlugin_predictor_buffer_pcCorrected);\n  always @(*) begin\n    IBusSimplePlugin_predictor_hit = (IBusSimplePlugin_predictor_line_source == _zz_IBusSimplePlugin_predictor_hit);\n    if(when_Fetcher_l550) begin\n      IBusSimplePlugin_predictor_hit = 1'b0;\n    end\n  end\n\n  assign when_Fetcher_l550 = ((! IBusSimplePlugin_predictor_line_last2Bytes) && IBusSimplePlugin_iBusRsp_stages_1_input_payload[1]);\n  assign IBusSimplePlugin_fetchPc_predictionPcLoad_valid = (((IBusSimplePlugin_predictor_line_branchWish[1] && IBusSimplePlugin_predictor_hit) && (! IBusSimplePlugin_predictor_hazard)) && IBusSimplePlugin_iBusRsp_stages_1_input_valid);\n  assign IBusSimplePlugin_fetchPc_predictionPcLoad_payload = IBusSimplePlugin_predictor_line_target;\n  assign IBusSimplePlugin_predictor_fetchContext_hazard = IBusSimplePlugin_predictor_hazard;\n  assign IBusSimplePlugin_predictor_fetchContext_hit = IBusSimplePlugin_predictor_hit;\n  assign IBusSimplePlugin_predictor_fetchContext_line_source = IBusSimplePlugin_predictor_line_source;\n  assign IBusSimplePlugin_predictor_fetchContext_line_branchWish = IBusSimplePlugin_predictor_line_branchWish;\n  assign IBusSimplePlugin_predictor_fetchContext_line_last2Bytes = IBusSimplePlugin_predictor_line_last2Bytes;\n  assign IBusSimplePlugin_predictor_fetchContext_line_target = IBusSimplePlugin_predictor_line_target;\n  assign IBusSimplePlugin_predictor_iBusRspContextOutput_hazard = IBusSimplePlugin_predictor_fetchContext_hazard;\n  always @(*) begin\n    IBusSimplePlugin_predictor_iBusRspContextOutput_hit = IBusSimplePlugin_predictor_fetchContext_hit;\n    if(when_Fetcher_l611) begin\n      IBusSimplePlugin_predictor_iBusRspContextOutput_hit = 1'b0;\n    end\n  end\n\n  assign IBusSimplePlugin_predictor_iBusRspContextOutput_line_source = IBusSimplePlugin_predictor_fetchContext_line_source;\n  assign IBusSimplePlugin_predictor_iBusRspContextOutput_line_branchWish = IBusSimplePlugin_predictor_fetchContext_line_branchWish;\n  assign IBusSimplePlugin_predictor_iBusRspContextOutput_line_last2Bytes = IBusSimplePlugin_predictor_fetchContext_line_last2Bytes;\n  assign IBusSimplePlugin_predictor_iBusRspContextOutput_line_target = IBusSimplePlugin_predictor_fetchContext_line_target;\n  assign IBusSimplePlugin_predictor_injectorContext_hazard = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hazard;\n  assign IBusSimplePlugin_predictor_injectorContext_hit = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hit;\n  assign IBusSimplePlugin_predictor_injectorContext_line_source = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_source;\n  assign IBusSimplePlugin_predictor_injectorContext_line_branchWish = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_branchWish;\n  assign IBusSimplePlugin_predictor_injectorContext_line_last2Bytes = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_last2Bytes;\n  assign IBusSimplePlugin_predictor_injectorContext_line_target = IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_target;\n  assign IBusSimplePlugin_fetchPrediction_cmd_hadBranch = ((memory_PREDICTION_CONTEXT_hit && (! memory_PREDICTION_CONTEXT_hazard)) && memory_PREDICTION_CONTEXT_line_branchWish[1]);\n  assign IBusSimplePlugin_fetchPrediction_cmd_targetPc = memory_PREDICTION_CONTEXT_line_target;\n  always @(*) begin\n    IBusSimplePlugin_predictor_historyWrite_valid = 1'b0;\n    if(IBusSimplePlugin_fetchPrediction_rsp_wasRight) begin\n      IBusSimplePlugin_predictor_historyWrite_valid = memory_PREDICTION_CONTEXT_hit;\n    end else begin\n      if(memory_PREDICTION_CONTEXT_hit) begin\n        IBusSimplePlugin_predictor_historyWrite_valid = 1'b1;\n      end else begin\n        IBusSimplePlugin_predictor_historyWrite_valid = 1'b1;\n      end\n    end\n    if(when_Fetcher_l596) begin\n      IBusSimplePlugin_predictor_historyWrite_valid = 1'b0;\n    end\n    if(IBusSimplePlugin_predictor_compressor_unalignedWordIssue) begin\n      IBusSimplePlugin_predictor_historyWrite_valid = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    IBusSimplePlugin_predictor_historyWrite_payload_address = IBusSimplePlugin_fetchPrediction_rsp_sourceLastWord[11 : 2];\n    if(IBusSimplePlugin_predictor_compressor_unalignedWordIssue) begin\n      IBusSimplePlugin_predictor_historyWrite_payload_address = _zz_IBusSimplePlugin_predictor_historyWrite_payload_address[9:0];\n    end\n  end\n\n  assign IBusSimplePlugin_predictor_historyWrite_payload_data_source = (IBusSimplePlugin_fetchPrediction_rsp_sourceLastWord >>> 12);\n  assign IBusSimplePlugin_predictor_historyWrite_payload_data_target = IBusSimplePlugin_fetchPrediction_rsp_finalPc;\n  assign IBusSimplePlugin_predictor_historyWrite_payload_data_last2Bytes = (memory_PC[1] && memory_IS_RVC);\n  always @(*) begin\n    if(IBusSimplePlugin_fetchPrediction_rsp_wasRight) begin\n      IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = (_zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish - _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_3);\n    end else begin\n      if(memory_PREDICTION_CONTEXT_hit) begin\n        IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = (_zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_5 + _zz_IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish_8);\n      end else begin\n        IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = 2'b10;\n      end\n    end\n    if(IBusSimplePlugin_predictor_compressor_unalignedWordIssue) begin\n      IBusSimplePlugin_predictor_historyWrite_payload_data_branchWish = 2'b00;\n    end\n  end\n\n  assign when_Fetcher_l596 = (memory_PREDICTION_CONTEXT_hazard || (! memory_arbitration_isFiring));\n  assign IBusSimplePlugin_predictor_compressor_predictionBranch = ((IBusSimplePlugin_predictor_fetchContext_hit && (! IBusSimplePlugin_predictor_fetchContext_hazard)) && IBusSimplePlugin_predictor_fetchContext_line_branchWish[1]);\n  assign IBusSimplePlugin_predictor_compressor_unalignedWordIssue = (((IBusSimplePlugin_iBusRsp_output_valid && IBusSimplePlugin_predictor_compressor_predictionBranch) && IBusSimplePlugin_predictor_fetchContext_line_last2Bytes) && (IBusSimplePlugin_decompressor_unaligned ? (! IBusSimplePlugin_decompressor_isInputHighRvc) : (IBusSimplePlugin_decompressor_isInputLowRvc && (! IBusSimplePlugin_decompressor_isInputHighRvc))));\n  assign when_Fetcher_l611 = (IBusSimplePlugin_predictor_fetchContext_line_last2Bytes && (IBusSimplePlugin_decompressor_bufferValid || ((! IBusSimplePlugin_decompressor_throw2Bytes) && IBusSimplePlugin_decompressor_isInputLowRvc)));\n  assign IBusSimplePlugin_injector_decodeInput_fire = (IBusSimplePlugin_injector_decodeInput_valid && IBusSimplePlugin_injector_decodeInput_ready);\n  assign IBusSimplePlugin_decodePc_predictionPcLoad_valid = (((IBusSimplePlugin_predictor_injectorContext_line_branchWish[1] && IBusSimplePlugin_predictor_injectorContext_hit) && (! IBusSimplePlugin_predictor_injectorContext_hazard)) && IBusSimplePlugin_injector_decodeInput_fire);\n  assign IBusSimplePlugin_decodePc_predictionPcLoad_payload = IBusSimplePlugin_predictor_injectorContext_line_target;\n  assign IBusSimplePlugin_decompressor_output_fire_1 = (IBusSimplePlugin_decompressor_output_valid && IBusSimplePlugin_decompressor_output_ready);\n  assign when_Fetcher_l617 = (((IBusSimplePlugin_predictor_fetchContext_line_branchWish[1] && IBusSimplePlugin_predictor_iBusRspContextOutput_hit) && (! IBusSimplePlugin_predictor_fetchContext_hazard)) && IBusSimplePlugin_decompressor_output_fire_1);\n  assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid;\n  assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready;\n  assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc;\n  assign IBusSimplePlugin_pending_next = (_zz_IBusSimplePlugin_pending_next - _zz_IBusSimplePlugin_pending_next_3);\n  assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111));\n  assign when_IBusSimplePlugin_l305 = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready)));\n  assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit);\n  assign IBusSimplePlugin_cmd_fire = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready);\n  assign IBusSimplePlugin_pending_inc = IBusSimplePlugin_cmd_fire;\n  assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_0_input_payload[31 : 2],2'b00};\n  assign iBus_rsp_toStream_valid = iBus_rsp_valid;\n  assign iBus_rsp_toStream_payload_error = iBus_rsp_payload_error;\n  assign iBus_rsp_toStream_payload_inst = iBus_rsp_payload_inst;\n  assign iBus_rsp_toStream_ready = IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;\n  assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush);\n  assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000));\n  assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;\n  assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;\n  assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush);\n  assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready);\n  assign IBusSimplePlugin_pending_dec = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire;\n  assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload;\n  always @(*) begin\n    IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error;\n    if(when_IBusSimplePlugin_l376) begin\n      IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0;\n    end\n  end\n\n  assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst;\n  assign when_IBusSimplePlugin_l376 = (! IBusSimplePlugin_rspJoin_rspBuffer_output_valid);\n  assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0;\n  assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid);\n  assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc;\n  assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error;\n  assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;\n  assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc;\n  assign IBusSimplePlugin_rspJoin_join_fire = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready);\n  assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? IBusSimplePlugin_rspJoin_join_fire : IBusSimplePlugin_rspJoin_join_ready);\n  assign IBusSimplePlugin_rspJoin_join_fire_1 = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready);\n  assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = IBusSimplePlugin_rspJoin_join_fire_1;\n  assign _zz_IBusSimplePlugin_iBusRsp_output_valid = (! IBusSimplePlugin_rspJoin_exceptionDetected);\n  assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_IBusSimplePlugin_iBusRsp_output_valid);\n  assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_IBusSimplePlugin_iBusRsp_output_valid);\n  assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc;\n  assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error;\n  assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst;\n  assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc;\n  assign _zz_dBus_cmd_valid = 1'b0;\n  always @(*) begin\n    execute_DBusSimplePlugin_skipCmd = 1'b0;\n    if(execute_ALIGNEMENT_FAULT) begin\n      execute_DBusSimplePlugin_skipCmd = 1'b1;\n    end\n  end\n\n  assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid));\n  assign dBus_cmd_payload_wr = execute_MEMORY_STORE;\n  assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];\n  always @(*) begin\n    case(dBus_cmd_payload_size)\n      2'b00 : begin\n        _zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};\n      end\n      2'b01 : begin\n        _zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]};\n      end\n      default : begin\n        _zz_dBus_cmd_payload_data = execute_RS2[31 : 0];\n      end\n    endcase\n  end\n\n  assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data;\n  assign when_DBusSimplePlugin_l428 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid));\n  always @(*) begin\n    case(dBus_cmd_payload_size)\n      2'b00 : begin\n        _zz_execute_DBusSimplePlugin_formalMask = 4'b0001;\n      end\n      2'b01 : begin\n        _zz_execute_DBusSimplePlugin_formalMask = 4'b0011;\n      end\n      default : begin\n        _zz_execute_DBusSimplePlugin_formalMask = 4'b1111;\n      end\n    endcase\n  end\n\n  assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]);\n  assign dBus_cmd_payload_address = execute_SRC_ADD;\n  assign when_DBusSimplePlugin_l482 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0));\n  always @(*) begin\n    DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;\n    if(memory_ALIGNEMENT_FAULT) begin\n      DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;\n    end\n    if(when_DBusSimplePlugin_l515) begin\n      DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;\n    end\n  end\n\n  always @(*) begin\n    DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx;\n    if(memory_ALIGNEMENT_FAULT) begin\n      DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_DBusSimplePlugin_memoryExceptionPort_payload_code};\n    end\n  end\n\n  assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA;\n  assign when_DBusSimplePlugin_l515 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers))));\n  always @(*) begin\n    writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA;\n    case(writeBack_MEMORY_ADDRESS_LOW)\n      2'b01 : begin\n        writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8];\n      end\n      2'b10 : begin\n        writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16];\n      end\n      2'b11 : begin\n        writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24];\n      end\n      default : begin\n      end\n    endcase\n  end\n\n  assign switch_Misc_l211_2 = writeBack_INSTRUCTION[13 : 12];\n  assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14]));\n  always @(*) begin\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0];\n  end\n\n  assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14]));\n  always @(*) begin\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2;\n    _zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0];\n  end\n\n  always @(*) begin\n    case(switch_Misc_l211_2)\n      2'b00 : begin\n        writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1;\n      end\n      2'b01 : begin\n        writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3;\n      end\n      default : begin\n        writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted;\n      end\n    endcase\n  end\n\n  assign when_DBusSimplePlugin_l558 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);\n  assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0);\n  assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);\n  assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);\n  assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010);\n  assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_5,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{(|_zz__zz_decode_BRANCH_CTRL_2_5),{_zz__zz_decode_BRANCH_CTRL_2_8,{_zz__zz_decode_BRANCH_CTRL_2_10,_zz__zz_decode_BRANCH_CTRL_2_13}}}}}};\n  assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[1 : 0];\n  assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;\n  assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[6 : 5];\n  assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;\n  assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[8 : 7];\n  assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;\n  assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[17 : 16];\n  assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;\n  assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[20 : 19];\n  assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;\n  assign _zz_decode_BRANCH_CTRL_7 = _zz_decode_BRANCH_CTRL_2[22 : 21];\n  assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_7;\n  assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));\n  assign decodeExceptionPort_payload_code = 4'b0010;\n  assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;\n  assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);\n  assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];\n  assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];\n  assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;\n  assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;\n  always @(*) begin\n    lastStageRegFileWrite_valid = (_zz_rvfi_rd_addr && writeBack_arbitration_isFiring);\n    if(_zz_3) begin\n      lastStageRegFileWrite_valid = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    lastStageRegFileWrite_payload_address = _zz_rvfi_rs1_addr[11 : 7];\n    if(_zz_3) begin\n      lastStageRegFileWrite_payload_address = 5'h0;\n    end\n  end\n\n  always @(*) begin\n    lastStageRegFileWrite_payload_data = _zz_rvfi_rd_wdata;\n    if(_zz_3) begin\n      lastStageRegFileWrite_payload_data = 32'h0;\n    end\n  end\n\n  always @(*) begin\n    case(execute_ALU_BITWISE_CTRL)\n      AluBitwiseCtrlEnum_AND_1 : begin\n        execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);\n      end\n      AluBitwiseCtrlEnum_OR_1 : begin\n        execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);\n      end\n      default : begin\n        execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);\n      end\n    endcase\n  end\n\n  always @(*) begin\n    case(execute_ALU_CTRL)\n      AluCtrlEnum_BITWISE : begin\n        _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;\n      end\n      AluCtrlEnum_SLT_SLTU : begin\n        _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};\n      end\n      default : begin\n        _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;\n      end\n    endcase\n  end\n\n  always @(*) begin\n    case(decode_SRC1_CTRL)\n      Src1CtrlEnum_RS : begin\n        _zz_decode_SRC1_1 = _zz_decode_SRC1;\n      end\n      Src1CtrlEnum_PC_INCREMENT : begin\n        _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1};\n      end\n      Src1CtrlEnum_IMU : begin\n        _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0};\n      end\n      default : begin\n        _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1};\n      end\n    endcase\n  end\n\n  assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31];\n  always @(*) begin\n    _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2;\n    _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2;\n  end\n\n  assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11];\n  always @(*) begin\n    _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4;\n    _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4;\n  end\n\n  always @(*) begin\n    case(decode_SRC2_CTRL)\n      Src2CtrlEnum_RS : begin\n        _zz_decode_SRC2_6 = _zz_decode_SRC2_1;\n      end\n      Src2CtrlEnum_IMI : begin\n        _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]};\n      end\n      Src2CtrlEnum_IMS : begin\n        _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}};\n      end\n      default : begin\n        _zz_decode_SRC2_6 = _zz_decode_SRC2;\n      end\n    endcase\n  end\n\n  always @(*) begin\n    execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;\n    if(execute_SRC2_FORCE_ZERO) begin\n      execute_SrcPlugin_addSub = execute_SRC1;\n    end\n  end\n\n  assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));\n  assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];\n  always @(*) begin\n    _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];\n    _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];\n    _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];\n    _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];\n    _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];\n    _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];\n    _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];\n    _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];\n    _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];\n    _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];\n    _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];\n    _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];\n    _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];\n    _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];\n    _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];\n    _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];\n    _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];\n    _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];\n    _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];\n    _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];\n    _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];\n    _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];\n    _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];\n    _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];\n    _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];\n    _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];\n    _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];\n    _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];\n    _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];\n    _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];\n    _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];\n    _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];\n  end\n\n  assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);\n  always @(*) begin\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[0] = memory_SHIFT_RIGHT[31];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[1] = memory_SHIFT_RIGHT[30];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[2] = memory_SHIFT_RIGHT[29];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[3] = memory_SHIFT_RIGHT[28];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[4] = memory_SHIFT_RIGHT[27];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[5] = memory_SHIFT_RIGHT[26];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[6] = memory_SHIFT_RIGHT[25];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[7] = memory_SHIFT_RIGHT[24];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[8] = memory_SHIFT_RIGHT[23];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[9] = memory_SHIFT_RIGHT[22];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[10] = memory_SHIFT_RIGHT[21];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[11] = memory_SHIFT_RIGHT[20];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[12] = memory_SHIFT_RIGHT[19];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[13] = memory_SHIFT_RIGHT[18];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[14] = memory_SHIFT_RIGHT[17];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[15] = memory_SHIFT_RIGHT[16];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[16] = memory_SHIFT_RIGHT[15];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[17] = memory_SHIFT_RIGHT[14];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[18] = memory_SHIFT_RIGHT[13];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[19] = memory_SHIFT_RIGHT[12];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[20] = memory_SHIFT_RIGHT[11];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[21] = memory_SHIFT_RIGHT[10];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[22] = memory_SHIFT_RIGHT[9];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[23] = memory_SHIFT_RIGHT[8];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[24] = memory_SHIFT_RIGHT[7];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[25] = memory_SHIFT_RIGHT[6];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[26] = memory_SHIFT_RIGHT[5];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[27] = memory_SHIFT_RIGHT[4];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[28] = memory_SHIFT_RIGHT[3];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[29] = memory_SHIFT_RIGHT[2];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[30] = memory_SHIFT_RIGHT[1];\n    _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[31] = memory_SHIFT_RIGHT[0];\n  end\n\n  always @(*) begin\n    HazardSimplePlugin_src0Hazard = 1'b0;\n    if(HazardSimplePlugin_writeBackBuffer_valid) begin\n      if(HazardSimplePlugin_addr0Match) begin\n        HazardSimplePlugin_src0Hazard = 1'b1;\n      end\n    end\n    if(when_HazardSimplePlugin_l57) begin\n      if(when_HazardSimplePlugin_l58) begin\n        if(when_HazardSimplePlugin_l59) begin\n          HazardSimplePlugin_src0Hazard = 1'b1;\n        end\n      end\n    end\n    if(when_HazardSimplePlugin_l57_1) begin\n      if(when_HazardSimplePlugin_l58_1) begin\n        if(when_HazardSimplePlugin_l59_1) begin\n          HazardSimplePlugin_src0Hazard = 1'b1;\n        end\n      end\n    end\n    if(when_HazardSimplePlugin_l57_2) begin\n      if(when_HazardSimplePlugin_l58_2) begin\n        if(when_HazardSimplePlugin_l59_2) begin\n          HazardSimplePlugin_src0Hazard = 1'b1;\n        end\n      end\n    end\n    if(when_HazardSimplePlugin_l105) begin\n      HazardSimplePlugin_src0Hazard = 1'b0;\n    end\n  end\n\n  always @(*) begin\n    HazardSimplePlugin_src1Hazard = 1'b0;\n    if(HazardSimplePlugin_writeBackBuffer_valid) begin\n      if(HazardSimplePlugin_addr1Match) begin\n        HazardSimplePlugin_src1Hazard = 1'b1;\n      end\n    end\n    if(when_HazardSimplePlugin_l57) begin\n      if(when_HazardSimplePlugin_l58) begin\n        if(when_HazardSimplePlugin_l62) begin\n          HazardSimplePlugin_src1Hazard = 1'b1;\n        end\n      end\n    end\n    if(when_HazardSimplePlugin_l57_1) begin\n      if(when_HazardSimplePlugin_l58_1) begin\n        if(when_HazardSimplePlugin_l62_1) begin\n          HazardSimplePlugin_src1Hazard = 1'b1;\n        end\n      end\n    end\n    if(when_HazardSimplePlugin_l57_2) begin\n      if(when_HazardSimplePlugin_l58_2) begin\n        if(when_HazardSimplePlugin_l62_2) begin\n          HazardSimplePlugin_src1Hazard = 1'b1;\n        end\n      end\n    end\n    if(when_HazardSimplePlugin_l108) begin\n      HazardSimplePlugin_src1Hazard = 1'b0;\n    end\n  end\n\n  assign HazardSimplePlugin_writeBackWrites_valid = (_zz_rvfi_rd_addr && writeBack_arbitration_isFiring);\n  assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_rvfi_rs1_addr[11 : 7];\n  assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_rvfi_rd_wdata;\n  assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);\n  assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);\n  assign when_HazardSimplePlugin_l59 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);\n  assign when_HazardSimplePlugin_l62 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);\n  assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);\n  assign when_HazardSimplePlugin_l58 = (1'b1 || (! 1'b1));\n  assign when_HazardSimplePlugin_l59_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);\n  assign when_HazardSimplePlugin_l62_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);\n  assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);\n  assign when_HazardSimplePlugin_l58_1 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE));\n  assign when_HazardSimplePlugin_l59_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);\n  assign when_HazardSimplePlugin_l62_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);\n  assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);\n  assign when_HazardSimplePlugin_l58_2 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE));\n  assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);\n  assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);\n  assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));\n  assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);\n  assign switch_Misc_l211_3 = execute_INSTRUCTION[14 : 12];\n  always @(*) begin\n    casez(switch_Misc_l211_3)\n      3'b000 : begin\n        _zz_execute_BRANCH_DO = execute_BranchPlugin_eq;\n      end\n      3'b001 : begin\n        _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq);\n      end\n      3'b1?1 : begin\n        _zz_execute_BRANCH_DO = (! execute_SRC_LESS);\n      end\n      default : begin\n        _zz_execute_BRANCH_DO = execute_SRC_LESS;\n      end\n    endcase\n  end\n\n  always @(*) begin\n    case(execute_BRANCH_CTRL)\n      BranchCtrlEnum_INC : begin\n        _zz_execute_BRANCH_DO_1 = 1'b0;\n      end\n      BranchCtrlEnum_JAL : begin\n        _zz_execute_BRANCH_DO_1 = 1'b1;\n      end\n      BranchCtrlEnum_JALR : begin\n        _zz_execute_BRANCH_DO_1 = 1'b1;\n      end\n      default : begin\n        _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO;\n      end\n    endcase\n  end\n\n  assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC);\n  assign _zz_execute_BRANCH_SRC22 = _zz__zz_execute_BRANCH_SRC22[19];\n  always @(*) begin\n    _zz_execute_BRANCH_SRC22_1[10] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[9] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[8] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[7] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[6] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[5] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[4] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[3] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[2] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[1] = _zz_execute_BRANCH_SRC22;\n    _zz_execute_BRANCH_SRC22_1[0] = _zz_execute_BRANCH_SRC22;\n  end\n\n  assign _zz_execute_BRANCH_SRC22_2 = execute_INSTRUCTION[31];\n  always @(*) begin\n    _zz_execute_BRANCH_SRC22_3[19] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[18] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[17] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[16] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[15] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[14] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[13] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[12] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[11] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[10] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[9] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[8] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[7] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[6] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[5] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[4] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[3] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[2] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[1] = _zz_execute_BRANCH_SRC22_2;\n    _zz_execute_BRANCH_SRC22_3[0] = _zz_execute_BRANCH_SRC22_2;\n  end\n\n  assign _zz_execute_BRANCH_SRC22_4 = _zz__zz_execute_BRANCH_SRC22_4[11];\n  always @(*) begin\n    _zz_execute_BRANCH_SRC22_5[18] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[17] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[16] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[15] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[14] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[13] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[12] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[11] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[10] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[9] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[8] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[7] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[6] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[5] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[4] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[3] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[2] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[1] = _zz_execute_BRANCH_SRC22_4;\n    _zz_execute_BRANCH_SRC22_5[0] = _zz_execute_BRANCH_SRC22_4;\n  end\n\n  always @(*) begin\n    case(execute_BRANCH_CTRL)\n      BranchCtrlEnum_JAL : begin\n        _zz_execute_BRANCH_SRC22_6 = {{_zz_execute_BRANCH_SRC22_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};\n      end\n      BranchCtrlEnum_JALR : begin\n        _zz_execute_BRANCH_SRC22_6 = {_zz_execute_BRANCH_SRC22_3,execute_INSTRUCTION[31 : 20]};\n      end\n      default : begin\n        _zz_execute_BRANCH_SRC22_6 = {{_zz_execute_BRANCH_SRC22_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};\n      end\n    endcase\n  end\n\n  assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BRANCH_SRC22);\n  assign memory_BranchPlugin_predictionMissmatch = ((IBusSimplePlugin_fetchPrediction_cmd_hadBranch != memory_BRANCH_DO) || (memory_BRANCH_DO && memory_TARGET_MISSMATCH2));\n  assign IBusSimplePlugin_fetchPrediction_rsp_wasRight = (! memory_BranchPlugin_predictionMissmatch);\n  assign IBusSimplePlugin_fetchPrediction_rsp_finalPc = memory_BRANCH_CALC;\n  assign IBusSimplePlugin_fetchPrediction_rsp_sourceLastWord = (((! memory_IS_RVC) && memory_PC[1]) ? memory_NEXT_PC2 : memory_PC);\n  assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BranchPlugin_predictionMissmatch) && (! 1'b0));\n  assign BranchPlugin_jumpInterface_payload = (memory_BRANCH_DO ? memory_BRANCH_CALC : memory_NEXT_PC2);\n  assign when_Pipeline_l124 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_2 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_10 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_15 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_16 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);\n  assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;\n  assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_21 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_22 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);\n  assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;\n  assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;\n  assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);\n  assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;\n  assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;\n  assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_29 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_32 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_36 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_37 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_38 = (! execute_arbitration_isStuck);\n  assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;\n  assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;\n  assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);\n  assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;\n  assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;\n  assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;\n  assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;\n  assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck);\n  assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;\n  assign when_Pipeline_l124_41 = (! memory_arbitration_isStuck);\n  assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;\n  assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;\n  assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;\n  assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);\n  assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;\n  assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_44 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_45 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_47 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_48 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck);\n  assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_56 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_58 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_63 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_64 = (! writeBack_arbitration_isStuck);\n  assign when_Pipeline_l124_65 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_66 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_67 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_68 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_69 = (! memory_arbitration_isStuck);\n  assign when_Pipeline_l124_70 = (! writeBack_arbitration_isStuck);\n  assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));\n  assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));\n  assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));\n  assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));\n  assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));\n  assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);\n  assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));\n  assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));\n  assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));\n  assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);\n  assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));\n  assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));\n  assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));\n  assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);\n  assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));\n  assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));\n  assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);\n  assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);\n  assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));\n  assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));\n  assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);\n  assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));\n  assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);\n  assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));\n  assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);\n  assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));\n  always @(posedge clk) begin\n    if(reset) begin\n      writeBack_FormalPlugin_order <= 64'h0;\n      writeBack_FormalPlugin_haltRequest_delay_1 <= 1'b0;\n      writeBack_FormalPlugin_haltRequest_delay_2 <= 1'b0;\n      writeBack_FormalPlugin_haltRequest_delay_3 <= 1'b0;\n      writeBack_FormalPlugin_haltRequest_delay_4 <= 1'b0;\n      writeBack_FormalPlugin_haltRequest_delay_5 <= 1'b0;\n      writeBack_FormalPlugin_haltFired <= 1'b0;\n      IBusSimplePlugin_fetchPc_pcReg <= 32'h0;\n      IBusSimplePlugin_fetchPc_correctionReg <= 1'b0;\n      IBusSimplePlugin_fetchPc_booted <= 1'b0;\n      IBusSimplePlugin_fetchPc_inc <= 1'b0;\n      IBusSimplePlugin_decodePc_pcReg <= 32'h0;\n      _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid <= 1'b0;\n      IBusSimplePlugin_decompressor_bufferValid <= 1'b0;\n      IBusSimplePlugin_decompressor_throw2BytesReg <= 1'b0;\n      _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0;\n      IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;\n      IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;\n      IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;\n      IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;\n      IBusSimplePlugin_pending_value <= 3'b000;\n      IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000;\n      _zz_3 <= 1'b1;\n      HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;\n      execute_arbitration_isValid <= 1'b0;\n      memory_arbitration_isValid <= 1'b0;\n      writeBack_arbitration_isValid <= 1'b0;\n    end else begin\n      if(writeBack_arbitration_isFiring) begin\n        writeBack_FormalPlugin_order <= (writeBack_FormalPlugin_order + 64'h0000000000000001);\n      end\n      writeBack_FormalPlugin_haltRequest_delay_1 <= writeBack_FormalPlugin_haltRequest;\n      writeBack_FormalPlugin_haltRequest_delay_2 <= writeBack_FormalPlugin_haltRequest_delay_1;\n      writeBack_FormalPlugin_haltRequest_delay_3 <= writeBack_FormalPlugin_haltRequest_delay_2;\n      writeBack_FormalPlugin_haltRequest_delay_4 <= writeBack_FormalPlugin_haltRequest_delay_3;\n      writeBack_FormalPlugin_haltRequest_delay_5 <= writeBack_FormalPlugin_haltRequest_delay_4;\n      if(when_FormalPlugin_l127) begin\n        writeBack_FormalPlugin_haltFired <= 1'b1;\n      end\n      if(IBusSimplePlugin_fetchPc_correction) begin\n        IBusSimplePlugin_fetchPc_correctionReg <= 1'b1;\n      end\n      if(IBusSimplePlugin_fetchPc_output_fire) begin\n        IBusSimplePlugin_fetchPc_correctionReg <= 1'b0;\n      end\n      IBusSimplePlugin_fetchPc_booted <= 1'b1;\n      if(when_Fetcher_l131) begin\n        IBusSimplePlugin_fetchPc_inc <= 1'b0;\n      end\n      if(IBusSimplePlugin_fetchPc_output_fire_1) begin\n        IBusSimplePlugin_fetchPc_inc <= 1'b1;\n      end\n      if(when_Fetcher_l131_1) begin\n        IBusSimplePlugin_fetchPc_inc <= 1'b0;\n      end\n      if(when_Fetcher_l158) begin\n        IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc;\n      end\n      if(when_Fetcher_l180) begin\n        IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_decodePc_pcPlus;\n      end\n      if(IBusSimplePlugin_decodePc_predictionPcLoad_valid) begin\n        IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_decodePc_predictionPcLoad_payload;\n      end\n      if(when_Fetcher_l192) begin\n        IBusSimplePlugin_decodePc_pcReg <= IBusSimplePlugin_jump_pcLoad_payload;\n      end\n      if(IBusSimplePlugin_iBusRsp_flush) begin\n        _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid <= 1'b0;\n      end\n      if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin\n        _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_valid <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0));\n      end\n      if(IBusSimplePlugin_decompressor_output_fire) begin\n        IBusSimplePlugin_decompressor_throw2BytesReg <= ((((! IBusSimplePlugin_decompressor_unaligned) && IBusSimplePlugin_decompressor_isInputLowRvc) && IBusSimplePlugin_decompressor_isInputHighRvc) || (IBusSimplePlugin_decompressor_bufferValid && IBusSimplePlugin_decompressor_isInputHighRvc));\n      end\n      if(when_Fetcher_l283) begin\n        IBusSimplePlugin_decompressor_bufferValid <= 1'b0;\n      end\n      if(when_Fetcher_l286) begin\n        if(IBusSimplePlugin_decompressor_bufferFill) begin\n          IBusSimplePlugin_decompressor_bufferValid <= 1'b1;\n        end\n      end\n      if(when_Fetcher_l291) begin\n        IBusSimplePlugin_decompressor_throw2BytesReg <= 1'b0;\n        IBusSimplePlugin_decompressor_bufferValid <= 1'b0;\n      end\n      if(decode_arbitration_removeIt) begin\n        _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0;\n      end\n      if(IBusSimplePlugin_decompressor_output_ready) begin\n        _zz_IBusSimplePlugin_injector_decodeInput_valid <= (IBusSimplePlugin_decompressor_output_valid && (! IBusSimplePlugin_externalFlush));\n      end\n      if(when_Fetcher_l329) begin\n        IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1;\n      end\n      if(IBusSimplePlugin_decodePc_flushed) begin\n        IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0;\n      end\n      if(when_Fetcher_l329_1) begin\n        IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0;\n      end\n      if(IBusSimplePlugin_decodePc_flushed) begin\n        IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0;\n      end\n      if(when_Fetcher_l329_2) begin\n        IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1;\n      end\n      if(IBusSimplePlugin_decodePc_flushed) begin\n        IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0;\n      end\n      if(when_Fetcher_l329_3) begin\n        IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2;\n      end\n      if(IBusSimplePlugin_decodePc_flushed) begin\n        IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0;\n      end\n      if(when_Fetcher_l617) begin\n        IBusSimplePlugin_decompressor_bufferValid <= 1'b0;\n        IBusSimplePlugin_decompressor_throw2BytesReg <= 1'b0;\n      end\n      IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next;\n      IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter);\n      if(IBusSimplePlugin_iBusRsp_flush) begin\n        IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2);\n      end\n      _zz_3 <= 1'b0;\n      HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;\n      if(when_Pipeline_l151) begin\n        execute_arbitration_isValid <= 1'b0;\n      end\n      if(when_Pipeline_l154) begin\n        execute_arbitration_isValid <= decode_arbitration_isValid;\n      end\n      if(when_Pipeline_l151_1) begin\n        memory_arbitration_isValid <= 1'b0;\n      end\n      if(when_Pipeline_l154_1) begin\n        memory_arbitration_isValid <= execute_arbitration_isValid;\n      end\n      if(when_Pipeline_l151_2) begin\n        writeBack_arbitration_isValid <= 1'b0;\n      end\n      if(when_Pipeline_l154_2) begin\n        writeBack_arbitration_isValid <= memory_arbitration_isValid;\n      end\n    end\n  end\n\n  always @(posedge clk) begin\n    if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin\n      _zz_IBusSimplePlugin_iBusRsp_stages_0_output_m2sPipe_payload <= IBusSimplePlugin_iBusRsp_stages_0_output_payload;\n    end\n    if(IBusSimplePlugin_decompressor_input_valid) begin\n      IBusSimplePlugin_decompressor_bufferValidLatch <= IBusSimplePlugin_decompressor_bufferValid;\n    end\n    if(IBusSimplePlugin_decompressor_input_valid) begin\n      IBusSimplePlugin_decompressor_throw2BytesLatch <= IBusSimplePlugin_decompressor_throw2Bytes;\n    end\n    if(when_Fetcher_l286) begin\n      IBusSimplePlugin_decompressor_bufferData <= IBusSimplePlugin_decompressor_input_payload_rsp_inst[31 : 16];\n    end\n    if(IBusSimplePlugin_decompressor_output_ready) begin\n      _zz_IBusSimplePlugin_injector_decodeInput_payload_pc <= IBusSimplePlugin_decompressor_output_payload_pc;\n      _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error <= IBusSimplePlugin_decompressor_output_payload_rsp_error;\n      _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_decompressor_output_payload_rsp_inst;\n      _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc <= IBusSimplePlugin_decompressor_output_payload_isRvc;\n    end\n    if(IBusSimplePlugin_injector_decodeInput_ready) begin\n      IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_decompressor_raw;\n    end\n    if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin\n      IBusSimplePlugin_predictor_writeLast_valid <= IBusSimplePlugin_predictor_historyWriteDelayPatched_valid;\n      IBusSimplePlugin_predictor_writeLast_payload_address <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_address;\n      IBusSimplePlugin_predictor_writeLast_payload_data_source <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_source;\n      IBusSimplePlugin_predictor_writeLast_payload_data_branchWish <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_branchWish;\n      IBusSimplePlugin_predictor_writeLast_payload_data_last2Bytes <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_last2Bytes;\n      IBusSimplePlugin_predictor_writeLast_payload_data_target <= IBusSimplePlugin_predictor_historyWriteDelayPatched_payload_data_target;\n    end\n    if(IBusSimplePlugin_iBusRsp_stages_0_input_ready) begin\n      IBusSimplePlugin_predictor_buffer_pcCorrected <= IBusSimplePlugin_fetchPc_corrected;\n    end\n    if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin\n      IBusSimplePlugin_predictor_line_source <= IBusSimplePlugin_predictor_buffer_line_source;\n      IBusSimplePlugin_predictor_line_branchWish <= IBusSimplePlugin_predictor_buffer_line_branchWish;\n      IBusSimplePlugin_predictor_line_last2Bytes <= IBusSimplePlugin_predictor_buffer_line_last2Bytes;\n      IBusSimplePlugin_predictor_line_target <= IBusSimplePlugin_predictor_buffer_line_target;\n    end\n    if(IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin\n      IBusSimplePlugin_predictor_buffer_hazard_regNextWhen <= IBusSimplePlugin_predictor_buffer_hazard;\n    end\n    if(IBusSimplePlugin_injector_decodeInput_ready) begin\n      IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hazard <= IBusSimplePlugin_predictor_iBusRspContextOutput_hazard;\n      IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_hit <= IBusSimplePlugin_predictor_iBusRspContextOutput_hit;\n      IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_source <= IBusSimplePlugin_predictor_iBusRspContextOutput_line_source;\n      IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_branchWish <= IBusSimplePlugin_predictor_iBusRspContextOutput_line_branchWish;\n      IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_last2Bytes <= IBusSimplePlugin_predictor_iBusRspContextOutput_line_last2Bytes;\n      IBusSimplePlugin_predictor_iBusRspContextOutput_delay_1_line_target <= IBusSimplePlugin_predictor_iBusRspContextOutput_line_target;\n    end\n    HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;\n    HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;\n    if(when_Pipeline_l124) begin\n      decode_to_execute_FORMAL_HALT <= _zz_when_FormalPlugin_l114_3;\n    end\n    if(when_Pipeline_l124_1) begin\n      execute_to_memory_FORMAL_HALT <= _zz_when_FormalPlugin_l114_2;\n    end\n    if(when_Pipeline_l124_2) begin\n      memory_to_writeBack_FORMAL_HALT <= _zz_when_FormalPlugin_l114_1;\n    end\n    if(when_Pipeline_l124_3) begin\n      decode_to_execute_PC <= _zz_decode_SRC2;\n    end\n    if(when_Pipeline_l124_4) begin\n      execute_to_memory_PC <= execute_PC;\n    end\n    if(when_Pipeline_l124_5) begin\n      memory_to_writeBack_PC <= memory_PC;\n    end\n    if(when_Pipeline_l124_6) begin\n      decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;\n    end\n    if(when_Pipeline_l124_7) begin\n      execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;\n    end\n    if(when_Pipeline_l124_8) begin\n      memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;\n    end\n    if(when_Pipeline_l124_9) begin\n      decode_to_execute_IS_RVC <= decode_IS_RVC;\n    end\n    if(when_Pipeline_l124_10) begin\n      execute_to_memory_IS_RVC <= execute_IS_RVC;\n    end\n    if(when_Pipeline_l124_11) begin\n      decode_to_execute_FORMAL_INSTRUCTION <= decode_FORMAL_INSTRUCTION;\n    end\n    if(when_Pipeline_l124_12) begin\n      execute_to_memory_FORMAL_INSTRUCTION <= execute_FORMAL_INSTRUCTION;\n    end\n    if(when_Pipeline_l124_13) begin\n      memory_to_writeBack_FORMAL_INSTRUCTION <= memory_FORMAL_INSTRUCTION;\n    end\n    if(when_Pipeline_l124_14) begin\n      decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT;\n    end\n    if(when_Pipeline_l124_15) begin\n      execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT;\n    end\n    if(when_Pipeline_l124_16) begin\n      memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT;\n    end\n    if(when_Pipeline_l124_17) begin\n      decode_to_execute_PREDICTION_CONTEXT_hazard <= decode_PREDICTION_CONTEXT_hazard;\n      decode_to_execute_PREDICTION_CONTEXT_hit <= decode_PREDICTION_CONTEXT_hit;\n      decode_to_execute_PREDICTION_CONTEXT_line_source <= decode_PREDICTION_CONTEXT_line_source;\n      decode_to_execute_PREDICTION_CONTEXT_line_branchWish <= decode_PREDICTION_CONTEXT_line_branchWish;\n      decode_to_execute_PREDICTION_CONTEXT_line_last2Bytes <= decode_PREDICTION_CONTEXT_line_last2Bytes;\n      decode_to_execute_PREDICTION_CONTEXT_line_target <= decode_PREDICTION_CONTEXT_line_target;\n    end\n    if(when_Pipeline_l124_18) begin\n      execute_to_memory_PREDICTION_CONTEXT_hazard <= execute_PREDICTION_CONTEXT_hazard;\n      execute_to_memory_PREDICTION_CONTEXT_hit <= execute_PREDICTION_CONTEXT_hit;\n      execute_to_memory_PREDICTION_CONTEXT_line_source <= execute_PREDICTION_CONTEXT_line_source;\n      execute_to_memory_PREDICTION_CONTEXT_line_branchWish <= execute_PREDICTION_CONTEXT_line_branchWish;\n      execute_to_memory_PREDICTION_CONTEXT_line_last2Bytes <= execute_PREDICTION_CONTEXT_line_last2Bytes;\n      execute_to_memory_PREDICTION_CONTEXT_line_target <= execute_PREDICTION_CONTEXT_line_target;\n    end\n    if(when_Pipeline_l124_19) begin\n      decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;\n    end\n    if(when_Pipeline_l124_20) begin\n      decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;\n    end\n    if(when_Pipeline_l124_21) begin\n      execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;\n    end\n    if(when_Pipeline_l124_22) begin\n      memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;\n    end\n    if(when_Pipeline_l124_23) begin\n      decode_to_execute_RS1_USE <= decode_RS1_USE;\n    end\n    if(when_Pipeline_l124_24) begin\n      execute_to_memory_RS1_USE <= execute_RS1_USE;\n    end\n    if(when_Pipeline_l124_25) begin\n      memory_to_writeBack_RS1_USE <= memory_RS1_USE;\n    end\n    if(when_Pipeline_l124_26) begin\n      decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;\n    end\n    if(when_Pipeline_l124_27) begin\n      decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;\n    end\n    if(when_Pipeline_l124_28) begin\n      execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;\n    end\n    if(when_Pipeline_l124_29) begin\n      memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;\n    end\n    if(when_Pipeline_l124_30) begin\n      decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;\n    end\n    if(when_Pipeline_l124_31) begin\n      decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;\n    end\n    if(when_Pipeline_l124_32) begin\n      execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;\n    end\n    if(when_Pipeline_l124_33) begin\n      decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE;\n    end\n    if(when_Pipeline_l124_34) begin\n      execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE;\n    end\n    if(when_Pipeline_l124_35) begin\n      decode_to_execute_RS2_USE <= decode_RS2_USE;\n    end\n    if(when_Pipeline_l124_36) begin\n      execute_to_memory_RS2_USE <= execute_RS2_USE;\n    end\n    if(when_Pipeline_l124_37) begin\n      memory_to_writeBack_RS2_USE <= memory_RS2_USE;\n    end\n    if(when_Pipeline_l124_38) begin\n      decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;\n    end\n    if(when_Pipeline_l124_39) begin\n      decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;\n    end\n    if(when_Pipeline_l124_40) begin\n      decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;\n    end\n    if(when_Pipeline_l124_41) begin\n      execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;\n    end\n    if(when_Pipeline_l124_42) begin\n      decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;\n    end\n    if(when_Pipeline_l124_43) begin\n      decode_to_execute_RS1 <= _zz_decode_SRC1;\n    end\n    if(when_Pipeline_l124_44) begin\n      execute_to_memory_RS1 <= execute_RS1;\n    end\n    if(when_Pipeline_l124_45) begin\n      memory_to_writeBack_RS1 <= memory_RS1;\n    end\n    if(when_Pipeline_l124_46) begin\n      decode_to_execute_RS2 <= _zz_decode_SRC2_1;\n    end\n    if(when_Pipeline_l124_47) begin\n      execute_to_memory_RS2 <= execute_RS2;\n    end\n    if(when_Pipeline_l124_48) begin\n      memory_to_writeBack_RS2 <= memory_RS2;\n    end\n    if(when_Pipeline_l124_49) begin\n      decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;\n    end\n    if(when_Pipeline_l124_50) begin\n      decode_to_execute_SRC1 <= decode_SRC1;\n    end\n    if(when_Pipeline_l124_51) begin\n      decode_to_execute_SRC2 <= decode_SRC2;\n    end\n    if(when_Pipeline_l124_52) begin\n      execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT;\n    end\n    if(when_Pipeline_l124_53) begin\n      execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;\n    end\n    if(when_Pipeline_l124_54) begin\n      memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW;\n    end\n    if(when_Pipeline_l124_55) begin\n      execute_to_memory_FORMAL_MEM_ADDR <= execute_FORMAL_MEM_ADDR;\n    end\n    if(when_Pipeline_l124_56) begin\n      memory_to_writeBack_FORMAL_MEM_ADDR <= memory_FORMAL_MEM_ADDR;\n    end\n    if(when_Pipeline_l124_57) begin\n      execute_to_memory_FORMAL_MEM_WMASK <= execute_FORMAL_MEM_WMASK;\n    end\n    if(when_Pipeline_l124_58) begin\n      memory_to_writeBack_FORMAL_MEM_WMASK <= memory_FORMAL_MEM_WMASK;\n    end\n    if(when_Pipeline_l124_59) begin\n      execute_to_memory_FORMAL_MEM_RMASK <= execute_FORMAL_MEM_RMASK;\n    end\n    if(when_Pipeline_l124_60) begin\n      memory_to_writeBack_FORMAL_MEM_RMASK <= memory_FORMAL_MEM_RMASK;\n    end\n    if(when_Pipeline_l124_61) begin\n      execute_to_memory_FORMAL_MEM_WDATA <= execute_FORMAL_MEM_WDATA;\n    end\n    if(when_Pipeline_l124_62) begin\n      memory_to_writeBack_FORMAL_MEM_WDATA <= memory_FORMAL_MEM_WDATA;\n    end\n    if(when_Pipeline_l124_63) begin\n      execute_to_memory_REGFILE_WRITE_DATA <= execute_REGFILE_WRITE_DATA;\n    end\n    if(when_Pipeline_l124_64) begin\n      memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_memory_to_writeBack_REGFILE_WRITE_DATA;\n    end\n    if(when_Pipeline_l124_65) begin\n      execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;\n    end\n    if(when_Pipeline_l124_66) begin\n      execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;\n    end\n    if(when_Pipeline_l124_67) begin\n      execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC;\n    end\n    if(when_Pipeline_l124_68) begin\n      execute_to_memory_NEXT_PC2 <= execute_NEXT_PC2;\n    end\n    if(when_Pipeline_l124_69) begin\n      execute_to_memory_TARGET_MISSMATCH2 <= execute_TARGET_MISSMATCH2;\n    end\n    if(when_Pipeline_l124_70) begin\n      memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA;\n    end\n  end\n\n\nendmodule\n\nmodule StreamFifoLowLatency (\n  input               io_push_valid,\n  output              io_push_ready,\n  input               io_push_payload_error,\n  input      [31:0]   io_push_payload_inst,\n  output reg          io_pop_valid,\n  input               io_pop_ready,\n  output reg          io_pop_payload_error,\n  output reg [31:0]   io_pop_payload_inst,\n  input               io_flush,\n  output     [0:0]    io_occupancy,\n  input               clk,\n  input               reset\n);\n\n  reg                 when_Phase_l623;\n  reg                 pushPtr_willIncrement;\n  reg                 pushPtr_willClear;\n  wire                pushPtr_willOverflowIfInc;\n  wire                pushPtr_willOverflow;\n  reg                 popPtr_willIncrement;\n  reg                 popPtr_willClear;\n  wire                popPtr_willOverflowIfInc;\n  wire                popPtr_willOverflow;\n  wire                ptrMatch;\n  reg                 risingOccupancy;\n  wire                empty;\n  wire                full;\n  wire                pushing;\n  wire                popping;\n  wire                readed_error;\n  wire       [31:0]   readed_inst;\n  wire       [32:0]   _zz_readed_error;\n  wire                when_Stream_l1019;\n  wire                when_Stream_l1032;\n  wire       [32:0]   _zz_readed_error_1;\n  reg        [32:0]   _zz_readed_error_2;\n\n  always @(*) begin\n    when_Phase_l623 = 1'b0;\n    if(pushing) begin\n      when_Phase_l623 = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    pushPtr_willIncrement = 1'b0;\n    if(pushing) begin\n      pushPtr_willIncrement = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    pushPtr_willClear = 1'b0;\n    if(io_flush) begin\n      pushPtr_willClear = 1'b1;\n    end\n  end\n\n  assign pushPtr_willOverflowIfInc = 1'b1;\n  assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);\n  always @(*) begin\n    popPtr_willIncrement = 1'b0;\n    if(popping) begin\n      popPtr_willIncrement = 1'b1;\n    end\n  end\n\n  always @(*) begin\n    popPtr_willClear = 1'b0;\n    if(io_flush) begin\n      popPtr_willClear = 1'b1;\n    end\n  end\n\n  assign popPtr_willOverflowIfInc = 1'b1;\n  assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);\n  assign ptrMatch = 1'b1;\n  assign empty = (ptrMatch && (! risingOccupancy));\n  assign full = (ptrMatch && risingOccupancy);\n  assign pushing = (io_push_valid && io_push_ready);\n  assign popping = (io_pop_valid && io_pop_ready);\n  assign io_push_ready = (! full);\n  assign _zz_readed_error = _zz_readed_error_1;\n  assign readed_error = _zz_readed_error[0];\n  assign readed_inst = _zz_readed_error[32 : 1];\n  assign when_Stream_l1019 = (! empty);\n  always @(*) begin\n    if(when_Stream_l1019) begin\n      io_pop_valid = 1'b1;\n    end else begin\n      io_pop_valid = io_push_valid;\n    end\n  end\n\n  always @(*) begin\n    if(when_Stream_l1019) begin\n      io_pop_payload_error = readed_error;\n    end else begin\n      io_pop_payload_error = io_push_payload_error;\n    end\n  end\n\n  always @(*) begin\n    if(when_Stream_l1019) begin\n      io_pop_payload_inst = readed_inst;\n    end else begin\n      io_pop_payload_inst = io_push_payload_inst;\n    end\n  end\n\n  assign when_Stream_l1032 = (pushing != popping);\n  assign io_occupancy = (risingOccupancy && ptrMatch);\n  assign _zz_readed_error_1 = _zz_readed_error_2;\n  always @(posedge clk) begin\n    if(reset) begin\n      risingOccupancy <= 1'b0;\n    end else begin\n      if(when_Stream_l1032) begin\n        risingOccupancy <= pushing;\n      end\n      if(io_flush) begin\n        risingOccupancy <= 1'b0;\n      end\n    end\n  end\n\n  always @(posedge clk) begin\n    if(when_Phase_l623) begin\n      _zz_readed_error_2 <= {io_push_payload_inst,io_push_payload_error};\n    end\n  end\n\n\nendmodule\n"
  },
  {
    "path": "cores/VexRiscv/checks.cfg",
    "content": "\n[options]\nisa rv32i\n\n[depth]\ninsn            20\nreg       15    30\npc_fwd    10    30\npc_bwd    10    30\nliveness  1  10 30\nunique    1  10 30\ncausal    10    30\n\n[defines]\n`define RISCV_FORMAL_ALIGNED_MEM\n`define RISCV_FORMAL_ALTOPS\n`define DEBUGNETS\n\n[defines liveness]\n`define VEXRISCV_FAIRNESS\n\n[verilog-files]\n@basedir@/cores/@core@/wrapper.sv\n@basedir@/cores/@core@/@core@.v\n"
  },
  {
    "path": "cores/VexRiscv/disasm.py",
    "content": "#!/usr/bin/env python3\n\nfrom Verilog_VCD.Verilog_VCD import parse_vcd\nfrom os import system\nfrom sys import argv\n\nrvfi_valid = None\nrvfi_order = None\nrvfi_insn = None\n\nfor netinfo in parse_vcd(argv[1]).values():\n    for net in netinfo['nets']:\n        # print(net[\"hier\"], net[\"name\"])\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_valid\":\n            rvfi_valid = netinfo['tv']\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_order\":\n            rvfi_order = netinfo['tv']\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_insn\":\n            rvfi_insn = netinfo['tv']\n\nassert len(rvfi_valid) == len(rvfi_order)\nassert len(rvfi_valid) == len(rvfi_insn)\n\nprog = list()\n\nfor tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn):\n    if tv_valid[1] == '1':\n        prog.append((int(tv_order[1], 2), int(tv_insn[1], 2)))\n\nwith open(\"disasm.s\", \"w\") as f:\n    for tv_order, tv_insn in sorted(prog):\n        if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0:\n            print(\".hword 0x%04x # %d\" % (tv_insn, tv_order), file=f)\n        else:\n            print(\".word 0x%08x # %d\" % (tv_insn, tv_order), file=f)\n\nsystem(\"riscv64-unknown-elf-gcc -c disasm.s\")\nsystem(\"riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o\")\n\n"
  },
  {
    "path": "cores/VexRiscv/dmemcheck.sby",
    "content": "[options]\nmode bmc\nappend 0\ntbtop testbench.uut\ndepth 22\n\n[engines]\nsmtbmc --presat --unroll boolector\n\n[script]\nread_verilog -sv dmemcheck.sv\nread_verilog ../../VexRiscv.v\nprep -nordff -top testbench\n\n[files]\ndmemcheck.sv\n../../checks/rvfi_macros.vh\n../../checks/rvfi_channel.sv\n../../checks/rvfi_testbench.sv\n../../checks/rvfi_dmem_check.sv\n\n"
  },
  {
    "path": "cores/VexRiscv/dmemcheck.sv",
    "content": "`define RISCV_FORMAL\n`define RISCV_FORMAL_NRET 1\n`define RISCV_FORMAL_XLEN 32\n`define RISCV_FORMAL_ILEN 32\n`define RISCV_FORMAL_ALIGNED_MEM\n`include \"rvfi_macros.vh\"\n`include \"rvfi_channel.sv\"\n`include \"rvfi_dmem_check.sv\"\n\nmodule testbench (\n\tinput clk\n);\n\treg reset = 1;\n\n\talways @(posedge clk)\n\t\treset <= 0;\n\n\n\n\n\t(* keep *) wire        iBus_cmd_valid;\n\t(* keep *) wire [31:0] iBus_cmd_payload_pc;\n\t(* keep *) `rvformal_rand_reg iBus_cmd_ready;\n\t(* keep *) `rvformal_rand_reg iBus_rsp_ready;\n\t(* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst;\n\n\n\t(* keep *) wire  dBus_cmd_valid;\n\t(* keep *) wire  dBus_cmd_payload_wr;\n\t(* keep *) wire [31:0] dBus_cmd_payload_address;\n\t(* keep *) wire [31:0] dBus_cmd_payload_data;\n\t(* keep *) wire [1:0] dBus_cmd_payload_size;\n\t(* keep *) `rvformal_rand_reg dBus_cmd_ready;\n\t(* keep *) `rvformal_rand_reg    dBus_rsp_ready;\n\t(* keep *) `rvformal_rand_reg   [31:0] dBus_rsp_data;\n\n\n\t`RVFI_WIRES\n\n\t(* keep *) wire [31:0] dmem_addr;\n\t(* keep *) reg [31:0] dmem_data;\n\n\trvfi_dmem_check checker_inst (\n\t\t.clock     (clk      ),\n\t\t.reset     (reset  ),\n\t\t.enable    (1'b1     ),\n\t\t.dmem_addr (dmem_addr),\n\t\t`RVFI_CONN\n\t);\n\n\t(* keep *) reg dmem_last_valid;\n\t(* keep *) wire [3:0] dBus_cmd_payload_mask;\n\n\tassign dBus_cmd_payload_mask = ((1 << (1 << dBus_cmd_payload_size))-1) << dBus_cmd_payload_address[1:0];\n\n\t\n\n\n\talways @(posedge clk) begin\n\t\tif (reset) begin\n\t\t\tdmem_last_valid <= 0;\n\t\tend else begin\n\t\t\tif(dmem_last_valid) begin\n\t\t\t\tassume(dBus_rsp_data == dmem_data);\n\t\t\tend\n\t\t\tif(dBus_rsp_ready) begin\n\t\t\t\tdmem_last_valid <= 0;\n\t\t\tend\n\t\t\tif(dBus_cmd_valid && dBus_cmd_ready) begin\n\t\t\t\tif((dBus_cmd_payload_address >> 2) == (dmem_addr >> 2)) begin\n\t\t\t\t\tif(!dBus_cmd_payload_wr) begin\n\t\t\t\t\t\tdmem_last_valid <= 1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tif (dBus_cmd_payload_mask[0]) dmem_data[ 7: 0] <= dBus_cmd_payload_data[ 7: 0];\n\t\t\t\t\t\tif (dBus_cmd_payload_mask[1]) dmem_data[15: 8] <= dBus_cmd_payload_data[15: 8];\n\t\t\t\t\t\tif (dBus_cmd_payload_mask[2]) dmem_data[23:16] <= dBus_cmd_payload_data[23:16];\n\t\t\t\t\t\tif (dBus_cmd_payload_mask[3]) dmem_data[31:24] <= dBus_cmd_payload_data[31:24];\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\t\t\n\t\tend\n\t\t\n\tend\n\n\n\n\n\n\tVexRiscv uut (\n\t\t.clk       (clk    ),\n\t\t.reset    (reset   ),\n\n\t\t.iBus_cmd_valid (iBus_cmd_valid),\n\t\t.iBus_cmd_ready (iBus_cmd_ready),\n\t\t.iBus_cmd_payload_pc  (iBus_cmd_payload_pc ),\n\t\t.iBus_rsp_ready(iBus_rsp_ready),\n\t\t.iBus_rsp_inst (iBus_rsp_inst),\n\t\t.iBus_rsp_error(1'b0),\n\n\t\t.dBus_cmd_valid(dBus_cmd_valid),\n\t\t.dBus_cmd_payload_wr(dBus_cmd_payload_wr),\n\t\t.dBus_cmd_payload_address(dBus_cmd_payload_address),\n\t\t.dBus_cmd_payload_data(dBus_cmd_payload_data),\n\t\t.dBus_cmd_payload_size(dBus_cmd_payload_size),\n\t\t.dBus_cmd_ready(dBus_cmd_ready),\n\t\t.dBus_rsp_ready(dBus_rsp_ready),\n\t\t.dBus_rsp_data(dBus_rsp_data),\n\t\t.dBus_rsp_error(1'b0),\n\n\t\t`RVFI_CONN\n\t);\n\nendmodule\n\n"
  },
  {
    "path": "cores/VexRiscv/imemcheck.sby",
    "content": "[options]\nmode bmc\nappend 0\ntbtop testbench.uut\ndepth 22\n\n[engines]\nsmtbmc --presat --unroll boolector\n\n[script]\nread_verilog -sv imemcheck.sv\nread_verilog ../../VexRiscv.v\nprep -nordff -top testbench\n\n[files]\nimemcheck.sv\n../../checks/rvfi_macros.vh\n../../checks/rvfi_channel.sv\n../../checks/rvfi_testbench.sv\n../../checks/rvfi_imem_check.sv\n"
  },
  {
    "path": "cores/VexRiscv/imemcheck.sv",
    "content": "`define RISCV_FORMAL\n`define RISCV_FORMAL_NRET 1\n`define RISCV_FORMAL_XLEN 32\n`define RISCV_FORMAL_ILEN 32\n`include \"rvfi_macros.vh\"\n`include \"rvfi_channel.sv\"\n`include \"rvfi_imem_check.sv\"\n\nmodule testbench (\n\tinput clk\n);\n\treg reset = 1;\n\n\talways @(posedge clk)\n\t\treset <= 0;\n\n\n\n\n\t(* keep *) wire        iBus_cmd_valid;\n\t(* keep *) wire [31:0] iBus_cmd_payload_pc;\n\t(* keep *) `rvformal_rand_reg iBus_cmd_ready;\n\t(* keep *) `rvformal_rand_reg iBus_rsp_ready;\n\t(* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst;\n\n\n\t(* keep *) wire  dBus_cmd_valid;\n\t(* keep *) wire  dBus_cmd_payload_wr;\n\t(* keep *) wire [31:0] dBus_cmd_payload_address;\n\t(* keep *) wire [31:0] dBus_cmd_payload_data;\n\t(* keep *) wire [1:0] dBus_cmd_payload_size;\n\t(* keep *) `rvformal_rand_reg dBus_cmd_ready;\n\t(* keep *) `rvformal_rand_reg    dBus_rsp_ready;\n\t(* keep *) `rvformal_rand_reg   [31:0] dBus_rsp_data;\n\n\n\n\t`RVFI_WIRES\n\n\t(* keep *) wire [31:0] imem_addr;\n\t(* keep *) wire [15:0] imem_data;\n\n\trvfi_imem_check checker_inst (\n\t\t.clock     (clk      ),\n\t\t.reset     (reset  ),\n\t\t.enable    (1'b1     ),\n\t\t.imem_addr (imem_addr),\n\t\t.imem_data (imem_data),\n\t\t`RVFI_CONN\n\t);\n\n\t(* keep *) wire imem_last_valid;\n\t(* keep *) wire [31:0] imem_last_addr;\n\n\talways @(posedge clk) begin\n\t\tif (reset) begin\n\t\t\timem_last_valid <= 0;\n\t\tend else begin\n\t\t\tif(imem_last_valid) begin\n\t\t\t\tif (imem_last_addr == imem_addr)\n\t\t\t\t\tassume(iBus_rsp_inst[15:0] == imem_data);\n\t\t\t\tif (imem_last_addr+2 == imem_addr)\n\t\t\t\t\tassume(iBus_rsp_inst[31:16] == imem_data);\n\t\t\tend\n\t\t\tif(iBus_rsp_ready) begin\n\t\t\t\timem_last_valid <= 0;\n\t\t\tend\n\t\t\tif(iBus_cmd_valid && iBus_cmd_ready) begin\n\t\t\t\timem_last_valid <= 1;\n\t\t\t\timem_last_addr <= iBus_cmd_payload_pc;\n\t\t\tend\n\t\tend\n\t\t\n\tend\n\n\n\n\n\n\tVexRiscv uut (\n\t\t.clk       (clk    ),\n\t\t.reset    (reset   ),\n\n\t\t.iBus_cmd_valid (iBus_cmd_valid),\n\t\t.iBus_cmd_ready (iBus_cmd_ready),\n\t\t.iBus_cmd_payload_pc  (iBus_cmd_payload_pc ),\n\t\t.iBus_rsp_ready(iBus_rsp_ready),\n\t\t.iBus_rsp_inst (iBus_rsp_inst),\n\t\t.iBus_rsp_error(1'b0),\n\n\t\t.dBus_cmd_valid(dBus_cmd_valid),\n\t\t.dBus_cmd_payload_wr(dBus_cmd_payload_wr),\n\t\t.dBus_cmd_payload_address(dBus_cmd_payload_address),\n\t\t.dBus_cmd_payload_data(dBus_cmd_payload_data),\n\t\t.dBus_cmd_payload_size(dBus_cmd_payload_size),\n\t\t.dBus_cmd_ready(dBus_cmd_ready),\n\t\t.dBus_rsp_ready(dBus_rsp_ready),\n\t\t.dBus_rsp_data(dBus_rsp_data),\n\t\t.dBus_rsp_error(1'b0),\n\n\t\t`RVFI_CONN\n\t);\n\nendmodule\n\n"
  },
  {
    "path": "cores/VexRiscv/wrapper.sv",
    "content": "module rvfi_wrapper (\n\tinput         clock,\n\tinput         reset,\n\t`RVFI_OUTPUTS\n);\n\t(* keep *) wire trap;\n\n\n\t(* keep *) wire        iBus_cmd_valid;\n\t(* keep *) wire [31:0] iBus_cmd_payload_pc;\n\t(* keep *) `rvformal_rand_reg iBus_cmd_ready;\n\t(* keep *) `rvformal_rand_reg iBus_rsp_ready;\n\t(* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst;\n\n\n\t(* keep *) wire  dBus_cmd_valid;\n\t(* keep *) wire  dBus_cmd_payload_wr;\n\t(* keep *) wire [31:0] dBus_cmd_payload_address;\n\t(* keep *) wire [31:0] dBus_cmd_payload_data;\n\t(* keep *) wire [1:0] dBus_cmd_payload_size;\n\t(* keep *) `rvformal_rand_reg dBus_cmd_ready;\n\t(* keep *) `rvformal_rand_reg    dBus_rsp_ready;\n\t(* keep *) `rvformal_rand_reg   [31:0] dBus_rsp_data;\n\n\n\n\n\tVexRiscv uut (\n\t\t.clk       (clock    ),\n\t\t.reset    (reset   ),\n\n\t\t.iBus_cmd_valid (iBus_cmd_valid),\n\t\t.iBus_cmd_ready (iBus_cmd_ready),\n\t\t.iBus_cmd_payload_pc  (iBus_cmd_payload_pc ),\n\t\t.iBus_rsp_valid(iBus_rsp_ready),\n\t\t.iBus_rsp_payload_inst(iBus_rsp_inst),\n\t\t.iBus_rsp_payload_error(1'b0),\n\n\t\t.dBus_cmd_valid(dBus_cmd_valid),\n\t\t.dBus_cmd_payload_wr(dBus_cmd_payload_wr),\n\t\t.dBus_cmd_payload_address(dBus_cmd_payload_address),\n\t\t.dBus_cmd_payload_data(dBus_cmd_payload_data),\n\t\t.dBus_cmd_payload_size(dBus_cmd_payload_size),\n\t\t.dBus_cmd_ready(dBus_cmd_ready),\n\t\t.dBus_rsp_ready(dBus_rsp_ready),\n\t\t.dBus_rsp_data(dBus_rsp_data),\n\t\t.dBus_rsp_error(1'b0),\n\n\t\t`RVFI_CONN\n\t);\n\n`ifdef VEXRISCV_FAIRNESS\n\t(* keep *) reg [2:0] iBusCmdPendingCycles = 0;\n\t(* keep *) reg [2:0] iBusRspPendingCycles = 0;\n\t(* keep *) reg       iBusRspPendingValid = 0;\n\t(* keep *) reg [2:0] dBusCmdPendingCycles = 0;\n\t(* keep *) reg [2:0] dBusRspPendingCycles = 0;\n\t(* keep *) reg       dBusRspPendingValid = 0;\n\talways @(posedge clock) begin\n\t\tif(iBus_cmd_valid && !iBus_cmd_ready) begin\n\t\t\tiBusCmdPendingCycles <= iBusCmdPendingCycles + 1;\n\t\tend else begin\n\t\t\tiBusCmdPendingCycles <= 0;\n\t\tend\n\n\t\tif(iBusRspPendingValid <= 1) begin\n\t\t\tiBusRspPendingCycles <= iBusRspPendingCycles + 1;\n\t\tend\n\t\tif(iBus_rsp_ready) begin\n\t\t\tiBusRspPendingValid <= 0;\n\t\t\tiBusRspPendingCycles <= 0;\n\t\tend\n\t\tif(iBus_cmd_valid && iBus_cmd_ready && !dBus_cmd_payload_wr) begin\n\t\t\tiBusRspPendingValid <= 1;\n\t\tend\n\n\t\tif(dBus_cmd_valid && !dBus_cmd_ready) begin\n\t\t\tdBusCmdPendingCycles <= dBusCmdPendingCycles + 1;\n\t\tend else begin\n\t\t\tdBusCmdPendingCycles <= 0;\n\t\tend\n\n\t\tif(dBusRspPendingValid <= 1) begin\n\t\t\tdBusRspPendingCycles <= dBusRspPendingCycles + 1;\n\t\tend\n\t\tif(dBus_rsp_ready) begin\n\t\t\tdBusRspPendingValid <= 0;\n\t\t\tdBusRspPendingCycles <= 0;\n\t\tend\n\t\tif(dBus_cmd_valid && dBus_cmd_ready && !dBus_cmd_payload_wr) begin\n\t\t\tdBusRspPendingValid <= 1;\n\t\tend\n\t\trestrict property(~rvfi_trap && dBusCmdPendingCycles < 4 && dBusRspPendingCycles < 4 && iBusCmdPendingCycles < 4 && iBusRspPendingCycles < 4);\n\tend\n`endif\nendmodule\n\n"
  },
  {
    "path": "cores/nerv/.gitignore",
    "content": "/checks/\n/cexdata/\n/testbench.vcd\n/firmware.elf\n/firmware.hex\n/disasm.o\n/disasm.s\n/testbench\n/gtkwave.log\n"
  },
  {
    "path": "cores/nerv/COPYING",
    "content": "NERV -- Naive Educational RISC-V Processor\n\nCopyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\nCopyright (C) 2020  N. Engelhardt <nak@yosyshq.com>\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\nANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\nACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\nOR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n"
  },
  {
    "path": "cores/nerv/Makefile",
    "content": "#  NERV -- Naive Educational RISC-V Processor\n#\n#  Copyright (C) 2020  N. Engelhardt <nak@yosyshq.com>\n#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n#\n#  Permission to use, copy, modify, and/or distribute this software for any\n#  purpose with or without fee is hereby granted, provided that the above\n#  copyright notice and this permission notice appear in all copies.\n#\n#  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nTOOLCHAIN_PREFIX?=riscv64-unknown-elf-\n\nRISCV_ARCH?=rv32i$(shell $(TOOLCHAIN_PREFIX)as -march=rv32i_zicsr --dump-config 2>/dev/null && echo _zicsr)\n\ntest: firmware.hex testbench\n\tvvp -N testbench +vcd\n\nfirmware.elf: firmware.s vectors.s firmware.c\n\t$(TOOLCHAIN_PREFIX)gcc -march=$(RISCV_ARCH) -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $^\n\nfirmware.hex: firmware.elf\n\t$(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@\n\ntestbench: testbench.sv nerv.sv\n\tiverilog -g2012 -o testbench -D STALL -D NERV_DBGREGS testbench.sv nerv.sv\n\nchecks:\n\tpython3 ../../checks/genchecks.py\n\t$(MAKE) -C checks\n\ncheck: checks\n\tbash cexdata.sh\n\tcat cexdata/warnings.txt\n\tcat cexdata/status.txt\n\nshow:\n\tgtkwave testbench.vcd testbench.gtkw >> gtkwave.log 2>&1 &\n\ntrace:\n\tgtkwave cexdata/checks_$(TRACE_CHECK)_ch0.vcd trace.gtkw >> gtkwave.log 2>&1 &\n\nclean:\n\trm -rf firmware.elf firmware.hex testbench testbench.vcd gtkwave.log\n\trm -rf disasm.o disasm.s checks/ cexdata/\n"
  },
  {
    "path": "cores/nerv/README.md",
    "content": "NERV - Naive Educational RISC-V Processor\n=========================================\n\nNERV is a very simple single-stage RV32I processor. \nIt is equipped with an [RVFI interface](https://github.com/yosyshq/riscv-formal/blob/master/docs/rvfi.md) and is formally verified.\n\n![system diagram](NERV.png)\n\nRunning the simulation testbench\n--------------------------------\n\n```\ngit clone https://github.com/yosyshq/nerv.git\ncd nerv\nmake\n```\n\n\nRunning the riscv-formal testbench\n----------------------------------\n\n```\ngit clone https://github.com/yosyshq/riscv-formal.git\ncd riscv-formal/cores/nerv\nmake -j8 check\n```\n\nUpdating riscv-formal's included nerv core\n------------------------------------------\n\nFrom root `riscv-formal` directory:\n\n```\ngit subtree pull --prefix cores/nerv git@github.com:YosysHQ/nerv.git main --squash\n```\n\nUpdating upstream nerv with changes from riscv-formal\n-----------------------------------------------------\n\nFrom root `riscv-formal` directory:\n\n```\ngit subtree push --prefix cores/nerv git@github.com:YosysHQ/nerv.git main\n```\n\niCEBreaker SOC example\n----------------------\n\nSee the [iCEBreaker SOC README](examples/icebreaker/README.md)\n"
  },
  {
    "path": "cores/nerv/axi_cache/.gitignore",
    "content": "/SVA-AXI4-FVIP\n/checks_axi\n/checks_internal\n*.vcd\n*.hex\n*.elf\ntestbench_internal\ntestbench_axi\n"
  },
  {
    "path": "cores/nerv/axi_cache/Makefile",
    "content": "#  NERV -- Naive Educational RISC-V Processor\n#\n#  Copyright (C) 2020  N. Engelhardt <nak@yosyshq.com>\n#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n#  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n#\n#  Permission to use, copy, modify, and/or distribute this software for any\n#  purpose with or without fee is hereby granted, provided that the above\n#  copyright notice and this permission notice appear in all copies.\n#\n#  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nTOOLCHAIN_PREFIX?=riscv64-unknown-elf-\n\nTESTBENCH_DEFINES?=-D NERV_DBGREGS -D NERV_CSR\nTESTBENCH_ARGS?=+vcd\nCHECKS?=\n\nCLONE?=0\n\nRISCV_ARCH?=rv32i$(shell $(TOOLCHAIN_PREFIX)as -march=rv32i_zicsr --dump-config 2>/dev/null && echo _zicsr)\n\nCACHE_SOURCES:=nerv_axi_cache.sv nerv_axi_cache_icache.sv nerv_axi_cache_dcache.sv\n\n.PHONY: test_internal test_axi verify_axi verify_axi_cover checks_internal checks_axi all\n\ntest_internal: firmware.hex testbench_internal\n\tvvp -N testbench_internal $(TESTBENCH_ARGS)\n\ntest_axi: firmware.hex testbench_axi\n\tvvp -N testbench_axi $(TESTBENCH_ARGS)\n\nverify_axi: SVA-AXI4-FVIP verify_axi.sby verify_axi.sv\n\tsby -f verify_axi.sby prove\n\nverify_axi_cover: SVA-AXI4-FVIP verify_axi.sby verify_axi.sv\n\tsby -f verify_axi.sby cover\n\nfirmware.elf: ../firmware.s ../vectors.s firmware.c\n\t$(TOOLCHAIN_PREFIX)gcc -march=$(RISCV_ARCH) -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $^\n\nfirmware.hex: firmware.elf\n\t$(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@\n\ntestbench_internal: testbench_internal.sv ../nerv.sv $(CACHE_SOURCES)\n\tiverilog -stestbench -g2012 -o $@ $(TESTBENCH_DEFINES) $^\n\ntestbench_axi: testbench_axi.sv ../nerv.sv $(CACHE_SOURCES) axi_ram.v\n\tiverilog -stestbench -g2012 -o $@ $(TESTBENCH_DEFINES) $^\n\nifeq ($(CLONE),1)\nSVA-AXI4-FVIP:\n\tgit clone https://github.com/YosysHQ-GmbH/SVA-AXI4-FVIP\nelse\nSVA-AXI4-FVIP:\n\t@echo \"SVA-AXI4-FVIP repository not found, use 'make SVA-AXI4-FVIP CLONE=1' to clone from GitHub\"\n\t@echo \"alternatively manually clone or symlink a clone of https://github.com/YosysHQ-GmbH/SVA-AXI4-FVIP\"\n\t@exit 1\nendif\n\nchecks_internal:\n\tcd .. && python3 ../../checks/genchecks.py axi_cache/checks_internal\n\t$(MAKE) -C checks_internal $(CHECKS)\n\nchecks_axi:\n\tcd .. && python3 ../../checks/genchecks.py axi_cache/checks_axi\n\t$(MAKE) -C checks_axi $(CHECKS)\n\nall: test_internal test_axi verify_axi verify_axi_cover checks_internal checks_axi\n\nclean:\n\trm -rf firmware.elf firmware.hex\n\trm -rf testbench_internal testbench_internal.vcd\n\trm -rf testbench_axi testbench_axi.vcd\n\trm -rf verify_axi_prove verify_axi_cover\n\trm -rf checks_internal checks_axi\n"
  },
  {
    "path": "cores/nerv/axi_cache/README.md",
    "content": "# Caches for NERV using an AXI interface\n\n\n## Contents\n\n### Cache Implementation\n\nSplit across [`nerv_axi_cache.sv`](./nerv_axi_cache.sv), [`nerv_axi_cache_icache.sv`](./nerv_axi_cache_icache.sv) and [`nerv_axi_cache_dcache.sv`](./nerv_axi_cache_dcache.sv).\n\nThe top-level module for the cache is `nerv_axi_cache` in [`nerv_axi_cache.sv`](./nerv_axi_cache.sv).\nModule parameters are documented in the comment above that module.\n\n### Testbenches\n\nThe testbenches were tested using `iverilog`, use `make test_axi` and `make test_internal` for running them.\nThere is [`testbench_internal.sv`](./testbench_internal.sv) which uses the cache-internal bus instead of the AXI interface and [`testbench_axi.sv`](./testbench_axi.sv) which uses the full AXI-interfacing cache together with a third-party open-source AXI4 memory implementation in [`axi_ram.v`](./axi_ram.v) (Taken from [Alex Forencich's \"Verilog AXI Components\"](https://github.com/alexforencich/verilog-axi)).\n\nThese testbenches also uses a different firmware than the top-level NERV testbench to actually exercise the cache a bit.\n\n### Formal Verification Using SVA AXI Properties\n\nThe caches' AXI interface is formally verified using the [YosysHQ SVA AXI Properties](https://github.com/YosysHQ-GmbH/SVA-AXI4-FVIP).\nUse `make verify_axi` to run this verification.\n\nThe verification is setup in [`verify_axi.sby`](./verify_axi.sby) and [`verify_axi.sv`](./verify_axi.sv).\n\nNote that SVA-AXI4-FVIP requires SVA support and thus this part requires the Tabby CAD Suite and does not work with the OSS CAD Suite. This limitation does not apply to verifying NERV using riscv-formal.\n\n### RISC-V Formal Bus Checks\n\nThe caches' correct operation when used together with the NERV core is formally verified using riscv-formal's bus memory checks.\n\nThis can be done for the complete caches using the AXI interface, using `make checks_axi`, as well as for the cache internal interface using `make checks_internal`.\n\nThe riscv-formal configurations are in [`checks_axi.cfg`](./checks_axi.cfg) and [`checks_internal.cfg`](./checks_internal.cfg). The RVFI wrappers are [`wrapper_axi.sv`](./wrapper_axi.sv) and [`wrapper_internal.sv`](./wrapper_internal.sv).\n\nThe RVFI wrapper for the AXI setup also uses a modified version of  [`axi_ram.v`](./axi_ram.v) in which the actual memory is removed and read data is unconstrained. This modified version is contained in [`axi_ram_abstraction.v`](./axi_ram_abstraction.v).\n"
  },
  {
    "path": "cores/nerv/axi_cache/axi_ram.v",
    "content": "// Modified to comment out the timescale directive\n/*\n\nCopyright (c) 2018 Alex Forencich\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n*/\n\n// Language: Verilog 2001\n\n`resetall\n// `timescale 1ns / 1ps\n`default_nettype none\n\n/*\n * AXI4 RAM\n */\nmodule axi_ram #\n(\n    // Width of data bus in bits\n    parameter DATA_WIDTH = 32,\n    // Width of address bus in bits\n    parameter ADDR_WIDTH = 16,\n    // Width of wstrb (width of data bus in words)\n    parameter STRB_WIDTH = (DATA_WIDTH/8),\n    // Width of ID signal\n    parameter ID_WIDTH = 8,\n    // Extra pipeline register on output\n    parameter PIPELINE_OUTPUT = 0\n)\n(\n    input  wire                   clk,\n    input  wire                   rst,\n\n    input  wire [ID_WIDTH-1:0]    s_axi_awid,\n    input  wire [ADDR_WIDTH-1:0]  s_axi_awaddr,\n    input  wire [7:0]             s_axi_awlen,\n    input  wire [2:0]             s_axi_awsize,\n    input  wire [1:0]             s_axi_awburst,\n    input  wire                   s_axi_awlock,\n    input  wire [3:0]             s_axi_awcache,\n    input  wire [2:0]             s_axi_awprot,\n    input  wire                   s_axi_awvalid,\n    output wire                   s_axi_awready,\n    input  wire [DATA_WIDTH-1:0]  s_axi_wdata,\n    input  wire [STRB_WIDTH-1:0]  s_axi_wstrb,\n    input  wire                   s_axi_wlast,\n    input  wire                   s_axi_wvalid,\n    output wire                   s_axi_wready,\n    output wire [ID_WIDTH-1:0]    s_axi_bid,\n    output wire [1:0]             s_axi_bresp,\n    output wire                   s_axi_bvalid,\n    input  wire                   s_axi_bready,\n    input  wire [ID_WIDTH-1:0]    s_axi_arid,\n    input  wire [ADDR_WIDTH-1:0]  s_axi_araddr,\n    input  wire [7:0]             s_axi_arlen,\n    input  wire [2:0]             s_axi_arsize,\n    input  wire [1:0]             s_axi_arburst,\n    input  wire                   s_axi_arlock,\n    input  wire [3:0]             s_axi_arcache,\n    input  wire [2:0]             s_axi_arprot,\n    input  wire                   s_axi_arvalid,\n    output wire                   s_axi_arready,\n    output wire [ID_WIDTH-1:0]    s_axi_rid,\n    output wire [DATA_WIDTH-1:0]  s_axi_rdata,\n    output wire [1:0]             s_axi_rresp,\n    output wire                   s_axi_rlast,\n    output wire                   s_axi_rvalid,\n    input  wire                   s_axi_rready\n);\n\nparameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH);\nparameter WORD_WIDTH = STRB_WIDTH;\nparameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;\n\n// bus width assertions\ninitial begin\n    if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin\n        $error(\"Error: AXI data width not evenly divisble (instance %m)\");\n        $finish;\n    end\n\n    if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin\n        $error(\"Error: AXI word width must be even power of two (instance %m)\");\n        $finish;\n    end\nend\n\nlocalparam [0:0]\n    READ_STATE_IDLE = 1'd0,\n    READ_STATE_BURST = 1'd1;\n\nreg [0:0] read_state_reg = READ_STATE_IDLE, read_state_next;\n\nlocalparam [1:0]\n    WRITE_STATE_IDLE = 2'd0,\n    WRITE_STATE_BURST = 2'd1,\n    WRITE_STATE_RESP = 2'd2;\n\nreg [1:0] write_state_reg = WRITE_STATE_IDLE, write_state_next;\n\nreg mem_wr_en;\nreg mem_rd_en;\n\nreg [ID_WIDTH-1:0] read_id_reg = {ID_WIDTH{1'b0}}, read_id_next;\nreg [ADDR_WIDTH-1:0] read_addr_reg = {ADDR_WIDTH{1'b0}}, read_addr_next;\nreg [7:0] read_count_reg = 8'd0, read_count_next;\nreg [2:0] read_size_reg = 3'd0, read_size_next;\nreg [1:0] read_burst_reg = 2'd0, read_burst_next;\nreg [ID_WIDTH-1:0] write_id_reg = {ID_WIDTH{1'b0}}, write_id_next;\nreg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next;\nreg [7:0] write_count_reg = 8'd0, write_count_next;\nreg [2:0] write_size_reg = 3'd0, write_size_next;\nreg [1:0] write_burst_reg = 2'd0, write_burst_next;\n\nreg s_axi_awready_reg = 1'b0, s_axi_awready_next;\nreg s_axi_wready_reg = 1'b0, s_axi_wready_next;\nreg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}, s_axi_bid_next;\nreg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;\nreg s_axi_arready_reg = 1'b0, s_axi_arready_next;\nreg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}}, s_axi_rid_next;\nreg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}}, s_axi_rdata_next;\nreg s_axi_rlast_reg = 1'b0, s_axi_rlast_next;\nreg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;\nreg [ID_WIDTH-1:0] s_axi_rid_pipe_reg = {ID_WIDTH{1'b0}};\nreg [DATA_WIDTH-1:0] s_axi_rdata_pipe_reg = {DATA_WIDTH{1'b0}};\nreg s_axi_rlast_pipe_reg = 1'b0;\nreg s_axi_rvalid_pipe_reg = 1'b0;\n\n// (* RAM_STYLE=\"BLOCK\" *)\nreg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];\n\nwire [VALID_ADDR_WIDTH-1:0] s_axi_awaddr_valid = s_axi_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);\nwire [VALID_ADDR_WIDTH-1:0] s_axi_araddr_valid = s_axi_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);\nwire [VALID_ADDR_WIDTH-1:0] read_addr_valid = read_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);\nwire [VALID_ADDR_WIDTH-1:0] write_addr_valid = write_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);\n\nassign s_axi_awready = s_axi_awready_reg;\nassign s_axi_wready = s_axi_wready_reg;\nassign s_axi_bid = s_axi_bid_reg;\nassign s_axi_bresp = 2'b00;\nassign s_axi_bvalid = s_axi_bvalid_reg;\nassign s_axi_arready = s_axi_arready_reg;\nassign s_axi_rid = PIPELINE_OUTPUT ? s_axi_rid_pipe_reg : s_axi_rid_reg;\nassign s_axi_rdata = PIPELINE_OUTPUT ? s_axi_rdata_pipe_reg : s_axi_rdata_reg;\nassign s_axi_rresp = 2'b00;\nassign s_axi_rlast = PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : s_axi_rlast_reg;\nassign s_axi_rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg;\n\ninteger i, j;\n\ninitial begin\n    // two nested loops for smaller number of iterations per loop\n    // workaround for synthesizer complaints about large loop counts\n    for (i = 0; i < 2**VALID_ADDR_WIDTH; i = i + 2**(VALID_ADDR_WIDTH/2)) begin\n        for (j = i; j < i + 2**(VALID_ADDR_WIDTH/2); j = j + 1) begin\n            mem[j] = 0;\n        end\n    end\nend\n\nalways @* begin\n    write_state_next = WRITE_STATE_IDLE;\n\n    mem_wr_en = 1'b0;\n\n    write_id_next = write_id_reg;\n    write_addr_next = write_addr_reg;\n    write_count_next = write_count_reg;\n    write_size_next = write_size_reg;\n    write_burst_next = write_burst_reg;\n\n    s_axi_awready_next = 1'b0;\n    s_axi_wready_next = 1'b0;\n    s_axi_bid_next = s_axi_bid_reg;\n    s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;\n\n    case (write_state_reg)\n        WRITE_STATE_IDLE: begin\n            s_axi_awready_next = 1'b1;\n\n            if (s_axi_awready && s_axi_awvalid) begin\n                write_id_next = s_axi_awid;\n                write_addr_next = s_axi_awaddr;\n                write_count_next = s_axi_awlen;\n                write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH);\n                write_burst_next = s_axi_awburst;\n\n                s_axi_awready_next = 1'b0;\n                s_axi_wready_next = 1'b1;\n                write_state_next = WRITE_STATE_BURST;\n            end else begin\n                write_state_next = WRITE_STATE_IDLE;\n            end\n        end\n        WRITE_STATE_BURST: begin\n            s_axi_wready_next = 1'b1;\n\n            if (s_axi_wready && s_axi_wvalid) begin\n                mem_wr_en = 1'b1;\n                if (write_burst_reg != 2'b00) begin\n                    write_addr_next = write_addr_reg + (1 << write_size_reg);\n                end\n                write_count_next = write_count_reg - 1;\n                if (write_count_reg > 0) begin\n                    write_state_next = WRITE_STATE_BURST;\n                end else begin\n                    s_axi_wready_next = 1'b0;\n                    if (s_axi_bready || !s_axi_bvalid) begin\n                        s_axi_bid_next = write_id_reg;\n                        s_axi_bvalid_next = 1'b1;\n                        s_axi_awready_next = 1'b1;\n                        write_state_next = WRITE_STATE_IDLE;\n                    end else begin\n                        write_state_next = WRITE_STATE_RESP;\n                    end\n                end\n            end else begin\n                write_state_next = WRITE_STATE_BURST;\n            end\n        end\n        WRITE_STATE_RESP: begin\n            if (s_axi_bready || !s_axi_bvalid) begin\n                s_axi_bid_next = write_id_reg;\n                s_axi_bvalid_next = 1'b1;\n                s_axi_awready_next = 1'b1;\n                write_state_next = WRITE_STATE_IDLE;\n            end else begin\n                write_state_next = WRITE_STATE_RESP;\n            end\n        end\n    endcase\nend\n\nalways @(posedge clk) begin\n    write_state_reg <= write_state_next;\n\n    write_id_reg <= write_id_next;\n    write_addr_reg <= write_addr_next;\n    write_count_reg <= write_count_next;\n    write_size_reg <= write_size_next;\n    write_burst_reg <= write_burst_next;\n\n    s_axi_awready_reg <= s_axi_awready_next;\n    s_axi_wready_reg <= s_axi_wready_next;\n    s_axi_bid_reg <= s_axi_bid_next;\n    s_axi_bvalid_reg <= s_axi_bvalid_next;\n\n    for (i = 0; i < WORD_WIDTH; i = i + 1) begin\n        if (mem_wr_en & s_axi_wstrb[i]) begin\n            mem[write_addr_valid][WORD_SIZE*i +: WORD_SIZE] <= s_axi_wdata[WORD_SIZE*i +: WORD_SIZE];\n        end\n    end\n\n    if (rst) begin\n        write_state_reg <= WRITE_STATE_IDLE;\n\n        s_axi_awready_reg <= 1'b0;\n        s_axi_wready_reg <= 1'b0;\n        s_axi_bvalid_reg <= 1'b0;\n    end\nend\n\nalways @* begin\n    read_state_next = READ_STATE_IDLE;\n\n    mem_rd_en = 1'b0;\n\n    s_axi_rid_next = s_axi_rid_reg;\n    s_axi_rlast_next = s_axi_rlast_reg;\n    s_axi_rvalid_next = s_axi_rvalid_reg && !(s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg));\n\n    read_id_next = read_id_reg;\n    read_addr_next = read_addr_reg;\n    read_count_next = read_count_reg;\n    read_size_next = read_size_reg;\n    read_burst_next = read_burst_reg;\n\n    s_axi_arready_next = 1'b0;\n\n    case (read_state_reg)\n        READ_STATE_IDLE: begin\n            s_axi_arready_next = 1'b1;\n\n            if (s_axi_arready && s_axi_arvalid) begin\n                read_id_next = s_axi_arid;\n                read_addr_next = s_axi_araddr;\n                read_count_next = s_axi_arlen;\n                read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH);\n                read_burst_next = s_axi_arburst;\n\n                s_axi_arready_next = 1'b0;\n                read_state_next = READ_STATE_BURST;\n            end else begin\n                read_state_next = READ_STATE_IDLE;\n            end\n        end\n        READ_STATE_BURST: begin\n            if (s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg) || !s_axi_rvalid_reg) begin\n                mem_rd_en = 1'b1;\n                s_axi_rvalid_next = 1'b1;\n                s_axi_rid_next = read_id_reg;\n                s_axi_rlast_next = read_count_reg == 0;\n                if (read_burst_reg != 2'b00) begin\n                    read_addr_next = read_addr_reg + (1 << read_size_reg);\n                end\n                read_count_next = read_count_reg - 1;\n                if (read_count_reg > 0) begin\n                    read_state_next = READ_STATE_BURST;\n                end else begin\n                    s_axi_arready_next = 1'b1;\n                    read_state_next = READ_STATE_IDLE;\n                end\n            end else begin\n                read_state_next = READ_STATE_BURST;\n            end\n        end\n    endcase\nend\n\nalways @(posedge clk) begin\n    read_state_reg <= read_state_next;\n\n    read_id_reg <= read_id_next;\n    read_addr_reg <= read_addr_next;\n    read_count_reg <= read_count_next;\n    read_size_reg <= read_size_next;\n    read_burst_reg <= read_burst_next;\n\n    s_axi_arready_reg <= s_axi_arready_next;\n    s_axi_rid_reg <= s_axi_rid_next;\n    s_axi_rlast_reg <= s_axi_rlast_next;\n    s_axi_rvalid_reg <= s_axi_rvalid_next;\n\n    if (mem_rd_en) begin\n        s_axi_rdata_reg <= mem[read_addr_valid];\n    end\n\n    if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin\n        s_axi_rid_pipe_reg <= s_axi_rid_reg;\n        s_axi_rdata_pipe_reg <= s_axi_rdata_reg;\n        s_axi_rlast_pipe_reg <= s_axi_rlast_reg;\n        s_axi_rvalid_pipe_reg <= s_axi_rvalid_reg;\n    end\n\n    if (rst) begin\n        read_state_reg <= READ_STATE_IDLE;\n\n        s_axi_arready_reg <= 1'b0;\n        s_axi_rvalid_reg <= 1'b0;\n        s_axi_rvalid_pipe_reg <= 1'b0;\n    end\nend\n\nendmodule\n\n`resetall\n"
  },
  {
    "path": "cores/nerv/axi_cache/checks_axi.cfg",
    "content": "#  NERV -- Naive Educational RISC-V Processor\n#\n#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n#  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n#\n#  Permission to use, copy, modify, and/or distribute this software for any\n#  purpose with or without fee is hereby granted, provided that the above\n#  copyright notice and this permission notice appear in all copies.\n#\n#  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n[options]\nisa rv32i\nnbus 2\nbuslen 32\nmode bmc\nsolver boolector\n\n[depth]\n\ninsn                        16\n\nfault                       16\n\ncausal_mem              1   16\ncausal_io               1   16\n\nbus_imem                1   16\nbus_imem_fault          1   16\nbus_dmem                1   16\nbus_dmem_fault          1   16\n\nbus_dmem_io_read        1   16\nbus_dmem_io_read_fault  1   16\n\nbus_dmem_io_write       1   16\nbus_dmem_io_write_fault 1   16\n\nbus_dmem_io_order       1   16\n\n[csrs]\nmcause\n\n[defines]\n`define YOSYS // Hotfix for older Tabby CAD Releases\n`define NERV_RVFI\n`define NERV_FAULT\n`define RISCV_FORMAL_ALIGNED_MEM\n\n`define RISCV_FORMAL_MEM_FAULT\n\n`define RISCV_FORMAL_FAULT_WIDTH 8 // The cache makes faults more coarse than single RVFI_BUS transfers\n\n`define RISCV_FORMAL_IOADDR(addr) addr[31:16] == 16'h1234\n\n[defines liveness]\n`define NERV_FAIRNESS\n\n[verilog-files]\n@basedir@/bus/rvfi_bus_util.sv\n@basedir@/bus/rvfi_bus_axi4.sv\n@basedir@/cores/@core@/axi_cache/wrapper_axi.sv\n@basedir@/cores/@core@/@core@.sv\n@basedir@/cores/@core@/axi_cache/nerv_axi_cache.sv\n@basedir@/cores/@core@/axi_cache/nerv_axi_cache_icache.sv\n@basedir@/cores/@core@/axi_cache/nerv_axi_cache_dcache.sv\n"
  },
  {
    "path": "cores/nerv/axi_cache/checks_internal.cfg",
    "content": "#  NERV -- Naive Educational RISC-V Processor\n#\n#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n#  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n#\n#  Permission to use, copy, modify, and/or distribute this software for any\n#  purpose with or without fee is hereby granted, provided that the above\n#  copyright notice and this permission notice appear in all copies.\n#\n#  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n[options]\nisa rv32i\nnbus 3\nbuslen 256\nmode bmc\nsolver boolector\n\n[depth]\nbus_imem            1    14\nbus_imem_fault      1    14\nbus_dmem            1    14\nbus_dmem_fault      1    14\n\n[csrs]\nmcause\n\n[defines]\n`define YOSYS // Hotfix for older Tabby CAD Releases\n`define NERV_RVFI\n`define NERV_FAULT\n`define RISCV_FORMAL_ALIGNED_MEM\n`define RISCV_FORMAL_MEM_FAULT\n\n[defines liveness]\n`define NERV_FAIRNESS\n\n[verilog-files]\n@basedir@/cores/@core@/axi_cache/wrapper_internal.sv\n@basedir@/cores/@core@/@core@.sv\n@basedir@/cores/@core@/axi_cache/nerv_axi_cache_icache.sv\n@basedir@/cores/@core@/axi_cache/nerv_axi_cache_dcache.sv\n"
  },
  {
    "path": "cores/nerv/axi_cache/firmware.c",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nvoid putc(int c)\n{\n\tvolatile char *p = (void*)0x02000000;\n\t*p = c;\n}\n\nvoid do_exit()\n{\n\tvolatile unsigned *p = (void*)0x02000000;\n\t*p = 0x100;\n}\n\nvoid puts(char *s)\n{\n\twhile (*s) putc(*(s++));\n}\n\n\n#define SIEVE_SIZE 128\n\nvoid print_num(unsigned p)\n{\n\tchar force = 0;\n\tchar c;\n\tc = '0';\n\twhile (p >= 100)\n\t\tp -= 100, c++;\n\tif (c != '0' || force)\n\t\tputc(c), force = 1;\n\tc = '0';\n\twhile (p >= 10)\n\t\tp -= 10, c++;\n\tif (c != '0' || force)\n\t\tputc(c), force = 1;\n\tputc('0' + p);\n\tputc('\\n');\n}\n\nint main()\n{\n\tchar sieve[SIEVE_SIZE];\n\n\tputs(\"Some Primes:\\n\");\n\tfor (unsigned i = 2; i < SIEVE_SIZE; i++)\n\t\tsieve[i] = 1;\n\n\tfor (unsigned p = 2, p2 = 4; p < SIEVE_SIZE; p += 1, p2 += (p << 1) - 1) {\n\t\tif (sieve[p]) {\n\t\t\tprint_num(p);\n\t\t\tif (p2 < SIEVE_SIZE) {\n\t\t\t\tfor (unsigned i = p2; i < SIEVE_SIZE; i += p) {\n\t\t\t\t\tsieve[i] = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tdo_exit();\n\treturn 0;\n}\n"
  },
  {
    "path": "cores/nerv/axi_cache/nerv_axi_cache.sv",
    "content": "// Direct mapped, write-back/write-allocate AXI cache for the NERV core.\n//\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n`default_nettype none\n\n// The complete AXI cache.\n//\n// Provides NERV's native `imem_*` and `dmem_*` interface on one side and an\n// AXI4 manager interface on the other side.\n//\n// The NERV core expects single cycle accesses for both instruction and data\n// memory, and has a single `stall` signal that needs to be asserted to halt\n// the core when accesses take logner. To support multiplexing between the\n// cache and uncached memory/devices on the NERV side, this cache provides a\n// `stall` output and a `stalled` input. The `stalled` signal should be\n// connected to the same signal as NERV's `stall` input while NERV's `stall`\n// input should be an or of the cache's `stall` output with any other external\n// stall signal.\n//\n// ## Parameters\n//\n// This uses the convention that `<NAME>_WIDTH` = `8 << <NAME>_SIZE`.\n//\n// * `ADDRESS_WIDTH`: Address bit width for both AXI and NERV's interface. NERV\n//   only supports 32 bit, but the cache is generic.\n//\n// * `DATA_SIZE`: Data size for NERV's interface, NERV only supports 2\n//   (corresponding to 32-bit).\n//\n// * `INSN_SIZE`: Instruction size for NERV's interface, NERV only supports 2\n//   (corresponding to 32-bit).\n//\n// * `LINE_SIZE`: Size of a cache line, needs to be  larger than the maximum of\n//   `DATA_SIZE` and `INSN_SIZE` (corresponding to a cache line that is at\n//   least twice as wide as the NERV side accesses).\n//\n// * `ICACHE_INDEX_SIZE`, `DCACHE_INDEX_SIZE`: How many address bits are used\n//   to index the instruction/data cache memory. The size of the corresponding\n//   cache is `1 << INDEX_SIZE` cache lines.\n//\n// * `AXI_DATA_WIDTH`: Data width of the AXI interface, independent from the\n//   the widths used for NERV's interface.\n//\n// * `AXI_ID_WIDTH`: ID width for the AXI interface, doesn't affect NERV's\n//   interface.\n//\n// * `AXI_IMEM_ID`, `AXI_DMEM_ID`: which AXI ID to use for instruction and data\n//   accesses. Can be the same.\nmodule nerv_axi_cache #(\n    parameter ADDRESS_WIDTH = 32,\n    parameter DATA_SIZE = 2,\n    parameter INSN_SIZE = 2,\n    parameter LINE_SIZE = 3,\n    parameter ICACHE_INDEX_SIZE = 3,\n    parameter DCACHE_INDEX_SIZE = 3,\n\n    parameter AXI_DATA_WIDTH = 32,\n    parameter AXI_ID_WIDTH = 1,\n\n    parameter AXI_IMEM_ID = 0,\n    parameter AXI_DMEM_ID = 1,\n\n    localparam INSN_WIDTH = 8 << INSN_SIZE,\n    localparam DATA_WIDTH = 8 << DATA_SIZE,\n    localparam LINE_WIDTH = 8 << LINE_SIZE,\n\n    localparam AXI_ADDRESS_WIDTH = ADDRESS_WIDTH,\n    localparam AXI_AWUSER_WIDTH = 1,\n    localparam AXI_WUSER_WIDTH = 1,\n    localparam AXI_BUSER_WIDTH = 1,\n    localparam AXI_ARUSER_WIDTH = 1,\n    localparam AXI_RUSER_WIDTH = 1,\n    localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8\n) (\n    input wire clock,\n    input wire reset,\n\n    input wire stalled,\n    output var stall,\n\n    // NERV's instruction memory interface\n    input wire [ADDRESS_WIDTH-1:0]   imem_addr,\n    output var [INSN_WIDTH-1:0]      imem_data,\n    output var                       imem_fault,\n\n    // NERV's data memory interface\n    input wire                       dmem_valid,\n    input wire [ADDRESS_WIDTH-1:0]   dmem_addr,\n    input wire [DATA_WIDTH/8-1:0]    dmem_wstrb,\n    input wire [DATA_WIDTH-1:0]      dmem_wdata,\n    output var [DATA_WIDTH-1:0]      dmem_rdata,\n    output var                       dmem_fault,\n\n    // Bypass the data cache for this access.\n    input wire                       dmem_io,\n    // This can also be wired up as a condition on dmem_addr to implement fixed\n    // uncached IO memory regions.\n\n    // Write Address Channel (AW)\n    output var [AXI_ID_WIDTH-1:0]       axi_awid,\n    output var [AXI_ADDRESS_WIDTH-1:0]  axi_awaddr,\n    output var [3:0]                    axi_awregion,  // not used, default value\n    output var [7:0]                    axi_awlen,\n    output var [2:0]                    axi_awsize,\n    output var [1:0]                    axi_awburst,\n    output var                          axi_awlock,    // not used, default value\n    output var [3:0]                    axi_awcache,   // not used, fixed value\n    output var [2:0]                    axi_awprot,\n    output var [3:0]                    axi_awqos,     // not used, default value\n    output var [AXI_AWUSER_WIDTH-1:0]   axi_awuser,    // not used, all zero\n    output var                          axi_awvalid,\n    input wire                          axi_awready,\n    // Write Data Channel (W)\n    output var [AXI_DATA_WIDTH-1:0]     axi_wdata,\n    output var [AXI_STRB_WIDTH-1:0]     axi_wstrb,\n    output var                          axi_wlast,\n    output var [AXI_WUSER_WIDTH-1:0]    axi_wuser,     // not used, all zero\n    output var                          axi_wvalid,\n    input wire                          axi_wready,\n    // Write Response Channel (B)\n    input wire [AXI_ID_WIDTH-1:0]       axi_bid,       // ignored, cache does not use overlapping transactions\n    input wire [1:0]                    axi_bresp,     // ignored, cache does not handle faults during writeback\n    input wire [AXI_BUSER_WIDTH-1:0]    axi_buser,     // ignored\n    input wire                          axi_bvalid,\n    output var                          axi_bready,\n    // Read Address Channel (AR)\n    output var [AXI_ID_WIDTH-1:0]       axi_arid,\n    output var [AXI_ADDRESS_WIDTH-1:0]  axi_araddr,\n    output var [3:0]                    axi_arregion,  // not used, default value\n    output var [7:0]                    axi_arlen,\n    output var [2:0]                    axi_arsize,\n    output var [1:0]                    axi_arburst,\n    output var                          axi_arlock,    // not used, default value\n    output var [3:0]                    axi_arcache,   // not used, fixed value\n    output var [2:0]                    axi_arprot,\n    output var [3:0]                    axi_arqos,     // not used, default value\n    output var [AXI_ARUSER_WIDTH-1:0]   axi_aruser,    // not used, all zero\n    output var                          axi_arvalid,\n    input wire                          axi_arready,\n    // Read Data Channel (R)\n    input wire [AXI_ID_WIDTH-1:0]       axi_rid,       // ignored, cache does not use overlapping transactions\n    input wire [AXI_DATA_WIDTH-1:0]     axi_rdata,\n    input wire [1:0]                    axi_rresp,\n    input wire                          axi_rlast,\n    input wire [AXI_RUSER_WIDTH-1:0]    axi_ruser,     // ignored\n    input wire                          axi_rvalid,\n    output var                          axi_rready\n\n);\n\n    logic [ADDRESS_WIDTH-1:0]   imem_req_addr;\n    logic                       imem_req_valid;\n\n    logic [LINE_WIDTH-1:0]      imem_res_data;\n    logic                       imem_res_fault;\n    logic                       imem_res_valid;\n\n    logic [ADDRESS_WIDTH-1:0]   dmem_req_r_addr;\n    logic                       dmem_req_r_valid;\n\n    logic [LINE_WIDTH-1:0]      dmem_res_r_data;\n    logic                       dmem_res_r_fault;\n    logic                       dmem_res_r_valid;\n\n    logic [ADDRESS_WIDTH-1:0]   dmem_req_w_addr;\n    logic [LINE_WIDTH-1:0]      dmem_req_w_data;\n    logic                       dmem_req_w_valid;\n\n    logic                       dmem_res_w_fault;\n    logic                       dmem_res_w_valid;\n\n    logic [ADDRESS_WIDTH-1:0]   dmem_req_ur_addr;\n    logic                       dmem_req_ur_valid;\n\n    logic [DATA_WIDTH-1:0]      dmem_res_ur_data;\n    logic                       dmem_res_ur_fault;\n    logic                       dmem_res_ur_valid;\n\n    logic [ADDRESS_WIDTH-1:0]   dmem_req_uw_addr;\n    logic [DATA_WIDTH-1:0]      dmem_req_uw_data;\n    logic [DATA_WIDTH/8-1:0]    dmem_req_uw_strb;\n    logic                       dmem_req_uw_valid;\n\n    logic                       dmem_res_uw_fault;\n    logic                       dmem_res_uw_valid;\n\n    logic icache_stall, dcache_stall, io_stall;\n\n    assign stall = icache_stall || dcache_stall || io_stall;\n\n    logic [DATA_WIDTH-1:0]      dmem_rdata_cache;\n    logic                       dmem_fault_cache;\n\n    logic [DATA_WIDTH-1:0]      dmem_rdata_io;\n    logic                       dmem_fault_io;\n\n    logic last_dmem_io;\n\n    always @(posedge clock) begin\n        if (!stalled && dmem_valid) begin\n            last_dmem_io <= dmem_io;\n        end\n    end\n\n    assign dmem_rdata = last_dmem_io ? dmem_rdata_io : dmem_rdata_cache;\n    assign dmem_fault = last_dmem_io ? dmem_fault_io : dmem_fault_cache;\n\n    nerv_axi_cache_axi #(\n        .ADDRESS_WIDTH(ADDRESS_WIDTH),\n        .DATA_SIZE(DATA_SIZE),\n        .INSN_SIZE(INSN_SIZE),\n        .LINE_SIZE(LINE_SIZE),\n        .AXI_DATA_WIDTH(AXI_DATA_WIDTH),\n        .AXI_ID_WIDTH(AXI_ID_WIDTH),\n\n        .AXI_IMEM_ID(AXI_IMEM_ID),\n        .AXI_DMEM_ID(AXI_DMEM_ID)\n    ) axi (\n        .clock(clock),\n        .reset(reset),\n\n        .imem_req_addr(imem_req_addr),\n        .imem_req_valid(imem_req_valid),\n\n        .imem_res_data(imem_res_data),\n        .imem_res_fault(imem_res_fault),\n        .imem_res_valid(imem_res_valid),\n\n        .dmem_req_r_addr(dmem_req_r_addr),\n        .dmem_req_r_valid(dmem_req_r_valid),\n\n        .dmem_res_r_data(dmem_res_r_data),\n        .dmem_res_r_fault(dmem_res_r_fault),\n        .dmem_res_r_valid(dmem_res_r_valid),\n\n        .dmem_req_w_addr(dmem_req_w_addr),\n        .dmem_req_w_data(dmem_req_w_data),\n        .dmem_req_w_valid(dmem_req_w_valid),\n\n        .dmem_res_w_fault(dmem_res_w_fault),\n        .dmem_res_w_valid(dmem_res_w_valid),\n\n        .dmem_req_ur_addr(dmem_req_ur_addr),\n        .dmem_req_ur_valid(dmem_req_ur_valid),\n\n        .dmem_res_ur_data(dmem_res_ur_data),\n        .dmem_res_ur_fault(dmem_res_ur_fault),\n        .dmem_res_ur_valid(dmem_res_ur_valid),\n\n        .dmem_req_uw_addr(dmem_req_uw_addr),\n        .dmem_req_uw_data(dmem_req_uw_data),\n        .dmem_req_uw_strb(dmem_req_uw_strb),\n        .dmem_req_uw_valid(dmem_req_uw_valid),\n\n        .dmem_res_uw_fault(dmem_res_uw_fault),\n        .dmem_res_uw_valid(dmem_res_uw_valid),\n\n        // Write Address Channel (AW)\n        .axi_awid(axi_awid),\n        .axi_awaddr(axi_awaddr),\n        .axi_awregion(axi_awregion),\n        .axi_awlen(axi_awlen),\n        .axi_awsize(axi_awsize),\n        .axi_awburst(axi_awburst),\n        .axi_awlock(axi_awlock),\n        .axi_awcache(axi_awcache),\n        .axi_awprot(axi_awprot),\n        .axi_awqos(axi_awqos),\n        .axi_awuser(axi_awuser),\n        .axi_awvalid(axi_awvalid),\n        .axi_awready(axi_awready),\n        // Write Data Channel (W)\n        .axi_wdata(axi_wdata),\n        .axi_wstrb(axi_wstrb),\n        .axi_wlast(axi_wlast),\n        .axi_wuser(axi_wuser),\n        .axi_wvalid(axi_wvalid),\n        .axi_wready(axi_wready),\n        // Write Response Channel (B)\n        .axi_bid(axi_bid),\n        .axi_bresp(axi_bresp),\n        .axi_buser(axi_buser),\n        .axi_bvalid(axi_bvalid),\n        .axi_bready(axi_bready),\n        // Read Address Channel (AR)\n        .axi_arid(axi_arid),\n        .axi_araddr(axi_araddr),\n        .axi_arregion(axi_arregion),\n        .axi_arlen(axi_arlen),\n        .axi_arsize(axi_arsize),\n        .axi_arburst(axi_arburst),\n        .axi_arlock(axi_arlock),\n        .axi_arcache(axi_arcache),\n        .axi_arprot(axi_arprot),\n        .axi_arqos(axi_arqos),\n        .axi_aruser(axi_aruser),\n        .axi_arvalid(axi_arvalid),\n        .axi_arready(axi_arready),\n        // Read Data Channel (R)\n        .axi_rid(axi_rid),\n        .axi_rdata(axi_rdata),\n        .axi_rresp(axi_rresp),\n        .axi_rlast(axi_rlast),\n        .axi_ruser(axi_ruser),\n        .axi_rvalid(axi_rvalid),\n        .axi_rready(axi_rready)\n    );\n\n\n    nerv_axi_cache_icache #(\n        .ADDRESS_WIDTH(ADDRESS_WIDTH),\n        .INSN_SIZE(INSN_SIZE),\n        .LINE_SIZE(LINE_SIZE),\n        .INDEX_SIZE(ICACHE_INDEX_SIZE)\n    ) icache (\n        .clock(clock),\n        .reset(reset),\n\n        .stalled(stalled),\n        .stall(icache_stall),\n\n        .imem_addr(imem_addr),\n        .imem_data(imem_data),\n        .imem_fault(imem_fault),\n\n        .req_addr(imem_req_addr),\n        .req_valid(imem_req_valid),\n\n        .res_data(imem_res_data),\n        .res_fault(imem_res_fault),\n        .res_valid(imem_res_valid)\n    );\n\n    nerv_axi_cache_dcache #(\n        .ADDRESS_WIDTH(ADDRESS_WIDTH),\n        .DATA_SIZE(DATA_SIZE),\n        .LINE_SIZE(LINE_SIZE),\n        .INDEX_SIZE(DCACHE_INDEX_SIZE)\n    ) dcache (\n        .clock(clock),\n        .reset(reset),\n\n        .stalled(stalled),\n        .stall(dcache_stall),\n\n        .dmem_valid(dmem_valid && !dmem_io),\n        .dmem_addr(dmem_addr),\n        .dmem_wstrb(dmem_wstrb),\n        .dmem_wdata(dmem_wdata),\n        .dmem_rdata(dmem_rdata_cache),\n        .dmem_fault(dmem_fault_cache),\n\n        .req_r_addr(dmem_req_r_addr),\n        .req_r_valid(dmem_req_r_valid),\n\n        .res_r_data(dmem_res_r_data),\n        .res_r_fault(dmem_res_r_fault),\n        .res_r_valid(dmem_res_r_valid),\n\n        .req_w_addr(dmem_req_w_addr),\n        .req_w_data(dmem_req_w_data),\n        .req_w_valid(dmem_req_w_valid),\n\n        .res_w_fault(dmem_res_w_fault),\n        .res_w_valid(dmem_res_w_valid)\n    );\n\n    nerv_axi_cache_io #(\n        .ADDRESS_WIDTH(ADDRESS_WIDTH),\n        .DATA_SIZE(DATA_SIZE)\n    ) io (\n        .clock(clock),\n        .reset(reset),\n\n        .stalled(stalled),\n        .stall(io_stall),\n\n        .dmem_valid(dmem_valid && dmem_io),\n        .dmem_addr(dmem_addr),\n        .dmem_wstrb(dmem_wstrb),\n        .dmem_wdata(dmem_wdata),\n        .dmem_rdata(dmem_rdata_io),\n        .dmem_fault(dmem_fault_io),\n\n        .req_ur_addr(dmem_req_ur_addr),\n        .req_ur_valid(dmem_req_ur_valid),\n\n        .res_ur_data(dmem_res_ur_data),\n        .res_ur_fault(dmem_res_ur_fault),\n        .res_ur_valid(dmem_res_ur_valid),\n\n        .req_uw_addr(dmem_req_uw_addr),\n        .req_uw_data(dmem_req_uw_data),\n        .req_uw_strb(dmem_req_uw_strb),\n        .req_uw_valid(dmem_req_uw_valid),\n\n        .res_uw_fault(dmem_res_uw_fault),\n        .res_uw_valid(dmem_res_uw_valid)\n    );\n\n\n\nendmodule\n\nmodule nerv_axi_cache_io #(\n    parameter ADDRESS_WIDTH = 32,\n    parameter DATA_SIZE = 2,\n\n    localparam DATA_WIDTH = 8 << DATA_SIZE\n) (\n    input wire                       clock,\n    input wire                       reset,\n\n    input wire                       stalled,\n    output var                       stall,\n\n    input wire                       dmem_valid,\n    input wire [ADDRESS_WIDTH-1:0]   dmem_addr,\n    input wire [DATA_WIDTH/8-1:0]    dmem_wstrb,\n    input wire [DATA_WIDTH-1:0]      dmem_wdata,\n    output var [DATA_WIDTH-1:0]      dmem_rdata,\n    output var                       dmem_fault,\n\n    output var [ADDRESS_WIDTH-1:0]   req_ur_addr,\n    output var                       req_ur_valid,\n\n    input wire [DATA_WIDTH-1:0]      res_ur_data,\n    input wire                       res_ur_fault,\n    input wire                       res_ur_valid,\n\n    output var [ADDRESS_WIDTH-1:0]   req_uw_addr,\n    output var [DATA_WIDTH-1:0]      req_uw_data,\n    output var [DATA_WIDTH/8-1:0]    req_uw_strb,\n    output var                       req_uw_valid,\n\n    input wire                       res_uw_fault,\n    input wire                       res_uw_valid\n);\n    typedef logic [ADDRESS_WIDTH-1:0] addr_t;\n\n    // cache last dmem interface values while the core is stalled\n    addr_t stable_addr, stable_addr_q;\n    logic [DATA_WIDTH/8-1:0] stable_wstrb;\n    logic [DATA_WIDTH/8-1:0] stable_wstrb_q;\n    logic [DATA_WIDTH-1:0] stable_wdata;\n    logic [DATA_WIDTH-1:0] stable_wdata_q;\n    logic stable_valid, stable_valid_q;\n    logic stalled_q;\n    logic reset_q;\n\n    always_ff @(posedge clock) begin\n        stable_addr_q <= stable_addr;\n        stable_wstrb_q <= stable_wstrb;\n        stable_wdata_q <= stable_wdata;\n        stable_valid_q <= stable_valid;\n        stalled_q <= stalled;\n        reset_q <= reset;\n    end\n\n    always_comb begin\n        stable_addr = stable_addr_q;\n        stable_wstrb = stable_wstrb_q;\n        stable_wdata = stable_wdata_q;\n        stable_valid = stable_valid_q;\n        if (!stalled && dmem_valid) begin\n            stable_addr = dmem_addr;\n            stable_wdata = dmem_wdata;\n            stable_wstrb = dmem_wstrb;\n        end\n        if (!stalled) begin\n            stable_valid = dmem_valid;\n        end\n    end\n\n    logic [DATA_WIDTH-1:0] dmem_rdata_q;\n    logic dmem_fault_q;\n\n    always_ff @(posedge clock) begin\n        dmem_rdata_q <= dmem_rdata;\n        dmem_fault_q <= dmem_fault;\n    end\n\n    always_comb begin\n        dmem_rdata = dmem_rdata_q;\n        dmem_fault = dmem_fault_q;\n        if (res_ur_valid) begin\n            dmem_rdata = res_ur_data;\n            dmem_fault = res_ur_fault;\n        end\n        if (res_uw_valid) begin\n            dmem_fault = res_uw_fault;\n        end\n    end\n\n    logic req_uw_valid_q;\n    logic req_ur_valid_q;\n    logic res_uw_valid_q;\n    logic res_ur_valid_q;\n\n    assign stall = req_ur_valid_q || req_uw_valid_q;\n\n    always_ff @(posedge clock) begin\n        req_uw_valid_q <= req_uw_valid;\n        req_ur_valid_q <= req_ur_valid;\n        res_uw_valid_q <= res_uw_valid;\n        res_ur_valid_q <= res_ur_valid;\n    end\n\n    assign req_ur_addr = stable_addr;\n\n    assign req_uw_addr = stable_addr;\n    assign req_uw_data = stable_wdata;\n    assign req_uw_strb = stable_wstrb;\n\n    always_comb begin\n        req_uw_valid = req_uw_valid_q;\n        req_ur_valid = req_ur_valid_q;\n\n        if (res_ur_valid_q) begin\n            req_ur_valid = 0;\n        end\n\n        if (res_uw_valid_q) begin\n            req_uw_valid = 0;\n        end\n\n        if (!stalled && dmem_valid && !dmem_wstrb) begin\n            req_ur_valid = 1;\n        end\n\n\n        if (!stalled && dmem_valid && dmem_wstrb) begin\n            req_uw_valid = 1;\n        end\n\n\n        if (reset || reset_q) begin\n            req_uw_valid = 0;\n            req_ur_valid = 0;\n        end\n    end\n\nendmodule\n\n// AXI protocol handling\n//\n// This has the AXI interface on one side and the actual instruction and data\n// caches on the other side. The caches are interfaced using an internal\n// interface ({imem,dmem}_{req,res}_{r,w}_*) that transfers whole cache lines\n// at once.\n//\n// See `nerv_axi_cache` for parameter descriptions.\nmodule nerv_axi_cache_axi #(\n    parameter ADDRESS_WIDTH = 32,\n    parameter DATA_SIZE = 2,\n    parameter INSN_SIZE = 2,\n    parameter LINE_SIZE = 3,\n\n    parameter AXI_DATA_WIDTH = 32,\n    parameter AXI_ID_WIDTH = 1,\n\n    parameter AXI_IMEM_ID = 0,\n    parameter AXI_DMEM_ID = 1,\n    parameter AXI_IO_ID = AXI_DMEM_ID,\n\n    localparam INSN_WIDTH = 8 << INSN_SIZE,\n    localparam DATA_WIDTH = 8 << DATA_SIZE,\n    localparam LINE_WIDTH = 8 << LINE_SIZE,\n\n    localparam AXI_ADDRESS_WIDTH = ADDRESS_WIDTH,\n    localparam AXI_AWUSER_WIDTH = 1,\n    localparam AXI_WUSER_WIDTH = 1,\n    localparam AXI_BUSER_WIDTH = 1,\n    localparam AXI_ARUSER_WIDTH = 1,\n    localparam AXI_RUSER_WIDTH = 1,\n    localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8\n) (\n    input wire clock,\n    input wire reset,\n\n    input wire [ADDRESS_WIDTH-1:0]   imem_req_addr,\n    input wire                       imem_req_valid,\n\n    output var [LINE_WIDTH-1:0]      imem_res_data,\n    output var                       imem_res_fault,\n    output var                       imem_res_valid,\n\n    input wire [ADDRESS_WIDTH-1:0]   dmem_req_r_addr,\n    input wire                       dmem_req_r_valid,\n\n    output var [LINE_WIDTH-1:0]      dmem_res_r_data,\n    output var                       dmem_res_r_fault,\n    output var                       dmem_res_r_valid,\n\n    input wire [ADDRESS_WIDTH-1:0]   dmem_req_w_addr,\n    input wire [LINE_WIDTH-1:0]      dmem_req_w_data,\n    input wire                       dmem_req_w_valid,\n\n    output var                       dmem_res_w_fault,\n    output var                       dmem_res_w_valid,\n\n    input wire [ADDRESS_WIDTH-1:0]   dmem_req_ur_addr,\n    input wire                       dmem_req_ur_valid,\n\n    output var [DATA_WIDTH-1:0]      dmem_res_ur_data,\n    output var                       dmem_res_ur_fault,\n    output var                       dmem_res_ur_valid,\n\n    input wire [ADDRESS_WIDTH-1:0]   dmem_req_uw_addr,\n    input wire [DATA_WIDTH-1:0]      dmem_req_uw_data,\n    input wire [DATA_WIDTH/8-1:0]    dmem_req_uw_strb,\n    input wire                       dmem_req_uw_valid,\n\n    output var                       dmem_res_uw_fault,\n    output var                       dmem_res_uw_valid,\n\n    // Write Address Channel (AW)\n    output var [AXI_ID_WIDTH-1:0]       axi_awid,\n    output var [AXI_ADDRESS_WIDTH-1:0]  axi_awaddr,\n    output var [3:0]                    axi_awregion,  // not used, default value\n    output var [7:0]                    axi_awlen,\n    output var [2:0]                    axi_awsize,\n    output var [1:0]                    axi_awburst,\n    output var                          axi_awlock,    // not used, default value\n    output var [3:0]                    axi_awcache,   // not used, fixed value\n    output var [2:0]                    axi_awprot,\n    output var [3:0]                    axi_awqos,     // not used, default value\n    output var [AXI_AWUSER_WIDTH-1:0]   axi_awuser,    // not used, all zero\n    output var                          axi_awvalid,\n    input wire                          axi_awready,\n    // Write Data Channel (W)\n    output var [AXI_DATA_WIDTH-1:0]     axi_wdata,\n    output var [AXI_STRB_WIDTH-1:0]     axi_wstrb,\n    output var                          axi_wlast,\n    output var [AXI_WUSER_WIDTH-1:0]    axi_wuser,     // not used, all zero\n    output var                          axi_wvalid,\n    input wire                          axi_wready,\n    // Write Response Channel (B)\n    input wire [AXI_ID_WIDTH-1:0]       axi_bid,       // ignored, cache does not use overlapping transactions\n    input wire [1:0]                    axi_bresp,     // ignored, cache does not handle faults during writeback\n    input wire [AXI_BUSER_WIDTH-1:0]    axi_buser,     // ignored\n    input wire                          axi_bvalid,\n    output var                          axi_bready,\n    // Read Address Channel (AR)\n    output var [AXI_ID_WIDTH-1:0]       axi_arid,\n    output var [AXI_ADDRESS_WIDTH-1:0]  axi_araddr,\n    output var [3:0]                    axi_arregion,  // not used, default value\n    output var [7:0]                    axi_arlen,\n    output var [2:0]                    axi_arsize,\n    output var [1:0]                    axi_arburst,\n    output var                          axi_arlock,    // not used, default value\n    output var [3:0]                    axi_arcache,   // not used, fixed value\n    output var [2:0]                    axi_arprot,\n    output var [3:0]                    axi_arqos,     // not used, default value\n    output var [AXI_ARUSER_WIDTH-1:0]   axi_aruser,    // not used, all zero\n    output var                          axi_arvalid,\n    input wire                          axi_arready,\n    // Read Data Channel (R)\n    input wire [AXI_ID_WIDTH-1:0]       axi_rid,       // ignored, cache does not use overlapping transactions\n    input wire [AXI_DATA_WIDTH-1:0]     axi_rdata,\n    input wire [1:0]                    axi_rresp,\n    input wire                          axi_rlast,\n    input wire [AXI_RUSER_WIDTH-1:0]    axi_ruser,     // ignored\n    input wire                          axi_rvalid,\n    output var                          axi_rready\n);\n\n    // handle reads\n\n    typedef enum {\n        R_IDLE,\n        R_IFETCH,\n        R_DFETCH,\n        R_IOFETCH\n    } read_state_t;\n\n    read_state_t read_state, read_state_q;\n\n    assign axi_arregion = 0; // not used\n    assign axi_arlock = 0; // not used\n    assign axi_arcache = 4'b1111; // not used, TODO also support uncached accesses\n    assign axi_arqos = 0; // not used\n    assign axi_aruser = 0; // not used\n\n    assign axi_arsize = $clog2(AXI_DATA_WIDTH / 8); // always use full bus width\n    assign axi_arburst = 2'b01; // always incr\n\n    assign axi_rready = 1; // always ready\n\n    logic axi_arready_q, axi_arvalid_q;\n    logic [7:0] axi_arlen_q;\n    logic [2:0] axi_arprot_q;\n    logic [AXI_ID_WIDTH-1:0] axi_arid_q;\n    logic [AXI_ADDRESS_WIDTH-1:0] axi_araddr_q;\n\n    logic [LINE_WIDTH-1:0] read_data, read_data_q;\n    logic read_fault, read_fault_q;\n    logic read_valid;\n\n    logic reset_q;\n\n    always_ff @(posedge clock) begin\n        axi_arready_q <= axi_arready;\n\n        axi_arvalid_q <= axi_arvalid;\n        axi_arlen_q <= axi_arlen;\n        axi_arprot_q <= axi_arprot;\n        axi_arid_q <= axi_arid;\n        axi_araddr_q <= axi_araddr;\n\n        read_data_q <= read_data;\n        read_fault_q <= read_fault;\n\n        read_state_q <= read_state;\n\n        reset_q <= reset;\n    end\n\n    assign imem_res_fault = read_fault;\n    assign dmem_res_r_fault = read_fault;\n    assign dmem_res_ur_fault = read_fault;\n\n    assign imem_res_valid = (read_state_q == R_IFETCH && read_valid);\n    assign dmem_res_r_valid = (read_state_q == R_DFETCH && read_valid);\n    assign dmem_res_ur_valid = (read_state_q == R_IOFETCH && read_valid);\n\n    assign imem_res_data = read_data;\n    assign dmem_res_r_data = read_data;\n    assign dmem_res_ur_data = read_data[LINE_WIDTH - 1:LINE_WIDTH - DATA_WIDTH];\n\n    always_comb begin\n        logic local_read_valid;\n\n        axi_arvalid = axi_arvalid_q;\n        axi_arlen = axi_arlen_q;\n        axi_arprot = axi_arprot_q;\n        axi_arid = axi_arid_q;\n        axi_araddr = axi_araddr_q;\n\n        read_data = read_data_q;\n        read_fault = read_fault_q;\n\n        read_state = read_state_q;\n\n        local_read_valid = 0;\n\n        if (axi_arready_q && axi_arvalid_q) begin\n            axi_arvalid = 0;\n            read_fault = 0;\n        end\n\n        case (read_state)\n        R_IFETCH, R_DFETCH, R_IOFETCH:\n            if (axi_rvalid && axi_rready) begin\n                read_data = {axi_rdata, read_data[LINE_WIDTH - 1:AXI_DATA_WIDTH]};\n                if (axi_rresp[1]) begin\n                    read_fault = 1;\n                end\n\n                if (axi_rlast) begin\n                    read_state = R_IDLE;\n                    local_read_valid = 1;\n                end\n            end\n        default:\n            if (!axi_arvalid && !reset_q && (imem_req_valid || dmem_req_r_valid || dmem_req_ur_valid)) begin\n                axi_arvalid = 1;\n                // TODO also set axi_arcache\n                if (imem_req_valid) begin\n                    axi_arid = AXI_IMEM_ID;\n                    axi_arprot = 3'b111; // insn, non-secure, priviliged\n                    axi_araddr = imem_req_addr;\n                    axi_arlen = (LINE_WIDTH / AXI_DATA_WIDTH) - 1;\n                    read_state = R_IFETCH;\n                end else if (dmem_req_r_valid) begin\n                    axi_arid = AXI_DMEM_ID;\n                    axi_arprot = 3'b011; // data, non-secure, priviliged\n                    axi_araddr = dmem_req_r_addr;\n                    axi_arlen = (LINE_WIDTH / AXI_DATA_WIDTH) - 1;\n                    read_state = R_DFETCH;\n                end else begin\n                    axi_arid = AXI_IO_ID;\n                    axi_arprot = 3'b011; // data, non-secure, priviliged\n                    axi_araddr = dmem_req_ur_addr;\n                    axi_arlen = 0;\n                    read_state = R_IOFETCH;\n                end\n            end\n        endcase\n\n        if (reset) begin\n            axi_arvalid = 0;\n            read_state = R_IDLE;\n        end\n\n        read_valid = local_read_valid;\n    end\n\n    // handle writes\n\n    typedef enum {\n        W_IDLE,\n        W_DSTORE,\n        W_IOSTORE\n    } write_state_t;\n\n    write_state_t write_state, write_state_q;\n\n    assign axi_awregion = 0; // not used\n    assign axi_awlock = 0; // not used\n    assign axi_awcache = 4'b1111; // not used, TODO also support uncached accesses\n    assign axi_awqos = 0; // not used\n    assign axi_awuser = 0; // not used\n\n    assign axi_awsize = $clog2(AXI_DATA_WIDTH / 8); // always use full bus width\n    assign axi_awburst = 2'b01; // always incr\n    assign axi_wuser = 0; // not used\n    assign axi_bready = 1; // always ready\n\n    logic axi_awready_q, axi_awvalid_q;\n    logic [7:0] axi_awlen_q;\n    logic [2:0] axi_awprot_q;\n    logic [AXI_ID_WIDTH-1:0] axi_awid_q;\n    logic [AXI_ADDRESS_WIDTH-1:0] axi_awaddr_q;\n\n    logic [$clog2(LINE_WIDTH / AXI_DATA_WIDTH):0] wvalid_counter, wvalid_counter_q;\n    logic axi_wready_q;\n    logic [AXI_STRB_WIDTH-1:0] axi_wstrb_q;\n\n    logic [LINE_WIDTH-1:0] wdata_shiftreg, wdata_shiftreg_q;\n\n    logic axi_bvalid_q;\n\n    assign axi_wvalid = wvalid_counter != 0;\n    assign axi_wlast = wvalid_counter == 1;\n\n    assign axi_wdata = wdata_shiftreg[AXI_DATA_WIDTH-1:0];\n\n    always_ff @(posedge clock) begin\n        axi_awready_q <= axi_awready;\n\n        axi_awvalid_q <= axi_awvalid;\n        axi_awlen_q <= axi_awlen;\n        axi_awprot_q <= axi_awprot;\n        axi_awid_q <= axi_awid;\n        axi_awaddr_q <= axi_awaddr;\n\n        axi_wready_q <= axi_wready;\n        axi_wstrb_q <= axi_wstrb;\n\n        axi_bvalid_q <= axi_bvalid;\n\n        wvalid_counter_q <= wvalid_counter;\n        wdata_shiftreg_q <= wdata_shiftreg;\n\n        write_state_q <= write_state;\n    end\n\n    assign dmem_res_w_valid = write_state_q == W_DSTORE && axi_bready && axi_bvalid;\n    assign dmem_res_uw_valid = write_state_q == W_IOSTORE && axi_bready && axi_bvalid;\n\n    // We ignore write responses / write faults for now as our cache will never\n    // write something it hasn't successfully read before\n    assign dmem_res_w_fault = 0;\n\n    assign dmem_res_uw_fault = axi_bresp[1]; // TODO double check\n\n    always_comb begin\n        axi_awvalid = axi_awvalid_q;\n        axi_awlen = axi_awlen_q;\n        axi_awprot = axi_awprot_q;\n        axi_awid = axi_awid_q;\n        axi_awaddr = axi_awaddr_q;\n\n        axi_wstrb = axi_wstrb_q;\n\n        wvalid_counter = wvalid_counter_q;\n        wdata_shiftreg = wdata_shiftreg_q;\n\n        write_state = write_state_q;\n\n        if (axi_awready_q && axi_awvalid_q) begin\n            axi_awvalid = 0;\n        end\n\n        if (axi_wready_q && (wvalid_counter_q != 0)) begin\n            wvalid_counter -= 1;\n            wdata_shiftreg = {{AXI_DATA_WIDTH{1'b0}}, wdata_shiftreg[LINE_WIDTH-1:AXI_DATA_WIDTH]};\n\n        end\n\n        if (axi_bvalid_q) begin\n            write_state = W_IDLE;\n        end\n\n        if (write_state == W_IDLE && !axi_awvalid && wvalid_counter == 0 && (dmem_req_w_valid || dmem_req_uw_valid)) begin\n            axi_awvalid = 1;\n            if (dmem_req_w_valid) begin\n                wvalid_counter = LINE_WIDTH / AXI_DATA_WIDTH;\n                axi_awlen = wvalid_counter - 1;\n                axi_awid = AXI_DMEM_ID;\n                axi_awprot = 3'b011; // data, non-secure, priviliged\n                axi_awaddr = dmem_req_w_addr;\n                wdata_shiftreg = dmem_req_w_data;\n                axi_wstrb = '1;\n                write_state = W_DSTORE;\n            end else begin\n                wvalid_counter = 1;\n                axi_awlen = wvalid_counter - 1;\n                axi_awid = AXI_IO_ID;\n                axi_awprot = 3'b011; // data, non-secure, priviliged\n                axi_awaddr = dmem_req_uw_addr;\n                wdata_shiftreg = dmem_req_uw_data;\n                axi_wstrb = dmem_req_uw_strb;\n                write_state = W_IOSTORE;\n            end\n        end\n\n        if (reset) begin\n            axi_awvalid = 0;\n            wvalid_counter = 0;\n            write_state = W_IDLE;\n        end\n    end\n\nendmodule\n"
  },
  {
    "path": "cores/nerv/axi_cache/nerv_axi_cache_dcache.sv",
    "content": "// Direct mapped, write-back/write-allocate AXI cache for the NERV core.\n//\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n`default_nettype none\n\n// Read/write data cache.\n//\n// This implements the instruction cache. It directly uses NERV's native\n// interface on the core side but uses a simple internal interface that\n// transfers whole cache lines on the bus side. Translating this into AXI is\n// done using `nerv_axi_cache_axi` which together with this and the data cache\n// is wrapped by `nerv_axi_cache`.\n//\n// See `nerv_axi_cache` for parameter descriptions.\nmodule nerv_axi_cache_dcache #(\n    parameter ADDRESS_WIDTH = 32,\n    parameter DATA_SIZE = 2,\n    parameter LINE_SIZE = 5,\n    parameter INDEX_SIZE = 4,\n\n    localparam DATA_WIDTH = 8 << DATA_SIZE,\n    localparam LINE_WIDTH = 8 << LINE_SIZE,\n    localparam LINE_COUNT = 1 << INDEX_SIZE\n) (\n    input wire                       clock,\n    input wire                       reset,\n\n    input wire                       stalled,\n    output var                       stall,\n\n    input wire                       dmem_valid,\n    input wire [ADDRESS_WIDTH-1:0]   dmem_addr,\n    input wire [DATA_WIDTH/8-1:0]    dmem_wstrb,\n    input wire [DATA_WIDTH-1:0]      dmem_wdata,\n    output var [DATA_WIDTH-1:0]      dmem_rdata,\n    output var                       dmem_fault,\n\n    output var [ADDRESS_WIDTH-1:0]   req_r_addr,\n    output var                       req_r_valid,\n\n    input wire [LINE_WIDTH-1:0]      res_r_data,\n    input wire                       res_r_fault,\n    input wire                       res_r_valid,\n\n    output var [ADDRESS_WIDTH-1:0]   req_w_addr,\n    output var [LINE_WIDTH-1:0]      req_w_data,\n    output var                       req_w_valid,\n\n    input wire                       res_w_fault,\n    input wire                       res_w_valid\n);\n\n    typedef logic [ADDRESS_WIDTH-1:0] addr_t;\n    typedef logic [ADDRESS_WIDTH-LINE_SIZE-1:0] line_addr_t;\n    typedef logic [LINE_WIDTH-1:0] line_t;\n    typedef logic [INDEX_SIZE-1:0] index_t;\n    typedef logic [ADDRESS_WIDTH-LINE_SIZE-INDEX_SIZE-1:0] tag_t;\n\n    // cache memory\n\n    line_addr_t cache_line_addr_rd;\n    (*keep*) line_addr_t cache_line_addr_wr;\n\n    index_t cache_index_rd, cache_index_rd_q;\n    tag_t cache_tag_rd, cache_tag_rd_q;\n\n    index_t cache_index_wr;\n    tag_t cache_tag_wr;\n\n    assign {cache_tag_rd,   cache_index_rd  } = cache_line_addr_rd;\n    assign {cache_tag_wr,   cache_index_wr  } = cache_line_addr_wr;\n\n    line_t cache_data_mem [0:LINE_COUNT-1];\n    tag_t cache_tag_mem [0:LINE_COUNT-1];\n    logic [LINE_COUNT-1:0] cache_valid_mem;\n    logic [LINE_COUNT-1:0] cache_dirty_mem;\n\n    line_t cache_data_out, cache_data_out_q;\n    tag_t cache_tag_out;\n    logic cache_valid_out;\n    logic cache_dirty_out;\n\n    assign cache_data_out = cache_data_mem[cache_index_rd];\n    assign cache_tag_out = cache_tag_mem[cache_index_rd];\n    assign cache_valid_out = cache_valid_mem[cache_index_rd];\n    assign cache_dirty_out = cache_dirty_mem[cache_index_rd];\n\n    line_t cache_data_in;\n    logic cache_valid_in;\n    logic cache_dirty_in;\n\n    always @(posedge clock) begin\n        cache_data_out_q <= cache_data_out;\n\n        cache_data_mem[cache_index_wr] <= cache_data_in;\n        cache_tag_mem[cache_index_wr] <= cache_tag_wr;\n        cache_valid_mem[cache_index_wr] <= cache_valid_in;\n        cache_dirty_mem[cache_index_wr] <= cache_dirty_in;\n\n        if (reset) begin\n            cache_valid_mem <= 0;\n            cache_dirty_mem <= 0;\n        end\n    end\n\n    // cache last dmem interface values while the core is stalled\n\n    addr_t stable_addr, stable_addr_q;\n    logic [DATA_WIDTH/8-1:0] stable_wstrb;\n    logic [DATA_WIDTH/8-1:0] stable_wstrb_q;\n    logic [DATA_WIDTH-1:0] stable_wdata;\n    logic [DATA_WIDTH-1:0] stable_wdata_q;\n    logic stable_valid, stable_valid_q;\n    logic stalled_q;\n\n    always_ff @(posedge clock) begin\n        stable_addr_q <= stable_addr;\n        stable_wstrb_q <= stable_wstrb;\n        stable_wdata_q <= stable_wdata;\n        stable_valid_q <= stable_valid;\n        stalled_q <= stalled;\n    end\n\n    always_comb begin\n        stable_addr = stable_addr_q;\n        stable_wstrb = stable_wstrb_q;\n        stable_wdata = stable_wdata_q;\n        stable_valid = stable_valid_q;\n        if (!stalled && dmem_valid) begin\n            stable_addr = dmem_addr;\n            stable_wdata = dmem_wdata;\n            stable_wstrb = dmem_wstrb;\n        end\n        if (!stalled) begin\n            stable_valid = dmem_valid;\n        end\n    end\n\n    // fast path for read and write hits\n\n    wire line_addr_t line_addr = stable_addr[ADDRESS_WIDTH-1:LINE_SIZE];\n    wire line_addr_t line_addr_q = stable_addr_q[ADDRESS_WIDTH-1:LINE_SIZE];\n\n    assign cache_line_addr_rd = line_addr;\n    assign cache_line_addr_wr = line_addr;\n\n    wire logic [LINE_SIZE-DATA_SIZE-1:0] line_subaddr = stable_addr[LINE_SIZE-1:DATA_SIZE];\n    wire logic [LINE_SIZE-DATA_SIZE-1:0] line_subaddr_q = stable_addr_q[LINE_SIZE-1:DATA_SIZE];\n\n    line_t dmem_rdata_line, dmem_rdata_line_q;\n    logic dmem_next_fault, dmem_next_fault_q;\n\n    always_ff @(posedge clock) begin\n        dmem_rdata_line_q <= dmem_rdata_line;\n        dmem_next_fault_q <= dmem_next_fault;\n    end\n\n    assign dmem_rdata_line = cache_data_in;\n\n    assign dmem_rdata = dmem_rdata_line_q[line_subaddr_q * DATA_WIDTH +: DATA_WIDTH];\n\n    assign dmem_fault = dmem_next_fault_q;\n\n    wire logic cache_hit = (cache_tag_out == cache_tag_rd && cache_valid_out);\n    wire logic cache_miss = (stable_valid && !cache_hit);\n\n    logic cache_hit_q, cache_miss_q;\n\n    wire logic cache_writeback = (cache_miss  && cache_dirty_out && cache_valid_out);\n\n    always_ff @(posedge clock) begin\n        cache_hit_q <= cache_hit && !reset;\n        cache_miss_q <= cache_miss && !reset;\n    end\n\n    always_comb begin\n        dmem_next_fault = dmem_next_fault_q && stalled;\n\n        cache_data_in = cache_data_out;\n        cache_dirty_in = cache_dirty_out;\n        cache_valid_in = cache_hit;\n\n        // inject fetched data\n        if (res_r_valid) begin\n            cache_data_in = res_r_data;\n            cache_dirty_in = 0;\n            cache_valid_in = !res_r_fault;\n            dmem_next_fault = res_r_fault;\n        end\n\n        for (int i = 0; i < DATA_WIDTH / 8; i++) begin\n            if (stable_valid && stable_wstrb[i]) begin\n                cache_dirty_in = 1;\n                cache_data_in[line_subaddr * DATA_WIDTH + 8 * i +: 8] =\n                    stable_wdata[8 * i +: 8];\n            end\n        end\n\n        if (reset) begin\n            dmem_next_fault = 0;\n        end\n    end\n\n    // fetch misses and perform writebacks\n\n    assign req_r_addr = {cache_line_addr_rd, {LINE_SIZE{1'b0}}};\n\n    addr_t req_w_addr_q;\n    line_t req_w_data_q;\n    logic req_w_valid_q;\n    logic req_r_valid_q;\n    logic res_w_valid_q;\n    logic res_r_valid_q;\n\n    always_ff @(posedge clock) begin\n        req_w_addr_q <= req_w_addr;\n        req_w_data_q <= req_w_data;\n        req_w_valid_q <= req_w_valid;\n        req_r_valid_q <= req_r_valid;\n        res_w_valid_q <= res_w_valid;\n        res_r_valid_q <= res_r_valid;\n    end\n\n    assign stall = (cache_miss_q && !dmem_next_fault_q) || req_w_valid_q;\n\n    always_comb begin\n        req_w_valid = req_w_valid_q;\n        req_w_data = req_w_data_q;\n        req_w_addr = req_w_addr_q;\n\n        req_r_valid = req_r_valid_q;\n\n        if (res_r_valid_q) begin\n            req_r_valid = 0;\n        end\n\n        if (cache_miss && !stalled) begin\n            req_r_valid = 1;\n        end\n\n        if (res_w_valid_q) begin\n            req_w_valid = 0;\n        end\n\n        if (cache_writeback && !stalled) begin\n            req_w_valid = 1;\n            req_w_addr = {cache_tag_out, cache_index_rd, {LINE_SIZE{1'b0}}};\n            req_w_data = cache_data_out;\n        end\n\n        if (reset) begin\n            req_w_valid = 0;\n            req_r_valid = 0;\n        end\n    end\nendmodule\n"
  },
  {
    "path": "cores/nerv/axi_cache/nerv_axi_cache_icache.sv",
    "content": "// Direct mapped, write-back/write-allocate AXI cache for the NERV core.\n//\n// Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n//\n// Permission to use, copy, modify, and/or distribute this software for any\n// purpose with or without fee is hereby granted, provided that the above\n// copyright notice and this permission notice appear in all copies.\n//\n// THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n`default_nettype none\n\n// Read only instruction cache.\n//\n// This implements the instruction cache. It directly uses NERV's native\n// interface on the core side but uses a simple internal interface that\n// transfers whole cache lines on the bus side. Translating this into AXI is\n// done using `nerv_axi_cache_axi` which together with this and the data cache\n// is wrapped by `nerv_axi_cache`.\n//\n// See `nerv_axi_cache` for parameter descriptions.\nmodule nerv_axi_cache_icache #(\n    parameter ADDRESS_WIDTH = 32,\n    parameter INSN_SIZE = 2,\n    parameter LINE_SIZE = 3,\n    parameter INDEX_SIZE = 2,\n\n    localparam INSN_WIDTH = 8 << INSN_SIZE,\n    localparam LINE_WIDTH = 8 << LINE_SIZE,\n    localparam LINE_COUNT = 1 << INDEX_SIZE\n) (\n    input wire                       clock,\n    input wire                       reset,\n\n    input wire                       stalled,\n    output var                       stall,\n\n    input wire [ADDRESS_WIDTH-1:0]   imem_addr,\n    output var [INSN_WIDTH-1:0]      imem_data,\n    output var                       imem_fault,\n\n    output var [ADDRESS_WIDTH-1:0]   req_addr,\n    output var                       req_valid,\n\n    input wire [LINE_WIDTH-1:0]      res_data,\n    input wire                       res_fault,\n    input wire                       res_valid\n);\n\n    typedef logic [ADDRESS_WIDTH-1:0] addr_t;\n    typedef logic [ADDRESS_WIDTH-LINE_SIZE-1:0] line_addr_t;\n    typedef logic [LINE_WIDTH-1:0] line_t;\n    typedef logic [INDEX_SIZE-1:0] index_t;\n    typedef logic [ADDRESS_WIDTH-LINE_SIZE-INDEX_SIZE-1:0] tag_t;\n\n    // cache memory\n\n    line_addr_t cache_line_addr_rd;\n    (*keep*) line_addr_t cache_line_addr_wr;\n\n    index_t cache_index_rd, cache_index_rd_q;\n    tag_t cache_tag_rd, cache_tag_rd_q;\n\n    index_t cache_index_wr;\n    tag_t cache_tag_wr;\n\n    assign {cache_tag_rd,   cache_index_rd  } = cache_line_addr_rd;\n    assign {cache_tag_wr,   cache_index_wr  } = cache_line_addr_wr;\n\n    line_t cache_data_mem [0:LINE_COUNT-1];\n    tag_t cache_tag_mem [0:LINE_COUNT-1];\n    logic [LINE_COUNT-1:0] cache_valid_mem;\n    logic [LINE_COUNT-1:0] cache_dirty_mem;\n\n    line_t cache_data_out, cache_data_out_q;\n    tag_t cache_tag_out;\n    logic cache_valid_out;\n    logic cache_dirty_out;\n\n    assign cache_data_out = cache_data_mem[cache_index_rd];\n    assign cache_tag_out = cache_tag_mem[cache_index_rd];\n    assign cache_valid_out = cache_valid_mem[cache_index_rd];\n    assign cache_dirty_out = cache_dirty_mem[cache_index_rd];\n\n    line_t cache_data_in;\n    logic cache_valid_in;\n    logic cache_dirty_in;\n\n    always @(posedge clock) begin\n        cache_data_out_q <= cache_data_out;\n\n        cache_data_mem[cache_index_wr] <= cache_data_in;\n        cache_tag_mem[cache_index_wr] <= cache_tag_wr;\n        cache_valid_mem[cache_index_wr] <= cache_valid_in;\n        cache_dirty_mem[cache_index_wr] <= cache_dirty_in;\n\n        if (reset) begin\n            cache_valid_mem <= 0;\n            cache_dirty_mem <= 0;\n        end\n    end\n\n    // cache last imem interface values while the core is stalled\n\n    addr_t stable_addr, stable_addr_q;\n    logic stable_valid, stable_valid_q;\n    logic stalled_q;\n\n    always_ff @(posedge clock) begin\n        stable_addr_q <= stable_addr;\n        stable_valid_q <= stable_valid;\n        stalled_q <= stalled;\n    end\n\n    always_comb begin\n        stable_addr = stable_addr_q;\n        stable_valid = stable_valid_q;\n        if (!stalled) begin\n            stable_addr = imem_addr;\n            stable_valid = 1;\n        end\n    end\n\n    // fast path for read and write hits\n\n    wire line_addr_t line_addr = stable_addr[ADDRESS_WIDTH-1:LINE_SIZE];\n    wire line_addr_t line_addr_q = stable_addr_q[ADDRESS_WIDTH-1:LINE_SIZE];\n\n    assign cache_line_addr_rd = line_addr;\n    assign cache_line_addr_wr = line_addr;\n\n    wire logic [LINE_SIZE-INSN_SIZE-1:0] line_subaddr = stable_addr[LINE_SIZE-1:INSN_SIZE];\n    wire logic [LINE_SIZE-INSN_SIZE-1:0] line_subaddr_q = stable_addr_q[LINE_SIZE-1:INSN_SIZE];\n\n    line_t imem_data_line, imem_data_line_q;\n    logic imem_next_fault, imem_next_fault_q;\n\n    always_ff @(posedge clock) begin\n        imem_data_line_q <= imem_data_line;\n        imem_next_fault_q <= imem_next_fault;\n    end\n\n    assign imem_data_line = cache_data_in;\n\n    assign imem_data = imem_data_line_q[line_subaddr_q * INSN_WIDTH +: INSN_WIDTH];\n\n    assign imem_fault = imem_next_fault_q;\n\n    wire logic cache_hit = (cache_tag_out == cache_tag_rd && cache_valid_out);\n    wire logic cache_miss = (stable_valid && !cache_hit);\n\n    logic cache_hit_q, cache_miss_q;\n\n    wire logic cache_writeback = (cache_miss  && cache_dirty_out && cache_valid_out);\n\n    always_ff @(posedge clock) begin\n        cache_hit_q <= cache_hit && !reset;\n        cache_miss_q <= cache_miss && !reset;\n    end\n\n    always_comb begin\n        imem_next_fault = imem_next_fault_q && stalled;\n\n        cache_data_in = cache_data_out;\n        cache_dirty_in = cache_dirty_out;\n        cache_valid_in = cache_hit;\n\n        // inject fetched data\n        if (res_valid) begin\n            cache_data_in = res_data;\n            cache_dirty_in = 0;\n            cache_valid_in = !res_fault;\n            imem_next_fault = res_fault;\n        end\n\n        if (reset) begin\n            imem_next_fault = 0;\n        end\n    end\n\n    assign stall = cache_miss_q && !imem_next_fault_q;\n\n    // fetch misses\n\n    assign req_addr = {cache_line_addr_rd, {LINE_SIZE{1'b0}}};\n\n    logic req_valid_q, res_valid_q;\n\n    always_ff @(posedge clock) begin\n        req_valid_q <= req_valid;\n        res_valid_q <= res_valid;\n    end\n\n    always_comb begin\n        req_valid = req_valid_q;\n\n        if (res_valid_q) begin\n            req_valid = 0;\n        end\n\n        if (cache_miss && !stalled) begin\n            req_valid = 1;\n        end\n\n        if (reset) begin\n            req_valid = 0;\n        end\n    end\n\nendmodule\n"
  },
  {
    "path": "cores/nerv/axi_cache/testbench_axi.sv",
    "content": "// Testbench using the AXI4 interface\n/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  N. Engelhardt <nak@yosyshq.com>\n *  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule testbench;\n\nlocalparam MEM_ADDR_WIDTH = 16;\nlocalparam TIMEOUT = (1<<14);\n\nreg clock;\nreg reset = 1'b1;\nreg stall = 1'b0;\nwire trap;\n\nwire [31:0] imem_addr;\nwire [31:0] imem_data;\nwire        imem_fault;\n\nwire        dmem_valid;\nwire [31:0] dmem_addr;\nwire [ 3:0] dmem_wstrb;\nwire [31:0] dmem_wdata;\nreg  [31:0] dmem_rdata;\nwire        dmem_fault;\n\nreg  [31:0] irq; initial irq = 0;\n\nalways #5 clock = clock === 1'b0;\nalways @(posedge clock) reset <= 0;\n\nreg [7:0] mem [0:(1<<MEM_ADDR_WIDTH)-1];\n\nwire wr_in_mem_range = (dmem_addr[31:2] < (1<<MEM_ADDR_WIDTH));\nwire wr_in_output = (dmem_addr == 32'h 02000000);\n\nreg [31:0] out;\nreg out_valid = 0;\n\nint stall_counter = 0;\nint nonstall_counter = 0;\n\nalways @(posedge clock) begin\n\tif (stalled)\n\t\tstall_counter <= stall_counter + 1;\n\telse\n\t\tnonstall_counter <= nonstall_counter + 1;\n\n\tif (out_valid) begin\n\t\tif (out[8]) begin $display(\"%d %d\", nonstall_counter, stall_counter); $finish(); end;\n\t\t$write(\"%c\", out[7:0]);\n\t\tif (out[7:0] == \"\\n\")\n\t\t\t$write(\"%d %d: \", nonstall_counter, stall_counter);\n`ifndef VERILATOR\n\t\t$fflush();\n`endif\n\tend\nend\n\n`ifdef STALL\nalways @(posedge clock) begin\n\tstall <= $random;\nend\n`endif\n\nalways @(posedge clock) begin\n\tif (imem_addr >= (1<<MEM_ADDR_WIDTH)) begin\n\t\t$display(\"Memory access out of range: imem_addr = 0x%08x\", imem_addr);\n\tend\n\tif (dmem_valid && !(wr_in_mem_range || wr_in_output)) begin\n\t\t$display(\"Memory access out of range: dmem_addr = 0x%08x\", dmem_addr);\n\tend\nend\n\ninteger i;\nalways @(posedge clock) begin\n\tout <= 32'h 0;\n\tout_valid <= 1'b0;\n\tif (!stalled && !reset) begin\n\t\tif (dmem_valid) begin\n\t\t\tfor (i=0;i<4;i=i+1) begin\n\t\t\t\tif (dmem_wstrb[i]) begin\n\t\t\t\t\tif (wr_in_output) begin\n\t\t\t\t\t\tout[(i*8)+: 8] <= dmem_wdata[(i*8)+: 8];\n\t\t\t\t\t\tout_valid <= 1'b1;\n\t\t\t\t\tend;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nend\n\ninitial begin\n\t$readmemh(\"firmware.hex\", mem);\n\tif ($test$plusargs(\"vcd\")) begin\n\t\t$dumpfile(\"testbench_axi.vcd\");\n\t\t$dumpvars(0, testbench);\n\tend\nend\n\nwire cache_stall;\n\nwire stalled = stall || cache_stall;\n\nlocalparam AXI_DATA_WIDTH = 32;\n\nlocalparam AXI_ADDRESS_WIDTH = 32;\nlocalparam AXI_ID_WIDTH = 1;\nlocalparam AXI_AWUSER_WIDTH = 1;\nlocalparam AXI_WUSER_WIDTH = 1;\nlocalparam AXI_BUSER_WIDTH = 1;\nlocalparam AXI_ARUSER_WIDTH = 1;\nlocalparam AXI_RUSER_WIDTH = 1;\nlocalparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;\n\nlogic [AXI_ID_WIDTH-1:0]       axi_awid;\nlogic [AXI_ADDRESS_WIDTH-1:0]  axi_awaddr;\nlogic [3:0]                    axi_awregion;\nlogic [7:0]                    axi_awlen;\nlogic [2:0]                    axi_awsize;\nlogic [1:0]                    axi_awburst;\nlogic                          axi_awlock;\nlogic [3:0]                    axi_awcache;\nlogic [2:0]                    axi_awprot;\nlogic [3:0]                    axi_awqos;\nlogic [AXI_AWUSER_WIDTH-1:0]   axi_awuser;\nlogic                          axi_awvalid;\nlogic                          axi_awready;\n// Write Data Channel (W)\nlogic [AXI_DATA_WIDTH-1:0]     axi_wdata;\nlogic [AXI_STRB_WIDTH-1:0]     axi_wstrb;\nlogic                          axi_wlast;\nlogic [AXI_WUSER_WIDTH-1:0]    axi_wuser;\nlogic                          axi_wvalid;\nlogic                          axi_wready;\n// Write Response Channel (B)\nlogic [AXI_ID_WIDTH-1:0]       axi_bid;\nlogic [1:0]                    axi_bresp;\nlogic [AXI_BUSER_WIDTH-1:0]    axi_buser;\nlogic                          axi_bvalid;\nlogic                          axi_bready;\n// Read Address Channel (AR)\nlogic [AXI_ID_WIDTH-1:0]       axi_arid;\nlogic [AXI_ADDRESS_WIDTH-1:0]  axi_araddr;\nlogic [3:0]                    axi_arregion;\nlogic [7:0]                    axi_arlen;\nlogic [2:0]                    axi_arsize;\nlogic [1:0]                    axi_arburst;\nlogic                          axi_arlock;\nlogic [3:0]                    axi_arcache;\nlogic [2:0]                    axi_arprot;\nlogic [3:0]                    axi_arqos;\nlogic [AXI_ARUSER_WIDTH-1:0]   axi_aruser;\nlogic                          axi_arvalid;\nlogic                          axi_arready;\n// Read Data Channel (R)\nlogic [AXI_ID_WIDTH-1:0]       axi_rid;\nlogic [AXI_DATA_WIDTH-1:0]     axi_rdata;\nlogic [1:0]                    axi_rresp;\nlogic                          axi_rlast;\nlogic [AXI_RUSER_WIDTH-1:0]    axi_ruser;\nlogic                          axi_rvalid;\nlogic                          axi_rready;\n\n\naxi_ram #(\n\t.ID_WIDTH(1)\n) ram (\n\t.clk(clock),\n\t.rst(reset),\n\t// Write Address Channel (AW)\n\t.s_axi_awid(axi_awid),\n\t.s_axi_awaddr(axi_awaddr[15:0]),\n\t.s_axi_awlen(axi_awlen),\n\t.s_axi_awsize(axi_awsize),\n\t.s_axi_awburst(axi_awburst),\n\t.s_axi_awlock(axi_awlock),\n\t.s_axi_awcache(axi_awcache),\n\t.s_axi_awprot(axi_awprot),\n\t.s_axi_awvalid(axi_awvalid),\n\t.s_axi_awready(axi_awready),\n\t// Write Data Channel (W)\n\t.s_axi_wdata(axi_wdata),\n\t.s_axi_wstrb(axi_wstrb),\n\t.s_axi_wlast(axi_wlast),\n\t.s_axi_wvalid(axi_wvalid),\n\t.s_axi_wready(axi_wready),\n\t// Write Response Channel (B)\n\t.s_axi_bid(axi_bid),\n\t.s_axi_bresp(axi_bresp),\n\t.s_axi_bvalid(axi_bvalid),\n\t.s_axi_bready(axi_bready),\n\t// Read Address Channel (AR)\n\t.s_axi_arid(axi_arid),\n\t.s_axi_araddr(axi_araddr[15:0]),\n\t.s_axi_arlen(axi_arlen),\n\t.s_axi_arsize(axi_arsize),\n\t.s_axi_arburst(axi_arburst),\n\t.s_axi_arlock(axi_arlock),\n\t.s_axi_arcache(axi_arcache),\n\t.s_axi_arprot(axi_arprot),\n\t.s_axi_arvalid(axi_arvalid),\n\t.s_axi_arready(axi_arready),\n\t// Read Data Channel (R)\n\t.s_axi_rid(axi_rid),\n\t.s_axi_rdata(axi_rdata),\n\t.s_axi_rresp(axi_rresp),\n\t.s_axi_rlast(axi_rlast),\n\t.s_axi_rvalid(axi_rvalid),\n\t.s_axi_rready(axi_rready)\n);\n\ninitial begin\n\t#1;\n\tfor (int i = 0; i < (1<<MEM_ADDR_WIDTH) / 4; i++) begin\n\t\tram.mem[i] = 0;\n\n\t\tfor (int j = 0; j < 4; j++) begin\n\t\t\tram.mem[i][j * 8 +: 8] = mem[i * 4 + j];\n\t\tend\n\tend\nend\n\nlogic inject_fault = 0;\n\n`ifdef INJECT_FAULT\nalways @(posedge clock) begin\n\tinject_fault <= $random < (32'hffff_ffff / 200);\nend\n`endif\n\nnerv_axi_cache cache (\n\t.clock(clock),\n\t.reset(reset),\n\n\t.stalled(stalled),\n\t.stall(cache_stall),\n\n\t.imem_addr(imem_addr),\n\t.imem_data(imem_data),\n\t.imem_fault(imem_fault),\n\n\t.dmem_valid(dmem_valid && wr_in_mem_range),\n\t.dmem_addr(dmem_addr),\n\t.dmem_wstrb(dmem_wstrb),\n\t.dmem_wdata(dmem_wdata),\n\t.dmem_rdata(dmem_rdata),\n\t.dmem_fault(dmem_fault),\n\n\t.dmem_io(1'b1),\n\n\t// Write Address Channel (AW)\n\t.axi_awid(axi_awid),\n\t.axi_awaddr(axi_awaddr),\n\t.axi_awregion(axi_awregion),\n\t.axi_awlen(axi_awlen),\n\t.axi_awsize(axi_awsize),\n\t.axi_awburst(axi_awburst),\n\t.axi_awlock(axi_awlock),\n\t.axi_awcache(axi_awcache),\n\t.axi_awprot(axi_awprot),\n\t.axi_awqos(axi_awqos),\n\t.axi_awuser(axi_awuser),\n\t.axi_awvalid(axi_awvalid),\n\t.axi_awready(axi_awready),\n\t// Write Data Channel (W)\n\t.axi_wdata(axi_wdata),\n\t.axi_wstrb(axi_wstrb),\n\t.axi_wlast(axi_wlast),\n\t.axi_wuser(axi_wuser),\n\t.axi_wvalid(axi_wvalid),\n\t.axi_wready(axi_wready),\n\t// Write Response Channel (B)\n\t.axi_bid(axi_bid),\n\t.axi_bresp(axi_bresp),\n\t.axi_buser(axi_buser),\n\t.axi_bvalid(axi_bvalid),\n\t.axi_bready(axi_bready),\n\t// Read Address Channel (AR)\n\t.axi_arid(axi_arid),\n\t.axi_araddr(axi_araddr),\n\t.axi_arregion(axi_arregion),\n\t.axi_arlen(axi_arlen),\n\t.axi_arsize(axi_arsize),\n\t.axi_arburst(axi_arburst),\n\t.axi_arlock(axi_arlock),\n\t.axi_arcache(axi_arcache),\n\t.axi_arprot(axi_arprot),\n\t.axi_arqos(axi_arqos),\n\t.axi_aruser(axi_aruser),\n\t.axi_arvalid(axi_arvalid),\n\t.axi_arready(axi_arready),\n\t// Read Data Channel (R)\n\t.axi_rid(axi_rid),\n\t.axi_rdata(axi_rdata),\n\t.axi_rresp(axi_rresp | {inject_fault && !axi_arprot[2], 1'b0}),\n\t.axi_rlast(axi_rlast),\n\t.axi_ruser(axi_ruser),\n\t.axi_rvalid(axi_rvalid),\n\t.axi_rready(axi_rready)\n);\n\n\nnerv dut (\n\t.clock(clock),\n\t.reset(reset),\n\t.stall(stalled),\n\t.trap(trap),\n\n\t.imem_addr(imem_addr),\n\t.imem_data(stalled ? 32'bx : imem_data),\n\n\t.dmem_valid(dmem_valid),\n\t.dmem_addr(dmem_addr),\n\t.dmem_wstrb(dmem_wstrb),\n\t.dmem_wdata(dmem_wdata),\n\t.dmem_rdata(stalled ? 32'bx : dmem_rdata),\n\n`ifdef NERV_FAULT\n\t.imem_fault(imem_fault),\n\t.dmem_fault(dmem_fault),\n`endif\n\n\t.irq(irq)\n);\n\nreg [31:0] cycles = 0;\n\nalways @(posedge clock) begin\n\tcycles <= cycles + 32'h1;\n\tif (trap || (cycles >= TIMEOUT)) begin\n\t\t$display(\"Simulated %0d cycles\", cycles);\n\t\t$finish;\n\tend\nend\n\nendmodule\n"
  },
  {
    "path": "cores/nerv/axi_cache/testbench_internal.sv",
    "content": "// Testbench using the internal bus side interface\n/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  N. Engelhardt <nak@yosyshq.com>\n *  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule testbench;\n\nlocalparam MEM_ADDR_WIDTH = 16;\nlocalparam TIMEOUT = (1<<14);\n\nreg clock;\nreg reset = 1'b1;\nreg stall = 1'b0;\nwire trap;\n\nwire [31:0] imem_addr;\nwire [31:0] imem_data;\n\nwire        dmem_valid;\nwire [31:0] dmem_addr;\nwire [ 3:0] dmem_wstrb;\nwire [31:0] dmem_wdata;\nreg  [31:0] dmem_rdata;\n\nreg  [31:0] irq; initial irq = 0;\n\nalways #5 clock = clock === 1'b0;\nalways @(posedge clock) reset <= 0;\n\nreg [7:0] mem [0:(1<<MEM_ADDR_WIDTH)-1];\n\nwire wr_in_mem_range = (dmem_addr[31:2] < (1<<MEM_ADDR_WIDTH));\nwire wr_in_output = (dmem_addr == 32'h 02000000);\n\nreg [31:0] out;\nreg out_valid = 0;\n\nint stall_counter = 0;\nint nonstall_counter = 0;\n\nalways @(posedge clock) begin\n\tif (stalled)\n\t\tstall_counter <= stall_counter + 1;\n\telse\n\t\tnonstall_counter <= nonstall_counter + 1;\n\n\tif (out_valid) begin\n\t\tif (out[8]) begin $display(\"%d %d\", nonstall_counter, stall_counter); $finish(); end;\n\t\t$write(\"%c\", out[7:0]);\n\t\tif (out[7:0] == \"\\n\")\n\t\t\t$write(\"%d %d: \", nonstall_counter, stall_counter);\n`ifndef VERILATOR\n\t\t$fflush();\n`endif\n\tend\nend\n\n`ifdef STALL\nalways @(posedge clock) begin\n\tstall <= $random;\nend\n`endif\n\nalways @(posedge clock) begin\n\tif (imem_addr >= (1<<MEM_ADDR_WIDTH)) begin\n\t\t$display(\"Memory access out of range: imem_addr = 0x%08x\", imem_addr);\n\tend\n\tif (dmem_valid && !(wr_in_mem_range || wr_in_output)) begin\n\t\t$display(\"Memory access out of range: dmem_addr = 0x%08x\", dmem_addr);\n\tend\nend\n\ninteger i;\nalways @(posedge clock) begin\n\tout <= 32'h 0;\n\tout_valid <= 1'b0;\n\tif (!stalled && !reset) begin\n\t\tif (dmem_valid) begin\n\t\t\tfor (i=0;i<4;i=i+1) begin\n\t\t\t\tif (dmem_wstrb[i]) begin\n\t\t\t\t\tif (wr_in_output) begin\n\t\t\t\t\t\tout[(i*8)+: 8] <= dmem_wdata[(i*8)+: 8];\n\t\t\t\t\t\tout_valid <= 1'b1;\n\t\t\t\t\tend\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\n\timem_res_valid <= 0;\n\tif (imem_req_valid) begin\n\t\tfor (int i = 0; i < 32; i++) begin\n\t\t\timem_res_data[i * 8 +: 8] <= mem[imem_req_addr ^ i];\n\t\tend\n`ifdef STALL\n\t\trepeat ($random() & 3) @(posedge clock);\n`endif\n\t\timem_res_valid <= 1;\n\tend\n\n\tdmem_res_r_valid <= 0;\n\tif (dmem_req_r_valid) begin\n\t\tfor (int i = 0; i < 32; i++) begin\n\t\t\tdmem_res_r_data[i * 8 +: 8] <= mem[dmem_req_r_addr ^ i];\n\t\tend\n`ifdef STALL\n\t\trepeat ($random() & 3) @(posedge clock);\n`endif\n\t\tdmem_res_r_valid <= 1;\n\tend\n\n\tdmem_res_w_valid <= 0;\n\tif (dmem_req_w_valid) begin\n\t\tfor (int i = 0; i < 32; i++) begin\n\t\t\tmem[dmem_req_w_addr ^ i] <= dmem_req_w_data[i * 8 +: 8];\n\t\tend\n`ifdef STALL\n\t\trepeat ($random() & 3) @(posedge clock);\n`endif\n\t\tdmem_res_w_valid <= 1;\n\tend\nend\n\ninitial begin\n\t$readmemh(\"firmware.hex\", mem);\n\tif ($test$plusargs(\"vcd\")) begin\n\t\t$dumpfile(\"testbench_internal.vcd\");\n\t\t$dumpvars(0, testbench);\n\tend\nend\n\nwire icache_stall, dcache_stall;\n\nwire stalled = stall || icache_stall || dcache_stall;\n\nwire [31:0] imem_req_addr;\nwire imem_req_valid;\n\nreg [255:0] imem_res_data;\nreg imem_res_fault = 0;\nreg imem_res_valid = 0;\n\n\nwire [31:0] dmem_req_r_addr;\nwire dmem_req_r_valid;\n\nreg [255:0] dmem_res_r_data;\nreg dmem_res_r_fault = 0;\nreg dmem_res_r_valid = 0;\n\nwire [31:0] dmem_req_w_addr;\nwire [255:0] dmem_req_w_data;\nwire dmem_req_w_valid;\n\nreg dmem_res_w_fault = 0;\nreg dmem_res_w_valid = 0;\n\nnerv_axi_cache_icache #(.LINE_SIZE(5), .INDEX_SIZE(4)) icache (\n\t.clock(clock),\n\t.reset(reset),\n\n\t.stalled(stalled),\n\t.stall(icache_stall),\n\n\t.imem_addr(imem_addr),\n\t.imem_data(imem_data),\n\n\t.req_addr(imem_req_addr),\n\t.req_valid(imem_req_valid),\n\n\t.res_data(imem_res_data),\n\t.res_fault(imem_res_fault),\n\t.res_valid(imem_res_valid)\n\n);\n\nnerv_axi_cache_dcache #(.LINE_SIZE(5), .INDEX_SIZE(1)) dcache (\n\t.clock(clock),\n\t.reset(reset),\n\n\t.stalled(stalled),\n\t.stall(dcache_stall),\n\n\t.dmem_valid(dmem_valid && wr_in_mem_range),\n\t.dmem_addr(dmem_addr),\n\t.dmem_wstrb(dmem_wstrb),\n\t.dmem_wdata(dmem_wdata),\n\t.dmem_rdata(dmem_rdata),\n\n\t.req_r_addr(dmem_req_r_addr),\n\t.req_r_valid(dmem_req_r_valid),\n\n\t.res_r_data(dmem_res_r_data),\n\t.res_r_fault(dmem_res_r_fault),\n\t.res_r_valid(dmem_res_r_valid),\n\n\t.req_w_addr(dmem_req_w_addr),\n\t.req_w_data(dmem_req_w_data),\n\t.req_w_valid(dmem_req_w_valid),\n\n\t.res_w_fault(dmem_res_w_fault),\n\t.res_w_valid(dmem_res_w_valid)\n\n);\n\nnerv dut (\n\t.clock(clock),\n\t.reset(reset),\n\t.stall(stalled),\n\t.trap(trap),\n\n\t.imem_addr(imem_addr),\n\t.imem_data(stalled ? 32'bx : imem_data),\n\n\t.dmem_valid(dmem_valid),\n\t.dmem_addr(dmem_addr),\n\t.dmem_wstrb(dmem_wstrb),\n\t.dmem_wdata(dmem_wdata),\n\t.dmem_rdata(stalled ? 32'bx : dmem_rdata),\n\n`ifdef NERV_FAULT\n\t.imem_fault(1'b0),\n\t.dmem_fault(1'b0),\n`endif\n\n\t.irq(irq)\n);\n\nreg [31:0] cycles = 0;\n\nalways @(posedge clock) begin\n\tcycles <= cycles + 32'h1;\n\tif (trap || (cycles >= TIMEOUT)) begin\n\t\t$display(\"Simulated %0d cycles\", cycles);\n\t\t$finish;\n\tend\nend\n\nendmodule\n"
  },
  {
    "path": "cores/nerv/axi_cache/verify_axi.sby",
    "content": "[tasks]\nprove\ncover\n\n[options]\nprove: mode prove\ncover: mode cover\n\n# The cache's AXI interface is too simple to cover everything SVA-AXI-FVIP's\n# can check for\ncover: expect fail\n\n[engines]\nprove: abc pdr\ncover: smtbmc boolector\n\n[script]\n\nverific -set-ignore VERI-1875\n\n# Read packages first\n# This one should be alwyas read first\nread -sv amba_axi4_protocol_checker_pkg.sv\n# Then the rest of them\nread -sv amba_axi4_single_interface_requirements.sv\nread -sv amba_axi4_definition_of_axi4_lite.sv\nread -sv amba_axi4_atomic_accesses.sv\nread -sv amba_axi4_transaction_structure.sv\nread -sv amba_axi4_transaction_attributes.sv\nread -sv amba_axi4_low_power_interface.sv\nread -sv amba_axi4_low_power_channel.sv\n\n# This is a checker, not a package\nread -sv amba_axi4_write_response_dependencies.sv\nread -sv amba_axi4_exclusive_access_source_perspective.sv\n\n# The modules containing the properties\nread -sv amba_axi4_protocol_checker.sv\nread -sv amba_axi4_read_address_channel.sv\nread -sv amba_axi4_read_data_channel.sv\nread -sv amba_axi4_write_data_channel.sv\nread -sv amba_axi4_write_response_channel.sv\nread -sv amba_axi4_write_address_channel.sv\n\n# Then the dut\nread -sv nerv_axi_cache_icache.sv nerv_axi_cache_dcache.sv nerv_axi_cache.sv\n\n# The bind file\nread -sv verify_axi.sv\n\n# Elaborate\nprep -top nerv_axi_cache\n\n[files]\n# Packages\nSVA-AXI4-FVIP/AXI4/src/amba_axi4_protocol_checker_pkg.sv\nSVA-AXI4-FVIP/AXI4/src/amba_axi4_low_power_channel.sv\nSVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_single_interface_requirements.sv\nSVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_definition_of_axi4_lite.sv\nSVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_atomic_accesses.sv\nSVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_transaction_structure.sv\nSVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_transaction_attributes.sv\nSVA-AXI4-FVIP/AXI4/src/axi4_spec/amba_axi4_low_power_interface.sv\nSVA-AXI4-FVIP/AXI4/src/axi4_lib/amba_axi4_write_response_dependencies.sv\nSVA-AXI4-FVIP/AXI4/src/axi4_lib/amba_axi4_exclusive_access_source_perspective.sv\n\n# Modules containing the properties\nSVA-AXI4-FVIP/AXI4/src/amba_axi4_protocol_checker.sv\nSVA-AXI4-FVIP/AXI4/src/amba_axi4_read_address_channel.sv\nSVA-AXI4-FVIP/AXI4/src/amba_axi4_read_data_channel.sv\nSVA-AXI4-FVIP/AXI4/src/amba_axi4_write_data_channel.sv\nSVA-AXI4-FVIP/AXI4/src/amba_axi4_write_response_channel.sv\nSVA-AXI4-FVIP/AXI4/src/amba_axi4_write_address_channel.sv\n\n# Bind file\nverify_axi.sv\n\n# # DUT\nnerv_axi_cache_icache.sv\nnerv_axi_cache_dcache.sv\nnerv_axi_cache.sv\n"
  },
  {
    "path": "cores/nerv/axi_cache/verify_axi.sv",
    "content": "`default_nettype none\n\nmodule resetgen(input wire clock, input wire reset, input wire axi_arvalid, input wire axi_arready);\n    initial assume(reset);\nendmodule\n\nbind nerv_axi_cache resetgen resetgen(.*);\n\nbind nerv_axi_cache amba_axi4_protocol_checker\n  #('{ID_WIDTH:          1,\n      ADDRESS_WIDTH:     32,\n      DATA_WIDTH:        32,\n      AWUSER_WIDTH:      1,\n      WUSER_WIDTH:       1,\n      BUSER_WIDTH:       1,\n      ARUSER_WIDTH:      1,\n      RUSER_WIDTH:       1,\n      MAX_WR_BURSTS:     1,\n      MAX_RD_BURSTS:     1,\n      MAX_WR_LENGTH:     2,\n      MAX_RD_LENGTH:     2,\n      MAXWAIT:           5,\n      VERIFY_AGENT_TYPE: amba_axi4_protocol_checker_pkg::SOURCE,\n      PROTOCOL_TYPE:     amba_axi4_protocol_checker_pkg::AXI4FULL,\n      INTERFACE_REQS:    1,\n      ENABLE_COVER:      1,\n      ENABLE_XPROP:      0,\n      ARM_RECOMMENDED:   1,\n      CHECK_PARAMETERS:  1,\n      OPTIONAL_WSTRB:    0,\n      FULL_WR_STRB:      1,\n      OPTIONAL_RESET:    1,\n      EXCLUSIVE_ACCESS:  0,\n      OPTIONAL_LP:       0})\ndest_check (\n        .ACLK(clock),\n        .ARESETn(!reset),\n\n        .AWID(axi_awid),\n        .AWADDR(axi_awaddr),\n        .AWREGION(axi_awregion),\n        .AWLEN(axi_awlen),\n        .AWSIZE(axi_awsize),\n        .AWBURST(axi_awburst),\n        .AWLOCK(axi_awlock),\n        .AWCACHE(axi_awcache),\n        .AWPROT(axi_awprot),\n        .AWQOS(axi_awqos),\n        .AWVALID(axi_awvalid),\n        .AWREADY(axi_awready),\n        .AWUSER(axi_awuser),\n\n        .WDATA(axi_wdata),\n        .WSTRB(axi_wstrb),\n        .WLAST(axi_wlast),\n        .WVALID(axi_wvalid),\n        .WREADY(axi_wready),\n        .WUSER(axi_wuser),\n\n        .BID(axi_bid),\n        .BRESP(axi_bresp),\n        .BVALID(axi_bvalid),\n        .BREADY(axi_bready),\n        .BUSER(axi_buser),\n\n        .ARID(axi_arid),\n        .ARADDR(axi_araddr),\n        .ARREGION(axi_arregion),\n        .ARLEN(axi_arlen),\n        .ARSIZE(axi_arsize),\n        .ARBURST(axi_arburst),\n        .ARLOCK(axi_arlock),\n        .ARCACHE(axi_arcache),\n        .ARPROT(axi_arprot),\n        .ARQOS(axi_arqos),\n        .ARVALID(axi_arvalid),\n        .ARREADY(axi_arready),\n        .ARUSER(axi_aruser),\n\n        .RID(axi_rid),\n        .RDATA(axi_rdata),\n        .RRESP(axi_rresp),\n        .RLAST(axi_rlast),\n        .RVALID(axi_rvalid),\n        .RREADY(axi_rready),\n        .RUSER(axi_ruser),\n\n        .CSYSREQ(1'b1),\n        .CSYSACK(1'b1),\n        .CACTIVE(1'b1)\n        );\n"
  },
  {
    "path": "cores/nerv/axi_cache/wrapper_axi.sv",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n`default_nettype wire\n\nmodule rvfi_wrapper (\n\tinput         clock,\n\tinput         reset,\n\t`RVFI_OUTPUTS\n\t`RVFI_BUS_OUTPUTS\n);\n\t(* keep *) `rvformal_rand_reg random_stall;\n\twire cache_stall;\n\n\t(* keep *) `rvformal_rand_reg [31:0] random_imem_data;\n\n\twire [31:0] imem_addr;\n\twire [31:0] imem_data;\n\twire        imem_fault;\n\n\twire        dmem_valid;\n\twire [31:0] dmem_addr;\n\twire [ 3:0] dmem_wstrb;\n\twire [31:0] dmem_wdata;\n\twire [31:0] dmem_rdata;\n\twire        dmem_fault;\n\n\twire stall = random_stall || cache_stall;\n\n\twire trap;\n\n\tnerv #(\n\t) uut (\n\t\t.clock      (clock    ),\n\t\t.reset      (reset    ),\n\t\t.stall      (stall    ),\n\t\t.trap       (trap     ),\n\n\t\t.imem_addr  (imem_addr ),\n\t\t.imem_data  (imem_data ),\n\n\t\t.dmem_valid (dmem_valid),\n\t\t.dmem_addr  (dmem_addr ),\n\t\t.dmem_wstrb (dmem_wstrb),\n\t\t.dmem_wdata (dmem_wdata),\n\t\t.dmem_rdata (dmem_rdata),\n\n`ifdef NERV_FAULT\n\t\t.imem_fault (imem_fault),\n\t\t.dmem_fault (dmem_fault),\n`endif\n\n\t\t.irq (0),\n\n\t\t`RVFI_CONN32\n\t);\n\n\tlocalparam AXI_DATA_WIDTH = 32;\n\tlocalparam AXI_ADDRESS_WIDTH = 32;\n\tlocalparam AXI_ID_WIDTH = 1;\n\tlocalparam AXI_AWUSER_WIDTH = 1;\n\tlocalparam AXI_WUSER_WIDTH = 1;\n\tlocalparam AXI_BUSER_WIDTH = 1;\n\tlocalparam AXI_ARUSER_WIDTH = 1;\n\tlocalparam AXI_RUSER_WIDTH = 1;\n\tlocalparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;\n\n\twire [AXI_ID_WIDTH-1:0]       axi_awid;\n\twire [AXI_ADDRESS_WIDTH-1:0]  axi_awaddr;\n\twire [3:0]                    axi_awregion;\n\twire [7:0]                    axi_awlen;\n\twire [2:0]                    axi_awsize;\n\twire [1:0]                    axi_awburst;\n\twire                          axi_awlock;\n\twire [3:0]                    axi_awcache;\n\twire [2:0]                    axi_awprot;\n\twire [3:0]                    axi_awqos;\n\twire [AXI_AWUSER_WIDTH-1:0]   axi_awuser;\n\twire                          axi_awvalid;\n\twire                          axi_awready;\n\t// Write Data Channel (W)\n\twire [AXI_DATA_WIDTH-1:0]     axi_wdata;\n\twire [AXI_STRB_WIDTH-1:0]     axi_wstrb;\n\twire                          axi_wlast;\n\twire [AXI_WUSER_WIDTH-1:0]    axi_wuser;\n\twire                          axi_wvalid;\n\twire                          axi_wready;\n\t// Write Response Channel (B)\n\twire [AXI_ID_WIDTH-1:0]       axi_bid;\n\twire [1:0]                    axi_bresp;\n\twire [AXI_BUSER_WIDTH-1:0]    axi_buser;\n\twire                          axi_bvalid;\n\twire                          axi_bready;\n\t// Read Address Channel (AR)\n\twire [AXI_ID_WIDTH-1:0]       axi_arid;\n\twire [AXI_ADDRESS_WIDTH-1:0]  axi_araddr;\n\twire [3:0]                    axi_arregion;\n\twire [7:0]                    axi_arlen;\n\twire [2:0]                    axi_arsize;\n\twire [1:0]                    axi_arburst;\n\twire                          axi_arlock;\n\twire [3:0]                    axi_arcache;\n\twire [2:0]                    axi_arprot;\n\twire [3:0]                    axi_arqos;\n\twire [AXI_ARUSER_WIDTH-1:0]   axi_aruser;\n\twire                          axi_arvalid;\n\twire                          axi_arready;\n\t// Read Data Channel (R)\n\twire [AXI_ID_WIDTH-1:0]       axi_rid;\n\twire [AXI_DATA_WIDTH-1:0]     axi_rdata;\n\twire [1:0]                    axi_rresp;\n\twire                          axi_rlast;\n\twire [AXI_RUSER_WIDTH-1:0]    axi_ruser;\n\twire                          axi_rvalid;\n\twire                          axi_rready;\n\n`ifndef RISCV_FORMAL_MEM_FAULT\n\talways @* assume(!axi_rresp[1]);\n\talways @* assume(!axi_bresp[1]);\n`endif\n\n\tnerv_axi_cache #(\n\t\t.AXI_DATA_WIDTH(AXI_DATA_WIDTH),\n\t\t.LINE_SIZE(3),\n\t\t.ICACHE_INDEX_SIZE(1),\n\t\t.DCACHE_INDEX_SIZE(1)\n\t) cache (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\n\t\t.stalled(stall),\n\t\t.stall(cache_stall),\n\n\t\t.imem_addr(imem_addr),\n\t\t.imem_data(imem_data),\n\t\t.imem_fault(imem_fault),\n\n\t\t.dmem_valid(dmem_valid),\n\t\t.dmem_addr(dmem_addr),\n\t\t.dmem_wstrb(dmem_wstrb),\n\t\t.dmem_wdata(dmem_wdata),\n\t\t.dmem_rdata(dmem_rdata),\n\t\t.dmem_fault(dmem_fault),\n\n\t\t.dmem_io(dmem_addr[31:16] == 16'h1234),\n\n\t\t// Write Address Channel (AW)\n\t\t.axi_awid(axi_awid),\n\t\t.axi_awaddr(axi_awaddr),\n\t\t.axi_awregion(axi_awregion),\n\t\t.axi_awlen(axi_awlen),\n\t\t.axi_awsize(axi_awsize),\n\t\t.axi_awburst(axi_awburst),\n\t\t.axi_awlock(axi_awlock),\n\t\t.axi_awcache(axi_awcache),\n\t\t.axi_awprot(axi_awprot),\n\t\t.axi_awqos(axi_awqos),\n\t\t.axi_awuser(axi_awuser),\n\t\t.axi_awvalid(axi_awvalid),\n\t\t.axi_awready(axi_awready),\n\t\t// Write Data Channel (W)\n\t\t.axi_wdata(axi_wdata),\n\t\t.axi_wstrb(axi_wstrb),\n\t\t.axi_wlast(axi_wlast),\n\t\t.axi_wuser(axi_wuser),\n\t\t.axi_wvalid(axi_wvalid),\n\t\t.axi_wready(axi_wready),\n\t\t// Write Response Channel (B)\n\t\t.axi_bid(axi_bid),\n\t\t.axi_bresp(axi_bresp),\n\t\t.axi_buser(axi_buser),\n\t\t.axi_bvalid(axi_bvalid),\n\t\t.axi_bready(axi_bready),\n\t\t// Read Address Channel (AR)\n\t\t.axi_arid(axi_arid),\n\t\t.axi_araddr(axi_araddr),\n\t\t.axi_arregion(axi_arregion),\n\t\t.axi_arlen(axi_arlen),\n\t\t.axi_arsize(axi_arsize),\n\t\t.axi_arburst(axi_arburst),\n\t\t.axi_arlock(axi_arlock),\n\t\t.axi_arcache(axi_arcache),\n\t\t.axi_arprot(axi_arprot),\n\t\t.axi_arqos(axi_arqos),\n\t\t.axi_aruser(axi_aruser),\n\t\t.axi_arvalid(axi_arvalid),\n\t\t.axi_arready(axi_arready),\n\t\t// Read Data Channel (R)\n\t\t.axi_rid(axi_rid),\n\t\t.axi_rdata(axi_rdata),\n\t\t.axi_rresp(axi_rresp),\n\t\t.axi_rlast(axi_rlast),\n\t\t.axi_ruser(axi_ruser),\n\t\t.axi_rvalid(axi_rvalid),\n\t\t.axi_rready(axi_rready)\n\t);\n\n`ifdef RISCV_FORMAL_BUS\n\trvfi_bus_axi4_observer_write axi_write (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\n\t\t// Write Address Channel (AW)\n\t\t.axi_awid(axi_awid),\n\t\t.axi_awaddr(axi_awaddr),\n\t\t.axi_awregion(axi_awregion),\n\t\t.axi_awlen(axi_awlen),\n\t\t.axi_awsize(axi_awsize),\n\t\t.axi_awburst(axi_awburst),\n\t\t.axi_awlock(axi_awlock),\n\t\t.axi_awcache(axi_awcache),\n\t\t.axi_awprot(axi_awprot),\n\t\t.axi_awqos(axi_awqos),\n\t\t.axi_awuser(axi_awuser),\n\t\t.axi_awvalid(axi_awvalid),\n\t\t.axi_awready(axi_awready),\n\t\t// Write Data Channel (W)\n\t\t.axi_wdata(axi_wdata),\n\t\t.axi_wstrb(axi_wstrb),\n\t\t.axi_wlast(axi_wlast),\n\t\t.axi_wuser(axi_wuser),\n\t\t.axi_wvalid(axi_wvalid),\n\t\t.axi_wready(axi_wready),\n\t\t// Write Response Channel (B)\n\t\t.axi_bid(axi_bid),\n\t\t.axi_bresp(axi_bresp),\n\t\t.axi_buser(axi_buser),\n\t\t.axi_bvalid(axi_bvalid),\n\t\t.axi_bready(axi_bready)\n\n\t\t`RVFI_BUS_CHANNEL_CONN(0)\n\t);\n\n\n\trvfi_bus_axi4_observer_read axi_read (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\n\t\t// Read Address Channel (AR)\n\t\t.axi_arid(axi_arid),\n\t\t.axi_araddr(axi_araddr),\n\t\t.axi_arregion(axi_arregion),\n\t\t.axi_arlen(axi_arlen),\n\t\t.axi_arsize(axi_arsize),\n\t\t.axi_arburst(axi_arburst),\n\t\t.axi_arlock(axi_arlock),\n\t\t.axi_arcache(axi_arcache),\n\t\t.axi_arprot(axi_arprot),\n\t\t.axi_arqos(axi_arqos),\n\t\t.axi_aruser(axi_aruser),\n\t\t.axi_arvalid(axi_arvalid),\n\t\t.axi_arready(axi_arready),\n\t\t// Read Data Channel (R)\n\t\t.axi_rid(axi_rid),\n\t\t.axi_rdata(axi_rdata),\n\t\t.axi_rresp(axi_rresp),\n\t\t.axi_rlast(axi_rlast),\n\t\t.axi_ruser(axi_ruser),\n\t\t.axi_rvalid(axi_rvalid),\n\t\t.axi_rready(axi_rready)\n\n\t\t`RVFI_BUS_CHANNEL_CONN(1)\n\t);\n`endif\n\n\trvfi_bus_axi4_abstract_read ram_read (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\t\t// Read Address Channel (AR)\n\t\t.axi_arid(axi_arid),\n\t\t.axi_araddr(axi_araddr),\n\t\t.axi_arregion(axi_arregion),\n\t\t.axi_arlen(axi_arlen),\n\t\t.axi_arsize(axi_arsize),\n\t\t.axi_arburst(axi_arburst),\n\t\t.axi_arlock(axi_arlock),\n\t\t.axi_arcache(axi_arcache),\n\t\t.axi_arprot(axi_arprot),\n\t\t.axi_arqos(axi_arqos),\n\t\t.axi_aruser(axi_aruser),\n\t\t.axi_arvalid(axi_arvalid),\n\t\t.axi_arready(axi_arready),\n\t\t// Read Data Channel (R)\n\t\t.axi_rid(axi_rid),\n\t\t.axi_rdata(axi_rdata),\n\t\t.axi_rresp(axi_rresp),\n\t\t.axi_rlast(axi_rlast),\n\t\t.axi_ruser(axi_ruser),\n\t\t.axi_rvalid(axi_rvalid),\n\t\t.axi_rready(axi_rready)\n\t);\n\n\trvfi_bus_axi4_abstract_write ram_write (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\t\t// Write Address Channel (AW)\n\t\t.axi_awid(axi_awid),\n\t\t.axi_awaddr(axi_awaddr),\n\t\t.axi_awregion(axi_awregion),\n\t\t.axi_awlen(axi_awlen),\n\t\t.axi_awsize(axi_awsize),\n\t\t.axi_awburst(axi_awburst),\n\t\t.axi_awlock(axi_awlock),\n\t\t.axi_awcache(axi_awcache),\n\t\t.axi_awprot(axi_awprot),\n\t\t.axi_awqos(axi_awqos),\n\t\t.axi_awuser(axi_awuser),\n\t\t.axi_awvalid(axi_awvalid),\n\t\t.axi_awready(axi_awready),\n\t\t// Write Data Channel (W)\n\t\t.axi_wdata(axi_wdata),\n\t\t.axi_wstrb(axi_wstrb),\n\t\t.axi_wlast(axi_wlast),\n\t\t.axi_wuser(axi_wuser),\n\t\t.axi_wvalid(axi_wvalid),\n\t\t.axi_wready(axi_wready),\n\t\t// Write Response Channel (B)\n\t\t.axi_bid(axi_bid),\n\t\t.axi_bresp(axi_bresp),\n\t\t.axi_buser(axi_buser),\n\t\t.axi_bvalid(axi_bvalid),\n\t\t.axi_bready(axi_bready)\n\t);\n\n`ifdef NERV_FAIRNESS\n\treg [2:0] stalled = 0;\n\talways @(posedge clock) begin\n\t\tstalled <= {stalled, random_stall};\n\t\tassume (~stalled);\n\tend\n`endif\nendmodule\n"
  },
  {
    "path": "cores/nerv/axi_cache/wrapper_internal.sv",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule rvfi_wrapper (\n\tinput         clock,\n\tinput         reset,\n\t`RVFI_OUTPUTS\n\t`RVFI_BUS_OUTPUTS\n);\n\t(* keep *) `rvformal_rand_reg random_stall;\n\t(* keep *) `rvformal_rand_reg [31:0] irq;\n\n\twire imem_fault;\n\twire dmem_fault;\n\n\t(* keep *) wire trap;\n\n\t(* keep *) wire [31:0] imem_addr;\n\t(* keep *) wire [31:0] imem_data;\n\n\t(* keep *) wire        dmem_valid;\n\t(* keep *) wire [31:0] dmem_addr;\n\t(* keep *) wire [ 3:0] dmem_wstrb;\n\t(* keep *) wire [31:0] dmem_wdata;\n\t(* keep *) wire [31:0] dmem_rdata;\n\n\twire icache_stall, dcache_stall;\n\n\twire stall = random_stall || icache_stall || dcache_stall;\n\n\twire [31:0] imem_req_addr;\n\twire imem_req_valid;\n\n\treg [255:0] imem_res_data;\n\treg imem_res_fault;\n\treg imem_res_valid;\n\n\n\twire [31:0] dmem_req_r_addr;\n\twire dmem_req_r_valid;\n\n\treg [255:0] dmem_res_r_data;\n\treg dmem_res_r_fault;\n\treg dmem_res_r_valid;\n\n\twire [31:0] dmem_req_w_addr;\n\twire [255:0] dmem_req_w_data;\n\twire dmem_req_w_valid;\n\n\treg dmem_res_w_fault;\n\treg dmem_res_w_valid;\n\n\tnerv_axi_cache_icache #(.LINE_SIZE(5), .INDEX_SIZE(1)) icache (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\n\t\t.stalled(stall),\n\t\t.stall(icache_stall),\n\n\t\t.imem_addr(imem_addr),\n\t\t.imem_data(imem_data),\n\n\t\t.imem_fault(imem_fault),\n\n\t\t.req_addr(imem_req_addr),\n\t\t.req_valid(imem_req_valid),\n\n\t\t.res_data(imem_res_data),\n\t\t.res_fault(imem_res_fault),\n\t\t.res_valid(imem_res_valid)\n\n\t);\n\n\tnerv_axi_cache_dcache #(.LINE_SIZE(5), .INDEX_SIZE(1)) dcache (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\n\t\t.stalled(stall),\n\t\t.stall(dcache_stall),\n\n\t\t.dmem_valid(dmem_valid),\n\t\t.dmem_addr(dmem_addr),\n\t\t.dmem_wstrb(dmem_wstrb),\n\t\t.dmem_wdata(dmem_wdata),\n\t\t.dmem_rdata(dmem_rdata),\n\n\t\t.dmem_fault(dmem_fault),\n\n\t\t.req_r_addr(dmem_req_r_addr),\n\t\t.req_r_valid(dmem_req_r_valid),\n\n\t\t.res_r_data(dmem_res_r_data),\n\t\t.res_r_fault(dmem_res_r_fault),\n\t\t.res_r_valid(dmem_res_r_valid),\n\n\t\t.req_w_addr(dmem_req_w_addr),\n\t\t.req_w_data(dmem_req_w_data),\n\t\t.req_w_valid(dmem_req_w_valid),\n\n\t\t.res_w_fault(dmem_res_w_fault),\n\t\t.res_w_valid(dmem_res_w_valid)\n\n\t);\n\n\tnerv uut (\n\t\t.clock      (clock    ),\n\t\t.reset      (reset    ),\n\t\t.stall      (stall    ),\n\t\t.trap       (trap     ),\n\n\t\t.imem_addr  (imem_addr ),\n\t\t.imem_data  (imem_data ),\n\n\t\t.dmem_valid (dmem_valid),\n\t\t.dmem_addr  (dmem_addr ),\n\t\t.dmem_wstrb (dmem_wstrb),\n\t\t.dmem_wdata (dmem_wdata),\n\t\t.dmem_rdata (dmem_rdata),\n\n`ifdef NERV_FAULT\n\t\t.imem_fault (imem_fault),\n\t\t.dmem_fault (dmem_fault),\n`endif\n\n\t\t.irq (irq),\n\n\t\t`RVFI_CONN32\n\t);\n\n`ifdef RISCV_FORMAL_BUS\n\n`define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \\\n\t(* keep *) reg [(width) - 1:0] imem_``name; assign rvfi_``name[0 * (width) +: (width)] = imem_``name;\n`RVFI_BUS_SIGNALS\n`undef RISCV_FORMAL_CHANNEL_SIGNAL\n\n`define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \\\n\t(* keep *) reg [(width) - 1:0] dmem_r_``name; assign rvfi_``name[1 * (width) +: (width)] = dmem_r_``name;\n`RVFI_BUS_SIGNALS\n`undef RISCV_FORMAL_CHANNEL_SIGNAL\n\n`define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \\\n\t(* keep *) reg [(width) - 1:0] dmem_w_``name; assign rvfi_``name[2 * (width) +: (width)] = dmem_w_``name;\n`RVFI_BUS_SIGNALS\n`undef RISCV_FORMAL_CHANNEL_SIGNAL\n\n\t(* keep *) `rvformal_rand_reg [`RISCV_FORMAL_BUSLEN-1:0] next_imem_res_data;\n\t(* keep *) `rvformal_rand_reg next_imem_res_fault;\n\t(* keep *) `rvformal_rand_reg next_imem_res_valid;\n\n\tlogic imem_req_valid_q;\n\n\talways @(posedge clock) begin\n\t\timem_res_data <= next_imem_res_data;\n\t\timem_res_fault <= next_imem_res_fault;\n\t\timem_res_valid <= next_imem_res_valid && imem_req_valid && !imem_req_valid_q;\n\t\timem_req_valid_q <= imem_req_valid && !reset;\n\tend\n\n\talways @* begin\n\t\timem_bus_addr  = imem_req_addr;\n\t\timem_bus_insn  = 1;\n\t\timem_bus_data  = 0;\n\t\timem_bus_rmask = {`RISCV_FORMAL_BUSLEN / 8{1'b1}};\n\t\timem_bus_wmask = {`RISCV_FORMAL_BUSLEN / 8{1'b0}};\n\t\timem_bus_rdata = next_imem_res_data;\n\t\timem_bus_wdata = 0;\n\t\timem_bus_fault = next_imem_res_fault;\n\t\timem_bus_valid = next_imem_res_valid && imem_req_valid && !imem_req_valid_q;\n\tend\n\n\t(* keep *) `rvformal_rand_reg [`RISCV_FORMAL_BUSLEN-1:0] next_dmem_res_r_data;\n\t(* keep *) `rvformal_rand_reg next_dmem_res_r_valid;\n\t(* keep *) `rvformal_rand_reg next_dmem_res_r_fault;\n\n\tlogic dmem_req_r_valid_q;\n\n\talways @(posedge clock) begin\n\t\tdmem_res_r_data <= next_dmem_res_r_data;\n\t\tdmem_res_r_fault <= next_dmem_res_r_fault;\n\t\tdmem_res_r_valid <= next_dmem_res_r_valid && dmem_req_r_valid && !dmem_req_r_valid_q;\n\t\tdmem_req_r_valid_q <= dmem_req_r_valid && !reset;\n\tend\n\n\talways @* begin\n\t\tdmem_r_bus_addr  = dmem_req_r_addr;\n\t\tdmem_r_bus_insn  = 0;\n\t\tdmem_r_bus_data  = 1;\n\t\tdmem_r_bus_rmask = {`RISCV_FORMAL_BUSLEN / 8{1'b1}};\n\t\tdmem_r_bus_wmask = {`RISCV_FORMAL_BUSLEN / 8{1'b0}};\n\t\tdmem_r_bus_rdata = next_dmem_res_r_data;\n\t\tdmem_r_bus_wdata = 0;\n\t\tdmem_r_bus_fault = next_dmem_res_r_fault;\n\t\tdmem_r_bus_valid = next_dmem_res_r_valid && dmem_req_r_valid && !dmem_req_r_valid_q;\n\tend\n\n\t(* keep *) `rvformal_rand_reg next_dmem_res_w_valid;\n\t(* keep *) `rvformal_rand_reg next_dmem_res_w_fault;\n\n\n\tlogic dmem_req_w_valid_q;\n\n\talways @(posedge clock) begin\n\t\tdmem_res_w_valid <= next_dmem_res_w_valid && dmem_req_w_valid && !dmem_req_w_valid_q;\n\t\tdmem_res_w_fault <= next_dmem_res_w_fault;\n\t\tdmem_req_w_valid_q <= dmem_req_w_valid && !reset;\n\tend\n\n\talways @* begin\n\t\tdmem_w_bus_addr  = dmem_req_w_addr;\n\t\tdmem_w_bus_insn  = 0;\n\t\tdmem_w_bus_data  = 1;\n\t\tdmem_w_bus_rmask = {`RISCV_FORMAL_BUSLEN / 8{1'b0}};\n\t\tdmem_w_bus_wmask = {`RISCV_FORMAL_BUSLEN / 8{1'b1}};\n\t\tdmem_w_bus_rdata = 0;\n\t\tdmem_w_bus_wdata = dmem_req_w_data;\n\t\tdmem_w_bus_fault = next_dmem_res_w_fault;\n\t\tdmem_w_bus_valid = next_dmem_res_w_valid && dmem_req_w_valid && !dmem_req_w_valid_q;\n\tend\n`endif\n\n`ifdef NERV_FAIRNESS\n\treg [2:0] stalled = 0;\n\talways @(posedge clock) begin\n\t\tstalled <= {stalled, stall};\n\t\tassume (~stalled);\n\tend\n`endif\nendmodule\n"
  },
  {
    "path": "cores/nerv/cexdata.sh",
    "content": "#!/bin/bash\n#\n#  NERV -- Naive Educational RISC-V Processor\n#\n#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n#\n#  Permission to use, copy, modify, and/or distribute this software for any\n#  purpose with or without fee is hereby granted, provided that the above\n#  copyright notice and this permission notice appear in all copies.\n#\n#  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nset -ex\n\nrm -rf cexdata\nmkdir cexdata\n\nfor x in {checks,testbug[0-9][0-9][0-9]}/*/FAIL; do\n\ttest -f $x || continue\n\tx=${x%/FAIL}\n\ty=${x/\\//_}\n\tcp $x/logfile.txt cexdata/$y.log\n\tif test -f $x/engine_*/trace.vcd; then\n\t\tcp $x/engine_*/trace.vcd cexdata/$y.vcd\n\t\tpython3 disasm.py cexdata/$y.vcd > cexdata/$y.asm\n\tfi\ndone\n\nsed -re '/WARNING|[Ww]arning/ ! d; /\\[VERI-1927\\] .*\\/wrapper.sv:/ d; s/^([^:]|:[^ ])*: //;' checks/*/logfile.txt | sort -Vu > cexdata/warnings.txt\n\nfor x in {checks,testbug[0-9][0-9][0-9]}/*.sby; do\n\ttest -f $x || continue\n\tx=${x%.sby}\n\tif [ -f $x/PASS ]; then\n\t\tprintf \"%-30s %s %10s\\n\" $x \"  pass  \" $(sed '/Elapsed process time/ { s/.*\\]: //; s/ .*//; p; }; d;' $x/logfile.txt)\n\telif [ -f $x/FAIL ]; then\n\t\tprintf \"%-30s %s %10s\\n\" $x \"**FAIL**\" $(sed '/Elapsed process time/ { s/.*\\]: //; s/ .*//; p; }; d;' $x/logfile.txt)\n\telse\n\t\tprintf \"%-30s %s\\n\" $x unknown\n\tfi\ndone | awk '{ print gensub(\":\", \"\", \"g\", $3), $0; }' | sort -n | cut -f2- -d' ' > cexdata/status.txt\n\n"
  },
  {
    "path": "cores/nerv/checks.cfg",
    "content": "#  NERV -- Naive Educational RISC-V Processor\n#\n#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n#\n#  Permission to use, copy, modify, and/or distribute this software for any\n#  purpose with or without fee is hereby granted, provided that the above\n#  copyright notice and this permission notice appear in all copies.\n#\n#  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\n[options]\nisa rv32i\nnbus 2\ncsr_spec 1.12\n\n[depth]\ninsn            10\nreg        5    10\npc_fwd     5    10\npc_bwd     5    10\nunique     1  5 10\ncausal     5    10\ncover      1    10\nill             10\ncsrw            10\ncsr_ill         10\n\nbus_imem            1    10\nbus_imem_fault      1    10\nbus_dmem            1    10\nbus_dmem_fault      1    10\ncsrc_zero  1    5\ncsrc_any   1    5\ncsrc_inc   1    5\ncsrc_const 1    5\ncsrc_upcnt 1    10\ncsrc_hpm   1    10\n\n[sort]\nreg_ch0\nbus_[id]mem(_fault)?_ch0\ninsn_[ls][bhw]u?_ch0\ncsrc_upcnt_(.*)_ch0\n\n[csrs]\nmcycle          upcnt\nminstret        upcnt\nmhpmcounter5    inc\nmhpmevent5      hpm=1\nmhpmevent9      hpm=2\nmhpmevent3      hpm=3\n\n[custom_csrs]\nfc0     m       custom_ro       const=\"32'h dead_beef\"\nbc0     mu      custom          any\n\n[illegal_csrs]\nfff     msu     rw\nf11     m       w\n\n[defines]\n`define YOSYS // Hotfix for older Tabby CAD Releases\n`define NERV_RVFI\n`define NERV_FAULT\n`define RISCV_FORMAL_ALIGNED_MEM\n`define RISCV_FORMAL_MEM_FAULT\n\n\n[defines liveness]\n`define NERV_FAIRNESS\n\n[verilog-files]\n@basedir@/cores/@core@/wrapper.sv\n@basedir@/cores/@core@/@core@.sv\n\n[cover]\nalways @* if (!reset) cover (channel[0].cnt_insns == 2);\nalways @* if (!reset) cover (rvfi_csr_mstatus_rdata[3] != 0 && rvfi_valid == 1);\n"
  },
  {
    "path": "cores/nerv/disasm.py",
    "content": "#!/usr/bin/env python3\n#\n#  NERV -- Naive Educational RISC-V Processor\n#\n#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n#\n#  Permission to use, copy, modify, and/or distribute this software for any\n#  purpose with or without fee is hereby granted, provided that the above\n#  copyright notice and this permission notice appear in all copies.\n#\n#  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nfrom Verilog_VCD.Verilog_VCD import parse_vcd\nfrom os import system\nfrom sys import argv\n\nrvfi_valid = None\nrvfi_order = None\nrvfi_insn = None\n\nfor netinfo in parse_vcd(argv[1]).values():\n    for net in netinfo['nets']:\n        # print(net[\"hier\"], net[\"name\"])\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_valid\":\n            rvfi_valid = netinfo['tv']\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_order\":\n            rvfi_order = netinfo['tv']\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_insn\":\n            rvfi_insn = netinfo['tv']\n\nassert len(rvfi_valid) == len(rvfi_order)\nassert len(rvfi_valid) == len(rvfi_insn)\n\nprog = list()\n\nfor tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn):\n    if tv_valid[1] == '1':\n        prog.append((int(tv_order[1], 2), int(tv_insn[1], 2)))\n\nwith open(\"disasm.s\", \"w\") as f:\n    for tv_order, tv_insn in sorted(prog):\n        if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0:\n            print(\".hword 0x%04x # %d\" % (tv_insn, tv_order), file=f)\n        else:\n            print(\".word 0x%08x # %d\" % (tv_insn, tv_order), file=f)\n\nsystem(\"riscv64-unknown-elf-as -march=rv32i -o disasm.o disasm.s\")\nsystem(\"riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o\")\n\n"
  },
  {
    "path": "cores/nerv/examples/icebreaker/.gitignore",
    "content": "/testbench.vcd\n/firmware.elf\n/firmware.hex\n/testbench\n/*.log\n/design.*"
  },
  {
    "path": "cores/nerv/examples/icebreaker/Makefile",
    "content": "#  NERV -- Naive Educational RISC-V Processor\n#\n#  Copyright (C) 2020  N. Engelhardt <nak@yosyshq.com>\n#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n#\n#  Permission to use, copy, modify, and/or distribute this software for any\n#  purpose with or without fee is hereby granted, provided that the above\n#  copyright notice and this permission notice appear in all copies.\n#\n#  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\nTOOLCHAIN_PREFIX?=riscv64-unknown-elf-\n\ntest: firmware.hex testbench\n\tvvp -N testbench +vcd\n\nfirmware.elf: firmware.s firmware.c\n\t$(TOOLCHAIN_PREFIX)gcc -march=rv32i -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $^\n\nfirmware.hex: firmware.elf\n\t$(TOOLCHAIN_PREFIX)objcopy -O verilog $< /dev/stdout | sed -r 's,(..) (..) (..) (..),\\4\\3\\2\\1,g' > $@\n\ntestbench: testbench.sv ../../nerv.sv ../../nervsoc.sv top.v firmware.hex\n\tiverilog -o testbench -D STALL -D NERV_DBGREGS testbench.sv ../../nerv.sv ../../nervsoc.sv top.v\n\ndesign.json: ../../nerv.sv ../../nervsoc.sv top.v firmware.hex\n\tyosys -l design_ys.log -p 'synth_ice40 -top top -json $@' ../../nerv.sv ../../nervsoc.sv top.v\n\ndesign.asc: design.json icebreaker.pcf\n\tnextpnr-ice40 -l design_pnr.log --up5k --package sg48 --asc design.asc --pcf icebreaker.pcf --json design.json --placer heap\n\ndesign.bin: design.asc\n\ticepack $< $@\n\nprog: design.bin\n\ticeprog $<\n\t\nshow:\n\tgtkwave testbench.vcd testbench.gtkw >> gtkwave.log 2>&1 &\n\nclean:\n\trm -rf firmware.elf firmware.hex testbench testbench.vcd gtkwave.log\n\trm -rf design.json design.asc design.bin design_ys.log design_pnr.log\n"
  },
  {
    "path": "cores/nerv/examples/icebreaker/README.md",
    "content": "# SOC example for iCEBreaker\n\n![iCEBreaker SOC](icebreaker_soc.png)\n\n# Demo\n\nCounts on the 8 LEDs.\n\n```\nmake prog\n```\n\n# SOC\n\nThe SOC instantiates [nervsoc](../../nervsoc.sv).\n\n* [top.v](top.v) Connects clock input and 8 LEDs on the iCEBreaker and provides power on reset\n* [sections.lds](sections.lds) sets flash and ram to 4k each.\n* [firmware.s](firmware.s) initialises registers, copies data section, initialises bss and starts main\n* [firmware.c](firmware.c) flashes the LEDs.\n"
  },
  {
    "path": "cores/nerv/examples/icebreaker/firmware.c",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Miodrag Milanovic <miodrag@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include <stdint.h>\n\nvoid delay(uint32_t count)\n{\n\twhile(count-->0) {\n\t\t__asm__ volatile (\"nop\");\n\t}\n}\n\nint main()\n{\n\tvolatile uint32_t *leds = (void*)0x01000000;\n\t*leds = 0;\n\tuint32_t cnt = 0;\n\twhile(1)\n\t{\n\t\tdelay(100000);\n\t\t*leds = cnt++;\n\t}\n\treturn 0;\n}\n"
  },
  {
    "path": "cores/nerv/examples/icebreaker/firmware.s",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n.section .text\n.global main\n.global _start\n_start:\naddi x1, zero, 0\naddi x2, zero, 0\naddi x3, zero, 0\naddi x4, zero, 0\naddi x5, zero, 0\naddi x6, zero, 0\naddi x7, zero, 0\naddi x8, zero, 0\naddi x9, zero, 0\naddi x10, zero, 0\naddi x11, zero, 0\naddi x12, zero, 0\naddi x13, zero, 0\naddi x14, zero, 0\naddi x15, zero, 0\naddi x16, zero, 0\naddi x17, zero, 0\naddi x18, zero, 0\naddi x19, zero, 0\naddi x20, zero, 0\naddi x21, zero, 0\naddi x22, zero, 0\naddi x23, zero, 0\naddi x24, zero, 0\naddi x25, zero, 0\naddi x26, zero, 0\naddi x27, zero, 0\naddi x28, zero, 0\naddi x29, zero, 0\naddi x30, zero, 0\naddi x31, zero, 0\n\n# copy data section\nla a0, _sidata\nla a1, _sdata\nla a2, _edata\nbge a1, a2, end_init_data\nloop_init_data:\nlw a3, 0(a0)\nsw a3, 0(a1)\naddi a0, a0, 4\naddi a1, a1, 4\nblt a1, a2, loop_init_data\nend_init_data:\n\n# zero-init bss section\nla a0, _sbss\nla a1, _ebss\nbge a0, a1, end_init_bss\nloop_init_bss:\nsw zero, 0(a0)\naddi a0, a0, 4\nblt a0, a1, loop_init_bss\nend_init_bss:\n\n# place SP at the end of RAM\nli sp, 0x00001000\n\n# call main\ncall main\n\n# halt\nebreak\n"
  },
  {
    "path": "cores/nerv/examples/icebreaker/icebreaker.pcf",
    "content": "# 12 MHz clock\nset_io -nowarn CLK        35\n\n# RS232\nset_io -nowarn RX          6\nset_io -nowarn TX          9\n\n# LEDs and Button\nset_io -nowarn BTN_N      10\nset_io -nowarn LEDR_N     11\nset_io -nowarn LEDG_N     37\n\n# RGB LED Driver\nset_io -nowarn LED_RED_N  39\nset_io -nowarn LED_GRN_N  40\nset_io -nowarn LED_BLU_N  41\n\n# SPI Flash\nset_io -nowarn FLASH_SCK  15\nset_io -nowarn FLASH_SSB  16\nset_io -nowarn FLASH_IO0  14\nset_io -nowarn FLASH_IO1  17\nset_io -nowarn FLASH_IO2  12\nset_io -nowarn FLASH_IO3  13\n\n# PMOD 1A\nset_io -nowarn P1A1        4\nset_io -nowarn P1A2        2\nset_io -nowarn P1A3       47\nset_io -nowarn P1A4       45\nset_io -nowarn P1A7        3\nset_io -nowarn P1A8       48\nset_io -nowarn P1A9       46\nset_io -nowarn P1A10      44\n\n# PMOD 1B\nset_io -nowarn P1B1       43\nset_io -nowarn P1B2       38\nset_io -nowarn P1B3       34\nset_io -nowarn P1B4       31\nset_io -nowarn P1B7       42\nset_io -nowarn P1B8       36\nset_io -nowarn P1B9       32\nset_io -nowarn P1B10      28\n\n# PMOD 2\nset_io -nowarn P2_1       27\nset_io -nowarn P2_2       25\nset_io -nowarn P2_3       21\nset_io -nowarn P2_4       19\nset_io -nowarn P2_7       26\nset_io -nowarn P2_8       23\nset_io -nowarn P2_9       20\nset_io -nowarn P2_10      18\n\n# LEDs and Buttons (PMOD 2)\nset_io -nowarn LED1       27\nset_io -nowarn LED2       25\nset_io -nowarn LED3       21\nset_io -nowarn BTN2       19\nset_io -nowarn LED5       26\nset_io -nowarn LED4       23\nset_io -nowarn BTN1       20\nset_io -nowarn BTN3       18\n"
  },
  {
    "path": "cores/nerv/examples/icebreaker/sections.lds",
    "content": "MEMORY\n{\n    FLASH(xr)       : ORIGIN = 0x00000000, LENGTH = 0x001000\n    RAM  (rw)       : ORIGIN = 0x00000000, LENGTH = 0x001000\n}\n\nSECTIONS {\n    /* The program code and other data goes into FLASH */\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           /* .text sections (code) */\n        *(.text*)          /* .text* sections (code) */\n        *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n        *(.srodata)        /* .rodata sections (constants, strings, etc.) */\n        *(.srodata*)       /* .rodata* sections (constants, strings, etc.) */\n        . = ALIGN(4);\n        _etext = .;        /* define a global symbol at end of code */\n        _sidata = _etext;  /* This is used by the startup in order to initialize the .data secion */\n    } >FLASH\n\n\n    /* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. */\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */\n        _ram_start = .;    /* create a global symbol at ram start for garbage collector */\n        . = ALIGN(4);\n        *(.data)           /* .data sections */\n        *(.data*)          /* .data* sections */\n        *(.sdata)           /* .sdata sections */\n        *(.sdata*)          /* .sdata* sections */\n        . = ALIGN(4);\n        _edata = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */\n    } >RAM\n\n    /* Uninitialized data section */\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         /* define a global symbol at bss start; used by startup code */\n        *(.bss)\n        *(.bss*)\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         /* define a global symbol at bss end; used by startup code */\n    } >RAM\n\n    /* this is to define the start of the heap, and make sure we have a minimum size */\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    /* define a global symbol at heap start */\n    } >RAM\n}\n"
  },
  {
    "path": "cores/nerv/examples/icebreaker/testbench.gtkw",
    "content": "[*]\n[*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI\n[*] Tue Nov  3 15:34:10 2020\n[*]\n[dumpfile] \"/home/matt/work/symbiotic/riscv-formal/cores/nerv/examples/icebreaker/testbench.vcd\"\n[dumpfile_mtime] \"Tue Nov  3 15:33:50 2020\"\n[dumpfile_size] 472777\n[savefile] \"/home/matt/work/symbiotic/riscv-formal/cores/nerv/examples/icebreaker/testbench.gtkw\"\n[timestart] 0\n[size] 1920 1015\n[pos] -1 -1\n*-11.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1\n[treeopen] testbench.\n[treeopen] testbench.dut.\n[treeopen] testbench.dut.soc.\n[sst_width] 240\n[signals_width] 286\n[sst_expanded] 1\n[sst_vpaned_height] 289\n@28\ntestbench.LEDR_N\ntestbench.LEDG_N\ntestbench.LED1\ntestbench.LED2\ntestbench.LED3\ntestbench.LED4\ntestbench.LED5\n@201\n-\n@28\ntestbench.clock\n@22\ntestbench.cycles[31:0]\n@200\n-\n@28\ntestbench.dut.soc.clock\n@22\ntestbench.dut.soc.dmem_addr[31:0]\ntestbench.dut.soc.dmem_rdata[31:0]\n@28\ntestbench.dut.soc.dmem_valid\n@22\ntestbench.dut.soc.dmem_wdata[31:0]\ntestbench.dut.soc.dmem_wstrb[3:0]\ntestbench.dut.soc.imem_addr[31:0]\ntestbench.dut.soc.imem_data[31:0]\ntestbench.dut.soc.leds[31:0]\n@28\ntestbench.dut.soc.reset\ntestbench.dut.soc.stall\ntestbench.dut.soc.trap\n[pattern_trace] 1\n[pattern_trace] 0\n"
  },
  {
    "path": "cores/nerv/examples/icebreaker/testbench.sv",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  N. Engelhardt <nak@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule testbench;\n\nlocalparam TIMEOUT = (1<<10);\nreg clock;\n\nwire LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5;\n\nalways #5 clock = clock === 1'b0;\n\ntop dut (\n\t.CLK(clock),\n\t.LEDR_N(LEDR_N),\n\t.LEDG_N(LEDG_N),\n\t.LED1(LED1),\n\t.LED2(LED2),\n\t.LED3(LED3),\n\t.LED4(LED4),\n\t.LED5(LED5)\n);\n\ninitial begin\n\tif ($test$plusargs(\"vcd\")) begin\n\t\t$dumpfile(\"testbench.vcd\");\n\t\t$dumpvars(0, testbench);\n\tend\nend\n\nreg [31:0] cycles = 0;\n\nalways @(posedge clock) begin\n\tcycles <= cycles + 32'h1;\n\tif (cycles >= TIMEOUT) begin\n\t\t$display(\"Simulated %0d cycles\", cycles);\n\t\t$finish;\n\tend\nend\n\nendmodule\n"
  },
  {
    "path": "cores/nerv/examples/icebreaker/top.v",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Miodrag Milanovic <miodrag@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule top(\n\tinput CLK,\n\toutput LEDR_N,\n\toutput LEDG_N,\n\toutput LED1,\n\toutput LED2,\n\toutput LED3,\n\toutput LED4,\n\toutput LED5\n);\n\n// Create reset signal 16 clocks long\nreg reset = 1'b1;\nreg [3:0] reset_cnt = 0;\nalways @(posedge CLK)\nbegin\n\treset <= (reset_cnt != 15);\n\treset_cnt <= reset_cnt + (reset_cnt != 15);\nend\n\n// Map 7 LEDs that exists on icebreaker board\nwire [31:0] leds;\nassign { LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5 } = {~leds[6:5], leds[4:0]};\n\nnervsoc soc (\n\t.clock(CLK),\n\t.reset(reset),\n\t.leds(leds)\n);\n\nendmodule\n"
  },
  {
    "path": "cores/nerv/firmware.c",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nvoid putc(int c)\n{\n\tvolatile char *p = (void*)0x02000000;\n\t*p = c;\n}\n\nvoid puts(char *s)\n{\n\twhile (*s) putc(*(s++));\n}\n\nint main()\n{\n\tputs(\"Hello World!\\n\");\n\tputc(0);\n\treturn 0;\n}\n"
  },
  {
    "path": "cores/nerv/firmware.s",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n.section .text\n.global main\n.global _start\n_start:\naddi x1, zero, 0\naddi x2, zero, 0\naddi x3, zero, 0\naddi x4, zero, 0\naddi x5, zero, 0\naddi x6, zero, 0\naddi x7, zero, 0\naddi x8, zero, 0\naddi x9, zero, 0\naddi x10, zero, 0\naddi x11, zero, 0\naddi x12, zero, 0\naddi x13, zero, 0\naddi x14, zero, 0\naddi x15, zero, 0\naddi x16, zero, 0\naddi x17, zero, 0\naddi x18, zero, 0\naddi x19, zero, 0\naddi x20, zero, 0\naddi x21, zero, 0\naddi x22, zero, 0\naddi x23, zero, 0\naddi x24, zero, 0\naddi x25, zero, 0\naddi x26, zero, 0\naddi x27, zero, 0\naddi x28, zero, 0\naddi x29, zero, 0\naddi x30, zero, 0\naddi x31, zero, 0\n\n# place SP at the end of RAM\nli sp, 0x00010000\n\n# set vector table address and vectored mode\nla a0, __vector_start\nori a0, a0, 0x1\ncsrw mtvec, a0\n\n# enable all interrupts\nli a0, 0xffffffff\ncsrw mie, a0\n\n# set mie bit\ncsrr a0, mstatus\nori a0, a0, 0x8\ncsrw mstatus, a0\n\n# copy data section\nla a0, _sidata\nla a1, _sdata\nla a2, _edata\nbge a1, a2, end_init_data\nloop_init_data:\nlw a3, 0(a0)\nsw a3, 0(a1)\naddi a0, a0, 4\naddi a1, a1, 4\nblt a1, a2, loop_init_data\nend_init_data:\n\n# zero-init bss section\nla a0, _sbss\nla a1, _ebss\nbge a0, a1, end_init_bss\nloop_init_bss:\nsw zero, 0(a0)\naddi a0, a0, 4\nblt a0, a1, loop_init_bss\nend_init_bss:\n\n# call main\ncall main\n\n#ecall\n#wfi\n\n# halt\nebreak\n\nend_of_file:\nj end_of_file\n"
  },
  {
    "path": "cores/nerv/imemcheck.sby",
    "content": "[options]\nmode prove\ndepth 10\n\n[engines]\nsmtbmc bitwuzla\n\n[script]\nread -sv defines.sv rvfi_imem_check.sv imemcheck.sv nerv.sv\nprep -flatten -nordff -top testbench\nchformal -early\n\n[files]\nimemcheck.sv\nnerv.sv\n../../checks/rvfi_macros.vh\n../../checks/rvfi_imem_check.sv\n\n[file defines.sv]\n`define RISCV_FORMAL\n`define RISCV_FORMAL_NRET 1\n`define RISCV_FORMAL_XLEN 32\n`define RISCV_FORMAL_ILEN 32\n`define NERV_RVFI\n`define NERV_FAIRNESS  # Required to make k-induction work\n`define RISCV_FORMAL_ALIGNED_MEM\n`include \"rvfi_macros.vh\"\n"
  },
  {
    "path": "cores/nerv/imemcheck.sv",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule testbench (\n\tinput         clock,\n\t`RVFI_OUTPUTS\n);\n\treg reset = 1;\n\talways @(posedge clock)\n\t\treset <= 0;\n\n\t(* keep *) `rvformal_rand_reg stall;\n\t(* keep *) `rvformal_rand_reg [31:0] imem_data;\n\t(* keep *) `rvformal_rand_reg [31:0] dmem_rdata;\n\n\t(* keep *) wire [31:0] imem_addr;\n\n\t(* keep *) wire        dmem_valid;\n\t(* keep *) wire [31:0] dmem_addr;\n\t(* keep *) wire [ 3:0] dmem_wstrb;\n\t(* keep *) wire [31:0] dmem_wdata;\n\n\twire [31:0] check_imem_addr;\n\twire [15:0] check_imem_data;\n\n\trvfi_imem_check checker_inst (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\t\t.enable(1'b1),\n\t\t.imem_addr(check_imem_addr),\n\t\t.imem_data(check_imem_data),\n\t\t`RVFI_CONN\n\t);\n\n\treg [31:0] imem_addr_q;\n\n\talways @(posedge clock) begin\n\t\timem_addr_q <= imem_addr;\n\tend\n\n\talways @* begin\n\t\tif (!reset && !stall) begin\n\t\t\tif (imem_addr_q == check_imem_addr)\n\t\t\t\tassume(imem_data[15:0] == check_imem_data);\n\t\t\tif (imem_addr_q+2 == check_imem_addr)\n\t\t\t\tassume(imem_data[31:16] == check_imem_data);\n\t\tend\n\tend\n\n\tnerv uut (\n\t\t.clock      (clock    ),\n\t\t.reset      (reset    ),\n\t\t.stall      (stall    ),\n\n\t\t.imem_addr  (imem_addr ),\n\t\t.imem_data  (imem_data ),\n\n\t\t.dmem_valid (dmem_valid),\n\t\t.dmem_addr  (dmem_addr ),\n\t\t.dmem_wstrb (dmem_wstrb),\n\t\t.dmem_wdata (dmem_wdata),\n\t\t.dmem_rdata (dmem_rdata),\n\n\t\t`RVFI_CONN\n\t);\n\n`ifdef NERV_FAIRNESS\n\treg [2:0] stalled = 0;\n\talways @(posedge clock) begin\n\t\tstalled <= {stalled, stall};\n\t\tassume (~stalled);\n\tend\n`endif\nendmodule\n"
  },
  {
    "path": "cores/nerv/nerv.sv",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n`define NERV_CSR\n\n`ifdef NERV_CSR\n\t/**********************\n\t *  CSR DECLARATIONS  *\n\t **********************/\n\n\t// Note: The Memory-Mapped Machine Timers (mtime and timecmp) are not\n\t// part of the processor core itself. It's up to the SoC to provide\n\t// this part of the RISC-V M-Mode Spec.\n\n\t// FIXME: Additional instructions: ECALL, EBREAK, MRET, WFI\n\n`define NERV_MACHINE_CSRS /* Machine Information CSRs */\t\t\t\t\\\n\t/* all of these CSRs are mandatory but can legally be all 0 */\t\t\t\\\n\t`NERV_CSR_VAL_MRO(mvendorid,         12'h F11, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRO(marchid,           12'h F12, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRO(mimpid,            12'h F13, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRO(mhartid,           12'h F14, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRO(mconfigptr,        12'h F15, 32'h 0000_0000)\n\n`define NERV_TRAP_SETUP_CSRS /* Machine Trap Setup CSRs */\t\t\t\t\\\n\t`NERV_CSR_REG_MRW(mstatus,           12'h 300, 32'h 0000_0000)\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* misa can legally return all zeros */\t\t\t\t\t\t\\\n\t`NERV_CSR_REG_MRW(misa,              12'h 301, 32'h 0000_0000)\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* medeleg and mideleg should only exist if S mode is available */\t\t\\\n/*\t`NERV_CSR_REG_MRW(medeleg,           12'h 302, 32'h 0000_0000) */  \t\t\\\n/*\t`NERV_CSR_REG_MRW(mideleg,           12'h 303, 32'h 0000_0000) */  \t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t`NERV_CSR_REG_MRW(mie,               12'h 304, 32'h 0000_0000)\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* mtvec can be implemented as read-only */\t\t\t\t\t\\\n\t`NERV_CSR_REG_MRW(mtvec,             12'h 305, 32'h 0000_0000)\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* mcounteren should only exist if U mode is available */\t\t\t\\\n/*\t`NERV_CSR_REG_MRW(mcounteren,        12'h 306, 32'h 0000_0000) */\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t`NERV_CSR_REG_MRW(mstatush,          12'h 310, 32'h 0000_0000)\n\n`define NERV_TRAP_HANDLING_CSRS /* Machine Trap Handling CSRs */\t\t\t\\\n\t`NERV_CSR_REG_MRW(mscratch,          12'h 340, 32'h 0000_0000)\t \t\t\\\n\t`NERV_CSR_REG_MRW(mepc,              12'h 341, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_REG_MRW(mcause,            12'h 342, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_REG_MRW(mtval,             12'h 343, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_REG_MRW(mip,               12'h 344, 32'h 0000_0000)\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* mtinst and mtval2 added by hypervisor extension */\t\t\t\t\\\n/*\t`NERV_CSR_REG_MRW(mtinst,            12'h 34A, 32'h 0000_0000) */\t\t\\\n/*\t`NERV_CSR_REG_MRW(mtval2,            12'h 34B, 32'h 0000_0000) */\n\n`define NERV_MACHINE_CONFIG_CSRS /* machine configuration CSRs */\t\t\t\\\n\t/* menvcfg should only exist if U mode is available */\t\t\t\t\\\n/*\t`NERV_CSR_REG_MRW(menvcfg,           12'h 30A, 32'h 0000_0000) */\t\t\\\n/*\t`NERV_CSR_REG_MRW(menvcfgh,          12'h 31A, 32'h 0000_0000) */\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* mseccfg not yet fully defined, and is not currently required */\t\t\\\n/*\t`NERV_CSR_REG_MRW(mseccfg,           12'h 747, 32'h 0000_0000) */\t\t\\\n/*\t`NERV_CSR_REG_MRW(mseccfgh,          12'h 757, 32'h 0000_0000) */\n\n`ifdef NERV_PMP\n/* PMP is optional and can be implemented with 0, 16, or 64 address CSRS */\n`define NERV_PMP_CFG_CSRS /* Machine Memory Protection Config CSRs */\t\t\t\\\n\t/* PMP configuration is 8-bits long, */\t\t\t\t\t\t\\\n\t/* so each cfg controls four PMPs in RV32 */\t\t\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg0,           12'h 3A0, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg1,           12'h 3A1, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg2,           12'h 3A2, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg3,           12'h 3A3, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg4,           12'h 3A4, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg5,           12'h 3A5, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg6,           12'h 3A6, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg7,           12'h 3A7, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg8,           12'h 3A8, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg9,           12'h 3A9, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg10,          12'h 3AA, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg11,          12'h 3AB, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg12,          12'h 3AC, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg13,          12'h 3AD, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg14,          12'h 3AE, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpcfg15,          12'h 3AF, 32'h 0000_0000)\n\n`define NERV_PMP_ADDR_CSRS /* Machine Memory Protection Addr CSRs */\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr0,          12'h 3B0, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr1,          12'h 3B1, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr2,          12'h 3B2, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr3,          12'h 3B3, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr4,          12'h 3B4, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr5,          12'h 3B5, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr6,          12'h 3B6, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr7,          12'h 3B7, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr8,          12'h 3B8, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr9,          12'h 3B9, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr10,         12'h 3BA, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr11,         12'h 3BB, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr12,         12'h 3BC, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr13,         12'h 3BD, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr14,         12'h 3BE, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr15,         12'h 3BF, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr16,         12'h 3C0, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr17,         12'h 3C1, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr18,         12'h 3C2, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr19,         12'h 3C3, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr20,         12'h 3C4, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr21,         12'h 3C5, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr22,         12'h 3C6, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr23,         12'h 3C7, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr24,         12'h 3C8, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr25,         12'h 3C9, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr26,         12'h 3CA, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr27,         12'h 3CB, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr28,         12'h 3CC, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr29,         12'h 3CD, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr30,         12'h 3CE, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr31,         12'h 3CF, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr32,         12'h 3D0, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr33,         12'h 3D1, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr34,         12'h 3D2, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr35,         12'h 3D3, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr36,         12'h 3D4, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr37,         12'h 3D5, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr38,         12'h 3D6, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr39,         12'h 3D7, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr40,         12'h 3D8, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr41,         12'h 3D9, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr42,         12'h 3DA, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr43,         12'h 3DB, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr44,         12'h 3DC, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr45,         12'h 3DD, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr46,         12'h 3DE, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr47,         12'h 3DF, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr48,         12'h 3E0, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr49,         12'h 3E1, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr50,         12'h 3E2, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr51,         12'h 3E3, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr52,         12'h 3E4, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr53,         12'h 3E5, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr54,         12'h 3E6, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr55,         12'h 3E7, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr56,         12'h 3E8, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr57,         12'h 3E9, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr58,         12'h 3EA, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr59,         12'h 3EB, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr60,         12'h 3EC, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr61,         12'h 3ED, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr62,         12'h 3EE, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRW(pmpaddr63,         12'h 3EF, 32'h 0000_0000)\n\n`else\n`define NERV_PMP_CFG_CSRS\n`define NERV_PMP_ADDR_CSRS\n`endif\n\n`define NERV_COUNTER_CSRS /* Machine Counter/Timers CSRs */\t\t\t\t\\\n\t`NERV_CSR_ARR_DEF(hpm_counter, 32)\t\t\t\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 0, mcycle,            12'h B00)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 2, minstret,          12'h B02)\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* mhpmcounter3..31 provide hardware performance monitoring */ \t\t\t\\\n\t/* the counted event is defined by the corresponding hpm_event CSR */\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 3,  mhpmcounter3,     12'h B03)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 4,  mhpmcounter4,     12'h B04)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 5,  mhpmcounter5,     12'h B05)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 6,  mhpmcounter6,     12'h B06)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 7,  mhpmcounter7,     12'h B07)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 8,  mhpmcounter8,     12'h B08)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 9,  mhpmcounter9,     12'h B09)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 10, mhpmcounter10,    12'h B0A)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 11, mhpmcounter11,    12'h B0B)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 12, mhpmcounter12,    12'h B0C)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 13, mhpmcounter13,    12'h B0D)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 14, mhpmcounter14,    12'h B0E)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 15, mhpmcounter15,    12'h B0F)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 16, mhpmcounter16,    12'h B10)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 17, mhpmcounter17,    12'h B11)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 18, mhpmcounter18,    12'h B12)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 19, mhpmcounter19,    12'h B13)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 20, mhpmcounter20,    12'h B14)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 21, mhpmcounter21,    12'h B15)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 22, mhpmcounter22,    12'h B16)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 23, mhpmcounter23,    12'h B17)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 24, mhpmcounter24,    12'h B18)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 25, mhpmcounter25,    12'h B19)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 26, mhpmcounter26,    12'h B1A)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 27, mhpmcounter27,    12'h B1B)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 28, mhpmcounter28,    12'h B1C)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 29, mhpmcounter29,    12'h B1D)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 30, mhpmcounter30,    12'h B1E)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counter, 31, mhpmcounter31,    12'h B1F)\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t`NERV_CSR_ARR_DEF(hpm_counterh, 32)\t\t\t\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 0, mcycleh,          12'h B80)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 2, minstreth,        12'h B82)\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 3,  mhpmcounter3h,   12'h B83)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 4,  mhpmcounter4h,   12'h B84)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 5,  mhpmcounter5h,   12'h B85)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 6,  mhpmcounter6h,   12'h B86)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 7,  mhpmcounter7h,   12'h B87)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 8,  mhpmcounter8h,   12'h B88)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 9,  mhpmcounter9h,   12'h B89)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 10, mhpmcounter10h,  12'h B8A)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 11, mhpmcounter11h,  12'h B8B)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 12, mhpmcounter12h,  12'h B8C)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 13, mhpmcounter13h,  12'h B8D)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 14, mhpmcounter14h,  12'h B8E)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 15, mhpmcounter15h,  12'h B8F)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 16, mhpmcounter16h,  12'h B90)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 17, mhpmcounter17h,  12'h B91)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 18, mhpmcounter18h,  12'h B92)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 19, mhpmcounter19h,  12'h B93)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 20, mhpmcounter20h,  12'h B94)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 21, mhpmcounter21h,  12'h B95)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 22, mhpmcounter22h,  12'h B96)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 23, mhpmcounter23h,  12'h B97)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 24, mhpmcounter24h,  12'h B98)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 25, mhpmcounter25h,  12'h B99)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 26, mhpmcounter26h,  12'h B9A)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 27, mhpmcounter27h,  12'h B9B)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 28, mhpmcounter28h,  12'h B9C)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 29, mhpmcounter29h,  12'h B9D)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 30, mhpmcounter30h,  12'h B9E)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_counterh, 31, mhpmcounter31h,  12'h B9F)\t\t\n\n`define NERV_COUNTER_SETUP_CSRS /* Machine Counter Setup CSRs */\t\t\t\\\n\t/* mcountinhibit is optional */\t\t\t\t\t\t\t\\\n/*\t`NERV_CSR_REG_MRW(mcountinhibit,     12'h 320, 32'h 0000_0000) */\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* mhpmevent3..31 select which hardware event the corresponding */\t\t\\\n\t/* mhpmcounter should be triggered by and thus count */\t\t\t\t\\\n\t`NERV_CSR_ARR_DEF(hpm_event, 32)\t\t\t\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 3,  mhpmevent3,         12'h 323)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 4,  mhpmevent4,         12'h 324)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 5,  mhpmevent5,         12'h 325)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 6,  mhpmevent6,         12'h 326)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 7,  mhpmevent7,         12'h 327)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 8,  mhpmevent8,         12'h 328)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 9,  mhpmevent9,         12'h 329)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 10, mhpmevent10,        12'h 32A)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 11, mhpmevent11,        12'h 32B)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 12, mhpmevent12,        12'h 32C)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 13, mhpmevent13,        12'h 32D)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 14, mhpmevent14,        12'h 32E)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 15, mhpmevent15,        12'h 32F)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 16, mhpmevent16,        12'h 330)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 17, mhpmevent17,        12'h 331)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 18, mhpmevent18,        12'h 332)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 19, mhpmevent19,        12'h 333)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 20, mhpmevent20,        12'h 334)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 21, mhpmevent21,        12'h 335)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 22, mhpmevent22,        12'h 336)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 23, mhpmevent23,        12'h 337)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 24, mhpmevent24,        12'h 338)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 25, mhpmevent25,        12'h 339)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 26, mhpmevent26,        12'h 33A)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 27, mhpmevent27,        12'h 33B)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 28, mhpmevent28,        12'h 33C)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 29, mhpmevent29,        12'h 33D)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 30, mhpmevent30,        12'h 33E)\t\t\t\\\n\t`NERV_CSR_ARR_MRW(hpm_event, 31, mhpmevent31,        12'h 33F)\n \n`define NERV_CUSTOM_CSRS /* Custom CSR for testing */\t\t\t\t\t\\\n\t`NERV_CSR_REG_MRW(custom,            12'h BC0, 32'h 0000_0000)\t\t\t\\\n\t`NERV_CSR_VAL_MRO(custom_ro,         12'h FC0, 32'h dead_beef)\n\n`define NERV_CSRS\t\t\t\\\n\t`NERV_MACHINE_CSRS\t\t\\\n\t`NERV_TRAP_SETUP_CSRS\t\t\\\n\t`NERV_TRAP_HANDLING_CSRS\t\\\n\t`NERV_MACHINE_CONFIG_CSRS\t\\\n\t`NERV_PMP_CFG_CSRS\t\t\\\n\t`NERV_PMP_ADDR_CSRS\t\t\\\n\t`NERV_COUNTER_CSRS\t\t\\\n\t`NERV_COUNTER_SETUP_CSRS\t\\\n\t`NERV_CUSTOM_CSRS\n`endif\n\nmodule nerv #(\n\tparameter [31:0] RESET_ADDR = 32'h 0000_0000,\n\tparameter integer NUMREGS = 32\n) (\n\tinput clock,\n\tinput reset,\n\tinput stall,\n\toutput trap,\n\n`ifdef NERV_RVFI\n\toutput reg        rvfi_valid,\n\toutput reg [63:0] rvfi_order,\n\toutput reg [31:0] rvfi_insn,\n\toutput reg        rvfi_trap,\n\toutput reg        rvfi_halt,\n\toutput reg        rvfi_intr,\n\toutput reg [ 1:0] rvfi_mode,\n\toutput reg [ 1:0] rvfi_ixl,\n\toutput reg [ 4:0] rvfi_rs1_addr,\n\toutput reg [ 4:0] rvfi_rs2_addr,\n\toutput reg [31:0] rvfi_rs1_rdata,\n\toutput reg [31:0] rvfi_rs2_rdata,\n\toutput reg [ 4:0] rvfi_rd_addr,\n\toutput reg [31:0] rvfi_rd_wdata,\n\toutput reg [31:0] rvfi_pc_rdata,\n\toutput reg [31:0] rvfi_pc_wdata,\n\n`ifdef NERV_CSR\n`define NERV_CSR_REG_MRW(NAME, ADDR, VALUE)\t\t\t\\\n\toutput reg [31:0] rvfi_csr_``NAME``_rmask,\t\t\\\n\toutput reg [31:0] rvfi_csr_``NAME``_wmask,\t\t\\\n\toutput reg [31:0] rvfi_csr_``NAME``_rdata,\t\t\\\n\toutput reg [31:0] rvfi_csr_``NAME``_wdata,\n\n`define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE)\t\t\t\\\n\t`NERV_CSR_REG_MRW(NAME, ADDR, VALUE)\n\n`define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE)\t\t\t\\\n\t`NERV_CSR_REG_MRW(NAME, ADDR, VALUE)\n\n`define NERV_CSR_ARR_DEF(ARRAY, DEPTH)\n\n`define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR)\t\t\\\n\toutput reg [31:0] rvfi_csr_``NAME``_rmask,\t\t\t\\\n\toutput reg [31:0] rvfi_csr_``NAME``_wmask,\t\t\t\\\n\toutput reg [31:0] rvfi_csr_``NAME``_rdata,\t\t\t\\\n\toutput reg [31:0] rvfi_csr_``NAME``_wdata,\n\n`NERV_CSRS\n`undef NERV_CSR_REG_MRW\n`undef NERV_CSR_VAL_MRW\n`undef NERV_CSR_VAL_MRO\n`undef NERV_CSR_ARR_DEF\n`undef NERV_CSR_ARR_MRW\n`endif\n\n\toutput reg [31:0] rvfi_mem_addr,\n\toutput reg [ 3:0] rvfi_mem_rmask,\n\toutput reg [ 3:0] rvfi_mem_wmask,\n\toutput reg [31:0] rvfi_mem_rdata,\n\toutput reg [31:0] rvfi_mem_wdata,\n\n`ifdef NERV_FAULT\n\toutput reg        rvfi_mem_fault,\n\toutput reg [ 3:0] rvfi_mem_fault_rmask,\n\toutput reg [ 3:0] rvfi_mem_fault_wmask,\n`endif\n`endif\n\n\t// we have 2 external memories\n\t// one is instruction memory\n\toutput [31:0] imem_addr,\n\tinput  [31:0] imem_data,\n\n\t// the other is data memory\n\toutput        dmem_valid,\n\toutput [31:0] dmem_addr,\n\toutput [ 3:0] dmem_wstrb,\n\toutput [31:0] dmem_wdata,\n\tinput  [31:0] dmem_rdata,\n\n`ifdef NERV_FAULT\n\tinput         imem_fault,\n\tinput         dmem_fault,\n`endif\n\t// interrupt inputs\n\tinput  [31:0] irq\n);\n\n`ifndef NERV_FAULT\n\twire imem_fault = 0;\n\twire dmem_fault = 0;\n`endif\n\n\treg mem_wr_enable;\n\treg [31:0] mem_wr_addr;\n\treg [31:0] mem_wr_data;\n\treg [3:0] mem_wr_strb;\n\n\treg mem_rd_enable;\n\treg [31:0] mem_rd_addr;\n\treg [4:0] mem_rd_reg;\n\treg [4:0] mem_rd_func;\n\n\treg mem_rd_enable_q;\n\treg [4:0] mem_rd_reg_q;\n\treg [4:0] mem_rd_func_q;\n\n\treg mem_wr_enable_q;\n\n\t// delayed copies of mem_rd (and mem_wr for NERV_FAULTS)\n\talways @(posedge clock) begin\n\t\tif (!stall) begin\n\t\t\tmem_rd_enable_q <= mem_rd_enable;\n\t\t\tmem_rd_reg_q <= mem_rd_reg;\n\t\t\tmem_rd_func_q <= mem_rd_func;\n\t\t\tmem_wr_enable_q <= mem_wr_enable;\n\t\tend\n\t\tif (reset) begin\n\t\t\tmem_rd_enable_q <= 0;\n\t\tend\n\tend\n\n\t// memory signals\n\tassign dmem_valid = mem_wr_enable || mem_rd_enable;\n\tassign dmem_addr  = mem_wr_enable ? mem_wr_addr : mem_rd_enable ? mem_rd_addr : 32'h x;\n\tassign dmem_wstrb = mem_wr_enable ? mem_wr_strb : mem_rd_enable ? 4'h 0 : 4'h x;\n\tassign dmem_wdata = mem_wr_enable ? mem_wr_data : 32'h x;\n\n\t// registers, instruction reg, program counter, next pc\n\treg [31:0] regfile [0:NUMREGS-1];\n\twire [31:0] insn;\n\treg [31:0] npc;\n\treg [31:0] pc;\n\n\treg [31:0] imem_addr_q;\n\n\talways @(posedge clock) begin\n\t\timem_addr_q <= imem_addr;\n\tend\n\n\t// instruction memory pointer\n\tassign imem_addr = npc;\n\tassign insn = imem_data;\n\n\t// components of the instruction\n\twire [6:0] insn_funct7;\n\twire [4:0] insn_rs2;\n\twire [4:0] insn_rs1;\n\twire [2:0] insn_funct3;\n\twire [4:0] insn_rd;\n\twire [6:0] insn_opcode;\n\n\t// rs1 and rs2 are source for the instruction\n\twire [31:0] rs1_value = !insn_rs1 ? 0 : regfile[insn_rs1];\n\twire [31:0] rs2_value = !insn_rs2 ? 0 : regfile[insn_rs2];\n\n\t// split R-type instruction - see section 2.2 of RiscV spec\n\tassign {insn_funct7, insn_rs2, insn_rs1, insn_funct3, insn_rd, insn_opcode} = insn;\n\n\t// setup for I, S, B & J type instructions\n\t// I - short immediates and loads\n\twire [11:0] imm_i;\n\tassign imm_i = insn[31:20];\n\n\t// S - stores\n\twire [11:0] imm_s;\n\tassign imm_s[11:5] = insn_funct7, imm_s[4:0] = insn_rd;\n\n\t// B - conditionals\n\twire [12:0] imm_b;\n\tassign {imm_b[12], imm_b[10:5]} = insn_funct7, {imm_b[4:1], imm_b[11]} = insn_rd, imm_b[0] = 1'b0;\n\n\t// J - unconditional jumps\n\twire [20:0] imm_j;\n\tassign {imm_j[20], imm_j[10:1], imm_j[11], imm_j[19:12], imm_j[0]} = {insn[31:12], 1'b0};\n\n\twire [31:0] imm_i_sext = $signed(imm_i);\n\twire [31:0] imm_s_sext = $signed(imm_s);\n\twire [31:0] imm_b_sext = $signed(imm_b);\n\twire [31:0] imm_j_sext = $signed(imm_j);\n\n\t// opcodes - see section 19 of RiscV spec\n\tlocalparam OPCODE_LOAD       = 7'b 00_000_11;\n\tlocalparam OPCODE_STORE      = 7'b 01_000_11;\n\tlocalparam OPCODE_MADD       = 7'b 10_000_11;\n\tlocalparam OPCODE_BRANCH     = 7'b 11_000_11;\n\n\tlocalparam OPCODE_LOAD_FP    = 7'b 00_001_11;\n\tlocalparam OPCODE_STORE_FP   = 7'b 01_001_11;\n\tlocalparam OPCODE_MSUB       = 7'b 10_001_11;\n\tlocalparam OPCODE_JALR       = 7'b 11_001_11;\n\n\tlocalparam OPCODE_CUSTOM_0   = 7'b 00_010_11;\n\tlocalparam OPCODE_CUSTOM_1   = 7'b 01_010_11;\n\tlocalparam OPCODE_NMSUB      = 7'b 10_010_11;\n\tlocalparam OPCODE_RESERVED_0 = 7'b 11_010_11;\n\n\tlocalparam OPCODE_MISC_MEM   = 7'b 00_011_11;\n\tlocalparam OPCODE_AMO        = 7'b 01_011_11;\n\tlocalparam OPCODE_NMADD      = 7'b 10_011_11;\n\tlocalparam OPCODE_JAL        = 7'b 11_011_11;\n\n\tlocalparam OPCODE_OP_IMM     = 7'b 00_100_11;\n\tlocalparam OPCODE_OP         = 7'b 01_100_11;\n\tlocalparam OPCODE_OP_FP      = 7'b 10_100_11;\n\tlocalparam OPCODE_SYSTEM     = 7'b 11_100_11;\n\n\tlocalparam OPCODE_AUIPC      = 7'b 00_101_11;\n\tlocalparam OPCODE_LUI        = 7'b 01_101_11;\n\tlocalparam OPCODE_RESERVED_1 = 7'b 10_101_11;\n\tlocalparam OPCODE_RESERVED_2 = 7'b 11_101_11;\n\n\tlocalparam OPCODE_OP_IMM_32  = 7'b 00_110_11;\n\tlocalparam OPCODE_OP_32      = 7'b 01_110_11;\n\tlocalparam OPCODE_CUSTOM_2   = 7'b 10_110_11;\n\tlocalparam OPCODE_CUSTOM_3   = 7'b 11_110_11;\n\n\tlocalparam MCAUSE_MACHINE_SOFTWARE_INTERRUPT = 32'h80000003;\n\tlocalparam MCAUSE_MACHINE_TIMER_INTERRUPT    = 32'h80000007;\n\tlocalparam MCAUSE_MACHINE_EXTERNAL_INTERRUPT = 32'h8000000b;\n\n\tlocalparam MCAUSE_INSN_ADDRESS_MISALIGNED  = 32'h00000000;\n\tlocalparam MCAUSE_INSN_ACCESS_FAULT        = 32'h00000001;\n\tlocalparam MCAUSE_INVALID_INSTRUCTION      = 32'h00000002;\n\tlocalparam MCAUSE_BREAKPOINT               = 32'h00000003;\n\tlocalparam MCAUSE_LOAD_ADDRESS_MISALIGNED  = 32'h00000004;\n\tlocalparam MCAUSE_LOAD_ACCESS_FAULT        = 32'h00000005;\n\tlocalparam MCAUSE_STORE_ADDRESS_MISALIGNED = 32'h00000006;\n\tlocalparam MCAUSE_STORE_ACCESS_FAULT       = 32'h00000007;\n\tlocalparam MCAUSE_ECALL_M_MODE             = 32'h0000000b;\n\n\tlocalparam IRQ_MASK = 32'hFFFF0888;\n\n\t// next write, next destination (rd) value & register\n\treg next_wr;\n\treg [31:0] next_rd;\n\treg [4:0] wr_rd;\n\n\t// illegal instruction registers\n\treg illinsn;\n\n\treg reset_q;\n\twire running = !stall && !reset && !reset_q;\n\n\t// action to perform this cycle\n\treg cycle_intr; // cycle to start fetching new PC for interrupts\n\treg cycle_insn; // first non-trapping cycle of an instruction\n\treg cycle_trap; // trap in the first cycle of an instruction\n\treg cycle_late_wr; // 2nd cycle for mem_rd_enable instructions\n\n`ifdef NERV_FAULT\n\treg cycle_dmem_fault;\n`endif\n\n\tassign trap = cycle_trap;\n\n`ifdef NERV_CSR\n\t/*********************\n\t *  CSR DEFINITIONS  *\n\t *********************/\n\n\treg        csr_ack;\n\treg [31:0] csr_rdval;\n\treg [31:0] csr_next;\n\n\twire imem_valid = !mem_rd_enable_q && !mem_wr_enable_q && !imem_fault;\n\twire [ 1:0] csr_mode = (running && imem_valid && !irq_num && insn_opcode == OPCODE_SYSTEM) ? insn_funct3[1:0] : 2'b 00; // 00=None, 01=RW, 10=RS, 11=RC\n\twire [11:0] csr_addr = imm_i;\n\twire [31:0] csr_rsval = insn_funct3[2] ? insn_rs1 : rs1_value;\n\twire csr_ro = csr_mode && (csr_mode != 2'b01 && !insn_rs1);\n\n\tinteger hpm_idx, hpm_increment, hpm_event;\n\n`define NERV_CSR_REG_MRW(NAME, ADDR, VALUE)\t\t\t\t\\\n\twire csr_``NAME``_sel = csr_mode && csr_addr == ADDR;\t\t\\\n\treg [31:0] csr_``NAME``_value;\t\t\t\t\t\\\n\treg [31:0] csr_``NAME``_wdata;\t\t\t\t\t\\\n\treg [31:0] csr_``NAME``_next;\t\t\t\t\t\\\n\talways @(posedge clock) begin\t\t\t\t\t\\\n\t\tcsr_``NAME``_value <= csr_``NAME``_next;\t\t\\\n\t\tif (reset || reset_q)\t\t\t\t\t\\\n\t\t\tcsr_``NAME``_value <= VALUE;\t\t\t\\\n\tend\n\n`define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE)\t\t\t\t\\\n\twire csr_``NAME``_sel = csr_mode && csr_addr == ADDR;\t\t\\\n\twire [31:0] csr_``NAME``_wdata = csr_``NAME``_sel ? csr_next : csr_``NAME``_value; \\\n\tlocalparam [31:0] csr_``NAME``_value = VALUE;\n\n`define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE)\t\t\t\t\\\n\twire csr_``NAME``_sel = csr_ro && csr_addr == ADDR;\t\t\\\n\tlocalparam [31:0] csr_``NAME``_value = VALUE;\n\n`define NERV_CSR_ARR_DEF(ARRAY, DEPTH)\t\t\t\t\t\\\n\tinteger ARRAY``_idx;\t\t\t\t\t\t\\\n\twire [DEPTH-1:0] csr_``ARRAY``_sel;\t\t\t\\\n\treg [(DEPTH*32)-1:0] csr_``ARRAY``_value;\t\t\t\\\n\treg [(DEPTH*32)-1:0] csr_``ARRAY``_wdata;\t\t\t\\\n\treg [(DEPTH*32)-1:0] csr_``ARRAY``_next;\t\t\t\\\n\talways @(posedge clock) begin\t\t\t\t\t\\\n\t\tcsr_``ARRAY``_value <= csr_``ARRAY``_next;\t\t\\\n\t\tif (reset || reset_q)\t\t\t\t\t\\\n\t\t\tcsr_``ARRAY``_value <= 'b0;\t\t\t\\\n\tend\n\n`define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR)\t\t\t\t\\\n\twire csr_``NAME``_sel = csr_mode && csr_addr == ADDR;\t\t\t\\\n\twire [31:0] csr_``NAME``_value = csr_``ARRAY``_value[(INDEX)*32 +: 32];\t\\\n\twire [31:0] csr_``NAME``_wdata = csr_``ARRAY``_wdata[(INDEX)*32 +: 32];\t\\\n\twire [31:0] csr_``NAME``_next  = csr_``ARRAY``_next[(INDEX)*32 +: 32];  \\\n\tassign csr_``ARRAY``_sel[INDEX] = csr_``NAME``_sel;\n\n\t// dummy out missing select lines\n\tassign csr_hpm_event_sel[2:0] = 0;\n\tassign csr_hpm_counter_sel[1] = 0;\n\tassign csr_hpm_counterh_sel[1] = 0;\n\n`NERV_CSRS\n`undef NERV_CSR_REG_MRW\n`undef NERV_CSR_VAL_MRW\n`undef NERV_CSR_VAL_MRO\n`undef NERV_CSR_ARR_DEF\n`undef NERV_CSR_ARR_MRW\n`endif // NERV_CSR\n\n\twire [31:0] irq_en;\n\treg [4:0] irq_num;\n\tassign irq_en = irq & csr_mie_value;\n\n\t// resolve interrupt priority\n\talways @* begin\n\t\tif (irq_en[31]) irq_num = 5'd31;\n\t\telse if (irq_en[30]) irq_num = 5'd30;\n\t\telse if (irq_en[29]) irq_num = 5'd29;\n\t\telse if (irq_en[28]) irq_num = 5'd28;\n\t\telse if (irq_en[27]) irq_num = 5'd27;\n\t\telse if (irq_en[26]) irq_num = 5'd26;\n\t\telse if (irq_en[25]) irq_num = 5'd25;\n\t\telse if (irq_en[24]) irq_num = 5'd24;\n\t\telse if (irq_en[23]) irq_num = 5'd23;\n\t\telse if (irq_en[22]) irq_num = 5'd22;\n\t\telse if (irq_en[21]) irq_num = 5'd21;\n\t\telse if (irq_en[20]) irq_num = 5'd20;\n\t\telse if (irq_en[19]) irq_num = 5'd19;\n\t\telse if (irq_en[18]) irq_num = 5'd18;\n\t\telse if (irq_en[17]) irq_num = 5'd17;\n\t\telse if (irq_en[16]) irq_num = 5'd16;\n\t\telse if (irq_en[11]) irq_num = 5'd11;\n\t\telse if (irq_en[7]) irq_num = 5'd7;\n\t\telse if (irq_en[3]) irq_num = 5'd3;\n\t\telse irq_num = 5'd0;\n\tend\n\n\talways @* begin\n\t\t// advance pc\n\t\tnpc = pc + 4;\n\n\t\t// defaults for read, write\n\t\tnext_wr = 0;\n\t\tnext_rd = 0;\n\t\tcycle_intr = 0;\n\t\tcycle_trap = 0;\n\t\tcycle_insn = 0;\n\t\tcycle_late_wr = 0;\n`ifdef NERV_FAULT\n\t\tcycle_dmem_fault = 0;\n`endif\n\t\twr_rd = insn_rd;\n\n\t\tillinsn = 0;\n\n\t\tmem_wr_enable = 0;\n\t\tmem_wr_addr = 32'hx;\n\t\tmem_wr_data = 32'hx;\n\t\tmem_wr_strb = 4'hx;\n\n\t\tmem_rd_enable = 0;\n\t\tmem_rd_addr = 32'hx;\n\t\tmem_rd_reg = 5'hx;\n\t\tmem_rd_func = 5'hx;\n\n`ifdef NERV_CSR\n\t\tcsr_ack = 0;\n\t\tcsr_rdval = 'hx;\n\n\t\tunique case (1'b1)\n`define NERV_CSR_REG_MRW(NAME, ADDR, VALUE)\t\t\\\n\t\t\tcsr_mode && csr_``NAME``_sel: begin\t\t\\\n\t\t\t\tcsr_ack = 1;\t\t\t\t\\\n\t\t\t\tcsr_rdval = csr_``NAME``_value;\t\\\n\t\t\tend\n\n`define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE)\t\t\\\n\t\t\tcsr_mode && csr_``NAME``_sel: begin\t\t\\\n\t\t\t\tcsr_ack = 1;\t\t\t\t\\\n\t\t\t\tcsr_rdval = csr_``NAME``_value;\t\\\n\t\t\tend\n\n`define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE)\t\t\\\n\t\t\tcsr_ro && csr_``NAME``_sel: begin\t\t\\\n\t\t\t\tcsr_ack = 1;\t\t\t\t\\\n\t\t\t\tcsr_rdval = csr_``NAME``_value;\t\\\n\t\t\tend\n`define NERV_CSR_ARR_DEF(ARRAY, DEPTH)\n`define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR)\t\t\\\n\t`NERV_CSR_REG_MRW(NAME, ADDR, 32'h 0000_0000)\n\n`NERV_CSRS\n`undef NERV_CSR_REG_MRW\n`undef NERV_CSR_VAL_MRW\n`undef NERV_CSR_VAL_MRO\n`undef NERV_CSR_ARR_DEF\n`undef NERV_CSR_ARR_MRW\n\n\t\t\tdefault: /* nothing */;\n\t\tendcase\n\n\t\tcsr_next = csr_rdval;\n\t\tcase (csr_mode)\n\t\t\t2'b 01 /* RW */: csr_next = csr_rsval;\n\t\t\t2'b 10 /* RS */: csr_next = csr_next | csr_rsval;\n\t\t\t2'b 11 /* RC */: csr_next = csr_next & ~csr_rsval;\n\t\tendcase\n\n`define NERV_CSR_REG_MRW(NAME, ADDR, VALUE) \\\n\t\tcsr_``NAME``_wdata = csr_``NAME``_sel ? csr_next : csr_``NAME``_value; \\\n\t\tcsr_``NAME``_next = csr_``NAME``_wdata;\n\n`define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE)\n`define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE)\n`define NERV_CSR_ARR_DEF(ARRAY, DEPTH)\t\t\t\t\t\t\t\t\\\n\t\tfor (ARRAY``_idx=0; ARRAY``_idx < DEPTH; ARRAY``_idx=ARRAY``_idx+1) begin \t\\\n\t\t\tcsr_``ARRAY``_wdata[(ARRAY``_idx)*32 +: 32] = \t\t\t\t\\\n\t\t\t\tcsr_``ARRAY``_sel[ARRAY``_idx] \t\t\t\t\t\\\n\t\t\t\t? csr_next \t\t\t\t\t\t\t\\\n\t\t\t\t: csr_``ARRAY``_value[(ARRAY``_idx)*32 +: 32];\t\t\t\\\n\t\tend\t\t\t\t\t\t\t\t\t\t\\\n\t\tcsr_``ARRAY``_next = csr_``ARRAY``_wdata;\n\n`define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR)\n\n`NERV_CSRS\n`undef NERV_CSR_REG_MRW\n`undef NERV_CSR_VAL_MRW\n`undef NERV_CSR_VAL_MRO\n`undef NERV_CSR_ARR_DEF\n`undef NERV_CSR_ARR_MRW\n\n\t\tfor (hpm_idx=0; hpm_idx < 32; hpm_idx=hpm_idx+1) begin\n\t\t\tcase (hpm_idx)\n\t\t\t\t0 /* mcycle */ : hpm_event = 32'h 1;\n\t\t\t\t2 /* minstret */ : hpm_event = 32'h 2;\n\t\t\t\tdefault:\n\t\t\t\t\thpm_event = csr_hpm_event_next[(hpm_idx)*32 +: 32];\n\t\t\tendcase\n\t\t\tcase (hpm_event)\n\t\t\t\t32'h 1 /* cycle counter */: hpm_increment = 1;\n\t\t\t\t32'h 2 /* instruction counter */: hpm_increment = running ? 1 : 0;\n\t\t\t\t32'h 3 /* memory writes */: hpm_increment = mem_wr_enable_q ? 1 : 0;\n\t\t\t\tdefault: begin\n\t\t\t\t\tcsr_hpm_event_next[(hpm_idx)*32 +: 32] = 0;\n\t\t\t\t\thpm_increment = 0;\n\t\t\t\tend\n\t\t\tendcase\n\t\t\t{csr_hpm_counterh_next[(hpm_idx)*32 +: 32], csr_hpm_counter_next[(hpm_idx)*32 +: 32]} = \n\t\t\t\t{csr_hpm_counterh_next[(hpm_idx)*32 +: 32], csr_hpm_counter_next[(hpm_idx)*32 +: 32]} + hpm_increment;\n\t\tend\n\n\t// mstatus & mstatush - Machine Status\n\tcsr_mstatus_next[31] = 'b0; // SD is always 0 if FS, VS, and XS are not enabled\n\tcsr_mstatus_next[30:23] = 'b0; // WPRI\n\tcsr_mstatus_next[22] = 'b0; // TSR = 0 if no S\n\tcsr_mstatus_next[21] = 'b0; // TW = 0 if no U or S\n\tcsr_mstatus_next[20] = 'b0; // TVM = 0 if no S\n\tcsr_mstatus_next[19] = 'b0; // MXR = 0 if no S\n\tcsr_mstatus_next[18] = 'b0; // SUM = 0 if no S\n\tcsr_mstatus_next[17] = 'b0; // MPRV = 0 if no U\n\tcsr_mstatus_next[16:15] = 'b0; // XS = 0 if no user extensions\n\tcsr_mstatus_next[14:13] = 'b0; // FS = 0 if no S and no floating point extension\n\tcsr_mstatus_next[12:11] = 2'b11; // MPP = b11 if no U\n\tcsr_mstatus_next[10:9] = 'b0; // VS = 0 if no vector extension\n\tcsr_mstatus_next[8] = 'b0; // SPP = 0 if no S\n\t//csr_mstatus_next[7] = ; // MPIE controlled by trap handling\n\tcsr_mstatus_next[6] = 'b0; // UBE = 0 if no U\n\tcsr_mstatus_next[5] = 'b0; // SPIE = 0 if no S\n\tcsr_mstatus_next[4] = 'b0; // WPRI\n\t//csr_mstatus_next[3] = ; // MIE controlled by code\n\tcsr_mstatus_next[2] = 'b0; // WPRI\n\tcsr_mstatus_next[1] = 'b0; // SIE = 0 if no S\n\tcsr_mstatus_next[0] = 'b0; // WPRI\n\n\tcsr_mstatush_next[31:6] = 'b0; // WPRI\n\tcsr_mstatush_next[5] = 1'b0; // MBE = 1 if big endian, 0 if little endian\n\tcsr_mstatush_next[4] = 'b0; // SBE = 0 if no S\n\tcsr_mstatush_next[3:0] = 'b0; // WPRI\n\n\t// misa - Machine ISA\n\t// read-only 0 for unimplemented register\n\tcsr_misa_next[31:20] = 'b0; // MXL = 1 for XLEN=32\n\tcsr_misa_next[29:26] = 'b0; // 0\n\tcsr_misa_next[25:0] = 'b0; // Extensions enabled\n\n\t// mie - Machine Interrupt-Enable\n\t// A bit in mie must be writable if the corresponding interrupt can ever become pending.\n\t// Bits of mie that are not writable must be read-only 0.\n\t//csr_mie_next[31:16] = 'b0; // bits 16 and above for custom/platform interrupts\n\tcsr_mie_next[15:12] = 'b0; // 0\n\t//csr_mie_next[11] = 'b0; // MEIE - Machine-level External Interrupt Enable\n\tcsr_mie_next[10] = 'b0; // 0\n\tcsr_mie_next[9] = 'b0; // SEIE = 0 if no S\n\tcsr_mie_next[8] = 'b0; // 0\n\t//csr_mie_next[7] = 'b0; // MTIE - Machine Timer Interrupt Enable\n\tcsr_mie_next[6] = 'b0; // 0\n\tcsr_mie_next[5] = 'b0; // STIE = 0 if no S\n\tcsr_mie_next[4] = 'b0; // 0\n\t//csr_mie_next[3] = 'b0; // MSIE - Machine-level Software Interrupt Enable\n\tcsr_mie_next[2] = 'b0; // 0\n\tcsr_mie_next[1] = 'b0; // SSIE = 0 if no S\n\tcsr_mie_next[0] = 'b0; // 0\n\n\t// mip - Machine Interrupt-Pending\n\t//csr_mip_next[31:16] = 'b0; // bits 16 and above for custom/platform interrupts\n\t//csr_mip_next[15:12] = 'b0; // 0\n\t//csr_mip_next[11] = 'b0; // MEIE - Machine-level External Interrupt Pending\n\t//csr_mip_next[10] = 'b0; // 0\n\t//csr_mip_next[9] = 'b0; // SEIE = 0 if no S\n\t//csr_mip_next[8] = 'b0; // 0\n\t//csr_mip_next[7] = 'b0; // MTIE - Machine Timer Interrupt Pending\n\t//csr_mip_next[6] = 'b0; // 0\n\t//csr_mip_next[5] = 'b0; // STIE = 0 if no S\n\t//csr_mip_next[4] = 'b0; // 0\n\t//csr_mip_next[3] = 'b0; // MSIE - Machine-level Software Interrupt Pending\n\t//csr_mip_next[2] = 'b0; // 0\n\t//csr_mip_next[1] = 'b0; // SSIE = 0 if no S\n\t//csr_mip_next[0] = 'b0; // 0\n\tcsr_mip_next = irq & IRQ_MASK;\n\n\t// mtvec - Machine Trap-Vector Base-Address\n\tcsr_mtvec_next[1] = 'b0; // MODE - keep high bit always 0\n\n\t// mcause - keep these bits at 0\n\tcsr_mcause_next[30:5] ='b0;\n\n\t// mepc - keep alignment\n\tcsr_mepc_next[1:0] = 'b0;\n\n`endif // NERV_CSR\n\n\t\t// act on opcodes\n\t\tcase (insn_opcode)\n\t\t\t// Load Upper Immediate\n\t\t\tOPCODE_LUI: begin\n\t\t\t\tnext_wr = 1;\n\t\t\t\tnext_rd = insn[31:12] << 12;\n\t\t\tend\n\t\t\t// Add Upper Immediate to Program Counter\n\t\t\tOPCODE_AUIPC: begin\n\t\t\t\tnext_wr = 1;\n\t\t\t\tnext_rd = (insn[31:12] << 12) + pc;\n\t\t\tend\n\t\t\t// Jump And Link (unconditional jump)\n\t\t\tOPCODE_JAL: begin\n\t\t\t\tnext_wr = 1;\n\t\t\t\tnext_rd = npc;\n\t\t\t\tnpc = pc + imm_j_sext;\n\t\t\t\tif (npc & 32'b 11) begin\n\t\t\t\t\tillinsn = 1;\n\t\t\t\t\tnpc = npc & ~32'b 11;\n\t\t\t\tend\n\t\t\tend\n\t\t\t// Jump And Link Register (indirect jump)\n\t\t\tOPCODE_JALR: begin\n\t\t\t\tcase (insn_funct3)\n\t\t\t\t\t3'b 000 /* JALR */: begin\n\t\t\t\t\t\tnext_wr = 1;\n\t\t\t\t\t\tnext_rd = npc;\n\t\t\t\t\t\tnpc = (rs1_value + imm_i_sext) & ~32'b 1;\n\t\t\t\t\tend\n\t\t\t\t\tdefault: illinsn = 1;\n\t\t\t\tendcase\n\t\t\t\tif (npc & 32'b 11) begin\n\t\t\t\t\tillinsn = 1;\n\t\t\t\t\tnpc = npc & ~32'b 11;\n\t\t\t\tend\n\t\t\tend\n\t\t\t// branch instructions: Branch If Equal, Branch Not Equal, Branch Less Than, Branch Greater Than, Branch Less Than Unsigned, Branch Greater Than Unsigned\n\t\t\tOPCODE_BRANCH: begin\n\t\t\t\tcase (insn_funct3)\n\t\t\t\t\t3'b 000 /* BEQ  */: begin if (rs1_value == rs2_value) npc = pc + imm_b_sext; end\n\t\t\t\t\t3'b 001 /* BNE  */: begin if (rs1_value != rs2_value) npc = pc + imm_b_sext; end\n\t\t\t\t\t3'b 100 /* BLT  */: begin if ($signed(rs1_value) < $signed(rs2_value)) npc = pc + imm_b_sext; end\n\t\t\t\t\t3'b 101 /* BGE  */: begin if ($signed(rs1_value) >= $signed(rs2_value)) npc = pc + imm_b_sext; end\n\t\t\t\t\t3'b 110 /* BLTU */: begin if (rs1_value < rs2_value) npc = pc + imm_b_sext; end\n\t\t\t\t\t3'b 111 /* BGEU */: begin if (rs1_value >= rs2_value) npc = pc + imm_b_sext; end\n\t\t\t\t\tdefault: illinsn = 1;\n\t\t\t\tendcase\n\t\t\t\tif (npc & 32'b 11) begin\n\t\t\t\t\tillinsn = 1;\n\t\t\t\t\tnpc = npc & ~32'b 11;\n\t\t\t\tend\n\t\t\tend\n\t\t\t// load from memory into rd: Load Byte, Load Halfword, Load Word, Load Byte Unsigned, Load Halfword Unsigned\n\t\t\tOPCODE_LOAD: begin\n\t\t\t\tmem_rd_addr = rs1_value + imm_i_sext;\n\t\t\t\tcasez ({insn_funct3, mem_rd_addr[1:0]})\n\t\t\t\t\t5'b 000_zz /* LB  */,\n\t\t\t\t\t5'b 001_z0 /* LH  */,\n\t\t\t\t\t5'b 010_00 /* LW  */,\n\t\t\t\t\t5'b 100_zz /* LBU */,\n\t\t\t\t\t5'b 101_z0 /* LHU */: begin\n\t\t\t\t\t\tmem_rd_enable = 1;\n\t\t\t\t\t\tmem_rd_reg = insn_rd;\n\t\t\t\t\t\tmem_rd_func = {mem_rd_addr[1:0], insn_funct3};\n\t\t\t\t\t\tmem_rd_addr = {mem_rd_addr[31:2], 2'b 00};\n\t\t\t\t\tend\n\t\t\t\t\tdefault: illinsn = 1;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\t// store to memory instructions: Store Byte, Store Halfword, Store Word\n\t\t\tOPCODE_STORE: begin\n\t\t\t\tmem_wr_addr = rs1_value + imm_s_sext;\n\t\t\t\tcasez ({insn_funct3, mem_wr_addr[1:0]})\n\t\t\t\t\t5'b 000_zz /* SB */,\n\t\t\t\t\t5'b 001_z0 /* SH */,\n\t\t\t\t\t5'b 010_00 /* SW */: begin\n\t\t\t\t\t\tmem_wr_enable = 1;\n\t\t\t\t\t\tmem_wr_data = rs2_value;\n\t\t\t\t\t\tmem_wr_strb = 4'b 1111;\n\t\t\t\t\t\tcase (insn_funct3)\n\t\t\t\t\t\t\t3'b 000 /* SB  */: begin mem_wr_strb = 4'b 0001; end\n\t\t\t\t\t\t\t3'b 001 /* SH  */: begin mem_wr_strb = 4'b 0011; end\n\t\t\t\t\t\t\t3'b 010 /* SW  */: begin mem_wr_strb = 4'b 1111; end\n\t\t\t\t\t\tendcase\n\t\t\t\t\t\tmem_wr_data = mem_wr_data << (8*mem_wr_addr[1:0]);\n\t\t\t\t\t\tmem_wr_strb = mem_wr_strb << mem_wr_addr[1:0];\n\t\t\t\t\t\tmem_wr_addr = {mem_wr_addr[31:2], 2'b 00};\n\t\t\t\t\tend\n\t\t\t\t\tdefault: illinsn = 1;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\t// immediate ALU instructions: Add Immediate, Set Less Than Immediate, Set Less Than Immediate Unsigned, XOR Immediate,\n\t\t\t// OR Immediate, And Immediate, Shift Left Logical Immediate, Shift Right Logical Immediate, Shift Right Arithmetic Immediate\n\t\t\tOPCODE_OP_IMM: begin\n\t\t\t\tcasez ({insn_funct7, insn_funct3})\n\t\t\t\t\t10'b zzzzzzz_000 /* ADDI  */: begin next_wr = 1; next_rd = rs1_value + imm_i_sext; end\n\t\t\t\t\t10'b zzzzzzz_010 /* SLTI  */: begin next_wr = 1; next_rd = $signed(rs1_value) < $signed(imm_i_sext); end\n\t\t\t\t\t10'b zzzzzzz_011 /* SLTIU */: begin next_wr = 1; next_rd = rs1_value < imm_i_sext; end\n\t\t\t\t\t10'b zzzzzzz_100 /* XORI  */: begin next_wr = 1; next_rd = rs1_value ^ imm_i_sext; end\n\t\t\t\t\t10'b zzzzzzz_110 /* ORI   */: begin next_wr = 1; next_rd = rs1_value | imm_i_sext; end\n\t\t\t\t\t10'b zzzzzzz_111 /* ANDI  */: begin next_wr = 1; next_rd = rs1_value & imm_i_sext; end\n\t\t\t\t\t10'b 0000000_001 /* SLLI  */: begin next_wr = 1; next_rd = rs1_value << insn[24:20]; end\n\t\t\t\t\t10'b 0000000_101 /* SRLI  */: begin next_wr = 1; next_rd = rs1_value >> insn[24:20]; end\n\t\t\t\t\t10'b 0100000_101 /* SRAI  */: begin next_wr = 1; next_rd = $signed(rs1_value) >>> insn[24:20]; end\n\t\t\t\t\tdefault: illinsn = 1;\n\t\t\t\tendcase\n\t\t\tend\n\t\t\tOPCODE_OP: begin\n\t\t\t// ALU instructions: Add, Subtract, Shift Left Logical, Set Left Than, Set Less Than Unsigned, XOR, Shift Right Logical,\n\t\t\t// Shift Right Arithmetic, OR, AND\n\t\t\t\tcase ({insn_funct7, insn_funct3})\n\t\t\t\t\t10'b 0000000_000 /* ADD  */: begin next_wr = 1; next_rd = rs1_value + rs2_value; end\n\t\t\t\t\t10'b 0100000_000 /* SUB  */: begin next_wr = 1; next_rd = rs1_value - rs2_value; end\n\t\t\t\t\t10'b 0000000_001 /* SLL  */: begin next_wr = 1; next_rd = rs1_value << rs2_value[4:0]; end\n\t\t\t\t\t10'b 0000000_010 /* SLT  */: begin next_wr = 1; next_rd = $signed(rs1_value) < $signed(rs2_value); end\n\t\t\t\t\t10'b 0000000_011 /* SLTU */: begin next_wr = 1; next_rd = rs1_value < rs2_value; end\n\t\t\t\t\t10'b 0000000_100 /* XOR  */: begin next_wr = 1; next_rd = rs1_value ^ rs2_value; end\n\t\t\t\t\t10'b 0000000_101 /* SRL  */: begin next_wr = 1; next_rd = rs1_value >> rs2_value[4:0]; end\n\t\t\t\t\t10'b 0100000_101 /* SRA  */: begin next_wr = 1; next_rd = $signed(rs1_value) >>> rs2_value[4:0]; end\n\t\t\t\t\t10'b 0000000_110 /* OR   */: begin next_wr = 1; next_rd = rs1_value | rs2_value; end\n\t\t\t\t\t10'b 0000000_111 /* AND  */: begin next_wr = 1; next_rd = rs1_value & rs2_value; end\n\t\t\t\t\tdefault: illinsn = 1;\n\t\t\t\tendcase\n\t\t\tend\n`ifdef NERV_CSR\n\t\t\tOPCODE_SYSTEM: begin\n\t\t\t\tcase (insn_funct3)\n\t\t\t\t\t3'b 000 : begin\n\t\t\t\t\t\tcase ({insn_funct7, insn_rs2})\n\t\t\t\t\t\t\t12'b 0000000_00000 /* ECALL */:\n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\tcsr_mepc_next = { pc[31:2], 2'b00 };\n\t\t\t\t\t\t\t\t\tnpc = csr_mtvec_value & ~3;\n\t\t\t\t\t\t\t\t\tcsr_mcause_next = MCAUSE_ECALL_M_MODE;\n\t\t\t\t\t\t\t\t\tcsr_mstatus_next[7] = csr_mstatus_value[3];  // save MIE to MPIE\n\t\t\t\t\t\t\t\t\tcsr_mstatus_next[3] = 0; // MIE to 0\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t12'b 0000000_00001 /* EBREAK */:\n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\tcsr_mepc_next = { pc[31:2], 2'b00 };\n\t\t\t\t\t\t\t\t\tnpc = csr_mtvec_value & ~3;\n\t\t\t\t\t\t\t\t\tcsr_mcause_next = MCAUSE_BREAKPOINT;\n\t\t\t\t\t\t\t\t\tcsr_mstatus_next[7] = csr_mstatus_value[3];  // save MIE to MPIE\n\t\t\t\t\t\t\t\t\tcsr_mstatus_next[3] = 0; // MIE to 0\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t12'b 0011000_00010 /* MRET */:\n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\tnpc = csr_mepc_value;\n\t\t\t\t\t\t\t\t\tcsr_mcause_next = 'b0;\n\t\t\t\t\t\t\t\t\tcsr_mstatus_next[3] = csr_mstatus_value[7];  // restore MIE from MPIE\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\t12'b 0001000_00101 /* WFI */:\n\t\t\t\t\t\t\t\tbegin\n\t\t\t\t\t\t\t\t\t// implemented as NOP\n\t\t\t\t\t\t\t\tend\n\t\t\t\t\t\t\tdefault: illinsn = 1;\n\t\t\t\t\t\tendcase\n\t\t\t\t\tend\n\t\t\t\t\tdefault : begin\n\t\t\t\t\t\tif (csr_ack) begin\n\t\t\t\t\t\t\tnext_wr = 1;\n\t\t\t\t\t\t\tnext_rd = csr_rdval;\n\t\t\t\t\t\tend else\n\t\t\t\t\t\t\tillinsn = 1;\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\tend\n`endif\n\t\t\tdefault: illinsn = 1;\n\t\tendcase\n\n\t\tif (reset || reset_q) begin\n\t\t\t// reset has the highest priority\n\t\t\tnpc = RESET_ADDR;\n\t\t\tcsr_mstatus_next[3] = 0; // MIE\n\t\tend else if (stall) begin\n\t\t\t// if this is a stall cycle, don't perform any action\n\t\t\tnpc = pc;\n`ifdef NERV_FAULT\n\t\tend else if (mem_rd_enable_q || mem_wr_enable_q) begin\n\t\t\tnpc = pc;\n\n\t\t\tif (dmem_fault) begin\n\t\t\t\tcycle_dmem_fault = 1;\n\t\t\t\tcsr_mepc_next[31:2] = pc[31:2];\n\t\t\t\tnpc = csr_mtvec_value & ~3;\n\t\t\t\tcsr_mcause_next = mem_wr_enable_q ? MCAUSE_STORE_ACCESS_FAULT : MCAUSE_LOAD_ACCESS_FAULT;\n\t\t\t\tcsr_mcause_wdata = csr_mcause_next;\n\t\t\t\tcsr_mstatus_next[7] = csr_mstatus_value[3];  // save MIE to MPIE\n\t\t\t\tcsr_mstatus_next[3] = 0; // MIE to 0\n\t\t\tend else begin\n\t\t\t\tcycle_late_wr = 1;\n\n\t\t\t\tif (mem_rd_enable_q) begin\n\t\t\t\t\twr_rd = mem_rd_reg_q;\n\t\t\t\t\tnext_rd = mem_rdata;\n\t\t\t\tend\n\t\t\tend\n`else\n\t\tend else if (mem_rd_enable_q) begin\n\t\t\t// if last cycle was a memory read, then this cycle is the 2nd part of it and imem_data will not be a valid instruction\n\t\t\tnpc = pc;\n\t\t\tcycle_late_wr = 1;\n\t\t\twr_rd = mem_rd_reg_q;\n\t\t\tnext_rd = mem_rdata;\n`endif\n\t\tend else if (irq_num!=0) begin\n\t\t\t// if there's a pending IRQ, take it\n\t\t\tcsr_mepc_next = { pc[31:2], 2'b00 };\n\t\t\tcsr_mcause_next = 1 << 31 | irq_num;\n\t\t\tif (csr_mtvec_value & 1)\n\t\t\t\tnpc = (csr_mtvec_value & ~3) + (irq_num << 2);\n\t\t\telse\n\t\t\t\tnpc = csr_mtvec_value & ~3;\n\t\t\tcsr_mstatus_next[7] = 1; // MPIE to 1\n\t\t\tcsr_mstatus_next[3] = 0; // MIE to 0\n\n\t\t\tcycle_intr = 1;\n\t\tend else if (imem_fault || illinsn) begin\n\t\t\t// instruction fetch memory fault\n\t\t\tcycle_trap = 1;\n\t\t\tcsr_mepc_next[31:2] = pc[31:2];\n\t\t\tnpc = csr_mtvec_value & ~3;\n\t\t\tcsr_mcause_next = imem_fault ? MCAUSE_INSN_ACCESS_FAULT : MCAUSE_INVALID_INSTRUCTION;\n\t\t\tcsr_mcause_wdata = csr_mcause_next;\n\t\t\tcsr_mstatus_next[7] = csr_mstatus_value[3];  // save MIE to MPIE\n\t\t\tcsr_mstatus_next[3] = 0; // MIE to 0\n\t\tend else begin\n\t\t\t// the instruction is valid and nothing else has priority\n\t\t\tcycle_insn = 1;\n\t\tend\n\n\t\tif (!cycle_insn) begin\n\t\t\tnext_wr = cycle_late_wr && mem_rd_enable_q;\n\t\t\tmem_rd_enable = 0;\n\t\t\tmem_wr_enable = 0;\n\t\tend\n\tend\n\n\treg [31:0] mem_rdata;\n`ifdef NERV_RVFI\n\treg next_rvfi_intr;\n\treg rvfi_trap_q;\n\n`ifdef NERV_FAULT\n\twire next_rvfi_valid = (cycle_insn && !mem_rd_enable && !mem_wr_enable) || cycle_trap || cycle_dmem_fault || cycle_late_wr;\n`else\n\twire next_rvfi_valid = (cycle_insn && !mem_rd_enable) || cycle_trap || cycle_late_wr;\n`endif\n\n`endif\n\n\t// mem read functions: Lower and Upper Bytes, signed and unsigned\n\talways @* begin\n\t\tmem_rdata = dmem_rdata >> (8*mem_rd_func_q[4:3]);\n\t\tcase (mem_rd_func_q[2:0])\n\t\t\t3'b 000 /* LB  */: begin mem_rdata = $signed(mem_rdata[7:0]); end\n\t\t\t3'b 001 /* LH  */: begin mem_rdata = $signed(mem_rdata[15:0]); end\n\t\t\t3'b 100 /* LBU */: begin mem_rdata = mem_rdata[7:0]; end\n\t\t\t3'b 101 /* LHU */: begin mem_rdata = mem_rdata[15:0]; end\n\t\tendcase\n\tend\n\n\t// every cycle\n\talways @(posedge clock) begin\n\t\treset_q <= reset || (reset_q && stall);\n\n\t\t// update pc\n\t\tpc <= npc;\n\n\t\tif (next_wr)\n\t\t\tregfile[wr_rd] <= next_rd;\n\n`ifdef NERV_RVFI\n\t\trvfi_valid <= next_rvfi_valid;\n\n\t\tif (cycle_intr)\n\t\t\tnext_rvfi_intr <= 1;\n\n\t\tif (cycle_insn || cycle_late_wr || cycle_trap) begin\n\t\t\trvfi_rd_addr <= next_wr ? wr_rd : 0;\n\t\t\trvfi_rd_wdata <= next_wr && wr_rd ? next_rd : 0;\n\t\t\trvfi_mem_rdata <= dmem_rdata;\n\t\tend\n\n\t\tif (cycle_insn || cycle_trap) begin\n\t\t\tnext_rvfi_intr <= cycle_trap;\n\t\t\trvfi_order <= rvfi_order + 1;\n\t\t\trvfi_insn <= imem_fault ? 32'b0 : insn;\n\t\t\trvfi_trap <= cycle_trap;\n\t\t\trvfi_halt <= 0;\n\t\t\trvfi_intr <= next_rvfi_intr;\n\t\t\trvfi_mode <= 3;\n\t\t\trvfi_ixl <= 1;\n\t\t\trvfi_rs1_addr <= insn_rs1;\n\t\t\trvfi_rs2_addr <= insn_rs2;\n\t\t\trvfi_rs1_rdata <= rs1_value;\n\t\t\trvfi_rs2_rdata <= rs2_value;\n\t\t\trvfi_pc_rdata <= pc;\n\t\t\trvfi_pc_wdata <= npc;\n\t\t\tif (dmem_valid) begin\n\t\t\t\trvfi_mem_addr <= dmem_addr;\n\t\t\t\tcase ({mem_rd_enable, insn_funct3})\n\t\t\t\t\t4'b 1_000 /* LB  */: begin rvfi_mem_rmask <= 4'b 0001 << mem_rd_func[4:3]; end\n\t\t\t\t\t4'b 1_001 /* LH  */: begin rvfi_mem_rmask <= 4'b 0011 << mem_rd_func[4:3]; end\n\t\t\t\t\t4'b 1_010 /* LW  */: begin rvfi_mem_rmask <= 4'b 1111 << mem_rd_func[4:3]; end\n\t\t\t\t\t4'b 1_100 /* LBU */: begin rvfi_mem_rmask <= 4'b 0001 << mem_rd_func[4:3]; end\n\t\t\t\t\t4'b 1_101 /* LHU */: begin rvfi_mem_rmask <= 4'b 0011 << mem_rd_func[4:3]; end\n\t\t\t\t\tdefault: rvfi_mem_rmask <= 0;\n\t\t\t\tendcase\n\t\t\t\trvfi_mem_wmask <= dmem_wstrb;\n\t\t\t\trvfi_mem_wdata <= dmem_wdata;\n\t\t\tend else begin\n\t\t\t\trvfi_mem_addr <= 0;\n\t\t\t\trvfi_mem_rmask <= 0;\n\t\t\t\trvfi_mem_wmask <= 0;\n\t\t\t\trvfi_mem_wdata <= 0;\n\t\t\tend\n`ifdef NERV_FAULT\n\t\t\trvfi_mem_fault <= imem_fault;\n\t\t\trvfi_mem_fault_rmask <= 0;\n\t\t\trvfi_mem_fault_wmask <= 0;\n`endif\n\t\tend\n\n`ifdef NERV_FAULT\n\t\tif (cycle_dmem_fault) begin\n\t\t\tnext_rvfi_intr <= 1;\n\t\t\trvfi_trap <= 1;\n\t\t\trvfi_mem_fault <= 1;\n\t\t\trvfi_rd_addr <= 0;\n\t\t\trvfi_rd_wdata <= 0;\n\n\t\t\trvfi_mem_fault_rmask <= rvfi_mem_rmask;\n\t\t\trvfi_mem_fault_wmask <= rvfi_mem_wmask;\n\n\t\t\trvfi_mem_rmask <= 0;\n\t\t\trvfi_mem_wmask <= 0;\n\t\tend\n`endif\n\n\t\tif (next_rvfi_valid) begin\n`ifdef NERV_CSR\n`define NERV_CSR_REG_MRW(NAME, ADDR, VALUE) \\\n\t\t\trvfi_csr_``NAME``_rmask <= 32'h ffff_ffff;\t\\\n\t\t\trvfi_csr_``NAME``_wmask <= 32'h ffff_ffff;\t\\\n\t\t\trvfi_csr_``NAME``_rdata <= csr_``NAME``_value;\t\\\n\t\t\trvfi_csr_``NAME``_wdata <= csr_``NAME``_wdata;\n\n`define NERV_CSR_VAL_MRW(NAME, ADDR, VALUE) \\\n\t`NERV_CSR_REG_MRW(NAME, ADDR, VALUE)\n\n`define NERV_CSR_VAL_MRO(NAME, ADDR, VALUE) \\\n\t\t\trvfi_csr_``NAME``_rmask <= 32'h ffff_ffff;\t\\\n\t\t\trvfi_csr_``NAME``_wmask <= 32'h ffff_ffff;\t\\\n\t\t\trvfi_csr_``NAME``_rdata <= csr_``NAME``_value;\t\\\n\t\t\trvfi_csr_``NAME``_wdata <= csr_``NAME``_value;\n\n`define NERV_CSR_ARR_DEF(ARRAY, DEPTH)\n`define NERV_CSR_ARR_MRW(ARRAY, INDEX, NAME, ADDR) \\\n\t`NERV_CSR_REG_MRW(NAME, ADDR, 32'h 0000_0000)\n\n`NERV_CSRS\n`undef NERV_CSR_REG_MRW\n`undef NERV_CSR_VAL_MRW\n`undef NERV_CSR_VAL_MRO\n`undef NERV_CSR_ARR_DEF\n`undef NERV_CSR_ARR_MRW\n`endif\n\t\tend\n`endif\n\n\t\t// reset\n\t\tif (reset || reset_q) begin\n\t\t\tpc <= RESET_ADDR - (reset ? 4 : 0);\n`ifdef NERV_RVFI\n\t\t\tnext_rvfi_intr <= 0;\n\t\t\trvfi_valid <= 0;\n\t\t\trvfi_order <= 0;\n\t\t\trvfi_trap <= 0;\n`endif\n\t\tend\n\tend\n\n\n`ifdef NERV_DBGREGS\n\twire [31:0] dbg_reg_x0  = 0;\n\twire [31:0] dbg_reg_x1  = regfile[1];\n\twire [31:0] dbg_reg_x2  = regfile[2];\n\twire [31:0] dbg_reg_x3  = regfile[3];\n\twire [31:0] dbg_reg_x4  = regfile[4];\n\twire [31:0] dbg_reg_x5  = regfile[5];\n\twire [31:0] dbg_reg_x6  = regfile[6];\n\twire [31:0] dbg_reg_x7  = regfile[7];\n\twire [31:0] dbg_reg_x8  = regfile[8];\n\twire [31:0] dbg_reg_x9  = regfile[9];\n\twire [31:0] dbg_reg_x10 = regfile[10];\n\twire [31:0] dbg_reg_x11 = regfile[11];\n\twire [31:0] dbg_reg_x12 = regfile[12];\n\twire [31:0] dbg_reg_x13 = regfile[13];\n\twire [31:0] dbg_reg_x14 = regfile[14];\n\twire [31:0] dbg_reg_x15 = regfile[15];\n\twire [31:0] dbg_reg_x16 = regfile[16];\n\twire [31:0] dbg_reg_x17 = regfile[17];\n\twire [31:0] dbg_reg_x18 = regfile[18];\n\twire [31:0] dbg_reg_x19 = regfile[19];\n\twire [31:0] dbg_reg_x20 = regfile[20];\n\twire [31:0] dbg_reg_x21 = regfile[21];\n\twire [31:0] dbg_reg_x22 = regfile[22];\n\twire [31:0] dbg_reg_x23 = regfile[23];\n\twire [31:0] dbg_reg_x24 = regfile[24];\n\twire [31:0] dbg_reg_x25 = regfile[25];\n\twire [31:0] dbg_reg_x26 = regfile[26];\n\twire [31:0] dbg_reg_x27 = regfile[27];\n\twire [31:0] dbg_reg_x28 = regfile[28];\n\twire [31:0] dbg_reg_x29 = regfile[29];\n\twire [31:0] dbg_reg_x30 = regfile[30];\n\twire [31:0] dbg_reg_x31 = regfile[31];\n`endif\nendmodule\n"
  },
  {
    "path": "cores/nerv/nervsoc.sv",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule nervsoc (\n\tinput clock,\n\tinput reset,\n\toutput reg [31:0] leds\n);\n\treg [31:0] imem [0:1023];\n\treg [31:0] dmem [0:1023];\n\n\twire stall = 0;\n\twire trap;\n\n\twire [31:0] imem_addr;\n\treg  [31:0] imem_data;\n\n\twire        dmem_valid;\n\twire [31:0] dmem_addr;\n\twire [3:0]  dmem_wstrb;\n\twire [31:0] dmem_wdata;\n\treg  [31:0] dmem_rdata;\n\n\tinitial begin\n\t\t$readmemh(\"firmware.hex\", imem);\n\tend\n\n\talways @(posedge clock)\n\t\timem_data <= imem[imem_addr[31:2]];\n\n\talways @(posedge clock) begin\n\t\tif (dmem_valid) begin\n\t\t\tif (dmem_addr == 32'h 0100_0000) begin\n\t\t\t\tif (dmem_wstrb[0]) leds[ 7: 0] <= dmem_wdata[ 7: 0];\n\t\t\t\tif (dmem_wstrb[1]) leds[15: 8] <= dmem_wdata[15: 8];\n\t\t\t\tif (dmem_wstrb[2]) leds[23:16] <= dmem_wdata[23:16];\n\t\t\t\tif (dmem_wstrb[3]) leds[31:24] <= dmem_wdata[31:24];\n\t\t\tend else begin\n\t\t\t\tif (dmem_wstrb[0]) dmem[dmem_addr[31:2]][ 7: 0] <= dmem_wdata[ 7: 0];\n\t\t\t\tif (dmem_wstrb[1]) dmem[dmem_addr[31:2]][15: 8] <= dmem_wdata[15: 8];\n\t\t\t\tif (dmem_wstrb[2]) dmem[dmem_addr[31:2]][23:16] <= dmem_wdata[23:16];\n\t\t\t\tif (dmem_wstrb[3]) dmem[dmem_addr[31:2]][31:24] <= dmem_wdata[31:24];\n\t\t\tend\n\t\t\tdmem_rdata <= dmem[dmem_addr[31:2]];\n\t\tend\n\tend\n\n\tnerv cpu (\n\t\t.clock     (clock     ),\n\t\t.reset     (reset     ),\n\t\t.stall     (stall     ),\n\t\t.trap      (trap      ),\n\n\t\t.imem_addr (imem_addr ),\n\t\t.imem_data (imem_data ),\n\n\t\t.dmem_valid(dmem_valid),\n\t\t.dmem_addr (dmem_addr ),\n\t\t.dmem_wstrb(dmem_wstrb),\n\t\t.dmem_wdata(dmem_wdata),\n\t\t.dmem_rdata(dmem_rdata)\n\t);\nendmodule\n"
  },
  {
    "path": "cores/nerv/sections.lds",
    "content": "MEMORY\n{\n    /* the memory in the testbench is 64k in size;\n     * set LENGTH=48k and leave at least 16k for stack */\n    RAM (xrw)       : ORIGIN = 0x00000000, LENGTH = 0x00c000\n}\n\nSECTIONS {\n    /* The program code and other data goes into FLASH */\n    .text :\n    {\n        . = ALIGN(4);\n        *(.text)           /* .text sections (code) */\n        *(.text*)          /* .text* sections (code) */\n        PROVIDE(__vector_start = .);\n        KEEP(*(.vectors));\n        *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n        *(.srodata)        /* .rodata sections (constants, strings, etc.) */\n        *(.srodata*)       /* .rodata* sections (constants, strings, etc.) */\n        . = ALIGN(4);\n        _etext = .;        /* define a global symbol at end of code */\n        _sidata = _etext;  /* This is used by the startup in order to initialize the .data secion */\n    } >RAM\n\n\n    /* This is the initialized data section\n    The program executes knowing that the data is in the RAM\n    but the loader puts the initial values in the FLASH (inidata).\n    It is one task of the startup to copy the initial values from FLASH to RAM. */\n    .data : AT ( _sidata )\n    {\n        . = ALIGN(4);\n        _sdata = .;        /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */\n        _ram_start = .;    /* create a global symbol at ram start for garbage collector */\n        . = ALIGN(4);\n        *(.data)           /* .data sections */\n        *(.data*)          /* .data* sections */\n        *(.sdata)           /* .sdata sections */\n        *(.sdata*)          /* .sdata* sections */\n        . = ALIGN(4);\n        _edata = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */\n    } >RAM\n\n    /* Uninitialized data section */\n    .bss :\n    {\n        . = ALIGN(4);\n        _sbss = .;         /* define a global symbol at bss start; used by startup code */\n        *(.bss)\n        *(.bss*)\n        *(.sbss)\n        *(.sbss*)\n        *(COMMON)\n\n        . = ALIGN(4);\n        _ebss = .;         /* define a global symbol at bss end; used by startup code */\n    } >RAM\n\n    /* this is to define the start of the heap, and make sure we have a minimum size */\n    .heap :\n    {\n        . = ALIGN(4);\n        _heap_start = .;    /* define a global symbol at heap start */\n    } >RAM\n}\n"
  },
  {
    "path": "cores/nerv/testbench.gtkw",
    "content": "[*]\n[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI\n[*] Tue Oct 20 19:25:31 2020\n[*]\n[dumpfile] \"/home/claire/Work/riscv-formal/cores/nerv/testbench.vcd\"\n[dumpfile_mtime] \"Tue Oct 20 19:24:49 2020\"\n[dumpfile_size] 76428\n[savefile] \"/home/claire/Work/riscv-formal/cores/nerv/testbench.gtkw\"\n[timestart] 305\n[size] 1397 995\n[pos] -1 -1\n*-6.000000 497 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1\n[treeopen] testbench.\n[sst_width] 240\n[signals_width] 174\n[sst_expanded] 1\n[sst_vpaned_height] 289\n@28\ntestbench.dut.clock\ntestbench.dut.reset\ntestbench.dut.stall\ntestbench.dut.trap\n@200\n-\n@22\ntestbench.dut.imem_addr[31:0]\ntestbench.dut.imem_data[31:0]\n@200\n-\n@28\ntestbench.dut.dmem_valid\n@22\ntestbench.dut.dmem_addr[31:0]\ntestbench.dut.dmem_wstrb[3:0]\ntestbench.dut.dmem_wdata[31:0]\ntestbench.dut.dmem_rdata[31:0]\n@200\n-\n@22\ntestbench.dut.pc[31:0]\ntestbench.dut.insn[31:0]\n@28\ntestbench.dut.illinsn\n@c00200\n-insn_decoded\n@22\ntestbench.dut.insn_funct7[6:0]\ntestbench.dut.insn_rs2[4:0]\ntestbench.dut.insn_rs1[4:0]\n@28\ntestbench.dut.insn_funct3[2:0]\n@22\ntestbench.dut.insn_rd[4:0]\ntestbench.dut.insn_opcode[6:0]\n@200\n-\n@22\ntestbench.dut.imm_b_sext[31:0]\ntestbench.dut.imm_i_sext[31:0]\ntestbench.dut.imm_j_sext[31:0]\ntestbench.dut.imm_s_sext[31:0]\n@1401200\n-insn_decoded\n@22\ntestbench.dut.rs1_value[31:0]\ntestbench.dut.rs2_value[31:0]\n@28\ntestbench.dut.next_wr\n@22\ntestbench.dut.next_rd[31:0]\n@c00200\n-registers\n@22\ntestbench.dut.dbg_reg_x0[31:0]\ntestbench.dut.dbg_reg_x1[31:0]\ntestbench.dut.dbg_reg_x2[31:0]\ntestbench.dut.dbg_reg_x3[31:0]\ntestbench.dut.dbg_reg_x4[31:0]\ntestbench.dut.dbg_reg_x5[31:0]\ntestbench.dut.dbg_reg_x6[31:0]\ntestbench.dut.dbg_reg_x7[31:0]\ntestbench.dut.dbg_reg_x8[31:0]\ntestbench.dut.dbg_reg_x9[31:0]\ntestbench.dut.dbg_reg_x10[31:0]\ntestbench.dut.dbg_reg_x11[31:0]\ntestbench.dut.dbg_reg_x12[31:0]\ntestbench.dut.dbg_reg_x13[31:0]\ntestbench.dut.dbg_reg_x14[31:0]\ntestbench.dut.dbg_reg_x15[31:0]\ntestbench.dut.dbg_reg_x16[31:0]\ntestbench.dut.dbg_reg_x17[31:0]\ntestbench.dut.dbg_reg_x18[31:0]\ntestbench.dut.dbg_reg_x19[31:0]\ntestbench.dut.dbg_reg_x20[31:0]\ntestbench.dut.dbg_reg_x21[31:0]\ntestbench.dut.dbg_reg_x22[31:0]\ntestbench.dut.dbg_reg_x23[31:0]\ntestbench.dut.dbg_reg_x24[31:0]\ntestbench.dut.dbg_reg_x25[31:0]\ntestbench.dut.dbg_reg_x26[31:0]\ntestbench.dut.dbg_reg_x27[31:0]\ntestbench.dut.dbg_reg_x28[31:0]\ntestbench.dut.dbg_reg_x29[31:0]\ntestbench.dut.dbg_reg_x30[31:0]\ntestbench.dut.dbg_reg_x31[31:0]\n@1401200\n-registers\n@200\n-\n@28\ntestbench.dut.mem_rd_enable\n@22\ntestbench.dut.mem_rd_addr[31:0]\ntestbench.dut.mem_rd_func[4:0]\ntestbench.dut.mem_rd_reg[4:0]\n@200\n-\n@28\ntestbench.dut.mem_rd_enable_q\n@22\ntestbench.dut.mem_rd_func_q[4:0]\ntestbench.dut.mem_rd_reg_q[4:0]\ntestbench.dut.mem_rdata[31:0]\n@200\n-\n@28\ntestbench.dut.mem_wr_enable\n@22\ntestbench.dut.mem_wr_addr[31:0]\ntestbench.dut.mem_wr_data[31:0]\ntestbench.dut.mem_wr_strb[3:0]\n@200\n-\n-CSRs\n@24\ntestbench.dut.csr_mcycle_value[31:0]\ntestbench.dut.csr_minstret_value[31:0]\n@28\ntestbench.dut.csr_mstatus_value[31:0]\n@22\ntestbench.dut.csr_mtvec_value[31:0]\ntestbench.dut.csr_mcause_value[31:0]\ntestbench.dut.csr_mepc_value[31:0]\n@201\n-Interrupts\n@22\ntestbench.dut.irq[31:0]\ntestbench.dut.irq_en[31:0]\ntestbench.dut.irq_num[4:0]\n[pattern_trace] 1\n[pattern_trace] 0\n"
  },
  {
    "path": "cores/nerv/testbench.sv",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  N. Engelhardt <nak@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule testbench;\n\nlocalparam MEM_ADDR_WIDTH = 16;\nlocalparam TIMEOUT = (1<<10);\n\nreg clock;\nreg reset = 1'b1;\nreg stall = 1'b0;\nwire trap;\n\nwire [31:0] imem_addr;\nreg  [31:0] imem_data;\n\nwire        dmem_valid;\nwire [31:0] dmem_addr;\nwire [ 3:0] dmem_wstrb;\nwire [31:0] dmem_wdata;\nreg  [31:0] dmem_rdata;\n\nreg  [31:0] irq = 'b0;\n\nalways #5 clock = clock === 1'b0;\nalways @(posedge clock) reset <= 0;\n\nreg [7:0] mem [0:(1<<MEM_ADDR_WIDTH)-1];\n\nwire wr_in_mem_range = (dmem_addr[31:2] < (1<<MEM_ADDR_WIDTH));\nwire wr_in_output = (dmem_addr == 32'h 02000000);\n\nreg [31:0] out;\nreg out_valid;\nalways @(posedge clock) begin\n\tif (out_valid) begin\n\t\t$write(\"%c\", out[7:0]);\n`ifndef VERILATOR\n\t\t$fflush();\n`endif\n\tend\nend\n\n`ifdef STALL\nalways @(posedge clock) begin\n\tstall <= $random;\nend\n`endif\n\nalways @(posedge clock) begin\n\tif (imem_addr >= (1<<MEM_ADDR_WIDTH)) begin\n\t\t$display(\"Memory access out of range: imem_addr = 0x%08x\", imem_addr);\n\tend\n\tif (dmem_valid && !(wr_in_mem_range || wr_in_output)) begin\n\t\t$display(\"Memory access out of range: dmem_addr = 0x%08x\", dmem_addr);\n\tend\nend\n\ninteger i;\nalways @(posedge clock) begin\n\tout <= 32'h 0;\n\tout_valid <= 1'b0;\n\tif (!stall && !reset) begin\n\t\timem_data <= {\n\t\t\tmem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b11}],\n\t\t\tmem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b10}],\n\t\t\tmem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b01}],\n\t\t\tmem[{imem_addr[MEM_ADDR_WIDTH-1:2], 2'b00}]\n\t\t};\n\n\t\tif (dmem_valid) begin\n\t\t\tdmem_rdata <= {\n\t\t\t\tmem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b11}],\n\t\t\t\tmem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b10}],\n\t\t\t\tmem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b01}],\n\t\t\t\tmem[{dmem_addr[MEM_ADDR_WIDTH-1:2], 2'b00}]\n\t\t\t};\n\t\t\tfor (i=0;i<4;i=i+1) begin\n\t\t\t\tif (dmem_wstrb[i]) begin\n\t\t\t\t\tif (wr_in_mem_range) begin\n\t\t\t\t\t\tmem[{dmem_addr[MEM_ADDR_WIDTH-1:2], i[1:0]}] <= dmem_wdata[(i*8)+: 8];\n\t\t\t\t\tend\n\t\t\t\t\tif (wr_in_output) begin\n\t\t\t\t\t\tout[(i*8)+: 8] <= dmem_wdata[(i*8)+: 8];\n\t\t\t\t\t\tout_valid <= 1'b1;\n\t\t\t\t\tend\n\t\t\t\t\tdmem_rdata <= 'hx;\n\t\t\t\tend\n\t\t\tend\n\t\tend else begin\n\t\t\tdmem_rdata <= 32'h XXXX_XXXX;\n\t\tend\n\tend\nend\n\ninitial begin\n\t$readmemh(\"firmware.hex\", mem);\n\tif ($test$plusargs(\"vcd\")) begin\n\t\t$dumpfile(\"testbench.vcd\");\n\t\t$dumpvars(0, testbench);\n\tend\nend\n\nnerv dut (\n\t.clock(clock),\n\t.reset(reset),\n\t.stall(stall),\n\t.trap(trap),\n\n\t.imem_addr(imem_addr),\n\t.imem_data(stall ? 32'bx : imem_data),\n\n\t.dmem_valid(dmem_valid),\n\t.dmem_addr(dmem_addr),\n\t.dmem_wstrb(dmem_wstrb),\n\t.dmem_wdata(dmem_wdata),\n\t.dmem_rdata(stall ? 32'bx : dmem_rdata),\n\n`ifdef NERV_FAULT\n\t.imem_fault(1'b0),\n\t.dmem_fault(1'b0),\n`endif\n\n\t.irq(irq)\n);\n\nreg [31:0] cycles = 0;\n\nalways @(posedge clock) begin\n\tcycles <= cycles + 32'h1;\n\tif (trap || (cycles >= TIMEOUT)) begin\n\t\t$display(\"Simulated %0d cycles\", cycles);\n\t\t$finish;\n\tend\nend\n\n\n\nendmodule\n"
  },
  {
    "path": "cores/nerv/trace.gtkw",
    "content": "[*]\n[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI\n[*] Wed Oct 21 17:13:34 2020\n[*]\n[dumpfile] \"(null)\"\n[savefile] \"/home/claire/Work/riscv-formal/cores/nerv/trace.gtkw\"\n[timestart] 0\n[size] 1259 841\n[pos] 2135 225\n*-5.139064 105 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1\n[treeopen] rvfi_testbench.\n[treeopen] rvfi_testbench.checker_inst.\n[treeopen] rvfi_testbench.wrapper.\n[sst_width] 240\n[signals_width] 287\n[sst_expanded] 1\n[sst_vpaned_height] 235\n@24\nsmt_step\n@200\n-\n-Core\n@28\nrvfi_testbench.wrapper.uut.clock\nrvfi_testbench.wrapper.uut.reset\nrvfi_testbench.wrapper.uut.stall\nrvfi_testbench.wrapper.uut.trap\n@200\n-\n@23\nrvfi_testbench.wrapper.uut.pc[31:0]\n@22\nrvfi_testbench.wrapper.uut.insn[31:0]\n@c00200\n-insn_decoded\n@22\nrvfi_testbench.wrapper.uut.insn_funct7[6:0]\nrvfi_testbench.wrapper.uut.insn_rs2[4:0]\nrvfi_testbench.wrapper.uut.insn_rs1[4:0]\n@28\nrvfi_testbench.wrapper.uut.insn_funct3[2:0]\n@22\nrvfi_testbench.wrapper.uut.insn_rd[4:0]\nrvfi_testbench.wrapper.uut.insn_opcode[6:0]\n@200\n-\n@22\nrvfi_testbench.wrapper.uut.imm_b_sext[31:0]\nrvfi_testbench.wrapper.uut.imm_i_sext[31:0]\nrvfi_testbench.wrapper.uut.imm_j_sext[31:0]\nrvfi_testbench.wrapper.uut.imm_s_sext[31:0]\n@1401200\n-insn_decoded\n@200\n-\n-Checker\n@24\nrvfi_testbench.checker_inst.rvfi_order[63:0]\n@28\nrvfi_testbench.checker_inst.rvfi_valid\n@29\nrvfi_testbench.checker_inst.spec_valid\n@28\nrvfi_testbench.checker_inst.rvfi_trap\n@22\nrvfi_testbench.checker_inst.rvfi_insn[31:0]\nrvfi_testbench.wrapper.uut.rvfi_pc_rdata[31:0]\n@c00200\n-spec\n@28\nrvfi_testbench.checker_inst.spec_valid\nrvfi_testbench.checker_inst.spec_trap\n@200\n-\n@22\nrvfi_testbench.checker_inst.spec_rs1_addr[4:0]\nrvfi_testbench.checker_inst.spec_rs2_addr[4:0]\nrvfi_testbench.checker_inst.spec_rd_addr[4:0]\nrvfi_testbench.checker_inst.spec_rd_wdata[31:0]\nrvfi_testbench.checker_inst.spec_pc_wdata[31:0]\n@200\n-\n@22\nrvfi_testbench.checker_inst.spec_mem_addr[31:0]\nrvfi_testbench.checker_inst.spec_mem_wdata[31:0]\nrvfi_testbench.checker_inst.spec_mem_rmask[3:0]\nrvfi_testbench.checker_inst.spec_mem_wmask[3:0]\n@1401200\n-spec\n@c00200\n-rvfi\n@24\nrvfi_testbench.checker_inst.rvfi_order[63:0]\n@28\nrvfi_testbench.checker_inst.rvfi_valid\nrvfi_testbench.checker_inst.rvfi_trap\nrvfi_testbench.checker_inst.rvfi_halt\nrvfi_testbench.checker_inst.rvfi_intr\nrvfi_testbench.checker_inst.rvfi_ixl[1:0]\nrvfi_testbench.checker_inst.rvfi_mode[1:0]\n@22\nrvfi_testbench.checker_inst.rvfi_insn[31:0]\n@200\n-\n@22\nrvfi_testbench.checker_inst.rvfi_pc_rdata[31:0]\nrvfi_testbench.checker_inst.rvfi_pc_wdata[31:0]\n@200\n-\n@22\nrvfi_testbench.checker_inst.rvfi_rs1_addr[4:0]\nrvfi_testbench.checker_inst.rvfi_rs2_addr[4:0]\nrvfi_testbench.checker_inst.rvfi_rd_addr[4:0]\n@200\n-\n@22\nrvfi_testbench.checker_inst.rvfi_rs1_rdata[31:0]\nrvfi_testbench.checker_inst.rvfi_rs2_rdata[31:0]\nrvfi_testbench.checker_inst.rvfi_rd_wdata[31:0]\n@200\n-\n@22\nrvfi_testbench.checker_inst.rvfi_mem_addr[31:0]\nrvfi_testbench.checker_inst.rvfi_mem_rdata[31:0]\nrvfi_testbench.checker_inst.rvfi_mem_rmask[3:0]\nrvfi_testbench.checker_inst.rvfi_mem_wdata[31:0]\nrvfi_testbench.checker_inst.rvfi_mem_wmask[3:0]\n@1401200\n-rvfi\n@c00200\n-csr\n@28\nrvfi_testbench.checker_inst.check\nrvfi_testbench.checker_inst.csr_write_valid\nrvfi_testbench.checker_inst.csr_read_valid\nrvfi_testbench.checker_inst.csr_written\nrvfi_testbench.checker_inst.csr_read_shadowed\nrvfi_testbench.checker_inst.csr_mode_shadow\n@22\nrvfi_testbench.checker_inst.csr_mode[1:0]\nrvfi_testbench.checker_inst.csr_insn_addr[11:0]\nrvfi_testbench.checker_inst.csr_insn_rdata[31:0]\nrvfi_testbench.checker_inst.csr_insn_rmask[31:0]\nrvfi_testbench.checker_inst.csr_insn_wdata[31:0]\nrvfi_testbench.checker_inst.csr_insn_wmask[31:0]\nrvfi_testbench.checker_inst.rsval_shadow[31:0]\nrvfi_testbench.checker_inst.wdata_shadow[31:0]\nrvfi_testbench.checker_inst.rdata_shadow[31:0]\nrvfi_testbench.checker_inst.csr_mode_shadow[1:0]\n@1401200\n-csr\n[pattern_trace] 1\n[pattern_trace] 0\n"
  },
  {
    "path": "cores/nerv/vectors.s",
    "content": "/*\n* Copyright 2019 ETH Zürich and University of Bologna\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*/\n\n.section .vectors, \"ax\"\n.option norvc\nvector_table:\n\tj sw_irq_handler         /* 0 */\n\tj __no_irq_handler       /* 1 */\n\tj __no_irq_handler       /* 2 */\n\tj software_irq_handler   /* 3 */\n\tj __no_irq_handler       /* 4 */\n\tj __no_irq_handler       /* 5 */\n\tj __no_irq_handler       /* 6 */\n\tj timer_irq_handler      /* 7 */\n\tj __no_irq_handler       /* 8 */\n\tj __no_irq_handler       /* 9 */\n\tj __no_irq_handler       /* 10 */\n\tj external_irq_handler   /* 11 */\n\tj __no_irq_handler       /* 12 */\n\tj __no_irq_handler       /* 13 */\n\tj __no_irq_handler       /* 14 */\n\tj __no_irq_handler       /* 15 */\n\tj __no_irq_handler       /* 16 */\n\tj __no_irq_handler       /* 17 */\n\tj __no_irq_handler       /* 18 */\n\tj __no_irq_handler       /* 19 */\n\tj __no_irq_handler       /* 20 */\n\tj __no_irq_handler       /* 21 */\n\tj __no_irq_handler       /* 22 */\n\tj __no_irq_handler       /* 23 */\n\tj __no_irq_handler       /* 24 */\n\tj __no_irq_handler       /* 25 */\n\tj __no_irq_handler       /* 26 */\n\tj __no_irq_handler       /* 27 */\n\tj __no_irq_handler       /* 28 */\n\tj __no_irq_handler       /* 29 */\n\tj __no_irq_handler       /* 30 */\n\tj __no_irq_handler       /* 31 */\n\n.section .text.vecs\n/* exception handling */\n__no_irq_handler:\n\tla a0, no_exception_handler_msg\n\tjal ra, puts\n\tj __no_irq_handler\n\n\nsw_irq_handler:\n\tcsrr t0, mcause\n\tslli t0, t0, 1  /* shift off the high bit */\n\tsrli t0, t0, 1\n\tli t1, 2\n\tbeq t0, t1, handle_illegal_insn\n\tli t1, 11\n\tbeq t0, t1, handle_ecall\n\tli t1, 3\n\tbeq t0, t1, handle_ebreak\n\tj handle_unknown\n\nhandle_ecall:\n\tla a0, ecall_msg\n\tjal ra, puts\n\tj end_handler\n\nhandle_ebreak:\n\tla a0, ebreak_msg\n\tjal ra, puts\n\tj end_handler\n\nhandle_illegal_insn:\n\tla a0, illegal_insn_msg\n\tjal ra, puts\n\tj end_handler\n\nhandle_unknown:\n\tla a0, unknown_msg\n\tjal ra, puts\n\tj end_handler\n\nend_handler:\n\tcsrr a0, mepc\n\taddi a0, a0, 4\n\tcsrw mepc, a0\n\tmret\n/* this interrupt can be generated for verification purposes, random or when the PC is equal to a given value*/\nverification_irq_handler:\n\tmret\n\nsoftware_irq_handler:\n\tla a0, software_irq_msg\n\tjal ra, puts\n\tmret\n\ntimer_irq_handler:\n\tla a0, timer_irq_msg\n\tjal ra, puts\n\tmret\n\nexternal_irq_handler:\n\tla a0, external_irq_msg\n\tjal ra, puts\n\tmret\n\n\n.section .rodata\nillegal_insn_msg:\n\t.string \"illegal instruction exception handler entered\\n\"\necall_msg:\n\t.string \"ecall exception handler entered\\n\"\nebreak_msg:\n\t.string \"ebreak exception handler entered\\n\"\nunknown_msg:\n\t.string \"unknown exception handler entered\\n\"\nno_exception_handler_msg:\n\t.string \"no exception handler installed\\n\"\nsoftware_irq_msg:\n\t.string \"software irq handler entered\\n\"\ntimer_irq_msg:\n\t.string \"timer irq handler entered\\n\"\nexternal_irq_msg:\n\t.string \"external irq handler entered\\n\"\n"
  },
  {
    "path": "cores/nerv/wrapper.sv",
    "content": "/*\n *  NERV -- Naive Educational RISC-V Processor\n *\n *  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>\n *\n *  Permission to use, copy, modify, and/or distribute this software for any\n *  purpose with or without fee is hereby granted, provided that the above\n *  copyright notice and this permission notice appear in all copies.\n *\n *  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\nmodule rvfi_wrapper (\n\tinput         clock,\n\tinput         reset,\n\t`RVFI_OUTPUTS\n\t`RVFI_BUS_OUTPUTS\n);\n\t(* keep *) `rvformal_rand_reg stall;\n\t(* keep *) `rvformal_rand_reg [31:0] imem_data;\n\t(* keep *) `rvformal_rand_reg [31:0] dmem_rdata;\n\t(* keep *) `rvformal_rand_reg [31:0] irq;\n\n`ifdef NERV_FAULT\n\t(* keep *) `rvformal_rand_reg imem_fault;\n\t(* keep *) `rvformal_rand_reg dmem_fault;\n`else\n\twire imem_fault = 0;\n\twire dmem_fault = 0;\n`endif\n\n\t(* keep *) wire trap;\n\n\t(* keep *) wire [31:0] imem_addr;\n\n\t(* keep *) wire        dmem_valid;\n\t(* keep *) wire [31:0] dmem_addr;\n\t(* keep *) wire [ 3:0] dmem_wstrb;\n\t(* keep *) wire [31:0] dmem_wdata;\n\n\tnerv uut (\n\t\t.clock      (clock    ),\n\t\t.reset      (reset    ),\n\t\t.stall      (stall    ),\n\t\t.trap       (trap     ),\n\n\t\t.imem_addr  (imem_addr ),\n\t\t.imem_data  (imem_data ),\n\n\t\t.dmem_valid (dmem_valid),\n\t\t.dmem_addr  (dmem_addr ),\n\t\t.dmem_wstrb (dmem_wstrb),\n\t\t.dmem_wdata (dmem_wdata),\n\t\t.dmem_rdata (dmem_rdata),\n\n`ifdef NERV_FAULT\n\t\t.imem_fault (imem_fault),\n\t\t.dmem_fault (dmem_fault),\n`endif\n\n\t\t.irq (irq),\n\n\t\t`RVFI_CONN32\n\t);\n\n`ifdef RISCV_FORMAL_BUS\n\n`define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \\\n\t(* keep *) reg [(width) - 1:0] imem_``name; assign rvfi_``name[0 * (width) +: (width)] = imem_``name;\n`RVFI_BUS_SIGNALS\n`undef RISCV_FORMAL_CHANNEL_SIGNAL\n\n`define RISCV_FORMAL_CHANNEL_SIGNAL(channels, width, name) \\\n\t(* keep *) reg [(width) - 1:0] dmem_``name; assign rvfi_``name[1 * (width) +: (width)] = dmem_``name;\n`RVFI_BUS_SIGNALS\n`undef RISCV_FORMAL_CHANNEL_SIGNAL\n\n\n\treg [31:0] imem_addr_q;\n\n\talways @(posedge clock) begin\n\t\tif (!stall)\n\t\t\timem_addr_q <= imem_addr;\n\tend\n\n\talways @* begin\n\t\timem_bus_addr  = imem_addr_q;\n\t\timem_bus_insn  = 1;\n\t\timem_bus_data  = 0;\n\t\timem_bus_rmask = 4'b1111;\n\t\timem_bus_wmask = 4'b0000;\n\t\timem_bus_rdata = imem_data;\n\t\timem_bus_wdata = 0;\n\t\timem_bus_fault = imem_fault;\n\t\timem_bus_valid = !stall;\n\tend;\n\n\treg        dmem_valid_q;\n\treg [31:0] dmem_addr_q;\n\treg [ 3:0] dmem_wstrb_q;\n\treg [31:0] dmem_wdata_q;\n\n\n\t(* keep *) `rvformal_rand_reg [31:0] next_dmem_rdata;\n\treg [31:0] next_dmem_rdata_q;\n\n`ifdef NERV_FAULT\n\t(* keep *) `rvformal_rand_reg [31:0] next_dmem_fault;\n\treg [31:0] next_dmem_fault_q;\n`endif\n\n\talways @(posedge clock) begin\n\t\tif (!stall) begin\n\t\t\tnext_dmem_rdata_q <= next_dmem_rdata;\n`ifdef NERV_FAULT\n\t\t\tnext_dmem_fault_q <= next_dmem_fault;\n`endif\n\t\tend\n\tend\n\n\talways @* begin\n\t\tif (!stall) begin\n\t\t\tassume (dmem_rdata == next_dmem_rdata_q);\n`ifdef NERV_FAULT\n\t\t\tassume (dmem_fault == next_dmem_fault_q);\n`endif\n\t\tend\n\t\tdmem_bus_addr  = dmem_addr;\n\t\tdmem_bus_insn  = 0;\n\t\tdmem_bus_data  = 1;\n\t\tdmem_bus_rmask = dmem_wstrb ? 4'b0000 : 4'b1111;\n\t\tdmem_bus_wmask = dmem_wstrb;\n\t\tdmem_bus_rdata = next_dmem_rdata;\n\t\tdmem_bus_wdata = dmem_wdata;\n\t\tdmem_bus_fault = next_dmem_fault;\n\t\tdmem_bus_valid = !stall && dmem_valid;\n\tend;\n\n`endif\n\n`ifdef NERV_FAIRNESS\n\treg [2:0] stalled = 0;\n\talways @(posedge clock) begin\n\t\tstalled <= {stalled, stall};\n\t\tassume (~stalled);\n\tend\n`endif\nendmodule\n"
  },
  {
    "path": "cores/picorv32/.gitignore",
    "content": "/cover/\n/complete/\n/honest/\n/checks/\n/testbug[0-9][0-9][0-9].cfg\n/testbug[0-9][0-9][0-9]/\n/testbugs.mk\n/cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9]\n/cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9].zip\n/picorv32.v\n/disasm.s\n/disasm.o\n"
  },
  {
    "path": "cores/picorv32/Makefile",
    "content": "\npicorv32.v:\n\twget -O picorv32.v https://raw.githubusercontent.com/YosysHQ/picorv32/master/picorv32.v\n\nchecks: picorv32.v\n\tpython3 ../../checks/genchecks.py\n\t$(MAKE) -C checks\n\ncheck: checks\n\tbash cexdata.sh\n\tcat cexdata-*/status.txt\n\nclean:\n\trm -f picorv32.v cexdata-*.zip\n\trm -rf disasm.o disasm.s checks/ cexdata-*/\n\trm -f testbug*.cfg\n\trm -rf testbug*/\n"
  },
  {
    "path": "cores/picorv32/README.md",
    "content": "\nriscv-formal proofs for picorv32\n================================\n\nQuickstart guide:\n\nFirst install Yosys, SBY, and the solvers. See the \n[SBY Installation Guide](https://yosyshq.readthedocs.io/projects/sby/en/latest/install.html)\nfor instructions.  Then download the core, generate the formal checks and run them:\n\n```\nmake check -j$(nproc)\n```\n\n"
  },
  {
    "path": "cores/picorv32/cexdata.sh",
    "content": "#!/bin/bash\n\nset -ex\ncexdata=\"cexdata-$(date '+%Y%m%d')\"\n\nrm -rf $cexdata\nmkdir $cexdata\n\nfor x in {checks,testbug[0-9][0-9][0-9]}/*/FAIL; do\n\ttest -f $x || continue\n\tx=${x%/FAIL}\n\ty=${x/\\//_}\n\tcp $x/logfile.txt $cexdata/$y.log\n\tif test -f $x/engine_*/trace.vcd; then\n\t\tcp $x/engine_*/trace.vcd $cexdata/$y.vcd\n\t\tpython3 disasm.py $cexdata/$y.vcd > $cexdata/$y.asm\n\tfi\ndone\n\nfor x in {checks,testbug[0-9][0-9][0-9]}/*.sby; do\n\ttest -f $x || continue\n\tx=${x%.sby}\n\tif [ -f $x/PASS ]; then\n\t\tprintf \"%-30s %s %10s\\n\" $x pass $(sed '/Elapsed process time/ { s/.*\\]: //; s/ .*//; p; }; d;' $x/logfile.txt)\n\telif [ -f $x/FAIL ]; then\n\t\tprintf \"%-30s %s %10s\\n\" $x FAIL $(sed '/Elapsed process time/ { s/.*\\]: //; s/ .*//; p; }; d;' $x/logfile.txt)\n\telse\n\t\tprintf \"%-30s %s\\n\" $x unknown\n\tfi\ndone | awk '{ print gensub(\":\", \"\", \"g\", $3), $0; }' | sort -n | cut -f2- -d' ' > $cexdata/status.txt\n\nrm -f $cexdata.zip\nzip -r $cexdata.zip $cexdata/\n"
  },
  {
    "path": "cores/picorv32/checks.cfg",
    "content": "[options]\nisa rv32imc\n\n[depth]\ninsn            20\nreg       15    25\npc_fwd    10    30\npc_bwd    10    30\nliveness  1  10 30\nunique    1  10 30\ncausal    10    30\ncover     1     15\n\ncsrw            15\ncsr_ill         15\ncsrc_inc   1    15\ncsrc_upcnt 1    15\n\n[sort]\nreg_ch0\n\n[csrs]\nmcycle          inc upcnt\nminstret        inc upcnt\n\n[illegal_csrs]\nc00     u       w\nc80     u       w\nc02     u       w\nc82     u       w\n\n[defines]\n`define RISCV_FORMAL_ALIGNED_MEM\n`define RISCV_FORMAL_ALTOPS\n`define RISCV_FORMAL_UMODE\n`define PICORV32_TESTBUG_NONE\n`define DEBUGNETS\n\n[defines liveness]\n`define PICORV32_FAIRNESS\n\n[verilog-files]\n@basedir@/cores/@core@/wrapper.sv\n@basedir@/cores/@core@/@core@.v\n\n[cover]\nalways @* if (!reset) cover (channel[0].cnt_insns == 2);\n"
  },
  {
    "path": "cores/picorv32/checks.gtkw",
    "content": "[*]\n[*] GTKWave Analyzer v3.3.65 (w)1999-2015 BSI\n[*] Wed Sep 13 00:29:24 2017\n[*]\n[dumpfile] \"(null)\"\n[savefile] \"/home/claire/Work/riscv-formal/cores/picorv32/checks.gtkw\"\n[timestart] 0\n[size] 1263 878\n[pos] -1 -1\n*-6.814997 100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1\n[treeopen] rvfi_testbench.\n[treeopen] rvfi_testbench.wrapper.\n[sst_width] 225\n[signals_width] 335\n[sst_expanded] 1\n[sst_vpaned_height] 258\n@24\nsmt_step\n@200\n-\n-PicoRV32\n@28\nrvfi_testbench.wrapper.uut.resetn\n@820\nrvfi_testbench.wrapper.uut.dbg_ascii_state[127:0]\nrvfi_testbench.wrapper.uut.dbg_ascii_instr[63:0]\n@200\n-\n@28\nrvfi_testbench.wrapper.mem_valid\nrvfi_testbench.wrapper.mem_ready\nrvfi_testbench.wrapper.mem_instr\n@22\nrvfi_testbench.wrapper.mem_addr[31:0]\nrvfi_testbench.wrapper.mem_wstrb[3:0]\nrvfi_testbench.wrapper.mem_rdata[31:0]\nrvfi_testbench.wrapper.mem_wdata[31:0]\n@200\n-\n-RVFI\n@28\nrvfi_testbench.checker_inst.reset\nrvfi_testbench.checker_inst.trig\nrvfi_testbench.checker_inst.check\n@200\n-\n@28\nrvfi_testbench.checker_inst.rvfi_valid\nrvfi_testbench.checker_inst.rvfi_trap\nrvfi_testbench.checker_inst.rvfi_intr\nrvfi_testbench.checker_inst.rvfi_halt\n@200\n-\n@25\nrvfi_testbench.checker_inst.rvfi_order[63:0]\n@22\nrvfi_testbench.checker_inst.rvfi_insn[31:0]\nrvfi_testbench.checker_inst.rvfi_pc_rdata[31:0]\nrvfi_testbench.checker_inst.rvfi_pc_wdata[31:0]\n@200\n-\n@22\nrvfi_testbench.checker_inst.rvfi_rs1_addr[4:0]\nrvfi_testbench.checker_inst.rvfi_rs2_addr[4:0]\nrvfi_testbench.checker_inst.rvfi_rd_addr[4:0]\n@200\n-\n@22\nrvfi_testbench.checker_inst.rvfi_rs1_rdata[31:0]\nrvfi_testbench.checker_inst.rvfi_rs2_rdata[31:0]\nrvfi_testbench.checker_inst.rvfi_rd_wdata[31:0]\n@200\n-\n@22\nrvfi_testbench.checker_inst.rvfi_mem_addr[31:0]\nrvfi_testbench.checker_inst.rvfi_mem_rmask[3:0]\nrvfi_testbench.checker_inst.rvfi_mem_wmask[3:0]\nrvfi_testbench.checker_inst.rvfi_mem_rdata[31:0]\nrvfi_testbench.checker_inst.rvfi_mem_wdata[31:0]\n@200\n-\n[pattern_trace] 1\n[pattern_trace] 0\n"
  },
  {
    "path": "cores/picorv32/complete.sby",
    "content": "[options]\nmode bmc\naigsmt z3\ndepth 20\n\n[engines]\nabc bmc3\n\n[script]\nverilog_defines -D DEBUGNETS\nverilog_defines -D RISCV_FORMAL\nverilog_defines -D RISCV_FORMAL_NRET=1\nverilog_defines -D RISCV_FORMAL_XLEN=32\nverilog_defines -D RISCV_FORMAL_ILEN=32\nverilog_defines -D RISCV_FORMAL_COMPRESSED\nverilog_defines -D RISCV_FORMAL_ALIGNED_MEM\nread_verilog -sv rvfi_macros.vh\nread_verilog -sv picorv32.v\n\n--pycode-begin--\nwith open(\"../../insns/isa_rv32ic.txt\") as f:\n  for line in f:\n    output(\"read_verilog -sv insn_%s.v\" % line.strip())\n--pycode-end--\n\nread_verilog -sv isa_rv32ic.v\nread_verilog -sv complete.sv\nprep -nordff -top testbench\n\n[files]\ncomplete.sv\n../../../picorv32/picorv32.v\n../../checks/rvfi_macros.vh\n../../insns/isa_rv32ic.v\n\n--pycode-begin--\nwith open(\"../../insns/isa_rv32ic.txt\") as f:\n  for line in f:\n    output(\"../../insns/insn_%s.v\" % line.strip())\n--pycode-end--\n\n"
  },
  {
    "path": "cores/picorv32/complete.sv",
    "content": "module testbench (\n\tinput clk,\n\n\tinput         mem_ready,\n\toutput        mem_valid,\n\toutput        mem_instr,\n\toutput [31:0] mem_addr,\n\toutput [31:0] mem_wdata,\n\toutput [3:0]  mem_wstrb,\n\tinput  [31:0] mem_rdata,\n\n);\n\treg resetn = 0;\n\twire trap;\n\n\talways @(posedge clk)\n\t\tresetn <= 1;\n\n\t`RVFI_WIRES\n\n\tpicorv32 #(\n\t\t.COMPRESSED_ISA(1),\n\t\t.BARREL_SHIFTER(1)\n\t) uut (\n\t\t.clk            (clk           ),\n\t\t.resetn         (resetn        ),\n\t\t.trap           (trap          ),\n\n\t\t.mem_valid      (mem_valid     ),\n\t\t.mem_instr      (mem_instr     ),\n\t\t.mem_ready      (mem_ready     ),\n\t\t.mem_addr       (mem_addr      ),\n\t\t.mem_wdata      (mem_wdata     ),\n\t\t.mem_wstrb      (mem_wstrb     ),\n\t\t.mem_rdata      (mem_rdata     ),\n\n\t\t`RVFI_CONN\n\t);\n\n\t(* keep *) wire                                spec_valid;\n\t(* keep *) wire                                spec_trap;\n\t(* keep *) wire [                       4 : 0] spec_rs1_addr;\n\t(* keep *) wire [                       4 : 0] spec_rs2_addr;\n\t(* keep *) wire [                       4 : 0] spec_rd_addr;\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata;\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata;\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr;\n\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask;\n\t(* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask;\n\t(* keep *) wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata;\n\n\trvfi_isa_rv32ic isa_spec (\n\t\t.rvfi_valid    (rvfi_valid    ),\n\t\t.rvfi_insn     (rvfi_insn     ),\n\t\t.rvfi_pc_rdata (rvfi_pc_rdata ),\n\t\t.rvfi_rs1_rdata(rvfi_rs1_rdata),\n\t\t.rvfi_rs2_rdata(rvfi_rs2_rdata),\n\t\t.rvfi_mem_rdata(rvfi_mem_rdata),\n\n\t\t.spec_valid    (spec_valid    ),\n\t\t.spec_trap     (spec_trap     ),\n\t\t.spec_rs1_addr (spec_rs1_addr ),\n\t\t.spec_rs2_addr (spec_rs2_addr ),\n\t\t.spec_rd_addr  (spec_rd_addr  ),\n\t\t.spec_rd_wdata (spec_rd_wdata ),\n\t\t.spec_pc_wdata (spec_pc_wdata ),\n\t\t.spec_mem_addr (spec_mem_addr ),\n\t\t.spec_mem_rmask(spec_mem_rmask),\n\t\t.spec_mem_wmask(spec_mem_wmask),\n\t\t.spec_mem_wdata(spec_mem_wdata)\n\t);\n\n\talways @* begin\n\t\tif (resetn && rvfi_valid && !rvfi_trap) begin\n\t\t\tif (rvfi_insn[6:0] != 7'b1110011)\n\t\t\t\tassert(spec_valid && !spec_trap);\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "cores/picorv32/cover.sby",
    "content": "[options]\nmode cover\ndepth 100\n\n[engines]\nsmtbmc boolector\n\n[script]\nverilog_defines -D RISCV_FORMAL\nverilog_defines -D RISCV_FORMAL_NRET=1\nverilog_defines -D RISCV_FORMAL_XLEN=32\nverilog_defines -D RISCV_FORMAL_ILEN=32\nverilog_defines -D RISCV_FORMAL_ALIGNED_MEM\nread_verilog rvfi_macros.vh\nread_verilog picorv32.v\nread_verilog -sv -formal cover.sv\nprep -nordff -top testbench\n\n[files]\n../../checks/rvfi_macros.vh\n../../../picorv32/picorv32.v\ncover.sv\n"
  },
  {
    "path": "cores/picorv32/cover.sv",
    "content": "module testbench (\n\tinput clk,\n\n\tinput         mem_ready,\n\toutput        mem_valid,\n\toutput        mem_instr,\n\toutput [31:0] mem_addr,\n\toutput [31:0] mem_wdata,\n\toutput [3:0]  mem_wstrb,\n\tinput  [31:0] mem_rdata,\n\n);\n\treg resetn = 0;\n\twire trap;\n\n\talways @(posedge clk)\n\t\tresetn <= 1;\n\n\t`RVFI_WIRES\n\n\tpicorv32 #(\n\t\t.REGS_INIT_ZERO(1),\n\t\t.COMPRESSED_ISA(1),\n\t\t.BARREL_SHIFTER(1)\n\t) uut (\n\t\t.clk            (clk           ),\n\t\t.resetn         (resetn        ),\n\t\t.trap           (trap          ),\n\n\t\t.mem_valid      (mem_valid     ),\n\t\t.mem_instr      (mem_instr     ),\n\t\t.mem_ready      (mem_ready     ),\n\t\t.mem_addr       (mem_addr      ),\n\t\t.mem_wdata      (mem_wdata     ),\n\t\t.mem_wstrb      (mem_wstrb     ),\n\t\t.mem_rdata      (mem_rdata     ),\n\n\t\t`RVFI_CONN\n\t);\n\n\tinteger count_dmemrd = 0;\n\tinteger count_dmemwr = 0;\n\tinteger count_longinsn = 0;\n\tinteger count_comprinsn = 0;\n\n\talways @(posedge clk) begin\n\t\tif (resetn && rvfi_valid) begin\n\t\t\tif (rvfi_mem_rmask)\n\t\t\t\tcount_dmemrd <= count_dmemrd + 1;\n\t\t\tif (rvfi_mem_wmask)\n\t\t\t\tcount_dmemwr <= count_dmemwr + 1;\n\t\t\tif (rvfi_insn[1:0] == 3)\n\t\t\t\tcount_longinsn <= count_longinsn + 1;\n\t\t\tif (rvfi_insn[1:0] != 3)\n\t\t\t\tcount_comprinsn <= count_comprinsn + 1;\n\t\tend\n\tend\n\n\tcover property (count_dmemrd);\n\tcover property (count_dmemwr);\n\tcover property (count_longinsn);\n\tcover property (count_comprinsn);\n\n\tcover property (count_dmemrd >= 1 && count_dmemwr >= 1 && count_longinsn >= 1 && count_comprinsn >= 1);\n\tcover property (count_dmemrd >= 2 && count_dmemwr >= 2 && count_longinsn >= 2 && count_comprinsn >= 2);\n\tcover property (count_dmemrd >= 3 && count_dmemwr >= 2 && count_longinsn >= 2 && count_comprinsn >= 2);\n\tcover property (count_dmemrd >= 2 && count_dmemwr >= 3 && count_longinsn >= 2 && count_comprinsn >= 2);\n\tcover property (count_dmemrd >= 2 && count_dmemwr >= 2 && count_longinsn >= 3 && count_comprinsn >= 2);\n\tcover property (count_dmemrd >= 2 && count_dmemwr >= 2 && count_longinsn >= 2 && count_comprinsn >= 3);\nendmodule\n"
  },
  {
    "path": "cores/picorv32/disasm.py",
    "content": "#!/usr/bin/env python3\n\nfrom Verilog_VCD.Verilog_VCD import parse_vcd\nfrom os import system\nfrom sys import argv\n\nrvfi_valid = None\nrvfi_order = None\nrvfi_insn = None\n\nfor netinfo in parse_vcd(argv[1]).values():\n    for net in netinfo['nets']:\n        # print(net[\"hier\"], net[\"name\"])\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_valid\":\n            rvfi_valid = netinfo['tv']\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_order\":\n            rvfi_order = netinfo['tv']\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_insn\":\n            rvfi_insn = netinfo['tv']\n\nassert len(rvfi_valid) == len(rvfi_order)\nassert len(rvfi_valid) == len(rvfi_insn)\n\nprog = list()\n\nfor tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn):\n    if tv_valid[1] == '1':\n        prog.append((int(tv_order[1], 2), int(tv_insn[1], 2)))\n\nwith open(\"disasm.s\", \"w\") as f:\n    for tv_order, tv_insn in sorted(prog):\n        if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0:\n            print(\".hword 0x%04x # %d\" % (tv_insn, tv_order), file=f)\n        else:\n            print(\".word 0x%08x # %d\" % (tv_insn, tv_order), file=f)\n\nsystem(\"riscv32-unknown-elf-gcc -c disasm.s\")\nsystem(\"riscv32-unknown-elf-objdump -d -M numeric,no-aliases disasm.o\")\n\n"
  },
  {
    "path": "cores/picorv32/dmemcheck.sv",
    "content": "module testbench (\n\tinput clk,\n\n\tinput         mem_ready,\n\toutput        mem_valid,\n\toutput        mem_instr,\n\toutput [31:0] mem_addr,\n\toutput [31:0] mem_wdata,\n\toutput [3:0]  mem_wstrb,\n\tinput  [31:0] mem_rdata\n);\n\treg resetn = 0;\n\twire trap;\n\n\talways @(posedge clk)\n\t\tresetn <= 1;\n\n\t`RVFI_WIRES\n\n\twire [31:0] dmem_addr;\n\treg [31:0] dmem_data;\n\n\trvfi_dmem_check checker_inst (\n\t\t.clock     (clk      ),\n\t\t.reset     (!resetn  ),\n\t\t.enable    (1'b1     ),\n\t\t.dmem_addr (dmem_addr),\n\t\t`RVFI_CONN\n\t);\n\n\talways @(posedge clk) begin\n\t\tif (resetn && mem_valid && mem_ready && mem_addr == dmem_addr) begin\n\t\t\tif (mem_wstrb[0]) dmem_data[ 7: 0] <= mem_wdata[ 7: 0];\n\t\t\tif (mem_wstrb[1]) dmem_data[15: 8] <= mem_wdata[15: 8];\n\t\t\tif (mem_wstrb[2]) dmem_data[23:16] <= mem_wdata[23:16];\n\t\t\tif (mem_wstrb[3]) dmem_data[31:24] <= mem_wdata[31:24];\n\t\tend\n\tend\n\n\talways @* begin\n\t\tif (resetn && mem_valid && mem_ready && mem_addr == dmem_addr && !mem_wstrb)\n\t\t\tassume(dmem_data == mem_rdata);\n\tend\n\n\tpicorv32 #(\n\t\t.REGS_INIT_ZERO(1),\n\t\t.COMPRESSED_ISA(1),\n\t\t.BARREL_SHIFTER(1)\n\t) uut (\n\t\t.clk            (clk           ),\n\t\t.resetn         (resetn        ),\n\t\t.trap           (trap          ),\n\n\t\t.mem_valid      (mem_valid     ),\n\t\t.mem_instr      (mem_instr     ),\n\t\t.mem_ready      (mem_ready     ),\n\t\t.mem_addr       (mem_addr      ),\n\t\t.mem_wdata      (mem_wdata     ),\n\t\t.mem_wstrb      (mem_wstrb     ),\n\t\t.mem_rdata      (mem_rdata     ),\n\n\t\t`RVFI_CONN\n\t);\n\n\treg [4:0] mem_wait = 0;\n\talways @(posedge clk) begin\n\t\tmem_wait <= {mem_wait, mem_valid && !mem_ready};\n\t\t// restrict(~mem_wait && !trap);\n\tend\nendmodule\n\n"
  },
  {
    "path": "cores/picorv32/equiv.sh",
    "content": "#!/bin/bash\nset -ex\nyosys -p '\n\tread_verilog picorv32.v\n\tchparam -set COMPRESSED_ISA 0 -set BARREL_SHIFTER 1 picorv32\n\tprep -flatten -top picorv32\n\tdesign -stash gold\n\n\tread_verilog -D RISCV_FORMAL picorv32.v\n\tchparam -set COMPRESSED_ISA 0 -set BARREL_SHIFTER 1 picorv32\n\tprep -flatten -top picorv32\n\tdelete -port picorv32/rvfi_*\n\tdesign -stash gate\n\n\tdesign -copy-from gold -as gold picorv32\n\tdesign -copy-from gate -as gate picorv32\n\tmemory_map; opt -fast\n\tequiv_make gold gate equiv\n\thierarchy -top equiv\n\n\topt -fast\n\tequiv_simple\n\tequiv_induct\n\tequiv_status -assert\n'\n"
  },
  {
    "path": "cores/picorv32/honest.sby",
    "content": "[options]\nmode bmc\naigsmt z3\ndepth 30\n\n[engines]\nabc bmc3\n\n[script]\nverilog_defines -D DEBUGNETS\nverilog_defines -D RISCV_FORMAL\nverilog_defines -D RISCV_FORMAL_NRET=1\nverilog_defines -D RISCV_FORMAL_XLEN=32\nverilog_defines -D RISCV_FORMAL_ILEN=32\nverilog_defines -D RISCV_FORMAL_COMPRESSED\nverilog_defines -D RISCV_FORMAL_ALIGNED_MEM\nread_verilog -sv rvfi_macros.vh\nread_verilog -sv picorv32.v\nread_verilog -sv honest.sv\nprep -nordff -top testbench\n\n[files]\nhonest.sv\n../../../picorv32/picorv32.v\n../../checks/rvfi_macros.vh\n"
  },
  {
    "path": "cores/picorv32/honest.sv",
    "content": "module testbench (\n\tinput clk,\n\n\tinput         mem_ready,\n\toutput        mem_valid,\n\toutput        mem_instr,\n\toutput [31:0] mem_addr,\n\toutput [31:0] mem_wdata,\n\toutput [3:0]  mem_wstrb,\n\tinput  [31:0] mem_rdata,\n\n);\n\t(* anyconst *) reg [31:0] monitor_insn;\n\treg monitor_state = 0;\n\treg [7:0] cycle = 0;\n\n\treg resetn = 0;\n\twire trap;\n\n\talways @(posedge clk) begin\n\t\tresetn <= 1;\n\t\tcycle <= cycle + 1;\n\t\tassume((!mem_valid || mem_ready) || $past(!mem_valid || mem_ready));\n\tend\n\n\t`RVFI_WIRES\n\n\tpicorv32 #(\n\t\t.COMPRESSED_ISA(1),\n\t\t.BARREL_SHIFTER(1)\n\t) uut (\n\t\t.clk            (clk           ),\n\t\t.resetn         (resetn        ),\n\t\t.trap           (trap          ),\n\n\t\t.mem_valid      (mem_valid     ),\n\t\t.mem_instr      (mem_instr     ),\n\t\t.mem_ready      (mem_ready     ),\n\t\t.mem_addr       (mem_addr      ),\n\t\t.mem_wdata      (mem_wdata     ),\n\t\t.mem_wstrb      (mem_wstrb     ),\n\t\t.mem_rdata      (mem_rdata     ),\n\n\t\t`RVFI_CONN\n\t);\n\n\talways @* begin\n\t\tassume (mem_rdata == monitor_insn);\n\t\tif (!monitor_state) assert (cycle < 21);\n\tend\n\n\talways @(posedge clk) begin\n\t\tif (rvfi_valid && monitor_insn[1:0] == 3 && rvfi_insn == monitor_insn)\n\t\t\tmonitor_state <= 1;\n\t\tif (rvfi_valid && monitor_insn[1:0] != 3 && rvfi_insn[15:0] == monitor_insn[15:0])\n\t\t\tmonitor_state <= 1;\n\tend\nendmodule\n"
  },
  {
    "path": "cores/picorv32/imemcheck.sv",
    "content": "module testbench (\n\tinput clk,\n\n\tinput         mem_ready,\n\toutput        mem_valid,\n\toutput        mem_instr,\n\toutput [31:0] mem_addr,\n\toutput [31:0] mem_wdata,\n\toutput [3:0]  mem_wstrb,\n\tinput  [31:0] mem_rdata\n);\n\treg resetn = 0;\n\twire trap;\n\n\talways @(posedge clk)\n\t\tresetn <= 1;\n\n\t`RVFI_WIRES\n\n\twire [31:0] imem_addr;\n\twire [15:0] imem_data;\n\n\trvfi_imem_check checker_inst (\n\t\t.clock     (clk      ),\n\t\t.reset     (!resetn  ),\n\t\t.enable    (1'b1     ),\n\t\t.imem_addr (imem_addr),\n\t\t.imem_data (imem_data),\n\t\t`RVFI_CONN\n\t);\n\n\talways @* begin\n\t\tif (resetn && mem_valid && mem_ready) begin\n\t\t\tif (mem_addr == imem_addr)\n\t\t\t\tassume(mem_rdata[15:0] == imem_data);\n\t\t\tif (mem_addr+2 == imem_addr)\n\t\t\t\tassume(mem_rdata[31:16] == imem_data);\n\t\tend\n\tend\n\n\tpicorv32 #(\n\t\t.REGS_INIT_ZERO(1),\n\t\t.COMPRESSED_ISA(1),\n\t\t.BARREL_SHIFTER(1)\n\t) uut (\n\t\t.clk            (clk           ),\n\t\t.resetn         (resetn        ),\n\t\t.trap           (trap          ),\n\n\t\t.mem_valid      (mem_valid     ),\n\t\t.mem_instr      (mem_instr     ),\n\t\t.mem_ready      (mem_ready     ),\n\t\t.mem_addr       (mem_addr      ),\n\t\t.mem_wdata      (mem_wdata     ),\n\t\t.mem_wstrb      (mem_wstrb     ),\n\t\t.mem_rdata      (mem_rdata     ),\n\n\t\t`RVFI_CONN\n\t);\n\n\treg [4:0] mem_wait = 0;\n\talways @(posedge clk) begin\n\t\tmem_wait <= {mem_wait, mem_valid && !mem_ready};\n\t\t// restrict(~mem_wait && !trap);\n\tend\nendmodule\n\n"
  },
  {
    "path": "cores/picorv32/testbugs.sh",
    "content": "#!/bin/bash\n\nset -ex\n\necho \"all: checks\" > testbugs.mk\necho \"checks::\" >> testbugs.mk\necho \"\t\\$(MAKE) -C checks\" >> testbugs.mk\nif [ ! -d checks ]; then\n\tpython3 ../../checks/genchecks.py\nfi\nfor bug in 001 002 003 004 005; do\n\tsed \"s/PICORV32_TESTBUG_NONE/PICORV32_TESTBUG_${bug}/\" < checks.cfg > testbug${bug}.cfg\n\techo \"checks::\" >> testbugs.mk\n\techo \"\t\\$(MAKE) -C testbug${bug}\" >> testbugs.mk\n\tif [ ! -d testbug${bug} ]; then\n\t\tpython3 ../../checks/genchecks.py testbug${bug}\n\tfi\ndone\n"
  },
  {
    "path": "cores/picorv32/wrapper.sv",
    "content": "module rvfi_wrapper (\n\tinput         clock,\n\tinput         reset,\n\t`RVFI_OUTPUTS\n);\n\t(* keep *) wire trap;\n\n\t(* keep *) `rvformal_rand_reg mem_ready;\n\t(* keep *) `rvformal_rand_reg [31:0] mem_rdata;\n\n\t(* keep *) wire        mem_valid;\n\t(* keep *) wire        mem_instr;\n\t(* keep *) wire [31:0] mem_addr;\n\t(* keep *) wire [31:0] mem_wdata;\n\t(* keep *) wire [3:0]  mem_wstrb;\n\n\tpicorv32 #(\n\t\t.COMPRESSED_ISA(1),\n\t\t.ENABLE_FAST_MUL(1),\n\t\t.ENABLE_DIV(1),\n\t\t.BARREL_SHIFTER(1)\n\t) uut (\n\t\t.clk       (clock    ),\n\t\t.resetn    (!reset   ),\n\t\t.trap      (trap     ),\n\n\t\t.mem_valid (mem_valid),\n\t\t.mem_instr (mem_instr),\n\t\t.mem_ready (mem_ready),\n\t\t.mem_addr  (mem_addr ),\n\t\t.mem_wdata (mem_wdata),\n\t\t.mem_wstrb (mem_wstrb),\n\t\t.mem_rdata (mem_rdata),\n\n\t\t`RVFI_CONN\n\t);\n\n`ifdef PICORV32_FAIRNESS\n\treg [2:0] mem_wait = 0;\n\talways @(posedge clock) begin\n\t\tmem_wait <= {mem_wait, mem_valid && !mem_ready};\n\t\tassume (~mem_wait || trap);\n\tend\n`endif\n\n`ifdef PICORV32_CSR_RESTRICT\n\talways @* begin\n\t\tif (rvfi_valid && rvfi_insn[6:0] == 7'b1110011) begin\n\t\t\tif (rvfi_insn[14:12] == 3'b010) begin\n\t\t\t\tassume (rvfi_insn[31:20] == 12'hC00 || rvfi_insn[31:20] == 12'hC01 || rvfi_insn[31:20] == 12'hC02 ||\n\t\t\t\t\t\trvfi_insn[31:20] == 12'hC80 || rvfi_insn[31:20] == 12'hC81 || rvfi_insn[31:20] == 12'hC82);\n\t\t\t\tassume (rvfi_insn[19:15] == 0);\n\t\t\tend\n\t\t\tassume (rvfi_insn[14:12] != 3'b001);\n\t\t\tassume (rvfi_insn[14:12] != 3'b011);\n\t\t\tassume (rvfi_insn[14:12] != 3'b101);\n\t\t\tassume (rvfi_insn[14:12] != 3'b110);\n\t\t\tassume (rvfi_insn[14:12] != 3'b111);\n\t\tend\n\tend\n`endif\nendmodule\n\n"
  },
  {
    "path": "cores/rocket/.gitignore",
    "content": "/riscv-tools\n/riscv-tools-build\n/rocket-chip\n/rocket-syn\n/cover\n/coverage\n/checks\n/checks.cfg\n/testbench\n/testbench.v\n/testbench.vcd\n/obj_dir\n/disasm.s\n/disasm.o\n/cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9]\n/cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9].zip\n/muldivlen_cover\n/muldivlen_check\n"
  },
  {
    "path": "cores/rocket/README.md",
    "content": "\nriscv-formal proofs for rocket-chip\n===================================\n\nQuickstart guide:\n\nFirst install Yosys, SymbiYosys, and the solvers. See\n[here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing)\nfor instructions. Then build the version of rocket-chip with RVFI support and\nrsicv-tools, and generate the formal checks:\n\n```\nsudo apt-get install autoconf automake autotools-dev curl \\\n\t\tdevice-tree-compiler libmpc-dev libmpfr-dev \\\n\t\tlibgmp-dev gawk build-essential bison flex \\\n\t\ttexinfo gperf libtool patchutils bc zlib1g-dev \\\n\t\tlibusb-1.0-0-dev openjdk-8-jdk-headless\nbash generate.sh\n```\n\nThen run the formal checks:\n\n```\nmake -C checks -j$(nproc)\n```\n\nOr if you just want to simulate Rocket with RVFIMonitor:\n\n```\nexport CONFIG=DefaultConfigWithRVFIMonitors\nexport RISCV=$PWD/riscv-tools\ncd rocket-chip/emulator\nmake -j$(nproc)\nmake run\n```\n\nImportant Notes\n===============\n\nThis check sets all dangling wires in the design to constant zero. Without this\nthere would be a problem with propagating Xs and the checks would fail. Obviously\nthis is a problem that needs to be addressed in the design, but for now we work\naround it here so we can continue writing checks.\n\n"
  },
  {
    "path": "cores/rocket/cexdata.sh",
    "content": "#!/bin/bash\n\nset -ex\ncexdata=\"cexdata-$(date '+%Y%m%d')\"\n\nrm -rf $cexdata\nmkdir $cexdata\n\nwhile read dir; do echo \"$dir\t$(git -C $dir log -n1 --oneline)\"; \\\n\tdone < <( echo .; find rocket-chip -name '.git' -printf '%h\\n'; ) | \\\n\texpand -t30 > $cexdata/version.txt\n\ncp rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v $cexdata/rocketchip.v\ncp rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.fir $cexdata/rocketchip.fir\ngzip $cexdata/rocketchip.v $cexdata/rocketchip.fir\n\ncp rocket-chip/src/main/scala/system/Configs.scala $cexdata/Configs.scala\ngit -C rocket-chip diff src/main/scala/system/Configs.scala > $cexdata/Configs.scala.diff\n\nvcd2fst rocket-syn/init.vcd $cexdata/init.fst\n\nfor x in checks/*/{FAIL,ERROR} coverage/{FAIL,ERROR}; do\n\ttest -f $x || continue\n\tx=${x%/FAIL}\n\tx=${x%/ERROR}\n\ty=${x#checks/}\n\tcp $x/logfile.txt $cexdata/$y.log\n\tif test -f $x/engine_*/trace.vcd; then\n\t\tcp $x/engine_*/trace.vcd $cexdata/$y.vcd\n\t\tif grep -q \"^isa rv64\" checks.cfg; then\n\t\t\tpython3 disasm.py --64 $cexdata/$y.vcd > $cexdata/$y.asm\n\t\tfi\n\t\tif grep -q \"^isa rv32\" checks.cfg; then\n\t\t\tpython3 disasm.py $cexdata/$y.vcd > $cexdata/$y.asm\n\t\tfi\n\t\tvcd2fst $cexdata/$y.vcd $cexdata/$y.fst\n\t\trm -f $cexdata/$y.vcd\n\tfi\ndone\n\nfor x in checks/*.sby; do\n\tx=${x%.sby}\n\tx=${x#checks/}\n\tif [ -f checks/$x/PASS ]; then\n\t\tprintf \"%-20s %s %10s\\n\" $x pass  $(sed '/Elapsed process time/ { s/.*\\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt)\n\telif [ -f checks/$x/FAIL ]; then\n\t\tprintf \"%-20s %s %10s\\n\" $x FAIL  $(sed '/Elapsed process time/ { s/.*\\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt)\n\telif [ -f checks/$x/ERROR ]; then\n\t\tprintf \"%-20s %s\\n\" $x ERROR\n\telse\n\t\tprintf \"%-20s %s\\n\" $x unknown\n\tfi\ndone | awk '{ print gensub(\":\", \"\", \"g\", $3), $0; }' | sort -n | cut -f2- -d' ' > $cexdata/status.txt\n\nrm -f $cexdata.zip\nzip -r $cexdata.zip $cexdata/\n\n"
  },
  {
    "path": "cores/rocket/checks.gtkw",
    "content": "[*]\n[*] GTKWave Analyzer v3.3.65 (w)1999-2015 BSI\n[*] Tue Sep 12 08:17:07 2017\n[*]\n[dumpfile] \"/home/claire/Work/riscv-formal/cores/rocket/checks/pc_fwd_ch0/engine_0/trace.vcd\"\n[dumpfile_mtime] \"Tue Sep 12 00:05:15 2017\"\n[dumpfile_size] 4236356\n[savefile] \"/home/claire/Work/riscv-formal/cores/rocket/checks.gtkw\"\n[timestart] 218\n[size] 1024 1256\n[pos] 999 -429\n*-6.374269 285 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1\n[treeopen] rvfi_testbench.\n[treeopen] rvfi_testbench.wrapper.\n[sst_width] 225\n[signals_width] 269\n[sst_expanded] 1\n[sst_vpaned_height] 391\n@24\nsmt_step\n@28\nrvfi_testbench.checker_inst.reset\nrvfi_testbench.checker_inst.check\n@200\n-\n@22\nrvfi_testbench.checker_inst.insn_order[63:0]\nrvfi_testbench.checker_inst.expect_pc[31:0]\n@29\nrvfi_testbench.checker_inst.expect_pc_valid\n@200\n-\n-RVFI #0\n@28\nrvfi_testbench.wrapper.rvfi_channel_0.valid\nrvfi_testbench.wrapper.rvfi_channel_0.trap\nrvfi_testbench.wrapper.rvfi_channel_0.intr\n@24\nrvfi_testbench.wrapper.rvfi_channel_0.order[63:0]\n@22\nrvfi_testbench.wrapper.rvfi_channel_0.insn[31:0]\nrvfi_testbench.wrapper.rvfi_channel_0.pc_rdata[31:0]\nrvfi_testbench.wrapper.rvfi_channel_0.pc_wdata[31:0]\n@200\n-\n-RVFI #1\n@28\nrvfi_testbench.wrapper.rvfi_channel_1.valid\nrvfi_testbench.wrapper.rvfi_channel_1.trap\nrvfi_testbench.wrapper.rvfi_channel_1.intr\n@24\nrvfi_testbench.wrapper.rvfi_channel_1.order[63:0]\n@22\nrvfi_testbench.wrapper.rvfi_channel_1.insn[31:0]\nrvfi_testbench.wrapper.rvfi_channel_1.pc_rdata[31:0]\nrvfi_testbench.wrapper.rvfi_channel_1.pc_wdata[31:0]\n[pattern_trace] 1\n[pattern_trace] 0\n"
  },
  {
    "path": "cores/rocket/cover.gtkw",
    "content": "[*]\n[*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI\n[*] Wed Mar 28 21:36:23 2018\n[*]\n[dumpfile] \"/home/claire/Work/riscv-formal/cores/rocket/cover/engine_0/trace8.vcd\"\n[dumpfile_mtime] \"Wed Mar 28 21:28:42 2018\"\n[dumpfile_size] 3363780\n[savefile] \"/home/claire/Work/riscv-formal/cores/rocket/cover.gtkw\"\n[timestart] 0\n[size] 1400 947\n[pos] 471 0\n*-6.307628 100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1\n[treeopen] testbench.\n[treeopen] testbench.uut.\n[sst_width] 225\n[signals_width] 362\n[sst_expanded] 1\n[sst_vpaned_height] 277\n@28\ntestbench.clk\n@200\n-\n@28\ntestbench.rvfi_valid_ch0\n@22\ntestbench.rvfi_insn_ch0[31:0]\ntestbench.rvfi_pc_rdata_ch0[63:0]\ntestbench.rvfi_mem_addr_ch0[63:0]\n@200\n-\n@28\ntestbench.rvfi_valid_ch1\n@22\ntestbench.rvfi_insn_ch1[31:0]\ntestbench.rvfi_pc_rdata_ch1[63:0]\ntestbench.rvfi_mem_addr_ch1[63:0]\n@200\n-\n@29\ntestbench.p0o0\n@28\ntestbench.p0o1\ntestbench.p0o2\ntestbench.p0o3m0\ntestbench.p0o3m1\ntestbench.p0o4m0\ntestbench.p0o4m1\ntestbench.p1o0\ntestbench.p1o1\ntestbench.p1o2\ntestbench.p1o3m0\ntestbench.p1o3m1\ntestbench.p1o4m0\ntestbench.p1o4m1\n@200\n-\n@28\ntestbench.uut.tilelink_slave.channel_a_valid\ntestbench.uut.tilelink_slave.channel_a_ready\n@22\ntestbench.uut.tilelink_slave.channel_a_bits_size[3:0]\ntestbench.uut.tilelink_slave.channel_a_bits_address[31:0]\n@200\n-\n@28\ntestbench.uut.tilelink_slave.channel_d_valid\ntestbench.uut.tilelink_slave.channel_d_ready\n@22\ntestbench.uut.tilelink_slave.channel_d_bits_data[63:0]\n[pattern_trace] 1\n[pattern_trace] 0\n"
  },
  {
    "path": "cores/rocket/cover.sby",
    "content": "[options]\nmode cover\ntbtop uut.rocket\ndepth 55\n\n[engines]\nsmtbmc boolector\n\n[script]\nverilog_defines -D RISCV_FORMAL\nverilog_defines -D RISCV_FORMAL_NRET=2\nverilog_defines -D RISCV_FORMAL_XLEN=64\nverilog_defines -D RISCV_FORMAL_ILEN=32\nverilog_defines -D RISCV_FORMAL_COMPRESSED\nverilog_defines -D RISCV_FORMAL_FAIRNESS\nverilog_defines -D RISCV_FORMAL_CSR_MCYCLE\nverilog_defines -D RISCV_FORMAL_CSR_MISA\nverilog_defines -D ROCKET_NORESET\nread_verilog -sv rvfi_macros.vh\nread_verilog -sv rvfi_channel.sv\nread_verilog -sv wrapper.sv\nread_verilog -sv cover.sv\nread_ilang rocket-hier.il\nprep -flatten -top testbench\n\n[files]\ncover.sv\nwrapper.sv\nrocket-syn/rocket-hier.il\n../../checks/rvfi_macros.vh\n../../checks/rvfi_channel.sv\n"
  },
  {
    "path": "cores/rocket/cover.sv",
    "content": "module testbench (\n\tinput clk, reset\n);\n\t`RVFI_WIRES\n\n\t`RVFI_CHANNEL(rvfi_ch0, 0)\n\t`RVFI_CHANNEL(rvfi_ch1, 1)\n\n`ifdef YOSYS\n\tassume property (reset == $initstate);\n`endif\n\n\trvfi_wrapper uut (\n\t\t.clock (clk  ),\n\t\t.reset (reset),\n\t\t`RVFI_CONN\n\t);\n\n\tlocalparam [31:0] opcode0 = 32'h00051663; // bnez a0,18 <foo+0xc>\n\tlocalparam [31:0] opcode1 = 32'h00310093; // addi ra,sp,3\n\tlocalparam [31:0] opcode2 = 32'h005201b3; // add  gp,tp,t0\n\tlocalparam [31:0] opcode3 = 32'h0003a303; // lw   t1,0(t2)\n\tlocalparam [31:0] opcode4 = 32'h0084a023; // sw   s0,0(s1)\n\n\treg p0o0 = 0, p1o0 = 0;\n\treg p0o1 = 0, p1o1 = 0;\n\treg p0o2 = 0, p1o2 = 0;\n\treg p0o3m0 = 0, p0o3m1 = 0, p1o3m0 = 0, p1o3m1 = 0;\n\treg p0o4m0 = 0, p0o4m1 = 0, p1o4m0 = 0, p1o4m1 = 0;\n\n\twire [3:0] icount_p0 = p0o0 + p1o0 + p0o1;\n\twire [3:0] icount_p1 = p1o1 + p0o2 + p1o2;\n\twire [3:0] mcount_p0 = p0o3m0 + p0o3m1 + p0o4m0 + p0o4m1;\n\twire [3:0] mcount_p1 = p1o3m0 + p1o3m1 + p1o4m0 + p1o4m1;\n\twire [3:0] tcount = |icount_p0 + |icount_p1 + |mcount_p0 + |mcount_p1;\n\n\twire o0 = p0o0 || p1o0;\n\twire o1 = p0o1 || p1o1;\n\twire o2 = p0o2 || p1o2;\n\twire o3 = p0o3m0 || p0o3m1 || p1o3m0 || p1o3m1;\n\twire o4 = p0o4m0 || p0o4m1 || p1o4m0 || p1o4m1;\n\n\twire is_p0_ch0 = (rvfi_ch0.pc_rdata & 32'hffff0000) == 32'h00010000;\n\twire is_p1_ch0 = (rvfi_ch0.pc_rdata & 32'hffff0000) == 32'h00020000;\n\n\twire is_m0_ch0 = (rvfi_ch0.mem_addr & 32'hffff0000) == 32'h00010000;\n\twire is_m1_ch0 = (rvfi_ch0.mem_addr & 32'hffff0000) == 32'h00020000;\n\n\twire is_p0_ch1 = (rvfi_ch1.pc_rdata & 32'hffff0000) == 32'h00010000;\n\twire is_p1_ch1 = (rvfi_ch1.pc_rdata & 32'hffff0000) == 32'h00020000;\n\n\twire is_m0_ch1 = (rvfi_ch1.mem_addr & 32'hffff0000) == 32'h00010000;\n\twire is_m1_ch1 = (rvfi_ch1.mem_addr & 32'hffff0000) == 32'h00020000;\n\n\talways @(posedge clk) begin\n\t\tif (!reset) begin\n\t\t\tif (rvfi_ch0.valid) begin\n\t\t\t\tif (rvfi_ch0.insn == opcode0) begin\n\t\t\t\t\tif (is_p0_ch0) p0o0 <= 1;\n\t\t\t\t\tif (is_p1_ch0) p1o0 <= 1;\n\t\t\t\tend\n\t\t\t\tif (rvfi_ch0.insn == opcode1) begin\n\t\t\t\t\tif (is_p0_ch0) p0o1 <= 1;\n\t\t\t\t\tif (is_p1_ch0) p1o1 <= 1;\n\t\t\t\tend\n\t\t\t\tif (rvfi_ch0.insn == opcode2) begin\n\t\t\t\t\tif (is_p0_ch0) p0o2 <= 1;\n\t\t\t\t\tif (is_p1_ch0) p1o2 <= 1;\n\t\t\t\tend\n\t\t\t\tif (rvfi_ch0.insn == opcode3) begin\n\t\t\t\t\tif (is_p0_ch0 && is_m0_ch0) p0o3m0 <= 1;\n\t\t\t\t\tif (is_p0_ch0 && is_m1_ch0) p0o3m1 <= 1;\n\t\t\t\t\tif (is_p1_ch0 && is_m0_ch0) p1o3m0 <= 1;\n\t\t\t\t\tif (is_p1_ch0 && is_m1_ch0) p1o3m1 <= 1;\n\t\t\t\tend\n\t\t\t\tif (rvfi_ch0.insn == opcode4) begin\n\t\t\t\t\tif (is_p0_ch0 && is_m0_ch0) p0o4m0 <= 1;\n\t\t\t\t\tif (is_p0_ch0 && is_m1_ch0) p0o4m1 <= 1;\n\t\t\t\t\tif (is_p1_ch0 && is_m0_ch0) p1o4m0 <= 1;\n\t\t\t\t\tif (is_p1_ch0 && is_m1_ch0) p1o4m1 <= 1;\n\t\t\t\tend\n\t\t\tend\n\t\t\tif (rvfi_ch1.valid) begin\n\t\t\t\tif (rvfi_ch1.insn == opcode0) begin\n\t\t\t\t\tif (is_p0_ch1) p0o0 <= 1;\n\t\t\t\t\tif (is_p1_ch1) p1o0 <= 1;\n\t\t\t\tend\n\t\t\t\tif (rvfi_ch1.insn == opcode1) begin\n\t\t\t\t\tif (is_p0_ch1) p0o1 <= 1;\n\t\t\t\t\tif (is_p1_ch1) p1o1 <= 1;\n\t\t\t\tend\n\t\t\t\tif (rvfi_ch1.insn == opcode2) begin\n\t\t\t\t\tif (is_p0_ch1) p0o2 <= 1;\n\t\t\t\t\tif (is_p1_ch1) p1o2 <= 1;\n\t\t\t\tend\n\t\t\t\tif (rvfi_ch1.insn == opcode3) begin\n\t\t\t\t\tif (is_p0_ch1 && is_m0_ch1) p0o3m0 <= 1;\n\t\t\t\t\tif (is_p0_ch1 && is_m1_ch1) p0o3m1 <= 1;\n\t\t\t\t\tif (is_p1_ch1 && is_m0_ch1) p1o3m0 <= 1;\n\t\t\t\t\tif (is_p1_ch1 && is_m1_ch1) p1o3m1 <= 1;\n\t\t\t\tend\n\t\t\t\tif (rvfi_ch1.insn == opcode4) begin\n\t\t\t\t\tif (is_p0_ch1 && is_m0_ch1) p0o4m0 <= 1;\n\t\t\t\t\tif (is_p0_ch1 && is_m1_ch1) p0o4m1 <= 1;\n\t\t\t\t\tif (is_p1_ch1 && is_m0_ch1) p1o4m0 <= 1;\n\t\t\t\t\tif (is_p1_ch1 && is_m1_ch1) p1o4m1 <= 1;\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\n\n\talways @* begin\n\t\tcover (icount_p0 == 1);\n\t\tcover (icount_p0 == 2);\n\t\tcover (icount_p0 == 3);\n\n\t\tcover (icount_p1 == 1);\n\t\tcover (icount_p1 == 2);\n\t\tcover (icount_p1 == 3);\n\n\t\tcover (mcount_p0 == 1);\n\t\tcover (mcount_p0 == 2);\n\t\tcover (mcount_p0 == 3);\n\t\tcover (mcount_p0 == 4);\n\n\t\tcover (mcount_p1 == 1);\n\t\tcover (mcount_p1 == 2);\n\t\tcover (mcount_p1 == 3);\n\t\tcover (mcount_p1 == 4);\n\n\t\tcover (tcount == 2);\n\t\tcover (tcount == 3);\n\t\tcover (tcount == 4);\n\tend\nendmodule\n"
  },
  {
    "path": "cores/rocket/coverage.sby",
    "content": "[options]\nmode bmc\ntbtop uut.rocket\ndepth 20\nappend 2\n\n[engines]\nsmtbmc boolector\n\n[script]\nverilog_defines -D RISCV_FORMAL\nverilog_defines -D RISCV_FORMAL_NRET=2\nverilog_defines -D RISCV_FORMAL_XLEN=64\nverilog_defines -D RISCV_FORMAL_ILEN=32\nverilog_defines -D RISCV_FORMAL_COMPRESSED\nverilog_defines -D RISCV_FORMAL_FAIRNESS\nverilog_defines -D RISCV_FORMAL_CSR_MCYCLE\nverilog_defines -D ROCKET_NORESET\nread_verilog -sv rvfi_macros.vh\nread_verilog -sv rvfi_channel.sv\nread_verilog -sv riscv_rv64ic_insn.v\nread_verilog -sv wrapper.sv\nread_verilog -sv coverage.sv\nread_ilang rocket-hier.il\nprep -flatten -top testbench\n\n[files]\ncoverage.sv\nwrapper.sv\nrocket-syn/rocket-hier.il\n../../checks/rvfi_macros.vh\n../../checks/rvfi_channel.sv\n../../tests/coverage/riscv_rv64ic_insn.v\n"
  },
  {
    "path": "cores/rocket/coverage.sv",
    "content": "module testbench (\n\tinput clk, reset\n);\n\t`RVFI_WIRES\n\n\t`RVFI_CHANNEL(rvfi_ch0, 0)\n\t`RVFI_CHANNEL(rvfi_ch1, 1)\n\n`ifdef YOSYS\n\tassume property (reset == $initstate);\n`endif\n\n\trvfi_wrapper uut (\n\t\t.clock (clk  ),\n\t\t.reset (reset),\n\t\t`RVFI_CONN\n\t);\n\n\twire valid_ch0;\n\twire valid_ch1;\n\n\triscv_rv64ic_insn riscv_rv64ic_insn_ch0 (\n\t\t.insn(rvfi_insn_ch0),\n\t\t.valid(valid_ch0)\n\t);\n\n\triscv_rv64ic_insn riscv_rv64ic_insn_ch1 (\n\t\t.insn(rvfi_insn_ch1),\n\t\t.valid(valid_ch1)\n\t);\n\n\tfunction [0:0] check_insn;\n\t\tinput [31:0] insn;\n\t\tbegin\n\t\t\tcheck_insn = 0;\n\t\t\tcasez (insn)\n\t\t\t\t32'b 0000000000000000_010_?00000?????_10:; // C.LWSP (fix pending)\n\t\t\t\t32'b 0000000000000000_011_?00000?????_10:; // C.LDSP (fix pending)\n\t\t\t\t32'b ???????_?????_?????_???_?????_1110011:; // SYSTEM\n\t\t\t\t32'b ???????_?????_?????_000_?????_0001111:; // FENCE\n\t\t\t\t32'b ???????_?????_?????_001_?????_0001111:; // FENCE.I\n\t\t\t\t32'b 00010??_00000_?????_???_?????_0101111:; // LR.W\n\t\t\t\t32'b 00011??_?????_?????_???_?????_0101111:; // SC.W\n\t\t\t\t32'b 00001??_?????_?????_???_?????_0101111:; // AMOSWAP.W\n\t\t\t\t32'b 00000??_?????_?????_???_?????_0101111:; // AMOADD.W\n\t\t\t\t32'b 00100??_?????_?????_???_?????_0101111:; // AMOXOR.W\n\t\t\t\t32'b 01100??_?????_?????_???_?????_0101111:; // AMOAND.W\n\t\t\t\t32'b 01000??_?????_?????_???_?????_0101111:; // AMOOR.W\n\t\t\t\t32'b 10000??_?????_?????_???_?????_0101111:; // AMOMIN.W\n\t\t\t\t32'b 10100??_?????_?????_???_?????_0101111:; // AMOMAX.W\n\t\t\t\t32'b 11000??_?????_?????_???_?????_0101111:; // AMOMINU.W\n\t\t\t\t32'b 11100??_?????_?????_???_?????_0101111:; // AMOMAXU.W\n\t\t\t\tdefault: check_insn = 1;\n\t\t\tendcase\n\t\tend\n\tendfunction\n\n\twire check_insn_ch0 = check_insn(rvfi_insn_ch0);\n\twire check_insn_ch1 = check_insn(rvfi_insn_ch1);\n\n\talways @* begin\n\t\tif (!reset && rvfi_valid_ch0 && check_insn_ch0 && !rvfi_trap_ch0) begin\n\t\t\tassert (valid_ch0);\n\t\tend\n\t\tif (!reset && rvfi_valid_ch1 && check_insn_ch1 && !rvfi_trap_ch1) begin\n\t\t\tassert (valid_ch1);\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "cores/rocket/decode.sh",
    "content": "#!/bin/bash\nriscv=riscv32\ncase \"$1\" in\n\t-a) mopt=\"-M numeric\"; shift;;\n\t-n) mopt=\"-M no-aliases\"; shift;;\n\t-an) mopt=\"\"; shift;;\n\t-64) riscv=riscv64; shift;;\n\t*) mopt=\"-M numeric,no-aliases\"\nesac\nfor w; do echo \".word 0x${w#0x}\"; done > decode.s\n${riscv}-unknown-elf-gcc -c decode.s\n${riscv}-unknown-elf-objdump -d $mopt decode.o | grep -A999 ^000\nrm -f decode.s decode.o\n"
  },
  {
    "path": "cores/rocket/disasm.py",
    "content": "#!/usr/bin/env python3\n\nfrom Verilog_VCD.Verilog_VCD import parse_vcd\nfrom os import system\nfrom sys import argv, exit\nfrom getopt import getopt\n\nmode_d = False\nmode_64 = False\n\ndef usage():\n    print(\"Usage: %s [-d] [--64] <vcd-file>\" % argv[0])\n    exit(1)\n\ntry:\n    opts, args = getopt(argv[1:], \"d\", [\"64\"])\nexcept:\n    usage()\n\nfor o, a in opts:\n    if o == \"-d\":\n        mode_d = True\n    elif o == \"--64\":\n        mode_64 = True\n    else:\n        usage()\n\nif len(args) != 1:\n    usage()\n\nif mode_d:\n    tilelink_d_valid = None\n    tilelink_d_ready = None\n    tilelink_d_data = None\n\n    for netinfo in parse_vcd(args[0]).values():\n        for net in netinfo['nets']:\n            print(net[\"hier\"], net[\"name\"])\n            if net[\"hier\"] in [\"rvfi_testbench.wrapper\", \"testbench.uut\"] and net[\"name\"] == \"io_master_0_d_valid\":\n                tilelink_d_valid = netinfo['tv']\n            if net[\"hier\"] in [\"rvfi_testbench.wrapper\", \"testbench.uut\"] and net[\"name\"] == \"io_master_0_d_ready\":\n                tilelink_d_ready = netinfo['tv']\n            if net[\"hier\"] in [\"rvfi_testbench.wrapper\", \"testbench.uut\"] and net[\"name\"] == \"io_master_0_d_bits_data\":\n                tilelink_d_data = netinfo['tv']\n\n    assert len(tilelink_d_valid) == len(tilelink_d_ready)\n    assert len(tilelink_d_valid) == len(tilelink_d_data)\n\n    with open(\"disasm.s\", \"w\") as f:\n        for tv_valid, tv_ready, tv_data in zip(tilelink_d_valid, tilelink_d_ready, tilelink_d_data):\n            if int(tv_valid[1], 2) and int(tv_ready[1], 2):\n                print(\".word 0x%04x\" % int(tv_data[1], 2), file=f)\nelse:\n    rvfi_valid_0 = None\n    rvfi_valid_1 = None\n    rvfi_order_0 = None\n    rvfi_order_1 = None\n    rvfi_insn_0 = None\n    rvfi_insn_1 = None\n\n    for netinfo in parse_vcd(args[0]).values():\n        for net in netinfo['nets']:\n            # print(net[\"hier\"], net[\"name\"])\n            if net[\"hier\"] in [\"rvfi_testbench.wrapper.rvfi_channel_0\", \"testbench.uut.rvfi_channel_0\"] and net[\"name\"] == \"valid\":\n                rvfi_valid_0 = netinfo['tv']\n            if net[\"hier\"] in [\"rvfi_testbench.wrapper.rvfi_channel_0\", \"testbench.uut.rvfi_channel_0\"] and net[\"name\"] == \"order\":\n                rvfi_order_0 = netinfo['tv']\n            if net[\"hier\"] in [\"rvfi_testbench.wrapper.rvfi_channel_0\", \"testbench.uut.rvfi_channel_0\"] and net[\"name\"] == \"insn\":\n                rvfi_insn_0 = netinfo['tv']\n            if net[\"hier\"] in [\"rvfi_testbench.wrapper.rvfi_channel_1\", \"testbench.uut.rvfi_channel_1\"] and net[\"name\"] == \"valid\":\n                rvfi_valid_1 = netinfo['tv']\n            if net[\"hier\"] in [\"rvfi_testbench.wrapper.rvfi_channel_1\", \"testbench.uut.rvfi_channel_1\"] and net[\"name\"] == \"order\":\n                rvfi_order_1 = netinfo['tv']\n            if net[\"hier\"] in [\"rvfi_testbench.wrapper.rvfi_channel_1\", \"testbench.uut.rvfi_channel_1\"] and net[\"name\"] == \"insn\":\n                rvfi_insn_1 = netinfo['tv']\n\n    assert len(rvfi_valid_0) == len(rvfi_order_0)\n    assert len(rvfi_valid_1) == len(rvfi_order_1)\n\n    assert len(rvfi_valid_0) == len(rvfi_insn_0)\n    assert len(rvfi_valid_1) == len(rvfi_insn_1)\n\n    prog = list()\n\n    for tv_valid, tv_order, tv_insn in zip(rvfi_valid_0, rvfi_order_0, rvfi_insn_0):\n        if tv_valid[1] == '1':\n            prog.append((int(tv_order[1], 2), int(tv_insn[1], 2)))\n\n    for tv_valid, tv_order, tv_insn in zip(rvfi_valid_1, rvfi_order_1, rvfi_insn_1):\n        if tv_valid[1] == '1':\n            prog.append((int(tv_order[1], 2), int(tv_insn[1], 2)))\n\n    with open(\"disasm.s\", \"w\") as f:\n        for tv_order, tv_insn in sorted(prog):\n            if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0:\n                print(\".hword 0x%04x # %d\" % (tv_insn, tv_order), file=f)\n            else:\n                print(\".word 0x%08x # %d\" % (tv_insn, tv_order), file=f)\n\nif mode_64:\n    system(\"riscv-tools/bin/riscv64-unknown-elf-gcc -c disasm.s\")\n    system(\"riscv-tools/bin/riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o\")\nelse:\n    system(\"riscv-tools/bin/riscv32-unknown-elf-gcc -c disasm.s\")\n    system(\"riscv-tools/bin/riscv32-unknown-elf-objdump -d -M numeric,no-aliases disasm.o\")\n\n"
  },
  {
    "path": "cores/rocket/generate.sh",
    "content": "#!/bin/sh\n\nset -ex\n\nexport CONFIG=DefaultConfigWithRVFIMonitors\nexport MAKEFLAGS=\"-j$(nproc)\"\nexport RISCV=$PWD/riscv-tools\n\nenable_compressed=true\nenable_inithack=true\nenable_64bits=true\nenable_muldiv=true\nenable_misa=true\nenable_pmp=false\n\nif [ ! -d rocket-chip ]; then\n\tgit clone --recurse-submodules git@github.com:sifive/rocket-chip-grand-central.git rocket-chip\n\tcd rocket-chip\n\n\t# git checkout bc22847\n\t# git submodule update --recursive\n\n\tif $enable_compressed; then\n\t\t( cd ../../../monitor && python3 generate.py -i rv$(if $enable_64bits; then echo 64; else echo 32; fi)ic -p RVFIMonitor -c 2; ) > src/main/resources/vsrc/RVFIMonitor.v\n\telse\n\t\tsed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /new WithRVFIMonitors/ s/$/\\n  new WithoutCompressed ++/; };' src/main/scala/system/Configs.scala\n\t\t( cd ../../../monitor && python3 generate.py -i rv$(if $enable_64bits; then echo 64; else echo 32; fi)i -p RVFIMonitor -c 2; ) > src/main/resources/vsrc/RVFIMonitor.v\n\tfi\n\n\tif $enable_misa; then\n\t\tsed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /new WithoutMISAWrite/ d; };' src/main/scala/system/Configs.scala\n\tfi\n\n\tif $enable_muldiv; then\n\t\tsed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /new WithoutMulDiv/ d; };' src/main/scala/system/Configs.scala\n\tfi\n\n\tif $enable_64bits; then\n\t\tsed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /freechips.rocketchip.tile.XLen/ s,32,64,; }' src/main/scala/system/Configs.scala\n\telse\n\t\tsed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /freechips.rocketchip.tile.XLen/ s,64,32,; }' src/main/scala/system/Configs.scala\n\tfi\n\n\tif ! $enable_pmp; then\n\t\tsed -i -e '/DefaultConfigWithRVFIMonitors/,/^)/ { /new WithNPMP/ s/[0-9]\\+/0/; };' src/main/scala/system/Configs.scala\n\tfi\n\n\tsed -i 's/--top-module/-Wno-fatal &/' emulator/Makefrag-verilator\n\n\tcd ..\nfi\n\nif [ ! -d riscv-tools ]; then\n\tmkdir riscv-tools\n\trm -rf riscv-tools-build\n\tgit clone https://github.com/riscv/riscv-tools riscv-tools-build\n\tcd riscv-tools-build\n\tgit checkout $(cat ../rocket-chip/riscv-tools.hash)\n\tgit submodule update --init --recursive\n\t# sed -i 's/rv32ima/rv32i/g' build-rv32ima.sh\n\t./build.sh\n\t./build-rv32ima.sh\n\tcd ..\nfi\n\nmake -C rocket-chip/vsim verilog\n\nrm -rf rocket-syn\nmkdir -p rocket-syn\n\ncat > rocket-syn/rocket-syn.ys << EOT\nverific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v\nverific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.behav_srams.v\nverific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors/plusarg_reader.v\nverific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors/AsyncResetReg.v\nverific -sv rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors/SimDTM.v\n\nverific -vlog-define RISCV_FORMAL\nverific -vlog-define RISCV_FORMAL_NRET=2\nverific -vlog-define RISCV_FORMAL_XLEN=$(if $enable_64bits; then echo 64; else echo 32; fi)\nverific -vlog-define RISCV_FORMAL_ILEN=32\nverific -vlog-define RISCV_FORMAL_UMODE\nverific -vlog-define RISCV_FORMAL_EXTAMO\nverific -vlog-define RISCV_FORMAL_CSR_MCYCLE\nverific -vlog-define RISCV_FORMAL_CSR_MINSTRET\nverific -vlog-define RISCV_FORMAL_CSR_MISA\n\nverific -vlog-define ROCKET_INIT\n$(if $enable_inithack; then echo \"verific -vlog-define ROCKET_INITHACK\"; fi)\n\nverific -sv ../../checks/rvfi_macros.vh ../../checks/rvfi_channel.sv wrapper.sv rocketrvfi.sv\nverific -import -extnets rvfi_wrapper\n\n# ---- Simulate init sequence ----\n\nhierarchy -top rvfi_wrapper\nprep -nordff\nuniquify\nhierarchy\n\nsetundef -undriven -zero w:*\nopt -fast\n\nwrite_ilang rocket-syn/init.il\nsim -clock clock -reset reset -rstlen 10 -zinit -w -vcd rocket-syn/init.vcd -n 300\n\n# ---- Generate netlists ----\n\nrename rvfi_wrapper.rocket_rvfi_tile RocketTileWithRVFI\nhierarchy -top RocketTileWithRVFI\nuniquify\nchtype -set MulDiv RocketTileWithRVFI.rocket_tile.core/div\nhierarchy\n\n# rename -hide w:_*\n\n$(if ! $enable_inithack; then echo \"# \"; fi)setparam -set INIT 16384'bx RocketTileWithRVFI.rocket_tile.frontend.icache.data_arrays_*/ram\nwrite_ilang rocket-syn/rocket-hier.il\nEOT\n\nyosys -v2 -l rocket-syn/rocket-syn.log rocket-syn/rocket-syn.ys\n\ncat > checks.cfg <<EOT\n[options]\nisa rv$(if $enable_64bits; then echo  64; else echo  32; fi)i$(if $enable_muldiv; then echo m; fi)$(if $enable_compressed; then echo c; fi)\nnret 2\nsolver boolector\ndumpsmt2\n\n[depth]\ninsn    $(if $enable_inithack; then echo \"      20\"; else echo \"      35\"; fi)\nill     $(if $enable_inithack; then echo \"      20\"; else echo \"      35\"; fi)\nreg     $(if $enable_inithack; then echo \" 5    15\"; else echo \"20    30\"; fi)\npc_fwd  $(if $enable_inithack; then echo \" 5    15\"; else echo \"20    30\"; fi)\npc_bwd  $(if $enable_inithack; then echo \" 5    15\"; else echo \"20    30\"; fi)\nunique  $(if $enable_inithack; then echo \"10 15 20\"; else echo \"25 30 35\"; fi)\ncausal  $(if $enable_inithack; then echo \" 5    15\"; else echo \"20    30\"; fi)\nhang    $(if $enable_inithack; then echo \"10    40\"; else echo \"20    50\"; fi)\n\nreg_ch1 $(if $enable_inithack; then echo \" 5    15\"; else echo \"20    30\"; fi)\n\ncsrw    $(if $enable_inithack; then echo \"      20\"; else echo \"      35\"; fi)\n\n[csrs]\nmcycle\nminstret\nmisa\n\n[sort]\nhang\n(reg|causal)_ch?\ninsn_.*_ch1\n\n[defines]\n\\`define ROCKET_NORESET\n\\`define RISCV_FORMAL_VALIDADDR(addr) ({31{addr[32]}} == addr[63:33])\n\\`define RISCV_FORMAL_WAITINSN(insn) ((insn) == 32'b_0011000_00101_00000_000_00000_1110011)\n\\`define RISCV_FORMAL_PMA_MAP rocket_pma_map\n\\`define RISCV_FORMAL_EXTAMO\n\\`define RISCV_FORMAL_ALTOPS\n\n[script-sources]\nread_verilog -sv @basedir@/tests/coverage/riscv_rv32i_insn.v\nread_verilog -sv @basedir@/cores/@core@/wrapper.sv\nread_ilang @basedir@/cores/@core@/@core@-syn/@ilang_file@\n\n[filter-checks]\n+ insn_(lb|lbu|lh|lhu|lw|lwu|ld|c_lw|c_lwsp|c_ld|c_ldsp)_ch1\n+ insn_(mul|mulh|mulhsu|mulhu|div|divu|rem|remu|mulw|divw|divuw|remw|remuw)_ch1\n- (insn_.*|csrw_.*|ill)_ch1\nEOT\n\npython3 ../../checks/genchecks.py\n\n# see https://nbviewer.jupyter.org/url/svn.clairexen.net/fmbench/2018B/report.ipynb\n#sed -i '/^smtbmc/ s/boolector/yices/' checks/insn_b{ge,lt,geu,ltu}_ch0.sby\n#sed -i '/^smtbmc/ s/boolector/yices/' checks/{pc_bwd_ch0,unique_ch1,causal_ch0}.sby\n#sed -i '/^smtbmc/ s/boolector/yices/' checks/insn_j*.sby\n#sed -i '/^smtbmc/ s/boolector/yices/' checks/insn_c_{xor,mv,or,sw}_*.sby\n#sed -i '/^smtbmc/ s/boolector/yices/' checks/insn_{xor,sw,sh,addi}_*.sby\n"
  },
  {
    "path": "cores/rocket/muldivlen.py",
    "content": "#!/usr/bin/env python3\n\nimport os\nfrom Verilog_VCD.Verilog_VCD import parse_vcd\n\nlines = list()\n\nfor i in range(100):\n    fn = None\n    in1 = None\n    in2 = None\n    vcd = \"muldivlen_cover/engine_0/trace%d.vcd\" % i\n    if not os.path.isfile(vcd):\n        break\n    for netinfo in parse_vcd(vcd).values():\n        for net in netinfo['nets']:\n            if net[\"hier\"] != \"muldivlen\":\n                continue\n            if net[\"name\"] == \"io_req_bits_fn\":\n                fn = netinfo['tv'][0][1]\n            if net[\"name\"] == \"io_req_bits_in1\":\n                in1 = netinfo['tv'][0][1]\n            if net[\"name\"] == \"io_req_bits_in2\":\n                in2 = netinfo['tv'][0][1]\n    lines.append(\"%s %s %s\" % (fn, in1, in2))\n\nassert(len(lines) == 24)\n\nfor line in sorted(lines):\n    print(line)\n\n"
  },
  {
    "path": "cores/rocket/muldivlen.sby",
    "content": "[tasks]\ncheck\ncover\n\n[options]\ncheck: mode bmc\ncover: mode cover\ndepth 100\n\n[engines]\nsmtbmc yices\n\n[script]\nread_verilog freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v\nread_verilog -sv muldivlen.sv\nprep -nordff -top muldivlen\nchformal -assume -early\nopt_clean\n\n[files]\nrocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v\nmuldivlen.sv\n"
  },
  {
    "path": "cores/rocket/muldivlen.sv",
    "content": "module muldivlen (\n\tinput clock\n);\n\t// MulDiv inputs\n\t(* keep *) rand       reg        io_req_valid;\n\t(* keep *) rand const reg [ 3:0] io_req_bits_fn;\n\t(* keep *) rand const reg [31:0] io_req_bits_in1;\n\t(* keep *) rand const reg [31:0] io_req_bits_in2;\n\t(* keep *) rand       reg [ 4:0] io_req_bits_tag;\n\t(* keep *) rand       reg        io_kill;\n\t(* keep *) wire                  io_resp_ready;\n\n\t// MulDiv outputs\n\t(* keep *) wire        io_req_ready;\n\t(* keep *) wire        io_resp_valid;\n\t(* keep *) wire [31:0] io_resp_bits_data;\n\t(* keep *) wire [ 4:0] io_resp_bits_tag;\n\n\treg reset = 1;\n\talways @(posedge clock) reset <= 0;\n\n\tinteger i;\n\tinteger job_len;\n\n\tassign io_resp_ready = (job_len != 0);\n\n\twire values_ok =\n\t\t\t(io_req_bits_in1 == 32'h 0000_0000 || io_req_bits_in1 == 32'h ffff_ffff) &&\n\t\t\t(io_req_bits_in2 == 32'h 0000_0000 || io_req_bits_in2 == 32'h ffff_ffff);\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tassume (!io_req_valid);\n\t\t\tjob_len <= 0;\n\t\tend else begin\n\t\t\tjob_len <= job_len + |job_len;\n\t\t\tif (io_resp_ready && io_resp_valid) begin\n\t\t\t\tcase (io_req_bits_fn)\n\t\t\t\t\t0: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 33);\n\t\t\t\t\t\tassert (job_len == 33);\n\t\t\t\t\tend\n\t\t\t\t\t1: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 33);\n\t\t\t\t\t\tassert (job_len == 33);\n\t\t\t\t\tend\n\t\t\t\t\t2: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 33);\n\t\t\t\t\t\tassert (job_len == 33);\n\t\t\t\t\tend\n\t\t\t\t\t3: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 33);\n\t\t\t\t\t\tassert (job_len == 33);\n\t\t\t\t\tend\n\t\t\t\t\t4: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 34);\n\t\t\t\t\t\tcover (values_ok && job_len == 35);\n\t\t\t\t\t\tcover (values_ok && job_len == 36);\n\t\t\t\t\t\tassert (34 <= job_len && job_len <= 36);\n\t\t\t\t\tend\n\t\t\t\t\t5: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 34);\n\t\t\t\t\t\tassert (job_len == 34);\n\t\t\t\t\tend\n\t\t\t\t\t6: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 34);\n\t\t\t\t\t\tcover (values_ok && job_len == 35);\n\t\t\t\t\t\tcover (values_ok && job_len == 36);\n\t\t\t\t\t\tassert (34 <= job_len && job_len <= 36);\n\t\t\t\t\tend\n\t\t\t\t\t7: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 34);\n\t\t\t\t\t\tassert (job_len == 34);\n\t\t\t\t\tend\n\t\t\t\t\t8: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 33);\n\t\t\t\t\t\tassert (job_len == 33);\n\t\t\t\t\tend\n\t\t\t\t\t9: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 33);\n\t\t\t\t\t\tassert (job_len == 33);\n\t\t\t\t\tend\n\t\t\t\t\t10: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 33);\n\t\t\t\t\t\tassert (job_len == 33);\n\t\t\t\t\tend\n\t\t\t\t\t11: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 33);\n\t\t\t\t\t\tassert (job_len == 33);\n\t\t\t\t\tend\n\t\t\t\t\t12: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 34);\n\t\t\t\t\t\tcover (values_ok && job_len == 35);\n\t\t\t\t\t\tcover (values_ok && job_len == 36);\n\t\t\t\t\t\tassert (34 <= job_len && job_len <= 36);\n\t\t\t\t\tend\n\t\t\t\t\t13: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 34);\n\t\t\t\t\t\tassert (job_len == 34);\n\t\t\t\t\tend\n\t\t\t\t\t14: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 34);\n\t\t\t\t\t\tcover (values_ok && job_len == 35);\n\t\t\t\t\t\tcover (values_ok && job_len == 36);\n\t\t\t\t\t\tassert (34 <= job_len && job_len <= 36);\n\t\t\t\t\tend\n\t\t\t\t\t15: begin\n\t\t\t\t\t\tcover (values_ok && job_len == 34);\n\t\t\t\t\t\tassert (job_len == 34);\n\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\t\tjob_len <= 0;\n\t\t\tend\n\t\t\tif (io_req_ready && io_req_valid) begin\n\t\t\t\tassume (job_len == 0);\n\t\t\t\tjob_len <= 1;\n\t\t\tend\n\t\tend\n\tend\n\n\tMulDiv uut (\n\t\t.clock             (clock            ),\n\t\t.reset             (reset            ),\n\t\t.io_req_ready      (io_req_ready     ),\n\t\t.io_req_valid      (io_req_valid     ),\n\t\t.io_req_bits_fn    (io_req_bits_fn   ),\n\t\t.io_req_bits_in1   (io_req_bits_in1  ),\n\t\t.io_req_bits_in2   (io_req_bits_in2  ),\n\t\t.io_req_bits_tag   (io_req_bits_tag  ),\n\t\t.io_kill           (io_kill          ),\n\t\t.io_resp_ready     (io_resp_ready    ),\n\t\t.io_resp_valid     (io_resp_valid    ),\n\t\t.io_resp_bits_data (io_resp_bits_data),\n\t\t.io_resp_bits_tag  (io_resp_bits_tag ),\n\t);\nendmodule\n"
  },
  {
    "path": "cores/rocket/rocketrvfi.sv",
    "content": "module RocketTileWithRVFI (\n\tinput         clock,\n\tinput         reset,\n\t`RVFI_OUTPUTS,\n\n\tinput         intsink_sync_0,\n\tinput         int_1_sync_0,\n\tinput         int_0_sync_0,\n\tinput         int_0_sync_1,\n\n\toutput        tl_slave_a_ready,\n\tinput         tl_slave_a_valid,\n\tinput  [2:0]  tl_slave_a_bits_opcode,\n\tinput  [2:0]  tl_slave_a_bits_param,\n\tinput  [2:0]  tl_slave_a_bits_size,\n\tinput  [4:0]  tl_slave_a_bits_source,\n\tinput  [31:0] tl_slave_a_bits_address,\n\tinput  [7:0]  tl_slave_a_bits_mask,\n\tinput  [63:0] tl_slave_a_bits_data,\n\tinput         tl_slave_d_ready,\n\toutput        tl_slave_d_valid,\n\toutput [2:0]  tl_slave_d_bits_opcode,\n\toutput [1:0]  tl_slave_d_bits_param,\n\toutput [2:0]  tl_slave_d_bits_size,\n\toutput [4:0]  tl_slave_d_bits_source,\n\toutput        tl_slave_d_bits_sink,\n\toutput        tl_slave_d_bits_denied,\n\toutput [63:0] tl_slave_d_bits_data,\n\toutput        tl_slave_d_bits_corrupt,\n\n\tinput         tl_master_a_ready,\n\toutput        tl_master_a_valid,\n\toutput [2:0]  tl_master_a_bits_opcode,\n\toutput [2:0]  tl_master_a_bits_param,\n\toutput [3:0]  tl_master_a_bits_size,\n\toutput        tl_master_a_bits_source,\n\toutput [31:0] tl_master_a_bits_address,\n\toutput [7:0]  tl_master_a_bits_mask,\n\toutput [63:0] tl_master_a_bits_data,\n\toutput        tl_master_a_bits_corrupt,\n\toutput        tl_master_d_ready,\n\tinput         tl_master_d_valid,\n\tinput  [2:0]  tl_master_d_bits_opcode,\n\tinput  [1:0]  tl_master_d_bits_param,\n\tinput  [3:0]  tl_master_d_bits_size,\n\tinput         tl_master_d_bits_source,\n\tinput         tl_master_d_bits_sink,\n\tinput         tl_master_d_bits_denied,\n\tinput  [63:0] tl_master_d_bits_data,\n\tinput         tl_master_d_bits_corrupt\n);\n\tRocketTile rocket_tile (\n\t\t.clock                                  (clock                    ),\n\t\t.reset                                  (reset                    ),\n\n\t\t.auto_intsink_in_sync_0                 (intsink_sync_0           ),\n\t\t.auto_int_in_xing_in_1_sync_0           (int_1_sync_0             ),\n\t\t.auto_int_in_xing_in_0_sync_0           (int_0_sync_0             ),\n\t\t.auto_int_in_xing_in_0_sync_1           (int_0_sync_1             ),\n\n\t\t.auto_tl_slave_xing_in_a_ready          (tl_slave_a_ready         ),\n\t\t.auto_tl_slave_xing_in_a_valid          (tl_slave_a_valid         ),\n\t\t.auto_tl_slave_xing_in_a_bits_opcode    (tl_slave_a_bits_opcode   ),\n\t\t.auto_tl_slave_xing_in_a_bits_param     (tl_slave_a_bits_param    ),\n\t\t.auto_tl_slave_xing_in_a_bits_size      (tl_slave_a_bits_size     ),\n\t\t.auto_tl_slave_xing_in_a_bits_source    (tl_slave_a_bits_source   ),\n\t\t.auto_tl_slave_xing_in_a_bits_address   (tl_slave_a_bits_address  ),\n\t\t.auto_tl_slave_xing_in_a_bits_mask      (tl_slave_a_bits_mask     ),\n\t\t.auto_tl_slave_xing_in_a_bits_data      (tl_slave_a_bits_data     ),\n\t\t.auto_tl_slave_xing_in_d_ready          (tl_slave_d_ready         ),\n\t\t.auto_tl_slave_xing_in_d_valid          (tl_slave_d_valid         ),\n\t\t.auto_tl_slave_xing_in_d_bits_opcode    (tl_slave_d_bits_opcode   ),\n\t\t.auto_tl_slave_xing_in_d_bits_param     (tl_slave_d_bits_param    ),\n\t\t.auto_tl_slave_xing_in_d_bits_size      (tl_slave_d_bits_size     ),\n\t\t.auto_tl_slave_xing_in_d_bits_source    (tl_slave_d_bits_source   ),\n\t\t.auto_tl_slave_xing_in_d_bits_sink      (tl_slave_d_bits_sink     ),\n\t\t.auto_tl_slave_xing_in_d_bits_denied    (tl_slave_d_bits_denied   ),\n\t\t.auto_tl_slave_xing_in_d_bits_data      (tl_slave_d_bits_data     ),\n\t\t.auto_tl_slave_xing_in_d_bits_corrupt   (tl_slave_d_bits_corrupt  ),\n\n\t\t.auto_tl_master_xing_out_a_ready        (tl_master_a_ready        ),\n\t\t.auto_tl_master_xing_out_a_valid        (tl_master_a_valid        ),\n\t\t.auto_tl_master_xing_out_a_bits_opcode  (tl_master_a_bits_opcode  ),\n\t\t.auto_tl_master_xing_out_a_bits_param   (tl_master_a_bits_param   ),\n\t\t.auto_tl_master_xing_out_a_bits_size    (tl_master_a_bits_size    ),\n\t\t.auto_tl_master_xing_out_a_bits_source  (tl_master_a_bits_source  ),\n\t\t.auto_tl_master_xing_out_a_bits_address (tl_master_a_bits_address ),\n\t\t.auto_tl_master_xing_out_a_bits_mask    (tl_master_a_bits_mask    ),\n\t\t.auto_tl_master_xing_out_a_bits_data    (tl_master_a_bits_data    ),\n\t\t.auto_tl_master_xing_out_a_bits_corrupt (tl_master_a_bits_corrupt ),\n\t\t.auto_tl_master_xing_out_d_ready        (tl_master_d_ready        ),\n\t\t.auto_tl_master_xing_out_d_valid        (tl_master_d_valid        ),\n\t\t.auto_tl_master_xing_out_d_bits_opcode  (tl_master_d_bits_opcode  ),\n\t\t.auto_tl_master_xing_out_d_bits_param   (tl_master_d_bits_param   ),\n\t\t.auto_tl_master_xing_out_d_bits_size    (tl_master_d_bits_size    ),\n\t\t.auto_tl_master_xing_out_d_bits_source  (tl_master_d_bits_source  ),\n\t\t.auto_tl_master_xing_out_d_bits_sink    (tl_master_d_bits_sink    ),\n\t\t.auto_tl_master_xing_out_d_bits_denied  (tl_master_d_bits_denied  ),\n\t\t.auto_tl_master_xing_out_d_bits_data    (tl_master_d_bits_data    ),\n\t\t.auto_tl_master_xing_out_d_bits_corrupt (tl_master_d_bits_corrupt )\n\t);\n\n\tassign rvfi_valid                = rocket_tile.RVFI_valid;\n\tassign rvfi_order                = rocket_tile.RVFI_order;\n\tassign rvfi_insn                 = rocket_tile.RVFI_insn;\n\tassign rvfi_trap                 = rocket_tile.RVFI_trap;\n\tassign rvfi_halt                 = rocket_tile.RVFI_halt;\n\tassign rvfi_intr                 = rocket_tile.RVFI_intr;\n\tassign rvfi_mode                 = rocket_tile.RVFI_mode;\n\tassign rvfi_ixl                  = rocket_tile.RVFI_ixl;\n\n\tassign rvfi_pc_rdata             = rocket_tile.RVFI_pc_rdata;\n\tassign rvfi_pc_wdata             = rocket_tile.RVFI_pc_wdata;\n\n\tassign rvfi_rs1_addr             = rocket_tile.RVFI_rs1_addr;\n\tassign rvfi_rs1_rdata            = rocket_tile.RVFI_rs1_rdata;\n\n\tassign rvfi_rs2_addr             = rocket_tile.RVFI_rs2_addr;\n\tassign rvfi_rs2_rdata            = rocket_tile.RVFI_rs2_rdata;\n\n\tassign rvfi_rd_addr              = rocket_tile.RVFI_rd_addr;\n\tassign rvfi_rd_wdata             = rocket_tile.RVFI_rd_wdata;\n\n\tassign rvfi_mem_addr             = rocket_tile.RVFI_mem_addr;\n\tassign rvfi_mem_rdata            = rocket_tile.RVFI_mem_rdata;\n\tassign rvfi_mem_rmask            = rocket_tile.RVFI_mem_rmask;\n\tassign rvfi_mem_wdata            = rocket_tile.RVFI_mem_wdata;\n\tassign rvfi_mem_wmask            = rocket_tile.RVFI_mem_wmask;\n\tassign rvfi_mem_extamo           = rocket_tile.RVFI_mem_extamo;\n\n\tassign rvfi_csr_misa_wmask       = rocket_tile.RVFI_csr_misa_wmask;\n\tassign rvfi_csr_misa_rmask       = rocket_tile.RVFI_csr_misa_rmask;\n\tassign rvfi_csr_misa_wdata       = rocket_tile.RVFI_csr_misa_wdata;\n\tassign rvfi_csr_misa_rdata       = rocket_tile.RVFI_csr_misa_rdata;\n\n\tassign rvfi_csr_minstret_wmask   = rocket_tile.RVFI_csr_minstret_wmask;\n\tassign rvfi_csr_minstret_rmask   = rocket_tile.RVFI_csr_minstret_rmask;\n\tassign rvfi_csr_minstret_wdata   = rocket_tile.RVFI_csr_minstret_wdata;\n\tassign rvfi_csr_minstret_rdata   = rocket_tile.RVFI_csr_minstret_rdata;\n\n\tassign rvfi_csr_mcycle_wmask     = rocket_tile.RVFI_csr_mcycle_wmask;\n\tassign rvfi_csr_mcycle_rmask     = rocket_tile.RVFI_csr_mcycle_rmask;\n\tassign rvfi_csr_mcycle_wdata     = rocket_tile.RVFI_csr_mcycle_wdata;\n\tassign rvfi_csr_mcycle_rdata     = rocket_tile.RVFI_csr_mcycle_rdata;\nendmodule\n"
  },
  {
    "path": "cores/rocket/testbench.cc",
    "content": "#include \"Vtestbench.h\"\n#include \"verilated.h\"\n#include \"verilated_vcd_c.h\"\n\nint timer = 0;\n\ndouble sc_time_stamp()\n{\n\treturn timer;\n}\n\nint main(int argc, char **argv, char **env)\n{\n\tVerilated::traceEverOn(true);\n\n\tVerilated::commandArgs(argc, argv);\n\tVtestbench *tb = new Vtestbench;\n\n\tVerilatedVcdC *tfp = new VerilatedVcdC;\n\ttb->trace(tfp, 99);\n\ttfp->open(\"testbench.vcd\");\n\n\ttb->clock = 0;\n\ttb->eval();\n\ttfp->dump(timer++);\n\n\twhile (tb->genclock)\n\t{\n\t\tif (timer > 1)\n\t\t\ttb->clock = ~tb->clock;\n\n\t\ttb->eval();\n\t\ttfp->dump(timer++);\n\t}\n\n\ttfp->close();\n\n\tdelete tfp;\n\tdelete tb;\n\n\treturn 0;\n}\n"
  },
  {
    "path": "cores/rocket/testbench.sh",
    "content": "#!/bin/bash\n\nset -ex\n\nuse_iverilog=false\ntracetb=insncheck/insn_sw_ch0/engine_0/trace_tb.v\n\negrep -v 'UUT.(core.rvfi_|core.io_status_dprv|core.csr.io_time|core.csr.io_status_dprv|frontend.icache.io_resp_bits)' $tracetb > testbench.v\n\nif $use_iverilog; then\n\tiverilog -o testbench -s testbench -DSIMULATION -DRANDOMIZE_REG_INIT -DRANDOMIZE_MEM_INIT testbench.v \\\n\t\t\trocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v \\\n\t\t\trocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.behav_srams.v \\\n\t\t\trocket-chip/vsrc/plusarg_reader.v rocket-chip/vsrc/RVFIMonitor.v\n\t./testbench +vcd=testbench.vcd\nelse\n\tverilator --exe --cc -Wno-fatal --top-module testbench --trace --trace-underscore -DSIMULATION testbench.v testbench.cc \\\n\t\t\trocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v \\\n\t\t\trocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.behav_srams.v \\\n\t\t\trocket-chip/vsrc/plusarg_reader.v rocket-chip/vsrc/RVFIMonitor.v\n\tmake -C obj_dir -f Vtestbench.mk\n\t./obj_dir/Vtestbench\nfi\n\n"
  },
  {
    "path": "cores/rocket/wrapper.sv",
    "content": "`define XLEN_BYTES (`RISCV_FORMAL_XLEN == 32 ? 4 : 8)\n\nmodule rvfi_wrapper (\n\tinput         clock,\n\tinput         reset,\n\t`RVFI_OUTPUTS\n);\n`ifdef ROCKET_NORESET\n\twire actual_reset = 0;\n`else\n\treg [3:0] reset_cnt = 0;\n\twire actual_reset = reset || |reset_cnt;\n\n\talways @(posedge clock) begin\n\t\treset_cnt <= reset ? 4'd 5 : reset_cnt - |reset_cnt;\n\tend\n`endif\n\n\t(* keep *) wire  [31:0] reset_vector = 32'h10040;\n\n\t// Rocket TileLink Slave\n\n\t(* keep *) wire        tl_slave_a_ready;\n\t(* keep *) wire        tl_slave_a_valid = 0;\n\t(* keep *) wire [2:0]  tl_slave_a_bits_opcode = 0;\n\t(* keep *) wire [2:0]  tl_slave_a_bits_param = 0;\n\t(* keep *) wire [2:0]  tl_slave_a_bits_size = 0;\n\t(* keep *) wire [4:0]  tl_slave_a_bits_source = 0;\n\t(* keep *) wire [31:0] tl_slave_a_bits_address = 0;\n\t(* keep *) wire [7:0]  tl_slave_a_bits_mask = 0;\n\t(* keep *) wire [63:0] tl_slave_a_bits_data = 0;\n\n\t(* keep *) wire        tl_slave_d_ready = 0;\n\t(* keep *) wire        tl_slave_d_valid;\n\t(* keep *) wire [2:0]  tl_slave_d_bits_opcode;\n\t(* keep *) wire [1:0]  tl_slave_d_bits_param;\n\t(* keep *) wire [2:0]  tl_slave_d_bits_size;\n\t(* keep *) wire [4:0]  tl_slave_d_bits_source;\n\t(* keep *) wire        tl_slave_d_bits_sink;\n\t(* keep *) wire        tl_slave_d_bits_denied;\n\t(* keep *) wire [63:0] tl_slave_d_bits_data;\n\t(* keep *) wire        tl_slave_d_bits_corrupt;\n\n\t// Rocket TileLink Master\n\n\t(* keep *) wire        tl_master_a_ready;\n\t(* keep *) wire        tl_master_a_valid;\n\t(* keep *) wire [2:0]  tl_master_a_bits_opcode;\n\t(* keep *) wire [2:0]  tl_master_a_bits_param;\n\t(* keep *) wire [3:0]  tl_master_a_bits_size;\n\t(* keep *) wire        tl_master_a_bits_source;\n\t(* keep *) wire [31:0] tl_master_a_bits_address;\n\t(* keep *) wire [7:0]  tl_master_a_bits_mask;\n\t(* keep *) wire [63:0] tl_master_a_bits_data;\n\t(* keep *) wire        tl_master_a_bits_corrupt;\n\n\t(* keep *) wire        tl_master_d_ready;\n\t(* keep *) wire        tl_master_d_valid;\n\t(* keep *) wire [2:0]  tl_master_d_bits_opcode;\n\t(* keep *) wire [1:0]  tl_master_d_bits_param;\n\t(* keep *) wire [3:0]  tl_master_d_bits_size;\n\t(* keep *) wire        tl_master_d_bits_source;\n\t(* keep *) wire        tl_master_d_bits_sink;\n\t(* keep *) wire        tl_master_d_bits_denied;\n\t(* keep *) wire [63:0] tl_master_d_bits_data;\n\t(* keep *) wire        tl_master_d_bits_corrupt;\n\n\t// TileLink Master A-D Dummy Slave\n\n\ttilelink_ad_dummy tilelink_slave (\n\t\t.clock                  (clock                   ),\n\t\t.reset                  (actual_reset            ),\n\n\t\t.channel_a_ready        (tl_master_a_ready       ),\n\t\t.channel_a_valid        (tl_master_a_valid       ),\n\t\t.channel_a_bits_address (tl_master_a_bits_address),\n\t\t.channel_a_bits_data    (tl_master_a_bits_data   ),\n\t\t.channel_a_bits_mask    (tl_master_a_bits_mask   ),\n\t\t.channel_a_bits_opcode  (tl_master_a_bits_opcode ),\n\t\t.channel_a_bits_param   (tl_master_a_bits_param  ),\n\t\t.channel_a_bits_size    (tl_master_a_bits_size   ),\n\t\t.channel_a_bits_source  (tl_master_a_bits_source ),\n\n\t\t.channel_d_ready        (tl_master_d_ready       ),\n\t\t.channel_d_valid        (tl_master_d_valid       ),\n\t\t.channel_d_bits_data    (tl_master_d_bits_data   ),\n\t\t.channel_d_bits_denied  (tl_master_d_bits_denied ),\n\t\t.channel_d_bits_corrupt (tl_master_d_bits_corrupt),\n\t\t.channel_d_bits_opcode  (tl_master_d_bits_opcode ),\n\t\t.channel_d_bits_param   (tl_master_d_bits_param  ),\n\t\t.channel_d_bits_sink    (tl_master_d_bits_sink   ),\n\t\t.channel_d_bits_size    (tl_master_d_bits_size   ),\n\t\t.channel_d_bits_source  (tl_master_d_bits_source )\n\t);\n\n\t// Rocket Tile\n\n\tRocketTileWithRVFI rocket_rvfi_tile (\n\t\t.clock                  (clock                    ),\n\t\t.reset                  (actual_reset             ),\n\n\t\t`RVFI_CONN,\n\n\t\t.intsink_sync_0          (1'b0                    ),\n\t\t.int_1_sync_0            (1'b0                    ),\n\t\t.int_0_sync_0            (1'b0                    ),\n\t\t.int_0_sync_1            (1'b0                    ),\n\n\t\t.tl_slave_a_ready        (tl_slave_a_ready        ),\n\t\t.tl_slave_a_valid        (tl_slave_a_valid        ),\n\t\t.tl_slave_a_bits_opcode  (tl_slave_a_bits_opcode  ),\n\t\t.tl_slave_a_bits_param   (tl_slave_a_bits_param   ),\n\t\t.tl_slave_a_bits_size    (tl_slave_a_bits_size    ),\n\t\t.tl_slave_a_bits_source  (tl_slave_a_bits_source  ),\n\t\t.tl_slave_a_bits_address (tl_slave_a_bits_address ),\n\t\t.tl_slave_a_bits_mask    (tl_slave_a_bits_mask    ),\n\t\t.tl_slave_a_bits_data    (tl_slave_a_bits_data    ),\n\t\t.tl_slave_d_ready        (tl_slave_d_ready        ),\n\t\t.tl_slave_d_valid        (tl_slave_d_valid        ),\n\t\t.tl_slave_d_bits_opcode  (tl_slave_d_bits_opcode  ),\n\t\t.tl_slave_d_bits_param   (tl_slave_d_bits_param   ),\n\t\t.tl_slave_d_bits_size    (tl_slave_d_bits_size    ),\n\t\t.tl_slave_d_bits_source  (tl_slave_d_bits_source  ),\n\t\t.tl_slave_d_bits_sink    (tl_slave_d_bits_sink    ),\n\t\t.tl_slave_d_bits_denied  (tl_slave_d_bits_denied  ),\n\t\t.tl_slave_d_bits_data    (tl_slave_d_bits_data    ),\n\t\t.tl_slave_d_bits_corrupt (tl_slave_d_bits_corrupt ),\n\n\t\t.tl_master_a_ready       (tl_master_a_ready       ),\n\t\t.tl_master_a_valid       (tl_master_a_valid       ),\n\t\t.tl_master_a_bits_opcode (tl_master_a_bits_opcode ),\n\t\t.tl_master_a_bits_param  (tl_master_a_bits_param  ),\n\t\t.tl_master_a_bits_size   (tl_master_a_bits_size   ),\n\t\t.tl_master_a_bits_source (tl_master_a_bits_source ),\n\t\t.tl_master_a_bits_address(tl_master_a_bits_address),\n\t\t.tl_master_a_bits_mask   (tl_master_a_bits_mask   ),\n\t\t.tl_master_a_bits_data   (tl_master_a_bits_data   ),\n\t\t.tl_master_a_bits_corrupt(tl_master_a_bits_corrupt),\n\t\t.tl_master_d_ready       (tl_master_d_ready       ),\n\t\t.tl_master_d_valid       (tl_master_d_valid       ),\n\t\t.tl_master_d_bits_opcode (tl_master_d_bits_opcode ),\n\t\t.tl_master_d_bits_param  (tl_master_d_bits_param  ),\n\t\t.tl_master_d_bits_size   (tl_master_d_bits_size   ),\n\t\t.tl_master_d_bits_source (tl_master_d_bits_source ),\n\t\t.tl_master_d_bits_sink   (tl_master_d_bits_sink   ),\n\t\t.tl_master_d_bits_denied (tl_master_d_bits_denied ),\n\t\t.tl_master_d_bits_data   (tl_master_d_bits_data   ),\n\t\t.tl_master_d_bits_corrupt(tl_master_d_bits_corrupt)\n\t);\n\n\t(* keep *) rvfi_channel #(.CHANNEL_IDX(0)) rvfi_channel_0 (`RVFI_CONN);\n\t(* keep *) rvfi_channel #(.CHANNEL_IDX(1)) rvfi_channel_1 (`RVFI_CONN);\nendmodule\n\nmodule rocket_pma_map (\n\tinput [`RISCV_FORMAL_XLEN-1:0] address,\n\tinput [1:0] log2len,\n\toutput reg A, R, W, X, C\n);\n\treg [4:0] modes_first, modes_last;\n\twire [`RISCV_FORMAL_XLEN-1:0] address_first = address;\n\twire [`RISCV_FORMAL_XLEN-1:0] address_last = address + (1 << log2len) - 1;\n\n\talways @* begin\n\t\t// Generated Address Map\n\t\t//         0 -     1000 ARWX  debug-controller@0\n\t\t//      3000 -     4000 ARWX  error-device@3000\n\t\t//     10000 -    20000  R XC rom@10000\n\t\t//   2000000 -  2010000 ARW   clint@2000000\n\t\t//   c000000 - 10000000 ARW   interrupt-controller@c000000\n\t\t//  60000000 - 80000000  RWX  mmio@60000000\n\t\t//  80000000 - 80004000 ARWX  dtim@80000000\n\n\t\tmodes_first = 5'b 00000;\n\t\t// if (64'h 00000000 <= address_first && address_first < 64'h 00001000) modes_first = 5'b 11110;\n\t\tif (64'h 00003000 <= address_first && address_first < 64'h 00004000) modes_first = 5'b 11110;\n\t\tif (64'h 00010000 <= address_first && address_first < 64'h 00020000) modes_first = 5'b 01010;\n\t\tif (64'h 02000000 <= address_first && address_first < 64'h 02010000) modes_first = 5'b 11100;\n\t\tif (64'h 0c000000 <= address_first && address_first < 64'h 10000000) modes_first = 5'b 11100;\n\t\tif (64'h 60000000 <= address_first && address_first < 64'h 80000000) modes_first = 5'b 01110;\n\t\tif (64'h 80000000 <= address_first && address_first < 64'h 80004000) modes_first = 5'b 11110;\n\n\t\tmodes_last = 5'b 00000;\n\t\t// if (64'h 00000000 <= address_last && address_last < 64'h 00001000) modes_last = 5'b 11110;\n\t\tif (64'h 00003000 <= address_last && address_last < 64'h 00004000) modes_last = 5'b 11110;\n\t\tif (64'h 00010000 <= address_last && address_last < 64'h 00020000) modes_last = 5'b 01010;\n\t\tif (64'h 02000000 <= address_last && address_last < 64'h 02010000) modes_last = 5'b 11100;\n\t\tif (64'h 0c000000 <= address_last && address_last < 64'h 10000000) modes_last = 5'b 11100;\n\t\tif (64'h 60000000 <= address_last && address_last < 64'h 80000000) modes_last = 5'b 01110;\n\t\tif (64'h 80000000 <= address_last && address_last < 64'h 80004000) modes_last = 5'b 11110;\n\n\t\t{A, R, W, X, C} = modes_first & modes_last;\n\n\t\tif (log2len == 1 && address[0:0]) {A, R, W, C} = 0;\n\t\tif (log2len == 2 && address[1:0]) {A, R, W, C} = 0;\n\t\tif (log2len == 3 && address[2:0]) {A, R, W, C} = 0;\n\tend\nendmodule\n\nmodule tilelink_ad_dummy (\n\tinput clock,\n\tinput reset,\n\n\toutput                          channel_a_ready,\n\tinput                           channel_a_valid,\n\tinput  [                   2:0] channel_a_bits_opcode,\n\tinput  [                   2:0] channel_a_bits_param,\n\tinput  [                   3:0] channel_a_bits_size,\n\tinput                           channel_a_bits_source,\n\tinput  [                  31:0] channel_a_bits_address,\n\tinput  [       `XLEN_BYTES-1:0] channel_a_bits_mask,\n\tinput  [`RISCV_FORMAL_XLEN-1:0] channel_a_bits_data,\n\n\tinput                               channel_d_ready,\n\toutput                              channel_d_valid,\n\toutput reg [                   2:0] channel_d_bits_opcode,\n\toutput reg [                   1:0] channel_d_bits_param,\n\toutput reg [                   3:0] channel_d_bits_size,\n\toutput reg                          channel_d_bits_source,\n\toutput reg                          channel_d_bits_sink,\n\toutput reg [`RISCV_FORMAL_XLEN-1:0] channel_d_bits_data,\n\toutput reg                          channel_d_bits_denied,\n\toutput reg                          channel_d_bits_corrupt\n);\n\treg busy = 0, ready, last;\n\treg [15:0] count, next_count;\n\n\t// -- TL-UL --\n\n\tlocalparam [2:0] opcode_a_get = 4;            // -> opcode_d_accessackdata\n\tlocalparam [2:0] opcode_a_putfulldata = 0;    // -> opcode_d_accessack\n\tlocalparam [2:0] opcode_a_putpartialdata = 1; // -> opcode_d_accessack\n\n\tlocalparam [2:0] opcode_d_accessackdata = 1;\n\tlocalparam [2:0] opcode_d_accessack = 0;\n\n\t// -- TL-UH --\n\n\tlocalparam [2:0] opcode_a_arithmeticdata = 2; // -> opcode_d_accessackdata\n\tlocalparam [2:0] opcode_a_logicaldata = 3;    // -> opcode_d_accessackdata\n\tlocalparam [2:0] opcode_a_intent = 5;         // -> opcode_d_hintack\n\n\tlocalparam [2:0] opcode_d_hintack = 2;\n\n\treg [                   2:0] op_opcode;\n\treg [                   2:0] op_param;\n\treg [                   3:0] op_size;\n\treg                          op_source;\n\treg [`RISCV_FORMAL_XLEN-1:0] op_address;\n\treg [       `XLEN_BYTES-1:0] op_mask;\n\treg [`RISCV_FORMAL_XLEN-1:0] op_data;\n\n`ifdef ROCKET_INIT\n\tinteger cycle = 0;\n\talways @(posedge clock) cycle <= cycle+1;\n\n  `ifdef ROCKET_INITHACK\n\twire delay_a = 0, delay_d = 0;\n  `else\n\twire delay_a = 1, delay_d = 1;\n  `endif\n\n\twire [                   2:0] channel_d_bits_opcode_nd  = 0;\n\twire [                   1:0] channel_d_bits_param_nd   = 0;\n\twire [                   3:0] channel_d_bits_size_nd    = 0;\n\twire                          channel_d_bits_source_nd  = 0;\n\twire                          channel_d_bits_sink_nd    = 0;\n\twire [`RISCV_FORMAL_XLEN-1:0] channel_d_bits_data_nd    = op_address > 32'h 0001_0100 && cycle > 250 ? 64'h_f05ff06f_f05ff06f : 64'h_00000013_00000013;\n\twire                          channel_d_bits_denied_nd  = 0;\n\twire                          channel_d_bits_corrupt_nd = 0;\n`else\n\t`rvformal_rand_reg delay_a_nd;\n\t`rvformal_rand_reg delay_d_nd;\n\n  `ifdef RISCV_FORMAL_FAIRNESS\n\twire delay_a = 0, delay_d = 0;\n  `else\n\twire delay_a = delay_a_nd, delay_d = delay_d_nd;\n  `endif\n\n\t`rvformal_rand_reg [                   2:0] channel_d_bits_opcode_nd;\n\t`rvformal_rand_reg [                   1:0] channel_d_bits_param_nd;\n\t`rvformal_rand_reg [                   3:0] channel_d_bits_size_nd;\n\t`rvformal_rand_reg                          channel_d_bits_source_nd;\n\t`rvformal_rand_reg                          channel_d_bits_sink_nd;\n\t`rvformal_rand_reg [`RISCV_FORMAL_XLEN-1:0] channel_d_bits_data_nd;\n\t`rvformal_rand_reg                          channel_d_bits_denied_nd;\n\t`rvformal_rand_reg                          channel_d_bits_corrupt_nd;\n`endif\n\n\tassign channel_a_ready = (!busy || (last && channel_d_ready && channel_d_valid)) && !reset && !delay_a;\n\tassign channel_d_valid = ready && !reset && !delay_d;\n\n\talways @* begin\n\t\tlast = 1;\n\t\tready = 0;\n\t\tnext_count = count;\n\n\t\tchannel_d_bits_opcode = 0; // channel_d_bits_opcode_nd\n\t\tchannel_d_bits_param = channel_d_bits_param_nd;\n\t\tchannel_d_bits_size = channel_d_bits_size_nd;\n\t\tchannel_d_bits_source = channel_d_bits_source_nd;\n\t\tchannel_d_bits_sink = channel_d_bits_sink_nd;\n\t\tchannel_d_bits_data = channel_d_bits_data_nd;\n\t\tchannel_d_bits_denied = 1; // channel_d_bits_denied_nd\n\t\tchannel_d_bits_corrupt = 1; // channel_d_bits_corrupt_nd\n\n\t\tif (busy) begin\n\t\t\tif (op_opcode == opcode_a_get) begin\n\t\t\t\tchannel_d_bits_opcode = opcode_d_accessackdata;\n\t\t\t\tchannel_d_bits_param = 0;\n\t\t\t\tchannel_d_bits_size = op_size;\n\t\t\t\tchannel_d_bits_source = op_source;\n\t\t\t\tchannel_d_bits_denied = 0;\n\t\t\t\tchannel_d_bits_corrupt = 0;\n\t\t\t\tnext_count = (count + (`RISCV_FORMAL_XLEN / 8)) & 16'hffff;\n\t\t\t\tlast = next_count >= (1 << op_size);\n\t\t\t\tready = 1;\n\t\t\tend\n\n\t\t\tif (op_opcode == opcode_a_putfulldata) begin\n\t\t\t\tchannel_d_bits_opcode = opcode_d_accessack;\n\t\t\t\tchannel_d_bits_param = 0;\n\t\t\t\tchannel_d_bits_size = op_size;\n\t\t\t\tchannel_d_bits_source = op_source;\n\t\t\t\tchannel_d_bits_denied = 0;\n\t\t\t\tchannel_d_bits_corrupt = 0;\n\t\t\t\tlast = 1;\n\t\t\t\tready = 1;\n\t\t\tend\n\n\t\t\t// TBD: opcode_a_putpartialdata\n\t\t\t// TBD: opcode_a_arithmeticdata\n\t\t\t// TBD: opcode_a_logicaldata\n\t\t\t// TBD: opcode_a_intent\n\t\tend\n\tend\n\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tbusy <= 0;\n\t\tend else begin\n\t\t\tif (channel_d_ready && channel_d_valid) begin\n\t\t\t\tif (last)\n\t\t\t\t\tbusy <= 0;\n\t\t\t\telse\n\t\t\t\t\tcount <= next_count;\n\t\t\tend\n\n\t\t\tif (channel_a_ready && channel_a_valid) begin\n\t\t\t\top_opcode <= channel_a_bits_opcode;\n\t\t\t\top_param <= channel_a_bits_param;\n\t\t\t\top_size <= channel_a_bits_size;\n\t\t\t\top_source <= channel_a_bits_source;\n\t\t\t\top_address <= channel_a_bits_address;\n\t\t\t\top_mask <= channel_a_bits_mask;\n\t\t\t\top_data <= channel_a_bits_data;\n\t\t\t\tbusy <= 1;\n\t\t\t\tcount <= 0;\n\t\t\tend\n\t\tend\n\tend\nendmodule\n\n`ifndef ROCKET_INIT\nmodule MulDiv (\n\tinput         clock,\n\tinput         reset,\n\toutput        io__req_ready,\n\tinput         io__req_valid,\n\tinput  [ 3:0] io__req_bits_fn,\n\tinput         io__req_bits_dw,\n\tinput  [63:0] io__req_bits_in1,\n\tinput  [63:0] io__req_bits_in2,\n\tinput  [ 4:0] io__req_bits_tag,\n\tinput         io__kill,\n\tinput         io__resp_ready,\n\toutput        io__resp_valid,\n\toutput [63:0] io__resp_bits_data,\n\toutput [ 4:0] io__resp_bits_tag,\n\toutput        io_resp_valid,\n\toutput        io_resp_ready\n);\n\treg [63:0] internal_data;\n\treg [ 4:0] internal_tag;\n\treg        internal_busy = 0;\n\treg        internal_done = 0;\n\n\treg [63:0] result;\n\n\talways @* begin\n\t\tresult = 123456789;\n\t\tcase (io__req_bits_fn)\n\t\t\t0: result = (io__req_bits_in1 + io__req_bits_in2) ^ 64'h 2cdf52a55876063e; // MUL\n\t\t\t1: result = (io__req_bits_in1 + io__req_bits_in2) ^ 64'h 15d01651f6583fb7; // MULH\n\t\t\t2: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h ea3969edecfbe137; // MULHSU\n\t\t\t3: result = (io__req_bits_in1 + io__req_bits_in2) ^ 64'h d13db50d949ce5e8; // MULHU\n\t\t\t4: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h 29bbf66f7f8529ec; // DIV\n\t\t\t5: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h 8c629acb10e8fd70; // DIVU\n\t\t\t6: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h f5b7d8538da68fa5; // REM\n\t\t\t7: result = (io__req_bits_in1 - io__req_bits_in2) ^ 64'h bc4402413138d0e1; // REMU\n\t\tendcase\n\t\tif (!io__req_bits_dw) begin\n\t\t\tresult = $signed(result << 32) >>> 32;\n\t\tend\n\tend\n\n`ifdef RISCV_FORMAL_FAIRNESS\n\tassign io__req_ready = !internal_busy;\n`else\n\tassign io__req_ready = $anyseq(1) && !internal_busy;\n`endif\n\n\tassign io__resp_valid = internal_done;\n\tassign io__resp_bits_data = internal_done ? internal_data : $anyseq(64);\n\tassign io__resp_bits_tag = internal_done ? internal_tag : $anyseq(5);\n\n\tassign io_resp_valid = io__resp_valid;\n\tassign io_resp_ready = io__resp_ready;\n\n\talways @(posedge clock) begin\n\t\tif (reset || io__kill) begin\n\t\t\tinternal_busy <= 0;\n\t\t\tinternal_done <= 0;\n\t\tend else begin\n\t\t\tif (io__req_ready && io__req_valid) begin\n\t\t\t\tinternal_data <= result;\n\t\t\t\tinternal_tag <= io__req_bits_tag;\n\t\t\t\tinternal_busy <= 1;\n\t\t\tend\n\n`ifdef RISCV_FORMAL_FAIRNESS\n\t\t\tif (internal_busy) begin\n\t\t\t\tinternal_done <= 1;\n\t\t\tend\n`else\n\t\t\tif (internal_busy && $anyseq(1)) begin\n\t\t\t\tinternal_done <= 1;\n\t\t\tend\n`endif\n\n\t\t\tif (io__resp_ready && io__resp_valid) begin\n\t\t\t\tinternal_busy <= 0;\n\t\t\t\tinternal_done <= 0;\n\t\t\tend\n\t\tend\n\tend\n\n\treg [2:0] done_cnt = 0;\n\n\talways @(posedge clock) begin\n\t\tdone_cnt <= done_cnt + |{done_cnt, internal_done};\n\t\t// cover(done_cnt == 7);\n\tend\nendmodule\n`endif\n"
  },
  {
    "path": "cores/serv/.gitignore",
    "content": "/checks\n/cover\n/serv-src\n/cexdata\n/cexdata.zip\n/disasm.s\n/disasm.o\n"
  },
  {
    "path": "cores/serv/README.md",
    "content": "riscv-formal proofs for SErial RiscV (SERV)\n===========================================\n\nQuickstart guide:\n\nFirst install Yosys, SymbiYosys, and the solvers. See\n[here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing)\nfor instructions. Then build the version of SERV with RVFI support and\nriscv-tools, and generate the formal checks:\n\n```\nbash generate.sh\n```\n\nThen run the formal checks:\n\n```\nmake -C checks -j$(nproc)\nbash cexdata.sh\n```\n"
  },
  {
    "path": "cores/serv/cexdata.sh",
    "content": "#!/bin/bash\n\nset -ex\n\nrm -rf cexdata\nmkdir cexdata\n\nwhile read dir; do echo \"$dir\t$(git -C $dir log -n1 --oneline)\"; \\\n\tdone < <( echo .; find serv-src -name '.git' -printf '%h\\n'; ) | \\\n\texpand -t30 > cexdata/version.txt\n\nfor x in checks/*/FAIL; do\n\ttest -f $x || continue\n\tx=${x%/FAIL}\n\ty=${x#checks/}\n\tcp $x/logfile.txt cexdata/$y.log\n\tif test -f $x/engine_*/trace.vcd; then\n\t\tcp $x/engine_*/trace.vcd cexdata/$y.vcd\n\t\tif grep -q \"^isa rv64\" checks.cfg; then\n\t\t\tpython3 disasm.py --64 cexdata/$y.vcd > cexdata/$y.asm\n\t\tfi\n\t\tif grep -q \"^isa rv32\" checks.cfg; then\n\t\t\tpython3 disasm.py cexdata/$y.vcd > cexdata/$y.asm\n\t\tfi\n\tfi\ndone\n\nfor x in checks/*.sby; do\n\tx=${x%.sby}\n\tx=${x#checks/}\n\tif [ -f checks/$x/PASS ]; then\n\t\tprintf \"%-20s %s %10s\\n\" $x pass $(sed '/Elapsed process time/ { s/.*\\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt)\n\telif [ -f checks/$x/FAIL ]; then\n\t\tprintf \"%-20s %s %10s\\n\" $x FAIL $(sed '/Elapsed process time/ { s/.*\\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt)\n\telse\n\t\tprintf \"%-20s %s\\n\" $x unknown\n\tfi\ndone | awk '{ print gensub(\":\", \"\", \"g\", $3), $0; }' | sort -n | cut -f2- -d' ' > cexdata/status.txt\n\nrm -f cexdata.zip\nzip -r cexdata.zip cexdata/\n\n"
  },
  {
    "path": "cores/serv/checks.cfg",
    "content": "[options]\nisa rv32i\nnret 1\n\n[depth]\ninsn            80\nreg       1     80\npc_fwd    1     80\npc_bwd    1     80\nliveness  1  40 150\nunique    1  50 80\ncausal    1     80\n\n[defines]\n`define RISCV_FORMAL_ALIGNED_MEM\n\n[defines liveness]\n`define MEMIO_FAIRNESS\n\n[verilog-files]\n@basedir@/cores/@core@/wrapper.sv\n@basedir@/cores/@core@/serv-src/rtl/serv_bufreg.v\n@basedir@/cores/@core@/serv-src/rtl/serv_bufreg2.v\n@basedir@/cores/@core@/serv-src/rtl/serv_alu.v\n@basedir@/cores/@core@/serv-src/rtl/serv_csr.v\n@basedir@/cores/@core@/serv-src/rtl/serv_ctrl.v\n@basedir@/cores/@core@/serv-src/rtl/serv_decode.v\n@basedir@/cores/@core@/serv-src/rtl/serv_immdec.v\n@basedir@/cores/@core@/serv-src/rtl/serv_mem_if.v\n@basedir@/cores/@core@/serv-src/rtl/serv_rf_if.v\n@basedir@/cores/@core@/serv-src/rtl/serv_rf_ram.v\n@basedir@/cores/@core@/serv-src/rtl/serv_rf_ram_if.v\n@basedir@/cores/@core@/serv-src/rtl/serv_state.v\n@basedir@/cores/@core@/serv-src/rtl/serv_top.v\n@basedir@/cores/@core@/serv-src/rtl/serv_rf_top.v\n"
  },
  {
    "path": "cores/serv/cover.gtkw",
    "content": "[*]\n[*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI\n[*] Thu Nov  1 11:25:45 2018\n[*]\n[timestart] 0\n[size] 1394 830\n[pos] -1 -1\n*-5.990967 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1\n[treeopen] rvfi_testbench.\n[treeopen] rvfi_testbench.wrapper.\n[sst_width] 225\n[signals_width] 310\n[sst_expanded] 1\n[sst_vpaned_height] 241\n@24\nrvfi_testbench.cycle[7:0]\n@200\n-\n@28\nrvfi_testbench.wrapper.clock\nrvfi_testbench.wrapper.reset\n@200\n-\n-I-MEM\n@28\nrvfi_testbench.wrapper.ibus_cyc\nrvfi_testbench.wrapper.ibus_ack\n@22\nrvfi_testbench.wrapper.ibus_adr[31:0]\nrvfi_testbench.wrapper.ibus_rdt[31:0]\n@200\n-\n-D-MEM\n@28\nrvfi_testbench.wrapper.dbus_cyc\nrvfi_testbench.wrapper.dbus_ack\nrvfi_testbench.wrapper.dbus_we\n@22\nrvfi_testbench.wrapper.dbus_adr[31:0]\nrvfi_testbench.wrapper.dbus_dat[31:0]\nrvfi_testbench.wrapper.dbus_sel[3:0]\nrvfi_testbench.wrapper.dbus_rdt[31:0]\n@200\n-\n-RVFI\n@28\nrvfi_testbench.wrapper.rvfi_valid\n@22\nrvfi_testbench.wrapper.rvfi_insn[31:0]\nrvfi_testbench.wrapper.rvfi_pc_rdata[31:0]\n@200\n-\n-\n[pattern_trace] 1\n[pattern_trace] 0\n"
  },
  {
    "path": "cores/serv/cover.sby",
    "content": "[options]\nmode cover\nappend 0\ntbtop wrapper.uut\ndepth 150\n\n[engines]\nsmtbmc boolector\n\n[script]\nread -sv defines.sv \\\n    cover.sv \\\n    wrapper.sv \\\n    sbram.sv \\\n    serv_bufreg.v \\\n    serv_bufreg2.v \\\n    serv_alu.v \\\n    serv_csr.v \\\n    serv_ctrl.v \\\n    serv_decode.v \\\n    serv_immdec.v \\\n    serv_mem_if.v \\\n    serv_rf_if.v \\\n    serv_rf_ram.v \\\n    serv_rf_ram_if.v \\\n    serv_state.v \\\n    serv_top.v \\\n    serv_rf_top.v\nprep -flatten -nordff -top testbench\n\n[files]\ncover.sv\nwrapper.sv\nsbram.sv\nserv-src/rtl/serv_bufreg.v\nserv-src/rtl/serv_bufreg2.v\nserv-src/rtl/serv_alu.v\nserv-src/rtl/serv_csr.v\nserv-src/rtl/serv_ctrl.v\nserv-src/rtl/serv_decode.v\nserv-src/rtl/serv_immdec.v\nserv-src/rtl/serv_mem_if.v\nserv-src/rtl/serv_rf_if.v\nserv-src/rtl/serv_rf_ram.v\nserv-src/rtl/serv_rf_ram_if.v\nserv-src/rtl/serv_state.v\nserv-src/rtl/serv_top.v\nserv-src/rtl/serv_rf_top.v\n../../checks/rvfi_macros.vh\n\n[file defines.sv]\n`define RISCV_FORMAL\n`define RISCV_FORMAL_NRET 1\n`define RISCV_FORMAL_XLEN 32\n`define RISCV_FORMAL_ILEN 32\n`define RISCV_FORMAL_RESET_CYCLES 1\n`define RISCV_FORMAL_CHECK_CYCLE 20\n`define RISCV_FORMAL_CHANNEL_IDX 0\n`define RISCV_FORMAL_CHECKER rvfi_insn_check\n`define RISCV_FORMAL_INSN_MODEL rvfi_insn_add\n`define RISCV_FORMAL_ALIGNED_MEM\n`define MEMIO_FAIRNESS\n`include \"rvfi_macros.vh\"\n"
  },
  {
    "path": "cores/serv/cover.sv",
    "content": "module testbench (\n\tinput clock,\n\tinput reset,\n\t`RVFI_OUTPUTS\n);\n\trvfi_wrapper wrapper (\n\t\t.clock(clock),\n\t\t.reset(reset),\n\t\t`RVFI_CONN\n\t);\n\n\tinteger cycle = 0;\n\talways @(posedge clock) cycle <= cycle + 1;\n\n\talways @(posedge clock) begin\n\t\tassume (reset == (cycle == 0));\n\t\tcover (rvfi_valid);\n\tend\nendmodule\n"
  },
  {
    "path": "cores/serv/disasm.py",
    "content": "#!/usr/bin/env python3\n\nfrom Verilog_VCD.Verilog_VCD import parse_vcd\nfrom os import system\nfrom sys import argv\n\nrvfi_valid = None\nrvfi_order = None\nrvfi_insn = None\n\nfor netinfo in parse_vcd(argv[1]).values():\n    for net in netinfo['nets']:\n        # print(net[\"hier\"], net[\"name\"])\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_valid\":\n            rvfi_valid = netinfo['tv']\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_order\":\n            rvfi_order = netinfo['tv']\n        if net[\"hier\"] == \"rvfi_testbench.wrapper\" and net[\"name\"] == \"rvfi_insn\":\n            rvfi_insn = netinfo['tv']\n\nassert len(rvfi_valid) == len(rvfi_order)\nassert len(rvfi_valid) == len(rvfi_insn)\n\nprog = list()\n\nfor tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn):\n    if tv_valid[1] == '1':\n        prog.append((int(tv_order[1], 2), int(tv_insn[1], 2)))\n\nwith open(\"disasm.s\", \"w\") as f:\n    for tv_order, tv_insn in sorted(prog):\n        if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0:\n            print(\".hword 0x%04x # %d\" % (tv_insn, tv_order), file=f)\n        else:\n            print(\".word 0x%08x # %d\" % (tv_insn, tv_order), file=f)\n\nsystem(\"riscv64-unknown-elf-gcc -c disasm.s\")\nsystem(\"riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o\")\n\n"
  },
  {
    "path": "cores/serv/generate.sh",
    "content": "#!/bin/bash\nset -ex\nrm -rf serv-src\ngit clone git@github.com:olofk/serv.git serv-src\npython3 ../../checks/genchecks.py\n"
  },
  {
    "path": "cores/serv/sbram.sv",
    "content": "// SiliconBlue RAM Cells\n\nmodule SB_RAM40_4K (\n\toutput [15:0] RDATA,\n\tinput         RCLK, RCLKE, RE,\n\tinput  [10:0] RADDR,\n\tinput         WCLK, WCLKE, WE,\n\tinput  [10:0] WADDR,\n\tinput  [15:0] MASK, WDATA\n);\n\t// MODE 0:  256 x 16\n\t// MODE 1:  512 x 8\n\t// MODE 2: 1024 x 4\n\t// MODE 3: 2048 x 2\n\tparameter WRITE_MODE = 0;\n\tparameter READ_MODE = 0;\n\n\tparameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\n`ifndef BLACKBOX\n\twire [15:0] WMASK_I;\n\twire [15:0] RMASK_I;\n\n\treg  [15:0] RDATA_I;\n\twire [15:0] WDATA_I;\n\n\tgenerate\n\t\tcase (WRITE_MODE)\n\t\t\t0: assign WMASK_I = MASK;\n\n\t\t\t1: assign WMASK_I = WADDR[   8] == 0 ? 16'b 1010_1010_1010_1010 :\n\t\t\t                    WADDR[   8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;\n\n\t\t\t2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :\n\t\t\t                    WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :\n\t\t\t                    WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :\n\t\t\t                    WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;\n\n\t\t\t3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :\n\t\t\t                    WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :\n\t\t\t                    WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :\n\t\t\t                    WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :\n\t\t\t                    WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :\n\t\t\t                    WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :\n\t\t\t                    WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :\n\t\t\t                    WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;\n\t\tendcase\n\n\t\tcase (READ_MODE)\n\t\t\t0: assign RMASK_I = 16'b 0000_0000_0000_0000;\n\n\t\t\t1: assign RMASK_I = RADDR[   8] == 0 ? 16'b 1010_1010_1010_1010 :\n\t\t\t                    RADDR[   8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;\n\n\t\t\t2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :\n\t\t\t                    RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :\n\t\t\t                    RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :\n\t\t\t                    RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;\n\n\t\t\t3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :\n\t\t\t                    RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :\n\t\t\t                    RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :\n\t\t\t                    RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :\n\t\t\t                    RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :\n\t\t\t                    RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :\n\t\t\t                    RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :\n\t\t\t                    RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;\n\t\tendcase\n\n\t\tcase (WRITE_MODE)\n\t\t\t0: assign WDATA_I = WDATA;\n\n\t\t\t1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],\n\t\t\t                     WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],\n\t\t\t                     WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],\n\t\t\t                     WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};\n\n\t\t\t2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],\n\t\t\t                     WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],\n\t\t\t                     WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],\n\t\t\t                     WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};\n\n\t\t\t3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],\n\t\t\t                     WDATA[11], WDATA[11], WDATA[11], WDATA[11],\n\t\t\t                     WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],\n\t\t\t                     WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};\n\t\tendcase\n\n\t\tcase (READ_MODE)\n\t\t\t0: assign RDATA = RDATA_I;\n\t\t\t1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],\n\t\t\t                   1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};\n\t\t\t2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};\n\t\t\t3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};\n\t\tendcase\n\tendgenerate\n\n\tinteger i;\n\treg [15:0] memory [0:255];\n\n\tinitial begin\n\t\tfor (i=0; i<16; i=i+1) begin\n\t\t\tmemory[ 0*16 + i] <= INIT_0[16*i +: 16];\n\t\t\tmemory[ 1*16 + i] <= INIT_1[16*i +: 16];\n\t\t\tmemory[ 2*16 + i] <= INIT_2[16*i +: 16];\n\t\t\tmemory[ 3*16 + i] <= INIT_3[16*i +: 16];\n\t\t\tmemory[ 4*16 + i] <= INIT_4[16*i +: 16];\n\t\t\tmemory[ 5*16 + i] <= INIT_5[16*i +: 16];\n\t\t\tmemory[ 6*16 + i] <= INIT_6[16*i +: 16];\n\t\t\tmemory[ 7*16 + i] <= INIT_7[16*i +: 16];\n\t\t\tmemory[ 8*16 + i] <= INIT_8[16*i +: 16];\n\t\t\tmemory[ 9*16 + i] <= INIT_9[16*i +: 16];\n\t\t\tmemory[10*16 + i] <= INIT_A[16*i +: 16];\n\t\t\tmemory[11*16 + i] <= INIT_B[16*i +: 16];\n\t\t\tmemory[12*16 + i] <= INIT_C[16*i +: 16];\n\t\t\tmemory[13*16 + i] <= INIT_D[16*i +: 16];\n\t\t\tmemory[14*16 + i] <= INIT_E[16*i +: 16];\n\t\t\tmemory[15*16 + i] <= INIT_F[16*i +: 16];\n\t\tend\n\tend\n\n\talways @(posedge WCLK) begin\n\t\tif (WE && WCLKE) begin\n\t\t\tif (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];\n\t\t\tif (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];\n\t\t\tif (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];\n\t\t\tif (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];\n\t\t\tif (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];\n\t\t\tif (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];\n\t\t\tif (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];\n\t\t\tif (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];\n\t\t\tif (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];\n\t\t\tif (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];\n\t\t\tif (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];\n\t\t\tif (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];\n\t\t\tif (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];\n\t\t\tif (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];\n\t\t\tif (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];\n\t\t\tif (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];\n\t\tend\n\tend\n\n\talways @(posedge RCLK) begin\n\t\tif (RE && RCLKE) begin\n\t\t\tRDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;\n\t\tend\n\tend\n`endif\nendmodule\n\nmodule SB_RAM40_4KNR (\n\toutput [15:0] RDATA,\n\tinput         RCLKN, RCLKE, RE,\n\tinput  [10:0] RADDR,\n\tinput         WCLK, WCLKE, WE,\n\tinput  [10:0] WADDR,\n\tinput  [15:0] MASK, WDATA\n);\n\tparameter WRITE_MODE = 0;\n\tparameter READ_MODE = 0;\n\n\tparameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\n\tSB_RAM40_4K #(\n\t\t.WRITE_MODE(WRITE_MODE),\n\t\t.READ_MODE (READ_MODE ),\n\t\t.INIT_0    (INIT_0    ),\n\t\t.INIT_1    (INIT_1    ),\n\t\t.INIT_2    (INIT_2    ),\n\t\t.INIT_3    (INIT_3    ),\n\t\t.INIT_4    (INIT_4    ),\n\t\t.INIT_5    (INIT_5    ),\n\t\t.INIT_6    (INIT_6    ),\n\t\t.INIT_7    (INIT_7    ),\n\t\t.INIT_8    (INIT_8    ),\n\t\t.INIT_9    (INIT_9    ),\n\t\t.INIT_A    (INIT_A    ),\n\t\t.INIT_B    (INIT_B    ),\n\t\t.INIT_C    (INIT_C    ),\n\t\t.INIT_D    (INIT_D    ),\n\t\t.INIT_E    (INIT_E    ),\n\t\t.INIT_F    (INIT_F    )\n\t) RAM (\n\t\t.RDATA(RDATA),\n\t\t.RCLK (~RCLKN),\n\t\t.RCLKE(RCLKE),\n\t\t.RE   (RE   ),\n\t\t.RADDR(RADDR),\n\t\t.WCLK (WCLK ),\n\t\t.WCLKE(WCLKE),\n\t\t.WE   (WE   ),\n\t\t.WADDR(WADDR),\n\t\t.MASK (MASK ),\n\t\t.WDATA(WDATA)\n\t);\nendmodule\n\nmodule SB_RAM40_4KNW (\n\toutput [15:0] RDATA,\n\tinput         RCLK, RCLKE, RE,\n\tinput  [10:0] RADDR,\n\tinput         WCLKN, WCLKE, WE,\n\tinput  [10:0] WADDR,\n\tinput  [15:0] MASK, WDATA\n);\n\tparameter WRITE_MODE = 0;\n\tparameter READ_MODE = 0;\n\n\tparameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\n\tSB_RAM40_4K #(\n\t\t.WRITE_MODE(WRITE_MODE),\n\t\t.READ_MODE (READ_MODE ),\n\t\t.INIT_0    (INIT_0    ),\n\t\t.INIT_1    (INIT_1    ),\n\t\t.INIT_2    (INIT_2    ),\n\t\t.INIT_3    (INIT_3    ),\n\t\t.INIT_4    (INIT_4    ),\n\t\t.INIT_5    (INIT_5    ),\n\t\t.INIT_6    (INIT_6    ),\n\t\t.INIT_7    (INIT_7    ),\n\t\t.INIT_8    (INIT_8    ),\n\t\t.INIT_9    (INIT_9    ),\n\t\t.INIT_A    (INIT_A    ),\n\t\t.INIT_B    (INIT_B    ),\n\t\t.INIT_C    (INIT_C    ),\n\t\t.INIT_D    (INIT_D    ),\n\t\t.INIT_E    (INIT_E    ),\n\t\t.INIT_F    (INIT_F    )\n\t) RAM (\n\t\t.RDATA(RDATA),\n\t\t.RCLK (RCLK ),\n\t\t.RCLKE(RCLKE),\n\t\t.RE   (RE   ),\n\t\t.RADDR(RADDR),\n\t\t.WCLK (~WCLKN),\n\t\t.WCLKE(WCLKE),\n\t\t.WE   (WE   ),\n\t\t.WADDR(WADDR),\n\t\t.MASK (MASK ),\n\t\t.WDATA(WDATA)\n\t);\nendmodule\n\nmodule SB_RAM40_4KNRNW (\n\toutput [15:0] RDATA,\n\tinput         RCLKN, RCLKE, RE,\n\tinput  [10:0] RADDR,\n\tinput         WCLKN, WCLKE, WE,\n\tinput  [10:0] WADDR,\n\tinput  [15:0] MASK, WDATA\n);\n\tparameter WRITE_MODE = 0;\n\tparameter READ_MODE = 0;\n\n\tparameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\tparameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\n\n\tSB_RAM40_4K #(\n\t\t.WRITE_MODE(WRITE_MODE),\n\t\t.READ_MODE (READ_MODE ),\n\t\t.INIT_0    (INIT_0    ),\n\t\t.INIT_1    (INIT_1    ),\n\t\t.INIT_2    (INIT_2    ),\n\t\t.INIT_3    (INIT_3    ),\n\t\t.INIT_4    (INIT_4    ),\n\t\t.INIT_5    (INIT_5    ),\n\t\t.INIT_6    (INIT_6    ),\n\t\t.INIT_7    (INIT_7    ),\n\t\t.INIT_8    (INIT_8    ),\n\t\t.INIT_9    (INIT_9    ),\n\t\t.INIT_A    (INIT_A    ),\n\t\t.INIT_B    (INIT_B    ),\n\t\t.INIT_C    (INIT_C    ),\n\t\t.INIT_D    (INIT_D    ),\n\t\t.INIT_E    (INIT_E    ),\n\t\t.INIT_F    (INIT_F    )\n\t) RAM (\n\t\t.RDATA(RDATA),\n\t\t.RCLK (~RCLKN),\n\t\t.RCLKE(RCLKE),\n\t\t.RE   (RE   ),\n\t\t.RADDR(RADDR),\n\t\t.WCLK (~WCLKN),\n\t\t.WCLKE(WCLKE),\n\t\t.WE   (WE   ),\n\t\t.WADDR(WADDR),\n\t\t.MASK (MASK ),\n\t\t.WDATA(WDATA)\n\t);\nendmodule\n"
  },
  {
    "path": "cores/serv/wrapper.sv",
    "content": "module rvfi_wrapper (\n\tinput clock,\n\tinput reset,\n\t`RVFI_OUTPUTS\n);\n\t// I-MEM\n\t(* keep *)      wire [31:0] ibus_adr;\n\t(* keep *)      wire        ibus_cyc;\n\t(* keep *) rand reg  [31:0] ibus_rdt;\n\t(* keep *) rand reg         ibus_ack;\n\n\t// D-MEM\n\t(* keep *)      wire [31:0] dbus_adr;\n\t(* keep *)      wire [31:0] dbus_dat;\n\t(* keep *)      wire [3:0]  dbus_sel;\n\t(* keep *)      wire        dbus_we;\n\t(* keep *)      wire        dbus_cyc;\n\t(* keep *) rand reg  [31:0] dbus_rdt;\n\t(* keep *) rand reg         dbus_ack;\n\n\tserv_rf_top uut (\n\t\t.clk(clock),\n\t\t.i_rst(reset),\n\t\t.i_timer_irq(1'b0),\n\n\t\t`RVFI_CONN,\n\n\t\t.o_ibus_adr(ibus_adr),\n\t\t.o_ibus_cyc(ibus_cyc),\n\t\t.i_ibus_rdt(ibus_rdt),\n\t\t.i_ibus_ack(ibus_ack),\n\t\t.o_dbus_adr(dbus_adr),\n\t\t.o_dbus_dat(dbus_dat),\n\t\t.o_dbus_sel(dbus_sel),\n\t\t.o_dbus_we (dbus_we ),\n\t\t.o_dbus_cyc(dbus_cyc),\n\t\t.i_dbus_rdt(dbus_rdt),\n\t\t.i_dbus_ack(dbus_ack)\n\t);\n\n\t// I-MEM\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tassume (!ibus_ack);\n\t\tend\n\t\tif (!ibus_cyc) begin\n\t\t\tassume (!ibus_ack);\n\t\tend\n\tend\n\n\t// D-MEM\n\talways @(posedge clock) begin\n\t\tif (reset) begin\n\t\t\tassume (!dbus_ack);\n\t\tend\n\t\tif (!dbus_cyc) begin\n\t\t\tassume (!dbus_ack);\n\t\tend\n\tend\n\n`ifdef MEMIO_FAIRNESS\n\treg [3:0] timeout_ibus = 0;\n\treg [3:0] timeout_dbus = 0;\n\n\talways @(posedge clock) begin\n\t\ttimeout_ibus <= 0;\n\t\ttimeout_dbus <= 0;\n\n\t\tif (ibus_cyc && !ibus_ack)\n\t\t\ttimeout_ibus <= timeout_ibus + 1;\n\n\t\tif (dbus_cyc && !dbus_ack)\n\t\t\ttimeout_dbus <= timeout_dbus + 1;\n\n\t\tassume (!timeout_ibus[3]);\n\t\tassume (!timeout_dbus[3]);\n\tend\n`endif\nendmodule\n"
  },
  {
    "path": "docs/config.md",
    "content": "\nRISCV-FORMAL Configuration Macros\n=================================\n\nThe riscv-formal insn models and checkers are configured using a few Verilog\npre-processor macros. They must be defined bofore reading any riscv-formal\nverilog files. The first riscv-formal verilog file read after defining the\nmacros must be [rvfi_macros.vh](../checks/rvfi_macros.vh).\n\nExample configuration:\n\n    `define RISCV_FORMAL\n    `define RISCV_FORMAL_NRET 1\n    `define RISCV_FORMAL_XLEN 32\n    `define RISCV_FORMAL_ILEN 32\n    `define RISCV_FORMAL_COMPRESSED\n    `define RISCV_FORMAL_ALIGNED_MEM\n\nThe macros in this section must be defined by the user where relevant, while the next section\nincludes additional macros which may be automatically generated depending on configuration. Defining\n`RISCV_FORMAL`, `RISCV_FORMAL_NRET`, `RISCV_FORMAL_XLEN`, and `RISCV_FORMAL_ILEN` is mandatory if\n`genchecks.py` is not being used.\n\nRISCV_FORMAL_UMODE\n------------------\n\nThis macro must be defined when the core under tests supports U-mode.\n\nRISCV_FORMAL_SMODE\n------------------\n\nThis macro must be defined when the core under tests supports S-mode.\n\nRISCV_FORMAL_ALTOPS\n-------------------\n\nThis macro must be defined if the core under tests implements [alternative arithmetic semantic](https://github.com/YosysHQ/riscv-formal/blob/master/docs/rvfi.md#alternative-arithmetic-operations).\n\nRISCV_FORMAL_ALIGNED_MEM\n------------------------\n\nCores that only have hardware support for word-aligned memory access may choose\nto retire memory load/store operations for smaller units (half-words, bytes)\nword aligned with the appropiate `rmask/wmask` values to select the correct\nbytes. In this case the `RISCV_FORMAL_ALIGNED_MEM` macro must be defined.\n\nRISCV_FORMAL_VALIDADDR(addr)\n----------------------------\n\nSet this to an expression of `addr` that evaluates to 1 when the given address is a valid physical\naddress for the processor under test.  If not defined this expression will always evaluate to true.\n\nRISCV_FORMAL_VALIDHPMEVENT(event)\n---------------------------------\n\nSet this to an expression of `event` that evaluates to 1 when the given event is a valid assignment\nfor a hpmevent CSR.  If not defined this expression will always evaluate to true.\n\nRISCV_FORMAL_IOADDR(addr)\n-------------------------\n\nSet this to an expression of `addr` that evaluates to 1 when the given address belongs to an i/o\nmemory region.  If not defined this expression will always evaluate to true.\n\nRISCV_FORMAL_WAITINSN(insn)\n---------------------------\n\nSet this to an expression of `insn` that evaluates to 1 when the given instruction\nis a wait instruction similar to WFI. (WFI does not need to be recognized by the\nexpression. This is for non-standard instructions in addition to WFI.)\n\nRISCV_FORMAL_PMA_MAP\n--------------------\n\nSet this to the name of a module that takes an address as input and outputs\nthe PMA info for that address. The exact interface of such a module is not\nentirely defined yet.\n\nTestbench Macros\n================\n\nThe following macros are all defined automatically when using `genchecks.py`.  If tests are being\nperformed manually without the generated framework, some of these macros may be required to be\ndefined by the user prior to loading the testbench.  Additional information may be found in the\n[configuring check generation section](procedure.md#Configuring-Check-Generation) of the procedure\ndocument.\n\nRISCV_FORMAL\n------------\n\nThis macro is set whenever riscv-formal is used.  It is actually never used by any of the\nriscv-formal Verilog files, but can be used by cores under test to enable or disable generation of\nthe RVFI ports.\n\nRISCV_FORMAL_NRET\n-----------------\n\nThe number of channels for the RVFI port (and thus the theoretical maximum number of instructions\nthe core can retire via RVFI in one cycle).  The value of this macro can be set by providing the `nret` option in the check config.\n\nRISCV_FORMAL_XLEN\n-----------------\n\nThe width of integer registers in the ISA implemented by the core under test.  Valid values are 32,\n64, and 128.  Only 32 is fully supported at the moment.  `genchecks.py` will define this as 32,\nunless the `isa` string in the options contains rv64.\n\nRISCV_FORMAL_ILEN\n-----------------\n\nThe maximum width of an instruction retired by the core.  For cores supporting fused instructions\nthis is the maximum length of a complete fused instruction.  There is currently no way to\nautomatically generate tests with a value other than 32.\n\nRISCV_FORMAL_COMPRESSED\n-----------------------\n\nFor cores supporting the RISC-V Compressed ISA this define must be set.  This will be automatically defined if the `c` extension appears in the `isa` string.\n\nRISCV_FORMAL_BLACKBOX_REGS\n--------------------------\n\nWhen checking for correct implementation of the RISC-V instructions (\"insncheck\") it is possible to\nblack-box the processor register file.  This macro may be used in the core under test to black-box\nthe register file.  Controlled by the presence or absence of the `blackbox` option.\n\nRISCV_FORMAL_BLACKBOX_ALU\n-------------------------\n\nWhen checking for consistency of the stream of retired instructions (such as \"regcheck\") it is\npossible to black-box the actual ALU operations.  This macro may be used in the core under test to\nblack-box the ALU.  Controlled by the presence or absence of the `blackbox` option.\n\nRISCV_FORMAL_FAIRNESS\n---------------------\n\nWhen checking for liveness of the core, then the peripherals and abstractions used in the check must\nguarantee fairness.  This macro should be tested by the peripherals and abstractions to decide if\nfairness guarantees should be enabled.  Automatically defined for `liveness` and `hang` checks.\n\nRISCV_FORMAL_RESET_CYCLES\n-------------------------\n\nThe number of cycles to hold reset high for at the start of the model checking.\n\nRISCV_FORMAL_CHECK_CYCLE\n------------------------\n\nThe cycle number in which checks will be performed.  For bounded model checking, this should be the\nsolver depth.\n\nRISCV_FORMAL_TRIG_CYCLE\n-----------------------\n\nThe cycle number in which to trigger some check specific action.\n\nRISCV_FORMAL_CHANNEL_IDX\n------------------------\n\nFor checks which only operate on a single channel, this macro defines which channel is being\nchecked.\n\nRISCV_FORMAL_CHECKER\n--------------------\n\nThe name of the module to be instantiated by the testbench for formal verification. e.g.\n`rvfi_csrw_check`.\n\nRISCV_FORMAL_ASSUME\n-------------------\n\nIndicates that the `assume_stmts.vh` file should be included in the testbench.  This file is\nexpected to contain a series of SV assumptions that the solver should make.\n\nRISCV_FORMAL_UNBOUNDED\n----------------------\n\nThis macro is used to indicate that unbounded model checking is being used.\n\nRISCV_FORMAL_CSR_<CSRNAME>\n--------------------------\n\nEach CSR being connected over the RVFI interface should be defined with one of these macros. Refer\nto the [RVFI Interface Specification for CSRs](rvfi.md#Control-and-Status-Registers-(CSRs)) for more\ndetails on how this name is used.\n\nRISCV_FORMAL_CSRW_NAME\n----------------------\n\nThis macro defines the name of the CSR under test during `csrw` checks.\n\nRISCV_FORMAL_CSRWH\n------------------\n\nThis macro is used in the `csrw` checks to indicate that the current CSR consists of two registers,\nwith the second being of the same name but appended with 'h'.\n\nRISCV_FORMAL_INSN_MODEL\n-----------------------\n\nWhen performing `insn` checks, this is the name of the module for the current instruction. e.g.\n`rvfi_insn_add`.\n\nMacros defined by rvfi_macros.vh\n================================\n\nThe Verilog file `rvfi_macros.vh` defines a few useful helper macros.\n\nRVFI_WIRES, RVFI_OUTPUTS, RVFI_INPUTS, RVFI_CONN\n------------------------------------------------\n\nMacros to declare wires, output ports, or input ports for all `rvfi_*` signals. The last\nmacro is for creating the proper connections on module instances. This macros can be\nuseful for routing the `rvfi_*` signals through the design hierarchy.\n\nrvformal_rand_reg and rvformal_rand_const_reg\n---------------------------------------------\n\nMacros for defining unconstrained signals (`rvformal_rand_reg`) or constant signals with\nan unconstrained initial value (`rvformal_rand_const_reg`).\n\nUsage example:\n\n    `rvformal_rand_reg [7:0] anyseq;\n    `rvformal_rand_const_reg [7:0] anyconst;\n\nFor formal verification with Yosys (i.e. when `YOSYS` is defined), this will be\nconverted to the following code:\n\n    rand reg [7:0] anyseq;\n    rand const reg [7:0] anyconst;\n\nFor simulation (i.e. when `SIMULATION` is defined), this will be converted to:\n\n    reg [7:0] anyseq;\n    reg [7:0] anyconst;\n\nAnd otherwise (for use with any formal verification tool):\n\n    wire [7:0] anyseq;\n    reg [7:0] anyconst;\n\n"
  },
  {
    "path": "docs/csrs.md",
    "content": "RISC-V Formal CSR Sematics\n==========================\n\nFor the most part the CSR values output via RVFI match exactly the CSR values\nobservable via the ISA. But there are a few minor differences that are outlined\nhere.\n\nMost importantly, for RV64 processors in RV32 mode, the values output via\nRVFI are still following RV64 CSR encondings, including some of the information\nthat is not available through the RV32 ISA, such as SXL and UXL in `mstatus`.\n\nCounters are always output as singe 64-bit wide CSRs even on RV32 targets.\n\nM-mode CSRs\n-----------\n\n### Machine Information Registers\n\n#### mvendorid, marchid, mimpid, mhartid, mconfigptr\n\nThese CSRs are mandatory and expected to be constant, but may be all 0.\n\n### Machine Trap Setup\n\n#### mstatus\n\nMandatory. (Reminder: RV64 processors in RV32 mode are expected to output the\nRV64 format.)\nMay be all 0, reserved bits must be 0 regardless of writes.\n\n#### misa\n\nCan be read-only 0, but existence is mandatory.  Reserved bits must be 0\nregardless of writes.\n\n#### medeleg, mideleg\n\nOnly exist if S mode is supported.\n\n#### mie, mtvec\n\nMandatory.\n\n#### mcounteren\n\nCurrently only the `IR` and `CY` bits of `mcounteren` are supported by\nriscv-formal. The other bits are ignored.\nmcounteren must only exist if U mode is supported.\n\n### Machine Trap Handling\n\n#### mscratch\n\nNothing special for this CSR.\n\n#### mepc\n\nThe version of `mepc` observable through the ISA masks `mepc[1]` on CSR reads\nwhen the processor is in a mode that does not supprt 16-bit instruction\nalignment.  However, writes to that bit shall still modify the underlying\narchitectural state.\n\nIn riscv-formal semantics the `mepc` value output via RVFI must be the actual\narchitectural state with `mepc[1]` not masked.\n\n#### mcause, mtval, mip\n\nNothing special for these CSRs.\n\n### Machine Protection and Translation\n\nTBD\n\n### Machine Counter/Timers\n\n#### mcycle, minstret\n\nAlways 64-bit wide, even on pure RV32 processors (no mcycleh/minstreth).\n\nIncrementing those counters should happen \"between instructions\", this means\nfor example that an instruction that isn't a CSR write to `mcycle` should\nalways have `rvfi_csr_mcycle_rdata == rvfi_csr_mcycle_wdata`.\n\n#### mhpmcounter<N>, mhpmevent<N>\n\nMachine performance-monitoring counters are currently not supported by riscv-formal.\n\n### CSR 0xFFF\n\nThis address is used as a catch-all to mean no address and thus is not able to be tested normally.\n\nDebug-Mode CSRs\n---------------\n\nTBD\n\nU-Mode CSRs\n-----------\n\nTBD\n\nS-Mode CSRs\n-----------\n\nTBD\n"
  },
  {
    "path": "docs/examplebugs.md",
    "content": "\nExamples of bugs found by riscv-formal\n======================================\n\nThis page lists a few examples of common types of bugs found by riscv-formal.\n\nThis page is intentionally a bit vague on the details. Its purpose is to give\nreaders an idea of what kind of bugs can be found with riscv-formal, not to\npillory implementations for long fixed bugs.\n\nInstruction Semantics\n---------------------\n\nSome parts of the instruction semantics are easy to get wrong and are not\ntested very well by standard test-benches like riscv-torture or booting a linux\nkernel.\n\n### Reserved C-extension opcodes and hint instructions\n\nThe C-extension opcode map contains several reserved opcodes (that should\ntrigger an illegal instruction trap) and hint instructions (that should be\ntreated as NOPs). Some implementations get some of those opcodes wrong, and\nriscv-formal has found bugs like this.\n\nThere were even instances of implementations that fixed issues like that, and\nthen later reversed the fixes because someone looking over the code misread the\nstandard and thought they would fix a bug but instead they re-introduced one. A\ngood example why one should not only verify their implementation once, but\ncontinuously keep verifying it as long as changes are made to the design, even\nin cases where those changes are considered \"only trivial minor changes\".\n\n### JALR clears LSB after addition\n\nThe JALR instruction adds an immediate to its source register, clears the LSB\nof the sum, and then jumps to the resulting address. (It also stores the\naddress of the next instruction in the desitination register.)\n\nThe code C compilers generate usually (always?) have the LSB of the sum already cleared, so\na bug in an implementation where the LSB is not cleared by the instruction (but, for example, an\ninstruction address misaligned trap is triggered instead) is usually not\ndiscovered by just running compiler-generated code. With riscv-formal I have\nfound this exact bug in several implementations.\n\nTroubles with bypassing and forwarding\n--------------------------------------\n\nIn pipelined architectures bypassing and forwarding are used to avoid pipeline\nstalls. Bugs in bypassing and forwarding often are only triggered by a specific\nsequence of instructions, combined with just the right (wrong?) timing for\nexternal events (such as completion of a memory operation). I have found several\nbugs like this with riscv-formal.\n\nIssues with reset\n-----------------\n\nReset issues can be incredibly hard to find using simulation. One\nimplementation had a reset problem in the divider so that one could start a\ndivision, then reset the processor while the divide is in flight, and then\ndivide again as one of the first instructions after reset. If the timing was\njust right then this second division would return immediately, with the result\nof the divide that was launched before the reset.\n\nWeird and bizarre programs\n--------------------------\n\nSome assembler code snippets are so bizarre that rarely someone writes a test\nfor them. But a proper implementation of RISC-V should of course still cope\nwith those cases correctly.\n\n### Disabling the C ISA extension while not 32-bit aligned\n\nOn a processor that supports it, one can enable or disable individual ISA\nextensions by writing to the `misa` CSR. Disabling the C extension in an\ninstruction that isn't aligned to a 32-bit word should cause the processor to\ntrigger an instruction address misaligned trap for the next instruction. One\nprocessor had a bug so that when the next instruction was a load, that load was\nnot killed properly and then caused some strange effects when the load\nfinally completed.\n\nNoteworthy about this case is that disabling the C ISA extension while not\n32-bit aligned is not sufficient to reproduce the bug. Instead this CSR write\nmust be combined with a load instruction that should be killed by the trap, and\nthen it must be checked if the destination register of that load changes at a\nlater time (when the not-properly-killed load finishes).\n\n"
  },
  {
    "path": "docs/procedure.md",
    "content": "\nriscv-formal Verification Procedure\n===================================\n\nThe following formal test are performed to verify ISA compliance of RISC-V processors with `riscv-formal`. Depending on aspects like the strength of safety properties present in the core, the overall complexity of the core, and the verification requirements for the given application, the following tests might be set up as bounded model checks or as unbounded verification tasks.\n\nFor most cores the easiest approach is to create a wrapper HDL module and a `checks.cfg` file and\nuse the `genchecks.py` scripts to create the formal checks.  See\n[cores/picorv32/](../cores/picorv32/) for an example implementation.  The checks generated by\n`genchecks.py` are bounded model checks which use sby for verification.\n\nConfiguring Check Generation\n----------------------------\n\nA config file with extension `.cfg` is used to configure the `genchecks.py` script.  By default, the\nname of this config file is expected to be `checks`.  Calling `genchecks.py` with an argument will\ninstead use the provided name.  For example, `python3 ../../checks/genchecks.py tests` will load\nconfig settings from a file named `tests.cfg`.  Note that the script will generate a folder with the\nsame config name in the directory it is run.\n\nIt is expected for `genchecks.py` to be called from a subdirectory of the `cores` folder, such that\nthe script is called as `../../checks/genchecks.py`, and the subdirectory is the name of the core.\nThis core name will be used for naming certain intermediary files, but is otherwise arbitrary and\ndoes not need to match anything else.\n\nThe config file consists of a number of sections, with each section starting with the name of the\nsection in square brackets.  Some of these sections are shared between tests, and some are used only\nfor specific formal checks.  The shared sections will be covered here, while check specific details\nwill be covered in the relevant section below.\n\nComments can be included in the config file by prefixing a line with a `#` character.\n\n#### `[options]`\n\nThis section primarily contains options which describe the core under test.  Possible options are\nlisted below, along with their expected value.  For options with no expected value, simply including\nthe option enables the specified effect.\n\n| Option   | Value   | Description |\n| -------- | ------- | ----------- |\n| isa      | String  | ISA extensions, e.g. `RV64IMAFD`, or `rv32i`.  Note that X and Z extensions are not currently supported and should be removed from the string. |\n| nret     | Integer | The number of channels for the RVFI port.  Defaults to 1. |\n| blackbox | None    | Signifies register file and ALU should be black-boxed. |\n| solver   | String  | Name of solver, defaults to `boolector`. |\n| dumpsmt2 | None    | Passed to `smtbmc` engine to output SMT2 trace. |\n| abspath  | None    | Generated makefile will use absolute path of generated files. |\n| mode     | String  | Solver mode, currently supports either `bmc` or `prove`, and defaults to `bmc`. |\n\n#### `[depth]`\n\nThis section provides the execution depth to be used by the solver for each test.  The name of the\ncheck is listed, followed by one or more integers separated by a space.  For formal checks that\nexpect multiple values to be provided here, the meaning of each will be defined in the relevant\nsection.\n\nFor cores with multiple channels, the channel number can be used in the name of the check by\nappending `_ch#`.  Note that a more specific name will be used over a less specific name.  For\nexample, if `insn <depth0>` and `insn_ch1 <depth1>` are both listed, `insn` tests on channel 1 will\nuse `depth1`, while all other channels will use `depth0`.\n\nIf a formal check does not have a corresponding depth listed, it will not be generated.  For\nexample, providing `reg_ch2 <values>` but not `reg <values>` will run the `reg` check *only* on\nchannel 2.\n\n#### `[groups]`\n\nThis section defines a list of group names which are prepended to all check names which can then be\nused for grouping multiple checks together.  These groups can then be used for testing with multiple\ndepth values.  Each group must be separated by whitespace.\n\nAs an example, if groups `a` and `b` are listed with depth settings of `a_insn <x>`, \n`b_insn_bne <y>`, then all instructions will be tested with depth `x`, and the `bne` instruction\nwill be tested to both depths `x` and `y`.\n\n#### `[sort]`\n\nIf this section is included, any listed checks will be run in the order they appear in this list,\nand will be run *before* any un-listed checks.  Each item should be placed on its own line.  When\nmultiple checks match the same ordering, alphabetical order will be used.  \n\nNote that regex is used to search for a match of the *full* check name, including group and channel.\nThis can be used to, for example, list all checks on channel 2 before any others by adding `.*?_ch2`\nas the first item.  If the user is unfamiliar with regex, simply providing the names of checks\nverbatim will also work.\n\nNote that this sorting also determines the order in which checks are generated in the makefile.  The\norder in which tests are started should be maintained by Make, however if parallelism is enabled\nthen there is no guarantee that tests will *complete* in this order.\n\n#### `[filter-checks]`\n\nSpecific checks can be enabled or disabled by adding them to this section prefixed with either a `+`\nor `-` and a space.  As with `[sort]` above, regex is used for matching against each line.  Note\nthat the *first* match returns.  For example, if `+ insn_(mul|div)_ch1` is listed before \n`- insn_.*_ch1`, then the `mul` and `div` instructions will be enabled for testing on channel 1, \nwhile all other instructions are disabled.\n\n#### `[assume]`\n\nEach line of this section provides a two value tuple.  The first value is the regex pattern used to\nmatch the current check name, while the second value is code to be included in the file\n`assume_stmts.vh`.  If the first value begins with a `!`, the code is used for all checks that *do\nnot* match the pattern, otherwise the code is used for all checks that *do* match.  This file is\nincluded verbatim at the end of the `rvfi_testbench` module in\n[checks/rvfi_testbench.sv](../checks/rvfi_testbench.sv), and so should be valid System Verilog code.\n\n### Verbatim sections\n\nA number of sections are included in the sby script essentially as-is.  These sections are formatted\nwith a few keyword substitutions.  If using these substitutions, the keywords should be prepended\nand appended with a `@` symbol, e.g. `@basedir@/cores/@core@/wrapper.sv` is using the `basedir` and\n`core` keywords to define the path.\n\nPossible keywords include:\n\n- basedir: the root directory of riscv-formal\n- core: the name of the directory from which the script is executed\n- ilang_file: filename of intermediary output\n- channel: the current rvfi channel\n- check: the current check, e.g. `csrc`\n- checkch: the full name of the current check, e.g. `a_csrc_misa_ch0`\n\n#### `[script-defines]`\n\nThis section is included at the *start* of the sby `[script]` section.  Check specific code can also\nbe included as `[script-defines <check>]`, where `<check>` is the current check.\n\n#### `[verilog-files]` and `[vhdl-files]`\n\nThese sections list all of the core source files which should be included in testing.  All verilog files will be listed after `read -sv `, while all vhdl files will be listed after `read -vhdl`.\n\n#### `[script-sources]`\n\nThis section can be used to add any other source files which do not fit under `-sv` or `-vhdl`, and is included *before* the `prep` command.\n\n#### `[script-link]`\n\nThis section is included *after* the `prep` command and *before* `chformal`.\n\n#### `[defines]`\n\nThis section is included as part of `[file defines.sv]`.  Check specific code can also be included\nas `[defines <check>]`, where `<check>` is the current check.\n\nStandard Checks\n---------------\n\nThe following checks are managed by `genchecks.py` and can be implemented using the standard RVFI wrapper interface.\n\n### Instruction Checks\n\nThe majority of formal checks needed to verify a core with riscv-formal are instruction checks (one per RVFI channel and RISC-V instruction supported by the core).\n\nInstruction checks test if the instruction (`rvfi_insn`) matches the state transistion described by the other RVFI signals.\n\n### PC Checks\n\nThere are two PC checks: `pc_fwd` and `pc_bwd`. Both of them are run for each RVFI channel.\n\nThe `pc_fwd` check assumes that the core retires an instruction at the end of the bounded model check, and that the previous instruction in the program (`rvfi_order-1`) was retired earlier. It then tests if `rvfi_pc_wdata` of the previous instruction matches `rvfi_pc_rdata` of the next instruction.\n\n`pc_bwd` is like `pc_fwd` but for pairs of instructions that have been executed out of order: The check assumes that the core retires an instruction at the end of the bounded model check, and that the next instruction in the program (`rvfi_order+1`) was retired earlier. It then tests if `rvfi_pc_wdata` of the previous instruction matches `rvfi_pc_rdata` of the next instruction.\n\n#### `[depth]` section\n\nExpects two values: first is the number of cycles to reset for; second is the execution depth.\n\n### Register Checks\n\nThis checks if writes to and reads from the register file are consistent with each other, i.e. if the value written to a register matches the value read from the register file by a later instructions.\n\nThis check assumes that the last instruction at the end of the bounded model check, reads a register. It then checks that the value read is consistent with the matching write to the same register by an earlier instruction.\n\n#### `[depth]` section\n\nExpects two values: first is the number of cycles to reset for; second is the execution depth.\n\n### Causality\n\nThere are three causality checks: `causal`, `causal_mem` and `causal_io`.\n\nThe core may retire instructions out-of-order as long as causality is preserved. (This means a write must be retired before the reads that depend on it.)\n\nThe `causal` check tests if the instruction stream is causal with respect to registers.\nThe `causal_mem` check tests if the instruction stream is causal with respect to memory.\nThe `causal_io` check tests if the instruction stream is causal with respect to i/o memory, where every i/o memory access is assumed to depend on all earlier i/o memory accesses.\n\nWhich areas of the adress space are considered to be i/o memory can be configured using the RISCV_FORMAL_IOADDR(addr) macro.\n\n#### `[depth]` section\n\nExpects two values: first is the number of cycles to reset for; second is the execution depth.\n\n#### `[depth]` section\n\nExpects two values: first is the number of cycles to reset for; second is the execution depth.\n\n### Liveness\n\nThis check makes sure that the core never freezes (unless an instruction with `rvfi_halt` asserted is retired): This check assumes that an instruction is retired at a configurable trigger point in the middle of the bounded model check. It then checks that the next instruction (`rvfi_order+1`) is also retired at some point during the span of the bounded model check.\n\nIt might be neccessary to add some bounded fairness constraints to the design for this check to succeed.\n\n#### `[depth]` section\n\nExpects three values: first is the number of cycles to reset for; second is the trigger depth; and\nthird is the execution depth.\n\n### Uniqueness\n\nThis check makes sure that no two instructions with the same `rvfi_order` are retired by the core.\n\n#### `[depth]` section\n\nExpects three values: first is the number of cycles to reset for; second is the trigger depth; and\nthird is the execution depth.\n\n### Faults\n\nThis check makes sure that dynamically occuring memory faults are handled. It requires defining `RISCV_FORMAL_MEM_FAULT` and the `rvfi_mem_fault`, `rvfi_mem_fault_rmask` and `rvfi_mem_fault_wmask` signals.\nWhen the `mcause` CSR is exposed via RVFI, this will also check that it is correctly updated on a memory fault.\n\n#### `[depth]` section\n\nExpects two values: first is the number of cycles to reset for; second is the execution depth.\n\n### Cover\n\nA formal check using `cover()` SystemVerilog statements for various interesting RVFI events or\nsequences of events. The purpose of this formal check is to collect some data about the required\nbounds to reach certain states to set the bounds for the other bounded model checks. This check can\nalso be used for creating witness traces, for example to examine the conditions under which a\nspecific CSR bit goes high.\n\n#### `[depth]` section\n\nExpects two values: first is the number of cycles to reset for; second is the execution depth.\n\n#### `[cover]` section\n\nAll code in this section is included verbatim in the file `cover_stmts.vh`, which is included\nverbatim in [checks/rvfi_cover_check.sv](../checks/rvfi_cover_check.sv), and so should be valid\nSystem Verilog code.\n\n\nStandard Bus Checks\n-------------------\n\nThe following checks are managed by `genchecks.py` and can be implemented using the standard RVFI wrapper interface when implementing the RVFI_BUS extension.\n\n### Instruction Bus Memcheck\n\nThe `bus_imem` check adds a memory abstraction that only emulates a single word of memory (at an unconstrained address). This memory word is read-only and has an unconstrained value. The check makes sure that instructions fetched from this memory word are handled correctly and that the data from that memory word makes its way into `rvfi_insn` unharmed.\n\nWhen the granularity of access faults as observed from the core is coarser than the width of the bus, `RISCV_FORMAL_FAULT_WIDTH` needs to be defined and set to the corresponding width in bytes. E.g. for a setup where a single word fault the monitored bus means that from the perspective of the core, any access of the corresponding cache line will fault, you would define `RISCV_FORMAL_FAULT_WIDTH` to be the width of a cache line in bytes.\n\n### Instruction Bus Fault Memcheck\n\nThe `bus_imem_fault` check adds a memory abstraction that has a single always faulting word of memory (at an unconstrained address). The check makes sure that executing from this address causes an \"instruction access fault\" trap.\n\nThe RVFI signalling for the instruction with a faulting fetch requires an all-zero `rvfi_insn` value with `rvfi_trap` set.\nWhen `RISCV_FORMAL_MEM_FAULT` is defined the associated signals must also be set correctly.\n\n### Data Bus Memcheck\n\nThis `bus_dmem` check adds a memory abstraction that only emulates a single word of memory (at an unconstrained address). The memory word is read/write. The check tests if writes to and reads from the memory location (as reported via RVFI) are consistent. Additionally it checks that an initial value as reported via RVFI matches the fetched value on the bus. This check does not require writes to appear on the bus and is thus compatible with caches between the core and the observed bus.\n\nWhen the granularity of access faults as observed from the core is coarser than the width of the bus, `RISCV_FORMAL_FAULT_WIDTH` needs to be defined. See \"Instruction Bus Memcheck\" above for more details.\n\n### Data Bus Fault Memcheck\n\nThe `bus_dmem_fault` check adds a memory abstraction that has a single always faulting word of memory (at an unconstrained address). The check makes sure that reading from or writing to this address causes a \"load access fault\" or \"store/AMO access fault\" trap respectively.\n\nThe RVFI signalling for an instruction causing either fault has `rvfi_trap` and does not include a register update or memory write, even if the instruction would have performed one if the memory access didn't fault.\nWhen `RISCV_FORMAL_MEM_FAULT` is defined the associated signals must also be set correctly.\n\n### Data Bus I/O Checks\n\nThese checks can provide stronger guarantees on data bus accesses that are not required to hold in general, but should often hold for i/o memory regions.\nDepending on the use-case only a subset may be applicable or some checks may only be applicable for certain areas of the address space.\nThe memory addresses for which these checks are run can be configured using the `RISCV_FORMAL_IOADDR(addr)` macro.\n\n#### Data Bus I/O Reads\n\nThe `bus_dmem_io_read` check makes sure that every retired non-faulting i/o memory read access appears as an individual read on the bus. The whole read has to appear on its own in a single RVFI_BUS cycle.\nA read is allowed to also read adjacent bytes within the same RVFI_BUS cycle.\n\n#### Data Bus I/O Read Faults\n\nThe `bus_dmem_io_read_fault` check makes sure that every retired faulting i/o memory read access appears as an individual faulting read on the bus.\n\n#### Data Bus I/O Writes\n\nThe `bus_dmem_io_write` check makes sure that every retired non-faulting i/o memory write access appears as an individual write on the bus. The whole write has to appear on its own in a single RVFI_BUS cycle and may not write any additional adjacent bytes.\n\n#### Data Bus I/O Read Faults\n\nThe `bus_dmem_io_read_fault` check makes sure that every retired faulting i/o memory write access appears as an individual faulting write on the bus.\n\n#### Data Bus I/O Ordering\n\nThe `bus_dmem_io_order` check makes sure that all i/o memory accesses appear in-order on the bus.\nThis is done by checking that every pair of adjacent i/o memory accesses (as observed via RVFI) corresponds to adjacent i/o memory accesses on the bus.\nNon-i/o accesses are ignored by this check, so they can be arbitrarily reordered relative to i/o accesses and relative to each other.\n\nCSR Checks\n----------\n\nThe following checks are managed by `genchecks.py` and can be implemented using the standard RVFI\nwrapper interface.  All checks operate on one channel at a time and may not work correctly if a CSR\nis able to be modified by more than one channel.\n\n### CSR instruction check\n\nThe `csrw` check validates that CSR instructions modify the correct rvfi signal ports.\n`RISCV_FORMAL_CSRW_NAME <csrname>` must be defined for the CSR under test, along with\n`csr_{m,s,u}index_<csrname> <csraddr>`.  If the CSR has a corresponding 'h' register containing the\nupper bits, `RISCV_FORMAL_CSRWH` and `csr_{m,s,u}indexh_<csrname> <csraddr>` should also be defined.\n\nAs per the standard CSR address mapping convention: the top two bits (csr[11:10]) indicate whether\nthe register is read/write (00, 01, or 10) or read-only (11); and the next two bits (csr[9:8])\nencode the lowest privilege level that can access the CSR.  \n\nA valid read instruction must assign `rvfi_csr_<csrname>_rdata` to `rvfi_rd_wdata`, as well as the\ncorrect `rvfi_rd_addr`.  A valid write instruction must assign the correct value to\n`rvfi_csr_<csrname>_wdata`.  And any illegal accesses should result in a trap.\n\n### Illegal CSR access\n\nThe `csr_ill` check validates illegal access exceptions are raised for access to CSRs which are not\navailable through the RVFI wrapper interface, including those which may not be implemented.\n`RISCV_FORMAL_ILL_CSR_ADDR <csraddr>`  must be defined for the CSR under test.  Defining\n`RISCV_FORMAL_ILL_{M,S,U}MODE` specifies which modes should be tested for access, and\n`RISCV_FORMAL_ILL_{WRITE,READ}` specifies what accesses are expected to be illegal.\n\n### CSR consistency checks\n\nThese checks perform multiple reads/writes and compare the values on `rvfi_csr_<csrname>_rdata` and `rvfi_csr_<csrname>_wdata` during the `check` cycle.\n\nIn each case, `RISCV_FORMAL_CSRC_NAME <csrname>` must be defined for the CSR under test, along with\nthe corresponsing `csr_{m,s,u}index_<csrname> <csraddr>`.\n\n#### CSR write-any\n\nThe `csrc_any` check tests whether any value written to a CSR is then able to be read-back exactly\nas written.\n\n#### CSR increments\n\nThe `csrc_inc` check tests whether the value in a CSR is always greater than or equal to a previous\nread/write of the csr.  By constraining the most significant bit to be 0, this check can verify that\nthe value of a CSR can never decrease except by writing to it.  This is particularly useful for\nhardware performance monitors.\n\n#### CSR up-counter\n\nThe `csrc_upcnt` check is similar to the CSR increments check but with more constraints.  First, no\nwrites of the csr under test are allowed. Second, the test value *must* be greater than the\npreviously read value.  Without fairness guarantees this has limited use, but can verify some hpm functions, especially `mcycle` and `minstret`.\n\n#### CSR hpm event cover check\n\nUnlike most of the other checks, `csrc_hpm` is a cover check.  Similarly to the CSR up-counter\ncheck, the value of a hpm counter CSR is compared with a previously stored value and must increase.\nHowever, because this is a cover check this tests that the CSR *can* increase, not that it *must*\nincrease.  Used in conjunction with a `csrc_inc` test of the corresponding hpm counter CSR, this can\nverify that the hpm is able to increase and unable to decrease.\n\nThis check must be performed on a hpm event CSR, with `RISCV_FORMAL_CSRC_NAME mhpmevent#` and\n`RISCV_FORMAL_CSRC_HPMCOUNTER mhpmcounter#`.  The event must be defined by\n`RISCV_FORMAL_CSRC_HPMEVENT <value>`.  Note that both `RISCV_FORMAL_CSR_MHPMCOUNTER#` and\n`RISCV_FORMAL_CSR_MHPMEVENT#` must be defined and the corresponding rvfi signals connected.\n\n#### CSR read-constant\n\nThe `csrc_const` check tests whether the value in a CSR is always the same, ignoring any value which\nmay be written.  `RISCV_FORMAL_CSRC_CONSTVAL <value>` must be defined as the value to be expected.\nFor CSRs which can take any value so long as it remains constant during operation, a value of\n`rdata_shadow` can be assigned which will compare with the previously read value.\n\n#### CSR read-zero\n\nThe `csrc_zero` check is similar to the CSR read-constant check, but exclusively tests for a\nconstant value of all zero.\n\n### genchecks config\n\n#### `[depth]`\n\nThe `csrw` and `csr_ill` checks expect one value, indicating the maximum depth of the Bounded Model\nChecker (BMC).\n\nAll `csrc_*` checks expect two values, with the first being the number of cycles to hold reset for,\nand the second being the maximum depth of the BMC.\n\nDepth can be specified for all tests of one type, e.g. `csrc_zero`, or individual to a particular CSR, e.g. `csrw_mcycle`.\n\nAny test without a corresponding value in the `depth` section will not be run.\n\n#### `[csrs]`\n\nThe `csrs` config section lists all standard CSRs which can be tested.  By default, all CSRs will be\nrun through the CSR instruction check (`csrw`).  Consistency checks can be defined as a space\nseperated list after the csr name.  For checks which expect a value, using quotation marks will\nallow for verbatim values. \n\ne.g. `misa zero const=\"32'h 0\"` declares two tests for the `misa` CSR. First using the\n`csrc_zero_check`, and then using the `csrc_const_check` with `RISCV_FORMAL_CSRC_CONSTVAL` defined\nas `32'h 0`.\n\nEach named CSR must be connected as described in the [RVFI specification](rvfi.md).\n\nConsistency checks can be appended with `_mask=` with a verilog expression which will be applied to\nthe CSR as a bit mask before testing the return value.  Note that `_mask` must be defined *after*\nany other value assignment for the check.  For example, the statement `misa const=0_mask=\"32'h\n0aaa_ffff\"` masks the `misa` CSR and then checks for a constant value of 0. A mask value is\ncurrently only supported in the `const`, `zero`, and `any` checks.\n\n`const` supports value assignment, while `hpm` requires it.  If no value is provided for `const`, a\nvalue of `rdata_shadow` will be assigned such that any value is accepted provided it is constant.\nIn the case of `hpm` the value is assigned to the hpmevent register prior to testing if the\nhpmcounter register is able to increase.\n\n#### `[custom_csrs]`\n\nPlatform defined CSRs can be included for testing in the `custom_csrs` section.  Each line is a\nspace separated list of values defining one CSR and the corresponding tests.  The first value is the\nCSR address in hexadecimal, and the second value is the privilege modes in which the CSR is\navailable.  The rest of the line follows the same format as the `csrs` config section with the CSR name followed by any tests in addition to `csrw`.\n\ne.g. `fc0 m custom_ro const=\"32'h dead_beef\"` defines a CSR in the machine-level custom read-only\naddress space at address `0xFC0` called `custom_ro` which can be accessed from machine mode and\nshould be tested for a constant value of `0xdeadbeef` using `csrc_const_check`.\n\nAs with the standard CSRs, each of the custom CSRs must be connected through the RVFI wrapper.\n\nNote that the privilege modes defined will not prevent the CSR instruction check from expecting an\nillegal access exception based on the address.\n\n#### `[illegal_csrs]`\n\nThe `illegal_csrs` section lists unnamed CSRs not available through the RVFI wrapper interface. Each\nline lists one CSR address to be tested with `csr_ill`, along with the relevant modes to check.\nThree space separated values are expected; the first provides the address in hexadecimal, the second\nis the privilege modes to test, and the third indicates whether to test reads and writes or just\nwrites.\n\ne.g. `fff msu rw` defines a test at address oxFFF for machine, supervisor, and user modes which should cause an illegal access exception on both reads and writes.\n\n#### CSR spec test generation\n\nBy setting `csr_spec` in the `options` section, it is possible to automatically generate tests for\nall CSRs to match the specification recommendations/requirements.  This option will add all defined\nCSRs to be tested under `csrw` as well as generating corresponding `csrc` tests where relevant.  For\nthose CSRs which should only exist in certain conditions, e.g. if U mode is available, then those\nCSRs are included if the `isa` option includes them, otherwise the addresses are checked as being an\nexpected illegal access exception.  Optional CSRs are not automatically tested and will need to be\nspecified as described above.  CSRs which are defined with certain bits being reserved for future\nuse (either WPRI or WARL) are tested as being constant zero, masking for just the reserved bits.\n\nAt present the only supported value for `csr_spec` is `1.12`, corresponding to version 1.12 of the\nMachine ISA, as defined in the 20211203 Priveleged Architecture document.\n\nOther Checks\n------------\n\nThe following checks are not yet managed by `genchecks.py` and can not be implemented using the standard RVFI wrapper interface. Some of them may be integrated with `genchecks.py` in the future.\n\n### Instruction Memcheck\n\nThis check adds a memory abstraction that only emulates a single word of memory (at an unconstrained address). This memory word is read-only and has an unconstrained value. The check makes sure that instructions fetched from this memory word are handled correctly and that the data from that memory word makes its way into `rvfi_insn` unharmed.\n\nSee `imemcheck.sv` in [cores/picorv32/](../cores/picorv32/) for an example implementation.\n\nThis check is superseded by the equivalent standard bus check above.\n\n### Data Memcheck\n\nThis check adds a memory abstraction that only emulates a single word of memory (at an unconstrained address). The memory word is read/write. The check tests if writes to and reads from the memory location (as reported via RVFI) are consistent.\n\nSee `dmemcheck.sv` in [cores/picorv32/](../cores/picorv32/) for one possible implementation of this test.\n\nThis check is superseded by the equivalent standard bus check above.\n\n### Checking for equivalence of core with and without RVFI\n\nAn equivalence check of the core with and without RVFI (with respect to the non-RVFI outputs) is performed. This proves that the verification results for the core with enabled RVFI also prove that the (non-RVFI) production core is correct without extra burden on the core designer to isolate the RVFI implementation from the rest of the core.\n\nSee `equiv.sh` in [cores/picorv32/](../cores/picorv32/) for an example implementation.\n\n### Complete\n\nAn additional check to make sure the core can not (without trap) retire any instructions that are not covered by the riscv-formal instruction checks.\n\nSee `complete.sv` in [cores/picorv32/](../cores/picorv32/) for one possible implementation of this test.\n\n### Verification of riscv-formal models against spike models\n\nThe checks in [tests/spike/](../tests/spike/) use the Yosys SimpleC back-end and CBMC to check the `riscv-formal` models and the C instruction models from spike for equivalence.\n\n"
  },
  {
    "path": "docs/quickstart.md",
    "content": "\nQuick Start Guide\n=================\n\nSo you want to get your hands dirty with riscv-formal? Install the tools and\npick one of the exercises below.\n\nSee also [this presentation slides](http://bygone.clairexen.net/papers/2017/riscv-formal/) for an introduction to riscv-formal.\n\nPrerequisites\n-------------\n\nYou'll need Yosys, SymbiYosys, and Boolector for the formal proofs. See\n[here](https://yosyshq.readthedocs.io/projects/sby/en/latest/install.html)\nfor install instructions.\n\nFor additional python requirements:\n\n```\npython3 -m pip install Verilog_VCD\n```\n\nSome of those tools are packaged for some of the major Linux distribution, but\nthose packages are sometimes a few years old and do not work with riscv-formal.\nFollow the descriptions linked above and install from the latest sources instead.\n\nIf you want to inspect counter example traces you will need\n[gtkwave](http://gtkwave.sourceforge.net/). Whatever version of gtkwave is\npre-packaged in your distribution is probably fine.\n\nIf you want to disassemble the code executed in the counter example traces you\nwill need an installation of 32 bit [riscv-tools](https://github.com/riscv/riscv-tools),\nspecifically you'll need `riscv32-unknown-elf-gcc` and `riscv32-unknown-elf-objdump`\nin your `$PATH`.\n\nFor the 2nd exercise the PicoRV32 Makefile expects a toolchain with certain\nproperties in `/opt/riscv32i`. The easiest way to build this is to check out\nthe [PicoRV32 github repo](https://github.com/YosysHQ/picorv32) and run\n`make -j$(nproc) build-riscv32i-tools` (see [this](https://github.com/YosysHQ/picorv32#building-a-pure-rv32i-toolchain)\nfor prerequisites and more documentation on the process).\n\nFor the 2nd exercise you will also need [Icarus Verilog](http://iverilog.icarus.com/).\nIf your distribution packages v10 or better then this is fine, otherwise you'll\nneed to build it from source.\n\nExercise 1: Formally verify a core\n----------------------------------\n\nFormally verify that the NERV processor complies with the RISC-V ISA:\n\n```\ncd riscv-formal\ncd cores/nerv/\nmake -j$(nproc) check\n```\n\nNow make a random change to `nerv.sv` and re-run the tests:\n\n```\nmake clean\nmake -j$(nproc) check\n```\n\nThe check will likely fail now. (It will if the change did break ISA compliance\nof the core.)\n\nIf you have a 32 bit version of riscv-tools installed (`riscv32-unknown-elf-gcc` and\n`riscv32-unknown-elf-objdump` are in `$PATH`) then you can use `disasm.py` to display\nthe sequence of instructions that caused the error.\n\nLet's say `liveness_ch0` is the check that failed:\n\n```\npython3 disasm.py checks/liveness_ch0/engine_0/trace.vcd\n```\n\nOr you can simply use gtkwave to display the counter example trace:\n\n```\ngtkwave checks/liveness_ch0/engine_0/trace.vcd trace.gtkw\n```\n\nExercise 2: Build an RVFI Monitor and run it\n--------------------------------------------\n\nAn RVFI Monitor can be run side-by-side with your core and will detect when the\ncore violates the ISA spec. RVFI monitors are synthesizable, so in addition to\nsimulation they can also be used in FPGA emulation testing.\n\nLet's build an RVFI Monitor to be used with PicoRV32. PicoRV32 supports the\nrv32ic ISA (`-i rv32ic`), its RVFI port is one channel wide (`-c 1`), and it\nperforms memory operations with word alignment (`-a`):\n\n```\ncd monitor\npython3 generate.py -i rv32ic -c 1 -a -p picorv32_rvfimon > picorv32_rvfimon.v\n```\n\nNext we need to clone the PicoRV32 git repository and copy the monitor core:\n\n```\ngit clone https://github.com/YosysHQ/picorv32.git\ncp picorv32_rvfimon.v picorv32/rvfimon.v\ncd picorv32\n```\n\nAnd then run the test bench with RVFI monitor support:\n\n```\nmake test_rvf\n```\n\n(You will need to make minor changes to the Makefile if you don't have an rv32i\ntoolchain installed in `/opt/riscv32i`.)\n\nYou can now try making changes to `picorv32.v` and see if the RVFI monitor catches\nerrors in the test bench when you re-run `make test_rvf`.\n\nYou can also try running `generate.py` with `-V`. This will generate a monitor that\nprints some information about each packet it sees on the RVFI port.\n\n"
  },
  {
    "path": "docs/references.md",
    "content": "\nReferences and related work\n===========================\n\nARM's [ISA-Formal Framework](https://alastairreid.github.io/papers/cav2016_isa_formal.pdf) follows a similar set of ideas and has inspired the work on `riscv-formal`.\n\nOther RISC-V formal verification projects and related materials:\n\n- [Kami: A Framework for (RISC-V) HW Verification](https://riscv.org/wp-content/uploads/2016/07/Wed1130_Kami_Framework_Murali_Vijayaraghavan.pdf) ([kami on github](https://github.com/mit-plv/kami))\n- [Rewrite of Kami by SiFive](https://github.com/sifive/Kami)\n- [Verifying a RISC-V Processor, Nirav Dave, Prashanth Mundkur, SRI International](https://riscv.org/wp-content/uploads/2015/06/riscv-verification-workshop-june2015.pdf) ([l3riscv on github](https://github.com/SRI-CSL/l3riscv))\n- [RISC-V ISA Model in Bluespec BSV by Rishiyur S. Nikhil](https://github.com/rsnikhil/RISCV_ISA_Formal_Spec_in_BSV)\n- [RISC-V ISA Model in Haskell by Adam Chlipala and group (MIT)](https://github.com/mit-plv/riscv-semantics)\n- [RISC-V ISA Specification in Coq by MIT CSAIL](https://github.com/mit-plv/riscv-coq)\n- [RISC-V ISA Specification in Coq by SiFive](https://github.com/sifive/RiscvSpecFormal)\n- [RISC-V ISA specification work in Sail 2](https://github.com/riscv/sail-riscv)\n- [Sail: a language for describing instruction semantics](http://www.cl.cam.ac.uk/~pes20/sail/)\n- [riscv-fs: F# RISC-V Instruction Set formal specification](https://github.com/mrLSD/riscv-fs)\n\nPlease [open an issue](https://github.com/YosysHQ/riscv-formal/issues/new) if you know of other RISC-V formal verification projects I should link to in this section.\n\n"
  },
  {
    "path": "docs/rvfi.md",
    "content": "\nRISC-V Formal Interface (RVFI)\n==============================\n\nRVFI Specification\n------------------\n\nIn the following specification the term `XLEN` refers to the width of an `x` register in bits, as described in the RISC-V ISA specification. The term `NRET` refers to the maximum number of instructions that the core under test can retire in one cycle. If more than one of the retired instruction writes the same register, the channel with the highest index contains the instruction that wins the conflict. The term `ILEN` refers to the maximum instruction width for the processor under test.\n\nThe Interface consists only of output signals. Each signal is a concatenation of `NRET` values of constant width, effectively creating `NRET` channels. For simplicity, the following descriptions refer to one such channel. For example, we refer to `rvfi_valid` as a 1-bit signal, not a `NRET`-bits signal.\n\n### Instruction Metadata\n\n    output [NRET        - 1 : 0] rvfi_valid\n    output [NRET *   64 - 1 : 0] rvfi_order\n    output [NRET * ILEN - 1 : 0] rvfi_insn\n    output [NRET        - 1 : 0] rvfi_trap\n    output [NRET        - 1 : 0] rvfi_halt\n    output [NRET        - 1 : 0] rvfi_intr\n    output [NRET * 2    - 1 : 0] rvfi_mode\n    output [NRET * 2    - 1 : 0] rvfi_ixl\n\nWhen the core retires an instruction, it asserts the `rvfi_valid` signal and uses the signals described below to output the details of the retired instruction. The signals below are only valid during such a cycle and can be driven to arbitrary values in a cycle in which `rvfi_valid` is not asserted.\n\nThe `rvfi_order` field must be set to the instruction index. No indices must be used twice and there must be no gaps. Instructions may be retired in a reordered fashion, as long as causality is preserved (register and memory write operations must be retired before the read operations that depend on them).\n\n`rvfi_insn` is the instruction word for the retired instruction. In case of an instruction with fewer than `ILEN` bits, the upper bits of this output must be all zero. For compressed instructions the compressed instruction word must be output on this port. For fused instructions the complete fused instruction sequence must be output.\n\n`rvfi_trap` must be set for an instruction that cannot be decoded as a legal instruction, such as 0x00000000.\n\nIn addition, `rvfi_trap` must be set for a misaligned memory read or write in PMAs that don't allow misaligned access, or other memory access violations. `rvfi_trap` must also be set for a jump instruction that jumps to a misaligned instruction.\n\nThe signal `rvfi_halt` must be set when the instruction is the last instruction that the core retires before halting execution. It should not be set for an instruction that triggers a trap condition if the CPU reacts to the trap by executing a trap handler. This signal enables verification of liveness properties.\n\n`rvfi_intr` must be set for the first instruction that is part of a trap handler, i.e. an instruction that has a `rvfi_pc_rdata` that does not match the `rvfi_pc_wdata` of the previous instruction.\n\n`rvfi_mode` must be set to the current privilege level, using the following encoding: 0=U-Mode, 1=S-Mode, 2=Reserved, 3=M-Mode\n\nFinally `rvfi_ixl` must be set to the value of MXL/SXL/UXL in the current privilege level, using the following encoding: 1=32, 2=64\n\n### Integer Register Read/Write\n\n    output [NRET *    5 - 1 : 0] rvfi_rs1_addr\n    output [NRET *    5 - 1 : 0] rvfi_rs2_addr\n    output [NRET * XLEN - 1 : 0] rvfi_rs1_rdata\n    output [NRET * XLEN - 1 : 0] rvfi_rs2_rdata\n\n`rvfi_rs1_addr` and `rvfi_rs2_addr` are the decoded `rs1` and `rs1` register addresses for the retired instruction. For an instruction that reads no `rs1`/`rs2` register, this output can have an arbitrary value. However, if this output is nonzero then `rvfi_rs1_rdata` must carry the value stored in that register in the pre-state.\n\n`rvfi_rs1_rdata`/`rvfi_rs2_rdata` is the value of the `x` register addressed by `rs1`/`rs2` before execution of this instruction. This output must be zero when `rs1`/`rs2` is zero.\n\n    output [NRET *    5 - 1 : 0] rvfi_rd_addr\n    output [NRET * XLEN - 1 : 0] rvfi_rd_wdata\n\n`rvfi_rd_addr` is the decoded `rd` register address for the retired instruction. For an instruction that writes no `rd` register, this output must always be zero.\n\n`rvfi_rd_wdata` is the value of the `x` register addressed by `rd` after execution of this instruction. This output must be zero when `rd` is zero.\n\n### Program Counter\n\n    output [NRET * XLEN - 1 : 0] rvfi_pc_rdata\n    output [NRET * XLEN - 1 : 0] rvfi_pc_wdata\n\nThis is the program counter (`pc`) before (`rvfi_pc_rdata`) and after (`rvfi_pc_wdata`) execution of this instruction. I.e. this is the address of the retired instruction and the address of the next instruction.\n\n### Memory Access\n\n    output [NRET * XLEN   - 1 : 0] rvfi_mem_addr\n    output [NRET * XLEN/8 - 1 : 0] rvfi_mem_rmask\n    output [NRET * XLEN/8 - 1 : 0] rvfi_mem_wmask\n    output [NRET * XLEN   - 1 : 0] rvfi_mem_rdata\n    output [NRET * XLEN   - 1 : 0] rvfi_mem_wdata\n\nFor memory operations (`rvfi_mem_rmask` and/or `rvfi_mem_wmask` are non-zero), `rvfi_mem_addr` holds the accessed memory location.\n\nWhen the define `RISCV_FORMAL_ALIGNED_MEM` is set, the address must have a 4-byte alignment for `XLEN=32` and an 8-byte alignment for `XLEN=64`. When the define is not set, then the address must point directly to the LSB or the word / half word / byte that is accessed.\n\n`rvfi_mem_rmask` is a bitmask that specifies which bytes in `rvfi_mem_rdata` contain valid read data from `rvfi_mem_addr`.\n\n`rvfi_mem_wmask` is a bitmask that specifies which bytes in `rvfi_mem_wdata` contain valid data that is written to `rvfi_mem_addr`.\n\n`rvfi_mem_rdata` is the pre-state data read from `rvfi_mem_addr`. `rvfi_mem_rmask` specifies which bytes are valid.\n\n`rvfi_mem_wdata` is the post-state data written to `rvfi_mem_addr`. `rvfi_mem_wmask` specifies which bytes are valid.\n\nWhen `RISCV_FORMAL_ALIGNED_MEM` is set then `riscv-formal` assumes that unaligned memory access causes a trap.\n\n### Alternative Arithmetic Operations\n\nSome arithmetic operations (such as multiplication and division) are beyond to practical capabilities of even modern hardware model checkers. In order to still be able to verify things like bypassing for the arithmetic units performing those operations we define a set of alternative arithmetic operations. When the define `RISCV_FORMAL_ALTOPS` is set riscv-formal will expect the processor under test to implement those alternative operations instead.\n\nCommutative operations (like multiplication) are replaced with addition followed by applying XOR with a bitmask that indicates the type of the operation. Noncommutative operations (like division) are replaced with subtraction followed by applying XOR with a bitmask that indicates the type of the operation.\n\nThe bitmasks are 64 bits wide. RV32 implementations only use the lower 32 bits of the bitmasks. The\n`*W` instructions in RV64 (such as `MULW`) are implemented by adding or subtracting the lower 32\nbits of the operands, then XORing with the lower 32 bits of the bitmask, then sign extending the\nresult to 64 bits.\n\n#### Integer Multiply/Divide Instructions\n\n<!--  for n in MUL{,H,HSU,HU} DIV{,U} REM{,U}; do echo \"$( echo -n $n | md5sum ) $n\"; done | cut -c1-16,36- -->\n\n| Operation |  Add/Sub |      Bitmask       |\n|:----------|:--------:|:------------------:|\n| MUL       |    Add   | 0x2cdf52a55876063e |\n| MULH      |    Add   | 0x15d01651f6583fb7 |\n| MULHSU    |    Sub   | 0xea3969edecfbe137 |\n| MULHU     |    Add   | 0xd13db50d949ce5e8 |\n| DIV       |    Sub   | 0x29bbf66f7f8529ec |\n| DIVU      |    Sub   | 0x8c629acb10e8fd70 |\n| REM       |    Sub   | 0xf5b7d8538da68fa5 |\n| REMU      |    Sub   | 0xbc4402413138d0e1 |\n\n### Control and Status Registers (CSRs)\n\nFor each supported CSR there are four additional output ports:\n\n    output [NRET * XLEN - 1 : 0] rvfi_csr_<csrname>_rmask\n    output [NRET * XLEN - 1 : 0] rvfi_csr_<csrname>_wmask\n    output [NRET * XLEN - 1 : 0] rvfi_csr_<csrname>_rdata\n    output [NRET * XLEN - 1 : 0] rvfi_csr_<csrname>_wdata\n\nThe `rmask` and `wmask` ports specify which bits of `rdata` and `wdata` are valid.\n\nIt is always valid for an instruction to activate more `rmask`/`rdata` bits\nthan required by the instruction, as long as the reported bits correctly reflect\nthe machine state.\n\nIf reading a CSR has side effects, those side effects are not triggered by raised\n`rmask` bits but by the type of the instruction.\n\nThe Verilog define `RISCV_FORMAL_CSR_<CSRNAME>` must be set for each CSR traced\nvia RVFI by the core under test.\n\nSee [RISC-V Formal CSR Semantics](csrs.md) for the exact semantics of CSR values\noutput via RVFI.\n\n### Handling of Speculative Execution\n\nOut-of-order cores that execute speculatively can commit speculative instructions on RVFI.\n\nRollbacks must be output via the rollback interface, that is enabled when `RISCV_FORMAL_ROLLBACK` is defined:\n\n    output [ 0 : 0] rvfi_rollback_valid\n    output [63 : 0] rvfi_rollback_order\n\nAll RVFI packets output _prior_ to the cycle with asserted `rvfi_rollback_valid` with a `rvfi_order` field of _greater or equal_ to `rvfi_rollback_order` are invalidated by a rollback event.\n\nRVFI packets output in the same cycle as `rvfi_rollback_valid` are already part of the new instruction stream re-starting at the instruction number indicated in `rvfi_rollback_order`.\n\n### Handling of Dynamic Faults\n\nCores where the fault check for an instruction fetch or a data access is determined by an external bus response can signal such faults via RVFI.\n\nWhen `RISCV_FORMAL_MEM_FAULT` is defined, the RVFI interface is extended by the following signal:\n\n    output [NRET          - 1 : 0] rvfi_mem_fault\n    output [NRET * XLEN/8 - 1 : 0] rvfi_mem_fault_rmask\n    output [NRET * XLEN/8 - 1 : 0] rvfi_mem_fault_wmask\n\nAn instruction fetch that faults sets `rvfi_insn` to all zero and set `rvfi_mem_fault`. A memory access that faults sets `rvfi_mem_fault` and does not signal any register or memory writes. Instead the bytes that would have been accessed (if the access hadn't faulted) are output to `rvfi_mem_fault_rmask` and `rvfi_mem_fault_wmask` instead. The address is still output via `rvfi_mem_addr`.\n\n### Handling of External Memory Busses\n\nRISC-V Formal includes several checks that verify consistency properties between memory accesses observed via the RVFI and memory accesses observed on external instruction and/or data busses.\nTo not tie those checks to a specific bus, those checks extend the RVFI with the RVFI_BUS interface.\nRVFI_BUS consists of further outputs that observe memory accesses on a bus while abstracting over the exact signalling used for the bus.\n\nTo run these checks, the relevant busses of the core should be connected to an abstraction that implements the required bus signalling but provides unconstrai (This may be relaxed with an extensions )ned responses to the core. The accesses on the bus are then observed and constrained by these checks via the RVFI_BUS outputs.\n\nNote: When implementing such an abstraction it should output the access using RVFI_BUS as soon as the access first appears on the bus, even when the reply to the core happens in a later cycle. (Whether this is necessary and how much delay is acceptable depends on the checks performed and on the design of the core and the core's RVFI implementation. Too much delay can cause false positives by preventing the check from properly constraining the RVFI_BUS transfers.)\n\nFor standard busses the same unconstrained abstractions and RVFI_BUS observers can be re-used for multiple cores.\n\nThe RVFI_BUS extension can observe multiple busses using multiple RVFI_BUS channels. This is used to model separate data and instruction busses as well as busses that can transfer accesses to several unrelated addresses in the same cycle. The total number of channels is specified using `NBUS` which works like `NRET` for the main RVFI signals. The width of the observed bus is independent of `XLEN` and is specified using `BUSLEN`. If different channels observe busses of a different width, `BUSLEN` should be set to the maximum width in use.\n\nRVFI_BUS adds the following ouptuts:\n\n    output [NBUS *      1   - 1 : 0] rvfi_bus_valid\n    output [NBUS *      1   - 1 : 0] rvfi_bus_insn\n    output [NBUS *      1   - 1 : 0] rvfi_bus_data\n    output [NBUS *      1   - 1 : 0] rvfi_bus_fault\n    output [NBUS *   XLEN   - 1 : 0] rvfi_bus_addr\n    output [NBUS * BUSLEN/8 - 1 : 0] rvfi_bus_rmask\n    output [NBUS * BUSLEN/8 - 1 : 0] rvfi_bus_wmask\n    output [NBUS * BUSLEN   - 1 : 0] rvfi_bus_rdata\n    output [NBUS * BUSLEN   - 1 : 0] rvfi_bus_wdata\n\nWhen `rvfi_bus_valid` is set, there is an observed memory access present on the RVFI_BUS channel, otherwise, all other RVFI_BUS outputs are ignored.\n\nThe outputs `rvfi_bus_insn` and `rvfi_bus_data` are used to indicate whether the access is an instruction fetch or a data access. For cores or busses that do not distinguish between those, both have to be set.\n\nThe `rvfi_bus_addr` output is the address of the access.\n\nThe outputs `rvfi_bus_rmask` and `rvfi_bus_wmask` indicate which bytes starting with `rvfi_bus_addr` are accessed. This is used for both, masked writes as well as for outputting busses smaller than `BUSLEN`. Note that when the LSBs of `rvfi_bus_rmask` and `rvfi_bus_wmask` are cleared, `rvfi_bus_addr` may be lower than the first actually accessed byte.\n\nThe outputs `rvfi_bus_rdata` and `rvfi_bus_wdata` contain the read and written data and are only valid for the bytes corresponding to the respective bits in `rvfi_bus_rmask` and `rvfi_bus_wmask`.\n\nAll accesses observed using RVFI_BUS are assumed to be in order, including acceses in the same cycle which are ordered by increasing RVFI_BUS channel index. This may be relaxed by future extensions.\n\n#### RVFI_BUS observers for standard interfaces\n\nThe `bus` directory contains implementations RVFI_BUS observers and abstractions for standard interfaces.\n\nNote that the observers are passive and do not constrain any signals on their own. That means to test a core in isolation, the core's interface may have to be connected to an abstraction that provides the handshaking that the core expects to properly function without constraining the data or timing beyond that.\n\nAXI4 observers and abstractions are provided in `bus/rvfi_bus_axi4.sv`, which also contains some notes about the timing when translating AXI4 into RVFI_BUS signals.\n\n\nRVFI TODOs and Requests for Comments\n------------------------------------\n\nThe following section contains notes on future extensions to RVFI. They will come part of the spec as soon as there is at least one core that implements the feature, and a matching formal check that utilises the feature. In many cases the additional ports will only be used (and expected from the core) when additional to-be-defined `RISCV_FORMAL_*` Verilog defines are set.\n\n### Support for fused instructions\n\nFused instructions are simply handled as larger instructions in RVFI. Additional `rvfi_rs*` ports (or even `rvfi_rd*` ports) may be added to accommodate the fused instructions.\n\nNo instruction models for fused instructions have been created yet.\n\nAlternatively fused instructions may be output as individual instructions in separate RVFI channels.\n\n### Modelling of Floating-Point State\n\nThe following is the proposed RVFI extension for floating point ISAs:\n\n    output [NRET *    5 - 1 : 0] rvfi_frs1_addr\n    output [NRET *    5 - 1 : 0] rvfi_frs2_addr\n    output [NRET *    5 - 1 : 0] rvfi_frs3_addr\n    output [NRET *    5 - 1 : 0] rvfi_frd_addr\n    output [NRET        - 1 : 0] rvfi_frs1_rvalid\n    output [NRET        - 1 : 0] rvfi_frs2_rvalid\n    output [NRET        - 1 : 0] rvfi_frs3_rvalid\n    output [NRET        - 1 : 0] rvfi_frd_wvalid\n    output [NRET * FLEN - 1 : 0] rvfi_frs1_rdata\n    output [NRET * FLEN - 1 : 0] rvfi_frs2_rdata\n    output [NRET * FLEN - 1 : 0] rvfi_frs3_rdata\n    output [NRET * FLEN - 1 : 0] rvfi_frd_wdata\n    output [NRET * XLEN - 1 : 0] rvfi_csr_fcsr_rmask\n    output [NRET * XLEN - 1 : 0] rvfi_csr_fcsr_wmask\n    output [NRET * XLEN - 1 : 0] rvfi_csr_fcsr_rdata\n    output [NRET * XLEN - 1 : 0] rvfi_csr_fcsr_wdata\n\nSince `f0` is not a zero register, additional `*_[rw]valid` signals are required to indicate if `frs1`, `frs2`, `frs3`, and `frd` and their corresponding pre- or post-values are valid.\n\nAlternative arithmetic operations (`RISCV_FORMAL_ALTOPS`) will be defined for all non-trivial floating point operations.\n\n### Modelling of Virtual Memory\n\nFor processors with support for S-mode and virtual memory we define the following additional RVFI signals for data load/stores:\n\n    output [NRET *   64 - 1 : 0] rvfi_mem_paddr\n    output [NRET * XLEN - 1 : 0] rvfi_mem_pte0\n    output [NRET * XLEN - 1 : 0] rvfi_mem_pte1\n    output [NRET * XLEN - 1 : 0] rvfi_mem_pte2\n    output [NRET * XLEN - 1 : 0] rvfi_mem_pte3\n\nAnd the following additional RVFI signals for instruction fetches:\n\n    output [NRET *   64 - 1 : 0] rvfi_pc_paddr\n    output [NRET * XLEN - 1 : 0] rvfi_pc_pte0\n    output [NRET * XLEN - 1 : 0] rvfi_pc_pte1\n    output [NRET * XLEN - 1 : 0] rvfi_pc_pte2\n    output [NRET * XLEN - 1 : 0] rvfi_pc_pte3\n\nAnd we require that the `satp` CSR is observable through RVFI:\n\n    output [NRET * XLEN - 1 : 0] rvfi_csr_satp_rmask\n    output [NRET * XLEN - 1 : 0] rvfi_csr_satp_wmask\n    output [NRET * XLEN - 1 : 0] rvfi_csr_satp_rdata\n    output [NRET * XLEN - 1 : 0] rvfi_csr_satp_wdata\n\nThe `rvfi_mem_paddr` field carries the physical address of the memory access. The `rvfi_mem_pte[0123]` fields carry the values of the page table entries used to convert `rvfi_mem_addr` to `rvfi_mem_paddr`. Unused `rvfi_mem_pte[0123]` fields must always be set to zero.\n\nFor memory accesses in M-mode, or with `satp.MODE=0`, `rvfi_mem_paddr` must have the same value as `rvfi_mem_addr` and all four `rvfi_mem_pte[0123]` fields must be set to zero.\n\nFor example in Sv32 mode, modulo missing fences, `rvfi_mem_pte1` must carry the value of the 32-bit word at the following memory location:\n\n```\npt1 = rvfi_csr_satp_rdata & 0x003fffff\nvpn1 = (rvfi_mem_addr >> 22) & 0x3ff\npte1_addr = (pt1 << 12) | (vpn1 << 2)\n```\n\nAnd `rvfi_mem_pte0` must carry the value of the 32-bit word at the following memory location (or zero if `pte1.X` or `pte1.R` or `!pte1.V`):\n\n```\npt0 = rvfi_mem_pte1 >> 10\nvpn0 = (rvfi_mem_addr >> 12) & 0x3ff\npte0_addr = (pt0 << 12) | (vpn0 << 2)\n```\n\nFinally, `rvfi_mem_paddr` must be set to the following address:\n\n```\nppn = rvfi_mem_pte0 >> 10\noffset = rvfi_mem_addr & 0xfff\nrvfi_mem_paddr = (ppn << 12) | offset\n```\n\n### Modelling of Atomic Memory Operations\n\nAMO instructions (`AMOSWAP.W`, etc.) can be modelled using the existing `rvfi_mem_*` interface by asserting bits in both `rvfi_mem_rmask` and `rvfi_mem_wmask`.\n\nThere is also no extension to the RVFI port necessary to accommodate the `LR`, `SC`, `FENCE` and `FENCE.I` instructions.\n\nVerification of this instructions for a single-core systems can be done using the RVFI port only. A strategy must be defined to verify their correct behavior in multicore systems.\n\nFor atomic instructions with `rd = x0` a core might have no way of knowing the old or new value of the memory location. For those situations we add an additional RVFI output port:\n\n    output [NRET          - 1 : 0] rvfi_mem_extamo\n\nWhen `rvfi_mem_extamo` is set, `rvfi_mem_wdata` carries the `rs2` value used with the atomic instruction instead of the new value in the memory location. `rvfi_mem_rmask` is all-zeros in this case.\n\n### Skipping instructions\n\nConsider the following sequence of instructions:\n\n        ....\n        add t0,t1,t2\n        beqz t3,label\n        sub t0,t1,t3\n    label:\n        ....\n\nWhen t3 has a non-zero value the processor could decide not to schedule the add instruction because its value is never going to be used. In this case the processor would be unable to produce a valid RVFI trace for the instruction sequence.\n\nAn additional signal can be added to RVFI that can be used to mark such instructions:\n\n    output [NRET        - 1 : 0] rvfi_skip\n\nWhen `rvfi_skip` is high the core may output arbitrary data on the `*_rdata` and `*_wdata` ports (excluding `rvfi_pc_rdata` and `rvfi_pc_wdata`). The register values written by such intrustions may only be observed by other skipped instructions. An additional formal proof must be added to check this property.\n\nMemory operations (`rvfi_mem_rmask` and/or `rvfi_mem_wmask` are non-zero) can not be skipped.\n\n"
  },
  {
    "path": "insns/generate.py",
    "content": "#!/usr/bin/env python3\n#\n# Copyright (C) 2017  Claire Xenia Wolf <claire@yosyshq.com>\n#\n# Permission to use, copy, modify, and/or distribute this software for any\n# purpose with or without fee is hereby granted, provided that the above\n# copyright notice and this permission notice appear in all copies.\n#\n# THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n\ncurrent_isa = []\nisa_database = dict()\ndefaults_cache = None\n\nMISA_A = 1 <<  0 # Atomic\nMISA_B = 1 <<  1 # -reserved-\nMISA_C = 1 <<  2 # Compressed\nMISA_D = 1 <<  3 # Double-precision float\nMISA_E = 1 <<  4 # RV32E base ISA\nMISA_F = 1 <<  5 # Single-precision float\nMISA_G = 1 <<  6 # Additional std extensions\nMISA_H = 1 <<  7 # -reserved-\nMISA_I = 1 <<  8 # RV32I/RV64I/RV128I base ISA\nMISA_J = 1 <<  9 # -reserved-\nMISA_K = 1 << 10 # -reserved-\nMISA_L = 1 << 11 # -reserved-\nMISA_M = 1 << 12 # Muliply/Divide\nMISA_N = 1 << 13 # User-level interrupts\nMISA_O = 1 << 14 # -reserved-\nMISA_P = 1 << 15 # -reserved-\nMISA_Q = 1 << 16 # Quad-precision float\nMISA_R = 1 << 17 # -reserved-\nMISA_S = 1 << 18 # Supervisor mode\nMISA_T = 1 << 19 # -reserved-\nMISA_U = 1 << 20 # User mode\nMISA_V = 1 << 21 # -reserved-\nMISA_W = 1 << 22 # -reserved-\nMISA_X = 1 << 23 # Non-std extensions\nMISA_Y = 1 << 24 # -reserved-\nMISA_Z = 1 << 25 # -reserved-\n\ndef header(f, insn, isa_mode=False):\n    if not isa_mode:\n        global isa_database\n        for isa in current_isa:\n            if isa not in isa_database:\n                isa_database[isa] = set()\n            isa_database[isa].add(insn)\n\n    global defaults_cache\n    defaults_cache = dict()\n\n    print(\"// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\", file=f)\n    print(\"\", file=f)\n    if isa_mode:\n        print(\"module rvfi_isa_%s (\" % insn, file=f)\n    else:\n        print(\"module rvfi_insn_%s (\" % insn, file=f)\n\n    print(\"  input                                 rvfi_valid,\", file=f)\n    print(\"  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\", file=f)\n    print(\"  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\", file=f)\n    print(\"  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\", file=f)\n    print(\"  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\", file=f)\n    print(\"  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\", file=f)\n\n    print(\"`ifdef RISCV_FORMAL_CSR_MISA\", file=f)\n    print(\"  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\", file=f)\n    print(\"  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\", file=f)\n    print(\"`endif\", file=f)\n\n    print(\"\", file=f)\n    print(\"  output                                spec_valid,\", file=f)\n    print(\"  output                                spec_trap,\", file=f)\n    print(\"  output [                       4 : 0] spec_rs1_addr,\", file=f)\n    print(\"  output [                       4 : 0] spec_rs2_addr,\", file=f)\n    print(\"  output [                       4 : 0] spec_rd_addr,\", file=f)\n    print(\"  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\", file=f)\n    print(\"  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\", file=f)\n    print(\"  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\", file=f)\n    print(\"  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\", file=f)\n    print(\"  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\", file=f)\n    print(\"  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\", file=f)\n\n    print(\");\", file=f)\n\n    defaults_cache[\"spec_valid\"] = \"0\"\n    defaults_cache[\"spec_rs1_addr\"] = \"0\"\n    defaults_cache[\"spec_rs2_addr\"] = \"0\"\n    defaults_cache[\"spec_rd_addr\"] = \"0\"\n    defaults_cache[\"spec_rd_wdata\"] = \"0\"\n    defaults_cache[\"spec_pc_wdata\"] = \"0\"\n    defaults_cache[\"spec_trap\"] = \"!misa_ok\"\n    defaults_cache[\"spec_mem_addr\"] = \"0\"\n    defaults_cache[\"spec_mem_rmask\"] = \"0\"\n    defaults_cache[\"spec_mem_wmask\"] = \"0\"\n    defaults_cache[\"spec_mem_wdata\"] = \"0\"\n\ndef assign(f, sig, val):\n    print(\"  assign %s = %s;\" % (sig, val), file=f)\n\n    if sig in defaults_cache:\n        del defaults_cache[sig]\n\ndef misa_check(f, mask, ialign16=False):\n    print(\"\", file=f)\n    print(\"`ifdef RISCV_FORMAL_CSR_MISA\", file=f)\n    print(\"  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h %x) == `RISCV_FORMAL_XLEN'h %x;\" % (mask, mask), file=f)\n    print(\"  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h %x;\" % ((mask|MISA_C) if ialign16 else mask), file=f)\n    if ialign16:\n        print(\"  wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h %x) != `RISCV_FORMAL_XLEN'h 0;\" % (MISA_C), file=f)\n    print(\"`else\", file=f)\n    print(\"  wire misa_ok = 1;\", file=f)\n    if ialign16:\n        print(\"`ifdef RISCV_FORMAL_COMPRESSED\", file=f)\n        print(\"  wire ialign16 = 1;\", file=f)\n        print(\"`else\", file=f)\n        print(\"  wire ialign16 = 0;\", file=f)\n        print(\"`endif\", file=f)\n    print(\"`endif\", file=f)\n\ndef footer(f):\n    def default_assign(sig):\n        if sig in defaults_cache:\n            print(\"  assign %s = %s;\" % (sig, defaults_cache[sig]), file=f)\n\n    if len(defaults_cache) != 0:\n        print(\"\", file=f)\n        print(\"  // default assignments\", file=f)\n\n        default_assign(\"spec_valid\")\n        default_assign(\"spec_rs1_addr\")\n        default_assign(\"spec_rs2_addr\")\n        default_assign(\"spec_rd_addr\")\n        default_assign(\"spec_rd_wdata\")\n        default_assign(\"spec_pc_wdata\")\n        default_assign(\"spec_trap\")\n        default_assign(\"spec_mem_addr\")\n        default_assign(\"spec_mem_rmask\")\n        default_assign(\"spec_mem_wmask\")\n        default_assign(\"spec_mem_wdata\")\n\n    print(\"endmodule\", file=f)\n\ndef format_r(f):\n    print(\"\", file=f)\n    print(\"  // R-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\", file=f)\n    print(\"  wire [6:0] insn_funct7 = rvfi_insn[31:25];\", file=f)\n    print(\"  wire [4:0] insn_rs2    = rvfi_insn[24:20];\", file=f)\n    print(\"  wire [4:0] insn_rs1    = rvfi_insn[19:15];\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[14:12];\", file=f)\n    print(\"  wire [4:0] insn_rd     = rvfi_insn[11: 7];\", file=f)\n    print(\"  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\", file=f)\n\ndef format_ra(f):\n    print(\"\", file=f)\n    print(\"  // R-type instruction format (atomics variation)\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\", file=f)\n    print(\"  wire [6:0] insn_funct5 = rvfi_insn[31:27];\", file=f)\n    print(\"  wire       insn_aq     = rvfi_insn[26];\", file=f)\n    print(\"  wire       insn_rl     = rvfi_insn[25];\", file=f)\n    print(\"  wire [4:0] insn_rs2    = rvfi_insn[24:20];\", file=f)\n    print(\"  wire [4:0] insn_rs1    = rvfi_insn[19:15];\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[14:12];\", file=f)\n    print(\"  wire [4:0] insn_rd     = rvfi_insn[11: 7];\", file=f)\n    print(\"  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\", file=f)\n\ndef format_i(f):\n    print(\"\", file=f)\n    print(\"  // I-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\", file=f)\n    print(\"  wire [4:0] insn_rs1    = rvfi_insn[19:15];\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[14:12];\", file=f)\n    print(\"  wire [4:0] insn_rd     = rvfi_insn[11: 7];\", file=f)\n    print(\"  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\", file=f)\n\ndef format_i_shift(f):\n    print(\"\", file=f)\n    print(\"  // I-type instruction format (shift variation)\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\", file=f)\n    print(\"  wire [6:0] insn_funct6 = rvfi_insn[31:26];\", file=f)\n    print(\"  wire [5:0] insn_shamt  = rvfi_insn[25:20];\", file=f)\n    print(\"  wire [4:0] insn_rs1    = rvfi_insn[19:15];\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[14:12];\", file=f)\n    print(\"  wire [4:0] insn_rd     = rvfi_insn[11: 7];\", file=f)\n    print(\"  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\", file=f)\n\ndef format_s(f):\n    print(\"\", file=f)\n    print(\"  // S-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]});\", file=f)\n    print(\"  wire [4:0] insn_rs2    = rvfi_insn[24:20];\", file=f)\n    print(\"  wire [4:0] insn_rs1    = rvfi_insn[19:15];\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[14:12];\", file=f)\n    print(\"  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\", file=f)\n\ndef format_sb(f):\n    print(\"\", file=f)\n    print(\"  // SB-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0});\", file=f)\n    print(\"  wire [4:0] insn_rs2    = rvfi_insn[24:20];\", file=f)\n    print(\"  wire [4:0] insn_rs1    = rvfi_insn[19:15];\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[14:12];\", file=f)\n    print(\"  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\", file=f)\n\ndef format_u(f):\n    print(\"\", file=f)\n    print(\"  // U-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:12], 12'b0});\", file=f)\n    print(\"  wire [4:0] insn_rd     = rvfi_insn[11:7];\", file=f)\n    print(\"  wire [6:0] insn_opcode = rvfi_insn[ 6:0];\", file=f)\n\ndef format_uj(f):\n    print(\"\", file=f)\n    print(\"  // UJ-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[19:12], rvfi_insn[20], rvfi_insn[30:21], 1'b0});\", file=f)\n    print(\"  wire [4:0] insn_rd     = rvfi_insn[11:7];\", file=f)\n    print(\"  wire [6:0] insn_opcode = rvfi_insn[6:0];\", file=f)\n\ndef format_cr(f):\n    print(\"\", file=f)\n    print(\"  // CI-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [3:0] insn_funct4 = rvfi_insn[15:12];\", file=f)\n    print(\"  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\", file=f)\n    print(\"  wire [4:0] insn_rs2 = rvfi_insn[6:2];\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_ci(f):\n    print(\"\", file=f)\n    print(\"  // CI-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]});\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_ci_sp(f):\n    print(\"\", file=f)\n    print(\"  // CI-type instruction format (SP variation)\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[4:3], rvfi_insn[5], rvfi_insn[2], rvfi_insn[6], 4'b0});\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_ci_lui(f):\n    print(\"\", file=f)\n    print(\"  // CI-type instruction format (LUI variation)\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2], 12'b0});\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_ci_sri(f):\n    print(\"\", file=f)\n    print(\"  // CI-type instruction format (SRI variation)\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]};\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [1:0] insn_funct2 = rvfi_insn[11:10];\", file=f)\n    print(\"  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_ci_sli(f):\n    print(\"\", file=f)\n    print(\"  // CI-type instruction format (SLI variation)\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]};\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_ci_andi(f):\n    print(\"\", file=f)\n    print(\"  // CI-type instruction format (ANDI variation)\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]});\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [1:0] insn_funct2 = rvfi_insn[11:10];\", file=f)\n    print(\"  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_ci_lsp(f, numbytes):\n    print(\"\", file=f)\n    print(\"  // CI-type instruction format (LSP variation, %d bit version)\" % (8*numbytes), file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    if numbytes == 4:\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[3:2], rvfi_insn[12], rvfi_insn[6:4], 2'b00};\", file=f)\n    elif numbytes == 8:\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[4:2], rvfi_insn[12], rvfi_insn[6:5], 3'b000};\", file=f)\n    else:\n        assert False\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rd = rvfi_insn[11:7];\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_cl(f, numbytes):\n    print(\"\", file=f)\n    print(\"  // CL-type instruction format (%d bit version)\" % (8*numbytes), file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    if numbytes == 4:\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00};\", file=f)\n    elif numbytes == 8:\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[6:5], rvfi_insn[12:10], 3'b000};\", file=f)\n    else:\n        assert False\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};\", file=f)\n    print(\"  wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]};\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_css(f, numbytes):\n    print(\"\", file=f)\n    print(\"  // CSS-type instruction format (%d bit version)\" % (8*numbytes), file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    if numbytes == 4:\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[8:7], rvfi_insn[12:9], 2'b00};\", file=f)\n    elif numbytes == 8:\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[9:7], rvfi_insn[12:10], 3'b000};\", file=f)\n    else:\n        assert False\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rs2 = rvfi_insn[6:2];\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_cs(f, numbytes):\n    print(\"\", file=f)\n    print(\"  // CS-type instruction format (%d bit version)\" % (8*numbytes), file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    if numbytes == 4:\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00};\", file=f)\n    elif numbytes == 8:\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[6:5], rvfi_insn[12:10], 3'b000};\", file=f)\n    else:\n        assert False\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};\", file=f)\n    print(\"  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_cs_alu(f):\n    print(\"\", file=f)\n    print(\"  // CS-type instruction format (ALU version)\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [5:0] insn_funct6 = rvfi_insn[15:10];\", file=f)\n    print(\"  wire [1:0] insn_funct2 = rvfi_insn[6:5];\", file=f)\n    print(\"  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\", file=f)\n    print(\"  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_ciw(f):\n    print(\"\", file=f)\n    print(\"  // CIW-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[10:7], rvfi_insn[12:11], rvfi_insn[5], rvfi_insn[6], 2'b00};\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]};\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_cb(f):\n    print(\"\", file=f)\n    print(\"  // CB-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:5], rvfi_insn[2], rvfi_insn[11:10], rvfi_insn[4:3], 1'b0});\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef format_cj(f):\n    print(\"\", file=f)\n    print(\"  // CJ-type instruction format\", file=f)\n    print(\"  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\", file=f)\n    print(\"  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[8], rvfi_insn[10], rvfi_insn[9],\", file=f)\n    print(\"      rvfi_insn[6], rvfi_insn[7], rvfi_insn[2], rvfi_insn[11], rvfi_insn[5], rvfi_insn[4], rvfi_insn[3], 1'b0});\", file=f)\n    print(\"  wire [2:0] insn_funct3 = rvfi_insn[15:13];\", file=f)\n    print(\"  wire [1:0] insn_opcode = rvfi_insn[1:0];\", file=f)\n\ndef insn_lui(insn=\"lui\", misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_u(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_opcode == 7'b 0110111\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? insn_imm : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n\n        footer(f)\n\ndef insn_auipc(insn=\"auipc\", misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_u(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_opcode == 7'b 0010111\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? rvfi_pc_rdata + insn_imm : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n\n        footer(f)\n\ndef insn_jal(insn=\"jal\", misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_uj(f)\n        misa_check(f, misa,  ialign16=True)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_opcode == 7'b 1101111\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? rvfi_pc_rdata + 4 : 0\")\n        assign(f, \"spec_pc_wdata\", \"next_pc\")\n        assign(f, \"spec_trap\", \"(ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok\")\n\n        footer(f)\n\ndef insn_jalr(insn=\"jalr\", misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_i(f)\n        misa_check(f, misa, ialign16=True)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = (rvfi_rs1_rdata + insn_imm) & ~1;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 1100111\")\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? rvfi_pc_rdata + 4 : 0\")\n        assign(f, \"spec_pc_wdata\", \"next_pc\")\n        assign(f, \"spec_trap\", \"(ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok\")\n\n        footer(f)\n\ndef insn_b(insn, funct3, expr, misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_sb(f)\n        misa_check(f, misa, ialign16=True)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire cond = %s;\" % expr, file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b 1100011\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_pc_wdata\", \"next_pc\")\n        assign(f, \"spec_trap\", \"(ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok\")\n\n        footer(f)\n\ndef insn_l(insn, funct3, numbytes, signext, misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_i(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"`ifdef RISCV_FORMAL_ALIGNED_MEM\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        print(\"  wire [%d:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\" % (8*numbytes-1), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b 0000011\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_mem_addr\", \"addr & ~(`RISCV_FORMAL_XLEN/8-1)\")\n        assign(f, \"spec_mem_rmask\", \"((1 << %d)-1) << (addr-spec_mem_addr)\" % numbytes)\n        if signext:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? $signed(result) : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n        assign(f, \"spec_trap\", \"((addr & (%d-1)) != 0) || !misa_ok\" % numbytes)\n\n        print(\"`else\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        print(\"  wire [%d:0] result = rvfi_mem_rdata;\" % (8*numbytes-1), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && insn_funct3 == 3'b %s && insn_opcode == 7'b 0000011\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_mem_addr\", \"addr\")\n        assign(f, \"spec_mem_rmask\", \"((1 << %d)-1)\" % numbytes)\n        if signext:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? $signed(result) : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n        assign(f, \"spec_trap\", \"!misa_ok\")\n\n        print(\"`endif\", file=f)\n\n        footer(f)\n\ndef insn_s(insn, funct3, numbytes, misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_s(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"`ifdef RISCV_FORMAL_ALIGNED_MEM\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b 0100011\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_mem_addr\", \"addr & ~(`RISCV_FORMAL_XLEN/8-1)\")\n        assign(f, \"spec_mem_wmask\", \"((1 << %d)-1) << (addr-spec_mem_addr)\" % numbytes)\n        assign(f, \"spec_mem_wdata\", \"rvfi_rs2_rdata << (8*(addr-spec_mem_addr))\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n        assign(f, \"spec_trap\", \"((addr & (%d-1)) != 0) || !misa_ok\" % numbytes)\n\n        print(\"`else\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b 0100011\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_mem_addr\", \"addr\")\n        assign(f, \"spec_mem_wmask\", \"((1 << %d)-1)\" % numbytes)\n        assign(f, \"spec_mem_wdata\", \"rvfi_rs2_rdata\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n        assign(f, \"spec_trap\", \"!misa_ok\")\n\n        print(\"`endif\", file=f)\n\n        footer(f)\n\ndef insn_imm(insn, funct3, expr, wmode=False, misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_i(f)\n        misa_check(f, misa)\n\n        if wmode:\n            result_range = \"31:0\"\n            opcode = \"0011011\"\n        else:\n            result_range = \"`RISCV_FORMAL_XLEN-1:0\"\n            opcode = \"0010011\"\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [%s] result = %s;\" % (result_range, expr), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 7'b %s\" % (funct3, opcode))\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        if wmode:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n\n        footer(f)\n\ndef insn_shimm(insn, funct6, funct3, expr, wmode=False, misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_i_shift(f)\n        misa_check(f, misa)\n\n        if wmode:\n            xtra_shamt_check = \"!insn_shamt[5]\"\n            result_range = \"31:0\"\n            opcode = \"0011011\"\n        else:\n            xtra_shamt_check = \"(!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64)\"\n            result_range = \"`RISCV_FORMAL_XLEN-1:0\"\n            opcode = \"0010011\"\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [%s] result = %s;\" % (result_range, expr), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct6 == 6'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b %s && %s\" % (funct6, funct3, opcode, xtra_shamt_check))\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        if wmode:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n\n        footer(f)\n\ndef insn_alu(insn, funct7, funct3, expr, alt_add=None, alt_sub=None, shamt=False, wmode=False, misa=0):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_r(f)\n        misa_check(f, misa)\n\n        if wmode:\n            result_range = \"31:0\"\n            opcode = \"0111011\"\n        else:\n            result_range = \"`RISCV_FORMAL_XLEN-1:0\"\n            opcode = \"0110011\"\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        if shamt:\n            if wmode:\n                print(\"  wire [4:0] shamt = rvfi_rs2_rdata[4:0];\", file=f)\n            else:\n                print(\"  wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0];\", file=f)\n        if alt_add is not None or alt_sub is not None:\n            print(\"`ifdef RISCV_FORMAL_ALTOPS\", file=f)\n            if alt_add is not None:\n                print(\"  wire [%s] altops_bitmask = 64'h%016x;\" % (result_range, alt_add), file=f)\n                print(\"  wire [%s] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask;\" % result_range, file=f)\n            else:\n                print(\"  wire [%s] altops_bitmask = 64'h%016x;\" % (result_range, alt_sub), file=f)\n                print(\"  wire [%s] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\" % result_range, file=f)\n            print(\"`else\", file=f)\n            print(\"  wire [%s] result = %s;\" % (result_range, expr), file=f)\n            print(\"`endif\", file=f)\n        else:\n            print(\"  wire [%s] result = %s;\" % (result_range, expr), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct7 == 7'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b %s\" % (funct7, funct3, opcode))\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        if wmode:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n\n        footer(f)\n\ndef insn_amo(insn, funct5, funct3, expr, misa=MISA_A):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ra(f)\n        misa_check(f, misa)\n\n        if funct3 == \"010\":\n            oprange = \"31:0\"\n            numbytes = 4\n        else:\n            oprange = \"63:0\"\n            numbytes = 8\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [%s] mem_result = %s;\" % (oprange, expr), file=f)\n        print(\"  wire [%s] reg_result = rvfi_mem_rdata[%s];\" % (oprange, oprange), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata;\", file=f)\n\n        print(\"`ifdef RISCV_FORMAL_ALIGNED_MEM\", file=f)\n\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct5 == 5'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b 0101111\" % (funct5, funct3))\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? $signed(reg_result) : 0\")\n        assign(f, \"spec_mem_addr\", \"addr & ~(`RISCV_FORMAL_XLEN/8-1)\")\n        assign(f, \"spec_mem_wmask\", \"((1 << %d)-1) << (addr-spec_mem_addr)\" % numbytes)\n        assign(f, \"spec_mem_wdata\", \"mem_result << (8*(addr-spec_mem_addr))\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n        assign(f, \"spec_trap\", \"((addr & (%d-1)) != 0) || !misa_ok\" % numbytes)\n\n        print(\"`else\", file=f)\n\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct5 == 5'b %s && insn_funct3 == 3'b %s && insn_opcode == 7'b 0101111\" % (funct5, funct3))\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? $signed(reg_result) : 0\")\n        assign(f, \"spec_mem_addr\", \"addr\")\n        assign(f, \"spec_mem_wmask\", \"((1 << %d)-1)\" % numbytes)\n        assign(f, \"spec_mem_wdata\", \"mem_result\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 4\")\n        assign(f, \"spec_trap\", \"((addr & (%d-1)) != 0) || !misa_ok\" % numbytes)\n\n        print(\"`endif\", file=f)\n\n        footer(f)\n\ndef insn_c_addi4spn(insn=\"c_addi4spn\", misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ciw(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 00 && insn_imm\")\n        assign(f, \"spec_rs1_addr\", \"2\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\ndef insn_c_l(insn, funct3, numbytes, signext, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_cl(f, numbytes)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"`ifdef RISCV_FORMAL_ALIGNED_MEM\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        print(\"  wire [%d:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\" % (8*numbytes-1), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 00\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_mem_addr\", \"addr & ~(`RISCV_FORMAL_XLEN/8-1)\")\n        assign(f, \"spec_mem_rmask\", \"((1 << %d)-1) << (addr-spec_mem_addr)\" % numbytes)\n        if signext:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? $signed(result) : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_trap\", \"((addr & (%d-1)) != 0) || !misa_ok\" % numbytes)\n\n        print(\"`else\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        print(\"  wire [%d:0] result = rvfi_mem_rdata;\" % (8*numbytes-1), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 00\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_mem_addr\", \"addr\")\n        assign(f, \"spec_mem_rmask\", \"((1 << %d)-1)\" % numbytes)\n        if signext:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? $signed(result) : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_trap\", \"!misa_ok\")\n\n        print(\"`endif\", file=f)\n\n        footer(f)\n\ndef insn_c_s(insn, funct3, numbytes, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_cs(f, numbytes)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        print(\"`ifdef RISCV_FORMAL_ALIGNED_MEM\", file=f)\n\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 00\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_mem_addr\", \"addr & ~(`RISCV_FORMAL_XLEN/8-1)\")\n        assign(f, \"spec_mem_wmask\", \"((1 << %d)-1) << (addr-spec_mem_addr)\" % numbytes)\n        assign(f, \"spec_mem_wdata\", \"rvfi_rs2_rdata << (8*(addr-spec_mem_addr))\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_trap\", \"((addr & (%d-1)) != 0) || !misa_ok\" % numbytes)\n\n        print(\"`else\", file=f)\n\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 00\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_mem_addr\", \"addr\")\n        assign(f, \"spec_mem_wmask\", \"((1 << %d)-1)\" % numbytes)\n        assign(f, \"spec_mem_wdata\", \"rvfi_rs2_rdata\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_trap\", \"!misa_ok\")\n\n        print(\"`endif\", file=f)\n\n        footer(f)\n\ndef insn_c_addi(insn=\"c_addi\", wmode=False, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ci(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        if wmode:\n            print(\"  wire [31:0] result = rvfi_rs1_rdata[31:0] + insn_imm[31:0];\", file=f)\n            assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 0\")\n        else:\n            print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;\", file=f)\n            assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 01\")\n        assign(f, \"spec_rs1_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_addr\", \"insn_rs1_rd\")\n        if wmode:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\ndef insn_c_jal(insn, funct3, link, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_cj(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 01\" % (funct3))\n        if link:\n            assign(f, \"spec_rd_addr\", \"5'd 1\")\n            assign(f, \"spec_rd_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_pc_wdata\", \"next_pc\")\n\n        footer(f)\n\ndef insn_c_li(insn=\"c_li\", misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ci(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 01\")\n        assign(f, \"spec_rd_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\ndef insn_c_addi16sp(insn=\"c_addi16sp\", misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ci_sp(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd == 5'd 2 && insn_imm\")\n        assign(f, \"spec_rs1_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\ndef insn_c_lui(insn=\"c_lui\", misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ci_lui(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 2 && insn_imm\")\n        assign(f, \"spec_rd_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\ndef insn_c_sri(insn, funct2, expr, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ci_sri(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = %s;\" % expr, file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b %s && insn_opcode == 2'b 01 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64)\" % funct2)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\ndef insn_c_andi(insn=\"c_andi\", misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ci_andi(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 10 && insn_opcode == 2'b 01\")\n        assign(f, \"spec_rs1_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\ndef insn_c_alu(insn, funct6, funct2, expr, wmode=False, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_cs_alu(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        if wmode:\n            print(\"  wire [31:0] result = %s;\" % expr, file=f)\n        else:\n            print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = %s;\" % expr, file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct6 == 6'b %s && insn_funct2 == 2'b %s && insn_opcode == 2'b 01\" % (funct6, funct2))\n        assign(f, \"spec_rs1_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_rd_addr\", \"insn_rs1_rd\")\n        if wmode:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\ndef insn_c_b(insn, funct3, expr, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_cb(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire cond = %s;\" % expr, file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 2;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 01\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1\")\n        assign(f, \"spec_pc_wdata\", \"next_pc\")\n        assign(f, \"spec_trap\", \"(next_pc[0] != 0) || !misa_ok\")\n\n        footer(f)\n\ndef insn_c_sli(insn, expr, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ci_sli(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = %s;\" % expr, file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 10 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64)\")\n        assign(f, \"spec_rs1_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\ndef insn_c_lsp(insn, funct3, numbytes, signext, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_ci_lsp(f, numbytes)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"`ifdef RISCV_FORMAL_ALIGNED_MEM\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        print(\"  wire [%d:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\" % (8*numbytes-1), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 10 && insn_rd\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"2\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_mem_addr\", \"addr & ~(`RISCV_FORMAL_XLEN/8-1)\")\n        assign(f, \"spec_mem_rmask\", \"((1 << %d)-1) << (addr-spec_mem_addr)\" % numbytes)\n        if signext:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? $signed(result) : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_trap\", \"((addr & (%d-1)) != 0) || !misa_ok\" % numbytes)\n\n        print(\"`else\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        print(\"  wire [%d:0] result = rvfi_mem_rdata;\" % (8*numbytes-1), file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 10 && insn_rd\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"2\")\n        assign(f, \"spec_rd_addr\", \"insn_rd\")\n        assign(f, \"spec_mem_addr\", \"addr\")\n        assign(f, \"spec_mem_rmask\", \"((1 << %d)-1)\" % numbytes)\n        if signext:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? $signed(result) : 0\")\n        else:\n            assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_trap\", \"!misa_ok\")\n\n        print(\"`endif\", file=f)\n\n        footer(f)\n\ndef insn_c_ssp(insn, funct3, numbytes, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_css(f, numbytes)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"`ifdef RISCV_FORMAL_ALIGNED_MEM\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 10\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"2\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_mem_addr\", \"addr & ~(`RISCV_FORMAL_XLEN/8-1)\")\n        assign(f, \"spec_mem_wmask\", \"((1 << %d)-1) << (addr-spec_mem_addr)\" % numbytes)\n        assign(f, \"spec_mem_wdata\", \"rvfi_rs2_rdata << (8*(addr-spec_mem_addr))\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_trap\", \"((addr & (%d-1)) != 0) || !misa_ok\" % numbytes)\n\n        print(\"`else\", file=f)\n\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct3 == 3'b %s && insn_opcode == 2'b 10\" % funct3)\n        assign(f, \"spec_rs1_addr\", \"2\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_mem_addr\", \"addr\")\n        assign(f, \"spec_mem_wmask\", \"((1 << %d)-1)\" % numbytes)\n        assign(f, \"spec_mem_wdata\", \"rvfi_rs2_rdata\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_trap\", \"!misa_ok\")\n\n        print(\"`endif\", file=f)\n\n        footer(f)\n\ndef insn_c_jalr(insn, funct4, link, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_cr(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        print(\"  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_rs1_rdata & ~1;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct4 == 4'b %s && insn_rs1_rd && !insn_rs2 && insn_opcode == 2'b 10\" % funct4)\n        assign(f, \"spec_rs1_addr\", \"insn_rs1_rd\")\n        if link:\n            assign(f, \"spec_rd_addr\", \"5'd 1\")\n            assign(f, \"spec_rd_wdata\", \"rvfi_pc_rdata + 2\")\n        assign(f, \"spec_pc_wdata\", \"next_pc\")\n        assign(f, \"spec_trap\", \"(next_pc[0] != 0) || !misa_ok\")\n\n        footer(f)\n\ndef insn_c_mvadd(insn, funct4, add, misa=MISA_C):\n    with open(\"insn_%s.v\" % insn, \"w\") as f:\n        header(f, insn)\n        format_cr(f)\n        misa_check(f, misa)\n\n        print(\"\", file=f)\n        print(\"  // %s instruction\" % insn.upper(), file=f)\n        if add:\n            print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + rvfi_rs2_rdata;\", file=f)\n        else:\n            print(\"  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata;\", file=f)\n        assign(f, \"spec_valid\", \"rvfi_valid && !insn_padding && insn_funct4 == 4'b %s && insn_rs2 && insn_opcode == 2'b 10\" % funct4)\n        if add:\n            assign(f, \"spec_rs1_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rs2_addr\", \"insn_rs2\")\n        assign(f, \"spec_rd_addr\", \"insn_rs1_rd\")\n        assign(f, \"spec_rd_wdata\", \"spec_rd_addr ? result : 0\")\n        assign(f, \"spec_pc_wdata\", \"rvfi_pc_rdata + 2\")\n\n        footer(f)\n\n## Base Integer ISA (I)\n\ncurrent_isa = [\"rv32i\"]\n\ninsn_lui()\ninsn_auipc()\ninsn_jal()\ninsn_jalr()\n\ninsn_b(\"beq\",  \"000\", \"rvfi_rs1_rdata == rvfi_rs2_rdata\")\ninsn_b(\"bne\",  \"001\", \"rvfi_rs1_rdata != rvfi_rs2_rdata\")\ninsn_b(\"blt\",  \"100\", \"$signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata)\")\ninsn_b(\"bge\",  \"101\", \"$signed(rvfi_rs1_rdata) >= $signed(rvfi_rs2_rdata)\")\ninsn_b(\"bltu\", \"110\", \"rvfi_rs1_rdata < rvfi_rs2_rdata\")\ninsn_b(\"bgeu\", \"111\", \"rvfi_rs1_rdata >= rvfi_rs2_rdata\")\n\ninsn_l(\"lb\",  \"000\", 1, True)\ninsn_l(\"lh\",  \"001\", 2, True)\ninsn_l(\"lw\",  \"010\", 4, True)\ninsn_l(\"lbu\", \"100\", 1, False)\ninsn_l(\"lhu\", \"101\", 2, False)\n\ninsn_s(\"sb\",  \"000\", 1)\ninsn_s(\"sh\",  \"001\", 2)\ninsn_s(\"sw\",  \"010\", 4)\n\ninsn_imm(\"addi\",  \"000\", \"rvfi_rs1_rdata + insn_imm\")\ninsn_imm(\"slti\",  \"010\", \"$signed(rvfi_rs1_rdata) < $signed(insn_imm)\")\ninsn_imm(\"sltiu\", \"011\", \"rvfi_rs1_rdata < insn_imm\")\ninsn_imm(\"xori\",  \"100\", \"rvfi_rs1_rdata ^ insn_imm\")\ninsn_imm(\"ori\",   \"110\", \"rvfi_rs1_rdata | insn_imm\")\ninsn_imm(\"andi\",  \"111\", \"rvfi_rs1_rdata & insn_imm\")\n\ninsn_shimm(\"slli\", \"000000\", \"001\", \"rvfi_rs1_rdata << insn_shamt\")\ninsn_shimm(\"srli\", \"000000\", \"101\", \"rvfi_rs1_rdata >> insn_shamt\")\ninsn_shimm(\"srai\", \"010000\", \"101\", \"$signed(rvfi_rs1_rdata) >>> insn_shamt\")\n\ninsn_alu(\"add\",  \"0000000\", \"000\", \"rvfi_rs1_rdata + rvfi_rs2_rdata\")\ninsn_alu(\"sub\",  \"0100000\", \"000\", \"rvfi_rs1_rdata - rvfi_rs2_rdata\")\ninsn_alu(\"sll\",  \"0000000\", \"001\", \"rvfi_rs1_rdata << shamt\", shamt=True)\ninsn_alu(\"slt\",  \"0000000\", \"010\", \"$signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata)\")\ninsn_alu(\"sltu\", \"0000000\", \"011\", \"rvfi_rs1_rdata < rvfi_rs2_rdata\")\ninsn_alu(\"xor\",  \"0000000\", \"100\", \"rvfi_rs1_rdata ^ rvfi_rs2_rdata\")\ninsn_alu(\"srl\",  \"0000000\", \"101\", \"rvfi_rs1_rdata >> shamt\", shamt=True)\ninsn_alu(\"sra\",  \"0100000\", \"101\", \"$signed(rvfi_rs1_rdata) >>> shamt\", shamt=True)\ninsn_alu(\"or\",   \"0000000\", \"110\", \"rvfi_rs1_rdata | rvfi_rs2_rdata\")\ninsn_alu(\"and\",  \"0000000\", \"111\", \"rvfi_rs1_rdata & rvfi_rs2_rdata\")\n\ncurrent_isa = [\"rv64i\"]\n\ninsn_l(\"lwu\", \"110\", 4, False)\ninsn_l(\"ld\",  \"011\", 8, True)\ninsn_s(\"sd\",  \"011\", 8)\n\ninsn_imm(\"addiw\",  \"000\", \"rvfi_rs1_rdata[31:0] + insn_imm[31:0]\", wmode=True)\n\ninsn_shimm(\"slliw\", \"000000\", \"001\", \"rvfi_rs1_rdata[31:0] << insn_shamt\", wmode=True)\ninsn_shimm(\"srliw\", \"000000\", \"101\", \"rvfi_rs1_rdata[31:0] >> insn_shamt\", wmode=True)\ninsn_shimm(\"sraiw\", \"010000\", \"101\", \"$signed(rvfi_rs1_rdata[31:0]) >>> insn_shamt\", wmode=True)\n\ninsn_alu(\"addw\", \"0000000\", \"000\", \"rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0]\", wmode=True)\ninsn_alu(\"subw\", \"0100000\", \"000\", \"rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0]\", wmode=True)\ninsn_alu(\"sllw\", \"0000000\", \"001\", \"rvfi_rs1_rdata[31:0] << shamt\", shamt=True, wmode=True)\ninsn_alu(\"srlw\", \"0000000\", \"101\", \"rvfi_rs1_rdata[31:0] >> shamt\", shamt=True, wmode=True)\ninsn_alu(\"sraw\", \"0100000\", \"101\", \"$signed(rvfi_rs1_rdata[31:0]) >>> shamt\", shamt=True, wmode=True)\n\n## Multiply/Divide ISA (M)\n\ncurrent_isa = [\"rv32im\"]\n\ninsn_alu(\"mul\",    \"0000001\", \"000\", \"rvfi_rs1_rdata * rvfi_rs2_rdata\", alt_add=0x2cdf52a55876063e, misa=MISA_M)\ninsn_alu(\"mulh\",   \"0000001\", \"001\", \"({{`RISCV_FORMAL_XLEN{rvfi_rs1_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs1_rdata} *\\n\" +\n        \"\\t\\t{{`RISCV_FORMAL_XLEN{rvfi_rs2_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN\", alt_add=0x15d01651f6583fb7, misa=MISA_M)\ninsn_alu(\"mulhsu\", \"0000001\", \"010\", \"({{`RISCV_FORMAL_XLEN{rvfi_rs1_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs1_rdata} *\\n\" +\n        \"\\t\\t{`RISCV_FORMAL_XLEN'b0, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN\", alt_sub=0xea3969edecfbe137, misa=MISA_M)\ninsn_alu(\"mulhu\",  \"0000001\", \"011\", \"({`RISCV_FORMAL_XLEN'b0, rvfi_rs1_rdata} * {`RISCV_FORMAL_XLEN'b0, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN\", alt_add=0xd13db50d949ce5e8, misa=MISA_M)\n\ninsn_alu(\"div\",    \"0000001\", \"100\", \"\"\"rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? {`RISCV_FORMAL_XLEN{1'b1}} :\n                                         rvfi_rs1_rdata == {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} && rvfi_rs2_rdata == {`RISCV_FORMAL_XLEN{1'b1}} ? {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} :\n                                         $signed(rvfi_rs1_rdata) / $signed(rvfi_rs2_rdata)\"\"\", alt_sub=0x29bbf66f7f8529ec, misa=MISA_M)\n\ninsn_alu(\"divu\",   \"0000001\", \"101\", \"\"\"rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? {`RISCV_FORMAL_XLEN{1'b1}} :\n                                         rvfi_rs1_rdata / rvfi_rs2_rdata\"\"\", alt_sub=0x8c629acb10e8fd70, misa=MISA_M)\n\ninsn_alu(\"rem\",    \"0000001\", \"110\", \"\"\"rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? rvfi_rs1_rdata :\n                                         rvfi_rs1_rdata == {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} && rvfi_rs2_rdata == {`RISCV_FORMAL_XLEN{1'b1}} ? {`RISCV_FORMAL_XLEN{1'b0}} :\n                                         $signed(rvfi_rs1_rdata) % $signed(rvfi_rs2_rdata)\"\"\", alt_sub=0xf5b7d8538da68fa5, misa=MISA_M)\n\ninsn_alu(\"remu\",   \"0000001\", \"111\", \"\"\"rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? rvfi_rs1_rdata :\n                                         rvfi_rs1_rdata % rvfi_rs2_rdata\"\"\", alt_sub=0xbc4402413138d0e1, misa=MISA_M)\n\ncurrent_isa = [\"rv64im\"]\n\ninsn_alu(\"mulw\",    \"0000001\", \"000\", \"rvfi_rs1_rdata[31:0] * rvfi_rs2_rdata[31:0]\", alt_add=0x2cdf52a55876063e, wmode=True, misa=MISA_M)\n\ninsn_alu(\"divw\",    \"0000001\", \"100\", \"\"\"rvfi_rs2_rdata[31:0] == 32'b0 ? {32{1'b1}} :\n                       rvfi_rs1_rdata == {1'b1, {31{1'b0}}} && rvfi_rs2_rdata == {32{1'b1}} ? {1'b1, {31{1'b0}}} :\n                       $signed(rvfi_rs1_rdata[31:0]) / $signed(rvfi_rs2_rdata[31:0])\"\"\", alt_sub=0x29bbf66f7f8529ec, wmode=True, misa=MISA_M)\n\ninsn_alu(\"divuw\",   \"0000001\", \"101\", \"\"\"rvfi_rs2_rdata[31:0] == 32'b0 ? {32{1'b1}} :\n                       rvfi_rs1_rdata[31:0] / rvfi_rs2_rdata[31:0]\"\"\", alt_sub=0x8c629acb10e8fd70, wmode=True, misa=MISA_M)\n\ninsn_alu(\"remw\",    \"0000001\", \"110\", \"\"\"rvfi_rs2_rdata == 32'b0 ? rvfi_rs1_rdata :\n                       rvfi_rs1_rdata == {1'b1, {31{1'b0}}} && rvfi_rs2_rdata == {32{1'b1}} ? {32{1'b0}} :\n                       $signed(rvfi_rs1_rdata[31:0]) % $signed(rvfi_rs2_rdata[31:0])\"\"\", alt_sub=0xf5b7d8538da68fa5, wmode=True, misa=MISA_M)\n\ninsn_alu(\"remuw\",   \"0000001\", \"111\", \"\"\"rvfi_rs2_rdata == 32'b0 ? rvfi_rs1_rdata :\n                       rvfi_rs1_rdata[31:0] % rvfi_rs2_rdata[31:0]\"\"\", alt_sub=0xbc4402413138d0e1, wmode=True, misa=MISA_M)\n\n## Atomics ISA (A)\n\n# current_isa = [\"rv32ia\"]\n\n# FIXME: LR.W / SC.W\n# insn_amo(\"amoswap_w\", \"00001\", \"010\", \"rvfi_rs2_rdata[31:0]\")\n# insn_amo(\"amoadd_w\",  \"00000\", \"010\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : rvfi_mem_rdata + rvfi_rs2_rdata[31:0]\")\n# insn_amo(\"amoxor_w\",  \"00100\", \"010\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : rvfi_mem_rdata ^ rvfi_rs2_rdata[31:0]\")\n# insn_amo(\"amoand_w\",  \"01100\", \"010\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : rvfi_mem_rdata & rvfi_rs2_rdata[31:0]\")\n# insn_amo(\"amoor_w\",   \"01000\", \"010\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : rvfi_mem_rdata | rvfi_rs2_rdata[31:0]\")\n# insn_amo(\"amomin_w\",  \"10000\", \"010\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : ($signed(rvfi_mem_rdata) < $signed(rvfi_rs2_rdata[31:0]) ? rvfi_mem_rdata : rvfi_rs2_rdata[31:0])\")\n# insn_amo(\"amomax_w\",  \"10100\", \"010\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : ($signed(rvfi_mem_rdata) > $signed(rvfi_rs2_rdata[31:0]) ? rvfi_mem_rdata : rvfi_rs2_rdata[31:0])\")\n# insn_amo(\"amominu_w\", \"11000\", \"010\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : (rvfi_mem_rdata < rvfi_rs2_rdata[31:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[31:0])\")\n# insn_amo(\"amomaxu_w\", \"11100\", \"010\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[31:0] : (rvfi_mem_rdata > rvfi_rs2_rdata[31:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[31:0])\")\n\n# current_isa = [\"rv64ia\"]\n\n# FIXME: LR.D / SC.D\n# insn_amo(\"amoswap_d\", \"00001\", \"011\", \"rvfi_rs2_rdata[63:0]\")\n# insn_amo(\"amoadd_d\",  \"00000\", \"011\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : rvfi_mem_rdata + rvfi_rs2_rdata[63:0]\")\n# insn_amo(\"amoxor_d\",  \"00100\", \"011\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : rvfi_mem_rdata ^ rvfi_rs2_rdata[63:0]\")\n# insn_amo(\"amoand_d\",  \"01100\", \"011\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : rvfi_mem_rdata & rvfi_rs2_rdata[63:0]\")\n# insn_amo(\"amoor_d\",   \"01000\", \"011\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : rvfi_mem_rdata | rvfi_rs2_rdata[63:0]\")\n# insn_amo(\"amomin_d\",  \"10000\", \"011\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : ($signed(rvfi_mem_rdata) < $signed(rvfi_rs2_rdata[63:0]) ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])\")\n# insn_amo(\"amomax_d\",  \"10100\", \"011\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : ($signed(rvfi_mem_rdata) > $signed(rvfi_rs2_rdata[63:0]) ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])\")\n# insn_amo(\"amominu_d\", \"11000\", \"011\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : (rvfi_mem_rdata < rvfi_rs2_rdata[63:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])\")\n# insn_amo(\"amomaxu_d\", \"11100\", \"011\", \"rvfi_mem_extamo ? rvfi_rs2_rdata[63:0] : (rvfi_mem_rdata > rvfi_rs2_rdata[63:0] ? rvfi_mem_rdata : rvfi_rs2_rdata[63:0])\")\n\n## Compressed Integer ISA (IC)\n\ncurrent_isa = [\"rv32ic\"]\n\ninsn_c_addi4spn()\ninsn_c_l(\"c_lw\", \"010\", 4, True)\ninsn_c_s(\"c_sw\", \"110\", 4)\ninsn_c_addi()\ninsn_c_jal(\"c_jal\", \"001\", True)\ninsn_c_li()\ninsn_c_addi16sp()\ninsn_c_lui()\ninsn_c_sri(\"c_srli\", \"00\", \"rvfi_rs1_rdata >> insn_shamt\")\ninsn_c_sri(\"c_srai\", \"01\", \"$signed(rvfi_rs1_rdata) >>> insn_shamt\")\ninsn_c_andi()\ninsn_c_alu(\"c_sub\", \"100011\", \"00\", \"rvfi_rs1_rdata - rvfi_rs2_rdata\")\ninsn_c_alu(\"c_xor\", \"100011\", \"01\", \"rvfi_rs1_rdata ^ rvfi_rs2_rdata\")\ninsn_c_alu(\"c_or\",  \"100011\", \"10\", \"rvfi_rs1_rdata | rvfi_rs2_rdata\")\ninsn_c_alu(\"c_and\", \"100011\", \"11\", \"rvfi_rs1_rdata & rvfi_rs2_rdata\")\ninsn_c_jal(\"c_j\", \"101\", False)\ninsn_c_b(\"c_beqz\", \"110\", \"rvfi_rs1_rdata == 0\")\ninsn_c_b(\"c_bnez\", \"111\", \"rvfi_rs1_rdata != 0\")\ninsn_c_sli(\"c_slli\", \"rvfi_rs1_rdata << insn_shamt\")\ninsn_c_lsp(\"c_lwsp\", \"010\", 4, True)\ninsn_c_jalr(\"c_jr\", \"1000\", False)\ninsn_c_mvadd(\"c_mv\", \"1000\", False)\ninsn_c_jalr(\"c_jalr\", \"1001\", True)\ninsn_c_mvadd(\"c_add\", \"1001\", True)\ninsn_c_ssp(\"c_swsp\", \"110\", 4)\n\ncurrent_isa = [\"rv64ic\"]\n\ninsn_c_addi(\"c_addiw\", wmode=True)\ninsn_c_alu(\"c_subw\", \"100111\", \"00\", \"rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0]\", wmode=True)\ninsn_c_alu(\"c_addw\", \"100111\", \"01\", \"rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0]\", wmode=True)\n\ninsn_c_l(\"c_ld\", \"011\", 8, True)\ninsn_c_s(\"c_sd\", \"111\", 8)\ninsn_c_lsp(\"c_ldsp\", \"011\", 8, True)\ninsn_c_ssp(\"c_sdsp\", \"111\", 8)\n\n## ISA Propagate\n\ndef isa_propagate_pair(from_isa, to_isa):\n     global isa_database\n     assert from_isa in isa_database\n     if to_isa not in isa_database:\n         isa_database[to_isa] = set()\n     isa_database[to_isa] |= isa_database[from_isa]\n\ndef isa_propagate(suffix):\n    for i in range(2 ** len(suffix)):\n        src = \"\"\n        for k in range(len(suffix)):\n            if ((i >> k) & 1) == 0:\n                src += suffix[k]\n        if src != suffix:\n            isa_propagate_pair(\"rv32i\"+src, \"rv32i\"+suffix)\n            isa_propagate_pair(\"rv64i\"+src, \"rv64i\"+suffix)\n    isa_propagate_pair(\"rv32i\"+suffix, \"rv64i\"+suffix)\n\nisa_propagate(\"\")\nisa_propagate(\"c\")\nisa_propagate(\"m\")\nisa_propagate(\"mc\")\n\n## ISA Fixup\n\nfor isa, insns in isa_database.items():\n    if isa.startswith(\"rv64\"):\n        insns.discard(\"c_jal\")\n\n## ISA Listings and ISA Models\n\nfor isa, insns in isa_database.items():\n    with open(\"isa_%s.txt\" % isa, \"w\") as f:\n        for insn in sorted(insns):\n            print(insn, file=f)\n\n    with open(\"isa_%s.v\" % isa, \"w\") as f:\n        header(f, isa, isa_mode=True)\n\n        for insn in sorted(insns):\n            print(\"  wire                                spec_insn_%s_valid;\"     % insn, file=f)\n            print(\"  wire                                spec_insn_%s_trap;\"      % insn, file=f)\n            print(\"  wire [                       4 : 0] spec_insn_%s_rs1_addr;\"  % insn, file=f)\n            print(\"  wire [                       4 : 0] spec_insn_%s_rs2_addr;\"  % insn, file=f)\n            print(\"  wire [                       4 : 0] spec_insn_%s_rd_addr;\"   % insn, file=f)\n            print(\"  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_%s_rd_wdata;\"  % insn, file=f)\n            print(\"  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_%s_pc_wdata;\"  % insn, file=f)\n            print(\"  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_%s_mem_addr;\"  % insn, file=f)\n            print(\"  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_%s_mem_rmask;\" % insn, file=f)\n            print(\"  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_%s_mem_wmask;\" % insn, file=f)\n            print(\"  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_%s_mem_wdata;\"  % insn, file=f)\n            print(\"`ifdef RISCV_FORMAL_CSR_MISA\", file=f)\n            print(\"  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_%s_csr_misa_rmask;\" % insn, file=f)\n            print(\"`endif\", file=f)\n            print(\"\", file=f)\n            print(\"  rvfi_insn_%s insn_%s (\" % (insn, insn), file=f)\n            print(\"    .rvfi_valid(rvfi_valid),\", file=f)\n            print(\"    .rvfi_insn(rvfi_insn),\", file=f)\n            print(\"    .rvfi_pc_rdata(rvfi_pc_rdata),\", file=f)\n            print(\"    .rvfi_rs1_rdata(rvfi_rs1_rdata),\", file=f)\n            print(\"    .rvfi_rs2_rdata(rvfi_rs2_rdata),\", file=f)\n            print(\"    .rvfi_mem_rdata(rvfi_mem_rdata),\", file=f)\n            print(\"`ifdef RISCV_FORMAL_CSR_MISA\", file=f)\n            print(\"    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\", file=f)\n            print(\"    .spec_csr_misa_rmask(spec_insn_%s_csr_misa_rmask),\" % insn, file=f)\n            print(\"`endif\", file=f)\n            print(\"    .spec_valid(spec_insn_%s_valid),\" % insn, file=f)\n            print(\"    .spec_trap(spec_insn_%s_trap),\" % insn, file=f)\n            print(\"    .spec_rs1_addr(spec_insn_%s_rs1_addr),\" % insn, file=f)\n            print(\"    .spec_rs2_addr(spec_insn_%s_rs2_addr),\" % insn, file=f)\n            print(\"    .spec_rd_addr(spec_insn_%s_rd_addr),\" % insn, file=f)\n            print(\"    .spec_rd_wdata(spec_insn_%s_rd_wdata),\" % insn, file=f)\n            print(\"    .spec_pc_wdata(spec_insn_%s_pc_wdata),\" % insn, file=f)\n            print(\"    .spec_mem_addr(spec_insn_%s_mem_addr),\" % insn, file=f)\n            print(\"    .spec_mem_rmask(spec_insn_%s_mem_rmask),\" % insn, file=f)\n            print(\"    .spec_mem_wmask(spec_insn_%s_mem_wmask),\" % insn, file=f)\n            print(\"    .spec_mem_wdata(spec_insn_%s_mem_wdata)\" % insn, file=f)\n            print(\"  );\", file=f)\n            print(\"\", file=f)\n\n        for port in [\"valid\", \"trap\", \"rs1_addr\", \"rs2_addr\", \"rd_addr\", \"rd_wdata\", \"pc_wdata\", \"mem_addr\", \"mem_rmask\", \"mem_wmask\", \"mem_wdata\"]:\n            print(\"  assign spec_%s =\\n\\t\\t%s : 0;\" % (port, \" :\\n\\t\\t\".join([\"spec_insn_%s_valid ? spec_insn_%s_%s\" % (insn, insn, port) for insn in sorted(insns)])), file=f)\n\n        print(\"`ifdef RISCV_FORMAL_CSR_MISA\", file=f)\n        print(\"  assign spec_csr_misa_rmask =\\n\\t\\t%s : 0;\" % (\" :\\n\\t\\t\".join([\"spec_insn_%s_valid ? spec_insn_%s_csr_misa_rmask\" % (insn, insn) for insn in sorted(insns)])), file=f)\n        print(\"`endif\", file=f)\n\n        print(\"endmodule\", file=f)\n"
  },
  {
    "path": "insns/insn_add.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_add (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // ADD instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_addi.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_addi (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // ADDI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0010011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_addiw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_addiw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // ADDIW instruction\n  wire [31:0] result = rvfi_rs1_rdata[31:0] + insn_imm[31:0];\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0011011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_addw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_addw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // ADDW instruction\n  wire [31:0] result = rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0];\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_and.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_and (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // AND instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_andi.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_andi (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // ANDI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0010011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_auipc.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_auipc (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // U-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:12], 12'b0});\n  wire [4:0] insn_rd     = rvfi_insn[11:7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // AUIPC instruction\n  assign spec_valid = rvfi_valid && !insn_padding && insn_opcode == 7'b 0010111;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? rvfi_pc_rdata + insn_imm : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs1_addr = 0;\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_beq.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_beq (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // SB-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n  wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`ifdef RISCV_FORMAL_COMPRESSED\n  wire ialign16 = 1;\n`else\n  wire ialign16 = 0;\n`endif\n`endif\n\n  // BEQ instruction\n  wire cond = rvfi_rs1_rdata == rvfi_rs2_rdata;\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 1100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok;\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_bge.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_bge (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // SB-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n  wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`ifdef RISCV_FORMAL_COMPRESSED\n  wire ialign16 = 1;\n`else\n  wire ialign16 = 0;\n`endif\n`endif\n\n  // BGE instruction\n  wire cond = $signed(rvfi_rs1_rdata) >= $signed(rvfi_rs2_rdata);\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 101 && insn_opcode == 7'b 1100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok;\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_bgeu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_bgeu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // SB-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n  wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`ifdef RISCV_FORMAL_COMPRESSED\n  wire ialign16 = 1;\n`else\n  wire ialign16 = 0;\n`endif\n`endif\n\n  // BGEU instruction\n  wire cond = rvfi_rs1_rdata >= rvfi_rs2_rdata;\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 7'b 1100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok;\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_blt.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_blt (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // SB-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n  wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`ifdef RISCV_FORMAL_COMPRESSED\n  wire ialign16 = 1;\n`else\n  wire ialign16 = 0;\n`endif\n`endif\n\n  // BLT instruction\n  wire cond = $signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata);\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_opcode == 7'b 1100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok;\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_bltu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_bltu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // SB-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n  wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`ifdef RISCV_FORMAL_COMPRESSED\n  wire ialign16 = 1;\n`else\n  wire ialign16 = 0;\n`endif\n`endif\n\n  // BLTU instruction\n  wire cond = rvfi_rs1_rdata < rvfi_rs2_rdata;\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 7'b 1100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok;\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_bne.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_bne (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // SB-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n  wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`ifdef RISCV_FORMAL_COMPRESSED\n  wire ialign16 = 1;\n`else\n  wire ialign16 = 0;\n`endif\n`endif\n\n  // BNE instruction\n  wire cond = rvfi_rs1_rdata != rvfi_rs2_rdata;\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 4;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 7'b 1100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok;\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_add.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_add (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [3:0] insn_funct4 = rvfi_insn[15:12];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [4:0] insn_rs2 = rvfi_insn[6:2];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_ADD instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1001 && insn_rs2 && insn_opcode == 2'b 10;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_addi.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_addi (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_ADDI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_addi16sp.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_addi16sp (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format (SP variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[4:3], rvfi_insn[5], rvfi_insn[2], rvfi_insn[6], 4'b0});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_ADDI16SP instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd == 5'd 2 && insn_imm;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_addi4spn.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_addi4spn (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CIW-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[10:7], rvfi_insn[12:11], rvfi_insn[5], rvfi_insn[6], 2'b00};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_ADDI4SPN instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 00 && insn_imm;\n  assign spec_rs1_addr = 2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_addiw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_addiw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_ADDIW instruction\n  wire [31:0] result = rvfi_rs1_rdata[31:0] + insn_imm[31:0];\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 0;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_addw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_addw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CS-type instruction format (ALU version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [5:0] insn_funct6 = rvfi_insn[15:10];\n  wire [1:0] insn_funct2 = rvfi_insn[6:5];\n  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_ADDW instruction\n  wire [31:0] result = rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0];\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100111 && insn_funct2 == 2'b 01 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_and.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_and (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CS-type instruction format (ALU version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [5:0] insn_funct6 = rvfi_insn[15:10];\n  wire [1:0] insn_funct2 = rvfi_insn[6:5];\n  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_AND instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 11 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_andi.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_andi (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format (ANDI variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [1:0] insn_funct2 = rvfi_insn[11:10];\n  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_ANDI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 10 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_beqz.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_beqz (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CB-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:5], rvfi_insn[2], rvfi_insn[11:10], rvfi_insn[4:3], 1'b0});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_BEQZ instruction\n  wire cond = rvfi_rs1_rdata == 0;\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 2;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (next_pc[0] != 0) || !misa_ok;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_bnez.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_bnez (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CB-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:5], rvfi_insn[2], rvfi_insn[11:10], rvfi_insn[4:3], 1'b0});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_BNEZ instruction\n  wire cond = rvfi_rs1_rdata != 0;\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 2;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (next_pc[0] != 0) || !misa_ok;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_j.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_j (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CJ-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[8], rvfi_insn[10], rvfi_insn[9],\n      rvfi_insn[6], rvfi_insn[7], rvfi_insn[2], rvfi_insn[11], rvfi_insn[5], rvfi_insn[4], rvfi_insn[3], 1'b0});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_J instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 101 && insn_opcode == 2'b 01;\n  assign spec_pc_wdata = next_pc;\n\n  // default assignments\n  assign spec_rs1_addr = 0;\n  assign spec_rs2_addr = 0;\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_jal.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_jal (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CJ-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[8], rvfi_insn[10], rvfi_insn[9],\n      rvfi_insn[6], rvfi_insn[7], rvfi_insn[2], rvfi_insn[11], rvfi_insn[5], rvfi_insn[4], rvfi_insn[3], 1'b0});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_JAL instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 2'b 01;\n  assign spec_rd_addr = 5'd 1;\n  assign spec_rd_wdata = rvfi_pc_rdata + 2;\n  assign spec_pc_wdata = next_pc;\n\n  // default assignments\n  assign spec_rs1_addr = 0;\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_jalr.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_jalr (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [3:0] insn_funct4 = rvfi_insn[15:12];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [4:0] insn_rs2 = rvfi_insn[6:2];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_JALR instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_rs1_rdata & ~1;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1001 && insn_rs1_rd && !insn_rs2 && insn_opcode == 2'b 10;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rd_addr = 5'd 1;\n  assign spec_rd_wdata = rvfi_pc_rdata + 2;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (next_pc[0] != 0) || !misa_ok;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_jr.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_jr (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [3:0] insn_funct4 = rvfi_insn[15:12];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [4:0] insn_rs2 = rvfi_insn[6:2];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_JR instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_rs1_rdata & ~1;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1000 && insn_rs1_rd && !insn_rs2 && insn_opcode == 2'b 10;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (next_pc[0] != 0) || !misa_ok;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_ld.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_ld (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CL-type instruction format (64 bit version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[6:5], rvfi_insn[12:10], 3'b000};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_LD instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [63:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 00;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 8)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [63:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 00;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 8)-1);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_ldsp.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_ldsp (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format (LSP variation, 64 bit version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[4:2], rvfi_insn[12], rvfi_insn[6:5], 3'b000};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rd = rvfi_insn[11:7];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_LDSP instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [63:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 10 && insn_rd;\n  assign spec_rs1_addr = 2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 8)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [63:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 10 && insn_rd;\n  assign spec_rs1_addr = 2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 8)-1);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_li.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_li (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_LI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 01;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs1_addr = 0;\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_lui.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_lui (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format (LUI variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2], 12'b0});\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_LUI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 2 && insn_imm;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs1_addr = 0;\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_lw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_lw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CL-type instruction format (32 bit version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_LW instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [31:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 00;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 4)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [31:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 00;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 4)-1);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_lwsp.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_lwsp (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format (LSP variation, 32 bit version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[3:2], rvfi_insn[12], rvfi_insn[6:4], 2'b00};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rd = rvfi_insn[11:7];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_LWSP instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [31:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 10 && insn_rd;\n  assign spec_rs1_addr = 2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 4)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [31:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 10 && insn_rd;\n  assign spec_rs1_addr = 2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 4)-1);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_mv.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_mv (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [3:0] insn_funct4 = rvfi_insn[15:12];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [4:0] insn_rs2 = rvfi_insn[6:2];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_MV instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1000 && insn_rs2 && insn_opcode == 2'b 10;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs1_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_or.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_or (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CS-type instruction format (ALU version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [5:0] insn_funct6 = rvfi_insn[15:10];\n  wire [1:0] insn_funct2 = rvfi_insn[6:5];\n  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_OR instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 10 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_sd.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_sd (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CS-type instruction format (64 bit version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[6:5], rvfi_insn[12:10], 3'b000};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_SD instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 00;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_wmask = ((1 << 8)-1) << (addr-spec_mem_addr);\n  assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr));\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok;\n`else\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 00;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr;\n  assign spec_mem_wmask = ((1 << 8)-1);\n  assign spec_mem_wdata = rvfi_rs2_rdata;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_rmask = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_sdsp.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_sdsp (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CSS-type instruction format (64 bit version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[9:7], rvfi_insn[12:10], 3'b000};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs2 = rvfi_insn[6:2];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_SDSP instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 10;\n  assign spec_rs1_addr = 2;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_wmask = ((1 << 8)-1) << (addr-spec_mem_addr);\n  assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr));\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 10;\n  assign spec_rs1_addr = 2;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr;\n  assign spec_mem_wmask = ((1 << 8)-1);\n  assign spec_mem_wdata = rvfi_rs2_rdata;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_rmask = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_slli.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_slli (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format (SLI variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1_rd = rvfi_insn[11:7];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_SLLI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata << insn_shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 10 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64);\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_srai.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_srai (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format (SRI variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [1:0] insn_funct2 = rvfi_insn[11:10];\n  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_SRAI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) >>> insn_shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 01 && insn_opcode == 2'b 01 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64);\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_srli.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_srli (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CI-type instruction format (SRI variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [1:0] insn_funct2 = rvfi_insn[11:10];\n  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_SRLI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata >> insn_shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 00 && insn_opcode == 2'b 01 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64);\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_sub.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_sub (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CS-type instruction format (ALU version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [5:0] insn_funct6 = rvfi_insn[15:10];\n  wire [1:0] insn_funct2 = rvfi_insn[6:5];\n  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_SUB instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata - rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 00 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_subw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_subw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CS-type instruction format (ALU version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [5:0] insn_funct6 = rvfi_insn[15:10];\n  wire [1:0] insn_funct2 = rvfi_insn[6:5];\n  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_SUBW instruction\n  wire [31:0] result = rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0];\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100111 && insn_funct2 == 2'b 00 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_sw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_sw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CS-type instruction format (32 bit version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_SW instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 00;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_wmask = ((1 << 4)-1) << (addr-spec_mem_addr);\n  assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr));\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok;\n`else\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 00;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr;\n  assign spec_mem_wmask = ((1 << 4)-1);\n  assign spec_mem_wdata = rvfi_rs2_rdata;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_rmask = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_swsp.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_swsp (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CSS-type instruction format (32 bit version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[8:7], rvfi_insn[12:9], 2'b00};\n  wire [2:0] insn_funct3 = rvfi_insn[15:13];\n  wire [4:0] insn_rs2 = rvfi_insn[6:2];\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_SWSP instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 10;\n  assign spec_rs1_addr = 2;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_wmask = ((1 << 4)-1) << (addr-spec_mem_addr);\n  assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr));\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 10;\n  assign spec_rs1_addr = 2;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr;\n  assign spec_mem_wmask = ((1 << 4)-1);\n  assign spec_mem_wdata = rvfi_rs2_rdata;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_rmask = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_c_xor.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_c_xor (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // CS-type instruction format (ALU version)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16;\n  wire [5:0] insn_funct6 = rvfi_insn[15:10];\n  wire [1:0] insn_funct2 = rvfi_insn[6:5];\n  wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]};\n  wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]};\n  wire [1:0] insn_opcode = rvfi_insn[1:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // C_XOR instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 01 && insn_opcode == 2'b 01;\n  assign spec_rs1_addr = insn_rs1_rd;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rs1_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 2;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_div.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_div (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // DIV instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'h29bbf66f7f8529ec;\n  wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? {`RISCV_FORMAL_XLEN{1'b1}} :\n                                         rvfi_rs1_rdata == {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} && rvfi_rs2_rdata == {`RISCV_FORMAL_XLEN{1'b1}} ? {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} :\n                                         $signed(rvfi_rs1_rdata) / $signed(rvfi_rs2_rdata);\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_divu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_divu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // DIVU instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'h8c629acb10e8fd70;\n  wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? {`RISCV_FORMAL_XLEN{1'b1}} :\n                                         rvfi_rs1_rdata / rvfi_rs2_rdata;\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_divuw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_divuw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // DIVUW instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [31:0] altops_bitmask = 64'h8c629acb10e8fd70;\n  wire [31:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [31:0] result = rvfi_rs2_rdata[31:0] == 32'b0 ? {32{1'b1}} :\n                       rvfi_rs1_rdata[31:0] / rvfi_rs2_rdata[31:0];\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_divw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_divw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // DIVW instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [31:0] altops_bitmask = 64'h29bbf66f7f8529ec;\n  wire [31:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [31:0] result = rvfi_rs2_rdata[31:0] == 32'b0 ? {32{1'b1}} :\n                       rvfi_rs1_rdata == {1'b1, {31{1'b0}}} && rvfi_rs2_rdata == {32{1'b1}} ? {1'b1, {31{1'b0}}} :\n                       $signed(rvfi_rs1_rdata[31:0]) / $signed(rvfi_rs2_rdata[31:0]);\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_jal.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_jal (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // UJ-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31], rvfi_insn[19:12], rvfi_insn[20], rvfi_insn[30:21], 1'b0});\n  wire [4:0] insn_rd     = rvfi_insn[11:7];\n  wire [6:0] insn_opcode = rvfi_insn[6:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n  wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`ifdef RISCV_FORMAL_COMPRESSED\n  wire ialign16 = 1;\n`else\n  wire ialign16 = 0;\n`endif\n`endif\n\n  // JAL instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_opcode == 7'b 1101111;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? rvfi_pc_rdata + 4 : 0;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok;\n\n  // default assignments\n  assign spec_rs1_addr = 0;\n  assign spec_rs2_addr = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_jalr.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_jalr (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4;\n  wire ialign16 = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) != `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`ifdef RISCV_FORMAL_COMPRESSED\n  wire ialign16 = 1;\n`else\n  wire ialign16 = 0;\n`endif\n`endif\n\n  // JALR instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] next_pc = (rvfi_rs1_rdata + insn_imm) & ~1;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 1100111;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? rvfi_pc_rdata + 4 : 0;\n  assign spec_pc_wdata = next_pc;\n  assign spec_trap = (ialign16 ? (next_pc[0] != 0) : (next_pc[1:0] != 0)) || !misa_ok;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_lb.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_lb (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // LB instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [7:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 1)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (1-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [7:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 1)-1);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_lbu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_lbu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // LBU instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [7:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 1)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (1-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [7:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 1)-1);\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_ld.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_ld (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // LD instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [63:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 8)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [63:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 8)-1);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_lh.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_lh (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // LH instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [15:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 2)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (2-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [15:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 2)-1);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_lhu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_lhu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // LHU instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [15:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 2)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (2-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [15:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 2)-1);\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_lui.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_lui (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // U-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:12], 12'b0});\n  wire [4:0] insn_rd     = rvfi_insn[11:7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6:0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // LUI instruction\n  assign spec_valid = rvfi_valid && !insn_padding && insn_opcode == 7'b 0110111;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? insn_imm : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs1_addr = 0;\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_lw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_lw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // LW instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [31:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 4)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [31:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 4)-1);\n  assign spec_rd_wdata = spec_rd_addr ? $signed(result) : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_lwu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_lwu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // LWU instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [31:0] result = rvfi_mem_rdata >> (8*(addr-spec_mem_addr));\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_rmask = ((1 << 4)-1) << (addr-spec_mem_addr);\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  wire [31:0] result = rvfi_mem_rdata;\n  assign spec_valid = rvfi_valid && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0000011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_mem_addr = addr;\n  assign spec_mem_rmask = ((1 << 4)-1);\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_mul.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_mul (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // MUL instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'h2cdf52a55876063e;\n  wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata * rvfi_rs2_rdata;\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_mulh.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_mulh (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // MULH instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'h15d01651f6583fb7;\n  wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] result = ({{`RISCV_FORMAL_XLEN{rvfi_rs1_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs1_rdata} *\n\t\t{{`RISCV_FORMAL_XLEN{rvfi_rs2_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN;\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_mulhsu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_mulhsu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // MULHSU instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'hea3969edecfbe137;\n  wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] result = ({{`RISCV_FORMAL_XLEN{rvfi_rs1_rdata[`RISCV_FORMAL_XLEN-1]}}, rvfi_rs1_rdata} *\n\t\t{`RISCV_FORMAL_XLEN'b0, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN;\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_mulhu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_mulhu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // MULHU instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'hd13db50d949ce5e8;\n  wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] result = ({`RISCV_FORMAL_XLEN'b0, rvfi_rs1_rdata} * {`RISCV_FORMAL_XLEN'b0, rvfi_rs2_rdata}) >> `RISCV_FORMAL_XLEN;\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_mulw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_mulw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // MULW instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [31:0] altops_bitmask = 64'h2cdf52a55876063e;\n  wire [31:0] result = (rvfi_rs1_rdata + rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [31:0] result = rvfi_rs1_rdata[31:0] * rvfi_rs2_rdata[31:0];\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_or.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_or (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // OR instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_ori.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_ori (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // ORI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0010011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_rem.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_rem (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // REM instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'hf5b7d8538da68fa5;\n  wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? rvfi_rs1_rdata :\n                                         rvfi_rs1_rdata == {1'b1, {`RISCV_FORMAL_XLEN-1{1'b0}}} && rvfi_rs2_rdata == {`RISCV_FORMAL_XLEN{1'b1}} ? {`RISCV_FORMAL_XLEN{1'b0}} :\n                                         $signed(rvfi_rs1_rdata) % $signed(rvfi_rs2_rdata);\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_remu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_remu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // REMU instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [`RISCV_FORMAL_XLEN-1:0] altops_bitmask = 64'hbc4402413138d0e1;\n  wire [`RISCV_FORMAL_XLEN-1:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata == `RISCV_FORMAL_XLEN'b0 ? rvfi_rs1_rdata :\n                                         rvfi_rs1_rdata % rvfi_rs2_rdata;\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_remuw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_remuw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // REMUW instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [31:0] altops_bitmask = 64'hbc4402413138d0e1;\n  wire [31:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [31:0] result = rvfi_rs2_rdata == 32'b0 ? rvfi_rs1_rdata :\n                       rvfi_rs1_rdata[31:0] % rvfi_rs2_rdata[31:0];\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_remw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_remw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 1000) == `RISCV_FORMAL_XLEN'h 1000;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 1000;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // REMW instruction\n`ifdef RISCV_FORMAL_ALTOPS\n  wire [31:0] altops_bitmask = 64'hf5b7d8538da68fa5;\n  wire [31:0] result = (rvfi_rs1_rdata - rvfi_rs2_rdata) ^ altops_bitmask;\n`else\n  wire [31:0] result = rvfi_rs2_rdata == 32'b0 ? rvfi_rs1_rdata :\n                       rvfi_rs1_rdata == {1'b1, {31{1'b0}}} && rvfi_rs2_rdata == {32{1'b1}} ? {32{1'b0}} :\n                       $signed(rvfi_rs1_rdata[31:0]) % $signed(rvfi_rs2_rdata[31:0]);\n`endif\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000001 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sb.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sb (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // S-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SB instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_wmask = ((1 << 1)-1) << (addr-spec_mem_addr);\n  assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr));\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (1-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr;\n  assign spec_mem_wmask = ((1 << 1)-1);\n  assign spec_mem_wdata = rvfi_rs2_rdata;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_rmask = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sd.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sd (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // S-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SD instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_wmask = ((1 << 8)-1) << (addr-spec_mem_addr);\n  assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr));\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (8-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr;\n  assign spec_mem_wmask = ((1 << 8)-1);\n  assign spec_mem_wdata = rvfi_rs2_rdata;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_rmask = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sh.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sh (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // S-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SH instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_wmask = ((1 << 2)-1) << (addr-spec_mem_addr);\n  assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr));\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (2-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr;\n  assign spec_mem_wmask = ((1 << 2)-1);\n  assign spec_mem_wdata = rvfi_rs2_rdata;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_rmask = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sll.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sll (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SLL instruction\n  wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0];\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata << shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_slli.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_slli (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format (shift variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct6 = rvfi_insn[31:26];\n  wire [5:0] insn_shamt  = rvfi_insn[25:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SLLI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata << insn_shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64);\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_slliw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_slliw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format (shift variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct6 = rvfi_insn[31:26];\n  wire [5:0] insn_shamt  = rvfi_insn[25:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SLLIW instruction\n  wire [31:0] result = rvfi_rs1_rdata[31:0] << insn_shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011 && !insn_shamt[5];\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sllw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sllw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SLLW instruction\n  wire [4:0] shamt = rvfi_rs2_rdata[4:0];\n  wire [31:0] result = rvfi_rs1_rdata[31:0] << shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_slt.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_slt (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SLT instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata);\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_slti.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_slti (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SLTI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) < $signed(insn_imm);\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0010011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sltiu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sltiu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SLTIU instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata < insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0010011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sltu.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sltu (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SLTU instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata < rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sra.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sra (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SRA instruction\n  wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0];\n  wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) >>> shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_srai.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_srai (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format (shift variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct6 = rvfi_insn[31:26];\n  wire [5:0] insn_shamt  = rvfi_insn[25:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SRAI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) >>> insn_shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64);\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sraiw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sraiw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format (shift variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct6 = rvfi_insn[31:26];\n  wire [5:0] insn_shamt  = rvfi_insn[25:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SRAIW instruction\n  wire [31:0] result = $signed(rvfi_rs1_rdata[31:0]) >>> insn_shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5];\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sraw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sraw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SRAW instruction\n  wire [4:0] shamt = rvfi_rs2_rdata[4:0];\n  wire [31:0] result = $signed(rvfi_rs1_rdata[31:0]) >>> shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_srl.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_srl (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SRL instruction\n  wire [5:0] shamt = `RISCV_FORMAL_XLEN == 64 ? rvfi_rs2_rdata[5:0] : rvfi_rs2_rdata[4:0];\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata >> shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_srli.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_srli (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format (shift variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct6 = rvfi_insn[31:26];\n  wire [5:0] insn_shamt  = rvfi_insn[25:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SRLI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata >> insn_shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64);\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_srliw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_srliw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format (shift variation)\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct6 = rvfi_insn[31:26];\n  wire [5:0] insn_shamt  = rvfi_insn[25:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SRLIW instruction\n  wire [31:0] result = rvfi_rs1_rdata[31:0] >> insn_shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5];\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_srlw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_srlw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SRLW instruction\n  wire [4:0] shamt = rvfi_rs2_rdata[4:0];\n  wire [31:0] result = rvfi_rs1_rdata[31:0] >> shamt;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sub.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sub (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SUB instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata - rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_subw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_subw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SUBW instruction\n  wire [31:0] result = rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0];\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0111011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_sw.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_sw (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // S-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:25], rvfi_insn[11:7]});\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // SW instruction\n`ifdef RISCV_FORMAL_ALIGNED_MEM\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr & ~(`RISCV_FORMAL_XLEN/8-1);\n  assign spec_mem_wmask = ((1 << 4)-1) << (addr-spec_mem_addr);\n  assign spec_mem_wdata = rvfi_rs2_rdata << (8*(addr-spec_mem_addr));\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = ((addr & (4-1)) != 0) || !misa_ok;\n`else\n  wire [`RISCV_FORMAL_XLEN-1:0] addr = rvfi_rs1_rdata + insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0100011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_mem_addr = addr;\n  assign spec_mem_wmask = ((1 << 4)-1);\n  assign spec_mem_wdata = rvfi_rs2_rdata;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n  assign spec_trap = !misa_ok;\n`endif\n\n  // default assignments\n  assign spec_rd_addr = 0;\n  assign spec_rd_wdata = 0;\n  assign spec_mem_rmask = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_xor.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_xor (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // R-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [6:0] insn_funct7 = rvfi_insn[31:25];\n  wire [4:0] insn_rs2    = rvfi_insn[24:20];\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // XOR instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ rvfi_rs2_rdata;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0110011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rs2_addr = insn_rs2;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/insn_xori.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_insn_xori (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n\n  // I-type instruction format\n  wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16 >> 16;\n  wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]);\n  wire [4:0] insn_rs1    = rvfi_insn[19:15];\n  wire [2:0] insn_funct3 = rvfi_insn[14:12];\n  wire [4:0] insn_rd     = rvfi_insn[11: 7];\n  wire [6:0] insn_opcode = rvfi_insn[ 6: 0];\n\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0;\n  assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0;\n`else\n  wire misa_ok = 1;\n`endif\n\n  // XORI instruction\n  wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ insn_imm;\n  assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0010011;\n  assign spec_rs1_addr = insn_rs1;\n  assign spec_rd_addr = insn_rd;\n  assign spec_rd_wdata = spec_rd_addr ? result : 0;\n  assign spec_pc_wdata = rvfi_pc_rdata + 4;\n\n  // default assignments\n  assign spec_rs2_addr = 0;\n  assign spec_trap = !misa_ok;\n  assign spec_mem_addr = 0;\n  assign spec_mem_rmask = 0;\n  assign spec_mem_wmask = 0;\n  assign spec_mem_wdata = 0;\nendmodule\n"
  },
  {
    "path": "insns/isa_rv32i.txt",
    "content": "add\naddi\nand\nandi\nauipc\nbeq\nbge\nbgeu\nblt\nbltu\nbne\njal\njalr\nlb\nlbu\nlh\nlhu\nlui\nlw\nor\nori\nsb\nsh\nsll\nslli\nslt\nslti\nsltiu\nsltu\nsra\nsrai\nsrl\nsrli\nsub\nsw\nxor\nxori\n"
  },
  {
    "path": "insns/isa_rv32i.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_isa_rv32i (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n  wire                                spec_insn_add_valid;\n  wire                                spec_insn_add_trap;\n  wire [                       4 : 0] spec_insn_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_add insn_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_add_valid),\n    .spec_trap(spec_insn_add_trap),\n    .spec_rs1_addr(spec_insn_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_add_rs2_addr),\n    .spec_rd_addr(spec_insn_add_rd_addr),\n    .spec_rd_wdata(spec_insn_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_add_pc_wdata),\n    .spec_mem_addr(spec_insn_add_mem_addr),\n    .spec_mem_rmask(spec_insn_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_add_mem_wdata)\n  );\n\n  wire                                spec_insn_addi_valid;\n  wire                                spec_insn_addi_trap;\n  wire [                       4 : 0] spec_insn_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addi insn_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addi_valid),\n    .spec_trap(spec_insn_addi_trap),\n    .spec_rs1_addr(spec_insn_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_and_valid;\n  wire                                spec_insn_and_trap;\n  wire [                       4 : 0] spec_insn_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_and insn_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_and_valid),\n    .spec_trap(spec_insn_and_trap),\n    .spec_rs1_addr(spec_insn_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_and_rs2_addr),\n    .spec_rd_addr(spec_insn_and_rd_addr),\n    .spec_rd_wdata(spec_insn_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_and_pc_wdata),\n    .spec_mem_addr(spec_insn_and_mem_addr),\n    .spec_mem_rmask(spec_insn_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_and_mem_wdata)\n  );\n\n  wire                                spec_insn_andi_valid;\n  wire                                spec_insn_andi_trap;\n  wire [                       4 : 0] spec_insn_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_andi insn_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_andi_valid),\n    .spec_trap(spec_insn_andi_trap),\n    .spec_rs1_addr(spec_insn_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_auipc_valid;\n  wire                                spec_insn_auipc_trap;\n  wire [                       4 : 0] spec_insn_auipc_rs1_addr;\n  wire [                       4 : 0] spec_insn_auipc_rs2_addr;\n  wire [                       4 : 0] spec_insn_auipc_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_csr_misa_rmask;\n`endif\n\n  rvfi_insn_auipc insn_auipc (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_auipc_valid),\n    .spec_trap(spec_insn_auipc_trap),\n    .spec_rs1_addr(spec_insn_auipc_rs1_addr),\n    .spec_rs2_addr(spec_insn_auipc_rs2_addr),\n    .spec_rd_addr(spec_insn_auipc_rd_addr),\n    .spec_rd_wdata(spec_insn_auipc_rd_wdata),\n    .spec_pc_wdata(spec_insn_auipc_pc_wdata),\n    .spec_mem_addr(spec_insn_auipc_mem_addr),\n    .spec_mem_rmask(spec_insn_auipc_mem_rmask),\n    .spec_mem_wmask(spec_insn_auipc_mem_wmask),\n    .spec_mem_wdata(spec_insn_auipc_mem_wdata)\n  );\n\n  wire                                spec_insn_beq_valid;\n  wire                                spec_insn_beq_trap;\n  wire [                       4 : 0] spec_insn_beq_rs1_addr;\n  wire [                       4 : 0] spec_insn_beq_rs2_addr;\n  wire [                       4 : 0] spec_insn_beq_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_csr_misa_rmask;\n`endif\n\n  rvfi_insn_beq insn_beq (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_beq_valid),\n    .spec_trap(spec_insn_beq_trap),\n    .spec_rs1_addr(spec_insn_beq_rs1_addr),\n    .spec_rs2_addr(spec_insn_beq_rs2_addr),\n    .spec_rd_addr(spec_insn_beq_rd_addr),\n    .spec_rd_wdata(spec_insn_beq_rd_wdata),\n    .spec_pc_wdata(spec_insn_beq_pc_wdata),\n    .spec_mem_addr(spec_insn_beq_mem_addr),\n    .spec_mem_rmask(spec_insn_beq_mem_rmask),\n    .spec_mem_wmask(spec_insn_beq_mem_wmask),\n    .spec_mem_wdata(spec_insn_beq_mem_wdata)\n  );\n\n  wire                                spec_insn_bge_valid;\n  wire                                spec_insn_bge_trap;\n  wire [                       4 : 0] spec_insn_bge_rs1_addr;\n  wire [                       4 : 0] spec_insn_bge_rs2_addr;\n  wire [                       4 : 0] spec_insn_bge_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bge insn_bge (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bge_valid),\n    .spec_trap(spec_insn_bge_trap),\n    .spec_rs1_addr(spec_insn_bge_rs1_addr),\n    .spec_rs2_addr(spec_insn_bge_rs2_addr),\n    .spec_rd_addr(spec_insn_bge_rd_addr),\n    .spec_rd_wdata(spec_insn_bge_rd_wdata),\n    .spec_pc_wdata(spec_insn_bge_pc_wdata),\n    .spec_mem_addr(spec_insn_bge_mem_addr),\n    .spec_mem_rmask(spec_insn_bge_mem_rmask),\n    .spec_mem_wmask(spec_insn_bge_mem_wmask),\n    .spec_mem_wdata(spec_insn_bge_mem_wdata)\n  );\n\n  wire                                spec_insn_bgeu_valid;\n  wire                                spec_insn_bgeu_trap;\n  wire [                       4 : 0] spec_insn_bgeu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bgeu insn_bgeu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bgeu_valid),\n    .spec_trap(spec_insn_bgeu_trap),\n    .spec_rs1_addr(spec_insn_bgeu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bgeu_rs2_addr),\n    .spec_rd_addr(spec_insn_bgeu_rd_addr),\n    .spec_rd_wdata(spec_insn_bgeu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bgeu_pc_wdata),\n    .spec_mem_addr(spec_insn_bgeu_mem_addr),\n    .spec_mem_rmask(spec_insn_bgeu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bgeu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bgeu_mem_wdata)\n  );\n\n  wire                                spec_insn_blt_valid;\n  wire                                spec_insn_blt_trap;\n  wire [                       4 : 0] spec_insn_blt_rs1_addr;\n  wire [                       4 : 0] spec_insn_blt_rs2_addr;\n  wire [                       4 : 0] spec_insn_blt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_blt insn_blt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_blt_valid),\n    .spec_trap(spec_insn_blt_trap),\n    .spec_rs1_addr(spec_insn_blt_rs1_addr),\n    .spec_rs2_addr(spec_insn_blt_rs2_addr),\n    .spec_rd_addr(spec_insn_blt_rd_addr),\n    .spec_rd_wdata(spec_insn_blt_rd_wdata),\n    .spec_pc_wdata(spec_insn_blt_pc_wdata),\n    .spec_mem_addr(spec_insn_blt_mem_addr),\n    .spec_mem_rmask(spec_insn_blt_mem_rmask),\n    .spec_mem_wmask(spec_insn_blt_mem_wmask),\n    .spec_mem_wdata(spec_insn_blt_mem_wdata)\n  );\n\n  wire                                spec_insn_bltu_valid;\n  wire                                spec_insn_bltu_trap;\n  wire [                       4 : 0] spec_insn_bltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bltu insn_bltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bltu_valid),\n    .spec_trap(spec_insn_bltu_trap),\n    .spec_rs1_addr(spec_insn_bltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bltu_rs2_addr),\n    .spec_rd_addr(spec_insn_bltu_rd_addr),\n    .spec_rd_wdata(spec_insn_bltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bltu_pc_wdata),\n    .spec_mem_addr(spec_insn_bltu_mem_addr),\n    .spec_mem_rmask(spec_insn_bltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bltu_mem_wdata)\n  );\n\n  wire                                spec_insn_bne_valid;\n  wire                                spec_insn_bne_trap;\n  wire [                       4 : 0] spec_insn_bne_rs1_addr;\n  wire [                       4 : 0] spec_insn_bne_rs2_addr;\n  wire [                       4 : 0] spec_insn_bne_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bne insn_bne (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bne_valid),\n    .spec_trap(spec_insn_bne_trap),\n    .spec_rs1_addr(spec_insn_bne_rs1_addr),\n    .spec_rs2_addr(spec_insn_bne_rs2_addr),\n    .spec_rd_addr(spec_insn_bne_rd_addr),\n    .spec_rd_wdata(spec_insn_bne_rd_wdata),\n    .spec_pc_wdata(spec_insn_bne_pc_wdata),\n    .spec_mem_addr(spec_insn_bne_mem_addr),\n    .spec_mem_rmask(spec_insn_bne_mem_rmask),\n    .spec_mem_wmask(spec_insn_bne_mem_wmask),\n    .spec_mem_wdata(spec_insn_bne_mem_wdata)\n  );\n\n  wire                                spec_insn_jal_valid;\n  wire                                spec_insn_jal_trap;\n  wire [                       4 : 0] spec_insn_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jal insn_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jal_valid),\n    .spec_trap(spec_insn_jal_trap),\n    .spec_rs1_addr(spec_insn_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_jalr_valid;\n  wire                                spec_insn_jalr_trap;\n  wire [                       4 : 0] spec_insn_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jalr insn_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jalr_valid),\n    .spec_trap(spec_insn_jalr_trap),\n    .spec_rs1_addr(spec_insn_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_lb_valid;\n  wire                                spec_insn_lb_trap;\n  wire [                       4 : 0] spec_insn_lb_rs1_addr;\n  wire [                       4 : 0] spec_insn_lb_rs2_addr;\n  wire [                       4 : 0] spec_insn_lb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lb insn_lb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lb_valid),\n    .spec_trap(spec_insn_lb_trap),\n    .spec_rs1_addr(spec_insn_lb_rs1_addr),\n    .spec_rs2_addr(spec_insn_lb_rs2_addr),\n    .spec_rd_addr(spec_insn_lb_rd_addr),\n    .spec_rd_wdata(spec_insn_lb_rd_wdata),\n    .spec_pc_wdata(spec_insn_lb_pc_wdata),\n    .spec_mem_addr(spec_insn_lb_mem_addr),\n    .spec_mem_rmask(spec_insn_lb_mem_rmask),\n    .spec_mem_wmask(spec_insn_lb_mem_wmask),\n    .spec_mem_wdata(spec_insn_lb_mem_wdata)\n  );\n\n  wire                                spec_insn_lbu_valid;\n  wire                                spec_insn_lbu_trap;\n  wire [                       4 : 0] spec_insn_lbu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lbu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lbu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lbu insn_lbu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lbu_valid),\n    .spec_trap(spec_insn_lbu_trap),\n    .spec_rs1_addr(spec_insn_lbu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lbu_rs2_addr),\n    .spec_rd_addr(spec_insn_lbu_rd_addr),\n    .spec_rd_wdata(spec_insn_lbu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lbu_pc_wdata),\n    .spec_mem_addr(spec_insn_lbu_mem_addr),\n    .spec_mem_rmask(spec_insn_lbu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lbu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lbu_mem_wdata)\n  );\n\n  wire                                spec_insn_lh_valid;\n  wire                                spec_insn_lh_trap;\n  wire [                       4 : 0] spec_insn_lh_rs1_addr;\n  wire [                       4 : 0] spec_insn_lh_rs2_addr;\n  wire [                       4 : 0] spec_insn_lh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lh insn_lh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lh_valid),\n    .spec_trap(spec_insn_lh_trap),\n    .spec_rs1_addr(spec_insn_lh_rs1_addr),\n    .spec_rs2_addr(spec_insn_lh_rs2_addr),\n    .spec_rd_addr(spec_insn_lh_rd_addr),\n    .spec_rd_wdata(spec_insn_lh_rd_wdata),\n    .spec_pc_wdata(spec_insn_lh_pc_wdata),\n    .spec_mem_addr(spec_insn_lh_mem_addr),\n    .spec_mem_rmask(spec_insn_lh_mem_rmask),\n    .spec_mem_wmask(spec_insn_lh_mem_wmask),\n    .spec_mem_wdata(spec_insn_lh_mem_wdata)\n  );\n\n  wire                                spec_insn_lhu_valid;\n  wire                                spec_insn_lhu_trap;\n  wire [                       4 : 0] spec_insn_lhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lhu insn_lhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lhu_valid),\n    .spec_trap(spec_insn_lhu_trap),\n    .spec_rs1_addr(spec_insn_lhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lhu_rs2_addr),\n    .spec_rd_addr(spec_insn_lhu_rd_addr),\n    .spec_rd_wdata(spec_insn_lhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lhu_pc_wdata),\n    .spec_mem_addr(spec_insn_lhu_mem_addr),\n    .spec_mem_rmask(spec_insn_lhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lhu_mem_wdata)\n  );\n\n  wire                                spec_insn_lui_valid;\n  wire                                spec_insn_lui_trap;\n  wire [                       4 : 0] spec_insn_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lui insn_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lui_valid),\n    .spec_trap(spec_insn_lui_trap),\n    .spec_rs1_addr(spec_insn_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_lw_valid;\n  wire                                spec_insn_lw_trap;\n  wire [                       4 : 0] spec_insn_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lw insn_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lw_valid),\n    .spec_trap(spec_insn_lw_trap),\n    .spec_rs1_addr(spec_insn_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_or_valid;\n  wire                                spec_insn_or_trap;\n  wire [                       4 : 0] spec_insn_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_or insn_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_or_valid),\n    .spec_trap(spec_insn_or_trap),\n    .spec_rs1_addr(spec_insn_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_or_rs2_addr),\n    .spec_rd_addr(spec_insn_or_rd_addr),\n    .spec_rd_wdata(spec_insn_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_or_pc_wdata),\n    .spec_mem_addr(spec_insn_or_mem_addr),\n    .spec_mem_rmask(spec_insn_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_or_mem_wdata)\n  );\n\n  wire                                spec_insn_ori_valid;\n  wire                                spec_insn_ori_trap;\n  wire [                       4 : 0] spec_insn_ori_rs1_addr;\n  wire [                       4 : 0] spec_insn_ori_rs2_addr;\n  wire [                       4 : 0] spec_insn_ori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ori insn_ori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ori_valid),\n    .spec_trap(spec_insn_ori_trap),\n    .spec_rs1_addr(spec_insn_ori_rs1_addr),\n    .spec_rs2_addr(spec_insn_ori_rs2_addr),\n    .spec_rd_addr(spec_insn_ori_rd_addr),\n    .spec_rd_wdata(spec_insn_ori_rd_wdata),\n    .spec_pc_wdata(spec_insn_ori_pc_wdata),\n    .spec_mem_addr(spec_insn_ori_mem_addr),\n    .spec_mem_rmask(spec_insn_ori_mem_rmask),\n    .spec_mem_wmask(spec_insn_ori_mem_wmask),\n    .spec_mem_wdata(spec_insn_ori_mem_wdata)\n  );\n\n  wire                                spec_insn_sb_valid;\n  wire                                spec_insn_sb_trap;\n  wire [                       4 : 0] spec_insn_sb_rs1_addr;\n  wire [                       4 : 0] spec_insn_sb_rs2_addr;\n  wire [                       4 : 0] spec_insn_sb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sb insn_sb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sb_valid),\n    .spec_trap(spec_insn_sb_trap),\n    .spec_rs1_addr(spec_insn_sb_rs1_addr),\n    .spec_rs2_addr(spec_insn_sb_rs2_addr),\n    .spec_rd_addr(spec_insn_sb_rd_addr),\n    .spec_rd_wdata(spec_insn_sb_rd_wdata),\n    .spec_pc_wdata(spec_insn_sb_pc_wdata),\n    .spec_mem_addr(spec_insn_sb_mem_addr),\n    .spec_mem_rmask(spec_insn_sb_mem_rmask),\n    .spec_mem_wmask(spec_insn_sb_mem_wmask),\n    .spec_mem_wdata(spec_insn_sb_mem_wdata)\n  );\n\n  wire                                spec_insn_sh_valid;\n  wire                                spec_insn_sh_trap;\n  wire [                       4 : 0] spec_insn_sh_rs1_addr;\n  wire [                       4 : 0] spec_insn_sh_rs2_addr;\n  wire [                       4 : 0] spec_insn_sh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sh insn_sh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sh_valid),\n    .spec_trap(spec_insn_sh_trap),\n    .spec_rs1_addr(spec_insn_sh_rs1_addr),\n    .spec_rs2_addr(spec_insn_sh_rs2_addr),\n    .spec_rd_addr(spec_insn_sh_rd_addr),\n    .spec_rd_wdata(spec_insn_sh_rd_wdata),\n    .spec_pc_wdata(spec_insn_sh_pc_wdata),\n    .spec_mem_addr(spec_insn_sh_mem_addr),\n    .spec_mem_rmask(spec_insn_sh_mem_rmask),\n    .spec_mem_wmask(spec_insn_sh_mem_wmask),\n    .spec_mem_wdata(spec_insn_sh_mem_wdata)\n  );\n\n  wire                                spec_insn_sll_valid;\n  wire                                spec_insn_sll_trap;\n  wire [                       4 : 0] spec_insn_sll_rs1_addr;\n  wire [                       4 : 0] spec_insn_sll_rs2_addr;\n  wire [                       4 : 0] spec_insn_sll_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sll insn_sll (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sll_valid),\n    .spec_trap(spec_insn_sll_trap),\n    .spec_rs1_addr(spec_insn_sll_rs1_addr),\n    .spec_rs2_addr(spec_insn_sll_rs2_addr),\n    .spec_rd_addr(spec_insn_sll_rd_addr),\n    .spec_rd_wdata(spec_insn_sll_rd_wdata),\n    .spec_pc_wdata(spec_insn_sll_pc_wdata),\n    .spec_mem_addr(spec_insn_sll_mem_addr),\n    .spec_mem_rmask(spec_insn_sll_mem_rmask),\n    .spec_mem_wmask(spec_insn_sll_mem_wmask),\n    .spec_mem_wdata(spec_insn_sll_mem_wdata)\n  );\n\n  wire                                spec_insn_slli_valid;\n  wire                                spec_insn_slli_trap;\n  wire [                       4 : 0] spec_insn_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slli insn_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slli_valid),\n    .spec_trap(spec_insn_slli_trap),\n    .spec_rs1_addr(spec_insn_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_slt_valid;\n  wire                                spec_insn_slt_trap;\n  wire [                       4 : 0] spec_insn_slt_rs1_addr;\n  wire [                       4 : 0] spec_insn_slt_rs2_addr;\n  wire [                       4 : 0] spec_insn_slt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slt insn_slt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slt_valid),\n    .spec_trap(spec_insn_slt_trap),\n    .spec_rs1_addr(spec_insn_slt_rs1_addr),\n    .spec_rs2_addr(spec_insn_slt_rs2_addr),\n    .spec_rd_addr(spec_insn_slt_rd_addr),\n    .spec_rd_wdata(spec_insn_slt_rd_wdata),\n    .spec_pc_wdata(spec_insn_slt_pc_wdata),\n    .spec_mem_addr(spec_insn_slt_mem_addr),\n    .spec_mem_rmask(spec_insn_slt_mem_rmask),\n    .spec_mem_wmask(spec_insn_slt_mem_wmask),\n    .spec_mem_wdata(spec_insn_slt_mem_wdata)\n  );\n\n  wire                                spec_insn_slti_valid;\n  wire                                spec_insn_slti_trap;\n  wire [                       4 : 0] spec_insn_slti_rs1_addr;\n  wire [                       4 : 0] spec_insn_slti_rs2_addr;\n  wire [                       4 : 0] spec_insn_slti_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slti insn_slti (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slti_valid),\n    .spec_trap(spec_insn_slti_trap),\n    .spec_rs1_addr(spec_insn_slti_rs1_addr),\n    .spec_rs2_addr(spec_insn_slti_rs2_addr),\n    .spec_rd_addr(spec_insn_slti_rd_addr),\n    .spec_rd_wdata(spec_insn_slti_rd_wdata),\n    .spec_pc_wdata(spec_insn_slti_pc_wdata),\n    .spec_mem_addr(spec_insn_slti_mem_addr),\n    .spec_mem_rmask(spec_insn_slti_mem_rmask),\n    .spec_mem_wmask(spec_insn_slti_mem_wmask),\n    .spec_mem_wdata(spec_insn_slti_mem_wdata)\n  );\n\n  wire                                spec_insn_sltiu_valid;\n  wire                                spec_insn_sltiu_trap;\n  wire [                       4 : 0] spec_insn_sltiu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltiu insn_sltiu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltiu_valid),\n    .spec_trap(spec_insn_sltiu_trap),\n    .spec_rs1_addr(spec_insn_sltiu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltiu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltiu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltiu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltiu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltiu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltiu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltiu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltiu_mem_wdata)\n  );\n\n  wire                                spec_insn_sltu_valid;\n  wire                                spec_insn_sltu_trap;\n  wire [                       4 : 0] spec_insn_sltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltu insn_sltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltu_valid),\n    .spec_trap(spec_insn_sltu_trap),\n    .spec_rs1_addr(spec_insn_sltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltu_mem_wdata)\n  );\n\n  wire                                spec_insn_sra_valid;\n  wire                                spec_insn_sra_trap;\n  wire [                       4 : 0] spec_insn_sra_rs1_addr;\n  wire [                       4 : 0] spec_insn_sra_rs2_addr;\n  wire [                       4 : 0] spec_insn_sra_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sra insn_sra (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sra_valid),\n    .spec_trap(spec_insn_sra_trap),\n    .spec_rs1_addr(spec_insn_sra_rs1_addr),\n    .spec_rs2_addr(spec_insn_sra_rs2_addr),\n    .spec_rd_addr(spec_insn_sra_rd_addr),\n    .spec_rd_wdata(spec_insn_sra_rd_wdata),\n    .spec_pc_wdata(spec_insn_sra_pc_wdata),\n    .spec_mem_addr(spec_insn_sra_mem_addr),\n    .spec_mem_rmask(spec_insn_sra_mem_rmask),\n    .spec_mem_wmask(spec_insn_sra_mem_wmask),\n    .spec_mem_wdata(spec_insn_sra_mem_wdata)\n  );\n\n  wire                                spec_insn_srai_valid;\n  wire                                spec_insn_srai_trap;\n  wire [                       4 : 0] spec_insn_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srai insn_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srai_valid),\n    .spec_trap(spec_insn_srai_trap),\n    .spec_rs1_addr(spec_insn_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_srl_valid;\n  wire                                spec_insn_srl_trap;\n  wire [                       4 : 0] spec_insn_srl_rs1_addr;\n  wire [                       4 : 0] spec_insn_srl_rs2_addr;\n  wire [                       4 : 0] spec_insn_srl_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srl insn_srl (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srl_valid),\n    .spec_trap(spec_insn_srl_trap),\n    .spec_rs1_addr(spec_insn_srl_rs1_addr),\n    .spec_rs2_addr(spec_insn_srl_rs2_addr),\n    .spec_rd_addr(spec_insn_srl_rd_addr),\n    .spec_rd_wdata(spec_insn_srl_rd_wdata),\n    .spec_pc_wdata(spec_insn_srl_pc_wdata),\n    .spec_mem_addr(spec_insn_srl_mem_addr),\n    .spec_mem_rmask(spec_insn_srl_mem_rmask),\n    .spec_mem_wmask(spec_insn_srl_mem_wmask),\n    .spec_mem_wdata(spec_insn_srl_mem_wdata)\n  );\n\n  wire                                spec_insn_srli_valid;\n  wire                                spec_insn_srli_trap;\n  wire [                       4 : 0] spec_insn_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srli insn_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srli_valid),\n    .spec_trap(spec_insn_srli_trap),\n    .spec_rs1_addr(spec_insn_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_sub_valid;\n  wire                                spec_insn_sub_trap;\n  wire [                       4 : 0] spec_insn_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sub insn_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sub_valid),\n    .spec_trap(spec_insn_sub_trap),\n    .spec_rs1_addr(spec_insn_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_sw_valid;\n  wire                                spec_insn_sw_trap;\n  wire [                       4 : 0] spec_insn_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sw insn_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sw_valid),\n    .spec_trap(spec_insn_sw_trap),\n    .spec_rs1_addr(spec_insn_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_xor_valid;\n  wire                                spec_insn_xor_trap;\n  wire [                       4 : 0] spec_insn_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xor insn_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xor_valid),\n    .spec_trap(spec_insn_xor_trap),\n    .spec_rs1_addr(spec_insn_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_xori_valid;\n  wire                                spec_insn_xori_trap;\n  wire [                       4 : 0] spec_insn_xori_rs1_addr;\n  wire [                       4 : 0] spec_insn_xori_rs2_addr;\n  wire [                       4 : 0] spec_insn_xori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xori insn_xori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xori_valid),\n    .spec_trap(spec_insn_xori_trap),\n    .spec_rs1_addr(spec_insn_xori_rs1_addr),\n    .spec_rs2_addr(spec_insn_xori_rs2_addr),\n    .spec_rd_addr(spec_insn_xori_rd_addr),\n    .spec_rd_wdata(spec_insn_xori_rd_wdata),\n    .spec_pc_wdata(spec_insn_xori_pc_wdata),\n    .spec_mem_addr(spec_insn_xori_mem_addr),\n    .spec_mem_rmask(spec_insn_xori_mem_rmask),\n    .spec_mem_wmask(spec_insn_xori_mem_wmask),\n    .spec_mem_wdata(spec_insn_xori_mem_wdata)\n  );\n\n  assign spec_valid =\n\t\tspec_insn_add_valid ? spec_insn_add_valid :\n\t\tspec_insn_addi_valid ? spec_insn_addi_valid :\n\t\tspec_insn_and_valid ? spec_insn_and_valid :\n\t\tspec_insn_andi_valid ? spec_insn_andi_valid :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_valid :\n\t\tspec_insn_beq_valid ? spec_insn_beq_valid :\n\t\tspec_insn_bge_valid ? spec_insn_bge_valid :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_valid :\n\t\tspec_insn_blt_valid ? spec_insn_blt_valid :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_valid :\n\t\tspec_insn_bne_valid ? spec_insn_bne_valid :\n\t\tspec_insn_jal_valid ? spec_insn_jal_valid :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_valid :\n\t\tspec_insn_lb_valid ? spec_insn_lb_valid :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_valid :\n\t\tspec_insn_lh_valid ? spec_insn_lh_valid :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_valid :\n\t\tspec_insn_lui_valid ? spec_insn_lui_valid :\n\t\tspec_insn_lw_valid ? spec_insn_lw_valid :\n\t\tspec_insn_or_valid ? spec_insn_or_valid :\n\t\tspec_insn_ori_valid ? spec_insn_ori_valid :\n\t\tspec_insn_sb_valid ? spec_insn_sb_valid :\n\t\tspec_insn_sh_valid ? spec_insn_sh_valid :\n\t\tspec_insn_sll_valid ? spec_insn_sll_valid :\n\t\tspec_insn_slli_valid ? spec_insn_slli_valid :\n\t\tspec_insn_slt_valid ? spec_insn_slt_valid :\n\t\tspec_insn_slti_valid ? spec_insn_slti_valid :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_valid :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_valid :\n\t\tspec_insn_sra_valid ? spec_insn_sra_valid :\n\t\tspec_insn_srai_valid ? spec_insn_srai_valid :\n\t\tspec_insn_srl_valid ? spec_insn_srl_valid :\n\t\tspec_insn_srli_valid ? spec_insn_srli_valid :\n\t\tspec_insn_sub_valid ? spec_insn_sub_valid :\n\t\tspec_insn_sw_valid ? spec_insn_sw_valid :\n\t\tspec_insn_xor_valid ? spec_insn_xor_valid :\n\t\tspec_insn_xori_valid ? spec_insn_xori_valid : 0;\n  assign spec_trap =\n\t\tspec_insn_add_valid ? spec_insn_add_trap :\n\t\tspec_insn_addi_valid ? spec_insn_addi_trap :\n\t\tspec_insn_and_valid ? spec_insn_and_trap :\n\t\tspec_insn_andi_valid ? spec_insn_andi_trap :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_trap :\n\t\tspec_insn_beq_valid ? spec_insn_beq_trap :\n\t\tspec_insn_bge_valid ? spec_insn_bge_trap :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_trap :\n\t\tspec_insn_blt_valid ? spec_insn_blt_trap :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_trap :\n\t\tspec_insn_bne_valid ? spec_insn_bne_trap :\n\t\tspec_insn_jal_valid ? spec_insn_jal_trap :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_trap :\n\t\tspec_insn_lb_valid ? spec_insn_lb_trap :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_trap :\n\t\tspec_insn_lh_valid ? spec_insn_lh_trap :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_trap :\n\t\tspec_insn_lui_valid ? spec_insn_lui_trap :\n\t\tspec_insn_lw_valid ? spec_insn_lw_trap :\n\t\tspec_insn_or_valid ? spec_insn_or_trap :\n\t\tspec_insn_ori_valid ? spec_insn_ori_trap :\n\t\tspec_insn_sb_valid ? spec_insn_sb_trap :\n\t\tspec_insn_sh_valid ? spec_insn_sh_trap :\n\t\tspec_insn_sll_valid ? spec_insn_sll_trap :\n\t\tspec_insn_slli_valid ? spec_insn_slli_trap :\n\t\tspec_insn_slt_valid ? spec_insn_slt_trap :\n\t\tspec_insn_slti_valid ? spec_insn_slti_trap :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_trap :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_trap :\n\t\tspec_insn_sra_valid ? spec_insn_sra_trap :\n\t\tspec_insn_srai_valid ? spec_insn_srai_trap :\n\t\tspec_insn_srl_valid ? spec_insn_srl_trap :\n\t\tspec_insn_srli_valid ? spec_insn_srli_trap :\n\t\tspec_insn_sub_valid ? spec_insn_sub_trap :\n\t\tspec_insn_sw_valid ? spec_insn_sw_trap :\n\t\tspec_insn_xor_valid ? spec_insn_xor_trap :\n\t\tspec_insn_xori_valid ? spec_insn_xori_trap : 0;\n  assign spec_rs1_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs1_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs1_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs1_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs1_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs1_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs1_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs1_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs1_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs1_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs1_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs1_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs1_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs1_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs1_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs1_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs1_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs1_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs1_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs1_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs1_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs1_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs1_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs1_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs1_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs1_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs1_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs1_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs1_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs1_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs1_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs1_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs1_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs1_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs1_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0;\n  assign spec_rs2_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs2_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs2_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs2_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs2_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs2_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs2_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs2_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs2_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs2_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs2_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs2_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs2_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs2_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs2_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs2_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs2_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs2_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs2_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs2_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs2_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs2_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs2_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs2_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs2_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs2_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs2_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs2_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs2_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs2_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs2_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs2_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs2_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs2_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs2_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0;\n  assign spec_rd_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_addr : 0;\n  assign spec_rd_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0;\n  assign spec_pc_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_pc_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_pc_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_pc_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_pc_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_pc_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_pc_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_pc_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_pc_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_pc_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_pc_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_pc_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_pc_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_pc_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_pc_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_pc_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_pc_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_pc_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_pc_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_pc_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_pc_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_pc_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_pc_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_pc_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_pc_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_pc_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_pc_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_pc_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_pc_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_pc_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_pc_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_pc_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_pc_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_pc_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_pc_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0;\n  assign spec_mem_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_addr : 0;\n  assign spec_mem_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0;\n  assign spec_mem_wmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0;\n  assign spec_mem_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0;\n`ifdef RISCV_FORMAL_CSR_MISA\n  assign spec_csr_misa_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_csr_misa_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_csr_misa_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_csr_misa_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0;\n`endif\nendmodule\n"
  },
  {
    "path": "insns/isa_rv32ic.txt",
    "content": "add\naddi\nand\nandi\nauipc\nbeq\nbge\nbgeu\nblt\nbltu\nbne\nc_add\nc_addi\nc_addi16sp\nc_addi4spn\nc_and\nc_andi\nc_beqz\nc_bnez\nc_j\nc_jal\nc_jalr\nc_jr\nc_li\nc_lui\nc_lw\nc_lwsp\nc_mv\nc_or\nc_slli\nc_srai\nc_srli\nc_sub\nc_sw\nc_swsp\nc_xor\njal\njalr\nlb\nlbu\nlh\nlhu\nlui\nlw\nor\nori\nsb\nsh\nsll\nslli\nslt\nslti\nsltiu\nsltu\nsra\nsrai\nsrl\nsrli\nsub\nsw\nxor\nxori\n"
  },
  {
    "path": "insns/isa_rv32ic.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_isa_rv32ic (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n  wire                                spec_insn_add_valid;\n  wire                                spec_insn_add_trap;\n  wire [                       4 : 0] spec_insn_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_add insn_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_add_valid),\n    .spec_trap(spec_insn_add_trap),\n    .spec_rs1_addr(spec_insn_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_add_rs2_addr),\n    .spec_rd_addr(spec_insn_add_rd_addr),\n    .spec_rd_wdata(spec_insn_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_add_pc_wdata),\n    .spec_mem_addr(spec_insn_add_mem_addr),\n    .spec_mem_rmask(spec_insn_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_add_mem_wdata)\n  );\n\n  wire                                spec_insn_addi_valid;\n  wire                                spec_insn_addi_trap;\n  wire [                       4 : 0] spec_insn_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addi insn_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addi_valid),\n    .spec_trap(spec_insn_addi_trap),\n    .spec_rs1_addr(spec_insn_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_and_valid;\n  wire                                spec_insn_and_trap;\n  wire [                       4 : 0] spec_insn_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_and insn_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_and_valid),\n    .spec_trap(spec_insn_and_trap),\n    .spec_rs1_addr(spec_insn_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_and_rs2_addr),\n    .spec_rd_addr(spec_insn_and_rd_addr),\n    .spec_rd_wdata(spec_insn_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_and_pc_wdata),\n    .spec_mem_addr(spec_insn_and_mem_addr),\n    .spec_mem_rmask(spec_insn_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_and_mem_wdata)\n  );\n\n  wire                                spec_insn_andi_valid;\n  wire                                spec_insn_andi_trap;\n  wire [                       4 : 0] spec_insn_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_andi insn_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_andi_valid),\n    .spec_trap(spec_insn_andi_trap),\n    .spec_rs1_addr(spec_insn_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_auipc_valid;\n  wire                                spec_insn_auipc_trap;\n  wire [                       4 : 0] spec_insn_auipc_rs1_addr;\n  wire [                       4 : 0] spec_insn_auipc_rs2_addr;\n  wire [                       4 : 0] spec_insn_auipc_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_csr_misa_rmask;\n`endif\n\n  rvfi_insn_auipc insn_auipc (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_auipc_valid),\n    .spec_trap(spec_insn_auipc_trap),\n    .spec_rs1_addr(spec_insn_auipc_rs1_addr),\n    .spec_rs2_addr(spec_insn_auipc_rs2_addr),\n    .spec_rd_addr(spec_insn_auipc_rd_addr),\n    .spec_rd_wdata(spec_insn_auipc_rd_wdata),\n    .spec_pc_wdata(spec_insn_auipc_pc_wdata),\n    .spec_mem_addr(spec_insn_auipc_mem_addr),\n    .spec_mem_rmask(spec_insn_auipc_mem_rmask),\n    .spec_mem_wmask(spec_insn_auipc_mem_wmask),\n    .spec_mem_wdata(spec_insn_auipc_mem_wdata)\n  );\n\n  wire                                spec_insn_beq_valid;\n  wire                                spec_insn_beq_trap;\n  wire [                       4 : 0] spec_insn_beq_rs1_addr;\n  wire [                       4 : 0] spec_insn_beq_rs2_addr;\n  wire [                       4 : 0] spec_insn_beq_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_csr_misa_rmask;\n`endif\n\n  rvfi_insn_beq insn_beq (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_beq_valid),\n    .spec_trap(spec_insn_beq_trap),\n    .spec_rs1_addr(spec_insn_beq_rs1_addr),\n    .spec_rs2_addr(spec_insn_beq_rs2_addr),\n    .spec_rd_addr(spec_insn_beq_rd_addr),\n    .spec_rd_wdata(spec_insn_beq_rd_wdata),\n    .spec_pc_wdata(spec_insn_beq_pc_wdata),\n    .spec_mem_addr(spec_insn_beq_mem_addr),\n    .spec_mem_rmask(spec_insn_beq_mem_rmask),\n    .spec_mem_wmask(spec_insn_beq_mem_wmask),\n    .spec_mem_wdata(spec_insn_beq_mem_wdata)\n  );\n\n  wire                                spec_insn_bge_valid;\n  wire                                spec_insn_bge_trap;\n  wire [                       4 : 0] spec_insn_bge_rs1_addr;\n  wire [                       4 : 0] spec_insn_bge_rs2_addr;\n  wire [                       4 : 0] spec_insn_bge_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bge insn_bge (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bge_valid),\n    .spec_trap(spec_insn_bge_trap),\n    .spec_rs1_addr(spec_insn_bge_rs1_addr),\n    .spec_rs2_addr(spec_insn_bge_rs2_addr),\n    .spec_rd_addr(spec_insn_bge_rd_addr),\n    .spec_rd_wdata(spec_insn_bge_rd_wdata),\n    .spec_pc_wdata(spec_insn_bge_pc_wdata),\n    .spec_mem_addr(spec_insn_bge_mem_addr),\n    .spec_mem_rmask(spec_insn_bge_mem_rmask),\n    .spec_mem_wmask(spec_insn_bge_mem_wmask),\n    .spec_mem_wdata(spec_insn_bge_mem_wdata)\n  );\n\n  wire                                spec_insn_bgeu_valid;\n  wire                                spec_insn_bgeu_trap;\n  wire [                       4 : 0] spec_insn_bgeu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bgeu insn_bgeu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bgeu_valid),\n    .spec_trap(spec_insn_bgeu_trap),\n    .spec_rs1_addr(spec_insn_bgeu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bgeu_rs2_addr),\n    .spec_rd_addr(spec_insn_bgeu_rd_addr),\n    .spec_rd_wdata(spec_insn_bgeu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bgeu_pc_wdata),\n    .spec_mem_addr(spec_insn_bgeu_mem_addr),\n    .spec_mem_rmask(spec_insn_bgeu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bgeu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bgeu_mem_wdata)\n  );\n\n  wire                                spec_insn_blt_valid;\n  wire                                spec_insn_blt_trap;\n  wire [                       4 : 0] spec_insn_blt_rs1_addr;\n  wire [                       4 : 0] spec_insn_blt_rs2_addr;\n  wire [                       4 : 0] spec_insn_blt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_blt insn_blt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_blt_valid),\n    .spec_trap(spec_insn_blt_trap),\n    .spec_rs1_addr(spec_insn_blt_rs1_addr),\n    .spec_rs2_addr(spec_insn_blt_rs2_addr),\n    .spec_rd_addr(spec_insn_blt_rd_addr),\n    .spec_rd_wdata(spec_insn_blt_rd_wdata),\n    .spec_pc_wdata(spec_insn_blt_pc_wdata),\n    .spec_mem_addr(spec_insn_blt_mem_addr),\n    .spec_mem_rmask(spec_insn_blt_mem_rmask),\n    .spec_mem_wmask(spec_insn_blt_mem_wmask),\n    .spec_mem_wdata(spec_insn_blt_mem_wdata)\n  );\n\n  wire                                spec_insn_bltu_valid;\n  wire                                spec_insn_bltu_trap;\n  wire [                       4 : 0] spec_insn_bltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bltu insn_bltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bltu_valid),\n    .spec_trap(spec_insn_bltu_trap),\n    .spec_rs1_addr(spec_insn_bltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bltu_rs2_addr),\n    .spec_rd_addr(spec_insn_bltu_rd_addr),\n    .spec_rd_wdata(spec_insn_bltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bltu_pc_wdata),\n    .spec_mem_addr(spec_insn_bltu_mem_addr),\n    .spec_mem_rmask(spec_insn_bltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bltu_mem_wdata)\n  );\n\n  wire                                spec_insn_bne_valid;\n  wire                                spec_insn_bne_trap;\n  wire [                       4 : 0] spec_insn_bne_rs1_addr;\n  wire [                       4 : 0] spec_insn_bne_rs2_addr;\n  wire [                       4 : 0] spec_insn_bne_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bne insn_bne (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bne_valid),\n    .spec_trap(spec_insn_bne_trap),\n    .spec_rs1_addr(spec_insn_bne_rs1_addr),\n    .spec_rs2_addr(spec_insn_bne_rs2_addr),\n    .spec_rd_addr(spec_insn_bne_rd_addr),\n    .spec_rd_wdata(spec_insn_bne_rd_wdata),\n    .spec_pc_wdata(spec_insn_bne_pc_wdata),\n    .spec_mem_addr(spec_insn_bne_mem_addr),\n    .spec_mem_rmask(spec_insn_bne_mem_rmask),\n    .spec_mem_wmask(spec_insn_bne_mem_wmask),\n    .spec_mem_wdata(spec_insn_bne_mem_wdata)\n  );\n\n  wire                                spec_insn_c_add_valid;\n  wire                                spec_insn_c_add_trap;\n  wire [                       4 : 0] spec_insn_c_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_add insn_c_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_add_valid),\n    .spec_trap(spec_insn_c_add_trap),\n    .spec_rs1_addr(spec_insn_c_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_add_rs2_addr),\n    .spec_rd_addr(spec_insn_c_add_rd_addr),\n    .spec_rd_wdata(spec_insn_c_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_add_pc_wdata),\n    .spec_mem_addr(spec_insn_c_add_mem_addr),\n    .spec_mem_rmask(spec_insn_c_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_add_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi_valid;\n  wire                                spec_insn_c_addi_trap;\n  wire [                       4 : 0] spec_insn_c_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi insn_c_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi_valid),\n    .spec_trap(spec_insn_c_addi_trap),\n    .spec_rs1_addr(spec_insn_c_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi16sp_valid;\n  wire                                spec_insn_c_addi16sp_trap;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi16sp insn_c_addi16sp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi16sp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi16sp_valid),\n    .spec_trap(spec_insn_c_addi16sp_trap),\n    .spec_rs1_addr(spec_insn_c_addi16sp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi16sp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi16sp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi16sp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi16sp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi16sp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi16sp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi16sp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi16sp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi4spn_valid;\n  wire                                spec_insn_c_addi4spn_trap;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi4spn insn_c_addi4spn (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi4spn_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi4spn_valid),\n    .spec_trap(spec_insn_c_addi4spn_trap),\n    .spec_rs1_addr(spec_insn_c_addi4spn_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi4spn_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi4spn_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi4spn_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi4spn_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi4spn_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi4spn_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi4spn_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi4spn_mem_wdata)\n  );\n\n  wire                                spec_insn_c_and_valid;\n  wire                                spec_insn_c_and_trap;\n  wire [                       4 : 0] spec_insn_c_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_and insn_c_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_and_valid),\n    .spec_trap(spec_insn_c_and_trap),\n    .spec_rs1_addr(spec_insn_c_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_and_rs2_addr),\n    .spec_rd_addr(spec_insn_c_and_rd_addr),\n    .spec_rd_wdata(spec_insn_c_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_and_pc_wdata),\n    .spec_mem_addr(spec_insn_c_and_mem_addr),\n    .spec_mem_rmask(spec_insn_c_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_and_mem_wdata)\n  );\n\n  wire                                spec_insn_c_andi_valid;\n  wire                                spec_insn_c_andi_trap;\n  wire [                       4 : 0] spec_insn_c_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_andi insn_c_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_andi_valid),\n    .spec_trap(spec_insn_c_andi_trap),\n    .spec_rs1_addr(spec_insn_c_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_c_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_c_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_c_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_c_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_c_beqz_valid;\n  wire                                spec_insn_c_beqz_trap;\n  wire [                       4 : 0] spec_insn_c_beqz_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_beqz_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_beqz_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_beqz insn_c_beqz (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_beqz_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_beqz_valid),\n    .spec_trap(spec_insn_c_beqz_trap),\n    .spec_rs1_addr(spec_insn_c_beqz_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_beqz_rs2_addr),\n    .spec_rd_addr(spec_insn_c_beqz_rd_addr),\n    .spec_rd_wdata(spec_insn_c_beqz_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_beqz_pc_wdata),\n    .spec_mem_addr(spec_insn_c_beqz_mem_addr),\n    .spec_mem_rmask(spec_insn_c_beqz_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_beqz_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_beqz_mem_wdata)\n  );\n\n  wire                                spec_insn_c_bnez_valid;\n  wire                                spec_insn_c_bnez_trap;\n  wire [                       4 : 0] spec_insn_c_bnez_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_bnez_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_bnez_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_bnez insn_c_bnez (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_bnez_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_bnez_valid),\n    .spec_trap(spec_insn_c_bnez_trap),\n    .spec_rs1_addr(spec_insn_c_bnez_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_bnez_rs2_addr),\n    .spec_rd_addr(spec_insn_c_bnez_rd_addr),\n    .spec_rd_wdata(spec_insn_c_bnez_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_bnez_pc_wdata),\n    .spec_mem_addr(spec_insn_c_bnez_mem_addr),\n    .spec_mem_rmask(spec_insn_c_bnez_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_bnez_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_bnez_mem_wdata)\n  );\n\n  wire                                spec_insn_c_j_valid;\n  wire                                spec_insn_c_j_trap;\n  wire [                       4 : 0] spec_insn_c_j_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_j_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_j_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_j insn_c_j (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_j_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_j_valid),\n    .spec_trap(spec_insn_c_j_trap),\n    .spec_rs1_addr(spec_insn_c_j_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_j_rs2_addr),\n    .spec_rd_addr(spec_insn_c_j_rd_addr),\n    .spec_rd_wdata(spec_insn_c_j_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_j_pc_wdata),\n    .spec_mem_addr(spec_insn_c_j_mem_addr),\n    .spec_mem_rmask(spec_insn_c_j_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_j_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_j_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jal_valid;\n  wire                                spec_insn_c_jal_trap;\n  wire [                       4 : 0] spec_insn_c_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jal insn_c_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jal_valid),\n    .spec_trap(spec_insn_c_jal_trap),\n    .spec_rs1_addr(spec_insn_c_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jalr_valid;\n  wire                                spec_insn_c_jalr_trap;\n  wire [                       4 : 0] spec_insn_c_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jalr insn_c_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jalr_valid),\n    .spec_trap(spec_insn_c_jalr_trap),\n    .spec_rs1_addr(spec_insn_c_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jr_valid;\n  wire                                spec_insn_c_jr_trap;\n  wire [                       4 : 0] spec_insn_c_jr_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jr_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jr insn_c_jr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jr_valid),\n    .spec_trap(spec_insn_c_jr_trap),\n    .spec_rs1_addr(spec_insn_c_jr_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jr_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jr_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jr_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jr_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jr_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jr_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jr_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jr_mem_wdata)\n  );\n\n  wire                                spec_insn_c_li_valid;\n  wire                                spec_insn_c_li_trap;\n  wire [                       4 : 0] spec_insn_c_li_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_li_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_li_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_li insn_c_li (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_li_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_li_valid),\n    .spec_trap(spec_insn_c_li_trap),\n    .spec_rs1_addr(spec_insn_c_li_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_li_rs2_addr),\n    .spec_rd_addr(spec_insn_c_li_rd_addr),\n    .spec_rd_wdata(spec_insn_c_li_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_li_pc_wdata),\n    .spec_mem_addr(spec_insn_c_li_mem_addr),\n    .spec_mem_rmask(spec_insn_c_li_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_li_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_li_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lui_valid;\n  wire                                spec_insn_c_lui_trap;\n  wire [                       4 : 0] spec_insn_c_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lui insn_c_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lui_valid),\n    .spec_trap(spec_insn_c_lui_trap),\n    .spec_rs1_addr(spec_insn_c_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lw_valid;\n  wire                                spec_insn_c_lw_trap;\n  wire [                       4 : 0] spec_insn_c_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lw insn_c_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lw_valid),\n    .spec_trap(spec_insn_c_lw_trap),\n    .spec_rs1_addr(spec_insn_c_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lwsp_valid;\n  wire                                spec_insn_c_lwsp_trap;\n  wire [                       4 : 0] spec_insn_c_lwsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lwsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lwsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lwsp insn_c_lwsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lwsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lwsp_valid),\n    .spec_trap(spec_insn_c_lwsp_trap),\n    .spec_rs1_addr(spec_insn_c_lwsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lwsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lwsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lwsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lwsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lwsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lwsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lwsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lwsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_mv_valid;\n  wire                                spec_insn_c_mv_trap;\n  wire [                       4 : 0] spec_insn_c_mv_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_mv_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_mv_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_mv insn_c_mv (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_mv_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_mv_valid),\n    .spec_trap(spec_insn_c_mv_trap),\n    .spec_rs1_addr(spec_insn_c_mv_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_mv_rs2_addr),\n    .spec_rd_addr(spec_insn_c_mv_rd_addr),\n    .spec_rd_wdata(spec_insn_c_mv_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_mv_pc_wdata),\n    .spec_mem_addr(spec_insn_c_mv_mem_addr),\n    .spec_mem_rmask(spec_insn_c_mv_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_mv_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_mv_mem_wdata)\n  );\n\n  wire                                spec_insn_c_or_valid;\n  wire                                spec_insn_c_or_trap;\n  wire [                       4 : 0] spec_insn_c_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_or insn_c_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_or_valid),\n    .spec_trap(spec_insn_c_or_trap),\n    .spec_rs1_addr(spec_insn_c_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_or_rs2_addr),\n    .spec_rd_addr(spec_insn_c_or_rd_addr),\n    .spec_rd_wdata(spec_insn_c_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_or_pc_wdata),\n    .spec_mem_addr(spec_insn_c_or_mem_addr),\n    .spec_mem_rmask(spec_insn_c_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_or_mem_wdata)\n  );\n\n  wire                                spec_insn_c_slli_valid;\n  wire                                spec_insn_c_slli_trap;\n  wire [                       4 : 0] spec_insn_c_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_slli insn_c_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_slli_valid),\n    .spec_trap(spec_insn_c_slli_trap),\n    .spec_rs1_addr(spec_insn_c_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_c_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_c_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_c_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_c_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_c_srai_valid;\n  wire                                spec_insn_c_srai_trap;\n  wire [                       4 : 0] spec_insn_c_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_srai insn_c_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_srai_valid),\n    .spec_trap(spec_insn_c_srai_trap),\n    .spec_rs1_addr(spec_insn_c_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_c_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_c_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_c_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_c_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_c_srli_valid;\n  wire                                spec_insn_c_srli_trap;\n  wire [                       4 : 0] spec_insn_c_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_srli insn_c_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_srli_valid),\n    .spec_trap(spec_insn_c_srli_trap),\n    .spec_rs1_addr(spec_insn_c_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_c_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_c_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_c_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_c_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sub_valid;\n  wire                                spec_insn_c_sub_trap;\n  wire [                       4 : 0] spec_insn_c_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sub insn_c_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sub_valid),\n    .spec_trap(spec_insn_c_sub_trap),\n    .spec_rs1_addr(spec_insn_c_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sw_valid;\n  wire                                spec_insn_c_sw_trap;\n  wire [                       4 : 0] spec_insn_c_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sw insn_c_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sw_valid),\n    .spec_trap(spec_insn_c_sw_trap),\n    .spec_rs1_addr(spec_insn_c_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_swsp_valid;\n  wire                                spec_insn_c_swsp_trap;\n  wire [                       4 : 0] spec_insn_c_swsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_swsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_swsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_swsp insn_c_swsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_swsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_swsp_valid),\n    .spec_trap(spec_insn_c_swsp_trap),\n    .spec_rs1_addr(spec_insn_c_swsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_swsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_swsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_swsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_swsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_swsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_swsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_swsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_swsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_xor_valid;\n  wire                                spec_insn_c_xor_trap;\n  wire [                       4 : 0] spec_insn_c_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_xor insn_c_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_xor_valid),\n    .spec_trap(spec_insn_c_xor_trap),\n    .spec_rs1_addr(spec_insn_c_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_c_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_c_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_c_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_c_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_jal_valid;\n  wire                                spec_insn_jal_trap;\n  wire [                       4 : 0] spec_insn_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jal insn_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jal_valid),\n    .spec_trap(spec_insn_jal_trap),\n    .spec_rs1_addr(spec_insn_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_jalr_valid;\n  wire                                spec_insn_jalr_trap;\n  wire [                       4 : 0] spec_insn_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jalr insn_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jalr_valid),\n    .spec_trap(spec_insn_jalr_trap),\n    .spec_rs1_addr(spec_insn_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_lb_valid;\n  wire                                spec_insn_lb_trap;\n  wire [                       4 : 0] spec_insn_lb_rs1_addr;\n  wire [                       4 : 0] spec_insn_lb_rs2_addr;\n  wire [                       4 : 0] spec_insn_lb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lb insn_lb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lb_valid),\n    .spec_trap(spec_insn_lb_trap),\n    .spec_rs1_addr(spec_insn_lb_rs1_addr),\n    .spec_rs2_addr(spec_insn_lb_rs2_addr),\n    .spec_rd_addr(spec_insn_lb_rd_addr),\n    .spec_rd_wdata(spec_insn_lb_rd_wdata),\n    .spec_pc_wdata(spec_insn_lb_pc_wdata),\n    .spec_mem_addr(spec_insn_lb_mem_addr),\n    .spec_mem_rmask(spec_insn_lb_mem_rmask),\n    .spec_mem_wmask(spec_insn_lb_mem_wmask),\n    .spec_mem_wdata(spec_insn_lb_mem_wdata)\n  );\n\n  wire                                spec_insn_lbu_valid;\n  wire                                spec_insn_lbu_trap;\n  wire [                       4 : 0] spec_insn_lbu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lbu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lbu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lbu insn_lbu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lbu_valid),\n    .spec_trap(spec_insn_lbu_trap),\n    .spec_rs1_addr(spec_insn_lbu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lbu_rs2_addr),\n    .spec_rd_addr(spec_insn_lbu_rd_addr),\n    .spec_rd_wdata(spec_insn_lbu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lbu_pc_wdata),\n    .spec_mem_addr(spec_insn_lbu_mem_addr),\n    .spec_mem_rmask(spec_insn_lbu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lbu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lbu_mem_wdata)\n  );\n\n  wire                                spec_insn_lh_valid;\n  wire                                spec_insn_lh_trap;\n  wire [                       4 : 0] spec_insn_lh_rs1_addr;\n  wire [                       4 : 0] spec_insn_lh_rs2_addr;\n  wire [                       4 : 0] spec_insn_lh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lh insn_lh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lh_valid),\n    .spec_trap(spec_insn_lh_trap),\n    .spec_rs1_addr(spec_insn_lh_rs1_addr),\n    .spec_rs2_addr(spec_insn_lh_rs2_addr),\n    .spec_rd_addr(spec_insn_lh_rd_addr),\n    .spec_rd_wdata(spec_insn_lh_rd_wdata),\n    .spec_pc_wdata(spec_insn_lh_pc_wdata),\n    .spec_mem_addr(spec_insn_lh_mem_addr),\n    .spec_mem_rmask(spec_insn_lh_mem_rmask),\n    .spec_mem_wmask(spec_insn_lh_mem_wmask),\n    .spec_mem_wdata(spec_insn_lh_mem_wdata)\n  );\n\n  wire                                spec_insn_lhu_valid;\n  wire                                spec_insn_lhu_trap;\n  wire [                       4 : 0] spec_insn_lhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lhu insn_lhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lhu_valid),\n    .spec_trap(spec_insn_lhu_trap),\n    .spec_rs1_addr(spec_insn_lhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lhu_rs2_addr),\n    .spec_rd_addr(spec_insn_lhu_rd_addr),\n    .spec_rd_wdata(spec_insn_lhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lhu_pc_wdata),\n    .spec_mem_addr(spec_insn_lhu_mem_addr),\n    .spec_mem_rmask(spec_insn_lhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lhu_mem_wdata)\n  );\n\n  wire                                spec_insn_lui_valid;\n  wire                                spec_insn_lui_trap;\n  wire [                       4 : 0] spec_insn_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lui insn_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lui_valid),\n    .spec_trap(spec_insn_lui_trap),\n    .spec_rs1_addr(spec_insn_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_lw_valid;\n  wire                                spec_insn_lw_trap;\n  wire [                       4 : 0] spec_insn_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lw insn_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lw_valid),\n    .spec_trap(spec_insn_lw_trap),\n    .spec_rs1_addr(spec_insn_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_or_valid;\n  wire                                spec_insn_or_trap;\n  wire [                       4 : 0] spec_insn_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_or insn_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_or_valid),\n    .spec_trap(spec_insn_or_trap),\n    .spec_rs1_addr(spec_insn_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_or_rs2_addr),\n    .spec_rd_addr(spec_insn_or_rd_addr),\n    .spec_rd_wdata(spec_insn_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_or_pc_wdata),\n    .spec_mem_addr(spec_insn_or_mem_addr),\n    .spec_mem_rmask(spec_insn_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_or_mem_wdata)\n  );\n\n  wire                                spec_insn_ori_valid;\n  wire                                spec_insn_ori_trap;\n  wire [                       4 : 0] spec_insn_ori_rs1_addr;\n  wire [                       4 : 0] spec_insn_ori_rs2_addr;\n  wire [                       4 : 0] spec_insn_ori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ori insn_ori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ori_valid),\n    .spec_trap(spec_insn_ori_trap),\n    .spec_rs1_addr(spec_insn_ori_rs1_addr),\n    .spec_rs2_addr(spec_insn_ori_rs2_addr),\n    .spec_rd_addr(spec_insn_ori_rd_addr),\n    .spec_rd_wdata(spec_insn_ori_rd_wdata),\n    .spec_pc_wdata(spec_insn_ori_pc_wdata),\n    .spec_mem_addr(spec_insn_ori_mem_addr),\n    .spec_mem_rmask(spec_insn_ori_mem_rmask),\n    .spec_mem_wmask(spec_insn_ori_mem_wmask),\n    .spec_mem_wdata(spec_insn_ori_mem_wdata)\n  );\n\n  wire                                spec_insn_sb_valid;\n  wire                                spec_insn_sb_trap;\n  wire [                       4 : 0] spec_insn_sb_rs1_addr;\n  wire [                       4 : 0] spec_insn_sb_rs2_addr;\n  wire [                       4 : 0] spec_insn_sb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sb insn_sb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sb_valid),\n    .spec_trap(spec_insn_sb_trap),\n    .spec_rs1_addr(spec_insn_sb_rs1_addr),\n    .spec_rs2_addr(spec_insn_sb_rs2_addr),\n    .spec_rd_addr(spec_insn_sb_rd_addr),\n    .spec_rd_wdata(spec_insn_sb_rd_wdata),\n    .spec_pc_wdata(spec_insn_sb_pc_wdata),\n    .spec_mem_addr(spec_insn_sb_mem_addr),\n    .spec_mem_rmask(spec_insn_sb_mem_rmask),\n    .spec_mem_wmask(spec_insn_sb_mem_wmask),\n    .spec_mem_wdata(spec_insn_sb_mem_wdata)\n  );\n\n  wire                                spec_insn_sh_valid;\n  wire                                spec_insn_sh_trap;\n  wire [                       4 : 0] spec_insn_sh_rs1_addr;\n  wire [                       4 : 0] spec_insn_sh_rs2_addr;\n  wire [                       4 : 0] spec_insn_sh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sh insn_sh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sh_valid),\n    .spec_trap(spec_insn_sh_trap),\n    .spec_rs1_addr(spec_insn_sh_rs1_addr),\n    .spec_rs2_addr(spec_insn_sh_rs2_addr),\n    .spec_rd_addr(spec_insn_sh_rd_addr),\n    .spec_rd_wdata(spec_insn_sh_rd_wdata),\n    .spec_pc_wdata(spec_insn_sh_pc_wdata),\n    .spec_mem_addr(spec_insn_sh_mem_addr),\n    .spec_mem_rmask(spec_insn_sh_mem_rmask),\n    .spec_mem_wmask(spec_insn_sh_mem_wmask),\n    .spec_mem_wdata(spec_insn_sh_mem_wdata)\n  );\n\n  wire                                spec_insn_sll_valid;\n  wire                                spec_insn_sll_trap;\n  wire [                       4 : 0] spec_insn_sll_rs1_addr;\n  wire [                       4 : 0] spec_insn_sll_rs2_addr;\n  wire [                       4 : 0] spec_insn_sll_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sll insn_sll (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sll_valid),\n    .spec_trap(spec_insn_sll_trap),\n    .spec_rs1_addr(spec_insn_sll_rs1_addr),\n    .spec_rs2_addr(spec_insn_sll_rs2_addr),\n    .spec_rd_addr(spec_insn_sll_rd_addr),\n    .spec_rd_wdata(spec_insn_sll_rd_wdata),\n    .spec_pc_wdata(spec_insn_sll_pc_wdata),\n    .spec_mem_addr(spec_insn_sll_mem_addr),\n    .spec_mem_rmask(spec_insn_sll_mem_rmask),\n    .spec_mem_wmask(spec_insn_sll_mem_wmask),\n    .spec_mem_wdata(spec_insn_sll_mem_wdata)\n  );\n\n  wire                                spec_insn_slli_valid;\n  wire                                spec_insn_slli_trap;\n  wire [                       4 : 0] spec_insn_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slli insn_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slli_valid),\n    .spec_trap(spec_insn_slli_trap),\n    .spec_rs1_addr(spec_insn_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_slt_valid;\n  wire                                spec_insn_slt_trap;\n  wire [                       4 : 0] spec_insn_slt_rs1_addr;\n  wire [                       4 : 0] spec_insn_slt_rs2_addr;\n  wire [                       4 : 0] spec_insn_slt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slt insn_slt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slt_valid),\n    .spec_trap(spec_insn_slt_trap),\n    .spec_rs1_addr(spec_insn_slt_rs1_addr),\n    .spec_rs2_addr(spec_insn_slt_rs2_addr),\n    .spec_rd_addr(spec_insn_slt_rd_addr),\n    .spec_rd_wdata(spec_insn_slt_rd_wdata),\n    .spec_pc_wdata(spec_insn_slt_pc_wdata),\n    .spec_mem_addr(spec_insn_slt_mem_addr),\n    .spec_mem_rmask(spec_insn_slt_mem_rmask),\n    .spec_mem_wmask(spec_insn_slt_mem_wmask),\n    .spec_mem_wdata(spec_insn_slt_mem_wdata)\n  );\n\n  wire                                spec_insn_slti_valid;\n  wire                                spec_insn_slti_trap;\n  wire [                       4 : 0] spec_insn_slti_rs1_addr;\n  wire [                       4 : 0] spec_insn_slti_rs2_addr;\n  wire [                       4 : 0] spec_insn_slti_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slti insn_slti (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slti_valid),\n    .spec_trap(spec_insn_slti_trap),\n    .spec_rs1_addr(spec_insn_slti_rs1_addr),\n    .spec_rs2_addr(spec_insn_slti_rs2_addr),\n    .spec_rd_addr(spec_insn_slti_rd_addr),\n    .spec_rd_wdata(spec_insn_slti_rd_wdata),\n    .spec_pc_wdata(spec_insn_slti_pc_wdata),\n    .spec_mem_addr(spec_insn_slti_mem_addr),\n    .spec_mem_rmask(spec_insn_slti_mem_rmask),\n    .spec_mem_wmask(spec_insn_slti_mem_wmask),\n    .spec_mem_wdata(spec_insn_slti_mem_wdata)\n  );\n\n  wire                                spec_insn_sltiu_valid;\n  wire                                spec_insn_sltiu_trap;\n  wire [                       4 : 0] spec_insn_sltiu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltiu insn_sltiu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltiu_valid),\n    .spec_trap(spec_insn_sltiu_trap),\n    .spec_rs1_addr(spec_insn_sltiu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltiu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltiu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltiu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltiu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltiu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltiu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltiu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltiu_mem_wdata)\n  );\n\n  wire                                spec_insn_sltu_valid;\n  wire                                spec_insn_sltu_trap;\n  wire [                       4 : 0] spec_insn_sltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltu insn_sltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltu_valid),\n    .spec_trap(spec_insn_sltu_trap),\n    .spec_rs1_addr(spec_insn_sltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltu_mem_wdata)\n  );\n\n  wire                                spec_insn_sra_valid;\n  wire                                spec_insn_sra_trap;\n  wire [                       4 : 0] spec_insn_sra_rs1_addr;\n  wire [                       4 : 0] spec_insn_sra_rs2_addr;\n  wire [                       4 : 0] spec_insn_sra_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sra insn_sra (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sra_valid),\n    .spec_trap(spec_insn_sra_trap),\n    .spec_rs1_addr(spec_insn_sra_rs1_addr),\n    .spec_rs2_addr(spec_insn_sra_rs2_addr),\n    .spec_rd_addr(spec_insn_sra_rd_addr),\n    .spec_rd_wdata(spec_insn_sra_rd_wdata),\n    .spec_pc_wdata(spec_insn_sra_pc_wdata),\n    .spec_mem_addr(spec_insn_sra_mem_addr),\n    .spec_mem_rmask(spec_insn_sra_mem_rmask),\n    .spec_mem_wmask(spec_insn_sra_mem_wmask),\n    .spec_mem_wdata(spec_insn_sra_mem_wdata)\n  );\n\n  wire                                spec_insn_srai_valid;\n  wire                                spec_insn_srai_trap;\n  wire [                       4 : 0] spec_insn_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srai insn_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srai_valid),\n    .spec_trap(spec_insn_srai_trap),\n    .spec_rs1_addr(spec_insn_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_srl_valid;\n  wire                                spec_insn_srl_trap;\n  wire [                       4 : 0] spec_insn_srl_rs1_addr;\n  wire [                       4 : 0] spec_insn_srl_rs2_addr;\n  wire [                       4 : 0] spec_insn_srl_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srl insn_srl (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srl_valid),\n    .spec_trap(spec_insn_srl_trap),\n    .spec_rs1_addr(spec_insn_srl_rs1_addr),\n    .spec_rs2_addr(spec_insn_srl_rs2_addr),\n    .spec_rd_addr(spec_insn_srl_rd_addr),\n    .spec_rd_wdata(spec_insn_srl_rd_wdata),\n    .spec_pc_wdata(spec_insn_srl_pc_wdata),\n    .spec_mem_addr(spec_insn_srl_mem_addr),\n    .spec_mem_rmask(spec_insn_srl_mem_rmask),\n    .spec_mem_wmask(spec_insn_srl_mem_wmask),\n    .spec_mem_wdata(spec_insn_srl_mem_wdata)\n  );\n\n  wire                                spec_insn_srli_valid;\n  wire                                spec_insn_srli_trap;\n  wire [                       4 : 0] spec_insn_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srli insn_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srli_valid),\n    .spec_trap(spec_insn_srli_trap),\n    .spec_rs1_addr(spec_insn_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_sub_valid;\n  wire                                spec_insn_sub_trap;\n  wire [                       4 : 0] spec_insn_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sub insn_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sub_valid),\n    .spec_trap(spec_insn_sub_trap),\n    .spec_rs1_addr(spec_insn_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_sw_valid;\n  wire                                spec_insn_sw_trap;\n  wire [                       4 : 0] spec_insn_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sw insn_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sw_valid),\n    .spec_trap(spec_insn_sw_trap),\n    .spec_rs1_addr(spec_insn_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_xor_valid;\n  wire                                spec_insn_xor_trap;\n  wire [                       4 : 0] spec_insn_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xor insn_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xor_valid),\n    .spec_trap(spec_insn_xor_trap),\n    .spec_rs1_addr(spec_insn_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_xori_valid;\n  wire                                spec_insn_xori_trap;\n  wire [                       4 : 0] spec_insn_xori_rs1_addr;\n  wire [                       4 : 0] spec_insn_xori_rs2_addr;\n  wire [                       4 : 0] spec_insn_xori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xori insn_xori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xori_valid),\n    .spec_trap(spec_insn_xori_trap),\n    .spec_rs1_addr(spec_insn_xori_rs1_addr),\n    .spec_rs2_addr(spec_insn_xori_rs2_addr),\n    .spec_rd_addr(spec_insn_xori_rd_addr),\n    .spec_rd_wdata(spec_insn_xori_rd_wdata),\n    .spec_pc_wdata(spec_insn_xori_pc_wdata),\n    .spec_mem_addr(spec_insn_xori_mem_addr),\n    .spec_mem_rmask(spec_insn_xori_mem_rmask),\n    .spec_mem_wmask(spec_insn_xori_mem_wmask),\n    .spec_mem_wdata(spec_insn_xori_mem_wdata)\n  );\n\n  assign spec_valid =\n\t\tspec_insn_add_valid ? spec_insn_add_valid :\n\t\tspec_insn_addi_valid ? spec_insn_addi_valid :\n\t\tspec_insn_and_valid ? spec_insn_and_valid :\n\t\tspec_insn_andi_valid ? spec_insn_andi_valid :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_valid :\n\t\tspec_insn_beq_valid ? spec_insn_beq_valid :\n\t\tspec_insn_bge_valid ? spec_insn_bge_valid :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_valid :\n\t\tspec_insn_blt_valid ? spec_insn_blt_valid :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_valid :\n\t\tspec_insn_bne_valid ? spec_insn_bne_valid :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_valid :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_valid :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_valid :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_valid :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_valid :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_valid :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_valid :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_valid :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_valid :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_valid :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_valid :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_valid :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_valid :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_valid :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_valid :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_valid :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_valid :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_valid :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_valid :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_valid :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_valid :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_valid :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_valid :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_valid :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_valid :\n\t\tspec_insn_jal_valid ? spec_insn_jal_valid :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_valid :\n\t\tspec_insn_lb_valid ? spec_insn_lb_valid :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_valid :\n\t\tspec_insn_lh_valid ? spec_insn_lh_valid :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_valid :\n\t\tspec_insn_lui_valid ? spec_insn_lui_valid :\n\t\tspec_insn_lw_valid ? spec_insn_lw_valid :\n\t\tspec_insn_or_valid ? spec_insn_or_valid :\n\t\tspec_insn_ori_valid ? spec_insn_ori_valid :\n\t\tspec_insn_sb_valid ? spec_insn_sb_valid :\n\t\tspec_insn_sh_valid ? spec_insn_sh_valid :\n\t\tspec_insn_sll_valid ? spec_insn_sll_valid :\n\t\tspec_insn_slli_valid ? spec_insn_slli_valid :\n\t\tspec_insn_slt_valid ? spec_insn_slt_valid :\n\t\tspec_insn_slti_valid ? spec_insn_slti_valid :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_valid :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_valid :\n\t\tspec_insn_sra_valid ? spec_insn_sra_valid :\n\t\tspec_insn_srai_valid ? spec_insn_srai_valid :\n\t\tspec_insn_srl_valid ? spec_insn_srl_valid :\n\t\tspec_insn_srli_valid ? spec_insn_srli_valid :\n\t\tspec_insn_sub_valid ? spec_insn_sub_valid :\n\t\tspec_insn_sw_valid ? spec_insn_sw_valid :\n\t\tspec_insn_xor_valid ? spec_insn_xor_valid :\n\t\tspec_insn_xori_valid ? spec_insn_xori_valid : 0;\n  assign spec_trap =\n\t\tspec_insn_add_valid ? spec_insn_add_trap :\n\t\tspec_insn_addi_valid ? spec_insn_addi_trap :\n\t\tspec_insn_and_valid ? spec_insn_and_trap :\n\t\tspec_insn_andi_valid ? spec_insn_andi_trap :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_trap :\n\t\tspec_insn_beq_valid ? spec_insn_beq_trap :\n\t\tspec_insn_bge_valid ? spec_insn_bge_trap :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_trap :\n\t\tspec_insn_blt_valid ? spec_insn_blt_trap :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_trap :\n\t\tspec_insn_bne_valid ? spec_insn_bne_trap :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_trap :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_trap :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_trap :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_trap :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_trap :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_trap :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_trap :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_trap :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_trap :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_trap :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_trap :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_trap :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_trap :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_trap :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_trap :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_trap :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_trap :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_trap :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_trap :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_trap :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_trap :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_trap :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_trap :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_trap :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_trap :\n\t\tspec_insn_jal_valid ? spec_insn_jal_trap :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_trap :\n\t\tspec_insn_lb_valid ? spec_insn_lb_trap :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_trap :\n\t\tspec_insn_lh_valid ? spec_insn_lh_trap :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_trap :\n\t\tspec_insn_lui_valid ? spec_insn_lui_trap :\n\t\tspec_insn_lw_valid ? spec_insn_lw_trap :\n\t\tspec_insn_or_valid ? spec_insn_or_trap :\n\t\tspec_insn_ori_valid ? spec_insn_ori_trap :\n\t\tspec_insn_sb_valid ? spec_insn_sb_trap :\n\t\tspec_insn_sh_valid ? spec_insn_sh_trap :\n\t\tspec_insn_sll_valid ? spec_insn_sll_trap :\n\t\tspec_insn_slli_valid ? spec_insn_slli_trap :\n\t\tspec_insn_slt_valid ? spec_insn_slt_trap :\n\t\tspec_insn_slti_valid ? spec_insn_slti_trap :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_trap :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_trap :\n\t\tspec_insn_sra_valid ? spec_insn_sra_trap :\n\t\tspec_insn_srai_valid ? spec_insn_srai_trap :\n\t\tspec_insn_srl_valid ? spec_insn_srl_trap :\n\t\tspec_insn_srli_valid ? spec_insn_srli_trap :\n\t\tspec_insn_sub_valid ? spec_insn_sub_trap :\n\t\tspec_insn_sw_valid ? spec_insn_sw_trap :\n\t\tspec_insn_xor_valid ? spec_insn_xor_trap :\n\t\tspec_insn_xori_valid ? spec_insn_xori_trap : 0;\n  assign spec_rs1_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs1_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs1_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs1_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs1_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs1_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs1_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs1_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs1_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs1_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs1_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rs1_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rs1_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs1_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs1_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rs1_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rs1_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rs1_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rs1_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rs1_addr :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_rs1_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rs1_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rs1_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rs1_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rs1_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rs1_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs1_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rs1_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rs1_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rs1_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rs1_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rs1_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rs1_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rs1_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rs1_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rs1_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs1_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs1_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs1_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs1_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs1_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs1_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs1_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs1_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs1_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs1_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs1_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs1_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs1_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs1_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs1_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs1_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs1_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs1_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs1_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs1_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs1_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs1_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs1_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs1_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0;\n  assign spec_rs2_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs2_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs2_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs2_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs2_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs2_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs2_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs2_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs2_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs2_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs2_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rs2_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rs2_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs2_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs2_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rs2_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rs2_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rs2_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rs2_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rs2_addr :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_rs2_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rs2_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rs2_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rs2_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rs2_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rs2_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs2_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rs2_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rs2_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rs2_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rs2_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rs2_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rs2_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rs2_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rs2_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rs2_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs2_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs2_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs2_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs2_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs2_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs2_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs2_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs2_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs2_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs2_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs2_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs2_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs2_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs2_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs2_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs2_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs2_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs2_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs2_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs2_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs2_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs2_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs2_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs2_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0;\n  assign spec_rd_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rd_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rd_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rd_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rd_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rd_addr :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_rd_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rd_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rd_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rd_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rd_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rd_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rd_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rd_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rd_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rd_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rd_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rd_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rd_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_addr : 0;\n  assign spec_rd_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rd_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rd_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rd_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rd_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rd_wdata :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_rd_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rd_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rd_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rd_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rd_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rd_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rd_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rd_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rd_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rd_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rd_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rd_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rd_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0;\n  assign spec_pc_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_pc_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_pc_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_pc_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_pc_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_pc_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_pc_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_pc_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_pc_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_pc_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_pc_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_pc_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_pc_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_pc_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_pc_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_pc_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_pc_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_pc_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_pc_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_pc_wdata :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_pc_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_pc_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_pc_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_pc_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_pc_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_pc_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_pc_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_pc_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_pc_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_pc_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_pc_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_pc_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_pc_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_pc_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_pc_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_pc_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_pc_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_pc_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_pc_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_pc_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_pc_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_pc_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_pc_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_pc_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_pc_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_pc_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_pc_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_pc_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_pc_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_pc_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_pc_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_pc_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_pc_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_pc_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_pc_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_pc_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_pc_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_pc_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_pc_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_pc_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0;\n  assign spec_mem_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_addr :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_mem_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_addr : 0;\n  assign spec_mem_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_rmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_rmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_rmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_rmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_rmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_rmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_rmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_rmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_rmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_rmask :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_mem_rmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_rmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_rmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_rmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_rmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_rmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_rmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_rmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_rmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_rmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_rmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_rmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_rmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_rmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_rmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0;\n  assign spec_mem_wmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_wmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_wmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_wmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_wmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_wmask :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_mem_wmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_wmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_wmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_wmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_wmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_wmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_wmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_wmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_wmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_wmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_wmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_wmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_wmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0;\n  assign spec_mem_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_wdata :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_mem_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0;\n`ifdef RISCV_FORMAL_CSR_MISA\n  assign spec_csr_misa_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_csr_misa_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_csr_misa_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_csr_misa_rmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_csr_misa_rmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_csr_misa_rmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_csr_misa_rmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_csr_misa_rmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_csr_misa_rmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_csr_misa_rmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_csr_misa_rmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_csr_misa_rmask :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_csr_misa_rmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_csr_misa_rmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_csr_misa_rmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_csr_misa_rmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_csr_misa_rmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_csr_misa_rmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_csr_misa_rmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_csr_misa_rmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_csr_misa_rmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_csr_misa_rmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_csr_misa_rmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_csr_misa_rmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_csr_misa_rmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_csr_misa_rmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_csr_misa_rmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_csr_misa_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_csr_misa_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0;\n`endif\nendmodule\n"
  },
  {
    "path": "insns/isa_rv32im.txt",
    "content": "add\naddi\nand\nandi\nauipc\nbeq\nbge\nbgeu\nblt\nbltu\nbne\ndiv\ndivu\njal\njalr\nlb\nlbu\nlh\nlhu\nlui\nlw\nmul\nmulh\nmulhsu\nmulhu\nor\nori\nrem\nremu\nsb\nsh\nsll\nslli\nslt\nslti\nsltiu\nsltu\nsra\nsrai\nsrl\nsrli\nsub\nsw\nxor\nxori\n"
  },
  {
    "path": "insns/isa_rv32im.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_isa_rv32im (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n  wire                                spec_insn_add_valid;\n  wire                                spec_insn_add_trap;\n  wire [                       4 : 0] spec_insn_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_add insn_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_add_valid),\n    .spec_trap(spec_insn_add_trap),\n    .spec_rs1_addr(spec_insn_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_add_rs2_addr),\n    .spec_rd_addr(spec_insn_add_rd_addr),\n    .spec_rd_wdata(spec_insn_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_add_pc_wdata),\n    .spec_mem_addr(spec_insn_add_mem_addr),\n    .spec_mem_rmask(spec_insn_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_add_mem_wdata)\n  );\n\n  wire                                spec_insn_addi_valid;\n  wire                                spec_insn_addi_trap;\n  wire [                       4 : 0] spec_insn_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addi insn_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addi_valid),\n    .spec_trap(spec_insn_addi_trap),\n    .spec_rs1_addr(spec_insn_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_and_valid;\n  wire                                spec_insn_and_trap;\n  wire [                       4 : 0] spec_insn_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_and insn_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_and_valid),\n    .spec_trap(spec_insn_and_trap),\n    .spec_rs1_addr(spec_insn_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_and_rs2_addr),\n    .spec_rd_addr(spec_insn_and_rd_addr),\n    .spec_rd_wdata(spec_insn_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_and_pc_wdata),\n    .spec_mem_addr(spec_insn_and_mem_addr),\n    .spec_mem_rmask(spec_insn_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_and_mem_wdata)\n  );\n\n  wire                                spec_insn_andi_valid;\n  wire                                spec_insn_andi_trap;\n  wire [                       4 : 0] spec_insn_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_andi insn_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_andi_valid),\n    .spec_trap(spec_insn_andi_trap),\n    .spec_rs1_addr(spec_insn_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_auipc_valid;\n  wire                                spec_insn_auipc_trap;\n  wire [                       4 : 0] spec_insn_auipc_rs1_addr;\n  wire [                       4 : 0] spec_insn_auipc_rs2_addr;\n  wire [                       4 : 0] spec_insn_auipc_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_csr_misa_rmask;\n`endif\n\n  rvfi_insn_auipc insn_auipc (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_auipc_valid),\n    .spec_trap(spec_insn_auipc_trap),\n    .spec_rs1_addr(spec_insn_auipc_rs1_addr),\n    .spec_rs2_addr(spec_insn_auipc_rs2_addr),\n    .spec_rd_addr(spec_insn_auipc_rd_addr),\n    .spec_rd_wdata(spec_insn_auipc_rd_wdata),\n    .spec_pc_wdata(spec_insn_auipc_pc_wdata),\n    .spec_mem_addr(spec_insn_auipc_mem_addr),\n    .spec_mem_rmask(spec_insn_auipc_mem_rmask),\n    .spec_mem_wmask(spec_insn_auipc_mem_wmask),\n    .spec_mem_wdata(spec_insn_auipc_mem_wdata)\n  );\n\n  wire                                spec_insn_beq_valid;\n  wire                                spec_insn_beq_trap;\n  wire [                       4 : 0] spec_insn_beq_rs1_addr;\n  wire [                       4 : 0] spec_insn_beq_rs2_addr;\n  wire [                       4 : 0] spec_insn_beq_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_csr_misa_rmask;\n`endif\n\n  rvfi_insn_beq insn_beq (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_beq_valid),\n    .spec_trap(spec_insn_beq_trap),\n    .spec_rs1_addr(spec_insn_beq_rs1_addr),\n    .spec_rs2_addr(spec_insn_beq_rs2_addr),\n    .spec_rd_addr(spec_insn_beq_rd_addr),\n    .spec_rd_wdata(spec_insn_beq_rd_wdata),\n    .spec_pc_wdata(spec_insn_beq_pc_wdata),\n    .spec_mem_addr(spec_insn_beq_mem_addr),\n    .spec_mem_rmask(spec_insn_beq_mem_rmask),\n    .spec_mem_wmask(spec_insn_beq_mem_wmask),\n    .spec_mem_wdata(spec_insn_beq_mem_wdata)\n  );\n\n  wire                                spec_insn_bge_valid;\n  wire                                spec_insn_bge_trap;\n  wire [                       4 : 0] spec_insn_bge_rs1_addr;\n  wire [                       4 : 0] spec_insn_bge_rs2_addr;\n  wire [                       4 : 0] spec_insn_bge_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bge insn_bge (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bge_valid),\n    .spec_trap(spec_insn_bge_trap),\n    .spec_rs1_addr(spec_insn_bge_rs1_addr),\n    .spec_rs2_addr(spec_insn_bge_rs2_addr),\n    .spec_rd_addr(spec_insn_bge_rd_addr),\n    .spec_rd_wdata(spec_insn_bge_rd_wdata),\n    .spec_pc_wdata(spec_insn_bge_pc_wdata),\n    .spec_mem_addr(spec_insn_bge_mem_addr),\n    .spec_mem_rmask(spec_insn_bge_mem_rmask),\n    .spec_mem_wmask(spec_insn_bge_mem_wmask),\n    .spec_mem_wdata(spec_insn_bge_mem_wdata)\n  );\n\n  wire                                spec_insn_bgeu_valid;\n  wire                                spec_insn_bgeu_trap;\n  wire [                       4 : 0] spec_insn_bgeu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bgeu insn_bgeu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bgeu_valid),\n    .spec_trap(spec_insn_bgeu_trap),\n    .spec_rs1_addr(spec_insn_bgeu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bgeu_rs2_addr),\n    .spec_rd_addr(spec_insn_bgeu_rd_addr),\n    .spec_rd_wdata(spec_insn_bgeu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bgeu_pc_wdata),\n    .spec_mem_addr(spec_insn_bgeu_mem_addr),\n    .spec_mem_rmask(spec_insn_bgeu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bgeu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bgeu_mem_wdata)\n  );\n\n  wire                                spec_insn_blt_valid;\n  wire                                spec_insn_blt_trap;\n  wire [                       4 : 0] spec_insn_blt_rs1_addr;\n  wire [                       4 : 0] spec_insn_blt_rs2_addr;\n  wire [                       4 : 0] spec_insn_blt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_blt insn_blt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_blt_valid),\n    .spec_trap(spec_insn_blt_trap),\n    .spec_rs1_addr(spec_insn_blt_rs1_addr),\n    .spec_rs2_addr(spec_insn_blt_rs2_addr),\n    .spec_rd_addr(spec_insn_blt_rd_addr),\n    .spec_rd_wdata(spec_insn_blt_rd_wdata),\n    .spec_pc_wdata(spec_insn_blt_pc_wdata),\n    .spec_mem_addr(spec_insn_blt_mem_addr),\n    .spec_mem_rmask(spec_insn_blt_mem_rmask),\n    .spec_mem_wmask(spec_insn_blt_mem_wmask),\n    .spec_mem_wdata(spec_insn_blt_mem_wdata)\n  );\n\n  wire                                spec_insn_bltu_valid;\n  wire                                spec_insn_bltu_trap;\n  wire [                       4 : 0] spec_insn_bltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bltu insn_bltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bltu_valid),\n    .spec_trap(spec_insn_bltu_trap),\n    .spec_rs1_addr(spec_insn_bltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bltu_rs2_addr),\n    .spec_rd_addr(spec_insn_bltu_rd_addr),\n    .spec_rd_wdata(spec_insn_bltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bltu_pc_wdata),\n    .spec_mem_addr(spec_insn_bltu_mem_addr),\n    .spec_mem_rmask(spec_insn_bltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bltu_mem_wdata)\n  );\n\n  wire                                spec_insn_bne_valid;\n  wire                                spec_insn_bne_trap;\n  wire [                       4 : 0] spec_insn_bne_rs1_addr;\n  wire [                       4 : 0] spec_insn_bne_rs2_addr;\n  wire [                       4 : 0] spec_insn_bne_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bne insn_bne (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bne_valid),\n    .spec_trap(spec_insn_bne_trap),\n    .spec_rs1_addr(spec_insn_bne_rs1_addr),\n    .spec_rs2_addr(spec_insn_bne_rs2_addr),\n    .spec_rd_addr(spec_insn_bne_rd_addr),\n    .spec_rd_wdata(spec_insn_bne_rd_wdata),\n    .spec_pc_wdata(spec_insn_bne_pc_wdata),\n    .spec_mem_addr(spec_insn_bne_mem_addr),\n    .spec_mem_rmask(spec_insn_bne_mem_rmask),\n    .spec_mem_wmask(spec_insn_bne_mem_wmask),\n    .spec_mem_wdata(spec_insn_bne_mem_wdata)\n  );\n\n  wire                                spec_insn_div_valid;\n  wire                                spec_insn_div_trap;\n  wire [                       4 : 0] spec_insn_div_rs1_addr;\n  wire [                       4 : 0] spec_insn_div_rs2_addr;\n  wire [                       4 : 0] spec_insn_div_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_csr_misa_rmask;\n`endif\n\n  rvfi_insn_div insn_div (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_div_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_div_valid),\n    .spec_trap(spec_insn_div_trap),\n    .spec_rs1_addr(spec_insn_div_rs1_addr),\n    .spec_rs2_addr(spec_insn_div_rs2_addr),\n    .spec_rd_addr(spec_insn_div_rd_addr),\n    .spec_rd_wdata(spec_insn_div_rd_wdata),\n    .spec_pc_wdata(spec_insn_div_pc_wdata),\n    .spec_mem_addr(spec_insn_div_mem_addr),\n    .spec_mem_rmask(spec_insn_div_mem_rmask),\n    .spec_mem_wmask(spec_insn_div_mem_wmask),\n    .spec_mem_wdata(spec_insn_div_mem_wdata)\n  );\n\n  wire                                spec_insn_divu_valid;\n  wire                                spec_insn_divu_trap;\n  wire [                       4 : 0] spec_insn_divu_rs1_addr;\n  wire [                       4 : 0] spec_insn_divu_rs2_addr;\n  wire [                       4 : 0] spec_insn_divu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_divu insn_divu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_divu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_divu_valid),\n    .spec_trap(spec_insn_divu_trap),\n    .spec_rs1_addr(spec_insn_divu_rs1_addr),\n    .spec_rs2_addr(spec_insn_divu_rs2_addr),\n    .spec_rd_addr(spec_insn_divu_rd_addr),\n    .spec_rd_wdata(spec_insn_divu_rd_wdata),\n    .spec_pc_wdata(spec_insn_divu_pc_wdata),\n    .spec_mem_addr(spec_insn_divu_mem_addr),\n    .spec_mem_rmask(spec_insn_divu_mem_rmask),\n    .spec_mem_wmask(spec_insn_divu_mem_wmask),\n    .spec_mem_wdata(spec_insn_divu_mem_wdata)\n  );\n\n  wire                                spec_insn_jal_valid;\n  wire                                spec_insn_jal_trap;\n  wire [                       4 : 0] spec_insn_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jal insn_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jal_valid),\n    .spec_trap(spec_insn_jal_trap),\n    .spec_rs1_addr(spec_insn_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_jalr_valid;\n  wire                                spec_insn_jalr_trap;\n  wire [                       4 : 0] spec_insn_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jalr insn_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jalr_valid),\n    .spec_trap(spec_insn_jalr_trap),\n    .spec_rs1_addr(spec_insn_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_lb_valid;\n  wire                                spec_insn_lb_trap;\n  wire [                       4 : 0] spec_insn_lb_rs1_addr;\n  wire [                       4 : 0] spec_insn_lb_rs2_addr;\n  wire [                       4 : 0] spec_insn_lb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lb insn_lb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lb_valid),\n    .spec_trap(spec_insn_lb_trap),\n    .spec_rs1_addr(spec_insn_lb_rs1_addr),\n    .spec_rs2_addr(spec_insn_lb_rs2_addr),\n    .spec_rd_addr(spec_insn_lb_rd_addr),\n    .spec_rd_wdata(spec_insn_lb_rd_wdata),\n    .spec_pc_wdata(spec_insn_lb_pc_wdata),\n    .spec_mem_addr(spec_insn_lb_mem_addr),\n    .spec_mem_rmask(spec_insn_lb_mem_rmask),\n    .spec_mem_wmask(spec_insn_lb_mem_wmask),\n    .spec_mem_wdata(spec_insn_lb_mem_wdata)\n  );\n\n  wire                                spec_insn_lbu_valid;\n  wire                                spec_insn_lbu_trap;\n  wire [                       4 : 0] spec_insn_lbu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lbu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lbu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lbu insn_lbu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lbu_valid),\n    .spec_trap(spec_insn_lbu_trap),\n    .spec_rs1_addr(spec_insn_lbu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lbu_rs2_addr),\n    .spec_rd_addr(spec_insn_lbu_rd_addr),\n    .spec_rd_wdata(spec_insn_lbu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lbu_pc_wdata),\n    .spec_mem_addr(spec_insn_lbu_mem_addr),\n    .spec_mem_rmask(spec_insn_lbu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lbu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lbu_mem_wdata)\n  );\n\n  wire                                spec_insn_lh_valid;\n  wire                                spec_insn_lh_trap;\n  wire [                       4 : 0] spec_insn_lh_rs1_addr;\n  wire [                       4 : 0] spec_insn_lh_rs2_addr;\n  wire [                       4 : 0] spec_insn_lh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lh insn_lh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lh_valid),\n    .spec_trap(spec_insn_lh_trap),\n    .spec_rs1_addr(spec_insn_lh_rs1_addr),\n    .spec_rs2_addr(spec_insn_lh_rs2_addr),\n    .spec_rd_addr(spec_insn_lh_rd_addr),\n    .spec_rd_wdata(spec_insn_lh_rd_wdata),\n    .spec_pc_wdata(spec_insn_lh_pc_wdata),\n    .spec_mem_addr(spec_insn_lh_mem_addr),\n    .spec_mem_rmask(spec_insn_lh_mem_rmask),\n    .spec_mem_wmask(spec_insn_lh_mem_wmask),\n    .spec_mem_wdata(spec_insn_lh_mem_wdata)\n  );\n\n  wire                                spec_insn_lhu_valid;\n  wire                                spec_insn_lhu_trap;\n  wire [                       4 : 0] spec_insn_lhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lhu insn_lhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lhu_valid),\n    .spec_trap(spec_insn_lhu_trap),\n    .spec_rs1_addr(spec_insn_lhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lhu_rs2_addr),\n    .spec_rd_addr(spec_insn_lhu_rd_addr),\n    .spec_rd_wdata(spec_insn_lhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lhu_pc_wdata),\n    .spec_mem_addr(spec_insn_lhu_mem_addr),\n    .spec_mem_rmask(spec_insn_lhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lhu_mem_wdata)\n  );\n\n  wire                                spec_insn_lui_valid;\n  wire                                spec_insn_lui_trap;\n  wire [                       4 : 0] spec_insn_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lui insn_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lui_valid),\n    .spec_trap(spec_insn_lui_trap),\n    .spec_rs1_addr(spec_insn_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_lw_valid;\n  wire                                spec_insn_lw_trap;\n  wire [                       4 : 0] spec_insn_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lw insn_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lw_valid),\n    .spec_trap(spec_insn_lw_trap),\n    .spec_rs1_addr(spec_insn_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_mul_valid;\n  wire                                spec_insn_mul_trap;\n  wire [                       4 : 0] spec_insn_mul_rs1_addr;\n  wire [                       4 : 0] spec_insn_mul_rs2_addr;\n  wire [                       4 : 0] spec_insn_mul_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mul insn_mul (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mul_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mul_valid),\n    .spec_trap(spec_insn_mul_trap),\n    .spec_rs1_addr(spec_insn_mul_rs1_addr),\n    .spec_rs2_addr(spec_insn_mul_rs2_addr),\n    .spec_rd_addr(spec_insn_mul_rd_addr),\n    .spec_rd_wdata(spec_insn_mul_rd_wdata),\n    .spec_pc_wdata(spec_insn_mul_pc_wdata),\n    .spec_mem_addr(spec_insn_mul_mem_addr),\n    .spec_mem_rmask(spec_insn_mul_mem_rmask),\n    .spec_mem_wmask(spec_insn_mul_mem_wmask),\n    .spec_mem_wdata(spec_insn_mul_mem_wdata)\n  );\n\n  wire                                spec_insn_mulh_valid;\n  wire                                spec_insn_mulh_trap;\n  wire [                       4 : 0] spec_insn_mulh_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulh_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulh insn_mulh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulh_valid),\n    .spec_trap(spec_insn_mulh_trap),\n    .spec_rs1_addr(spec_insn_mulh_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulh_rs2_addr),\n    .spec_rd_addr(spec_insn_mulh_rd_addr),\n    .spec_rd_wdata(spec_insn_mulh_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulh_pc_wdata),\n    .spec_mem_addr(spec_insn_mulh_mem_addr),\n    .spec_mem_rmask(spec_insn_mulh_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulh_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulh_mem_wdata)\n  );\n\n  wire                                spec_insn_mulhsu_valid;\n  wire                                spec_insn_mulhsu_trap;\n  wire [                       4 : 0] spec_insn_mulhsu_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulhsu_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulhsu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulhsu insn_mulhsu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulhsu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulhsu_valid),\n    .spec_trap(spec_insn_mulhsu_trap),\n    .spec_rs1_addr(spec_insn_mulhsu_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulhsu_rs2_addr),\n    .spec_rd_addr(spec_insn_mulhsu_rd_addr),\n    .spec_rd_wdata(spec_insn_mulhsu_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulhsu_pc_wdata),\n    .spec_mem_addr(spec_insn_mulhsu_mem_addr),\n    .spec_mem_rmask(spec_insn_mulhsu_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulhsu_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulhsu_mem_wdata)\n  );\n\n  wire                                spec_insn_mulhu_valid;\n  wire                                spec_insn_mulhu_trap;\n  wire [                       4 : 0] spec_insn_mulhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulhu insn_mulhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulhu_valid),\n    .spec_trap(spec_insn_mulhu_trap),\n    .spec_rs1_addr(spec_insn_mulhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulhu_rs2_addr),\n    .spec_rd_addr(spec_insn_mulhu_rd_addr),\n    .spec_rd_wdata(spec_insn_mulhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulhu_pc_wdata),\n    .spec_mem_addr(spec_insn_mulhu_mem_addr),\n    .spec_mem_rmask(spec_insn_mulhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulhu_mem_wdata)\n  );\n\n  wire                                spec_insn_or_valid;\n  wire                                spec_insn_or_trap;\n  wire [                       4 : 0] spec_insn_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_or insn_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_or_valid),\n    .spec_trap(spec_insn_or_trap),\n    .spec_rs1_addr(spec_insn_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_or_rs2_addr),\n    .spec_rd_addr(spec_insn_or_rd_addr),\n    .spec_rd_wdata(spec_insn_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_or_pc_wdata),\n    .spec_mem_addr(spec_insn_or_mem_addr),\n    .spec_mem_rmask(spec_insn_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_or_mem_wdata)\n  );\n\n  wire                                spec_insn_ori_valid;\n  wire                                spec_insn_ori_trap;\n  wire [                       4 : 0] spec_insn_ori_rs1_addr;\n  wire [                       4 : 0] spec_insn_ori_rs2_addr;\n  wire [                       4 : 0] spec_insn_ori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ori insn_ori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ori_valid),\n    .spec_trap(spec_insn_ori_trap),\n    .spec_rs1_addr(spec_insn_ori_rs1_addr),\n    .spec_rs2_addr(spec_insn_ori_rs2_addr),\n    .spec_rd_addr(spec_insn_ori_rd_addr),\n    .spec_rd_wdata(spec_insn_ori_rd_wdata),\n    .spec_pc_wdata(spec_insn_ori_pc_wdata),\n    .spec_mem_addr(spec_insn_ori_mem_addr),\n    .spec_mem_rmask(spec_insn_ori_mem_rmask),\n    .spec_mem_wmask(spec_insn_ori_mem_wmask),\n    .spec_mem_wdata(spec_insn_ori_mem_wdata)\n  );\n\n  wire                                spec_insn_rem_valid;\n  wire                                spec_insn_rem_trap;\n  wire [                       4 : 0] spec_insn_rem_rs1_addr;\n  wire [                       4 : 0] spec_insn_rem_rs2_addr;\n  wire [                       4 : 0] spec_insn_rem_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_csr_misa_rmask;\n`endif\n\n  rvfi_insn_rem insn_rem (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_rem_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_rem_valid),\n    .spec_trap(spec_insn_rem_trap),\n    .spec_rs1_addr(spec_insn_rem_rs1_addr),\n    .spec_rs2_addr(spec_insn_rem_rs2_addr),\n    .spec_rd_addr(spec_insn_rem_rd_addr),\n    .spec_rd_wdata(spec_insn_rem_rd_wdata),\n    .spec_pc_wdata(spec_insn_rem_pc_wdata),\n    .spec_mem_addr(spec_insn_rem_mem_addr),\n    .spec_mem_rmask(spec_insn_rem_mem_rmask),\n    .spec_mem_wmask(spec_insn_rem_mem_wmask),\n    .spec_mem_wdata(spec_insn_rem_mem_wdata)\n  );\n\n  wire                                spec_insn_remu_valid;\n  wire                                spec_insn_remu_trap;\n  wire [                       4 : 0] spec_insn_remu_rs1_addr;\n  wire [                       4 : 0] spec_insn_remu_rs2_addr;\n  wire [                       4 : 0] spec_insn_remu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_remu insn_remu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_remu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_remu_valid),\n    .spec_trap(spec_insn_remu_trap),\n    .spec_rs1_addr(spec_insn_remu_rs1_addr),\n    .spec_rs2_addr(spec_insn_remu_rs2_addr),\n    .spec_rd_addr(spec_insn_remu_rd_addr),\n    .spec_rd_wdata(spec_insn_remu_rd_wdata),\n    .spec_pc_wdata(spec_insn_remu_pc_wdata),\n    .spec_mem_addr(spec_insn_remu_mem_addr),\n    .spec_mem_rmask(spec_insn_remu_mem_rmask),\n    .spec_mem_wmask(spec_insn_remu_mem_wmask),\n    .spec_mem_wdata(spec_insn_remu_mem_wdata)\n  );\n\n  wire                                spec_insn_sb_valid;\n  wire                                spec_insn_sb_trap;\n  wire [                       4 : 0] spec_insn_sb_rs1_addr;\n  wire [                       4 : 0] spec_insn_sb_rs2_addr;\n  wire [                       4 : 0] spec_insn_sb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sb insn_sb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sb_valid),\n    .spec_trap(spec_insn_sb_trap),\n    .spec_rs1_addr(spec_insn_sb_rs1_addr),\n    .spec_rs2_addr(spec_insn_sb_rs2_addr),\n    .spec_rd_addr(spec_insn_sb_rd_addr),\n    .spec_rd_wdata(spec_insn_sb_rd_wdata),\n    .spec_pc_wdata(spec_insn_sb_pc_wdata),\n    .spec_mem_addr(spec_insn_sb_mem_addr),\n    .spec_mem_rmask(spec_insn_sb_mem_rmask),\n    .spec_mem_wmask(spec_insn_sb_mem_wmask),\n    .spec_mem_wdata(spec_insn_sb_mem_wdata)\n  );\n\n  wire                                spec_insn_sh_valid;\n  wire                                spec_insn_sh_trap;\n  wire [                       4 : 0] spec_insn_sh_rs1_addr;\n  wire [                       4 : 0] spec_insn_sh_rs2_addr;\n  wire [                       4 : 0] spec_insn_sh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sh insn_sh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sh_valid),\n    .spec_trap(spec_insn_sh_trap),\n    .spec_rs1_addr(spec_insn_sh_rs1_addr),\n    .spec_rs2_addr(spec_insn_sh_rs2_addr),\n    .spec_rd_addr(spec_insn_sh_rd_addr),\n    .spec_rd_wdata(spec_insn_sh_rd_wdata),\n    .spec_pc_wdata(spec_insn_sh_pc_wdata),\n    .spec_mem_addr(spec_insn_sh_mem_addr),\n    .spec_mem_rmask(spec_insn_sh_mem_rmask),\n    .spec_mem_wmask(spec_insn_sh_mem_wmask),\n    .spec_mem_wdata(spec_insn_sh_mem_wdata)\n  );\n\n  wire                                spec_insn_sll_valid;\n  wire                                spec_insn_sll_trap;\n  wire [                       4 : 0] spec_insn_sll_rs1_addr;\n  wire [                       4 : 0] spec_insn_sll_rs2_addr;\n  wire [                       4 : 0] spec_insn_sll_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sll insn_sll (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sll_valid),\n    .spec_trap(spec_insn_sll_trap),\n    .spec_rs1_addr(spec_insn_sll_rs1_addr),\n    .spec_rs2_addr(spec_insn_sll_rs2_addr),\n    .spec_rd_addr(spec_insn_sll_rd_addr),\n    .spec_rd_wdata(spec_insn_sll_rd_wdata),\n    .spec_pc_wdata(spec_insn_sll_pc_wdata),\n    .spec_mem_addr(spec_insn_sll_mem_addr),\n    .spec_mem_rmask(spec_insn_sll_mem_rmask),\n    .spec_mem_wmask(spec_insn_sll_mem_wmask),\n    .spec_mem_wdata(spec_insn_sll_mem_wdata)\n  );\n\n  wire                                spec_insn_slli_valid;\n  wire                                spec_insn_slli_trap;\n  wire [                       4 : 0] spec_insn_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slli insn_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slli_valid),\n    .spec_trap(spec_insn_slli_trap),\n    .spec_rs1_addr(spec_insn_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_slt_valid;\n  wire                                spec_insn_slt_trap;\n  wire [                       4 : 0] spec_insn_slt_rs1_addr;\n  wire [                       4 : 0] spec_insn_slt_rs2_addr;\n  wire [                       4 : 0] spec_insn_slt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slt insn_slt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slt_valid),\n    .spec_trap(spec_insn_slt_trap),\n    .spec_rs1_addr(spec_insn_slt_rs1_addr),\n    .spec_rs2_addr(spec_insn_slt_rs2_addr),\n    .spec_rd_addr(spec_insn_slt_rd_addr),\n    .spec_rd_wdata(spec_insn_slt_rd_wdata),\n    .spec_pc_wdata(spec_insn_slt_pc_wdata),\n    .spec_mem_addr(spec_insn_slt_mem_addr),\n    .spec_mem_rmask(spec_insn_slt_mem_rmask),\n    .spec_mem_wmask(spec_insn_slt_mem_wmask),\n    .spec_mem_wdata(spec_insn_slt_mem_wdata)\n  );\n\n  wire                                spec_insn_slti_valid;\n  wire                                spec_insn_slti_trap;\n  wire [                       4 : 0] spec_insn_slti_rs1_addr;\n  wire [                       4 : 0] spec_insn_slti_rs2_addr;\n  wire [                       4 : 0] spec_insn_slti_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slti insn_slti (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slti_valid),\n    .spec_trap(spec_insn_slti_trap),\n    .spec_rs1_addr(spec_insn_slti_rs1_addr),\n    .spec_rs2_addr(spec_insn_slti_rs2_addr),\n    .spec_rd_addr(spec_insn_slti_rd_addr),\n    .spec_rd_wdata(spec_insn_slti_rd_wdata),\n    .spec_pc_wdata(spec_insn_slti_pc_wdata),\n    .spec_mem_addr(spec_insn_slti_mem_addr),\n    .spec_mem_rmask(spec_insn_slti_mem_rmask),\n    .spec_mem_wmask(spec_insn_slti_mem_wmask),\n    .spec_mem_wdata(spec_insn_slti_mem_wdata)\n  );\n\n  wire                                spec_insn_sltiu_valid;\n  wire                                spec_insn_sltiu_trap;\n  wire [                       4 : 0] spec_insn_sltiu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltiu insn_sltiu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltiu_valid),\n    .spec_trap(spec_insn_sltiu_trap),\n    .spec_rs1_addr(spec_insn_sltiu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltiu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltiu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltiu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltiu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltiu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltiu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltiu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltiu_mem_wdata)\n  );\n\n  wire                                spec_insn_sltu_valid;\n  wire                                spec_insn_sltu_trap;\n  wire [                       4 : 0] spec_insn_sltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltu insn_sltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltu_valid),\n    .spec_trap(spec_insn_sltu_trap),\n    .spec_rs1_addr(spec_insn_sltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltu_mem_wdata)\n  );\n\n  wire                                spec_insn_sra_valid;\n  wire                                spec_insn_sra_trap;\n  wire [                       4 : 0] spec_insn_sra_rs1_addr;\n  wire [                       4 : 0] spec_insn_sra_rs2_addr;\n  wire [                       4 : 0] spec_insn_sra_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sra insn_sra (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sra_valid),\n    .spec_trap(spec_insn_sra_trap),\n    .spec_rs1_addr(spec_insn_sra_rs1_addr),\n    .spec_rs2_addr(spec_insn_sra_rs2_addr),\n    .spec_rd_addr(spec_insn_sra_rd_addr),\n    .spec_rd_wdata(spec_insn_sra_rd_wdata),\n    .spec_pc_wdata(spec_insn_sra_pc_wdata),\n    .spec_mem_addr(spec_insn_sra_mem_addr),\n    .spec_mem_rmask(spec_insn_sra_mem_rmask),\n    .spec_mem_wmask(spec_insn_sra_mem_wmask),\n    .spec_mem_wdata(spec_insn_sra_mem_wdata)\n  );\n\n  wire                                spec_insn_srai_valid;\n  wire                                spec_insn_srai_trap;\n  wire [                       4 : 0] spec_insn_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srai insn_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srai_valid),\n    .spec_trap(spec_insn_srai_trap),\n    .spec_rs1_addr(spec_insn_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_srl_valid;\n  wire                                spec_insn_srl_trap;\n  wire [                       4 : 0] spec_insn_srl_rs1_addr;\n  wire [                       4 : 0] spec_insn_srl_rs2_addr;\n  wire [                       4 : 0] spec_insn_srl_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srl insn_srl (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srl_valid),\n    .spec_trap(spec_insn_srl_trap),\n    .spec_rs1_addr(spec_insn_srl_rs1_addr),\n    .spec_rs2_addr(spec_insn_srl_rs2_addr),\n    .spec_rd_addr(spec_insn_srl_rd_addr),\n    .spec_rd_wdata(spec_insn_srl_rd_wdata),\n    .spec_pc_wdata(spec_insn_srl_pc_wdata),\n    .spec_mem_addr(spec_insn_srl_mem_addr),\n    .spec_mem_rmask(spec_insn_srl_mem_rmask),\n    .spec_mem_wmask(spec_insn_srl_mem_wmask),\n    .spec_mem_wdata(spec_insn_srl_mem_wdata)\n  );\n\n  wire                                spec_insn_srli_valid;\n  wire                                spec_insn_srli_trap;\n  wire [                       4 : 0] spec_insn_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srli insn_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srli_valid),\n    .spec_trap(spec_insn_srli_trap),\n    .spec_rs1_addr(spec_insn_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_sub_valid;\n  wire                                spec_insn_sub_trap;\n  wire [                       4 : 0] spec_insn_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sub insn_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sub_valid),\n    .spec_trap(spec_insn_sub_trap),\n    .spec_rs1_addr(spec_insn_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_sw_valid;\n  wire                                spec_insn_sw_trap;\n  wire [                       4 : 0] spec_insn_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sw insn_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sw_valid),\n    .spec_trap(spec_insn_sw_trap),\n    .spec_rs1_addr(spec_insn_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_xor_valid;\n  wire                                spec_insn_xor_trap;\n  wire [                       4 : 0] spec_insn_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xor insn_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xor_valid),\n    .spec_trap(spec_insn_xor_trap),\n    .spec_rs1_addr(spec_insn_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_xori_valid;\n  wire                                spec_insn_xori_trap;\n  wire [                       4 : 0] spec_insn_xori_rs1_addr;\n  wire [                       4 : 0] spec_insn_xori_rs2_addr;\n  wire [                       4 : 0] spec_insn_xori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xori insn_xori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xori_valid),\n    .spec_trap(spec_insn_xori_trap),\n    .spec_rs1_addr(spec_insn_xori_rs1_addr),\n    .spec_rs2_addr(spec_insn_xori_rs2_addr),\n    .spec_rd_addr(spec_insn_xori_rd_addr),\n    .spec_rd_wdata(spec_insn_xori_rd_wdata),\n    .spec_pc_wdata(spec_insn_xori_pc_wdata),\n    .spec_mem_addr(spec_insn_xori_mem_addr),\n    .spec_mem_rmask(spec_insn_xori_mem_rmask),\n    .spec_mem_wmask(spec_insn_xori_mem_wmask),\n    .spec_mem_wdata(spec_insn_xori_mem_wdata)\n  );\n\n  assign spec_valid =\n\t\tspec_insn_add_valid ? spec_insn_add_valid :\n\t\tspec_insn_addi_valid ? spec_insn_addi_valid :\n\t\tspec_insn_and_valid ? spec_insn_and_valid :\n\t\tspec_insn_andi_valid ? spec_insn_andi_valid :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_valid :\n\t\tspec_insn_beq_valid ? spec_insn_beq_valid :\n\t\tspec_insn_bge_valid ? spec_insn_bge_valid :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_valid :\n\t\tspec_insn_blt_valid ? spec_insn_blt_valid :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_valid :\n\t\tspec_insn_bne_valid ? spec_insn_bne_valid :\n\t\tspec_insn_div_valid ? spec_insn_div_valid :\n\t\tspec_insn_divu_valid ? spec_insn_divu_valid :\n\t\tspec_insn_jal_valid ? spec_insn_jal_valid :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_valid :\n\t\tspec_insn_lb_valid ? spec_insn_lb_valid :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_valid :\n\t\tspec_insn_lh_valid ? spec_insn_lh_valid :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_valid :\n\t\tspec_insn_lui_valid ? spec_insn_lui_valid :\n\t\tspec_insn_lw_valid ? spec_insn_lw_valid :\n\t\tspec_insn_mul_valid ? spec_insn_mul_valid :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_valid :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_valid :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_valid :\n\t\tspec_insn_or_valid ? spec_insn_or_valid :\n\t\tspec_insn_ori_valid ? spec_insn_ori_valid :\n\t\tspec_insn_rem_valid ? spec_insn_rem_valid :\n\t\tspec_insn_remu_valid ? spec_insn_remu_valid :\n\t\tspec_insn_sb_valid ? spec_insn_sb_valid :\n\t\tspec_insn_sh_valid ? spec_insn_sh_valid :\n\t\tspec_insn_sll_valid ? spec_insn_sll_valid :\n\t\tspec_insn_slli_valid ? spec_insn_slli_valid :\n\t\tspec_insn_slt_valid ? spec_insn_slt_valid :\n\t\tspec_insn_slti_valid ? spec_insn_slti_valid :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_valid :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_valid :\n\t\tspec_insn_sra_valid ? spec_insn_sra_valid :\n\t\tspec_insn_srai_valid ? spec_insn_srai_valid :\n\t\tspec_insn_srl_valid ? spec_insn_srl_valid :\n\t\tspec_insn_srli_valid ? spec_insn_srli_valid :\n\t\tspec_insn_sub_valid ? spec_insn_sub_valid :\n\t\tspec_insn_sw_valid ? spec_insn_sw_valid :\n\t\tspec_insn_xor_valid ? spec_insn_xor_valid :\n\t\tspec_insn_xori_valid ? spec_insn_xori_valid : 0;\n  assign spec_trap =\n\t\tspec_insn_add_valid ? spec_insn_add_trap :\n\t\tspec_insn_addi_valid ? spec_insn_addi_trap :\n\t\tspec_insn_and_valid ? spec_insn_and_trap :\n\t\tspec_insn_andi_valid ? spec_insn_andi_trap :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_trap :\n\t\tspec_insn_beq_valid ? spec_insn_beq_trap :\n\t\tspec_insn_bge_valid ? spec_insn_bge_trap :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_trap :\n\t\tspec_insn_blt_valid ? spec_insn_blt_trap :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_trap :\n\t\tspec_insn_bne_valid ? spec_insn_bne_trap :\n\t\tspec_insn_div_valid ? spec_insn_div_trap :\n\t\tspec_insn_divu_valid ? spec_insn_divu_trap :\n\t\tspec_insn_jal_valid ? spec_insn_jal_trap :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_trap :\n\t\tspec_insn_lb_valid ? spec_insn_lb_trap :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_trap :\n\t\tspec_insn_lh_valid ? spec_insn_lh_trap :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_trap :\n\t\tspec_insn_lui_valid ? spec_insn_lui_trap :\n\t\tspec_insn_lw_valid ? spec_insn_lw_trap :\n\t\tspec_insn_mul_valid ? spec_insn_mul_trap :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_trap :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_trap :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_trap :\n\t\tspec_insn_or_valid ? spec_insn_or_trap :\n\t\tspec_insn_ori_valid ? spec_insn_ori_trap :\n\t\tspec_insn_rem_valid ? spec_insn_rem_trap :\n\t\tspec_insn_remu_valid ? spec_insn_remu_trap :\n\t\tspec_insn_sb_valid ? spec_insn_sb_trap :\n\t\tspec_insn_sh_valid ? spec_insn_sh_trap :\n\t\tspec_insn_sll_valid ? spec_insn_sll_trap :\n\t\tspec_insn_slli_valid ? spec_insn_slli_trap :\n\t\tspec_insn_slt_valid ? spec_insn_slt_trap :\n\t\tspec_insn_slti_valid ? spec_insn_slti_trap :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_trap :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_trap :\n\t\tspec_insn_sra_valid ? spec_insn_sra_trap :\n\t\tspec_insn_srai_valid ? spec_insn_srai_trap :\n\t\tspec_insn_srl_valid ? spec_insn_srl_trap :\n\t\tspec_insn_srli_valid ? spec_insn_srli_trap :\n\t\tspec_insn_sub_valid ? spec_insn_sub_trap :\n\t\tspec_insn_sw_valid ? spec_insn_sw_trap :\n\t\tspec_insn_xor_valid ? spec_insn_xor_trap :\n\t\tspec_insn_xori_valid ? spec_insn_xori_trap : 0;\n  assign spec_rs1_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs1_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs1_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs1_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs1_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs1_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs1_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs1_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs1_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs1_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs1_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rs1_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rs1_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs1_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs1_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs1_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs1_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs1_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs1_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs1_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs1_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rs1_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rs1_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rs1_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rs1_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs1_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs1_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rs1_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rs1_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs1_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs1_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs1_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs1_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs1_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs1_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs1_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs1_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs1_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs1_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs1_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs1_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs1_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs1_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0;\n  assign spec_rs2_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs2_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs2_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs2_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs2_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs2_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs2_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs2_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs2_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs2_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs2_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rs2_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rs2_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs2_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs2_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs2_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs2_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs2_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs2_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs2_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs2_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rs2_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rs2_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rs2_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rs2_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs2_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs2_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rs2_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rs2_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs2_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs2_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs2_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs2_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs2_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs2_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs2_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs2_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs2_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs2_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs2_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs2_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs2_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs2_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0;\n  assign spec_rd_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rd_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rd_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rd_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rd_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rd_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rd_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rd_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_addr : 0;\n  assign spec_rd_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_rd_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rd_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rd_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rd_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rd_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rd_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rd_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0;\n  assign spec_pc_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_pc_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_pc_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_pc_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_pc_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_pc_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_pc_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_pc_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_pc_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_pc_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_pc_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_pc_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_pc_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_pc_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_pc_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_pc_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_pc_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_pc_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_pc_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_pc_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_pc_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_pc_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_pc_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_pc_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_pc_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_pc_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_pc_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_pc_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_pc_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_pc_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_pc_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_pc_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_pc_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_pc_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_pc_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_pc_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_pc_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_pc_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_pc_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_pc_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_pc_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_pc_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_pc_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0;\n  assign spec_mem_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_addr : 0;\n  assign spec_mem_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_rmask :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_rmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_rmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_rmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_rmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_rmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_rmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_rmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0;\n  assign spec_mem_wmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wmask :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_wmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_wmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_wmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_wmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_wmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_wmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_wmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0;\n  assign spec_mem_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0;\n`ifdef RISCV_FORMAL_CSR_MISA\n  assign spec_csr_misa_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_csr_misa_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_csr_misa_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask :\n\t\tspec_insn_div_valid ? spec_insn_div_csr_misa_rmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_csr_misa_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_csr_misa_rmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_csr_misa_rmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_csr_misa_rmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_csr_misa_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_csr_misa_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_csr_misa_rmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_csr_misa_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0;\n`endif\nendmodule\n"
  },
  {
    "path": "insns/isa_rv32imc.txt",
    "content": "add\naddi\nand\nandi\nauipc\nbeq\nbge\nbgeu\nblt\nbltu\nbne\nc_add\nc_addi\nc_addi16sp\nc_addi4spn\nc_and\nc_andi\nc_beqz\nc_bnez\nc_j\nc_jal\nc_jalr\nc_jr\nc_li\nc_lui\nc_lw\nc_lwsp\nc_mv\nc_or\nc_slli\nc_srai\nc_srli\nc_sub\nc_sw\nc_swsp\nc_xor\ndiv\ndivu\njal\njalr\nlb\nlbu\nlh\nlhu\nlui\nlw\nmul\nmulh\nmulhsu\nmulhu\nor\nori\nrem\nremu\nsb\nsh\nsll\nslli\nslt\nslti\nsltiu\nsltu\nsra\nsrai\nsrl\nsrli\nsub\nsw\nxor\nxori\n"
  },
  {
    "path": "insns/isa_rv32imc.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_isa_rv32imc (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n  wire                                spec_insn_add_valid;\n  wire                                spec_insn_add_trap;\n  wire [                       4 : 0] spec_insn_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_add insn_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_add_valid),\n    .spec_trap(spec_insn_add_trap),\n    .spec_rs1_addr(spec_insn_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_add_rs2_addr),\n    .spec_rd_addr(spec_insn_add_rd_addr),\n    .spec_rd_wdata(spec_insn_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_add_pc_wdata),\n    .spec_mem_addr(spec_insn_add_mem_addr),\n    .spec_mem_rmask(spec_insn_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_add_mem_wdata)\n  );\n\n  wire                                spec_insn_addi_valid;\n  wire                                spec_insn_addi_trap;\n  wire [                       4 : 0] spec_insn_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addi insn_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addi_valid),\n    .spec_trap(spec_insn_addi_trap),\n    .spec_rs1_addr(spec_insn_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_and_valid;\n  wire                                spec_insn_and_trap;\n  wire [                       4 : 0] spec_insn_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_and insn_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_and_valid),\n    .spec_trap(spec_insn_and_trap),\n    .spec_rs1_addr(spec_insn_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_and_rs2_addr),\n    .spec_rd_addr(spec_insn_and_rd_addr),\n    .spec_rd_wdata(spec_insn_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_and_pc_wdata),\n    .spec_mem_addr(spec_insn_and_mem_addr),\n    .spec_mem_rmask(spec_insn_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_and_mem_wdata)\n  );\n\n  wire                                spec_insn_andi_valid;\n  wire                                spec_insn_andi_trap;\n  wire [                       4 : 0] spec_insn_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_andi insn_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_andi_valid),\n    .spec_trap(spec_insn_andi_trap),\n    .spec_rs1_addr(spec_insn_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_auipc_valid;\n  wire                                spec_insn_auipc_trap;\n  wire [                       4 : 0] spec_insn_auipc_rs1_addr;\n  wire [                       4 : 0] spec_insn_auipc_rs2_addr;\n  wire [                       4 : 0] spec_insn_auipc_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_csr_misa_rmask;\n`endif\n\n  rvfi_insn_auipc insn_auipc (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_auipc_valid),\n    .spec_trap(spec_insn_auipc_trap),\n    .spec_rs1_addr(spec_insn_auipc_rs1_addr),\n    .spec_rs2_addr(spec_insn_auipc_rs2_addr),\n    .spec_rd_addr(spec_insn_auipc_rd_addr),\n    .spec_rd_wdata(spec_insn_auipc_rd_wdata),\n    .spec_pc_wdata(spec_insn_auipc_pc_wdata),\n    .spec_mem_addr(spec_insn_auipc_mem_addr),\n    .spec_mem_rmask(spec_insn_auipc_mem_rmask),\n    .spec_mem_wmask(spec_insn_auipc_mem_wmask),\n    .spec_mem_wdata(spec_insn_auipc_mem_wdata)\n  );\n\n  wire                                spec_insn_beq_valid;\n  wire                                spec_insn_beq_trap;\n  wire [                       4 : 0] spec_insn_beq_rs1_addr;\n  wire [                       4 : 0] spec_insn_beq_rs2_addr;\n  wire [                       4 : 0] spec_insn_beq_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_csr_misa_rmask;\n`endif\n\n  rvfi_insn_beq insn_beq (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_beq_valid),\n    .spec_trap(spec_insn_beq_trap),\n    .spec_rs1_addr(spec_insn_beq_rs1_addr),\n    .spec_rs2_addr(spec_insn_beq_rs2_addr),\n    .spec_rd_addr(spec_insn_beq_rd_addr),\n    .spec_rd_wdata(spec_insn_beq_rd_wdata),\n    .spec_pc_wdata(spec_insn_beq_pc_wdata),\n    .spec_mem_addr(spec_insn_beq_mem_addr),\n    .spec_mem_rmask(spec_insn_beq_mem_rmask),\n    .spec_mem_wmask(spec_insn_beq_mem_wmask),\n    .spec_mem_wdata(spec_insn_beq_mem_wdata)\n  );\n\n  wire                                spec_insn_bge_valid;\n  wire                                spec_insn_bge_trap;\n  wire [                       4 : 0] spec_insn_bge_rs1_addr;\n  wire [                       4 : 0] spec_insn_bge_rs2_addr;\n  wire [                       4 : 0] spec_insn_bge_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bge insn_bge (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bge_valid),\n    .spec_trap(spec_insn_bge_trap),\n    .spec_rs1_addr(spec_insn_bge_rs1_addr),\n    .spec_rs2_addr(spec_insn_bge_rs2_addr),\n    .spec_rd_addr(spec_insn_bge_rd_addr),\n    .spec_rd_wdata(spec_insn_bge_rd_wdata),\n    .spec_pc_wdata(spec_insn_bge_pc_wdata),\n    .spec_mem_addr(spec_insn_bge_mem_addr),\n    .spec_mem_rmask(spec_insn_bge_mem_rmask),\n    .spec_mem_wmask(spec_insn_bge_mem_wmask),\n    .spec_mem_wdata(spec_insn_bge_mem_wdata)\n  );\n\n  wire                                spec_insn_bgeu_valid;\n  wire                                spec_insn_bgeu_trap;\n  wire [                       4 : 0] spec_insn_bgeu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bgeu insn_bgeu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bgeu_valid),\n    .spec_trap(spec_insn_bgeu_trap),\n    .spec_rs1_addr(spec_insn_bgeu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bgeu_rs2_addr),\n    .spec_rd_addr(spec_insn_bgeu_rd_addr),\n    .spec_rd_wdata(spec_insn_bgeu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bgeu_pc_wdata),\n    .spec_mem_addr(spec_insn_bgeu_mem_addr),\n    .spec_mem_rmask(spec_insn_bgeu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bgeu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bgeu_mem_wdata)\n  );\n\n  wire                                spec_insn_blt_valid;\n  wire                                spec_insn_blt_trap;\n  wire [                       4 : 0] spec_insn_blt_rs1_addr;\n  wire [                       4 : 0] spec_insn_blt_rs2_addr;\n  wire [                       4 : 0] spec_insn_blt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_blt insn_blt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_blt_valid),\n    .spec_trap(spec_insn_blt_trap),\n    .spec_rs1_addr(spec_insn_blt_rs1_addr),\n    .spec_rs2_addr(spec_insn_blt_rs2_addr),\n    .spec_rd_addr(spec_insn_blt_rd_addr),\n    .spec_rd_wdata(spec_insn_blt_rd_wdata),\n    .spec_pc_wdata(spec_insn_blt_pc_wdata),\n    .spec_mem_addr(spec_insn_blt_mem_addr),\n    .spec_mem_rmask(spec_insn_blt_mem_rmask),\n    .spec_mem_wmask(spec_insn_blt_mem_wmask),\n    .spec_mem_wdata(spec_insn_blt_mem_wdata)\n  );\n\n  wire                                spec_insn_bltu_valid;\n  wire                                spec_insn_bltu_trap;\n  wire [                       4 : 0] spec_insn_bltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bltu insn_bltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bltu_valid),\n    .spec_trap(spec_insn_bltu_trap),\n    .spec_rs1_addr(spec_insn_bltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bltu_rs2_addr),\n    .spec_rd_addr(spec_insn_bltu_rd_addr),\n    .spec_rd_wdata(spec_insn_bltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bltu_pc_wdata),\n    .spec_mem_addr(spec_insn_bltu_mem_addr),\n    .spec_mem_rmask(spec_insn_bltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bltu_mem_wdata)\n  );\n\n  wire                                spec_insn_bne_valid;\n  wire                                spec_insn_bne_trap;\n  wire [                       4 : 0] spec_insn_bne_rs1_addr;\n  wire [                       4 : 0] spec_insn_bne_rs2_addr;\n  wire [                       4 : 0] spec_insn_bne_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bne insn_bne (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bne_valid),\n    .spec_trap(spec_insn_bne_trap),\n    .spec_rs1_addr(spec_insn_bne_rs1_addr),\n    .spec_rs2_addr(spec_insn_bne_rs2_addr),\n    .spec_rd_addr(spec_insn_bne_rd_addr),\n    .spec_rd_wdata(spec_insn_bne_rd_wdata),\n    .spec_pc_wdata(spec_insn_bne_pc_wdata),\n    .spec_mem_addr(spec_insn_bne_mem_addr),\n    .spec_mem_rmask(spec_insn_bne_mem_rmask),\n    .spec_mem_wmask(spec_insn_bne_mem_wmask),\n    .spec_mem_wdata(spec_insn_bne_mem_wdata)\n  );\n\n  wire                                spec_insn_c_add_valid;\n  wire                                spec_insn_c_add_trap;\n  wire [                       4 : 0] spec_insn_c_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_add insn_c_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_add_valid),\n    .spec_trap(spec_insn_c_add_trap),\n    .spec_rs1_addr(spec_insn_c_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_add_rs2_addr),\n    .spec_rd_addr(spec_insn_c_add_rd_addr),\n    .spec_rd_wdata(spec_insn_c_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_add_pc_wdata),\n    .spec_mem_addr(spec_insn_c_add_mem_addr),\n    .spec_mem_rmask(spec_insn_c_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_add_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi_valid;\n  wire                                spec_insn_c_addi_trap;\n  wire [                       4 : 0] spec_insn_c_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi insn_c_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi_valid),\n    .spec_trap(spec_insn_c_addi_trap),\n    .spec_rs1_addr(spec_insn_c_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi16sp_valid;\n  wire                                spec_insn_c_addi16sp_trap;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi16sp insn_c_addi16sp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi16sp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi16sp_valid),\n    .spec_trap(spec_insn_c_addi16sp_trap),\n    .spec_rs1_addr(spec_insn_c_addi16sp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi16sp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi16sp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi16sp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi16sp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi16sp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi16sp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi16sp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi16sp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi4spn_valid;\n  wire                                spec_insn_c_addi4spn_trap;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi4spn insn_c_addi4spn (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi4spn_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi4spn_valid),\n    .spec_trap(spec_insn_c_addi4spn_trap),\n    .spec_rs1_addr(spec_insn_c_addi4spn_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi4spn_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi4spn_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi4spn_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi4spn_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi4spn_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi4spn_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi4spn_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi4spn_mem_wdata)\n  );\n\n  wire                                spec_insn_c_and_valid;\n  wire                                spec_insn_c_and_trap;\n  wire [                       4 : 0] spec_insn_c_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_and insn_c_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_and_valid),\n    .spec_trap(spec_insn_c_and_trap),\n    .spec_rs1_addr(spec_insn_c_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_and_rs2_addr),\n    .spec_rd_addr(spec_insn_c_and_rd_addr),\n    .spec_rd_wdata(spec_insn_c_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_and_pc_wdata),\n    .spec_mem_addr(spec_insn_c_and_mem_addr),\n    .spec_mem_rmask(spec_insn_c_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_and_mem_wdata)\n  );\n\n  wire                                spec_insn_c_andi_valid;\n  wire                                spec_insn_c_andi_trap;\n  wire [                       4 : 0] spec_insn_c_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_andi insn_c_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_andi_valid),\n    .spec_trap(spec_insn_c_andi_trap),\n    .spec_rs1_addr(spec_insn_c_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_c_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_c_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_c_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_c_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_c_beqz_valid;\n  wire                                spec_insn_c_beqz_trap;\n  wire [                       4 : 0] spec_insn_c_beqz_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_beqz_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_beqz_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_beqz insn_c_beqz (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_beqz_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_beqz_valid),\n    .spec_trap(spec_insn_c_beqz_trap),\n    .spec_rs1_addr(spec_insn_c_beqz_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_beqz_rs2_addr),\n    .spec_rd_addr(spec_insn_c_beqz_rd_addr),\n    .spec_rd_wdata(spec_insn_c_beqz_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_beqz_pc_wdata),\n    .spec_mem_addr(spec_insn_c_beqz_mem_addr),\n    .spec_mem_rmask(spec_insn_c_beqz_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_beqz_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_beqz_mem_wdata)\n  );\n\n  wire                                spec_insn_c_bnez_valid;\n  wire                                spec_insn_c_bnez_trap;\n  wire [                       4 : 0] spec_insn_c_bnez_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_bnez_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_bnez_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_bnez insn_c_bnez (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_bnez_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_bnez_valid),\n    .spec_trap(spec_insn_c_bnez_trap),\n    .spec_rs1_addr(spec_insn_c_bnez_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_bnez_rs2_addr),\n    .spec_rd_addr(spec_insn_c_bnez_rd_addr),\n    .spec_rd_wdata(spec_insn_c_bnez_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_bnez_pc_wdata),\n    .spec_mem_addr(spec_insn_c_bnez_mem_addr),\n    .spec_mem_rmask(spec_insn_c_bnez_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_bnez_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_bnez_mem_wdata)\n  );\n\n  wire                                spec_insn_c_j_valid;\n  wire                                spec_insn_c_j_trap;\n  wire [                       4 : 0] spec_insn_c_j_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_j_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_j_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_j insn_c_j (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_j_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_j_valid),\n    .spec_trap(spec_insn_c_j_trap),\n    .spec_rs1_addr(spec_insn_c_j_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_j_rs2_addr),\n    .spec_rd_addr(spec_insn_c_j_rd_addr),\n    .spec_rd_wdata(spec_insn_c_j_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_j_pc_wdata),\n    .spec_mem_addr(spec_insn_c_j_mem_addr),\n    .spec_mem_rmask(spec_insn_c_j_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_j_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_j_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jal_valid;\n  wire                                spec_insn_c_jal_trap;\n  wire [                       4 : 0] spec_insn_c_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jal insn_c_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jal_valid),\n    .spec_trap(spec_insn_c_jal_trap),\n    .spec_rs1_addr(spec_insn_c_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jalr_valid;\n  wire                                spec_insn_c_jalr_trap;\n  wire [                       4 : 0] spec_insn_c_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jalr insn_c_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jalr_valid),\n    .spec_trap(spec_insn_c_jalr_trap),\n    .spec_rs1_addr(spec_insn_c_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jr_valid;\n  wire                                spec_insn_c_jr_trap;\n  wire [                       4 : 0] spec_insn_c_jr_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jr_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jr insn_c_jr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jr_valid),\n    .spec_trap(spec_insn_c_jr_trap),\n    .spec_rs1_addr(spec_insn_c_jr_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jr_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jr_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jr_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jr_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jr_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jr_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jr_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jr_mem_wdata)\n  );\n\n  wire                                spec_insn_c_li_valid;\n  wire                                spec_insn_c_li_trap;\n  wire [                       4 : 0] spec_insn_c_li_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_li_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_li_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_li insn_c_li (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_li_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_li_valid),\n    .spec_trap(spec_insn_c_li_trap),\n    .spec_rs1_addr(spec_insn_c_li_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_li_rs2_addr),\n    .spec_rd_addr(spec_insn_c_li_rd_addr),\n    .spec_rd_wdata(spec_insn_c_li_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_li_pc_wdata),\n    .spec_mem_addr(spec_insn_c_li_mem_addr),\n    .spec_mem_rmask(spec_insn_c_li_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_li_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_li_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lui_valid;\n  wire                                spec_insn_c_lui_trap;\n  wire [                       4 : 0] spec_insn_c_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lui insn_c_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lui_valid),\n    .spec_trap(spec_insn_c_lui_trap),\n    .spec_rs1_addr(spec_insn_c_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lw_valid;\n  wire                                spec_insn_c_lw_trap;\n  wire [                       4 : 0] spec_insn_c_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lw insn_c_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lw_valid),\n    .spec_trap(spec_insn_c_lw_trap),\n    .spec_rs1_addr(spec_insn_c_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lwsp_valid;\n  wire                                spec_insn_c_lwsp_trap;\n  wire [                       4 : 0] spec_insn_c_lwsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lwsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lwsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lwsp insn_c_lwsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lwsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lwsp_valid),\n    .spec_trap(spec_insn_c_lwsp_trap),\n    .spec_rs1_addr(spec_insn_c_lwsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lwsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lwsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lwsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lwsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lwsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lwsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lwsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lwsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_mv_valid;\n  wire                                spec_insn_c_mv_trap;\n  wire [                       4 : 0] spec_insn_c_mv_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_mv_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_mv_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_mv insn_c_mv (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_mv_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_mv_valid),\n    .spec_trap(spec_insn_c_mv_trap),\n    .spec_rs1_addr(spec_insn_c_mv_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_mv_rs2_addr),\n    .spec_rd_addr(spec_insn_c_mv_rd_addr),\n    .spec_rd_wdata(spec_insn_c_mv_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_mv_pc_wdata),\n    .spec_mem_addr(spec_insn_c_mv_mem_addr),\n    .spec_mem_rmask(spec_insn_c_mv_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_mv_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_mv_mem_wdata)\n  );\n\n  wire                                spec_insn_c_or_valid;\n  wire                                spec_insn_c_or_trap;\n  wire [                       4 : 0] spec_insn_c_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_or insn_c_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_or_valid),\n    .spec_trap(spec_insn_c_or_trap),\n    .spec_rs1_addr(spec_insn_c_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_or_rs2_addr),\n    .spec_rd_addr(spec_insn_c_or_rd_addr),\n    .spec_rd_wdata(spec_insn_c_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_or_pc_wdata),\n    .spec_mem_addr(spec_insn_c_or_mem_addr),\n    .spec_mem_rmask(spec_insn_c_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_or_mem_wdata)\n  );\n\n  wire                                spec_insn_c_slli_valid;\n  wire                                spec_insn_c_slli_trap;\n  wire [                       4 : 0] spec_insn_c_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_slli insn_c_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_slli_valid),\n    .spec_trap(spec_insn_c_slli_trap),\n    .spec_rs1_addr(spec_insn_c_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_c_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_c_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_c_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_c_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_c_srai_valid;\n  wire                                spec_insn_c_srai_trap;\n  wire [                       4 : 0] spec_insn_c_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_srai insn_c_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_srai_valid),\n    .spec_trap(spec_insn_c_srai_trap),\n    .spec_rs1_addr(spec_insn_c_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_c_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_c_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_c_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_c_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_c_srli_valid;\n  wire                                spec_insn_c_srli_trap;\n  wire [                       4 : 0] spec_insn_c_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_srli insn_c_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_srli_valid),\n    .spec_trap(spec_insn_c_srli_trap),\n    .spec_rs1_addr(spec_insn_c_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_c_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_c_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_c_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_c_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sub_valid;\n  wire                                spec_insn_c_sub_trap;\n  wire [                       4 : 0] spec_insn_c_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sub insn_c_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sub_valid),\n    .spec_trap(spec_insn_c_sub_trap),\n    .spec_rs1_addr(spec_insn_c_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sw_valid;\n  wire                                spec_insn_c_sw_trap;\n  wire [                       4 : 0] spec_insn_c_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sw insn_c_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sw_valid),\n    .spec_trap(spec_insn_c_sw_trap),\n    .spec_rs1_addr(spec_insn_c_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_swsp_valid;\n  wire                                spec_insn_c_swsp_trap;\n  wire [                       4 : 0] spec_insn_c_swsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_swsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_swsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_swsp insn_c_swsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_swsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_swsp_valid),\n    .spec_trap(spec_insn_c_swsp_trap),\n    .spec_rs1_addr(spec_insn_c_swsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_swsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_swsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_swsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_swsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_swsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_swsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_swsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_swsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_xor_valid;\n  wire                                spec_insn_c_xor_trap;\n  wire [                       4 : 0] spec_insn_c_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_xor insn_c_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_xor_valid),\n    .spec_trap(spec_insn_c_xor_trap),\n    .spec_rs1_addr(spec_insn_c_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_c_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_c_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_c_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_c_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_div_valid;\n  wire                                spec_insn_div_trap;\n  wire [                       4 : 0] spec_insn_div_rs1_addr;\n  wire [                       4 : 0] spec_insn_div_rs2_addr;\n  wire [                       4 : 0] spec_insn_div_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_csr_misa_rmask;\n`endif\n\n  rvfi_insn_div insn_div (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_div_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_div_valid),\n    .spec_trap(spec_insn_div_trap),\n    .spec_rs1_addr(spec_insn_div_rs1_addr),\n    .spec_rs2_addr(spec_insn_div_rs2_addr),\n    .spec_rd_addr(spec_insn_div_rd_addr),\n    .spec_rd_wdata(spec_insn_div_rd_wdata),\n    .spec_pc_wdata(spec_insn_div_pc_wdata),\n    .spec_mem_addr(spec_insn_div_mem_addr),\n    .spec_mem_rmask(spec_insn_div_mem_rmask),\n    .spec_mem_wmask(spec_insn_div_mem_wmask),\n    .spec_mem_wdata(spec_insn_div_mem_wdata)\n  );\n\n  wire                                spec_insn_divu_valid;\n  wire                                spec_insn_divu_trap;\n  wire [                       4 : 0] spec_insn_divu_rs1_addr;\n  wire [                       4 : 0] spec_insn_divu_rs2_addr;\n  wire [                       4 : 0] spec_insn_divu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_divu insn_divu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_divu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_divu_valid),\n    .spec_trap(spec_insn_divu_trap),\n    .spec_rs1_addr(spec_insn_divu_rs1_addr),\n    .spec_rs2_addr(spec_insn_divu_rs2_addr),\n    .spec_rd_addr(spec_insn_divu_rd_addr),\n    .spec_rd_wdata(spec_insn_divu_rd_wdata),\n    .spec_pc_wdata(spec_insn_divu_pc_wdata),\n    .spec_mem_addr(spec_insn_divu_mem_addr),\n    .spec_mem_rmask(spec_insn_divu_mem_rmask),\n    .spec_mem_wmask(spec_insn_divu_mem_wmask),\n    .spec_mem_wdata(spec_insn_divu_mem_wdata)\n  );\n\n  wire                                spec_insn_jal_valid;\n  wire                                spec_insn_jal_trap;\n  wire [                       4 : 0] spec_insn_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jal insn_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jal_valid),\n    .spec_trap(spec_insn_jal_trap),\n    .spec_rs1_addr(spec_insn_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_jalr_valid;\n  wire                                spec_insn_jalr_trap;\n  wire [                       4 : 0] spec_insn_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jalr insn_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jalr_valid),\n    .spec_trap(spec_insn_jalr_trap),\n    .spec_rs1_addr(spec_insn_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_lb_valid;\n  wire                                spec_insn_lb_trap;\n  wire [                       4 : 0] spec_insn_lb_rs1_addr;\n  wire [                       4 : 0] spec_insn_lb_rs2_addr;\n  wire [                       4 : 0] spec_insn_lb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lb insn_lb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lb_valid),\n    .spec_trap(spec_insn_lb_trap),\n    .spec_rs1_addr(spec_insn_lb_rs1_addr),\n    .spec_rs2_addr(spec_insn_lb_rs2_addr),\n    .spec_rd_addr(spec_insn_lb_rd_addr),\n    .spec_rd_wdata(spec_insn_lb_rd_wdata),\n    .spec_pc_wdata(spec_insn_lb_pc_wdata),\n    .spec_mem_addr(spec_insn_lb_mem_addr),\n    .spec_mem_rmask(spec_insn_lb_mem_rmask),\n    .spec_mem_wmask(spec_insn_lb_mem_wmask),\n    .spec_mem_wdata(spec_insn_lb_mem_wdata)\n  );\n\n  wire                                spec_insn_lbu_valid;\n  wire                                spec_insn_lbu_trap;\n  wire [                       4 : 0] spec_insn_lbu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lbu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lbu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lbu insn_lbu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lbu_valid),\n    .spec_trap(spec_insn_lbu_trap),\n    .spec_rs1_addr(spec_insn_lbu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lbu_rs2_addr),\n    .spec_rd_addr(spec_insn_lbu_rd_addr),\n    .spec_rd_wdata(spec_insn_lbu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lbu_pc_wdata),\n    .spec_mem_addr(spec_insn_lbu_mem_addr),\n    .spec_mem_rmask(spec_insn_lbu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lbu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lbu_mem_wdata)\n  );\n\n  wire                                spec_insn_lh_valid;\n  wire                                spec_insn_lh_trap;\n  wire [                       4 : 0] spec_insn_lh_rs1_addr;\n  wire [                       4 : 0] spec_insn_lh_rs2_addr;\n  wire [                       4 : 0] spec_insn_lh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lh insn_lh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lh_valid),\n    .spec_trap(spec_insn_lh_trap),\n    .spec_rs1_addr(spec_insn_lh_rs1_addr),\n    .spec_rs2_addr(spec_insn_lh_rs2_addr),\n    .spec_rd_addr(spec_insn_lh_rd_addr),\n    .spec_rd_wdata(spec_insn_lh_rd_wdata),\n    .spec_pc_wdata(spec_insn_lh_pc_wdata),\n    .spec_mem_addr(spec_insn_lh_mem_addr),\n    .spec_mem_rmask(spec_insn_lh_mem_rmask),\n    .spec_mem_wmask(spec_insn_lh_mem_wmask),\n    .spec_mem_wdata(spec_insn_lh_mem_wdata)\n  );\n\n  wire                                spec_insn_lhu_valid;\n  wire                                spec_insn_lhu_trap;\n  wire [                       4 : 0] spec_insn_lhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lhu insn_lhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lhu_valid),\n    .spec_trap(spec_insn_lhu_trap),\n    .spec_rs1_addr(spec_insn_lhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lhu_rs2_addr),\n    .spec_rd_addr(spec_insn_lhu_rd_addr),\n    .spec_rd_wdata(spec_insn_lhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lhu_pc_wdata),\n    .spec_mem_addr(spec_insn_lhu_mem_addr),\n    .spec_mem_rmask(spec_insn_lhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lhu_mem_wdata)\n  );\n\n  wire                                spec_insn_lui_valid;\n  wire                                spec_insn_lui_trap;\n  wire [                       4 : 0] spec_insn_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lui insn_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lui_valid),\n    .spec_trap(spec_insn_lui_trap),\n    .spec_rs1_addr(spec_insn_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_lw_valid;\n  wire                                spec_insn_lw_trap;\n  wire [                       4 : 0] spec_insn_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lw insn_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lw_valid),\n    .spec_trap(spec_insn_lw_trap),\n    .spec_rs1_addr(spec_insn_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_mul_valid;\n  wire                                spec_insn_mul_trap;\n  wire [                       4 : 0] spec_insn_mul_rs1_addr;\n  wire [                       4 : 0] spec_insn_mul_rs2_addr;\n  wire [                       4 : 0] spec_insn_mul_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mul insn_mul (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mul_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mul_valid),\n    .spec_trap(spec_insn_mul_trap),\n    .spec_rs1_addr(spec_insn_mul_rs1_addr),\n    .spec_rs2_addr(spec_insn_mul_rs2_addr),\n    .spec_rd_addr(spec_insn_mul_rd_addr),\n    .spec_rd_wdata(spec_insn_mul_rd_wdata),\n    .spec_pc_wdata(spec_insn_mul_pc_wdata),\n    .spec_mem_addr(spec_insn_mul_mem_addr),\n    .spec_mem_rmask(spec_insn_mul_mem_rmask),\n    .spec_mem_wmask(spec_insn_mul_mem_wmask),\n    .spec_mem_wdata(spec_insn_mul_mem_wdata)\n  );\n\n  wire                                spec_insn_mulh_valid;\n  wire                                spec_insn_mulh_trap;\n  wire [                       4 : 0] spec_insn_mulh_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulh_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulh insn_mulh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulh_valid),\n    .spec_trap(spec_insn_mulh_trap),\n    .spec_rs1_addr(spec_insn_mulh_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulh_rs2_addr),\n    .spec_rd_addr(spec_insn_mulh_rd_addr),\n    .spec_rd_wdata(spec_insn_mulh_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulh_pc_wdata),\n    .spec_mem_addr(spec_insn_mulh_mem_addr),\n    .spec_mem_rmask(spec_insn_mulh_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulh_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulh_mem_wdata)\n  );\n\n  wire                                spec_insn_mulhsu_valid;\n  wire                                spec_insn_mulhsu_trap;\n  wire [                       4 : 0] spec_insn_mulhsu_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulhsu_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulhsu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulhsu insn_mulhsu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulhsu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulhsu_valid),\n    .spec_trap(spec_insn_mulhsu_trap),\n    .spec_rs1_addr(spec_insn_mulhsu_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulhsu_rs2_addr),\n    .spec_rd_addr(spec_insn_mulhsu_rd_addr),\n    .spec_rd_wdata(spec_insn_mulhsu_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulhsu_pc_wdata),\n    .spec_mem_addr(spec_insn_mulhsu_mem_addr),\n    .spec_mem_rmask(spec_insn_mulhsu_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulhsu_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulhsu_mem_wdata)\n  );\n\n  wire                                spec_insn_mulhu_valid;\n  wire                                spec_insn_mulhu_trap;\n  wire [                       4 : 0] spec_insn_mulhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulhu insn_mulhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulhu_valid),\n    .spec_trap(spec_insn_mulhu_trap),\n    .spec_rs1_addr(spec_insn_mulhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulhu_rs2_addr),\n    .spec_rd_addr(spec_insn_mulhu_rd_addr),\n    .spec_rd_wdata(spec_insn_mulhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulhu_pc_wdata),\n    .spec_mem_addr(spec_insn_mulhu_mem_addr),\n    .spec_mem_rmask(spec_insn_mulhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulhu_mem_wdata)\n  );\n\n  wire                                spec_insn_or_valid;\n  wire                                spec_insn_or_trap;\n  wire [                       4 : 0] spec_insn_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_or insn_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_or_valid),\n    .spec_trap(spec_insn_or_trap),\n    .spec_rs1_addr(spec_insn_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_or_rs2_addr),\n    .spec_rd_addr(spec_insn_or_rd_addr),\n    .spec_rd_wdata(spec_insn_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_or_pc_wdata),\n    .spec_mem_addr(spec_insn_or_mem_addr),\n    .spec_mem_rmask(spec_insn_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_or_mem_wdata)\n  );\n\n  wire                                spec_insn_ori_valid;\n  wire                                spec_insn_ori_trap;\n  wire [                       4 : 0] spec_insn_ori_rs1_addr;\n  wire [                       4 : 0] spec_insn_ori_rs2_addr;\n  wire [                       4 : 0] spec_insn_ori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ori insn_ori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ori_valid),\n    .spec_trap(spec_insn_ori_trap),\n    .spec_rs1_addr(spec_insn_ori_rs1_addr),\n    .spec_rs2_addr(spec_insn_ori_rs2_addr),\n    .spec_rd_addr(spec_insn_ori_rd_addr),\n    .spec_rd_wdata(spec_insn_ori_rd_wdata),\n    .spec_pc_wdata(spec_insn_ori_pc_wdata),\n    .spec_mem_addr(spec_insn_ori_mem_addr),\n    .spec_mem_rmask(spec_insn_ori_mem_rmask),\n    .spec_mem_wmask(spec_insn_ori_mem_wmask),\n    .spec_mem_wdata(spec_insn_ori_mem_wdata)\n  );\n\n  wire                                spec_insn_rem_valid;\n  wire                                spec_insn_rem_trap;\n  wire [                       4 : 0] spec_insn_rem_rs1_addr;\n  wire [                       4 : 0] spec_insn_rem_rs2_addr;\n  wire [                       4 : 0] spec_insn_rem_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_csr_misa_rmask;\n`endif\n\n  rvfi_insn_rem insn_rem (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_rem_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_rem_valid),\n    .spec_trap(spec_insn_rem_trap),\n    .spec_rs1_addr(spec_insn_rem_rs1_addr),\n    .spec_rs2_addr(spec_insn_rem_rs2_addr),\n    .spec_rd_addr(spec_insn_rem_rd_addr),\n    .spec_rd_wdata(spec_insn_rem_rd_wdata),\n    .spec_pc_wdata(spec_insn_rem_pc_wdata),\n    .spec_mem_addr(spec_insn_rem_mem_addr),\n    .spec_mem_rmask(spec_insn_rem_mem_rmask),\n    .spec_mem_wmask(spec_insn_rem_mem_wmask),\n    .spec_mem_wdata(spec_insn_rem_mem_wdata)\n  );\n\n  wire                                spec_insn_remu_valid;\n  wire                                spec_insn_remu_trap;\n  wire [                       4 : 0] spec_insn_remu_rs1_addr;\n  wire [                       4 : 0] spec_insn_remu_rs2_addr;\n  wire [                       4 : 0] spec_insn_remu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_remu insn_remu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_remu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_remu_valid),\n    .spec_trap(spec_insn_remu_trap),\n    .spec_rs1_addr(spec_insn_remu_rs1_addr),\n    .spec_rs2_addr(spec_insn_remu_rs2_addr),\n    .spec_rd_addr(spec_insn_remu_rd_addr),\n    .spec_rd_wdata(spec_insn_remu_rd_wdata),\n    .spec_pc_wdata(spec_insn_remu_pc_wdata),\n    .spec_mem_addr(spec_insn_remu_mem_addr),\n    .spec_mem_rmask(spec_insn_remu_mem_rmask),\n    .spec_mem_wmask(spec_insn_remu_mem_wmask),\n    .spec_mem_wdata(spec_insn_remu_mem_wdata)\n  );\n\n  wire                                spec_insn_sb_valid;\n  wire                                spec_insn_sb_trap;\n  wire [                       4 : 0] spec_insn_sb_rs1_addr;\n  wire [                       4 : 0] spec_insn_sb_rs2_addr;\n  wire [                       4 : 0] spec_insn_sb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sb insn_sb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sb_valid),\n    .spec_trap(spec_insn_sb_trap),\n    .spec_rs1_addr(spec_insn_sb_rs1_addr),\n    .spec_rs2_addr(spec_insn_sb_rs2_addr),\n    .spec_rd_addr(spec_insn_sb_rd_addr),\n    .spec_rd_wdata(spec_insn_sb_rd_wdata),\n    .spec_pc_wdata(spec_insn_sb_pc_wdata),\n    .spec_mem_addr(spec_insn_sb_mem_addr),\n    .spec_mem_rmask(spec_insn_sb_mem_rmask),\n    .spec_mem_wmask(spec_insn_sb_mem_wmask),\n    .spec_mem_wdata(spec_insn_sb_mem_wdata)\n  );\n\n  wire                                spec_insn_sh_valid;\n  wire                                spec_insn_sh_trap;\n  wire [                       4 : 0] spec_insn_sh_rs1_addr;\n  wire [                       4 : 0] spec_insn_sh_rs2_addr;\n  wire [                       4 : 0] spec_insn_sh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sh insn_sh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sh_valid),\n    .spec_trap(spec_insn_sh_trap),\n    .spec_rs1_addr(spec_insn_sh_rs1_addr),\n    .spec_rs2_addr(spec_insn_sh_rs2_addr),\n    .spec_rd_addr(spec_insn_sh_rd_addr),\n    .spec_rd_wdata(spec_insn_sh_rd_wdata),\n    .spec_pc_wdata(spec_insn_sh_pc_wdata),\n    .spec_mem_addr(spec_insn_sh_mem_addr),\n    .spec_mem_rmask(spec_insn_sh_mem_rmask),\n    .spec_mem_wmask(spec_insn_sh_mem_wmask),\n    .spec_mem_wdata(spec_insn_sh_mem_wdata)\n  );\n\n  wire                                spec_insn_sll_valid;\n  wire                                spec_insn_sll_trap;\n  wire [                       4 : 0] spec_insn_sll_rs1_addr;\n  wire [                       4 : 0] spec_insn_sll_rs2_addr;\n  wire [                       4 : 0] spec_insn_sll_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sll insn_sll (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sll_valid),\n    .spec_trap(spec_insn_sll_trap),\n    .spec_rs1_addr(spec_insn_sll_rs1_addr),\n    .spec_rs2_addr(spec_insn_sll_rs2_addr),\n    .spec_rd_addr(spec_insn_sll_rd_addr),\n    .spec_rd_wdata(spec_insn_sll_rd_wdata),\n    .spec_pc_wdata(spec_insn_sll_pc_wdata),\n    .spec_mem_addr(spec_insn_sll_mem_addr),\n    .spec_mem_rmask(spec_insn_sll_mem_rmask),\n    .spec_mem_wmask(spec_insn_sll_mem_wmask),\n    .spec_mem_wdata(spec_insn_sll_mem_wdata)\n  );\n\n  wire                                spec_insn_slli_valid;\n  wire                                spec_insn_slli_trap;\n  wire [                       4 : 0] spec_insn_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slli insn_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slli_valid),\n    .spec_trap(spec_insn_slli_trap),\n    .spec_rs1_addr(spec_insn_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_slt_valid;\n  wire                                spec_insn_slt_trap;\n  wire [                       4 : 0] spec_insn_slt_rs1_addr;\n  wire [                       4 : 0] spec_insn_slt_rs2_addr;\n  wire [                       4 : 0] spec_insn_slt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slt insn_slt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slt_valid),\n    .spec_trap(spec_insn_slt_trap),\n    .spec_rs1_addr(spec_insn_slt_rs1_addr),\n    .spec_rs2_addr(spec_insn_slt_rs2_addr),\n    .spec_rd_addr(spec_insn_slt_rd_addr),\n    .spec_rd_wdata(spec_insn_slt_rd_wdata),\n    .spec_pc_wdata(spec_insn_slt_pc_wdata),\n    .spec_mem_addr(spec_insn_slt_mem_addr),\n    .spec_mem_rmask(spec_insn_slt_mem_rmask),\n    .spec_mem_wmask(spec_insn_slt_mem_wmask),\n    .spec_mem_wdata(spec_insn_slt_mem_wdata)\n  );\n\n  wire                                spec_insn_slti_valid;\n  wire                                spec_insn_slti_trap;\n  wire [                       4 : 0] spec_insn_slti_rs1_addr;\n  wire [                       4 : 0] spec_insn_slti_rs2_addr;\n  wire [                       4 : 0] spec_insn_slti_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slti insn_slti (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slti_valid),\n    .spec_trap(spec_insn_slti_trap),\n    .spec_rs1_addr(spec_insn_slti_rs1_addr),\n    .spec_rs2_addr(spec_insn_slti_rs2_addr),\n    .spec_rd_addr(spec_insn_slti_rd_addr),\n    .spec_rd_wdata(spec_insn_slti_rd_wdata),\n    .spec_pc_wdata(spec_insn_slti_pc_wdata),\n    .spec_mem_addr(spec_insn_slti_mem_addr),\n    .spec_mem_rmask(spec_insn_slti_mem_rmask),\n    .spec_mem_wmask(spec_insn_slti_mem_wmask),\n    .spec_mem_wdata(spec_insn_slti_mem_wdata)\n  );\n\n  wire                                spec_insn_sltiu_valid;\n  wire                                spec_insn_sltiu_trap;\n  wire [                       4 : 0] spec_insn_sltiu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltiu insn_sltiu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltiu_valid),\n    .spec_trap(spec_insn_sltiu_trap),\n    .spec_rs1_addr(spec_insn_sltiu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltiu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltiu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltiu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltiu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltiu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltiu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltiu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltiu_mem_wdata)\n  );\n\n  wire                                spec_insn_sltu_valid;\n  wire                                spec_insn_sltu_trap;\n  wire [                       4 : 0] spec_insn_sltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltu insn_sltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltu_valid),\n    .spec_trap(spec_insn_sltu_trap),\n    .spec_rs1_addr(spec_insn_sltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltu_mem_wdata)\n  );\n\n  wire                                spec_insn_sra_valid;\n  wire                                spec_insn_sra_trap;\n  wire [                       4 : 0] spec_insn_sra_rs1_addr;\n  wire [                       4 : 0] spec_insn_sra_rs2_addr;\n  wire [                       4 : 0] spec_insn_sra_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sra insn_sra (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sra_valid),\n    .spec_trap(spec_insn_sra_trap),\n    .spec_rs1_addr(spec_insn_sra_rs1_addr),\n    .spec_rs2_addr(spec_insn_sra_rs2_addr),\n    .spec_rd_addr(spec_insn_sra_rd_addr),\n    .spec_rd_wdata(spec_insn_sra_rd_wdata),\n    .spec_pc_wdata(spec_insn_sra_pc_wdata),\n    .spec_mem_addr(spec_insn_sra_mem_addr),\n    .spec_mem_rmask(spec_insn_sra_mem_rmask),\n    .spec_mem_wmask(spec_insn_sra_mem_wmask),\n    .spec_mem_wdata(spec_insn_sra_mem_wdata)\n  );\n\n  wire                                spec_insn_srai_valid;\n  wire                                spec_insn_srai_trap;\n  wire [                       4 : 0] spec_insn_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srai insn_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srai_valid),\n    .spec_trap(spec_insn_srai_trap),\n    .spec_rs1_addr(spec_insn_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_srl_valid;\n  wire                                spec_insn_srl_trap;\n  wire [                       4 : 0] spec_insn_srl_rs1_addr;\n  wire [                       4 : 0] spec_insn_srl_rs2_addr;\n  wire [                       4 : 0] spec_insn_srl_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srl insn_srl (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srl_valid),\n    .spec_trap(spec_insn_srl_trap),\n    .spec_rs1_addr(spec_insn_srl_rs1_addr),\n    .spec_rs2_addr(spec_insn_srl_rs2_addr),\n    .spec_rd_addr(spec_insn_srl_rd_addr),\n    .spec_rd_wdata(spec_insn_srl_rd_wdata),\n    .spec_pc_wdata(spec_insn_srl_pc_wdata),\n    .spec_mem_addr(spec_insn_srl_mem_addr),\n    .spec_mem_rmask(spec_insn_srl_mem_rmask),\n    .spec_mem_wmask(spec_insn_srl_mem_wmask),\n    .spec_mem_wdata(spec_insn_srl_mem_wdata)\n  );\n\n  wire                                spec_insn_srli_valid;\n  wire                                spec_insn_srli_trap;\n  wire [                       4 : 0] spec_insn_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srli insn_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srli_valid),\n    .spec_trap(spec_insn_srli_trap),\n    .spec_rs1_addr(spec_insn_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_sub_valid;\n  wire                                spec_insn_sub_trap;\n  wire [                       4 : 0] spec_insn_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sub insn_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sub_valid),\n    .spec_trap(spec_insn_sub_trap),\n    .spec_rs1_addr(spec_insn_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_sw_valid;\n  wire                                spec_insn_sw_trap;\n  wire [                       4 : 0] spec_insn_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sw insn_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sw_valid),\n    .spec_trap(spec_insn_sw_trap),\n    .spec_rs1_addr(spec_insn_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_xor_valid;\n  wire                                spec_insn_xor_trap;\n  wire [                       4 : 0] spec_insn_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xor insn_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xor_valid),\n    .spec_trap(spec_insn_xor_trap),\n    .spec_rs1_addr(spec_insn_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_xori_valid;\n  wire                                spec_insn_xori_trap;\n  wire [                       4 : 0] spec_insn_xori_rs1_addr;\n  wire [                       4 : 0] spec_insn_xori_rs2_addr;\n  wire [                       4 : 0] spec_insn_xori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xori insn_xori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xori_valid),\n    .spec_trap(spec_insn_xori_trap),\n    .spec_rs1_addr(spec_insn_xori_rs1_addr),\n    .spec_rs2_addr(spec_insn_xori_rs2_addr),\n    .spec_rd_addr(spec_insn_xori_rd_addr),\n    .spec_rd_wdata(spec_insn_xori_rd_wdata),\n    .spec_pc_wdata(spec_insn_xori_pc_wdata),\n    .spec_mem_addr(spec_insn_xori_mem_addr),\n    .spec_mem_rmask(spec_insn_xori_mem_rmask),\n    .spec_mem_wmask(spec_insn_xori_mem_wmask),\n    .spec_mem_wdata(spec_insn_xori_mem_wdata)\n  );\n\n  assign spec_valid =\n\t\tspec_insn_add_valid ? spec_insn_add_valid :\n\t\tspec_insn_addi_valid ? spec_insn_addi_valid :\n\t\tspec_insn_and_valid ? spec_insn_and_valid :\n\t\tspec_insn_andi_valid ? spec_insn_andi_valid :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_valid :\n\t\tspec_insn_beq_valid ? spec_insn_beq_valid :\n\t\tspec_insn_bge_valid ? spec_insn_bge_valid :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_valid :\n\t\tspec_insn_blt_valid ? spec_insn_blt_valid :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_valid :\n\t\tspec_insn_bne_valid ? spec_insn_bne_valid :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_valid :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_valid :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_valid :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_valid :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_valid :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_valid :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_valid :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_valid :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_valid :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_valid :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_valid :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_valid :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_valid :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_valid :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_valid :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_valid :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_valid :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_valid :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_valid :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_valid :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_valid :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_valid :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_valid :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_valid :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_valid :\n\t\tspec_insn_div_valid ? spec_insn_div_valid :\n\t\tspec_insn_divu_valid ? spec_insn_divu_valid :\n\t\tspec_insn_jal_valid ? spec_insn_jal_valid :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_valid :\n\t\tspec_insn_lb_valid ? spec_insn_lb_valid :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_valid :\n\t\tspec_insn_lh_valid ? spec_insn_lh_valid :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_valid :\n\t\tspec_insn_lui_valid ? spec_insn_lui_valid :\n\t\tspec_insn_lw_valid ? spec_insn_lw_valid :\n\t\tspec_insn_mul_valid ? spec_insn_mul_valid :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_valid :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_valid :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_valid :\n\t\tspec_insn_or_valid ? spec_insn_or_valid :\n\t\tspec_insn_ori_valid ? spec_insn_ori_valid :\n\t\tspec_insn_rem_valid ? spec_insn_rem_valid :\n\t\tspec_insn_remu_valid ? spec_insn_remu_valid :\n\t\tspec_insn_sb_valid ? spec_insn_sb_valid :\n\t\tspec_insn_sh_valid ? spec_insn_sh_valid :\n\t\tspec_insn_sll_valid ? spec_insn_sll_valid :\n\t\tspec_insn_slli_valid ? spec_insn_slli_valid :\n\t\tspec_insn_slt_valid ? spec_insn_slt_valid :\n\t\tspec_insn_slti_valid ? spec_insn_slti_valid :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_valid :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_valid :\n\t\tspec_insn_sra_valid ? spec_insn_sra_valid :\n\t\tspec_insn_srai_valid ? spec_insn_srai_valid :\n\t\tspec_insn_srl_valid ? spec_insn_srl_valid :\n\t\tspec_insn_srli_valid ? spec_insn_srli_valid :\n\t\tspec_insn_sub_valid ? spec_insn_sub_valid :\n\t\tspec_insn_sw_valid ? spec_insn_sw_valid :\n\t\tspec_insn_xor_valid ? spec_insn_xor_valid :\n\t\tspec_insn_xori_valid ? spec_insn_xori_valid : 0;\n  assign spec_trap =\n\t\tspec_insn_add_valid ? spec_insn_add_trap :\n\t\tspec_insn_addi_valid ? spec_insn_addi_trap :\n\t\tspec_insn_and_valid ? spec_insn_and_trap :\n\t\tspec_insn_andi_valid ? spec_insn_andi_trap :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_trap :\n\t\tspec_insn_beq_valid ? spec_insn_beq_trap :\n\t\tspec_insn_bge_valid ? spec_insn_bge_trap :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_trap :\n\t\tspec_insn_blt_valid ? spec_insn_blt_trap :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_trap :\n\t\tspec_insn_bne_valid ? spec_insn_bne_trap :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_trap :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_trap :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_trap :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_trap :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_trap :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_trap :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_trap :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_trap :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_trap :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_trap :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_trap :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_trap :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_trap :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_trap :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_trap :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_trap :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_trap :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_trap :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_trap :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_trap :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_trap :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_trap :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_trap :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_trap :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_trap :\n\t\tspec_insn_div_valid ? spec_insn_div_trap :\n\t\tspec_insn_divu_valid ? spec_insn_divu_trap :\n\t\tspec_insn_jal_valid ? spec_insn_jal_trap :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_trap :\n\t\tspec_insn_lb_valid ? spec_insn_lb_trap :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_trap :\n\t\tspec_insn_lh_valid ? spec_insn_lh_trap :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_trap :\n\t\tspec_insn_lui_valid ? spec_insn_lui_trap :\n\t\tspec_insn_lw_valid ? spec_insn_lw_trap :\n\t\tspec_insn_mul_valid ? spec_insn_mul_trap :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_trap :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_trap :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_trap :\n\t\tspec_insn_or_valid ? spec_insn_or_trap :\n\t\tspec_insn_ori_valid ? spec_insn_ori_trap :\n\t\tspec_insn_rem_valid ? spec_insn_rem_trap :\n\t\tspec_insn_remu_valid ? spec_insn_remu_trap :\n\t\tspec_insn_sb_valid ? spec_insn_sb_trap :\n\t\tspec_insn_sh_valid ? spec_insn_sh_trap :\n\t\tspec_insn_sll_valid ? spec_insn_sll_trap :\n\t\tspec_insn_slli_valid ? spec_insn_slli_trap :\n\t\tspec_insn_slt_valid ? spec_insn_slt_trap :\n\t\tspec_insn_slti_valid ? spec_insn_slti_trap :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_trap :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_trap :\n\t\tspec_insn_sra_valid ? spec_insn_sra_trap :\n\t\tspec_insn_srai_valid ? spec_insn_srai_trap :\n\t\tspec_insn_srl_valid ? spec_insn_srl_trap :\n\t\tspec_insn_srli_valid ? spec_insn_srli_trap :\n\t\tspec_insn_sub_valid ? spec_insn_sub_trap :\n\t\tspec_insn_sw_valid ? spec_insn_sw_trap :\n\t\tspec_insn_xor_valid ? spec_insn_xor_trap :\n\t\tspec_insn_xori_valid ? spec_insn_xori_trap : 0;\n  assign spec_rs1_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs1_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs1_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs1_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs1_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs1_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs1_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs1_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs1_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs1_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs1_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rs1_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rs1_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs1_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs1_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rs1_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rs1_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rs1_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rs1_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rs1_addr :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_rs1_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rs1_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rs1_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rs1_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rs1_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rs1_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs1_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rs1_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rs1_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rs1_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rs1_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rs1_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rs1_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rs1_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rs1_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rs1_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rs1_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rs1_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs1_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs1_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs1_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs1_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs1_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs1_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs1_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs1_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rs1_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rs1_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rs1_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rs1_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs1_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs1_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rs1_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rs1_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs1_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs1_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs1_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs1_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs1_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs1_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs1_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs1_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs1_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs1_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs1_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs1_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs1_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs1_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0;\n  assign spec_rs2_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs2_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs2_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs2_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs2_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs2_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs2_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs2_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs2_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs2_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs2_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rs2_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rs2_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs2_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs2_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rs2_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rs2_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rs2_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rs2_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rs2_addr :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_rs2_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rs2_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rs2_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rs2_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rs2_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rs2_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs2_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rs2_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rs2_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rs2_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rs2_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rs2_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rs2_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rs2_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rs2_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rs2_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rs2_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rs2_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs2_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs2_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs2_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs2_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs2_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs2_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs2_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs2_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rs2_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rs2_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rs2_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rs2_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs2_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs2_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rs2_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rs2_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs2_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs2_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs2_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs2_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs2_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs2_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs2_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs2_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs2_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs2_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs2_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs2_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs2_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs2_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0;\n  assign spec_rd_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rd_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rd_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rd_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rd_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rd_addr :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_rd_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rd_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rd_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rd_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rd_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rd_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rd_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rd_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rd_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rd_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rd_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rd_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rd_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rd_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rd_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rd_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rd_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rd_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rd_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rd_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_addr : 0;\n  assign spec_rd_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rd_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rd_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rd_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rd_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rd_wdata :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_rd_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rd_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rd_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rd_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rd_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rd_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rd_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rd_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rd_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rd_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rd_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rd_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rd_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_rd_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rd_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rd_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rd_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rd_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rd_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rd_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0;\n  assign spec_pc_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_pc_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_pc_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_pc_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_pc_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_pc_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_pc_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_pc_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_pc_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_pc_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_pc_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_pc_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_pc_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_pc_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_pc_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_pc_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_pc_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_pc_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_pc_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_pc_wdata :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_pc_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_pc_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_pc_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_pc_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_pc_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_pc_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_pc_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_pc_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_pc_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_pc_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_pc_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_pc_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_pc_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_pc_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_pc_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_pc_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_pc_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_pc_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_pc_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_pc_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_pc_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_pc_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_pc_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_pc_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_pc_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_pc_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_pc_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_pc_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_pc_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_pc_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_pc_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_pc_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_pc_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_pc_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_pc_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_pc_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_pc_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_pc_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_pc_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_pc_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_pc_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_pc_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_pc_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_pc_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_pc_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_pc_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_pc_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_pc_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0;\n  assign spec_mem_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_addr :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_mem_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_addr : 0;\n  assign spec_mem_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_rmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_rmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_rmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_rmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_rmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_rmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_rmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_rmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_rmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_rmask :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_mem_rmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_rmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_rmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_rmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_rmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_rmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_rmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_rmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_rmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_rmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_rmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_rmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_rmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_rmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_rmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_rmask :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_rmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_rmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_rmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_rmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_rmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_rmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_rmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0;\n  assign spec_mem_wmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_wmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_wmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_wmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_wmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_wmask :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_mem_wmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_wmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_wmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_wmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_wmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_wmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_wmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_wmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_wmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_wmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_wmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_wmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_wmask :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_wmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_wmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_wmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_wmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_wmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_wmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_wmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0;\n  assign spec_mem_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_wdata :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_mem_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0;\n`ifdef RISCV_FORMAL_CSR_MISA\n  assign spec_csr_misa_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_csr_misa_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_csr_misa_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_csr_misa_rmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_csr_misa_rmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_csr_misa_rmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_csr_misa_rmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_csr_misa_rmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_csr_misa_rmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_csr_misa_rmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_csr_misa_rmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_csr_misa_rmask :\n\t\tspec_insn_c_jal_valid ? spec_insn_c_jal_csr_misa_rmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_csr_misa_rmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_csr_misa_rmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_csr_misa_rmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_csr_misa_rmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_csr_misa_rmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_csr_misa_rmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_csr_misa_rmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_csr_misa_rmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_csr_misa_rmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_csr_misa_rmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_csr_misa_rmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_csr_misa_rmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_csr_misa_rmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_csr_misa_rmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_csr_misa_rmask :\n\t\tspec_insn_div_valid ? spec_insn_div_csr_misa_rmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_csr_misa_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_csr_misa_rmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_csr_misa_rmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_csr_misa_rmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_csr_misa_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_csr_misa_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_csr_misa_rmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_csr_misa_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0;\n`endif\nendmodule\n"
  },
  {
    "path": "insns/isa_rv64i.txt",
    "content": "add\naddi\naddiw\naddw\nand\nandi\nauipc\nbeq\nbge\nbgeu\nblt\nbltu\nbne\njal\njalr\nlb\nlbu\nld\nlh\nlhu\nlui\nlw\nlwu\nor\nori\nsb\nsd\nsh\nsll\nslli\nslliw\nsllw\nslt\nslti\nsltiu\nsltu\nsra\nsrai\nsraiw\nsraw\nsrl\nsrli\nsrliw\nsrlw\nsub\nsubw\nsw\nxor\nxori\n"
  },
  {
    "path": "insns/isa_rv64i.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_isa_rv64i (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n  wire                                spec_insn_add_valid;\n  wire                                spec_insn_add_trap;\n  wire [                       4 : 0] spec_insn_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_add insn_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_add_valid),\n    .spec_trap(spec_insn_add_trap),\n    .spec_rs1_addr(spec_insn_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_add_rs2_addr),\n    .spec_rd_addr(spec_insn_add_rd_addr),\n    .spec_rd_wdata(spec_insn_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_add_pc_wdata),\n    .spec_mem_addr(spec_insn_add_mem_addr),\n    .spec_mem_rmask(spec_insn_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_add_mem_wdata)\n  );\n\n  wire                                spec_insn_addi_valid;\n  wire                                spec_insn_addi_trap;\n  wire [                       4 : 0] spec_insn_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addi insn_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addi_valid),\n    .spec_trap(spec_insn_addi_trap),\n    .spec_rs1_addr(spec_insn_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_addiw_valid;\n  wire                                spec_insn_addiw_trap;\n  wire [                       4 : 0] spec_insn_addiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_addiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_addiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addiw insn_addiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addiw_valid),\n    .spec_trap(spec_insn_addiw_trap),\n    .spec_rs1_addr(spec_insn_addiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_addiw_rs2_addr),\n    .spec_rd_addr(spec_insn_addiw_rd_addr),\n    .spec_rd_wdata(spec_insn_addiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_addiw_pc_wdata),\n    .spec_mem_addr(spec_insn_addiw_mem_addr),\n    .spec_mem_rmask(spec_insn_addiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_addiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_addiw_mem_wdata)\n  );\n\n  wire                                spec_insn_addw_valid;\n  wire                                spec_insn_addw_trap;\n  wire [                       4 : 0] spec_insn_addw_rs1_addr;\n  wire [                       4 : 0] spec_insn_addw_rs2_addr;\n  wire [                       4 : 0] spec_insn_addw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addw insn_addw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addw_valid),\n    .spec_trap(spec_insn_addw_trap),\n    .spec_rs1_addr(spec_insn_addw_rs1_addr),\n    .spec_rs2_addr(spec_insn_addw_rs2_addr),\n    .spec_rd_addr(spec_insn_addw_rd_addr),\n    .spec_rd_wdata(spec_insn_addw_rd_wdata),\n    .spec_pc_wdata(spec_insn_addw_pc_wdata),\n    .spec_mem_addr(spec_insn_addw_mem_addr),\n    .spec_mem_rmask(spec_insn_addw_mem_rmask),\n    .spec_mem_wmask(spec_insn_addw_mem_wmask),\n    .spec_mem_wdata(spec_insn_addw_mem_wdata)\n  );\n\n  wire                                spec_insn_and_valid;\n  wire                                spec_insn_and_trap;\n  wire [                       4 : 0] spec_insn_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_and insn_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_and_valid),\n    .spec_trap(spec_insn_and_trap),\n    .spec_rs1_addr(spec_insn_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_and_rs2_addr),\n    .spec_rd_addr(spec_insn_and_rd_addr),\n    .spec_rd_wdata(spec_insn_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_and_pc_wdata),\n    .spec_mem_addr(spec_insn_and_mem_addr),\n    .spec_mem_rmask(spec_insn_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_and_mem_wdata)\n  );\n\n  wire                                spec_insn_andi_valid;\n  wire                                spec_insn_andi_trap;\n  wire [                       4 : 0] spec_insn_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_andi insn_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_andi_valid),\n    .spec_trap(spec_insn_andi_trap),\n    .spec_rs1_addr(spec_insn_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_auipc_valid;\n  wire                                spec_insn_auipc_trap;\n  wire [                       4 : 0] spec_insn_auipc_rs1_addr;\n  wire [                       4 : 0] spec_insn_auipc_rs2_addr;\n  wire [                       4 : 0] spec_insn_auipc_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_csr_misa_rmask;\n`endif\n\n  rvfi_insn_auipc insn_auipc (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_auipc_valid),\n    .spec_trap(spec_insn_auipc_trap),\n    .spec_rs1_addr(spec_insn_auipc_rs1_addr),\n    .spec_rs2_addr(spec_insn_auipc_rs2_addr),\n    .spec_rd_addr(spec_insn_auipc_rd_addr),\n    .spec_rd_wdata(spec_insn_auipc_rd_wdata),\n    .spec_pc_wdata(spec_insn_auipc_pc_wdata),\n    .spec_mem_addr(spec_insn_auipc_mem_addr),\n    .spec_mem_rmask(spec_insn_auipc_mem_rmask),\n    .spec_mem_wmask(spec_insn_auipc_mem_wmask),\n    .spec_mem_wdata(spec_insn_auipc_mem_wdata)\n  );\n\n  wire                                spec_insn_beq_valid;\n  wire                                spec_insn_beq_trap;\n  wire [                       4 : 0] spec_insn_beq_rs1_addr;\n  wire [                       4 : 0] spec_insn_beq_rs2_addr;\n  wire [                       4 : 0] spec_insn_beq_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_csr_misa_rmask;\n`endif\n\n  rvfi_insn_beq insn_beq (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_beq_valid),\n    .spec_trap(spec_insn_beq_trap),\n    .spec_rs1_addr(spec_insn_beq_rs1_addr),\n    .spec_rs2_addr(spec_insn_beq_rs2_addr),\n    .spec_rd_addr(spec_insn_beq_rd_addr),\n    .spec_rd_wdata(spec_insn_beq_rd_wdata),\n    .spec_pc_wdata(spec_insn_beq_pc_wdata),\n    .spec_mem_addr(spec_insn_beq_mem_addr),\n    .spec_mem_rmask(spec_insn_beq_mem_rmask),\n    .spec_mem_wmask(spec_insn_beq_mem_wmask),\n    .spec_mem_wdata(spec_insn_beq_mem_wdata)\n  );\n\n  wire                                spec_insn_bge_valid;\n  wire                                spec_insn_bge_trap;\n  wire [                       4 : 0] spec_insn_bge_rs1_addr;\n  wire [                       4 : 0] spec_insn_bge_rs2_addr;\n  wire [                       4 : 0] spec_insn_bge_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bge insn_bge (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bge_valid),\n    .spec_trap(spec_insn_bge_trap),\n    .spec_rs1_addr(spec_insn_bge_rs1_addr),\n    .spec_rs2_addr(spec_insn_bge_rs2_addr),\n    .spec_rd_addr(spec_insn_bge_rd_addr),\n    .spec_rd_wdata(spec_insn_bge_rd_wdata),\n    .spec_pc_wdata(spec_insn_bge_pc_wdata),\n    .spec_mem_addr(spec_insn_bge_mem_addr),\n    .spec_mem_rmask(spec_insn_bge_mem_rmask),\n    .spec_mem_wmask(spec_insn_bge_mem_wmask),\n    .spec_mem_wdata(spec_insn_bge_mem_wdata)\n  );\n\n  wire                                spec_insn_bgeu_valid;\n  wire                                spec_insn_bgeu_trap;\n  wire [                       4 : 0] spec_insn_bgeu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bgeu insn_bgeu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bgeu_valid),\n    .spec_trap(spec_insn_bgeu_trap),\n    .spec_rs1_addr(spec_insn_bgeu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bgeu_rs2_addr),\n    .spec_rd_addr(spec_insn_bgeu_rd_addr),\n    .spec_rd_wdata(spec_insn_bgeu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bgeu_pc_wdata),\n    .spec_mem_addr(spec_insn_bgeu_mem_addr),\n    .spec_mem_rmask(spec_insn_bgeu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bgeu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bgeu_mem_wdata)\n  );\n\n  wire                                spec_insn_blt_valid;\n  wire                                spec_insn_blt_trap;\n  wire [                       4 : 0] spec_insn_blt_rs1_addr;\n  wire [                       4 : 0] spec_insn_blt_rs2_addr;\n  wire [                       4 : 0] spec_insn_blt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_blt insn_blt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_blt_valid),\n    .spec_trap(spec_insn_blt_trap),\n    .spec_rs1_addr(spec_insn_blt_rs1_addr),\n    .spec_rs2_addr(spec_insn_blt_rs2_addr),\n    .spec_rd_addr(spec_insn_blt_rd_addr),\n    .spec_rd_wdata(spec_insn_blt_rd_wdata),\n    .spec_pc_wdata(spec_insn_blt_pc_wdata),\n    .spec_mem_addr(spec_insn_blt_mem_addr),\n    .spec_mem_rmask(spec_insn_blt_mem_rmask),\n    .spec_mem_wmask(spec_insn_blt_mem_wmask),\n    .spec_mem_wdata(spec_insn_blt_mem_wdata)\n  );\n\n  wire                                spec_insn_bltu_valid;\n  wire                                spec_insn_bltu_trap;\n  wire [                       4 : 0] spec_insn_bltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bltu insn_bltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bltu_valid),\n    .spec_trap(spec_insn_bltu_trap),\n    .spec_rs1_addr(spec_insn_bltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bltu_rs2_addr),\n    .spec_rd_addr(spec_insn_bltu_rd_addr),\n    .spec_rd_wdata(spec_insn_bltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bltu_pc_wdata),\n    .spec_mem_addr(spec_insn_bltu_mem_addr),\n    .spec_mem_rmask(spec_insn_bltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bltu_mem_wdata)\n  );\n\n  wire                                spec_insn_bne_valid;\n  wire                                spec_insn_bne_trap;\n  wire [                       4 : 0] spec_insn_bne_rs1_addr;\n  wire [                       4 : 0] spec_insn_bne_rs2_addr;\n  wire [                       4 : 0] spec_insn_bne_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bne insn_bne (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bne_valid),\n    .spec_trap(spec_insn_bne_trap),\n    .spec_rs1_addr(spec_insn_bne_rs1_addr),\n    .spec_rs2_addr(spec_insn_bne_rs2_addr),\n    .spec_rd_addr(spec_insn_bne_rd_addr),\n    .spec_rd_wdata(spec_insn_bne_rd_wdata),\n    .spec_pc_wdata(spec_insn_bne_pc_wdata),\n    .spec_mem_addr(spec_insn_bne_mem_addr),\n    .spec_mem_rmask(spec_insn_bne_mem_rmask),\n    .spec_mem_wmask(spec_insn_bne_mem_wmask),\n    .spec_mem_wdata(spec_insn_bne_mem_wdata)\n  );\n\n  wire                                spec_insn_jal_valid;\n  wire                                spec_insn_jal_trap;\n  wire [                       4 : 0] spec_insn_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jal insn_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jal_valid),\n    .spec_trap(spec_insn_jal_trap),\n    .spec_rs1_addr(spec_insn_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_jalr_valid;\n  wire                                spec_insn_jalr_trap;\n  wire [                       4 : 0] spec_insn_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jalr insn_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jalr_valid),\n    .spec_trap(spec_insn_jalr_trap),\n    .spec_rs1_addr(spec_insn_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_lb_valid;\n  wire                                spec_insn_lb_trap;\n  wire [                       4 : 0] spec_insn_lb_rs1_addr;\n  wire [                       4 : 0] spec_insn_lb_rs2_addr;\n  wire [                       4 : 0] spec_insn_lb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lb insn_lb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lb_valid),\n    .spec_trap(spec_insn_lb_trap),\n    .spec_rs1_addr(spec_insn_lb_rs1_addr),\n    .spec_rs2_addr(spec_insn_lb_rs2_addr),\n    .spec_rd_addr(spec_insn_lb_rd_addr),\n    .spec_rd_wdata(spec_insn_lb_rd_wdata),\n    .spec_pc_wdata(spec_insn_lb_pc_wdata),\n    .spec_mem_addr(spec_insn_lb_mem_addr),\n    .spec_mem_rmask(spec_insn_lb_mem_rmask),\n    .spec_mem_wmask(spec_insn_lb_mem_wmask),\n    .spec_mem_wdata(spec_insn_lb_mem_wdata)\n  );\n\n  wire                                spec_insn_lbu_valid;\n  wire                                spec_insn_lbu_trap;\n  wire [                       4 : 0] spec_insn_lbu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lbu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lbu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lbu insn_lbu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lbu_valid),\n    .spec_trap(spec_insn_lbu_trap),\n    .spec_rs1_addr(spec_insn_lbu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lbu_rs2_addr),\n    .spec_rd_addr(spec_insn_lbu_rd_addr),\n    .spec_rd_wdata(spec_insn_lbu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lbu_pc_wdata),\n    .spec_mem_addr(spec_insn_lbu_mem_addr),\n    .spec_mem_rmask(spec_insn_lbu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lbu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lbu_mem_wdata)\n  );\n\n  wire                                spec_insn_ld_valid;\n  wire                                spec_insn_ld_trap;\n  wire [                       4 : 0] spec_insn_ld_rs1_addr;\n  wire [                       4 : 0] spec_insn_ld_rs2_addr;\n  wire [                       4 : 0] spec_insn_ld_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ld insn_ld (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ld_valid),\n    .spec_trap(spec_insn_ld_trap),\n    .spec_rs1_addr(spec_insn_ld_rs1_addr),\n    .spec_rs2_addr(spec_insn_ld_rs2_addr),\n    .spec_rd_addr(spec_insn_ld_rd_addr),\n    .spec_rd_wdata(spec_insn_ld_rd_wdata),\n    .spec_pc_wdata(spec_insn_ld_pc_wdata),\n    .spec_mem_addr(spec_insn_ld_mem_addr),\n    .spec_mem_rmask(spec_insn_ld_mem_rmask),\n    .spec_mem_wmask(spec_insn_ld_mem_wmask),\n    .spec_mem_wdata(spec_insn_ld_mem_wdata)\n  );\n\n  wire                                spec_insn_lh_valid;\n  wire                                spec_insn_lh_trap;\n  wire [                       4 : 0] spec_insn_lh_rs1_addr;\n  wire [                       4 : 0] spec_insn_lh_rs2_addr;\n  wire [                       4 : 0] spec_insn_lh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lh insn_lh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lh_valid),\n    .spec_trap(spec_insn_lh_trap),\n    .spec_rs1_addr(spec_insn_lh_rs1_addr),\n    .spec_rs2_addr(spec_insn_lh_rs2_addr),\n    .spec_rd_addr(spec_insn_lh_rd_addr),\n    .spec_rd_wdata(spec_insn_lh_rd_wdata),\n    .spec_pc_wdata(spec_insn_lh_pc_wdata),\n    .spec_mem_addr(spec_insn_lh_mem_addr),\n    .spec_mem_rmask(spec_insn_lh_mem_rmask),\n    .spec_mem_wmask(spec_insn_lh_mem_wmask),\n    .spec_mem_wdata(spec_insn_lh_mem_wdata)\n  );\n\n  wire                                spec_insn_lhu_valid;\n  wire                                spec_insn_lhu_trap;\n  wire [                       4 : 0] spec_insn_lhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lhu insn_lhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lhu_valid),\n    .spec_trap(spec_insn_lhu_trap),\n    .spec_rs1_addr(spec_insn_lhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lhu_rs2_addr),\n    .spec_rd_addr(spec_insn_lhu_rd_addr),\n    .spec_rd_wdata(spec_insn_lhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lhu_pc_wdata),\n    .spec_mem_addr(spec_insn_lhu_mem_addr),\n    .spec_mem_rmask(spec_insn_lhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lhu_mem_wdata)\n  );\n\n  wire                                spec_insn_lui_valid;\n  wire                                spec_insn_lui_trap;\n  wire [                       4 : 0] spec_insn_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lui insn_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lui_valid),\n    .spec_trap(spec_insn_lui_trap),\n    .spec_rs1_addr(spec_insn_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_lw_valid;\n  wire                                spec_insn_lw_trap;\n  wire [                       4 : 0] spec_insn_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lw insn_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lw_valid),\n    .spec_trap(spec_insn_lw_trap),\n    .spec_rs1_addr(spec_insn_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_lwu_valid;\n  wire                                spec_insn_lwu_trap;\n  wire [                       4 : 0] spec_insn_lwu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lwu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lwu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lwu insn_lwu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lwu_valid),\n    .spec_trap(spec_insn_lwu_trap),\n    .spec_rs1_addr(spec_insn_lwu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lwu_rs2_addr),\n    .spec_rd_addr(spec_insn_lwu_rd_addr),\n    .spec_rd_wdata(spec_insn_lwu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lwu_pc_wdata),\n    .spec_mem_addr(spec_insn_lwu_mem_addr),\n    .spec_mem_rmask(spec_insn_lwu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lwu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lwu_mem_wdata)\n  );\n\n  wire                                spec_insn_or_valid;\n  wire                                spec_insn_or_trap;\n  wire [                       4 : 0] spec_insn_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_or insn_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_or_valid),\n    .spec_trap(spec_insn_or_trap),\n    .spec_rs1_addr(spec_insn_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_or_rs2_addr),\n    .spec_rd_addr(spec_insn_or_rd_addr),\n    .spec_rd_wdata(spec_insn_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_or_pc_wdata),\n    .spec_mem_addr(spec_insn_or_mem_addr),\n    .spec_mem_rmask(spec_insn_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_or_mem_wdata)\n  );\n\n  wire                                spec_insn_ori_valid;\n  wire                                spec_insn_ori_trap;\n  wire [                       4 : 0] spec_insn_ori_rs1_addr;\n  wire [                       4 : 0] spec_insn_ori_rs2_addr;\n  wire [                       4 : 0] spec_insn_ori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ori insn_ori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ori_valid),\n    .spec_trap(spec_insn_ori_trap),\n    .spec_rs1_addr(spec_insn_ori_rs1_addr),\n    .spec_rs2_addr(spec_insn_ori_rs2_addr),\n    .spec_rd_addr(spec_insn_ori_rd_addr),\n    .spec_rd_wdata(spec_insn_ori_rd_wdata),\n    .spec_pc_wdata(spec_insn_ori_pc_wdata),\n    .spec_mem_addr(spec_insn_ori_mem_addr),\n    .spec_mem_rmask(spec_insn_ori_mem_rmask),\n    .spec_mem_wmask(spec_insn_ori_mem_wmask),\n    .spec_mem_wdata(spec_insn_ori_mem_wdata)\n  );\n\n  wire                                spec_insn_sb_valid;\n  wire                                spec_insn_sb_trap;\n  wire [                       4 : 0] spec_insn_sb_rs1_addr;\n  wire [                       4 : 0] spec_insn_sb_rs2_addr;\n  wire [                       4 : 0] spec_insn_sb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sb insn_sb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sb_valid),\n    .spec_trap(spec_insn_sb_trap),\n    .spec_rs1_addr(spec_insn_sb_rs1_addr),\n    .spec_rs2_addr(spec_insn_sb_rs2_addr),\n    .spec_rd_addr(spec_insn_sb_rd_addr),\n    .spec_rd_wdata(spec_insn_sb_rd_wdata),\n    .spec_pc_wdata(spec_insn_sb_pc_wdata),\n    .spec_mem_addr(spec_insn_sb_mem_addr),\n    .spec_mem_rmask(spec_insn_sb_mem_rmask),\n    .spec_mem_wmask(spec_insn_sb_mem_wmask),\n    .spec_mem_wdata(spec_insn_sb_mem_wdata)\n  );\n\n  wire                                spec_insn_sd_valid;\n  wire                                spec_insn_sd_trap;\n  wire [                       4 : 0] spec_insn_sd_rs1_addr;\n  wire [                       4 : 0] spec_insn_sd_rs2_addr;\n  wire [                       4 : 0] spec_insn_sd_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sd insn_sd (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sd_valid),\n    .spec_trap(spec_insn_sd_trap),\n    .spec_rs1_addr(spec_insn_sd_rs1_addr),\n    .spec_rs2_addr(spec_insn_sd_rs2_addr),\n    .spec_rd_addr(spec_insn_sd_rd_addr),\n    .spec_rd_wdata(spec_insn_sd_rd_wdata),\n    .spec_pc_wdata(spec_insn_sd_pc_wdata),\n    .spec_mem_addr(spec_insn_sd_mem_addr),\n    .spec_mem_rmask(spec_insn_sd_mem_rmask),\n    .spec_mem_wmask(spec_insn_sd_mem_wmask),\n    .spec_mem_wdata(spec_insn_sd_mem_wdata)\n  );\n\n  wire                                spec_insn_sh_valid;\n  wire                                spec_insn_sh_trap;\n  wire [                       4 : 0] spec_insn_sh_rs1_addr;\n  wire [                       4 : 0] spec_insn_sh_rs2_addr;\n  wire [                       4 : 0] spec_insn_sh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sh insn_sh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sh_valid),\n    .spec_trap(spec_insn_sh_trap),\n    .spec_rs1_addr(spec_insn_sh_rs1_addr),\n    .spec_rs2_addr(spec_insn_sh_rs2_addr),\n    .spec_rd_addr(spec_insn_sh_rd_addr),\n    .spec_rd_wdata(spec_insn_sh_rd_wdata),\n    .spec_pc_wdata(spec_insn_sh_pc_wdata),\n    .spec_mem_addr(spec_insn_sh_mem_addr),\n    .spec_mem_rmask(spec_insn_sh_mem_rmask),\n    .spec_mem_wmask(spec_insn_sh_mem_wmask),\n    .spec_mem_wdata(spec_insn_sh_mem_wdata)\n  );\n\n  wire                                spec_insn_sll_valid;\n  wire                                spec_insn_sll_trap;\n  wire [                       4 : 0] spec_insn_sll_rs1_addr;\n  wire [                       4 : 0] spec_insn_sll_rs2_addr;\n  wire [                       4 : 0] spec_insn_sll_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sll insn_sll (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sll_valid),\n    .spec_trap(spec_insn_sll_trap),\n    .spec_rs1_addr(spec_insn_sll_rs1_addr),\n    .spec_rs2_addr(spec_insn_sll_rs2_addr),\n    .spec_rd_addr(spec_insn_sll_rd_addr),\n    .spec_rd_wdata(spec_insn_sll_rd_wdata),\n    .spec_pc_wdata(spec_insn_sll_pc_wdata),\n    .spec_mem_addr(spec_insn_sll_mem_addr),\n    .spec_mem_rmask(spec_insn_sll_mem_rmask),\n    .spec_mem_wmask(spec_insn_sll_mem_wmask),\n    .spec_mem_wdata(spec_insn_sll_mem_wdata)\n  );\n\n  wire                                spec_insn_slli_valid;\n  wire                                spec_insn_slli_trap;\n  wire [                       4 : 0] spec_insn_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slli insn_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slli_valid),\n    .spec_trap(spec_insn_slli_trap),\n    .spec_rs1_addr(spec_insn_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_slliw_valid;\n  wire                                spec_insn_slliw_trap;\n  wire [                       4 : 0] spec_insn_slliw_rs1_addr;\n  wire [                       4 : 0] spec_insn_slliw_rs2_addr;\n  wire [                       4 : 0] spec_insn_slliw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slliw insn_slliw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slliw_valid),\n    .spec_trap(spec_insn_slliw_trap),\n    .spec_rs1_addr(spec_insn_slliw_rs1_addr),\n    .spec_rs2_addr(spec_insn_slliw_rs2_addr),\n    .spec_rd_addr(spec_insn_slliw_rd_addr),\n    .spec_rd_wdata(spec_insn_slliw_rd_wdata),\n    .spec_pc_wdata(spec_insn_slliw_pc_wdata),\n    .spec_mem_addr(spec_insn_slliw_mem_addr),\n    .spec_mem_rmask(spec_insn_slliw_mem_rmask),\n    .spec_mem_wmask(spec_insn_slliw_mem_wmask),\n    .spec_mem_wdata(spec_insn_slliw_mem_wdata)\n  );\n\n  wire                                spec_insn_sllw_valid;\n  wire                                spec_insn_sllw_trap;\n  wire [                       4 : 0] spec_insn_sllw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sllw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sllw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sllw insn_sllw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sllw_valid),\n    .spec_trap(spec_insn_sllw_trap),\n    .spec_rs1_addr(spec_insn_sllw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sllw_rs2_addr),\n    .spec_rd_addr(spec_insn_sllw_rd_addr),\n    .spec_rd_wdata(spec_insn_sllw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sllw_pc_wdata),\n    .spec_mem_addr(spec_insn_sllw_mem_addr),\n    .spec_mem_rmask(spec_insn_sllw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sllw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sllw_mem_wdata)\n  );\n\n  wire                                spec_insn_slt_valid;\n  wire                                spec_insn_slt_trap;\n  wire [                       4 : 0] spec_insn_slt_rs1_addr;\n  wire [                       4 : 0] spec_insn_slt_rs2_addr;\n  wire [                       4 : 0] spec_insn_slt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slt insn_slt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slt_valid),\n    .spec_trap(spec_insn_slt_trap),\n    .spec_rs1_addr(spec_insn_slt_rs1_addr),\n    .spec_rs2_addr(spec_insn_slt_rs2_addr),\n    .spec_rd_addr(spec_insn_slt_rd_addr),\n    .spec_rd_wdata(spec_insn_slt_rd_wdata),\n    .spec_pc_wdata(spec_insn_slt_pc_wdata),\n    .spec_mem_addr(spec_insn_slt_mem_addr),\n    .spec_mem_rmask(spec_insn_slt_mem_rmask),\n    .spec_mem_wmask(spec_insn_slt_mem_wmask),\n    .spec_mem_wdata(spec_insn_slt_mem_wdata)\n  );\n\n  wire                                spec_insn_slti_valid;\n  wire                                spec_insn_slti_trap;\n  wire [                       4 : 0] spec_insn_slti_rs1_addr;\n  wire [                       4 : 0] spec_insn_slti_rs2_addr;\n  wire [                       4 : 0] spec_insn_slti_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slti insn_slti (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slti_valid),\n    .spec_trap(spec_insn_slti_trap),\n    .spec_rs1_addr(spec_insn_slti_rs1_addr),\n    .spec_rs2_addr(spec_insn_slti_rs2_addr),\n    .spec_rd_addr(spec_insn_slti_rd_addr),\n    .spec_rd_wdata(spec_insn_slti_rd_wdata),\n    .spec_pc_wdata(spec_insn_slti_pc_wdata),\n    .spec_mem_addr(spec_insn_slti_mem_addr),\n    .spec_mem_rmask(spec_insn_slti_mem_rmask),\n    .spec_mem_wmask(spec_insn_slti_mem_wmask),\n    .spec_mem_wdata(spec_insn_slti_mem_wdata)\n  );\n\n  wire                                spec_insn_sltiu_valid;\n  wire                                spec_insn_sltiu_trap;\n  wire [                       4 : 0] spec_insn_sltiu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltiu insn_sltiu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltiu_valid),\n    .spec_trap(spec_insn_sltiu_trap),\n    .spec_rs1_addr(spec_insn_sltiu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltiu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltiu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltiu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltiu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltiu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltiu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltiu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltiu_mem_wdata)\n  );\n\n  wire                                spec_insn_sltu_valid;\n  wire                                spec_insn_sltu_trap;\n  wire [                       4 : 0] spec_insn_sltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltu insn_sltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltu_valid),\n    .spec_trap(spec_insn_sltu_trap),\n    .spec_rs1_addr(spec_insn_sltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltu_mem_wdata)\n  );\n\n  wire                                spec_insn_sra_valid;\n  wire                                spec_insn_sra_trap;\n  wire [                       4 : 0] spec_insn_sra_rs1_addr;\n  wire [                       4 : 0] spec_insn_sra_rs2_addr;\n  wire [                       4 : 0] spec_insn_sra_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sra insn_sra (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sra_valid),\n    .spec_trap(spec_insn_sra_trap),\n    .spec_rs1_addr(spec_insn_sra_rs1_addr),\n    .spec_rs2_addr(spec_insn_sra_rs2_addr),\n    .spec_rd_addr(spec_insn_sra_rd_addr),\n    .spec_rd_wdata(spec_insn_sra_rd_wdata),\n    .spec_pc_wdata(spec_insn_sra_pc_wdata),\n    .spec_mem_addr(spec_insn_sra_mem_addr),\n    .spec_mem_rmask(spec_insn_sra_mem_rmask),\n    .spec_mem_wmask(spec_insn_sra_mem_wmask),\n    .spec_mem_wdata(spec_insn_sra_mem_wdata)\n  );\n\n  wire                                spec_insn_srai_valid;\n  wire                                spec_insn_srai_trap;\n  wire [                       4 : 0] spec_insn_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srai insn_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srai_valid),\n    .spec_trap(spec_insn_srai_trap),\n    .spec_rs1_addr(spec_insn_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_sraiw_valid;\n  wire                                spec_insn_sraiw_trap;\n  wire [                       4 : 0] spec_insn_sraiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sraiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sraiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sraiw insn_sraiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sraiw_valid),\n    .spec_trap(spec_insn_sraiw_trap),\n    .spec_rs1_addr(spec_insn_sraiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sraiw_rs2_addr),\n    .spec_rd_addr(spec_insn_sraiw_rd_addr),\n    .spec_rd_wdata(spec_insn_sraiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sraiw_pc_wdata),\n    .spec_mem_addr(spec_insn_sraiw_mem_addr),\n    .spec_mem_rmask(spec_insn_sraiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sraiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sraiw_mem_wdata)\n  );\n\n  wire                                spec_insn_sraw_valid;\n  wire                                spec_insn_sraw_trap;\n  wire [                       4 : 0] spec_insn_sraw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sraw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sraw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sraw insn_sraw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sraw_valid),\n    .spec_trap(spec_insn_sraw_trap),\n    .spec_rs1_addr(spec_insn_sraw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sraw_rs2_addr),\n    .spec_rd_addr(spec_insn_sraw_rd_addr),\n    .spec_rd_wdata(spec_insn_sraw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sraw_pc_wdata),\n    .spec_mem_addr(spec_insn_sraw_mem_addr),\n    .spec_mem_rmask(spec_insn_sraw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sraw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sraw_mem_wdata)\n  );\n\n  wire                                spec_insn_srl_valid;\n  wire                                spec_insn_srl_trap;\n  wire [                       4 : 0] spec_insn_srl_rs1_addr;\n  wire [                       4 : 0] spec_insn_srl_rs2_addr;\n  wire [                       4 : 0] spec_insn_srl_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srl insn_srl (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srl_valid),\n    .spec_trap(spec_insn_srl_trap),\n    .spec_rs1_addr(spec_insn_srl_rs1_addr),\n    .spec_rs2_addr(spec_insn_srl_rs2_addr),\n    .spec_rd_addr(spec_insn_srl_rd_addr),\n    .spec_rd_wdata(spec_insn_srl_rd_wdata),\n    .spec_pc_wdata(spec_insn_srl_pc_wdata),\n    .spec_mem_addr(spec_insn_srl_mem_addr),\n    .spec_mem_rmask(spec_insn_srl_mem_rmask),\n    .spec_mem_wmask(spec_insn_srl_mem_wmask),\n    .spec_mem_wdata(spec_insn_srl_mem_wdata)\n  );\n\n  wire                                spec_insn_srli_valid;\n  wire                                spec_insn_srli_trap;\n  wire [                       4 : 0] spec_insn_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srli insn_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srli_valid),\n    .spec_trap(spec_insn_srli_trap),\n    .spec_rs1_addr(spec_insn_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_srliw_valid;\n  wire                                spec_insn_srliw_trap;\n  wire [                       4 : 0] spec_insn_srliw_rs1_addr;\n  wire [                       4 : 0] spec_insn_srliw_rs2_addr;\n  wire [                       4 : 0] spec_insn_srliw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srliw insn_srliw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srliw_valid),\n    .spec_trap(spec_insn_srliw_trap),\n    .spec_rs1_addr(spec_insn_srliw_rs1_addr),\n    .spec_rs2_addr(spec_insn_srliw_rs2_addr),\n    .spec_rd_addr(spec_insn_srliw_rd_addr),\n    .spec_rd_wdata(spec_insn_srliw_rd_wdata),\n    .spec_pc_wdata(spec_insn_srliw_pc_wdata),\n    .spec_mem_addr(spec_insn_srliw_mem_addr),\n    .spec_mem_rmask(spec_insn_srliw_mem_rmask),\n    .spec_mem_wmask(spec_insn_srliw_mem_wmask),\n    .spec_mem_wdata(spec_insn_srliw_mem_wdata)\n  );\n\n  wire                                spec_insn_srlw_valid;\n  wire                                spec_insn_srlw_trap;\n  wire [                       4 : 0] spec_insn_srlw_rs1_addr;\n  wire [                       4 : 0] spec_insn_srlw_rs2_addr;\n  wire [                       4 : 0] spec_insn_srlw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srlw insn_srlw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srlw_valid),\n    .spec_trap(spec_insn_srlw_trap),\n    .spec_rs1_addr(spec_insn_srlw_rs1_addr),\n    .spec_rs2_addr(spec_insn_srlw_rs2_addr),\n    .spec_rd_addr(spec_insn_srlw_rd_addr),\n    .spec_rd_wdata(spec_insn_srlw_rd_wdata),\n    .spec_pc_wdata(spec_insn_srlw_pc_wdata),\n    .spec_mem_addr(spec_insn_srlw_mem_addr),\n    .spec_mem_rmask(spec_insn_srlw_mem_rmask),\n    .spec_mem_wmask(spec_insn_srlw_mem_wmask),\n    .spec_mem_wdata(spec_insn_srlw_mem_wdata)\n  );\n\n  wire                                spec_insn_sub_valid;\n  wire                                spec_insn_sub_trap;\n  wire [                       4 : 0] spec_insn_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sub insn_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sub_valid),\n    .spec_trap(spec_insn_sub_trap),\n    .spec_rs1_addr(spec_insn_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_subw_valid;\n  wire                                spec_insn_subw_trap;\n  wire [                       4 : 0] spec_insn_subw_rs1_addr;\n  wire [                       4 : 0] spec_insn_subw_rs2_addr;\n  wire [                       4 : 0] spec_insn_subw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_subw insn_subw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_subw_valid),\n    .spec_trap(spec_insn_subw_trap),\n    .spec_rs1_addr(spec_insn_subw_rs1_addr),\n    .spec_rs2_addr(spec_insn_subw_rs2_addr),\n    .spec_rd_addr(spec_insn_subw_rd_addr),\n    .spec_rd_wdata(spec_insn_subw_rd_wdata),\n    .spec_pc_wdata(spec_insn_subw_pc_wdata),\n    .spec_mem_addr(spec_insn_subw_mem_addr),\n    .spec_mem_rmask(spec_insn_subw_mem_rmask),\n    .spec_mem_wmask(spec_insn_subw_mem_wmask),\n    .spec_mem_wdata(spec_insn_subw_mem_wdata)\n  );\n\n  wire                                spec_insn_sw_valid;\n  wire                                spec_insn_sw_trap;\n  wire [                       4 : 0] spec_insn_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sw insn_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sw_valid),\n    .spec_trap(spec_insn_sw_trap),\n    .spec_rs1_addr(spec_insn_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_xor_valid;\n  wire                                spec_insn_xor_trap;\n  wire [                       4 : 0] spec_insn_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xor insn_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xor_valid),\n    .spec_trap(spec_insn_xor_trap),\n    .spec_rs1_addr(spec_insn_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_xori_valid;\n  wire                                spec_insn_xori_trap;\n  wire [                       4 : 0] spec_insn_xori_rs1_addr;\n  wire [                       4 : 0] spec_insn_xori_rs2_addr;\n  wire [                       4 : 0] spec_insn_xori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xori insn_xori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xori_valid),\n    .spec_trap(spec_insn_xori_trap),\n    .spec_rs1_addr(spec_insn_xori_rs1_addr),\n    .spec_rs2_addr(spec_insn_xori_rs2_addr),\n    .spec_rd_addr(spec_insn_xori_rd_addr),\n    .spec_rd_wdata(spec_insn_xori_rd_wdata),\n    .spec_pc_wdata(spec_insn_xori_pc_wdata),\n    .spec_mem_addr(spec_insn_xori_mem_addr),\n    .spec_mem_rmask(spec_insn_xori_mem_rmask),\n    .spec_mem_wmask(spec_insn_xori_mem_wmask),\n    .spec_mem_wdata(spec_insn_xori_mem_wdata)\n  );\n\n  assign spec_valid =\n\t\tspec_insn_add_valid ? spec_insn_add_valid :\n\t\tspec_insn_addi_valid ? spec_insn_addi_valid :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_valid :\n\t\tspec_insn_addw_valid ? spec_insn_addw_valid :\n\t\tspec_insn_and_valid ? spec_insn_and_valid :\n\t\tspec_insn_andi_valid ? spec_insn_andi_valid :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_valid :\n\t\tspec_insn_beq_valid ? spec_insn_beq_valid :\n\t\tspec_insn_bge_valid ? spec_insn_bge_valid :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_valid :\n\t\tspec_insn_blt_valid ? spec_insn_blt_valid :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_valid :\n\t\tspec_insn_bne_valid ? spec_insn_bne_valid :\n\t\tspec_insn_jal_valid ? spec_insn_jal_valid :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_valid :\n\t\tspec_insn_lb_valid ? spec_insn_lb_valid :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_valid :\n\t\tspec_insn_ld_valid ? spec_insn_ld_valid :\n\t\tspec_insn_lh_valid ? spec_insn_lh_valid :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_valid :\n\t\tspec_insn_lui_valid ? spec_insn_lui_valid :\n\t\tspec_insn_lw_valid ? spec_insn_lw_valid :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_valid :\n\t\tspec_insn_or_valid ? spec_insn_or_valid :\n\t\tspec_insn_ori_valid ? spec_insn_ori_valid :\n\t\tspec_insn_sb_valid ? spec_insn_sb_valid :\n\t\tspec_insn_sd_valid ? spec_insn_sd_valid :\n\t\tspec_insn_sh_valid ? spec_insn_sh_valid :\n\t\tspec_insn_sll_valid ? spec_insn_sll_valid :\n\t\tspec_insn_slli_valid ? spec_insn_slli_valid :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_valid :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_valid :\n\t\tspec_insn_slt_valid ? spec_insn_slt_valid :\n\t\tspec_insn_slti_valid ? spec_insn_slti_valid :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_valid :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_valid :\n\t\tspec_insn_sra_valid ? spec_insn_sra_valid :\n\t\tspec_insn_srai_valid ? spec_insn_srai_valid :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_valid :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_valid :\n\t\tspec_insn_srl_valid ? spec_insn_srl_valid :\n\t\tspec_insn_srli_valid ? spec_insn_srli_valid :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_valid :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_valid :\n\t\tspec_insn_sub_valid ? spec_insn_sub_valid :\n\t\tspec_insn_subw_valid ? spec_insn_subw_valid :\n\t\tspec_insn_sw_valid ? spec_insn_sw_valid :\n\t\tspec_insn_xor_valid ? spec_insn_xor_valid :\n\t\tspec_insn_xori_valid ? spec_insn_xori_valid : 0;\n  assign spec_trap =\n\t\tspec_insn_add_valid ? spec_insn_add_trap :\n\t\tspec_insn_addi_valid ? spec_insn_addi_trap :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_trap :\n\t\tspec_insn_addw_valid ? spec_insn_addw_trap :\n\t\tspec_insn_and_valid ? spec_insn_and_trap :\n\t\tspec_insn_andi_valid ? spec_insn_andi_trap :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_trap :\n\t\tspec_insn_beq_valid ? spec_insn_beq_trap :\n\t\tspec_insn_bge_valid ? spec_insn_bge_trap :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_trap :\n\t\tspec_insn_blt_valid ? spec_insn_blt_trap :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_trap :\n\t\tspec_insn_bne_valid ? spec_insn_bne_trap :\n\t\tspec_insn_jal_valid ? spec_insn_jal_trap :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_trap :\n\t\tspec_insn_lb_valid ? spec_insn_lb_trap :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_trap :\n\t\tspec_insn_ld_valid ? spec_insn_ld_trap :\n\t\tspec_insn_lh_valid ? spec_insn_lh_trap :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_trap :\n\t\tspec_insn_lui_valid ? spec_insn_lui_trap :\n\t\tspec_insn_lw_valid ? spec_insn_lw_trap :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_trap :\n\t\tspec_insn_or_valid ? spec_insn_or_trap :\n\t\tspec_insn_ori_valid ? spec_insn_ori_trap :\n\t\tspec_insn_sb_valid ? spec_insn_sb_trap :\n\t\tspec_insn_sd_valid ? spec_insn_sd_trap :\n\t\tspec_insn_sh_valid ? spec_insn_sh_trap :\n\t\tspec_insn_sll_valid ? spec_insn_sll_trap :\n\t\tspec_insn_slli_valid ? spec_insn_slli_trap :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_trap :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_trap :\n\t\tspec_insn_slt_valid ? spec_insn_slt_trap :\n\t\tspec_insn_slti_valid ? spec_insn_slti_trap :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_trap :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_trap :\n\t\tspec_insn_sra_valid ? spec_insn_sra_trap :\n\t\tspec_insn_srai_valid ? spec_insn_srai_trap :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_trap :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_trap :\n\t\tspec_insn_srl_valid ? spec_insn_srl_trap :\n\t\tspec_insn_srli_valid ? spec_insn_srli_trap :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_trap :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_trap :\n\t\tspec_insn_sub_valid ? spec_insn_sub_trap :\n\t\tspec_insn_subw_valid ? spec_insn_subw_trap :\n\t\tspec_insn_sw_valid ? spec_insn_sw_trap :\n\t\tspec_insn_xor_valid ? spec_insn_xor_trap :\n\t\tspec_insn_xori_valid ? spec_insn_xori_trap : 0;\n  assign spec_rs1_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs1_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs1_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rs1_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rs1_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs1_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs1_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs1_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs1_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs1_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs1_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs1_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs1_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs1_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs1_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs1_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs1_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rs1_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs1_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs1_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs1_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs1_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rs1_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs1_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs1_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs1_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rs1_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs1_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs1_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs1_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rs1_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rs1_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs1_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs1_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs1_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs1_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs1_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rs1_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs1_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs1_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rs1_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rs1_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs1_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rs1_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs1_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs1_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0;\n  assign spec_rs2_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs2_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs2_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rs2_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rs2_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs2_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs2_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs2_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs2_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs2_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs2_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs2_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs2_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs2_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs2_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs2_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs2_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rs2_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs2_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs2_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs2_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs2_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rs2_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs2_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs2_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs2_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rs2_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs2_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs2_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs2_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rs2_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rs2_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs2_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs2_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs2_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs2_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs2_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rs2_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs2_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs2_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rs2_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rs2_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs2_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rs2_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs2_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs2_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0;\n  assign spec_rd_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rd_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rd_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rd_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rd_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rd_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rd_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rd_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rd_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rd_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rd_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rd_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_addr : 0;\n  assign spec_rd_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rd_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rd_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rd_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rd_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rd_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rd_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rd_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rd_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rd_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rd_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rd_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0;\n  assign spec_pc_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_pc_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_pc_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_pc_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_pc_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_pc_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_pc_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_pc_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_pc_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_pc_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_pc_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_pc_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_pc_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_pc_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_pc_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_pc_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_pc_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_pc_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_pc_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_pc_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_pc_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_pc_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_pc_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_pc_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_pc_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_pc_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_pc_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_pc_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_pc_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_pc_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_pc_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_pc_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_pc_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_pc_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_pc_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_pc_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_pc_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_pc_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_pc_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_pc_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_pc_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_pc_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_pc_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_pc_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_pc_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_pc_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0;\n  assign spec_mem_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_addr : 0;\n  assign spec_mem_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_rmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_rmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_rmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_rmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_rmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_rmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_rmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_rmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_rmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_rmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_rmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0;\n  assign spec_mem_wmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_wmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_wmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_wmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_wmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_wmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_wmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_wmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_wmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_wmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_wmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_wmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0;\n  assign spec_mem_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0;\n`ifdef RISCV_FORMAL_CSR_MISA\n  assign spec_csr_misa_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_csr_misa_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_csr_misa_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_csr_misa_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0;\n`endif\nendmodule\n"
  },
  {
    "path": "insns/isa_rv64ic.txt",
    "content": "add\naddi\naddiw\naddw\nand\nandi\nauipc\nbeq\nbge\nbgeu\nblt\nbltu\nbne\nc_add\nc_addi\nc_addi16sp\nc_addi4spn\nc_addiw\nc_addw\nc_and\nc_andi\nc_beqz\nc_bnez\nc_j\nc_jalr\nc_jr\nc_ld\nc_ldsp\nc_li\nc_lui\nc_lw\nc_lwsp\nc_mv\nc_or\nc_sd\nc_sdsp\nc_slli\nc_srai\nc_srli\nc_sub\nc_subw\nc_sw\nc_swsp\nc_xor\njal\njalr\nlb\nlbu\nld\nlh\nlhu\nlui\nlw\nlwu\nor\nori\nsb\nsd\nsh\nsll\nslli\nslliw\nsllw\nslt\nslti\nsltiu\nsltu\nsra\nsrai\nsraiw\nsraw\nsrl\nsrli\nsrliw\nsrlw\nsub\nsubw\nsw\nxor\nxori\n"
  },
  {
    "path": "insns/isa_rv64ic.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_isa_rv64ic (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n  wire                                spec_insn_add_valid;\n  wire                                spec_insn_add_trap;\n  wire [                       4 : 0] spec_insn_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_add insn_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_add_valid),\n    .spec_trap(spec_insn_add_trap),\n    .spec_rs1_addr(spec_insn_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_add_rs2_addr),\n    .spec_rd_addr(spec_insn_add_rd_addr),\n    .spec_rd_wdata(spec_insn_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_add_pc_wdata),\n    .spec_mem_addr(spec_insn_add_mem_addr),\n    .spec_mem_rmask(spec_insn_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_add_mem_wdata)\n  );\n\n  wire                                spec_insn_addi_valid;\n  wire                                spec_insn_addi_trap;\n  wire [                       4 : 0] spec_insn_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addi insn_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addi_valid),\n    .spec_trap(spec_insn_addi_trap),\n    .spec_rs1_addr(spec_insn_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_addiw_valid;\n  wire                                spec_insn_addiw_trap;\n  wire [                       4 : 0] spec_insn_addiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_addiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_addiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addiw insn_addiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addiw_valid),\n    .spec_trap(spec_insn_addiw_trap),\n    .spec_rs1_addr(spec_insn_addiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_addiw_rs2_addr),\n    .spec_rd_addr(spec_insn_addiw_rd_addr),\n    .spec_rd_wdata(spec_insn_addiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_addiw_pc_wdata),\n    .spec_mem_addr(spec_insn_addiw_mem_addr),\n    .spec_mem_rmask(spec_insn_addiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_addiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_addiw_mem_wdata)\n  );\n\n  wire                                spec_insn_addw_valid;\n  wire                                spec_insn_addw_trap;\n  wire [                       4 : 0] spec_insn_addw_rs1_addr;\n  wire [                       4 : 0] spec_insn_addw_rs2_addr;\n  wire [                       4 : 0] spec_insn_addw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addw insn_addw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addw_valid),\n    .spec_trap(spec_insn_addw_trap),\n    .spec_rs1_addr(spec_insn_addw_rs1_addr),\n    .spec_rs2_addr(spec_insn_addw_rs2_addr),\n    .spec_rd_addr(spec_insn_addw_rd_addr),\n    .spec_rd_wdata(spec_insn_addw_rd_wdata),\n    .spec_pc_wdata(spec_insn_addw_pc_wdata),\n    .spec_mem_addr(spec_insn_addw_mem_addr),\n    .spec_mem_rmask(spec_insn_addw_mem_rmask),\n    .spec_mem_wmask(spec_insn_addw_mem_wmask),\n    .spec_mem_wdata(spec_insn_addw_mem_wdata)\n  );\n\n  wire                                spec_insn_and_valid;\n  wire                                spec_insn_and_trap;\n  wire [                       4 : 0] spec_insn_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_and insn_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_and_valid),\n    .spec_trap(spec_insn_and_trap),\n    .spec_rs1_addr(spec_insn_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_and_rs2_addr),\n    .spec_rd_addr(spec_insn_and_rd_addr),\n    .spec_rd_wdata(spec_insn_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_and_pc_wdata),\n    .spec_mem_addr(spec_insn_and_mem_addr),\n    .spec_mem_rmask(spec_insn_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_and_mem_wdata)\n  );\n\n  wire                                spec_insn_andi_valid;\n  wire                                spec_insn_andi_trap;\n  wire [                       4 : 0] spec_insn_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_andi insn_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_andi_valid),\n    .spec_trap(spec_insn_andi_trap),\n    .spec_rs1_addr(spec_insn_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_auipc_valid;\n  wire                                spec_insn_auipc_trap;\n  wire [                       4 : 0] spec_insn_auipc_rs1_addr;\n  wire [                       4 : 0] spec_insn_auipc_rs2_addr;\n  wire [                       4 : 0] spec_insn_auipc_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_csr_misa_rmask;\n`endif\n\n  rvfi_insn_auipc insn_auipc (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_auipc_valid),\n    .spec_trap(spec_insn_auipc_trap),\n    .spec_rs1_addr(spec_insn_auipc_rs1_addr),\n    .spec_rs2_addr(spec_insn_auipc_rs2_addr),\n    .spec_rd_addr(spec_insn_auipc_rd_addr),\n    .spec_rd_wdata(spec_insn_auipc_rd_wdata),\n    .spec_pc_wdata(spec_insn_auipc_pc_wdata),\n    .spec_mem_addr(spec_insn_auipc_mem_addr),\n    .spec_mem_rmask(spec_insn_auipc_mem_rmask),\n    .spec_mem_wmask(spec_insn_auipc_mem_wmask),\n    .spec_mem_wdata(spec_insn_auipc_mem_wdata)\n  );\n\n  wire                                spec_insn_beq_valid;\n  wire                                spec_insn_beq_trap;\n  wire [                       4 : 0] spec_insn_beq_rs1_addr;\n  wire [                       4 : 0] spec_insn_beq_rs2_addr;\n  wire [                       4 : 0] spec_insn_beq_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_csr_misa_rmask;\n`endif\n\n  rvfi_insn_beq insn_beq (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_beq_valid),\n    .spec_trap(spec_insn_beq_trap),\n    .spec_rs1_addr(spec_insn_beq_rs1_addr),\n    .spec_rs2_addr(spec_insn_beq_rs2_addr),\n    .spec_rd_addr(spec_insn_beq_rd_addr),\n    .spec_rd_wdata(spec_insn_beq_rd_wdata),\n    .spec_pc_wdata(spec_insn_beq_pc_wdata),\n    .spec_mem_addr(spec_insn_beq_mem_addr),\n    .spec_mem_rmask(spec_insn_beq_mem_rmask),\n    .spec_mem_wmask(spec_insn_beq_mem_wmask),\n    .spec_mem_wdata(spec_insn_beq_mem_wdata)\n  );\n\n  wire                                spec_insn_bge_valid;\n  wire                                spec_insn_bge_trap;\n  wire [                       4 : 0] spec_insn_bge_rs1_addr;\n  wire [                       4 : 0] spec_insn_bge_rs2_addr;\n  wire [                       4 : 0] spec_insn_bge_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bge insn_bge (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bge_valid),\n    .spec_trap(spec_insn_bge_trap),\n    .spec_rs1_addr(spec_insn_bge_rs1_addr),\n    .spec_rs2_addr(spec_insn_bge_rs2_addr),\n    .spec_rd_addr(spec_insn_bge_rd_addr),\n    .spec_rd_wdata(spec_insn_bge_rd_wdata),\n    .spec_pc_wdata(spec_insn_bge_pc_wdata),\n    .spec_mem_addr(spec_insn_bge_mem_addr),\n    .spec_mem_rmask(spec_insn_bge_mem_rmask),\n    .spec_mem_wmask(spec_insn_bge_mem_wmask),\n    .spec_mem_wdata(spec_insn_bge_mem_wdata)\n  );\n\n  wire                                spec_insn_bgeu_valid;\n  wire                                spec_insn_bgeu_trap;\n  wire [                       4 : 0] spec_insn_bgeu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bgeu insn_bgeu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bgeu_valid),\n    .spec_trap(spec_insn_bgeu_trap),\n    .spec_rs1_addr(spec_insn_bgeu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bgeu_rs2_addr),\n    .spec_rd_addr(spec_insn_bgeu_rd_addr),\n    .spec_rd_wdata(spec_insn_bgeu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bgeu_pc_wdata),\n    .spec_mem_addr(spec_insn_bgeu_mem_addr),\n    .spec_mem_rmask(spec_insn_bgeu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bgeu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bgeu_mem_wdata)\n  );\n\n  wire                                spec_insn_blt_valid;\n  wire                                spec_insn_blt_trap;\n  wire [                       4 : 0] spec_insn_blt_rs1_addr;\n  wire [                       4 : 0] spec_insn_blt_rs2_addr;\n  wire [                       4 : 0] spec_insn_blt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_blt insn_blt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_blt_valid),\n    .spec_trap(spec_insn_blt_trap),\n    .spec_rs1_addr(spec_insn_blt_rs1_addr),\n    .spec_rs2_addr(spec_insn_blt_rs2_addr),\n    .spec_rd_addr(spec_insn_blt_rd_addr),\n    .spec_rd_wdata(spec_insn_blt_rd_wdata),\n    .spec_pc_wdata(spec_insn_blt_pc_wdata),\n    .spec_mem_addr(spec_insn_blt_mem_addr),\n    .spec_mem_rmask(spec_insn_blt_mem_rmask),\n    .spec_mem_wmask(spec_insn_blt_mem_wmask),\n    .spec_mem_wdata(spec_insn_blt_mem_wdata)\n  );\n\n  wire                                spec_insn_bltu_valid;\n  wire                                spec_insn_bltu_trap;\n  wire [                       4 : 0] spec_insn_bltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bltu insn_bltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bltu_valid),\n    .spec_trap(spec_insn_bltu_trap),\n    .spec_rs1_addr(spec_insn_bltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bltu_rs2_addr),\n    .spec_rd_addr(spec_insn_bltu_rd_addr),\n    .spec_rd_wdata(spec_insn_bltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bltu_pc_wdata),\n    .spec_mem_addr(spec_insn_bltu_mem_addr),\n    .spec_mem_rmask(spec_insn_bltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bltu_mem_wdata)\n  );\n\n  wire                                spec_insn_bne_valid;\n  wire                                spec_insn_bne_trap;\n  wire [                       4 : 0] spec_insn_bne_rs1_addr;\n  wire [                       4 : 0] spec_insn_bne_rs2_addr;\n  wire [                       4 : 0] spec_insn_bne_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bne insn_bne (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bne_valid),\n    .spec_trap(spec_insn_bne_trap),\n    .spec_rs1_addr(spec_insn_bne_rs1_addr),\n    .spec_rs2_addr(spec_insn_bne_rs2_addr),\n    .spec_rd_addr(spec_insn_bne_rd_addr),\n    .spec_rd_wdata(spec_insn_bne_rd_wdata),\n    .spec_pc_wdata(spec_insn_bne_pc_wdata),\n    .spec_mem_addr(spec_insn_bne_mem_addr),\n    .spec_mem_rmask(spec_insn_bne_mem_rmask),\n    .spec_mem_wmask(spec_insn_bne_mem_wmask),\n    .spec_mem_wdata(spec_insn_bne_mem_wdata)\n  );\n\n  wire                                spec_insn_c_add_valid;\n  wire                                spec_insn_c_add_trap;\n  wire [                       4 : 0] spec_insn_c_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_add insn_c_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_add_valid),\n    .spec_trap(spec_insn_c_add_trap),\n    .spec_rs1_addr(spec_insn_c_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_add_rs2_addr),\n    .spec_rd_addr(spec_insn_c_add_rd_addr),\n    .spec_rd_wdata(spec_insn_c_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_add_pc_wdata),\n    .spec_mem_addr(spec_insn_c_add_mem_addr),\n    .spec_mem_rmask(spec_insn_c_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_add_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi_valid;\n  wire                                spec_insn_c_addi_trap;\n  wire [                       4 : 0] spec_insn_c_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi insn_c_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi_valid),\n    .spec_trap(spec_insn_c_addi_trap),\n    .spec_rs1_addr(spec_insn_c_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi16sp_valid;\n  wire                                spec_insn_c_addi16sp_trap;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi16sp insn_c_addi16sp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi16sp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi16sp_valid),\n    .spec_trap(spec_insn_c_addi16sp_trap),\n    .spec_rs1_addr(spec_insn_c_addi16sp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi16sp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi16sp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi16sp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi16sp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi16sp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi16sp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi16sp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi16sp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi4spn_valid;\n  wire                                spec_insn_c_addi4spn_trap;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi4spn insn_c_addi4spn (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi4spn_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi4spn_valid),\n    .spec_trap(spec_insn_c_addi4spn_trap),\n    .spec_rs1_addr(spec_insn_c_addi4spn_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi4spn_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi4spn_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi4spn_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi4spn_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi4spn_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi4spn_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi4spn_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi4spn_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addiw_valid;\n  wire                                spec_insn_c_addiw_trap;\n  wire [                       4 : 0] spec_insn_c_addiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addiw insn_c_addiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addiw_valid),\n    .spec_trap(spec_insn_c_addiw_trap),\n    .spec_rs1_addr(spec_insn_c_addiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addiw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addiw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addiw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addiw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addiw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addw_valid;\n  wire                                spec_insn_c_addw_trap;\n  wire [                       4 : 0] spec_insn_c_addw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addw insn_c_addw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addw_valid),\n    .spec_trap(spec_insn_c_addw_trap),\n    .spec_rs1_addr(spec_insn_c_addw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_and_valid;\n  wire                                spec_insn_c_and_trap;\n  wire [                       4 : 0] spec_insn_c_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_and insn_c_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_and_valid),\n    .spec_trap(spec_insn_c_and_trap),\n    .spec_rs1_addr(spec_insn_c_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_and_rs2_addr),\n    .spec_rd_addr(spec_insn_c_and_rd_addr),\n    .spec_rd_wdata(spec_insn_c_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_and_pc_wdata),\n    .spec_mem_addr(spec_insn_c_and_mem_addr),\n    .spec_mem_rmask(spec_insn_c_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_and_mem_wdata)\n  );\n\n  wire                                spec_insn_c_andi_valid;\n  wire                                spec_insn_c_andi_trap;\n  wire [                       4 : 0] spec_insn_c_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_andi insn_c_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_andi_valid),\n    .spec_trap(spec_insn_c_andi_trap),\n    .spec_rs1_addr(spec_insn_c_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_c_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_c_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_c_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_c_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_c_beqz_valid;\n  wire                                spec_insn_c_beqz_trap;\n  wire [                       4 : 0] spec_insn_c_beqz_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_beqz_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_beqz_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_beqz insn_c_beqz (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_beqz_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_beqz_valid),\n    .spec_trap(spec_insn_c_beqz_trap),\n    .spec_rs1_addr(spec_insn_c_beqz_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_beqz_rs2_addr),\n    .spec_rd_addr(spec_insn_c_beqz_rd_addr),\n    .spec_rd_wdata(spec_insn_c_beqz_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_beqz_pc_wdata),\n    .spec_mem_addr(spec_insn_c_beqz_mem_addr),\n    .spec_mem_rmask(spec_insn_c_beqz_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_beqz_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_beqz_mem_wdata)\n  );\n\n  wire                                spec_insn_c_bnez_valid;\n  wire                                spec_insn_c_bnez_trap;\n  wire [                       4 : 0] spec_insn_c_bnez_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_bnez_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_bnez_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_bnez insn_c_bnez (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_bnez_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_bnez_valid),\n    .spec_trap(spec_insn_c_bnez_trap),\n    .spec_rs1_addr(spec_insn_c_bnez_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_bnez_rs2_addr),\n    .spec_rd_addr(spec_insn_c_bnez_rd_addr),\n    .spec_rd_wdata(spec_insn_c_bnez_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_bnez_pc_wdata),\n    .spec_mem_addr(spec_insn_c_bnez_mem_addr),\n    .spec_mem_rmask(spec_insn_c_bnez_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_bnez_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_bnez_mem_wdata)\n  );\n\n  wire                                spec_insn_c_j_valid;\n  wire                                spec_insn_c_j_trap;\n  wire [                       4 : 0] spec_insn_c_j_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_j_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_j_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_j insn_c_j (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_j_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_j_valid),\n    .spec_trap(spec_insn_c_j_trap),\n    .spec_rs1_addr(spec_insn_c_j_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_j_rs2_addr),\n    .spec_rd_addr(spec_insn_c_j_rd_addr),\n    .spec_rd_wdata(spec_insn_c_j_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_j_pc_wdata),\n    .spec_mem_addr(spec_insn_c_j_mem_addr),\n    .spec_mem_rmask(spec_insn_c_j_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_j_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_j_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jalr_valid;\n  wire                                spec_insn_c_jalr_trap;\n  wire [                       4 : 0] spec_insn_c_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jalr insn_c_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jalr_valid),\n    .spec_trap(spec_insn_c_jalr_trap),\n    .spec_rs1_addr(spec_insn_c_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jr_valid;\n  wire                                spec_insn_c_jr_trap;\n  wire [                       4 : 0] spec_insn_c_jr_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jr_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jr insn_c_jr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jr_valid),\n    .spec_trap(spec_insn_c_jr_trap),\n    .spec_rs1_addr(spec_insn_c_jr_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jr_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jr_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jr_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jr_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jr_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jr_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jr_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jr_mem_wdata)\n  );\n\n  wire                                spec_insn_c_ld_valid;\n  wire                                spec_insn_c_ld_trap;\n  wire [                       4 : 0] spec_insn_c_ld_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_ld_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_ld_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ld_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ld_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_ld insn_c_ld (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_ld_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_ld_valid),\n    .spec_trap(spec_insn_c_ld_trap),\n    .spec_rs1_addr(spec_insn_c_ld_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_ld_rs2_addr),\n    .spec_rd_addr(spec_insn_c_ld_rd_addr),\n    .spec_rd_wdata(spec_insn_c_ld_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_ld_pc_wdata),\n    .spec_mem_addr(spec_insn_c_ld_mem_addr),\n    .spec_mem_rmask(spec_insn_c_ld_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_ld_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_ld_mem_wdata)\n  );\n\n  wire                                spec_insn_c_ldsp_valid;\n  wire                                spec_insn_c_ldsp_trap;\n  wire [                       4 : 0] spec_insn_c_ldsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_ldsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_ldsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ldsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ldsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_ldsp insn_c_ldsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_ldsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_ldsp_valid),\n    .spec_trap(spec_insn_c_ldsp_trap),\n    .spec_rs1_addr(spec_insn_c_ldsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_ldsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_ldsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_ldsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_ldsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_ldsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_ldsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_ldsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_ldsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_li_valid;\n  wire                                spec_insn_c_li_trap;\n  wire [                       4 : 0] spec_insn_c_li_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_li_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_li_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_li insn_c_li (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_li_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_li_valid),\n    .spec_trap(spec_insn_c_li_trap),\n    .spec_rs1_addr(spec_insn_c_li_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_li_rs2_addr),\n    .spec_rd_addr(spec_insn_c_li_rd_addr),\n    .spec_rd_wdata(spec_insn_c_li_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_li_pc_wdata),\n    .spec_mem_addr(spec_insn_c_li_mem_addr),\n    .spec_mem_rmask(spec_insn_c_li_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_li_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_li_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lui_valid;\n  wire                                spec_insn_c_lui_trap;\n  wire [                       4 : 0] spec_insn_c_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lui insn_c_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lui_valid),\n    .spec_trap(spec_insn_c_lui_trap),\n    .spec_rs1_addr(spec_insn_c_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lw_valid;\n  wire                                spec_insn_c_lw_trap;\n  wire [                       4 : 0] spec_insn_c_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lw insn_c_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lw_valid),\n    .spec_trap(spec_insn_c_lw_trap),\n    .spec_rs1_addr(spec_insn_c_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lwsp_valid;\n  wire                                spec_insn_c_lwsp_trap;\n  wire [                       4 : 0] spec_insn_c_lwsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lwsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lwsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lwsp insn_c_lwsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lwsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lwsp_valid),\n    .spec_trap(spec_insn_c_lwsp_trap),\n    .spec_rs1_addr(spec_insn_c_lwsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lwsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lwsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lwsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lwsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lwsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lwsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lwsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lwsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_mv_valid;\n  wire                                spec_insn_c_mv_trap;\n  wire [                       4 : 0] spec_insn_c_mv_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_mv_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_mv_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_mv insn_c_mv (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_mv_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_mv_valid),\n    .spec_trap(spec_insn_c_mv_trap),\n    .spec_rs1_addr(spec_insn_c_mv_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_mv_rs2_addr),\n    .spec_rd_addr(spec_insn_c_mv_rd_addr),\n    .spec_rd_wdata(spec_insn_c_mv_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_mv_pc_wdata),\n    .spec_mem_addr(spec_insn_c_mv_mem_addr),\n    .spec_mem_rmask(spec_insn_c_mv_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_mv_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_mv_mem_wdata)\n  );\n\n  wire                                spec_insn_c_or_valid;\n  wire                                spec_insn_c_or_trap;\n  wire [                       4 : 0] spec_insn_c_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_or insn_c_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_or_valid),\n    .spec_trap(spec_insn_c_or_trap),\n    .spec_rs1_addr(spec_insn_c_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_or_rs2_addr),\n    .spec_rd_addr(spec_insn_c_or_rd_addr),\n    .spec_rd_wdata(spec_insn_c_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_or_pc_wdata),\n    .spec_mem_addr(spec_insn_c_or_mem_addr),\n    .spec_mem_rmask(spec_insn_c_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_or_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sd_valid;\n  wire                                spec_insn_c_sd_trap;\n  wire [                       4 : 0] spec_insn_c_sd_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sd_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sd_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sd_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sd_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sd insn_c_sd (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sd_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sd_valid),\n    .spec_trap(spec_insn_c_sd_trap),\n    .spec_rs1_addr(spec_insn_c_sd_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sd_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sd_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sd_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sd_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sd_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sd_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sd_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sd_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sdsp_valid;\n  wire                                spec_insn_c_sdsp_trap;\n  wire [                       4 : 0] spec_insn_c_sdsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sdsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sdsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sdsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sdsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sdsp insn_c_sdsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sdsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sdsp_valid),\n    .spec_trap(spec_insn_c_sdsp_trap),\n    .spec_rs1_addr(spec_insn_c_sdsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sdsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sdsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sdsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sdsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sdsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sdsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sdsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sdsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_slli_valid;\n  wire                                spec_insn_c_slli_trap;\n  wire [                       4 : 0] spec_insn_c_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_slli insn_c_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_slli_valid),\n    .spec_trap(spec_insn_c_slli_trap),\n    .spec_rs1_addr(spec_insn_c_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_c_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_c_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_c_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_c_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_c_srai_valid;\n  wire                                spec_insn_c_srai_trap;\n  wire [                       4 : 0] spec_insn_c_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_srai insn_c_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_srai_valid),\n    .spec_trap(spec_insn_c_srai_trap),\n    .spec_rs1_addr(spec_insn_c_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_c_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_c_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_c_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_c_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_c_srli_valid;\n  wire                                spec_insn_c_srli_trap;\n  wire [                       4 : 0] spec_insn_c_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_srli insn_c_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_srli_valid),\n    .spec_trap(spec_insn_c_srli_trap),\n    .spec_rs1_addr(spec_insn_c_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_c_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_c_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_c_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_c_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sub_valid;\n  wire                                spec_insn_c_sub_trap;\n  wire [                       4 : 0] spec_insn_c_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sub insn_c_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sub_valid),\n    .spec_trap(spec_insn_c_sub_trap),\n    .spec_rs1_addr(spec_insn_c_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_c_subw_valid;\n  wire                                spec_insn_c_subw_trap;\n  wire [                       4 : 0] spec_insn_c_subw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_subw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_subw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_subw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_subw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_subw insn_c_subw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_subw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_subw_valid),\n    .spec_trap(spec_insn_c_subw_trap),\n    .spec_rs1_addr(spec_insn_c_subw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_subw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_subw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_subw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_subw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_subw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_subw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_subw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_subw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sw_valid;\n  wire                                spec_insn_c_sw_trap;\n  wire [                       4 : 0] spec_insn_c_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sw insn_c_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sw_valid),\n    .spec_trap(spec_insn_c_sw_trap),\n    .spec_rs1_addr(spec_insn_c_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_swsp_valid;\n  wire                                spec_insn_c_swsp_trap;\n  wire [                       4 : 0] spec_insn_c_swsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_swsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_swsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_swsp insn_c_swsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_swsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_swsp_valid),\n    .spec_trap(spec_insn_c_swsp_trap),\n    .spec_rs1_addr(spec_insn_c_swsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_swsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_swsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_swsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_swsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_swsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_swsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_swsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_swsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_xor_valid;\n  wire                                spec_insn_c_xor_trap;\n  wire [                       4 : 0] spec_insn_c_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_xor insn_c_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_xor_valid),\n    .spec_trap(spec_insn_c_xor_trap),\n    .spec_rs1_addr(spec_insn_c_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_c_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_c_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_c_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_c_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_jal_valid;\n  wire                                spec_insn_jal_trap;\n  wire [                       4 : 0] spec_insn_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jal insn_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jal_valid),\n    .spec_trap(spec_insn_jal_trap),\n    .spec_rs1_addr(spec_insn_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_jalr_valid;\n  wire                                spec_insn_jalr_trap;\n  wire [                       4 : 0] spec_insn_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jalr insn_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jalr_valid),\n    .spec_trap(spec_insn_jalr_trap),\n    .spec_rs1_addr(spec_insn_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_lb_valid;\n  wire                                spec_insn_lb_trap;\n  wire [                       4 : 0] spec_insn_lb_rs1_addr;\n  wire [                       4 : 0] spec_insn_lb_rs2_addr;\n  wire [                       4 : 0] spec_insn_lb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lb insn_lb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lb_valid),\n    .spec_trap(spec_insn_lb_trap),\n    .spec_rs1_addr(spec_insn_lb_rs1_addr),\n    .spec_rs2_addr(spec_insn_lb_rs2_addr),\n    .spec_rd_addr(spec_insn_lb_rd_addr),\n    .spec_rd_wdata(spec_insn_lb_rd_wdata),\n    .spec_pc_wdata(spec_insn_lb_pc_wdata),\n    .spec_mem_addr(spec_insn_lb_mem_addr),\n    .spec_mem_rmask(spec_insn_lb_mem_rmask),\n    .spec_mem_wmask(spec_insn_lb_mem_wmask),\n    .spec_mem_wdata(spec_insn_lb_mem_wdata)\n  );\n\n  wire                                spec_insn_lbu_valid;\n  wire                                spec_insn_lbu_trap;\n  wire [                       4 : 0] spec_insn_lbu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lbu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lbu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lbu insn_lbu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lbu_valid),\n    .spec_trap(spec_insn_lbu_trap),\n    .spec_rs1_addr(spec_insn_lbu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lbu_rs2_addr),\n    .spec_rd_addr(spec_insn_lbu_rd_addr),\n    .spec_rd_wdata(spec_insn_lbu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lbu_pc_wdata),\n    .spec_mem_addr(spec_insn_lbu_mem_addr),\n    .spec_mem_rmask(spec_insn_lbu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lbu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lbu_mem_wdata)\n  );\n\n  wire                                spec_insn_ld_valid;\n  wire                                spec_insn_ld_trap;\n  wire [                       4 : 0] spec_insn_ld_rs1_addr;\n  wire [                       4 : 0] spec_insn_ld_rs2_addr;\n  wire [                       4 : 0] spec_insn_ld_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ld insn_ld (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ld_valid),\n    .spec_trap(spec_insn_ld_trap),\n    .spec_rs1_addr(spec_insn_ld_rs1_addr),\n    .spec_rs2_addr(spec_insn_ld_rs2_addr),\n    .spec_rd_addr(spec_insn_ld_rd_addr),\n    .spec_rd_wdata(spec_insn_ld_rd_wdata),\n    .spec_pc_wdata(spec_insn_ld_pc_wdata),\n    .spec_mem_addr(spec_insn_ld_mem_addr),\n    .spec_mem_rmask(spec_insn_ld_mem_rmask),\n    .spec_mem_wmask(spec_insn_ld_mem_wmask),\n    .spec_mem_wdata(spec_insn_ld_mem_wdata)\n  );\n\n  wire                                spec_insn_lh_valid;\n  wire                                spec_insn_lh_trap;\n  wire [                       4 : 0] spec_insn_lh_rs1_addr;\n  wire [                       4 : 0] spec_insn_lh_rs2_addr;\n  wire [                       4 : 0] spec_insn_lh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lh insn_lh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lh_valid),\n    .spec_trap(spec_insn_lh_trap),\n    .spec_rs1_addr(spec_insn_lh_rs1_addr),\n    .spec_rs2_addr(spec_insn_lh_rs2_addr),\n    .spec_rd_addr(spec_insn_lh_rd_addr),\n    .spec_rd_wdata(spec_insn_lh_rd_wdata),\n    .spec_pc_wdata(spec_insn_lh_pc_wdata),\n    .spec_mem_addr(spec_insn_lh_mem_addr),\n    .spec_mem_rmask(spec_insn_lh_mem_rmask),\n    .spec_mem_wmask(spec_insn_lh_mem_wmask),\n    .spec_mem_wdata(spec_insn_lh_mem_wdata)\n  );\n\n  wire                                spec_insn_lhu_valid;\n  wire                                spec_insn_lhu_trap;\n  wire [                       4 : 0] spec_insn_lhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lhu insn_lhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lhu_valid),\n    .spec_trap(spec_insn_lhu_trap),\n    .spec_rs1_addr(spec_insn_lhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lhu_rs2_addr),\n    .spec_rd_addr(spec_insn_lhu_rd_addr),\n    .spec_rd_wdata(spec_insn_lhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lhu_pc_wdata),\n    .spec_mem_addr(spec_insn_lhu_mem_addr),\n    .spec_mem_rmask(spec_insn_lhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lhu_mem_wdata)\n  );\n\n  wire                                spec_insn_lui_valid;\n  wire                                spec_insn_lui_trap;\n  wire [                       4 : 0] spec_insn_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lui insn_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lui_valid),\n    .spec_trap(spec_insn_lui_trap),\n    .spec_rs1_addr(spec_insn_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_lw_valid;\n  wire                                spec_insn_lw_trap;\n  wire [                       4 : 0] spec_insn_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lw insn_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lw_valid),\n    .spec_trap(spec_insn_lw_trap),\n    .spec_rs1_addr(spec_insn_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_lwu_valid;\n  wire                                spec_insn_lwu_trap;\n  wire [                       4 : 0] spec_insn_lwu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lwu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lwu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lwu insn_lwu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lwu_valid),\n    .spec_trap(spec_insn_lwu_trap),\n    .spec_rs1_addr(spec_insn_lwu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lwu_rs2_addr),\n    .spec_rd_addr(spec_insn_lwu_rd_addr),\n    .spec_rd_wdata(spec_insn_lwu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lwu_pc_wdata),\n    .spec_mem_addr(spec_insn_lwu_mem_addr),\n    .spec_mem_rmask(spec_insn_lwu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lwu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lwu_mem_wdata)\n  );\n\n  wire                                spec_insn_or_valid;\n  wire                                spec_insn_or_trap;\n  wire [                       4 : 0] spec_insn_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_or insn_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_or_valid),\n    .spec_trap(spec_insn_or_trap),\n    .spec_rs1_addr(spec_insn_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_or_rs2_addr),\n    .spec_rd_addr(spec_insn_or_rd_addr),\n    .spec_rd_wdata(spec_insn_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_or_pc_wdata),\n    .spec_mem_addr(spec_insn_or_mem_addr),\n    .spec_mem_rmask(spec_insn_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_or_mem_wdata)\n  );\n\n  wire                                spec_insn_ori_valid;\n  wire                                spec_insn_ori_trap;\n  wire [                       4 : 0] spec_insn_ori_rs1_addr;\n  wire [                       4 : 0] spec_insn_ori_rs2_addr;\n  wire [                       4 : 0] spec_insn_ori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ori insn_ori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ori_valid),\n    .spec_trap(spec_insn_ori_trap),\n    .spec_rs1_addr(spec_insn_ori_rs1_addr),\n    .spec_rs2_addr(spec_insn_ori_rs2_addr),\n    .spec_rd_addr(spec_insn_ori_rd_addr),\n    .spec_rd_wdata(spec_insn_ori_rd_wdata),\n    .spec_pc_wdata(spec_insn_ori_pc_wdata),\n    .spec_mem_addr(spec_insn_ori_mem_addr),\n    .spec_mem_rmask(spec_insn_ori_mem_rmask),\n    .spec_mem_wmask(spec_insn_ori_mem_wmask),\n    .spec_mem_wdata(spec_insn_ori_mem_wdata)\n  );\n\n  wire                                spec_insn_sb_valid;\n  wire                                spec_insn_sb_trap;\n  wire [                       4 : 0] spec_insn_sb_rs1_addr;\n  wire [                       4 : 0] spec_insn_sb_rs2_addr;\n  wire [                       4 : 0] spec_insn_sb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sb insn_sb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sb_valid),\n    .spec_trap(spec_insn_sb_trap),\n    .spec_rs1_addr(spec_insn_sb_rs1_addr),\n    .spec_rs2_addr(spec_insn_sb_rs2_addr),\n    .spec_rd_addr(spec_insn_sb_rd_addr),\n    .spec_rd_wdata(spec_insn_sb_rd_wdata),\n    .spec_pc_wdata(spec_insn_sb_pc_wdata),\n    .spec_mem_addr(spec_insn_sb_mem_addr),\n    .spec_mem_rmask(spec_insn_sb_mem_rmask),\n    .spec_mem_wmask(spec_insn_sb_mem_wmask),\n    .spec_mem_wdata(spec_insn_sb_mem_wdata)\n  );\n\n  wire                                spec_insn_sd_valid;\n  wire                                spec_insn_sd_trap;\n  wire [                       4 : 0] spec_insn_sd_rs1_addr;\n  wire [                       4 : 0] spec_insn_sd_rs2_addr;\n  wire [                       4 : 0] spec_insn_sd_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sd insn_sd (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sd_valid),\n    .spec_trap(spec_insn_sd_trap),\n    .spec_rs1_addr(spec_insn_sd_rs1_addr),\n    .spec_rs2_addr(spec_insn_sd_rs2_addr),\n    .spec_rd_addr(spec_insn_sd_rd_addr),\n    .spec_rd_wdata(spec_insn_sd_rd_wdata),\n    .spec_pc_wdata(spec_insn_sd_pc_wdata),\n    .spec_mem_addr(spec_insn_sd_mem_addr),\n    .spec_mem_rmask(spec_insn_sd_mem_rmask),\n    .spec_mem_wmask(spec_insn_sd_mem_wmask),\n    .spec_mem_wdata(spec_insn_sd_mem_wdata)\n  );\n\n  wire                                spec_insn_sh_valid;\n  wire                                spec_insn_sh_trap;\n  wire [                       4 : 0] spec_insn_sh_rs1_addr;\n  wire [                       4 : 0] spec_insn_sh_rs2_addr;\n  wire [                       4 : 0] spec_insn_sh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sh insn_sh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sh_valid),\n    .spec_trap(spec_insn_sh_trap),\n    .spec_rs1_addr(spec_insn_sh_rs1_addr),\n    .spec_rs2_addr(spec_insn_sh_rs2_addr),\n    .spec_rd_addr(spec_insn_sh_rd_addr),\n    .spec_rd_wdata(spec_insn_sh_rd_wdata),\n    .spec_pc_wdata(spec_insn_sh_pc_wdata),\n    .spec_mem_addr(spec_insn_sh_mem_addr),\n    .spec_mem_rmask(spec_insn_sh_mem_rmask),\n    .spec_mem_wmask(spec_insn_sh_mem_wmask),\n    .spec_mem_wdata(spec_insn_sh_mem_wdata)\n  );\n\n  wire                                spec_insn_sll_valid;\n  wire                                spec_insn_sll_trap;\n  wire [                       4 : 0] spec_insn_sll_rs1_addr;\n  wire [                       4 : 0] spec_insn_sll_rs2_addr;\n  wire [                       4 : 0] spec_insn_sll_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sll insn_sll (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sll_valid),\n    .spec_trap(spec_insn_sll_trap),\n    .spec_rs1_addr(spec_insn_sll_rs1_addr),\n    .spec_rs2_addr(spec_insn_sll_rs2_addr),\n    .spec_rd_addr(spec_insn_sll_rd_addr),\n    .spec_rd_wdata(spec_insn_sll_rd_wdata),\n    .spec_pc_wdata(spec_insn_sll_pc_wdata),\n    .spec_mem_addr(spec_insn_sll_mem_addr),\n    .spec_mem_rmask(spec_insn_sll_mem_rmask),\n    .spec_mem_wmask(spec_insn_sll_mem_wmask),\n    .spec_mem_wdata(spec_insn_sll_mem_wdata)\n  );\n\n  wire                                spec_insn_slli_valid;\n  wire                                spec_insn_slli_trap;\n  wire [                       4 : 0] spec_insn_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slli insn_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slli_valid),\n    .spec_trap(spec_insn_slli_trap),\n    .spec_rs1_addr(spec_insn_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_slliw_valid;\n  wire                                spec_insn_slliw_trap;\n  wire [                       4 : 0] spec_insn_slliw_rs1_addr;\n  wire [                       4 : 0] spec_insn_slliw_rs2_addr;\n  wire [                       4 : 0] spec_insn_slliw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slliw insn_slliw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slliw_valid),\n    .spec_trap(spec_insn_slliw_trap),\n    .spec_rs1_addr(spec_insn_slliw_rs1_addr),\n    .spec_rs2_addr(spec_insn_slliw_rs2_addr),\n    .spec_rd_addr(spec_insn_slliw_rd_addr),\n    .spec_rd_wdata(spec_insn_slliw_rd_wdata),\n    .spec_pc_wdata(spec_insn_slliw_pc_wdata),\n    .spec_mem_addr(spec_insn_slliw_mem_addr),\n    .spec_mem_rmask(spec_insn_slliw_mem_rmask),\n    .spec_mem_wmask(spec_insn_slliw_mem_wmask),\n    .spec_mem_wdata(spec_insn_slliw_mem_wdata)\n  );\n\n  wire                                spec_insn_sllw_valid;\n  wire                                spec_insn_sllw_trap;\n  wire [                       4 : 0] spec_insn_sllw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sllw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sllw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sllw insn_sllw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sllw_valid),\n    .spec_trap(spec_insn_sllw_trap),\n    .spec_rs1_addr(spec_insn_sllw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sllw_rs2_addr),\n    .spec_rd_addr(spec_insn_sllw_rd_addr),\n    .spec_rd_wdata(spec_insn_sllw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sllw_pc_wdata),\n    .spec_mem_addr(spec_insn_sllw_mem_addr),\n    .spec_mem_rmask(spec_insn_sllw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sllw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sllw_mem_wdata)\n  );\n\n  wire                                spec_insn_slt_valid;\n  wire                                spec_insn_slt_trap;\n  wire [                       4 : 0] spec_insn_slt_rs1_addr;\n  wire [                       4 : 0] spec_insn_slt_rs2_addr;\n  wire [                       4 : 0] spec_insn_slt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slt insn_slt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slt_valid),\n    .spec_trap(spec_insn_slt_trap),\n    .spec_rs1_addr(spec_insn_slt_rs1_addr),\n    .spec_rs2_addr(spec_insn_slt_rs2_addr),\n    .spec_rd_addr(spec_insn_slt_rd_addr),\n    .spec_rd_wdata(spec_insn_slt_rd_wdata),\n    .spec_pc_wdata(spec_insn_slt_pc_wdata),\n    .spec_mem_addr(spec_insn_slt_mem_addr),\n    .spec_mem_rmask(spec_insn_slt_mem_rmask),\n    .spec_mem_wmask(spec_insn_slt_mem_wmask),\n    .spec_mem_wdata(spec_insn_slt_mem_wdata)\n  );\n\n  wire                                spec_insn_slti_valid;\n  wire                                spec_insn_slti_trap;\n  wire [                       4 : 0] spec_insn_slti_rs1_addr;\n  wire [                       4 : 0] spec_insn_slti_rs2_addr;\n  wire [                       4 : 0] spec_insn_slti_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slti insn_slti (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slti_valid),\n    .spec_trap(spec_insn_slti_trap),\n    .spec_rs1_addr(spec_insn_slti_rs1_addr),\n    .spec_rs2_addr(spec_insn_slti_rs2_addr),\n    .spec_rd_addr(spec_insn_slti_rd_addr),\n    .spec_rd_wdata(spec_insn_slti_rd_wdata),\n    .spec_pc_wdata(spec_insn_slti_pc_wdata),\n    .spec_mem_addr(spec_insn_slti_mem_addr),\n    .spec_mem_rmask(spec_insn_slti_mem_rmask),\n    .spec_mem_wmask(spec_insn_slti_mem_wmask),\n    .spec_mem_wdata(spec_insn_slti_mem_wdata)\n  );\n\n  wire                                spec_insn_sltiu_valid;\n  wire                                spec_insn_sltiu_trap;\n  wire [                       4 : 0] spec_insn_sltiu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltiu insn_sltiu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltiu_valid),\n    .spec_trap(spec_insn_sltiu_trap),\n    .spec_rs1_addr(spec_insn_sltiu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltiu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltiu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltiu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltiu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltiu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltiu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltiu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltiu_mem_wdata)\n  );\n\n  wire                                spec_insn_sltu_valid;\n  wire                                spec_insn_sltu_trap;\n  wire [                       4 : 0] spec_insn_sltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltu insn_sltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltu_valid),\n    .spec_trap(spec_insn_sltu_trap),\n    .spec_rs1_addr(spec_insn_sltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltu_mem_wdata)\n  );\n\n  wire                                spec_insn_sra_valid;\n  wire                                spec_insn_sra_trap;\n  wire [                       4 : 0] spec_insn_sra_rs1_addr;\n  wire [                       4 : 0] spec_insn_sra_rs2_addr;\n  wire [                       4 : 0] spec_insn_sra_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sra insn_sra (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sra_valid),\n    .spec_trap(spec_insn_sra_trap),\n    .spec_rs1_addr(spec_insn_sra_rs1_addr),\n    .spec_rs2_addr(spec_insn_sra_rs2_addr),\n    .spec_rd_addr(spec_insn_sra_rd_addr),\n    .spec_rd_wdata(spec_insn_sra_rd_wdata),\n    .spec_pc_wdata(spec_insn_sra_pc_wdata),\n    .spec_mem_addr(spec_insn_sra_mem_addr),\n    .spec_mem_rmask(spec_insn_sra_mem_rmask),\n    .spec_mem_wmask(spec_insn_sra_mem_wmask),\n    .spec_mem_wdata(spec_insn_sra_mem_wdata)\n  );\n\n  wire                                spec_insn_srai_valid;\n  wire                                spec_insn_srai_trap;\n  wire [                       4 : 0] spec_insn_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srai insn_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srai_valid),\n    .spec_trap(spec_insn_srai_trap),\n    .spec_rs1_addr(spec_insn_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_sraiw_valid;\n  wire                                spec_insn_sraiw_trap;\n  wire [                       4 : 0] spec_insn_sraiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sraiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sraiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sraiw insn_sraiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sraiw_valid),\n    .spec_trap(spec_insn_sraiw_trap),\n    .spec_rs1_addr(spec_insn_sraiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sraiw_rs2_addr),\n    .spec_rd_addr(spec_insn_sraiw_rd_addr),\n    .spec_rd_wdata(spec_insn_sraiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sraiw_pc_wdata),\n    .spec_mem_addr(spec_insn_sraiw_mem_addr),\n    .spec_mem_rmask(spec_insn_sraiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sraiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sraiw_mem_wdata)\n  );\n\n  wire                                spec_insn_sraw_valid;\n  wire                                spec_insn_sraw_trap;\n  wire [                       4 : 0] spec_insn_sraw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sraw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sraw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sraw insn_sraw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sraw_valid),\n    .spec_trap(spec_insn_sraw_trap),\n    .spec_rs1_addr(spec_insn_sraw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sraw_rs2_addr),\n    .spec_rd_addr(spec_insn_sraw_rd_addr),\n    .spec_rd_wdata(spec_insn_sraw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sraw_pc_wdata),\n    .spec_mem_addr(spec_insn_sraw_mem_addr),\n    .spec_mem_rmask(spec_insn_sraw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sraw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sraw_mem_wdata)\n  );\n\n  wire                                spec_insn_srl_valid;\n  wire                                spec_insn_srl_trap;\n  wire [                       4 : 0] spec_insn_srl_rs1_addr;\n  wire [                       4 : 0] spec_insn_srl_rs2_addr;\n  wire [                       4 : 0] spec_insn_srl_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srl insn_srl (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srl_valid),\n    .spec_trap(spec_insn_srl_trap),\n    .spec_rs1_addr(spec_insn_srl_rs1_addr),\n    .spec_rs2_addr(spec_insn_srl_rs2_addr),\n    .spec_rd_addr(spec_insn_srl_rd_addr),\n    .spec_rd_wdata(spec_insn_srl_rd_wdata),\n    .spec_pc_wdata(spec_insn_srl_pc_wdata),\n    .spec_mem_addr(spec_insn_srl_mem_addr),\n    .spec_mem_rmask(spec_insn_srl_mem_rmask),\n    .spec_mem_wmask(spec_insn_srl_mem_wmask),\n    .spec_mem_wdata(spec_insn_srl_mem_wdata)\n  );\n\n  wire                                spec_insn_srli_valid;\n  wire                                spec_insn_srli_trap;\n  wire [                       4 : 0] spec_insn_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srli insn_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srli_valid),\n    .spec_trap(spec_insn_srli_trap),\n    .spec_rs1_addr(spec_insn_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_srliw_valid;\n  wire                                spec_insn_srliw_trap;\n  wire [                       4 : 0] spec_insn_srliw_rs1_addr;\n  wire [                       4 : 0] spec_insn_srliw_rs2_addr;\n  wire [                       4 : 0] spec_insn_srliw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srliw insn_srliw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srliw_valid),\n    .spec_trap(spec_insn_srliw_trap),\n    .spec_rs1_addr(spec_insn_srliw_rs1_addr),\n    .spec_rs2_addr(spec_insn_srliw_rs2_addr),\n    .spec_rd_addr(spec_insn_srliw_rd_addr),\n    .spec_rd_wdata(spec_insn_srliw_rd_wdata),\n    .spec_pc_wdata(spec_insn_srliw_pc_wdata),\n    .spec_mem_addr(spec_insn_srliw_mem_addr),\n    .spec_mem_rmask(spec_insn_srliw_mem_rmask),\n    .spec_mem_wmask(spec_insn_srliw_mem_wmask),\n    .spec_mem_wdata(spec_insn_srliw_mem_wdata)\n  );\n\n  wire                                spec_insn_srlw_valid;\n  wire                                spec_insn_srlw_trap;\n  wire [                       4 : 0] spec_insn_srlw_rs1_addr;\n  wire [                       4 : 0] spec_insn_srlw_rs2_addr;\n  wire [                       4 : 0] spec_insn_srlw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srlw insn_srlw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srlw_valid),\n    .spec_trap(spec_insn_srlw_trap),\n    .spec_rs1_addr(spec_insn_srlw_rs1_addr),\n    .spec_rs2_addr(spec_insn_srlw_rs2_addr),\n    .spec_rd_addr(spec_insn_srlw_rd_addr),\n    .spec_rd_wdata(spec_insn_srlw_rd_wdata),\n    .spec_pc_wdata(spec_insn_srlw_pc_wdata),\n    .spec_mem_addr(spec_insn_srlw_mem_addr),\n    .spec_mem_rmask(spec_insn_srlw_mem_rmask),\n    .spec_mem_wmask(spec_insn_srlw_mem_wmask),\n    .spec_mem_wdata(spec_insn_srlw_mem_wdata)\n  );\n\n  wire                                spec_insn_sub_valid;\n  wire                                spec_insn_sub_trap;\n  wire [                       4 : 0] spec_insn_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sub insn_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sub_valid),\n    .spec_trap(spec_insn_sub_trap),\n    .spec_rs1_addr(spec_insn_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_subw_valid;\n  wire                                spec_insn_subw_trap;\n  wire [                       4 : 0] spec_insn_subw_rs1_addr;\n  wire [                       4 : 0] spec_insn_subw_rs2_addr;\n  wire [                       4 : 0] spec_insn_subw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_subw insn_subw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_subw_valid),\n    .spec_trap(spec_insn_subw_trap),\n    .spec_rs1_addr(spec_insn_subw_rs1_addr),\n    .spec_rs2_addr(spec_insn_subw_rs2_addr),\n    .spec_rd_addr(spec_insn_subw_rd_addr),\n    .spec_rd_wdata(spec_insn_subw_rd_wdata),\n    .spec_pc_wdata(spec_insn_subw_pc_wdata),\n    .spec_mem_addr(spec_insn_subw_mem_addr),\n    .spec_mem_rmask(spec_insn_subw_mem_rmask),\n    .spec_mem_wmask(spec_insn_subw_mem_wmask),\n    .spec_mem_wdata(spec_insn_subw_mem_wdata)\n  );\n\n  wire                                spec_insn_sw_valid;\n  wire                                spec_insn_sw_trap;\n  wire [                       4 : 0] spec_insn_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sw insn_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sw_valid),\n    .spec_trap(spec_insn_sw_trap),\n    .spec_rs1_addr(spec_insn_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_xor_valid;\n  wire                                spec_insn_xor_trap;\n  wire [                       4 : 0] spec_insn_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xor insn_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xor_valid),\n    .spec_trap(spec_insn_xor_trap),\n    .spec_rs1_addr(spec_insn_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_xori_valid;\n  wire                                spec_insn_xori_trap;\n  wire [                       4 : 0] spec_insn_xori_rs1_addr;\n  wire [                       4 : 0] spec_insn_xori_rs2_addr;\n  wire [                       4 : 0] spec_insn_xori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xori insn_xori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xori_valid),\n    .spec_trap(spec_insn_xori_trap),\n    .spec_rs1_addr(spec_insn_xori_rs1_addr),\n    .spec_rs2_addr(spec_insn_xori_rs2_addr),\n    .spec_rd_addr(spec_insn_xori_rd_addr),\n    .spec_rd_wdata(spec_insn_xori_rd_wdata),\n    .spec_pc_wdata(spec_insn_xori_pc_wdata),\n    .spec_mem_addr(spec_insn_xori_mem_addr),\n    .spec_mem_rmask(spec_insn_xori_mem_rmask),\n    .spec_mem_wmask(spec_insn_xori_mem_wmask),\n    .spec_mem_wdata(spec_insn_xori_mem_wdata)\n  );\n\n  assign spec_valid =\n\t\tspec_insn_add_valid ? spec_insn_add_valid :\n\t\tspec_insn_addi_valid ? spec_insn_addi_valid :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_valid :\n\t\tspec_insn_addw_valid ? spec_insn_addw_valid :\n\t\tspec_insn_and_valid ? spec_insn_and_valid :\n\t\tspec_insn_andi_valid ? spec_insn_andi_valid :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_valid :\n\t\tspec_insn_beq_valid ? spec_insn_beq_valid :\n\t\tspec_insn_bge_valid ? spec_insn_bge_valid :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_valid :\n\t\tspec_insn_blt_valid ? spec_insn_blt_valid :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_valid :\n\t\tspec_insn_bne_valid ? spec_insn_bne_valid :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_valid :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_valid :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_valid :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_valid :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_valid :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_valid :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_valid :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_valid :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_valid :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_valid :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_valid :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_valid :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_valid :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_valid :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_valid :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_valid :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_valid :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_valid :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_valid :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_valid :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_valid :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_valid :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_valid :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_valid :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_valid :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_valid :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_valid :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_valid :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_valid :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_valid :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_valid :\n\t\tspec_insn_jal_valid ? spec_insn_jal_valid :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_valid :\n\t\tspec_insn_lb_valid ? spec_insn_lb_valid :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_valid :\n\t\tspec_insn_ld_valid ? spec_insn_ld_valid :\n\t\tspec_insn_lh_valid ? spec_insn_lh_valid :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_valid :\n\t\tspec_insn_lui_valid ? spec_insn_lui_valid :\n\t\tspec_insn_lw_valid ? spec_insn_lw_valid :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_valid :\n\t\tspec_insn_or_valid ? spec_insn_or_valid :\n\t\tspec_insn_ori_valid ? spec_insn_ori_valid :\n\t\tspec_insn_sb_valid ? spec_insn_sb_valid :\n\t\tspec_insn_sd_valid ? spec_insn_sd_valid :\n\t\tspec_insn_sh_valid ? spec_insn_sh_valid :\n\t\tspec_insn_sll_valid ? spec_insn_sll_valid :\n\t\tspec_insn_slli_valid ? spec_insn_slli_valid :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_valid :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_valid :\n\t\tspec_insn_slt_valid ? spec_insn_slt_valid :\n\t\tspec_insn_slti_valid ? spec_insn_slti_valid :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_valid :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_valid :\n\t\tspec_insn_sra_valid ? spec_insn_sra_valid :\n\t\tspec_insn_srai_valid ? spec_insn_srai_valid :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_valid :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_valid :\n\t\tspec_insn_srl_valid ? spec_insn_srl_valid :\n\t\tspec_insn_srli_valid ? spec_insn_srli_valid :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_valid :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_valid :\n\t\tspec_insn_sub_valid ? spec_insn_sub_valid :\n\t\tspec_insn_subw_valid ? spec_insn_subw_valid :\n\t\tspec_insn_sw_valid ? spec_insn_sw_valid :\n\t\tspec_insn_xor_valid ? spec_insn_xor_valid :\n\t\tspec_insn_xori_valid ? spec_insn_xori_valid : 0;\n  assign spec_trap =\n\t\tspec_insn_add_valid ? spec_insn_add_trap :\n\t\tspec_insn_addi_valid ? spec_insn_addi_trap :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_trap :\n\t\tspec_insn_addw_valid ? spec_insn_addw_trap :\n\t\tspec_insn_and_valid ? spec_insn_and_trap :\n\t\tspec_insn_andi_valid ? spec_insn_andi_trap :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_trap :\n\t\tspec_insn_beq_valid ? spec_insn_beq_trap :\n\t\tspec_insn_bge_valid ? spec_insn_bge_trap :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_trap :\n\t\tspec_insn_blt_valid ? spec_insn_blt_trap :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_trap :\n\t\tspec_insn_bne_valid ? spec_insn_bne_trap :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_trap :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_trap :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_trap :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_trap :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_trap :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_trap :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_trap :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_trap :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_trap :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_trap :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_trap :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_trap :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_trap :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_trap :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_trap :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_trap :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_trap :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_trap :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_trap :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_trap :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_trap :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_trap :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_trap :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_trap :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_trap :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_trap :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_trap :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_trap :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_trap :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_trap :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_trap :\n\t\tspec_insn_jal_valid ? spec_insn_jal_trap :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_trap :\n\t\tspec_insn_lb_valid ? spec_insn_lb_trap :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_trap :\n\t\tspec_insn_ld_valid ? spec_insn_ld_trap :\n\t\tspec_insn_lh_valid ? spec_insn_lh_trap :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_trap :\n\t\tspec_insn_lui_valid ? spec_insn_lui_trap :\n\t\tspec_insn_lw_valid ? spec_insn_lw_trap :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_trap :\n\t\tspec_insn_or_valid ? spec_insn_or_trap :\n\t\tspec_insn_ori_valid ? spec_insn_ori_trap :\n\t\tspec_insn_sb_valid ? spec_insn_sb_trap :\n\t\tspec_insn_sd_valid ? spec_insn_sd_trap :\n\t\tspec_insn_sh_valid ? spec_insn_sh_trap :\n\t\tspec_insn_sll_valid ? spec_insn_sll_trap :\n\t\tspec_insn_slli_valid ? spec_insn_slli_trap :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_trap :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_trap :\n\t\tspec_insn_slt_valid ? spec_insn_slt_trap :\n\t\tspec_insn_slti_valid ? spec_insn_slti_trap :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_trap :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_trap :\n\t\tspec_insn_sra_valid ? spec_insn_sra_trap :\n\t\tspec_insn_srai_valid ? spec_insn_srai_trap :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_trap :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_trap :\n\t\tspec_insn_srl_valid ? spec_insn_srl_trap :\n\t\tspec_insn_srli_valid ? spec_insn_srli_trap :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_trap :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_trap :\n\t\tspec_insn_sub_valid ? spec_insn_sub_trap :\n\t\tspec_insn_subw_valid ? spec_insn_subw_trap :\n\t\tspec_insn_sw_valid ? spec_insn_sw_trap :\n\t\tspec_insn_xor_valid ? spec_insn_xor_trap :\n\t\tspec_insn_xori_valid ? spec_insn_xori_trap : 0;\n  assign spec_rs1_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs1_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs1_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rs1_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rs1_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs1_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs1_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs1_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs1_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs1_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs1_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs1_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs1_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rs1_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rs1_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs1_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs1_addr :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_rs1_addr :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_rs1_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rs1_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rs1_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rs1_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rs1_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rs1_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rs1_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rs1_addr :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_rs1_addr :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rs1_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rs1_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rs1_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rs1_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs1_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rs1_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rs1_addr :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_rs1_addr :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rs1_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rs1_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rs1_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rs1_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rs1_addr :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_rs1_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rs1_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rs1_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rs1_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs1_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs1_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs1_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs1_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rs1_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs1_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs1_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs1_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs1_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rs1_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs1_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs1_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs1_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rs1_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs1_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs1_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs1_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rs1_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rs1_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs1_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs1_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs1_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs1_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs1_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rs1_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs1_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs1_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rs1_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rs1_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs1_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rs1_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs1_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs1_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0;\n  assign spec_rs2_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs2_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs2_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rs2_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rs2_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs2_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs2_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs2_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs2_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs2_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs2_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs2_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs2_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rs2_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rs2_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs2_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs2_addr :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_rs2_addr :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_rs2_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rs2_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rs2_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rs2_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rs2_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rs2_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rs2_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rs2_addr :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_rs2_addr :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rs2_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rs2_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rs2_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rs2_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs2_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rs2_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rs2_addr :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_rs2_addr :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rs2_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rs2_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rs2_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rs2_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rs2_addr :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_rs2_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rs2_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rs2_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rs2_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs2_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs2_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs2_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs2_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rs2_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs2_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs2_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs2_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs2_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rs2_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs2_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs2_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs2_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rs2_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs2_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs2_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs2_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rs2_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rs2_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs2_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs2_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs2_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs2_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs2_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rs2_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs2_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs2_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rs2_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rs2_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs2_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rs2_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs2_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs2_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0;\n  assign spec_rd_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rd_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rd_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rd_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rd_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_addr :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_rd_addr :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_rd_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rd_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rd_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rd_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rd_addr :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_rd_addr :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rd_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rd_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rd_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rd_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rd_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rd_addr :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_rd_addr :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rd_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rd_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rd_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rd_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rd_addr :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_rd_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rd_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rd_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rd_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rd_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rd_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rd_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rd_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rd_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rd_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rd_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rd_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_addr : 0;\n  assign spec_rd_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rd_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rd_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rd_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rd_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_wdata :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_rd_wdata :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_rd_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rd_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rd_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rd_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rd_wdata :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_rd_wdata :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rd_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rd_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rd_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rd_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rd_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rd_wdata :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_rd_wdata :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rd_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rd_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rd_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rd_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rd_wdata :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_rd_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rd_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rd_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rd_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rd_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rd_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rd_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rd_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rd_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rd_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rd_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rd_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0;\n  assign spec_pc_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_pc_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_pc_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_pc_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_pc_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_pc_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_pc_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_pc_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_pc_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_pc_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_pc_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_pc_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_pc_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_pc_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_pc_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_pc_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_pc_wdata :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_pc_wdata :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_pc_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_pc_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_pc_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_pc_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_pc_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_pc_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_pc_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_pc_wdata :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_pc_wdata :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_pc_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_pc_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_pc_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_pc_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_pc_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_pc_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_pc_wdata :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_pc_wdata :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_pc_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_pc_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_pc_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_pc_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_pc_wdata :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_pc_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_pc_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_pc_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_pc_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_pc_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_pc_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_pc_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_pc_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_pc_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_pc_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_pc_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_pc_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_pc_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_pc_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_pc_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_pc_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_pc_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_pc_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_pc_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_pc_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_pc_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_pc_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_pc_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_pc_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_pc_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_pc_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_pc_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_pc_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_pc_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_pc_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_pc_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_pc_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_pc_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_pc_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_pc_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_pc_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_pc_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0;\n  assign spec_mem_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_addr :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_addr :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_mem_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_addr :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_mem_addr :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_addr :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_mem_addr :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_addr :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_mem_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_addr : 0;\n  assign spec_mem_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_rmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_rmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_rmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_rmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_rmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_rmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_rmask :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_rmask :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_mem_rmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_rmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_rmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_rmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_rmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_rmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_rmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_rmask :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_mem_rmask :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_rmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_rmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_rmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_rmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_rmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_rmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_rmask :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_mem_rmask :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_rmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_rmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_rmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_rmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_rmask :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_mem_rmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_rmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_rmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_rmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_rmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_rmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_rmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_rmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_rmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_rmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_rmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_rmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0;\n  assign spec_mem_wmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_wmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_wmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_wmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_wmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wmask :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_wmask :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_mem_wmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_wmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_wmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_wmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_wmask :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_mem_wmask :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_wmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_wmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_wmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_wmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_wmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_wmask :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_mem_wmask :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_wmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_wmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_wmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_wmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_wmask :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_mem_wmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_wmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_wmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_wmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_wmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_wmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_wmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_wmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_wmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_wmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_wmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_wmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0;\n  assign spec_mem_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wdata :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_wdata :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_mem_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_wdata :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_mem_wdata :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_wdata :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_mem_wdata :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_wdata :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_mem_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0;\n`ifdef RISCV_FORMAL_CSR_MISA\n  assign spec_csr_misa_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_csr_misa_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_csr_misa_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_csr_misa_rmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_csr_misa_rmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_csr_misa_rmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_csr_misa_rmask :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_csr_misa_rmask :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_csr_misa_rmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_csr_misa_rmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_csr_misa_rmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_csr_misa_rmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_csr_misa_rmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_csr_misa_rmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_csr_misa_rmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_csr_misa_rmask :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_csr_misa_rmask :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_csr_misa_rmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_csr_misa_rmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_csr_misa_rmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_csr_misa_rmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_csr_misa_rmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_csr_misa_rmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_csr_misa_rmask :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_csr_misa_rmask :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_csr_misa_rmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_csr_misa_rmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_csr_misa_rmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_csr_misa_rmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_csr_misa_rmask :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_csr_misa_rmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_csr_misa_rmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_csr_misa_rmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_csr_misa_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_csr_misa_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0;\n`endif\nendmodule\n"
  },
  {
    "path": "insns/isa_rv64im.txt",
    "content": "add\naddi\naddiw\naddw\nand\nandi\nauipc\nbeq\nbge\nbgeu\nblt\nbltu\nbne\ndiv\ndivu\ndivuw\ndivw\njal\njalr\nlb\nlbu\nld\nlh\nlhu\nlui\nlw\nlwu\nmul\nmulh\nmulhsu\nmulhu\nmulw\nor\nori\nrem\nremu\nremuw\nremw\nsb\nsd\nsh\nsll\nslli\nslliw\nsllw\nslt\nslti\nsltiu\nsltu\nsra\nsrai\nsraiw\nsraw\nsrl\nsrli\nsrliw\nsrlw\nsub\nsubw\nsw\nxor\nxori\n"
  },
  {
    "path": "insns/isa_rv64im.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_isa_rv64im (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n  wire                                spec_insn_add_valid;\n  wire                                spec_insn_add_trap;\n  wire [                       4 : 0] spec_insn_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_add insn_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_add_valid),\n    .spec_trap(spec_insn_add_trap),\n    .spec_rs1_addr(spec_insn_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_add_rs2_addr),\n    .spec_rd_addr(spec_insn_add_rd_addr),\n    .spec_rd_wdata(spec_insn_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_add_pc_wdata),\n    .spec_mem_addr(spec_insn_add_mem_addr),\n    .spec_mem_rmask(spec_insn_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_add_mem_wdata)\n  );\n\n  wire                                spec_insn_addi_valid;\n  wire                                spec_insn_addi_trap;\n  wire [                       4 : 0] spec_insn_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addi insn_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addi_valid),\n    .spec_trap(spec_insn_addi_trap),\n    .spec_rs1_addr(spec_insn_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_addiw_valid;\n  wire                                spec_insn_addiw_trap;\n  wire [                       4 : 0] spec_insn_addiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_addiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_addiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addiw insn_addiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addiw_valid),\n    .spec_trap(spec_insn_addiw_trap),\n    .spec_rs1_addr(spec_insn_addiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_addiw_rs2_addr),\n    .spec_rd_addr(spec_insn_addiw_rd_addr),\n    .spec_rd_wdata(spec_insn_addiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_addiw_pc_wdata),\n    .spec_mem_addr(spec_insn_addiw_mem_addr),\n    .spec_mem_rmask(spec_insn_addiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_addiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_addiw_mem_wdata)\n  );\n\n  wire                                spec_insn_addw_valid;\n  wire                                spec_insn_addw_trap;\n  wire [                       4 : 0] spec_insn_addw_rs1_addr;\n  wire [                       4 : 0] spec_insn_addw_rs2_addr;\n  wire [                       4 : 0] spec_insn_addw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addw insn_addw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addw_valid),\n    .spec_trap(spec_insn_addw_trap),\n    .spec_rs1_addr(spec_insn_addw_rs1_addr),\n    .spec_rs2_addr(spec_insn_addw_rs2_addr),\n    .spec_rd_addr(spec_insn_addw_rd_addr),\n    .spec_rd_wdata(spec_insn_addw_rd_wdata),\n    .spec_pc_wdata(spec_insn_addw_pc_wdata),\n    .spec_mem_addr(spec_insn_addw_mem_addr),\n    .spec_mem_rmask(spec_insn_addw_mem_rmask),\n    .spec_mem_wmask(spec_insn_addw_mem_wmask),\n    .spec_mem_wdata(spec_insn_addw_mem_wdata)\n  );\n\n  wire                                spec_insn_and_valid;\n  wire                                spec_insn_and_trap;\n  wire [                       4 : 0] spec_insn_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_and insn_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_and_valid),\n    .spec_trap(spec_insn_and_trap),\n    .spec_rs1_addr(spec_insn_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_and_rs2_addr),\n    .spec_rd_addr(spec_insn_and_rd_addr),\n    .spec_rd_wdata(spec_insn_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_and_pc_wdata),\n    .spec_mem_addr(spec_insn_and_mem_addr),\n    .spec_mem_rmask(spec_insn_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_and_mem_wdata)\n  );\n\n  wire                                spec_insn_andi_valid;\n  wire                                spec_insn_andi_trap;\n  wire [                       4 : 0] spec_insn_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_andi insn_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_andi_valid),\n    .spec_trap(spec_insn_andi_trap),\n    .spec_rs1_addr(spec_insn_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_auipc_valid;\n  wire                                spec_insn_auipc_trap;\n  wire [                       4 : 0] spec_insn_auipc_rs1_addr;\n  wire [                       4 : 0] spec_insn_auipc_rs2_addr;\n  wire [                       4 : 0] spec_insn_auipc_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_csr_misa_rmask;\n`endif\n\n  rvfi_insn_auipc insn_auipc (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_auipc_valid),\n    .spec_trap(spec_insn_auipc_trap),\n    .spec_rs1_addr(spec_insn_auipc_rs1_addr),\n    .spec_rs2_addr(spec_insn_auipc_rs2_addr),\n    .spec_rd_addr(spec_insn_auipc_rd_addr),\n    .spec_rd_wdata(spec_insn_auipc_rd_wdata),\n    .spec_pc_wdata(spec_insn_auipc_pc_wdata),\n    .spec_mem_addr(spec_insn_auipc_mem_addr),\n    .spec_mem_rmask(spec_insn_auipc_mem_rmask),\n    .spec_mem_wmask(spec_insn_auipc_mem_wmask),\n    .spec_mem_wdata(spec_insn_auipc_mem_wdata)\n  );\n\n  wire                                spec_insn_beq_valid;\n  wire                                spec_insn_beq_trap;\n  wire [                       4 : 0] spec_insn_beq_rs1_addr;\n  wire [                       4 : 0] spec_insn_beq_rs2_addr;\n  wire [                       4 : 0] spec_insn_beq_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_csr_misa_rmask;\n`endif\n\n  rvfi_insn_beq insn_beq (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_beq_valid),\n    .spec_trap(spec_insn_beq_trap),\n    .spec_rs1_addr(spec_insn_beq_rs1_addr),\n    .spec_rs2_addr(spec_insn_beq_rs2_addr),\n    .spec_rd_addr(spec_insn_beq_rd_addr),\n    .spec_rd_wdata(spec_insn_beq_rd_wdata),\n    .spec_pc_wdata(spec_insn_beq_pc_wdata),\n    .spec_mem_addr(spec_insn_beq_mem_addr),\n    .spec_mem_rmask(spec_insn_beq_mem_rmask),\n    .spec_mem_wmask(spec_insn_beq_mem_wmask),\n    .spec_mem_wdata(spec_insn_beq_mem_wdata)\n  );\n\n  wire                                spec_insn_bge_valid;\n  wire                                spec_insn_bge_trap;\n  wire [                       4 : 0] spec_insn_bge_rs1_addr;\n  wire [                       4 : 0] spec_insn_bge_rs2_addr;\n  wire [                       4 : 0] spec_insn_bge_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bge insn_bge (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bge_valid),\n    .spec_trap(spec_insn_bge_trap),\n    .spec_rs1_addr(spec_insn_bge_rs1_addr),\n    .spec_rs2_addr(spec_insn_bge_rs2_addr),\n    .spec_rd_addr(spec_insn_bge_rd_addr),\n    .spec_rd_wdata(spec_insn_bge_rd_wdata),\n    .spec_pc_wdata(spec_insn_bge_pc_wdata),\n    .spec_mem_addr(spec_insn_bge_mem_addr),\n    .spec_mem_rmask(spec_insn_bge_mem_rmask),\n    .spec_mem_wmask(spec_insn_bge_mem_wmask),\n    .spec_mem_wdata(spec_insn_bge_mem_wdata)\n  );\n\n  wire                                spec_insn_bgeu_valid;\n  wire                                spec_insn_bgeu_trap;\n  wire [                       4 : 0] spec_insn_bgeu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bgeu insn_bgeu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bgeu_valid),\n    .spec_trap(spec_insn_bgeu_trap),\n    .spec_rs1_addr(spec_insn_bgeu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bgeu_rs2_addr),\n    .spec_rd_addr(spec_insn_bgeu_rd_addr),\n    .spec_rd_wdata(spec_insn_bgeu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bgeu_pc_wdata),\n    .spec_mem_addr(spec_insn_bgeu_mem_addr),\n    .spec_mem_rmask(spec_insn_bgeu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bgeu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bgeu_mem_wdata)\n  );\n\n  wire                                spec_insn_blt_valid;\n  wire                                spec_insn_blt_trap;\n  wire [                       4 : 0] spec_insn_blt_rs1_addr;\n  wire [                       4 : 0] spec_insn_blt_rs2_addr;\n  wire [                       4 : 0] spec_insn_blt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_blt insn_blt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_blt_valid),\n    .spec_trap(spec_insn_blt_trap),\n    .spec_rs1_addr(spec_insn_blt_rs1_addr),\n    .spec_rs2_addr(spec_insn_blt_rs2_addr),\n    .spec_rd_addr(spec_insn_blt_rd_addr),\n    .spec_rd_wdata(spec_insn_blt_rd_wdata),\n    .spec_pc_wdata(spec_insn_blt_pc_wdata),\n    .spec_mem_addr(spec_insn_blt_mem_addr),\n    .spec_mem_rmask(spec_insn_blt_mem_rmask),\n    .spec_mem_wmask(spec_insn_blt_mem_wmask),\n    .spec_mem_wdata(spec_insn_blt_mem_wdata)\n  );\n\n  wire                                spec_insn_bltu_valid;\n  wire                                spec_insn_bltu_trap;\n  wire [                       4 : 0] spec_insn_bltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bltu insn_bltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bltu_valid),\n    .spec_trap(spec_insn_bltu_trap),\n    .spec_rs1_addr(spec_insn_bltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bltu_rs2_addr),\n    .spec_rd_addr(spec_insn_bltu_rd_addr),\n    .spec_rd_wdata(spec_insn_bltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bltu_pc_wdata),\n    .spec_mem_addr(spec_insn_bltu_mem_addr),\n    .spec_mem_rmask(spec_insn_bltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bltu_mem_wdata)\n  );\n\n  wire                                spec_insn_bne_valid;\n  wire                                spec_insn_bne_trap;\n  wire [                       4 : 0] spec_insn_bne_rs1_addr;\n  wire [                       4 : 0] spec_insn_bne_rs2_addr;\n  wire [                       4 : 0] spec_insn_bne_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bne insn_bne (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bne_valid),\n    .spec_trap(spec_insn_bne_trap),\n    .spec_rs1_addr(spec_insn_bne_rs1_addr),\n    .spec_rs2_addr(spec_insn_bne_rs2_addr),\n    .spec_rd_addr(spec_insn_bne_rd_addr),\n    .spec_rd_wdata(spec_insn_bne_rd_wdata),\n    .spec_pc_wdata(spec_insn_bne_pc_wdata),\n    .spec_mem_addr(spec_insn_bne_mem_addr),\n    .spec_mem_rmask(spec_insn_bne_mem_rmask),\n    .spec_mem_wmask(spec_insn_bne_mem_wmask),\n    .spec_mem_wdata(spec_insn_bne_mem_wdata)\n  );\n\n  wire                                spec_insn_div_valid;\n  wire                                spec_insn_div_trap;\n  wire [                       4 : 0] spec_insn_div_rs1_addr;\n  wire [                       4 : 0] spec_insn_div_rs2_addr;\n  wire [                       4 : 0] spec_insn_div_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_csr_misa_rmask;\n`endif\n\n  rvfi_insn_div insn_div (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_div_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_div_valid),\n    .spec_trap(spec_insn_div_trap),\n    .spec_rs1_addr(spec_insn_div_rs1_addr),\n    .spec_rs2_addr(spec_insn_div_rs2_addr),\n    .spec_rd_addr(spec_insn_div_rd_addr),\n    .spec_rd_wdata(spec_insn_div_rd_wdata),\n    .spec_pc_wdata(spec_insn_div_pc_wdata),\n    .spec_mem_addr(spec_insn_div_mem_addr),\n    .spec_mem_rmask(spec_insn_div_mem_rmask),\n    .spec_mem_wmask(spec_insn_div_mem_wmask),\n    .spec_mem_wdata(spec_insn_div_mem_wdata)\n  );\n\n  wire                                spec_insn_divu_valid;\n  wire                                spec_insn_divu_trap;\n  wire [                       4 : 0] spec_insn_divu_rs1_addr;\n  wire [                       4 : 0] spec_insn_divu_rs2_addr;\n  wire [                       4 : 0] spec_insn_divu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_divu insn_divu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_divu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_divu_valid),\n    .spec_trap(spec_insn_divu_trap),\n    .spec_rs1_addr(spec_insn_divu_rs1_addr),\n    .spec_rs2_addr(spec_insn_divu_rs2_addr),\n    .spec_rd_addr(spec_insn_divu_rd_addr),\n    .spec_rd_wdata(spec_insn_divu_rd_wdata),\n    .spec_pc_wdata(spec_insn_divu_pc_wdata),\n    .spec_mem_addr(spec_insn_divu_mem_addr),\n    .spec_mem_rmask(spec_insn_divu_mem_rmask),\n    .spec_mem_wmask(spec_insn_divu_mem_wmask),\n    .spec_mem_wdata(spec_insn_divu_mem_wdata)\n  );\n\n  wire                                spec_insn_divuw_valid;\n  wire                                spec_insn_divuw_trap;\n  wire [                       4 : 0] spec_insn_divuw_rs1_addr;\n  wire [                       4 : 0] spec_insn_divuw_rs2_addr;\n  wire [                       4 : 0] spec_insn_divuw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divuw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divuw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_divuw insn_divuw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_divuw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_divuw_valid),\n    .spec_trap(spec_insn_divuw_trap),\n    .spec_rs1_addr(spec_insn_divuw_rs1_addr),\n    .spec_rs2_addr(spec_insn_divuw_rs2_addr),\n    .spec_rd_addr(spec_insn_divuw_rd_addr),\n    .spec_rd_wdata(spec_insn_divuw_rd_wdata),\n    .spec_pc_wdata(spec_insn_divuw_pc_wdata),\n    .spec_mem_addr(spec_insn_divuw_mem_addr),\n    .spec_mem_rmask(spec_insn_divuw_mem_rmask),\n    .spec_mem_wmask(spec_insn_divuw_mem_wmask),\n    .spec_mem_wdata(spec_insn_divuw_mem_wdata)\n  );\n\n  wire                                spec_insn_divw_valid;\n  wire                                spec_insn_divw_trap;\n  wire [                       4 : 0] spec_insn_divw_rs1_addr;\n  wire [                       4 : 0] spec_insn_divw_rs2_addr;\n  wire [                       4 : 0] spec_insn_divw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_divw insn_divw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_divw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_divw_valid),\n    .spec_trap(spec_insn_divw_trap),\n    .spec_rs1_addr(spec_insn_divw_rs1_addr),\n    .spec_rs2_addr(spec_insn_divw_rs2_addr),\n    .spec_rd_addr(spec_insn_divw_rd_addr),\n    .spec_rd_wdata(spec_insn_divw_rd_wdata),\n    .spec_pc_wdata(spec_insn_divw_pc_wdata),\n    .spec_mem_addr(spec_insn_divw_mem_addr),\n    .spec_mem_rmask(spec_insn_divw_mem_rmask),\n    .spec_mem_wmask(spec_insn_divw_mem_wmask),\n    .spec_mem_wdata(spec_insn_divw_mem_wdata)\n  );\n\n  wire                                spec_insn_jal_valid;\n  wire                                spec_insn_jal_trap;\n  wire [                       4 : 0] spec_insn_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jal insn_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jal_valid),\n    .spec_trap(spec_insn_jal_trap),\n    .spec_rs1_addr(spec_insn_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_jalr_valid;\n  wire                                spec_insn_jalr_trap;\n  wire [                       4 : 0] spec_insn_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jalr insn_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jalr_valid),\n    .spec_trap(spec_insn_jalr_trap),\n    .spec_rs1_addr(spec_insn_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_lb_valid;\n  wire                                spec_insn_lb_trap;\n  wire [                       4 : 0] spec_insn_lb_rs1_addr;\n  wire [                       4 : 0] spec_insn_lb_rs2_addr;\n  wire [                       4 : 0] spec_insn_lb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lb insn_lb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lb_valid),\n    .spec_trap(spec_insn_lb_trap),\n    .spec_rs1_addr(spec_insn_lb_rs1_addr),\n    .spec_rs2_addr(spec_insn_lb_rs2_addr),\n    .spec_rd_addr(spec_insn_lb_rd_addr),\n    .spec_rd_wdata(spec_insn_lb_rd_wdata),\n    .spec_pc_wdata(spec_insn_lb_pc_wdata),\n    .spec_mem_addr(spec_insn_lb_mem_addr),\n    .spec_mem_rmask(spec_insn_lb_mem_rmask),\n    .spec_mem_wmask(spec_insn_lb_mem_wmask),\n    .spec_mem_wdata(spec_insn_lb_mem_wdata)\n  );\n\n  wire                                spec_insn_lbu_valid;\n  wire                                spec_insn_lbu_trap;\n  wire [                       4 : 0] spec_insn_lbu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lbu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lbu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lbu insn_lbu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lbu_valid),\n    .spec_trap(spec_insn_lbu_trap),\n    .spec_rs1_addr(spec_insn_lbu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lbu_rs2_addr),\n    .spec_rd_addr(spec_insn_lbu_rd_addr),\n    .spec_rd_wdata(spec_insn_lbu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lbu_pc_wdata),\n    .spec_mem_addr(spec_insn_lbu_mem_addr),\n    .spec_mem_rmask(spec_insn_lbu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lbu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lbu_mem_wdata)\n  );\n\n  wire                                spec_insn_ld_valid;\n  wire                                spec_insn_ld_trap;\n  wire [                       4 : 0] spec_insn_ld_rs1_addr;\n  wire [                       4 : 0] spec_insn_ld_rs2_addr;\n  wire [                       4 : 0] spec_insn_ld_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ld insn_ld (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ld_valid),\n    .spec_trap(spec_insn_ld_trap),\n    .spec_rs1_addr(spec_insn_ld_rs1_addr),\n    .spec_rs2_addr(spec_insn_ld_rs2_addr),\n    .spec_rd_addr(spec_insn_ld_rd_addr),\n    .spec_rd_wdata(spec_insn_ld_rd_wdata),\n    .spec_pc_wdata(spec_insn_ld_pc_wdata),\n    .spec_mem_addr(spec_insn_ld_mem_addr),\n    .spec_mem_rmask(spec_insn_ld_mem_rmask),\n    .spec_mem_wmask(spec_insn_ld_mem_wmask),\n    .spec_mem_wdata(spec_insn_ld_mem_wdata)\n  );\n\n  wire                                spec_insn_lh_valid;\n  wire                                spec_insn_lh_trap;\n  wire [                       4 : 0] spec_insn_lh_rs1_addr;\n  wire [                       4 : 0] spec_insn_lh_rs2_addr;\n  wire [                       4 : 0] spec_insn_lh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lh insn_lh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lh_valid),\n    .spec_trap(spec_insn_lh_trap),\n    .spec_rs1_addr(spec_insn_lh_rs1_addr),\n    .spec_rs2_addr(spec_insn_lh_rs2_addr),\n    .spec_rd_addr(spec_insn_lh_rd_addr),\n    .spec_rd_wdata(spec_insn_lh_rd_wdata),\n    .spec_pc_wdata(spec_insn_lh_pc_wdata),\n    .spec_mem_addr(spec_insn_lh_mem_addr),\n    .spec_mem_rmask(spec_insn_lh_mem_rmask),\n    .spec_mem_wmask(spec_insn_lh_mem_wmask),\n    .spec_mem_wdata(spec_insn_lh_mem_wdata)\n  );\n\n  wire                                spec_insn_lhu_valid;\n  wire                                spec_insn_lhu_trap;\n  wire [                       4 : 0] spec_insn_lhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lhu insn_lhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lhu_valid),\n    .spec_trap(spec_insn_lhu_trap),\n    .spec_rs1_addr(spec_insn_lhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lhu_rs2_addr),\n    .spec_rd_addr(spec_insn_lhu_rd_addr),\n    .spec_rd_wdata(spec_insn_lhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lhu_pc_wdata),\n    .spec_mem_addr(spec_insn_lhu_mem_addr),\n    .spec_mem_rmask(spec_insn_lhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lhu_mem_wdata)\n  );\n\n  wire                                spec_insn_lui_valid;\n  wire                                spec_insn_lui_trap;\n  wire [                       4 : 0] spec_insn_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lui insn_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lui_valid),\n    .spec_trap(spec_insn_lui_trap),\n    .spec_rs1_addr(spec_insn_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_lw_valid;\n  wire                                spec_insn_lw_trap;\n  wire [                       4 : 0] spec_insn_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lw insn_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lw_valid),\n    .spec_trap(spec_insn_lw_trap),\n    .spec_rs1_addr(spec_insn_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_lwu_valid;\n  wire                                spec_insn_lwu_trap;\n  wire [                       4 : 0] spec_insn_lwu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lwu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lwu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lwu insn_lwu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lwu_valid),\n    .spec_trap(spec_insn_lwu_trap),\n    .spec_rs1_addr(spec_insn_lwu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lwu_rs2_addr),\n    .spec_rd_addr(spec_insn_lwu_rd_addr),\n    .spec_rd_wdata(spec_insn_lwu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lwu_pc_wdata),\n    .spec_mem_addr(spec_insn_lwu_mem_addr),\n    .spec_mem_rmask(spec_insn_lwu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lwu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lwu_mem_wdata)\n  );\n\n  wire                                spec_insn_mul_valid;\n  wire                                spec_insn_mul_trap;\n  wire [                       4 : 0] spec_insn_mul_rs1_addr;\n  wire [                       4 : 0] spec_insn_mul_rs2_addr;\n  wire [                       4 : 0] spec_insn_mul_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mul insn_mul (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mul_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mul_valid),\n    .spec_trap(spec_insn_mul_trap),\n    .spec_rs1_addr(spec_insn_mul_rs1_addr),\n    .spec_rs2_addr(spec_insn_mul_rs2_addr),\n    .spec_rd_addr(spec_insn_mul_rd_addr),\n    .spec_rd_wdata(spec_insn_mul_rd_wdata),\n    .spec_pc_wdata(spec_insn_mul_pc_wdata),\n    .spec_mem_addr(spec_insn_mul_mem_addr),\n    .spec_mem_rmask(spec_insn_mul_mem_rmask),\n    .spec_mem_wmask(spec_insn_mul_mem_wmask),\n    .spec_mem_wdata(spec_insn_mul_mem_wdata)\n  );\n\n  wire                                spec_insn_mulh_valid;\n  wire                                spec_insn_mulh_trap;\n  wire [                       4 : 0] spec_insn_mulh_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulh_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulh insn_mulh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulh_valid),\n    .spec_trap(spec_insn_mulh_trap),\n    .spec_rs1_addr(spec_insn_mulh_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulh_rs2_addr),\n    .spec_rd_addr(spec_insn_mulh_rd_addr),\n    .spec_rd_wdata(spec_insn_mulh_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulh_pc_wdata),\n    .spec_mem_addr(spec_insn_mulh_mem_addr),\n    .spec_mem_rmask(spec_insn_mulh_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulh_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulh_mem_wdata)\n  );\n\n  wire                                spec_insn_mulhsu_valid;\n  wire                                spec_insn_mulhsu_trap;\n  wire [                       4 : 0] spec_insn_mulhsu_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulhsu_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulhsu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulhsu insn_mulhsu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulhsu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulhsu_valid),\n    .spec_trap(spec_insn_mulhsu_trap),\n    .spec_rs1_addr(spec_insn_mulhsu_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulhsu_rs2_addr),\n    .spec_rd_addr(spec_insn_mulhsu_rd_addr),\n    .spec_rd_wdata(spec_insn_mulhsu_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulhsu_pc_wdata),\n    .spec_mem_addr(spec_insn_mulhsu_mem_addr),\n    .spec_mem_rmask(spec_insn_mulhsu_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulhsu_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulhsu_mem_wdata)\n  );\n\n  wire                                spec_insn_mulhu_valid;\n  wire                                spec_insn_mulhu_trap;\n  wire [                       4 : 0] spec_insn_mulhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulhu insn_mulhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulhu_valid),\n    .spec_trap(spec_insn_mulhu_trap),\n    .spec_rs1_addr(spec_insn_mulhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulhu_rs2_addr),\n    .spec_rd_addr(spec_insn_mulhu_rd_addr),\n    .spec_rd_wdata(spec_insn_mulhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulhu_pc_wdata),\n    .spec_mem_addr(spec_insn_mulhu_mem_addr),\n    .spec_mem_rmask(spec_insn_mulhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulhu_mem_wdata)\n  );\n\n  wire                                spec_insn_mulw_valid;\n  wire                                spec_insn_mulw_trap;\n  wire [                       4 : 0] spec_insn_mulw_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulw_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulw insn_mulw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulw_valid),\n    .spec_trap(spec_insn_mulw_trap),\n    .spec_rs1_addr(spec_insn_mulw_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulw_rs2_addr),\n    .spec_rd_addr(spec_insn_mulw_rd_addr),\n    .spec_rd_wdata(spec_insn_mulw_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulw_pc_wdata),\n    .spec_mem_addr(spec_insn_mulw_mem_addr),\n    .spec_mem_rmask(spec_insn_mulw_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulw_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulw_mem_wdata)\n  );\n\n  wire                                spec_insn_or_valid;\n  wire                                spec_insn_or_trap;\n  wire [                       4 : 0] spec_insn_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_or insn_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_or_valid),\n    .spec_trap(spec_insn_or_trap),\n    .spec_rs1_addr(spec_insn_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_or_rs2_addr),\n    .spec_rd_addr(spec_insn_or_rd_addr),\n    .spec_rd_wdata(spec_insn_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_or_pc_wdata),\n    .spec_mem_addr(spec_insn_or_mem_addr),\n    .spec_mem_rmask(spec_insn_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_or_mem_wdata)\n  );\n\n  wire                                spec_insn_ori_valid;\n  wire                                spec_insn_ori_trap;\n  wire [                       4 : 0] spec_insn_ori_rs1_addr;\n  wire [                       4 : 0] spec_insn_ori_rs2_addr;\n  wire [                       4 : 0] spec_insn_ori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ori insn_ori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ori_valid),\n    .spec_trap(spec_insn_ori_trap),\n    .spec_rs1_addr(spec_insn_ori_rs1_addr),\n    .spec_rs2_addr(spec_insn_ori_rs2_addr),\n    .spec_rd_addr(spec_insn_ori_rd_addr),\n    .spec_rd_wdata(spec_insn_ori_rd_wdata),\n    .spec_pc_wdata(spec_insn_ori_pc_wdata),\n    .spec_mem_addr(spec_insn_ori_mem_addr),\n    .spec_mem_rmask(spec_insn_ori_mem_rmask),\n    .spec_mem_wmask(spec_insn_ori_mem_wmask),\n    .spec_mem_wdata(spec_insn_ori_mem_wdata)\n  );\n\n  wire                                spec_insn_rem_valid;\n  wire                                spec_insn_rem_trap;\n  wire [                       4 : 0] spec_insn_rem_rs1_addr;\n  wire [                       4 : 0] spec_insn_rem_rs2_addr;\n  wire [                       4 : 0] spec_insn_rem_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_csr_misa_rmask;\n`endif\n\n  rvfi_insn_rem insn_rem (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_rem_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_rem_valid),\n    .spec_trap(spec_insn_rem_trap),\n    .spec_rs1_addr(spec_insn_rem_rs1_addr),\n    .spec_rs2_addr(spec_insn_rem_rs2_addr),\n    .spec_rd_addr(spec_insn_rem_rd_addr),\n    .spec_rd_wdata(spec_insn_rem_rd_wdata),\n    .spec_pc_wdata(spec_insn_rem_pc_wdata),\n    .spec_mem_addr(spec_insn_rem_mem_addr),\n    .spec_mem_rmask(spec_insn_rem_mem_rmask),\n    .spec_mem_wmask(spec_insn_rem_mem_wmask),\n    .spec_mem_wdata(spec_insn_rem_mem_wdata)\n  );\n\n  wire                                spec_insn_remu_valid;\n  wire                                spec_insn_remu_trap;\n  wire [                       4 : 0] spec_insn_remu_rs1_addr;\n  wire [                       4 : 0] spec_insn_remu_rs2_addr;\n  wire [                       4 : 0] spec_insn_remu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_remu insn_remu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_remu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_remu_valid),\n    .spec_trap(spec_insn_remu_trap),\n    .spec_rs1_addr(spec_insn_remu_rs1_addr),\n    .spec_rs2_addr(spec_insn_remu_rs2_addr),\n    .spec_rd_addr(spec_insn_remu_rd_addr),\n    .spec_rd_wdata(spec_insn_remu_rd_wdata),\n    .spec_pc_wdata(spec_insn_remu_pc_wdata),\n    .spec_mem_addr(spec_insn_remu_mem_addr),\n    .spec_mem_rmask(spec_insn_remu_mem_rmask),\n    .spec_mem_wmask(spec_insn_remu_mem_wmask),\n    .spec_mem_wdata(spec_insn_remu_mem_wdata)\n  );\n\n  wire                                spec_insn_remuw_valid;\n  wire                                spec_insn_remuw_trap;\n  wire [                       4 : 0] spec_insn_remuw_rs1_addr;\n  wire [                       4 : 0] spec_insn_remuw_rs2_addr;\n  wire [                       4 : 0] spec_insn_remuw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remuw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remuw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_remuw insn_remuw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_remuw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_remuw_valid),\n    .spec_trap(spec_insn_remuw_trap),\n    .spec_rs1_addr(spec_insn_remuw_rs1_addr),\n    .spec_rs2_addr(spec_insn_remuw_rs2_addr),\n    .spec_rd_addr(spec_insn_remuw_rd_addr),\n    .spec_rd_wdata(spec_insn_remuw_rd_wdata),\n    .spec_pc_wdata(spec_insn_remuw_pc_wdata),\n    .spec_mem_addr(spec_insn_remuw_mem_addr),\n    .spec_mem_rmask(spec_insn_remuw_mem_rmask),\n    .spec_mem_wmask(spec_insn_remuw_mem_wmask),\n    .spec_mem_wdata(spec_insn_remuw_mem_wdata)\n  );\n\n  wire                                spec_insn_remw_valid;\n  wire                                spec_insn_remw_trap;\n  wire [                       4 : 0] spec_insn_remw_rs1_addr;\n  wire [                       4 : 0] spec_insn_remw_rs2_addr;\n  wire [                       4 : 0] spec_insn_remw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_remw insn_remw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_remw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_remw_valid),\n    .spec_trap(spec_insn_remw_trap),\n    .spec_rs1_addr(spec_insn_remw_rs1_addr),\n    .spec_rs2_addr(spec_insn_remw_rs2_addr),\n    .spec_rd_addr(spec_insn_remw_rd_addr),\n    .spec_rd_wdata(spec_insn_remw_rd_wdata),\n    .spec_pc_wdata(spec_insn_remw_pc_wdata),\n    .spec_mem_addr(spec_insn_remw_mem_addr),\n    .spec_mem_rmask(spec_insn_remw_mem_rmask),\n    .spec_mem_wmask(spec_insn_remw_mem_wmask),\n    .spec_mem_wdata(spec_insn_remw_mem_wdata)\n  );\n\n  wire                                spec_insn_sb_valid;\n  wire                                spec_insn_sb_trap;\n  wire [                       4 : 0] spec_insn_sb_rs1_addr;\n  wire [                       4 : 0] spec_insn_sb_rs2_addr;\n  wire [                       4 : 0] spec_insn_sb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sb insn_sb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sb_valid),\n    .spec_trap(spec_insn_sb_trap),\n    .spec_rs1_addr(spec_insn_sb_rs1_addr),\n    .spec_rs2_addr(spec_insn_sb_rs2_addr),\n    .spec_rd_addr(spec_insn_sb_rd_addr),\n    .spec_rd_wdata(spec_insn_sb_rd_wdata),\n    .spec_pc_wdata(spec_insn_sb_pc_wdata),\n    .spec_mem_addr(spec_insn_sb_mem_addr),\n    .spec_mem_rmask(spec_insn_sb_mem_rmask),\n    .spec_mem_wmask(spec_insn_sb_mem_wmask),\n    .spec_mem_wdata(spec_insn_sb_mem_wdata)\n  );\n\n  wire                                spec_insn_sd_valid;\n  wire                                spec_insn_sd_trap;\n  wire [                       4 : 0] spec_insn_sd_rs1_addr;\n  wire [                       4 : 0] spec_insn_sd_rs2_addr;\n  wire [                       4 : 0] spec_insn_sd_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sd insn_sd (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sd_valid),\n    .spec_trap(spec_insn_sd_trap),\n    .spec_rs1_addr(spec_insn_sd_rs1_addr),\n    .spec_rs2_addr(spec_insn_sd_rs2_addr),\n    .spec_rd_addr(spec_insn_sd_rd_addr),\n    .spec_rd_wdata(spec_insn_sd_rd_wdata),\n    .spec_pc_wdata(spec_insn_sd_pc_wdata),\n    .spec_mem_addr(spec_insn_sd_mem_addr),\n    .spec_mem_rmask(spec_insn_sd_mem_rmask),\n    .spec_mem_wmask(spec_insn_sd_mem_wmask),\n    .spec_mem_wdata(spec_insn_sd_mem_wdata)\n  );\n\n  wire                                spec_insn_sh_valid;\n  wire                                spec_insn_sh_trap;\n  wire [                       4 : 0] spec_insn_sh_rs1_addr;\n  wire [                       4 : 0] spec_insn_sh_rs2_addr;\n  wire [                       4 : 0] spec_insn_sh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sh insn_sh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sh_valid),\n    .spec_trap(spec_insn_sh_trap),\n    .spec_rs1_addr(spec_insn_sh_rs1_addr),\n    .spec_rs2_addr(spec_insn_sh_rs2_addr),\n    .spec_rd_addr(spec_insn_sh_rd_addr),\n    .spec_rd_wdata(spec_insn_sh_rd_wdata),\n    .spec_pc_wdata(spec_insn_sh_pc_wdata),\n    .spec_mem_addr(spec_insn_sh_mem_addr),\n    .spec_mem_rmask(spec_insn_sh_mem_rmask),\n    .spec_mem_wmask(spec_insn_sh_mem_wmask),\n    .spec_mem_wdata(spec_insn_sh_mem_wdata)\n  );\n\n  wire                                spec_insn_sll_valid;\n  wire                                spec_insn_sll_trap;\n  wire [                       4 : 0] spec_insn_sll_rs1_addr;\n  wire [                       4 : 0] spec_insn_sll_rs2_addr;\n  wire [                       4 : 0] spec_insn_sll_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sll insn_sll (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sll_valid),\n    .spec_trap(spec_insn_sll_trap),\n    .spec_rs1_addr(spec_insn_sll_rs1_addr),\n    .spec_rs2_addr(spec_insn_sll_rs2_addr),\n    .spec_rd_addr(spec_insn_sll_rd_addr),\n    .spec_rd_wdata(spec_insn_sll_rd_wdata),\n    .spec_pc_wdata(spec_insn_sll_pc_wdata),\n    .spec_mem_addr(spec_insn_sll_mem_addr),\n    .spec_mem_rmask(spec_insn_sll_mem_rmask),\n    .spec_mem_wmask(spec_insn_sll_mem_wmask),\n    .spec_mem_wdata(spec_insn_sll_mem_wdata)\n  );\n\n  wire                                spec_insn_slli_valid;\n  wire                                spec_insn_slli_trap;\n  wire [                       4 : 0] spec_insn_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slli insn_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slli_valid),\n    .spec_trap(spec_insn_slli_trap),\n    .spec_rs1_addr(spec_insn_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_slliw_valid;\n  wire                                spec_insn_slliw_trap;\n  wire [                       4 : 0] spec_insn_slliw_rs1_addr;\n  wire [                       4 : 0] spec_insn_slliw_rs2_addr;\n  wire [                       4 : 0] spec_insn_slliw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slliw insn_slliw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slliw_valid),\n    .spec_trap(spec_insn_slliw_trap),\n    .spec_rs1_addr(spec_insn_slliw_rs1_addr),\n    .spec_rs2_addr(spec_insn_slliw_rs2_addr),\n    .spec_rd_addr(spec_insn_slliw_rd_addr),\n    .spec_rd_wdata(spec_insn_slliw_rd_wdata),\n    .spec_pc_wdata(spec_insn_slliw_pc_wdata),\n    .spec_mem_addr(spec_insn_slliw_mem_addr),\n    .spec_mem_rmask(spec_insn_slliw_mem_rmask),\n    .spec_mem_wmask(spec_insn_slliw_mem_wmask),\n    .spec_mem_wdata(spec_insn_slliw_mem_wdata)\n  );\n\n  wire                                spec_insn_sllw_valid;\n  wire                                spec_insn_sllw_trap;\n  wire [                       4 : 0] spec_insn_sllw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sllw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sllw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sllw insn_sllw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sllw_valid),\n    .spec_trap(spec_insn_sllw_trap),\n    .spec_rs1_addr(spec_insn_sllw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sllw_rs2_addr),\n    .spec_rd_addr(spec_insn_sllw_rd_addr),\n    .spec_rd_wdata(spec_insn_sllw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sllw_pc_wdata),\n    .spec_mem_addr(spec_insn_sllw_mem_addr),\n    .spec_mem_rmask(spec_insn_sllw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sllw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sllw_mem_wdata)\n  );\n\n  wire                                spec_insn_slt_valid;\n  wire                                spec_insn_slt_trap;\n  wire [                       4 : 0] spec_insn_slt_rs1_addr;\n  wire [                       4 : 0] spec_insn_slt_rs2_addr;\n  wire [                       4 : 0] spec_insn_slt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slt insn_slt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slt_valid),\n    .spec_trap(spec_insn_slt_trap),\n    .spec_rs1_addr(spec_insn_slt_rs1_addr),\n    .spec_rs2_addr(spec_insn_slt_rs2_addr),\n    .spec_rd_addr(spec_insn_slt_rd_addr),\n    .spec_rd_wdata(spec_insn_slt_rd_wdata),\n    .spec_pc_wdata(spec_insn_slt_pc_wdata),\n    .spec_mem_addr(spec_insn_slt_mem_addr),\n    .spec_mem_rmask(spec_insn_slt_mem_rmask),\n    .spec_mem_wmask(spec_insn_slt_mem_wmask),\n    .spec_mem_wdata(spec_insn_slt_mem_wdata)\n  );\n\n  wire                                spec_insn_slti_valid;\n  wire                                spec_insn_slti_trap;\n  wire [                       4 : 0] spec_insn_slti_rs1_addr;\n  wire [                       4 : 0] spec_insn_slti_rs2_addr;\n  wire [                       4 : 0] spec_insn_slti_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slti insn_slti (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slti_valid),\n    .spec_trap(spec_insn_slti_trap),\n    .spec_rs1_addr(spec_insn_slti_rs1_addr),\n    .spec_rs2_addr(spec_insn_slti_rs2_addr),\n    .spec_rd_addr(spec_insn_slti_rd_addr),\n    .spec_rd_wdata(spec_insn_slti_rd_wdata),\n    .spec_pc_wdata(spec_insn_slti_pc_wdata),\n    .spec_mem_addr(spec_insn_slti_mem_addr),\n    .spec_mem_rmask(spec_insn_slti_mem_rmask),\n    .spec_mem_wmask(spec_insn_slti_mem_wmask),\n    .spec_mem_wdata(spec_insn_slti_mem_wdata)\n  );\n\n  wire                                spec_insn_sltiu_valid;\n  wire                                spec_insn_sltiu_trap;\n  wire [                       4 : 0] spec_insn_sltiu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltiu insn_sltiu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltiu_valid),\n    .spec_trap(spec_insn_sltiu_trap),\n    .spec_rs1_addr(spec_insn_sltiu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltiu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltiu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltiu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltiu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltiu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltiu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltiu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltiu_mem_wdata)\n  );\n\n  wire                                spec_insn_sltu_valid;\n  wire                                spec_insn_sltu_trap;\n  wire [                       4 : 0] spec_insn_sltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltu insn_sltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltu_valid),\n    .spec_trap(spec_insn_sltu_trap),\n    .spec_rs1_addr(spec_insn_sltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltu_mem_wdata)\n  );\n\n  wire                                spec_insn_sra_valid;\n  wire                                spec_insn_sra_trap;\n  wire [                       4 : 0] spec_insn_sra_rs1_addr;\n  wire [                       4 : 0] spec_insn_sra_rs2_addr;\n  wire [                       4 : 0] spec_insn_sra_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sra insn_sra (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sra_valid),\n    .spec_trap(spec_insn_sra_trap),\n    .spec_rs1_addr(spec_insn_sra_rs1_addr),\n    .spec_rs2_addr(spec_insn_sra_rs2_addr),\n    .spec_rd_addr(spec_insn_sra_rd_addr),\n    .spec_rd_wdata(spec_insn_sra_rd_wdata),\n    .spec_pc_wdata(spec_insn_sra_pc_wdata),\n    .spec_mem_addr(spec_insn_sra_mem_addr),\n    .spec_mem_rmask(spec_insn_sra_mem_rmask),\n    .spec_mem_wmask(spec_insn_sra_mem_wmask),\n    .spec_mem_wdata(spec_insn_sra_mem_wdata)\n  );\n\n  wire                                spec_insn_srai_valid;\n  wire                                spec_insn_srai_trap;\n  wire [                       4 : 0] spec_insn_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srai insn_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srai_valid),\n    .spec_trap(spec_insn_srai_trap),\n    .spec_rs1_addr(spec_insn_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_sraiw_valid;\n  wire                                spec_insn_sraiw_trap;\n  wire [                       4 : 0] spec_insn_sraiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sraiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sraiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sraiw insn_sraiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sraiw_valid),\n    .spec_trap(spec_insn_sraiw_trap),\n    .spec_rs1_addr(spec_insn_sraiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sraiw_rs2_addr),\n    .spec_rd_addr(spec_insn_sraiw_rd_addr),\n    .spec_rd_wdata(spec_insn_sraiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sraiw_pc_wdata),\n    .spec_mem_addr(spec_insn_sraiw_mem_addr),\n    .spec_mem_rmask(spec_insn_sraiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sraiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sraiw_mem_wdata)\n  );\n\n  wire                                spec_insn_sraw_valid;\n  wire                                spec_insn_sraw_trap;\n  wire [                       4 : 0] spec_insn_sraw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sraw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sraw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sraw insn_sraw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sraw_valid),\n    .spec_trap(spec_insn_sraw_trap),\n    .spec_rs1_addr(spec_insn_sraw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sraw_rs2_addr),\n    .spec_rd_addr(spec_insn_sraw_rd_addr),\n    .spec_rd_wdata(spec_insn_sraw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sraw_pc_wdata),\n    .spec_mem_addr(spec_insn_sraw_mem_addr),\n    .spec_mem_rmask(spec_insn_sraw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sraw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sraw_mem_wdata)\n  );\n\n  wire                                spec_insn_srl_valid;\n  wire                                spec_insn_srl_trap;\n  wire [                       4 : 0] spec_insn_srl_rs1_addr;\n  wire [                       4 : 0] spec_insn_srl_rs2_addr;\n  wire [                       4 : 0] spec_insn_srl_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srl insn_srl (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srl_valid),\n    .spec_trap(spec_insn_srl_trap),\n    .spec_rs1_addr(spec_insn_srl_rs1_addr),\n    .spec_rs2_addr(spec_insn_srl_rs2_addr),\n    .spec_rd_addr(spec_insn_srl_rd_addr),\n    .spec_rd_wdata(spec_insn_srl_rd_wdata),\n    .spec_pc_wdata(spec_insn_srl_pc_wdata),\n    .spec_mem_addr(spec_insn_srl_mem_addr),\n    .spec_mem_rmask(spec_insn_srl_mem_rmask),\n    .spec_mem_wmask(spec_insn_srl_mem_wmask),\n    .spec_mem_wdata(spec_insn_srl_mem_wdata)\n  );\n\n  wire                                spec_insn_srli_valid;\n  wire                                spec_insn_srli_trap;\n  wire [                       4 : 0] spec_insn_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srli insn_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srli_valid),\n    .spec_trap(spec_insn_srli_trap),\n    .spec_rs1_addr(spec_insn_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_srliw_valid;\n  wire                                spec_insn_srliw_trap;\n  wire [                       4 : 0] spec_insn_srliw_rs1_addr;\n  wire [                       4 : 0] spec_insn_srliw_rs2_addr;\n  wire [                       4 : 0] spec_insn_srliw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srliw insn_srliw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srliw_valid),\n    .spec_trap(spec_insn_srliw_trap),\n    .spec_rs1_addr(spec_insn_srliw_rs1_addr),\n    .spec_rs2_addr(spec_insn_srliw_rs2_addr),\n    .spec_rd_addr(spec_insn_srliw_rd_addr),\n    .spec_rd_wdata(spec_insn_srliw_rd_wdata),\n    .spec_pc_wdata(spec_insn_srliw_pc_wdata),\n    .spec_mem_addr(spec_insn_srliw_mem_addr),\n    .spec_mem_rmask(spec_insn_srliw_mem_rmask),\n    .spec_mem_wmask(spec_insn_srliw_mem_wmask),\n    .spec_mem_wdata(spec_insn_srliw_mem_wdata)\n  );\n\n  wire                                spec_insn_srlw_valid;\n  wire                                spec_insn_srlw_trap;\n  wire [                       4 : 0] spec_insn_srlw_rs1_addr;\n  wire [                       4 : 0] spec_insn_srlw_rs2_addr;\n  wire [                       4 : 0] spec_insn_srlw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srlw insn_srlw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srlw_valid),\n    .spec_trap(spec_insn_srlw_trap),\n    .spec_rs1_addr(spec_insn_srlw_rs1_addr),\n    .spec_rs2_addr(spec_insn_srlw_rs2_addr),\n    .spec_rd_addr(spec_insn_srlw_rd_addr),\n    .spec_rd_wdata(spec_insn_srlw_rd_wdata),\n    .spec_pc_wdata(spec_insn_srlw_pc_wdata),\n    .spec_mem_addr(spec_insn_srlw_mem_addr),\n    .spec_mem_rmask(spec_insn_srlw_mem_rmask),\n    .spec_mem_wmask(spec_insn_srlw_mem_wmask),\n    .spec_mem_wdata(spec_insn_srlw_mem_wdata)\n  );\n\n  wire                                spec_insn_sub_valid;\n  wire                                spec_insn_sub_trap;\n  wire [                       4 : 0] spec_insn_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sub insn_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sub_valid),\n    .spec_trap(spec_insn_sub_trap),\n    .spec_rs1_addr(spec_insn_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_subw_valid;\n  wire                                spec_insn_subw_trap;\n  wire [                       4 : 0] spec_insn_subw_rs1_addr;\n  wire [                       4 : 0] spec_insn_subw_rs2_addr;\n  wire [                       4 : 0] spec_insn_subw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_subw insn_subw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_subw_valid),\n    .spec_trap(spec_insn_subw_trap),\n    .spec_rs1_addr(spec_insn_subw_rs1_addr),\n    .spec_rs2_addr(spec_insn_subw_rs2_addr),\n    .spec_rd_addr(spec_insn_subw_rd_addr),\n    .spec_rd_wdata(spec_insn_subw_rd_wdata),\n    .spec_pc_wdata(spec_insn_subw_pc_wdata),\n    .spec_mem_addr(spec_insn_subw_mem_addr),\n    .spec_mem_rmask(spec_insn_subw_mem_rmask),\n    .spec_mem_wmask(spec_insn_subw_mem_wmask),\n    .spec_mem_wdata(spec_insn_subw_mem_wdata)\n  );\n\n  wire                                spec_insn_sw_valid;\n  wire                                spec_insn_sw_trap;\n  wire [                       4 : 0] spec_insn_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sw insn_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sw_valid),\n    .spec_trap(spec_insn_sw_trap),\n    .spec_rs1_addr(spec_insn_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_xor_valid;\n  wire                                spec_insn_xor_trap;\n  wire [                       4 : 0] spec_insn_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xor insn_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xor_valid),\n    .spec_trap(spec_insn_xor_trap),\n    .spec_rs1_addr(spec_insn_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_xori_valid;\n  wire                                spec_insn_xori_trap;\n  wire [                       4 : 0] spec_insn_xori_rs1_addr;\n  wire [                       4 : 0] spec_insn_xori_rs2_addr;\n  wire [                       4 : 0] spec_insn_xori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xori insn_xori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xori_valid),\n    .spec_trap(spec_insn_xori_trap),\n    .spec_rs1_addr(spec_insn_xori_rs1_addr),\n    .spec_rs2_addr(spec_insn_xori_rs2_addr),\n    .spec_rd_addr(spec_insn_xori_rd_addr),\n    .spec_rd_wdata(spec_insn_xori_rd_wdata),\n    .spec_pc_wdata(spec_insn_xori_pc_wdata),\n    .spec_mem_addr(spec_insn_xori_mem_addr),\n    .spec_mem_rmask(spec_insn_xori_mem_rmask),\n    .spec_mem_wmask(spec_insn_xori_mem_wmask),\n    .spec_mem_wdata(spec_insn_xori_mem_wdata)\n  );\n\n  assign spec_valid =\n\t\tspec_insn_add_valid ? spec_insn_add_valid :\n\t\tspec_insn_addi_valid ? spec_insn_addi_valid :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_valid :\n\t\tspec_insn_addw_valid ? spec_insn_addw_valid :\n\t\tspec_insn_and_valid ? spec_insn_and_valid :\n\t\tspec_insn_andi_valid ? spec_insn_andi_valid :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_valid :\n\t\tspec_insn_beq_valid ? spec_insn_beq_valid :\n\t\tspec_insn_bge_valid ? spec_insn_bge_valid :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_valid :\n\t\tspec_insn_blt_valid ? spec_insn_blt_valid :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_valid :\n\t\tspec_insn_bne_valid ? spec_insn_bne_valid :\n\t\tspec_insn_div_valid ? spec_insn_div_valid :\n\t\tspec_insn_divu_valid ? spec_insn_divu_valid :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_valid :\n\t\tspec_insn_divw_valid ? spec_insn_divw_valid :\n\t\tspec_insn_jal_valid ? spec_insn_jal_valid :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_valid :\n\t\tspec_insn_lb_valid ? spec_insn_lb_valid :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_valid :\n\t\tspec_insn_ld_valid ? spec_insn_ld_valid :\n\t\tspec_insn_lh_valid ? spec_insn_lh_valid :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_valid :\n\t\tspec_insn_lui_valid ? spec_insn_lui_valid :\n\t\tspec_insn_lw_valid ? spec_insn_lw_valid :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_valid :\n\t\tspec_insn_mul_valid ? spec_insn_mul_valid :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_valid :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_valid :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_valid :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_valid :\n\t\tspec_insn_or_valid ? spec_insn_or_valid :\n\t\tspec_insn_ori_valid ? spec_insn_ori_valid :\n\t\tspec_insn_rem_valid ? spec_insn_rem_valid :\n\t\tspec_insn_remu_valid ? spec_insn_remu_valid :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_valid :\n\t\tspec_insn_remw_valid ? spec_insn_remw_valid :\n\t\tspec_insn_sb_valid ? spec_insn_sb_valid :\n\t\tspec_insn_sd_valid ? spec_insn_sd_valid :\n\t\tspec_insn_sh_valid ? spec_insn_sh_valid :\n\t\tspec_insn_sll_valid ? spec_insn_sll_valid :\n\t\tspec_insn_slli_valid ? spec_insn_slli_valid :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_valid :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_valid :\n\t\tspec_insn_slt_valid ? spec_insn_slt_valid :\n\t\tspec_insn_slti_valid ? spec_insn_slti_valid :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_valid :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_valid :\n\t\tspec_insn_sra_valid ? spec_insn_sra_valid :\n\t\tspec_insn_srai_valid ? spec_insn_srai_valid :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_valid :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_valid :\n\t\tspec_insn_srl_valid ? spec_insn_srl_valid :\n\t\tspec_insn_srli_valid ? spec_insn_srli_valid :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_valid :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_valid :\n\t\tspec_insn_sub_valid ? spec_insn_sub_valid :\n\t\tspec_insn_subw_valid ? spec_insn_subw_valid :\n\t\tspec_insn_sw_valid ? spec_insn_sw_valid :\n\t\tspec_insn_xor_valid ? spec_insn_xor_valid :\n\t\tspec_insn_xori_valid ? spec_insn_xori_valid : 0;\n  assign spec_trap =\n\t\tspec_insn_add_valid ? spec_insn_add_trap :\n\t\tspec_insn_addi_valid ? spec_insn_addi_trap :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_trap :\n\t\tspec_insn_addw_valid ? spec_insn_addw_trap :\n\t\tspec_insn_and_valid ? spec_insn_and_trap :\n\t\tspec_insn_andi_valid ? spec_insn_andi_trap :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_trap :\n\t\tspec_insn_beq_valid ? spec_insn_beq_trap :\n\t\tspec_insn_bge_valid ? spec_insn_bge_trap :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_trap :\n\t\tspec_insn_blt_valid ? spec_insn_blt_trap :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_trap :\n\t\tspec_insn_bne_valid ? spec_insn_bne_trap :\n\t\tspec_insn_div_valid ? spec_insn_div_trap :\n\t\tspec_insn_divu_valid ? spec_insn_divu_trap :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_trap :\n\t\tspec_insn_divw_valid ? spec_insn_divw_trap :\n\t\tspec_insn_jal_valid ? spec_insn_jal_trap :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_trap :\n\t\tspec_insn_lb_valid ? spec_insn_lb_trap :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_trap :\n\t\tspec_insn_ld_valid ? spec_insn_ld_trap :\n\t\tspec_insn_lh_valid ? spec_insn_lh_trap :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_trap :\n\t\tspec_insn_lui_valid ? spec_insn_lui_trap :\n\t\tspec_insn_lw_valid ? spec_insn_lw_trap :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_trap :\n\t\tspec_insn_mul_valid ? spec_insn_mul_trap :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_trap :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_trap :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_trap :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_trap :\n\t\tspec_insn_or_valid ? spec_insn_or_trap :\n\t\tspec_insn_ori_valid ? spec_insn_ori_trap :\n\t\tspec_insn_rem_valid ? spec_insn_rem_trap :\n\t\tspec_insn_remu_valid ? spec_insn_remu_trap :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_trap :\n\t\tspec_insn_remw_valid ? spec_insn_remw_trap :\n\t\tspec_insn_sb_valid ? spec_insn_sb_trap :\n\t\tspec_insn_sd_valid ? spec_insn_sd_trap :\n\t\tspec_insn_sh_valid ? spec_insn_sh_trap :\n\t\tspec_insn_sll_valid ? spec_insn_sll_trap :\n\t\tspec_insn_slli_valid ? spec_insn_slli_trap :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_trap :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_trap :\n\t\tspec_insn_slt_valid ? spec_insn_slt_trap :\n\t\tspec_insn_slti_valid ? spec_insn_slti_trap :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_trap :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_trap :\n\t\tspec_insn_sra_valid ? spec_insn_sra_trap :\n\t\tspec_insn_srai_valid ? spec_insn_srai_trap :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_trap :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_trap :\n\t\tspec_insn_srl_valid ? spec_insn_srl_trap :\n\t\tspec_insn_srli_valid ? spec_insn_srli_trap :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_trap :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_trap :\n\t\tspec_insn_sub_valid ? spec_insn_sub_trap :\n\t\tspec_insn_subw_valid ? spec_insn_subw_trap :\n\t\tspec_insn_sw_valid ? spec_insn_sw_trap :\n\t\tspec_insn_xor_valid ? spec_insn_xor_trap :\n\t\tspec_insn_xori_valid ? spec_insn_xori_trap : 0;\n  assign spec_rs1_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs1_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs1_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rs1_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rs1_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs1_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs1_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs1_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs1_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs1_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs1_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs1_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs1_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rs1_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rs1_addr :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_rs1_addr :\n\t\tspec_insn_divw_valid ? spec_insn_divw_rs1_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs1_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs1_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs1_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs1_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rs1_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs1_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs1_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs1_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs1_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rs1_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rs1_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rs1_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rs1_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rs1_addr :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_rs1_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs1_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs1_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rs1_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rs1_addr :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_rs1_addr :\n\t\tspec_insn_remw_valid ? spec_insn_remw_rs1_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs1_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rs1_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs1_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs1_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs1_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rs1_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rs1_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs1_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs1_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs1_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs1_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs1_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rs1_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs1_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs1_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rs1_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rs1_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs1_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rs1_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs1_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs1_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0;\n  assign spec_rs2_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs2_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs2_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rs2_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rs2_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs2_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs2_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs2_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs2_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs2_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs2_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs2_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs2_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rs2_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rs2_addr :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_rs2_addr :\n\t\tspec_insn_divw_valid ? spec_insn_divw_rs2_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs2_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs2_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs2_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs2_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rs2_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs2_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs2_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs2_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs2_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rs2_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rs2_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rs2_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rs2_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rs2_addr :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_rs2_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs2_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs2_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rs2_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rs2_addr :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_rs2_addr :\n\t\tspec_insn_remw_valid ? spec_insn_remw_rs2_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs2_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rs2_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs2_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs2_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs2_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rs2_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rs2_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs2_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs2_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs2_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs2_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs2_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rs2_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs2_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs2_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rs2_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rs2_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs2_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rs2_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs2_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs2_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0;\n  assign spec_rd_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rd_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rd_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rd_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rd_addr :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_rd_addr :\n\t\tspec_insn_divw_valid ? spec_insn_divw_rd_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rd_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rd_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rd_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rd_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rd_addr :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_rd_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rd_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rd_addr :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_rd_addr :\n\t\tspec_insn_remw_valid ? spec_insn_remw_rd_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rd_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rd_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rd_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rd_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rd_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rd_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rd_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_addr : 0;\n  assign spec_rd_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rd_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rd_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_rd_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rd_wdata :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_rd_wdata :\n\t\tspec_insn_divw_valid ? spec_insn_divw_rd_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rd_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rd_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rd_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rd_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rd_wdata :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_rd_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rd_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rd_wdata :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_rd_wdata :\n\t\tspec_insn_remw_valid ? spec_insn_remw_rd_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rd_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rd_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rd_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rd_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rd_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rd_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rd_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0;\n  assign spec_pc_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_pc_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_pc_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_pc_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_pc_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_pc_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_pc_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_pc_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_pc_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_pc_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_pc_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_pc_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_pc_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_pc_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_pc_wdata :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_pc_wdata :\n\t\tspec_insn_divw_valid ? spec_insn_divw_pc_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_pc_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_pc_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_pc_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_pc_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_pc_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_pc_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_pc_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_pc_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_pc_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_pc_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_pc_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_pc_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_pc_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_pc_wdata :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_pc_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_pc_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_pc_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_pc_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_pc_wdata :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_pc_wdata :\n\t\tspec_insn_remw_valid ? spec_insn_remw_pc_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_pc_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_pc_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_pc_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_pc_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_pc_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_pc_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_pc_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_pc_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_pc_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_pc_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_pc_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_pc_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_pc_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_pc_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_pc_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_pc_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_pc_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_pc_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_pc_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_pc_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_pc_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0;\n  assign spec_mem_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_addr :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_mem_addr :\n\t\tspec_insn_divw_valid ? spec_insn_divw_mem_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_addr :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_mem_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_addr :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_mem_addr :\n\t\tspec_insn_remw_valid ? spec_insn_remw_mem_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_addr : 0;\n  assign spec_mem_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_rmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_rmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_rmask :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_rmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_rmask :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_mem_rmask :\n\t\tspec_insn_divw_valid ? spec_insn_divw_mem_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_rmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_rmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_rmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_rmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_rmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_rmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_rmask :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_mem_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_rmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_rmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_rmask :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_mem_rmask :\n\t\tspec_insn_remw_valid ? spec_insn_remw_mem_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_rmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_rmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_rmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_rmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_rmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_rmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_rmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0;\n  assign spec_mem_wmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_wmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_wmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wmask :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_wmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_wmask :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_mem_wmask :\n\t\tspec_insn_divw_valid ? spec_insn_divw_mem_wmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_wmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_wmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_wmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_wmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_wmask :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_mem_wmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_wmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_wmask :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_mem_wmask :\n\t\tspec_insn_remw_valid ? spec_insn_remw_mem_wmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_wmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_wmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_wmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_wmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_wmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_wmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_wmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0;\n  assign spec_mem_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_wdata :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_mem_wdata :\n\t\tspec_insn_divw_valid ? spec_insn_divw_mem_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_wdata :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_mem_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_wdata :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_mem_wdata :\n\t\tspec_insn_remw_valid ? spec_insn_remw_mem_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0;\n`ifdef RISCV_FORMAL_CSR_MISA\n  assign spec_csr_misa_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_csr_misa_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_csr_misa_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask :\n\t\tspec_insn_div_valid ? spec_insn_div_csr_misa_rmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_csr_misa_rmask :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_csr_misa_rmask :\n\t\tspec_insn_divw_valid ? spec_insn_divw_csr_misa_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_csr_misa_rmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_csr_misa_rmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_csr_misa_rmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_csr_misa_rmask :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_csr_misa_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_csr_misa_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_csr_misa_rmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_csr_misa_rmask :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_csr_misa_rmask :\n\t\tspec_insn_remw_valid ? spec_insn_remw_csr_misa_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0;\n`endif\nendmodule\n"
  },
  {
    "path": "insns/isa_rv64imc.txt",
    "content": "add\naddi\naddiw\naddw\nand\nandi\nauipc\nbeq\nbge\nbgeu\nblt\nbltu\nbne\nc_add\nc_addi\nc_addi16sp\nc_addi4spn\nc_addiw\nc_addw\nc_and\nc_andi\nc_beqz\nc_bnez\nc_j\nc_jalr\nc_jr\nc_ld\nc_ldsp\nc_li\nc_lui\nc_lw\nc_lwsp\nc_mv\nc_or\nc_sd\nc_sdsp\nc_slli\nc_srai\nc_srli\nc_sub\nc_subw\nc_sw\nc_swsp\nc_xor\ndiv\ndivu\ndivuw\ndivw\njal\njalr\nlb\nlbu\nld\nlh\nlhu\nlui\nlw\nlwu\nmul\nmulh\nmulhsu\nmulhu\nmulw\nor\nori\nrem\nremu\nremuw\nremw\nsb\nsd\nsh\nsll\nslli\nslliw\nsllw\nslt\nslti\nsltiu\nsltu\nsra\nsrai\nsraiw\nsraw\nsrl\nsrli\nsrliw\nsrlw\nsub\nsubw\nsw\nxor\nxori\n"
  },
  {
    "path": "insns/isa_rv64imc.v",
    "content": "// DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py\n\nmodule rvfi_isa_rv64imc (\n  input                                 rvfi_valid,\n  input  [`RISCV_FORMAL_ILEN   - 1 : 0] rvfi_insn,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_pc_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs1_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_rs2_rdata,\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_mem_rdata,\n`ifdef RISCV_FORMAL_CSR_MISA\n  input  [`RISCV_FORMAL_XLEN   - 1 : 0] rvfi_csr_misa_rdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_csr_misa_rmask,\n`endif\n\n  output                                spec_valid,\n  output                                spec_trap,\n  output [                       4 : 0] spec_rs1_addr,\n  output [                       4 : 0] spec_rs2_addr,\n  output [                       4 : 0] spec_rd_addr,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_rd_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_pc_wdata,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_addr,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask,\n  output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask,\n  output [`RISCV_FORMAL_XLEN   - 1 : 0] spec_mem_wdata\n);\n  wire                                spec_insn_add_valid;\n  wire                                spec_insn_add_trap;\n  wire [                       4 : 0] spec_insn_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_add insn_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_add_valid),\n    .spec_trap(spec_insn_add_trap),\n    .spec_rs1_addr(spec_insn_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_add_rs2_addr),\n    .spec_rd_addr(spec_insn_add_rd_addr),\n    .spec_rd_wdata(spec_insn_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_add_pc_wdata),\n    .spec_mem_addr(spec_insn_add_mem_addr),\n    .spec_mem_rmask(spec_insn_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_add_mem_wdata)\n  );\n\n  wire                                spec_insn_addi_valid;\n  wire                                spec_insn_addi_trap;\n  wire [                       4 : 0] spec_insn_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addi insn_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addi_valid),\n    .spec_trap(spec_insn_addi_trap),\n    .spec_rs1_addr(spec_insn_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_addiw_valid;\n  wire                                spec_insn_addiw_trap;\n  wire [                       4 : 0] spec_insn_addiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_addiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_addiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addiw insn_addiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addiw_valid),\n    .spec_trap(spec_insn_addiw_trap),\n    .spec_rs1_addr(spec_insn_addiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_addiw_rs2_addr),\n    .spec_rd_addr(spec_insn_addiw_rd_addr),\n    .spec_rd_wdata(spec_insn_addiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_addiw_pc_wdata),\n    .spec_mem_addr(spec_insn_addiw_mem_addr),\n    .spec_mem_rmask(spec_insn_addiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_addiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_addiw_mem_wdata)\n  );\n\n  wire                                spec_insn_addw_valid;\n  wire                                spec_insn_addw_trap;\n  wire [                       4 : 0] spec_insn_addw_rs1_addr;\n  wire [                       4 : 0] spec_insn_addw_rs2_addr;\n  wire [                       4 : 0] spec_insn_addw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_addw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_addw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_addw insn_addw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_addw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_addw_valid),\n    .spec_trap(spec_insn_addw_trap),\n    .spec_rs1_addr(spec_insn_addw_rs1_addr),\n    .spec_rs2_addr(spec_insn_addw_rs2_addr),\n    .spec_rd_addr(spec_insn_addw_rd_addr),\n    .spec_rd_wdata(spec_insn_addw_rd_wdata),\n    .spec_pc_wdata(spec_insn_addw_pc_wdata),\n    .spec_mem_addr(spec_insn_addw_mem_addr),\n    .spec_mem_rmask(spec_insn_addw_mem_rmask),\n    .spec_mem_wmask(spec_insn_addw_mem_wmask),\n    .spec_mem_wdata(spec_insn_addw_mem_wdata)\n  );\n\n  wire                                spec_insn_and_valid;\n  wire                                spec_insn_and_trap;\n  wire [                       4 : 0] spec_insn_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_and insn_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_and_valid),\n    .spec_trap(spec_insn_and_trap),\n    .spec_rs1_addr(spec_insn_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_and_rs2_addr),\n    .spec_rd_addr(spec_insn_and_rd_addr),\n    .spec_rd_wdata(spec_insn_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_and_pc_wdata),\n    .spec_mem_addr(spec_insn_and_mem_addr),\n    .spec_mem_rmask(spec_insn_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_and_mem_wdata)\n  );\n\n  wire                                spec_insn_andi_valid;\n  wire                                spec_insn_andi_trap;\n  wire [                       4 : 0] spec_insn_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_andi insn_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_andi_valid),\n    .spec_trap(spec_insn_andi_trap),\n    .spec_rs1_addr(spec_insn_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_auipc_valid;\n  wire                                spec_insn_auipc_trap;\n  wire [                       4 : 0] spec_insn_auipc_rs1_addr;\n  wire [                       4 : 0] spec_insn_auipc_rs2_addr;\n  wire [                       4 : 0] spec_insn_auipc_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_auipc_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_auipc_csr_misa_rmask;\n`endif\n\n  rvfi_insn_auipc insn_auipc (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_auipc_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_auipc_valid),\n    .spec_trap(spec_insn_auipc_trap),\n    .spec_rs1_addr(spec_insn_auipc_rs1_addr),\n    .spec_rs2_addr(spec_insn_auipc_rs2_addr),\n    .spec_rd_addr(spec_insn_auipc_rd_addr),\n    .spec_rd_wdata(spec_insn_auipc_rd_wdata),\n    .spec_pc_wdata(spec_insn_auipc_pc_wdata),\n    .spec_mem_addr(spec_insn_auipc_mem_addr),\n    .spec_mem_rmask(spec_insn_auipc_mem_rmask),\n    .spec_mem_wmask(spec_insn_auipc_mem_wmask),\n    .spec_mem_wdata(spec_insn_auipc_mem_wdata)\n  );\n\n  wire                                spec_insn_beq_valid;\n  wire                                spec_insn_beq_trap;\n  wire [                       4 : 0] spec_insn_beq_rs1_addr;\n  wire [                       4 : 0] spec_insn_beq_rs2_addr;\n  wire [                       4 : 0] spec_insn_beq_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_beq_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_beq_csr_misa_rmask;\n`endif\n\n  rvfi_insn_beq insn_beq (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_beq_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_beq_valid),\n    .spec_trap(spec_insn_beq_trap),\n    .spec_rs1_addr(spec_insn_beq_rs1_addr),\n    .spec_rs2_addr(spec_insn_beq_rs2_addr),\n    .spec_rd_addr(spec_insn_beq_rd_addr),\n    .spec_rd_wdata(spec_insn_beq_rd_wdata),\n    .spec_pc_wdata(spec_insn_beq_pc_wdata),\n    .spec_mem_addr(spec_insn_beq_mem_addr),\n    .spec_mem_rmask(spec_insn_beq_mem_rmask),\n    .spec_mem_wmask(spec_insn_beq_mem_wmask),\n    .spec_mem_wdata(spec_insn_beq_mem_wdata)\n  );\n\n  wire                                spec_insn_bge_valid;\n  wire                                spec_insn_bge_trap;\n  wire [                       4 : 0] spec_insn_bge_rs1_addr;\n  wire [                       4 : 0] spec_insn_bge_rs2_addr;\n  wire [                       4 : 0] spec_insn_bge_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bge_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bge_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bge insn_bge (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bge_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bge_valid),\n    .spec_trap(spec_insn_bge_trap),\n    .spec_rs1_addr(spec_insn_bge_rs1_addr),\n    .spec_rs2_addr(spec_insn_bge_rs2_addr),\n    .spec_rd_addr(spec_insn_bge_rd_addr),\n    .spec_rd_wdata(spec_insn_bge_rd_wdata),\n    .spec_pc_wdata(spec_insn_bge_pc_wdata),\n    .spec_mem_addr(spec_insn_bge_mem_addr),\n    .spec_mem_rmask(spec_insn_bge_mem_rmask),\n    .spec_mem_wmask(spec_insn_bge_mem_wmask),\n    .spec_mem_wdata(spec_insn_bge_mem_wdata)\n  );\n\n  wire                                spec_insn_bgeu_valid;\n  wire                                spec_insn_bgeu_trap;\n  wire [                       4 : 0] spec_insn_bgeu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bgeu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bgeu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bgeu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bgeu insn_bgeu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bgeu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bgeu_valid),\n    .spec_trap(spec_insn_bgeu_trap),\n    .spec_rs1_addr(spec_insn_bgeu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bgeu_rs2_addr),\n    .spec_rd_addr(spec_insn_bgeu_rd_addr),\n    .spec_rd_wdata(spec_insn_bgeu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bgeu_pc_wdata),\n    .spec_mem_addr(spec_insn_bgeu_mem_addr),\n    .spec_mem_rmask(spec_insn_bgeu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bgeu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bgeu_mem_wdata)\n  );\n\n  wire                                spec_insn_blt_valid;\n  wire                                spec_insn_blt_trap;\n  wire [                       4 : 0] spec_insn_blt_rs1_addr;\n  wire [                       4 : 0] spec_insn_blt_rs2_addr;\n  wire [                       4 : 0] spec_insn_blt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_blt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_blt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_blt insn_blt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_blt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_blt_valid),\n    .spec_trap(spec_insn_blt_trap),\n    .spec_rs1_addr(spec_insn_blt_rs1_addr),\n    .spec_rs2_addr(spec_insn_blt_rs2_addr),\n    .spec_rd_addr(spec_insn_blt_rd_addr),\n    .spec_rd_wdata(spec_insn_blt_rd_wdata),\n    .spec_pc_wdata(spec_insn_blt_pc_wdata),\n    .spec_mem_addr(spec_insn_blt_mem_addr),\n    .spec_mem_rmask(spec_insn_blt_mem_rmask),\n    .spec_mem_wmask(spec_insn_blt_mem_wmask),\n    .spec_mem_wdata(spec_insn_blt_mem_wdata)\n  );\n\n  wire                                spec_insn_bltu_valid;\n  wire                                spec_insn_bltu_trap;\n  wire [                       4 : 0] spec_insn_bltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_bltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_bltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bltu insn_bltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bltu_valid),\n    .spec_trap(spec_insn_bltu_trap),\n    .spec_rs1_addr(spec_insn_bltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_bltu_rs2_addr),\n    .spec_rd_addr(spec_insn_bltu_rd_addr),\n    .spec_rd_wdata(spec_insn_bltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_bltu_pc_wdata),\n    .spec_mem_addr(spec_insn_bltu_mem_addr),\n    .spec_mem_rmask(spec_insn_bltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_bltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_bltu_mem_wdata)\n  );\n\n  wire                                spec_insn_bne_valid;\n  wire                                spec_insn_bne_trap;\n  wire [                       4 : 0] spec_insn_bne_rs1_addr;\n  wire [                       4 : 0] spec_insn_bne_rs2_addr;\n  wire [                       4 : 0] spec_insn_bne_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_bne_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_bne_csr_misa_rmask;\n`endif\n\n  rvfi_insn_bne insn_bne (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_bne_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_bne_valid),\n    .spec_trap(spec_insn_bne_trap),\n    .spec_rs1_addr(spec_insn_bne_rs1_addr),\n    .spec_rs2_addr(spec_insn_bne_rs2_addr),\n    .spec_rd_addr(spec_insn_bne_rd_addr),\n    .spec_rd_wdata(spec_insn_bne_rd_wdata),\n    .spec_pc_wdata(spec_insn_bne_pc_wdata),\n    .spec_mem_addr(spec_insn_bne_mem_addr),\n    .spec_mem_rmask(spec_insn_bne_mem_rmask),\n    .spec_mem_wmask(spec_insn_bne_mem_wmask),\n    .spec_mem_wdata(spec_insn_bne_mem_wdata)\n  );\n\n  wire                                spec_insn_c_add_valid;\n  wire                                spec_insn_c_add_trap;\n  wire [                       4 : 0] spec_insn_c_add_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_add_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_add_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_add_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_add_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_add insn_c_add (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_add_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_add_valid),\n    .spec_trap(spec_insn_c_add_trap),\n    .spec_rs1_addr(spec_insn_c_add_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_add_rs2_addr),\n    .spec_rd_addr(spec_insn_c_add_rd_addr),\n    .spec_rd_wdata(spec_insn_c_add_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_add_pc_wdata),\n    .spec_mem_addr(spec_insn_c_add_mem_addr),\n    .spec_mem_rmask(spec_insn_c_add_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_add_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_add_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi_valid;\n  wire                                spec_insn_c_addi_trap;\n  wire [                       4 : 0] spec_insn_c_addi_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi insn_c_addi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi_valid),\n    .spec_trap(spec_insn_c_addi_trap),\n    .spec_rs1_addr(spec_insn_c_addi_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi16sp_valid;\n  wire                                spec_insn_c_addi16sp_trap;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi16sp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi16sp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi16sp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi16sp insn_c_addi16sp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi16sp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi16sp_valid),\n    .spec_trap(spec_insn_c_addi16sp_trap),\n    .spec_rs1_addr(spec_insn_c_addi16sp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi16sp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi16sp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi16sp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi16sp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi16sp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi16sp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi16sp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi16sp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addi4spn_valid;\n  wire                                spec_insn_c_addi4spn_trap;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addi4spn_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addi4spn_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addi4spn_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addi4spn insn_c_addi4spn (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addi4spn_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addi4spn_valid),\n    .spec_trap(spec_insn_c_addi4spn_trap),\n    .spec_rs1_addr(spec_insn_c_addi4spn_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addi4spn_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addi4spn_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addi4spn_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addi4spn_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addi4spn_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addi4spn_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addi4spn_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addi4spn_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addiw_valid;\n  wire                                spec_insn_c_addiw_trap;\n  wire [                       4 : 0] spec_insn_c_addiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addiw insn_c_addiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addiw_valid),\n    .spec_trap(spec_insn_c_addiw_trap),\n    .spec_rs1_addr(spec_insn_c_addiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addiw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addiw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addiw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addiw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addiw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_addw_valid;\n  wire                                spec_insn_c_addw_trap;\n  wire [                       4 : 0] spec_insn_c_addw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_addw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_addw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_addw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_addw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_addw insn_c_addw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_addw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_addw_valid),\n    .spec_trap(spec_insn_c_addw_trap),\n    .spec_rs1_addr(spec_insn_c_addw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_addw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_addw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_addw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_addw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_addw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_addw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_addw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_addw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_and_valid;\n  wire                                spec_insn_c_and_trap;\n  wire [                       4 : 0] spec_insn_c_and_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_and_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_and_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_and_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_and_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_and insn_c_and (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_and_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_and_valid),\n    .spec_trap(spec_insn_c_and_trap),\n    .spec_rs1_addr(spec_insn_c_and_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_and_rs2_addr),\n    .spec_rd_addr(spec_insn_c_and_rd_addr),\n    .spec_rd_wdata(spec_insn_c_and_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_and_pc_wdata),\n    .spec_mem_addr(spec_insn_c_and_mem_addr),\n    .spec_mem_rmask(spec_insn_c_and_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_and_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_and_mem_wdata)\n  );\n\n  wire                                spec_insn_c_andi_valid;\n  wire                                spec_insn_c_andi_trap;\n  wire [                       4 : 0] spec_insn_c_andi_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_andi_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_andi_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_andi_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_andi_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_andi insn_c_andi (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_andi_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_andi_valid),\n    .spec_trap(spec_insn_c_andi_trap),\n    .spec_rs1_addr(spec_insn_c_andi_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_andi_rs2_addr),\n    .spec_rd_addr(spec_insn_c_andi_rd_addr),\n    .spec_rd_wdata(spec_insn_c_andi_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_andi_pc_wdata),\n    .spec_mem_addr(spec_insn_c_andi_mem_addr),\n    .spec_mem_rmask(spec_insn_c_andi_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_andi_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_andi_mem_wdata)\n  );\n\n  wire                                spec_insn_c_beqz_valid;\n  wire                                spec_insn_c_beqz_trap;\n  wire [                       4 : 0] spec_insn_c_beqz_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_beqz_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_beqz_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_beqz_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_beqz_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_beqz insn_c_beqz (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_beqz_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_beqz_valid),\n    .spec_trap(spec_insn_c_beqz_trap),\n    .spec_rs1_addr(spec_insn_c_beqz_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_beqz_rs2_addr),\n    .spec_rd_addr(spec_insn_c_beqz_rd_addr),\n    .spec_rd_wdata(spec_insn_c_beqz_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_beqz_pc_wdata),\n    .spec_mem_addr(spec_insn_c_beqz_mem_addr),\n    .spec_mem_rmask(spec_insn_c_beqz_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_beqz_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_beqz_mem_wdata)\n  );\n\n  wire                                spec_insn_c_bnez_valid;\n  wire                                spec_insn_c_bnez_trap;\n  wire [                       4 : 0] spec_insn_c_bnez_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_bnez_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_bnez_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_bnez_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_bnez_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_bnez insn_c_bnez (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_bnez_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_bnez_valid),\n    .spec_trap(spec_insn_c_bnez_trap),\n    .spec_rs1_addr(spec_insn_c_bnez_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_bnez_rs2_addr),\n    .spec_rd_addr(spec_insn_c_bnez_rd_addr),\n    .spec_rd_wdata(spec_insn_c_bnez_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_bnez_pc_wdata),\n    .spec_mem_addr(spec_insn_c_bnez_mem_addr),\n    .spec_mem_rmask(spec_insn_c_bnez_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_bnez_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_bnez_mem_wdata)\n  );\n\n  wire                                spec_insn_c_j_valid;\n  wire                                spec_insn_c_j_trap;\n  wire [                       4 : 0] spec_insn_c_j_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_j_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_j_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_j_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_j_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_j insn_c_j (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_j_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_j_valid),\n    .spec_trap(spec_insn_c_j_trap),\n    .spec_rs1_addr(spec_insn_c_j_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_j_rs2_addr),\n    .spec_rd_addr(spec_insn_c_j_rd_addr),\n    .spec_rd_wdata(spec_insn_c_j_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_j_pc_wdata),\n    .spec_mem_addr(spec_insn_c_j_mem_addr),\n    .spec_mem_rmask(spec_insn_c_j_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_j_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_j_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jalr_valid;\n  wire                                spec_insn_c_jalr_trap;\n  wire [                       4 : 0] spec_insn_c_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jalr insn_c_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jalr_valid),\n    .spec_trap(spec_insn_c_jalr_trap),\n    .spec_rs1_addr(spec_insn_c_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_c_jr_valid;\n  wire                                spec_insn_c_jr_trap;\n  wire [                       4 : 0] spec_insn_c_jr_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_jr_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_jr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_jr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_jr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_jr insn_c_jr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_jr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_jr_valid),\n    .spec_trap(spec_insn_c_jr_trap),\n    .spec_rs1_addr(spec_insn_c_jr_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_jr_rs2_addr),\n    .spec_rd_addr(spec_insn_c_jr_rd_addr),\n    .spec_rd_wdata(spec_insn_c_jr_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_jr_pc_wdata),\n    .spec_mem_addr(spec_insn_c_jr_mem_addr),\n    .spec_mem_rmask(spec_insn_c_jr_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_jr_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_jr_mem_wdata)\n  );\n\n  wire                                spec_insn_c_ld_valid;\n  wire                                spec_insn_c_ld_trap;\n  wire [                       4 : 0] spec_insn_c_ld_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_ld_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_ld_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ld_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ld_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ld_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_ld insn_c_ld (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_ld_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_ld_valid),\n    .spec_trap(spec_insn_c_ld_trap),\n    .spec_rs1_addr(spec_insn_c_ld_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_ld_rs2_addr),\n    .spec_rd_addr(spec_insn_c_ld_rd_addr),\n    .spec_rd_wdata(spec_insn_c_ld_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_ld_pc_wdata),\n    .spec_mem_addr(spec_insn_c_ld_mem_addr),\n    .spec_mem_rmask(spec_insn_c_ld_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_ld_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_ld_mem_wdata)\n  );\n\n  wire                                spec_insn_c_ldsp_valid;\n  wire                                spec_insn_c_ldsp_trap;\n  wire [                       4 : 0] spec_insn_c_ldsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_ldsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_ldsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ldsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_ldsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_ldsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_ldsp insn_c_ldsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_ldsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_ldsp_valid),\n    .spec_trap(spec_insn_c_ldsp_trap),\n    .spec_rs1_addr(spec_insn_c_ldsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_ldsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_ldsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_ldsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_ldsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_ldsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_ldsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_ldsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_ldsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_li_valid;\n  wire                                spec_insn_c_li_trap;\n  wire [                       4 : 0] spec_insn_c_li_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_li_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_li_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_li_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_li_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_li insn_c_li (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_li_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_li_valid),\n    .spec_trap(spec_insn_c_li_trap),\n    .spec_rs1_addr(spec_insn_c_li_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_li_rs2_addr),\n    .spec_rd_addr(spec_insn_c_li_rd_addr),\n    .spec_rd_wdata(spec_insn_c_li_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_li_pc_wdata),\n    .spec_mem_addr(spec_insn_c_li_mem_addr),\n    .spec_mem_rmask(spec_insn_c_li_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_li_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_li_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lui_valid;\n  wire                                spec_insn_c_lui_trap;\n  wire [                       4 : 0] spec_insn_c_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lui insn_c_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lui_valid),\n    .spec_trap(spec_insn_c_lui_trap),\n    .spec_rs1_addr(spec_insn_c_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lw_valid;\n  wire                                spec_insn_c_lw_trap;\n  wire [                       4 : 0] spec_insn_c_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lw insn_c_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lw_valid),\n    .spec_trap(spec_insn_c_lw_trap),\n    .spec_rs1_addr(spec_insn_c_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_lwsp_valid;\n  wire                                spec_insn_c_lwsp_trap;\n  wire [                       4 : 0] spec_insn_c_lwsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_lwsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_lwsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_lwsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_lwsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_lwsp insn_c_lwsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_lwsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_lwsp_valid),\n    .spec_trap(spec_insn_c_lwsp_trap),\n    .spec_rs1_addr(spec_insn_c_lwsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_lwsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_lwsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_lwsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_lwsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_lwsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_lwsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_lwsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_lwsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_mv_valid;\n  wire                                spec_insn_c_mv_trap;\n  wire [                       4 : 0] spec_insn_c_mv_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_mv_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_mv_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_mv_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_mv_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_mv insn_c_mv (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_mv_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_mv_valid),\n    .spec_trap(spec_insn_c_mv_trap),\n    .spec_rs1_addr(spec_insn_c_mv_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_mv_rs2_addr),\n    .spec_rd_addr(spec_insn_c_mv_rd_addr),\n    .spec_rd_wdata(spec_insn_c_mv_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_mv_pc_wdata),\n    .spec_mem_addr(spec_insn_c_mv_mem_addr),\n    .spec_mem_rmask(spec_insn_c_mv_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_mv_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_mv_mem_wdata)\n  );\n\n  wire                                spec_insn_c_or_valid;\n  wire                                spec_insn_c_or_trap;\n  wire [                       4 : 0] spec_insn_c_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_or insn_c_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_or_valid),\n    .spec_trap(spec_insn_c_or_trap),\n    .spec_rs1_addr(spec_insn_c_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_or_rs2_addr),\n    .spec_rd_addr(spec_insn_c_or_rd_addr),\n    .spec_rd_wdata(spec_insn_c_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_or_pc_wdata),\n    .spec_mem_addr(spec_insn_c_or_mem_addr),\n    .spec_mem_rmask(spec_insn_c_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_or_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sd_valid;\n  wire                                spec_insn_c_sd_trap;\n  wire [                       4 : 0] spec_insn_c_sd_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sd_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sd_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sd_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sd_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sd_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sd insn_c_sd (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sd_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sd_valid),\n    .spec_trap(spec_insn_c_sd_trap),\n    .spec_rs1_addr(spec_insn_c_sd_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sd_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sd_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sd_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sd_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sd_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sd_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sd_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sd_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sdsp_valid;\n  wire                                spec_insn_c_sdsp_trap;\n  wire [                       4 : 0] spec_insn_c_sdsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sdsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sdsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sdsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sdsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sdsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sdsp insn_c_sdsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sdsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sdsp_valid),\n    .spec_trap(spec_insn_c_sdsp_trap),\n    .spec_rs1_addr(spec_insn_c_sdsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sdsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sdsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sdsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sdsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sdsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sdsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sdsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sdsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_slli_valid;\n  wire                                spec_insn_c_slli_trap;\n  wire [                       4 : 0] spec_insn_c_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_slli insn_c_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_slli_valid),\n    .spec_trap(spec_insn_c_slli_trap),\n    .spec_rs1_addr(spec_insn_c_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_c_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_c_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_c_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_c_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_c_srai_valid;\n  wire                                spec_insn_c_srai_trap;\n  wire [                       4 : 0] spec_insn_c_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_srai insn_c_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_srai_valid),\n    .spec_trap(spec_insn_c_srai_trap),\n    .spec_rs1_addr(spec_insn_c_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_c_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_c_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_c_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_c_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_c_srli_valid;\n  wire                                spec_insn_c_srli_trap;\n  wire [                       4 : 0] spec_insn_c_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_srli insn_c_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_srli_valid),\n    .spec_trap(spec_insn_c_srli_trap),\n    .spec_rs1_addr(spec_insn_c_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_c_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_c_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_c_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_c_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sub_valid;\n  wire                                spec_insn_c_sub_trap;\n  wire [                       4 : 0] spec_insn_c_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sub insn_c_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sub_valid),\n    .spec_trap(spec_insn_c_sub_trap),\n    .spec_rs1_addr(spec_insn_c_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_c_subw_valid;\n  wire                                spec_insn_c_subw_trap;\n  wire [                       4 : 0] spec_insn_c_subw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_subw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_subw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_subw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_subw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_subw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_subw insn_c_subw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_subw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_subw_valid),\n    .spec_trap(spec_insn_c_subw_trap),\n    .spec_rs1_addr(spec_insn_c_subw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_subw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_subw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_subw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_subw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_subw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_subw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_subw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_subw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_sw_valid;\n  wire                                spec_insn_c_sw_trap;\n  wire [                       4 : 0] spec_insn_c_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_sw insn_c_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_sw_valid),\n    .spec_trap(spec_insn_c_sw_trap),\n    .spec_rs1_addr(spec_insn_c_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_c_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_c_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_c_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_c_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_c_swsp_valid;\n  wire                                spec_insn_c_swsp_trap;\n  wire [                       4 : 0] spec_insn_c_swsp_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_swsp_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_swsp_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_swsp_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_swsp_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_swsp insn_c_swsp (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_swsp_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_swsp_valid),\n    .spec_trap(spec_insn_c_swsp_trap),\n    .spec_rs1_addr(spec_insn_c_swsp_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_swsp_rs2_addr),\n    .spec_rd_addr(spec_insn_c_swsp_rd_addr),\n    .spec_rd_wdata(spec_insn_c_swsp_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_swsp_pc_wdata),\n    .spec_mem_addr(spec_insn_c_swsp_mem_addr),\n    .spec_mem_rmask(spec_insn_c_swsp_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_swsp_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_swsp_mem_wdata)\n  );\n\n  wire                                spec_insn_c_xor_valid;\n  wire                                spec_insn_c_xor_trap;\n  wire [                       4 : 0] spec_insn_c_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_c_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_c_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_c_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_c_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_c_xor insn_c_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_c_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_c_xor_valid),\n    .spec_trap(spec_insn_c_xor_trap),\n    .spec_rs1_addr(spec_insn_c_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_c_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_c_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_c_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_c_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_c_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_c_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_c_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_c_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_div_valid;\n  wire                                spec_insn_div_trap;\n  wire [                       4 : 0] spec_insn_div_rs1_addr;\n  wire [                       4 : 0] spec_insn_div_rs2_addr;\n  wire [                       4 : 0] spec_insn_div_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_div_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_div_csr_misa_rmask;\n`endif\n\n  rvfi_insn_div insn_div (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_div_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_div_valid),\n    .spec_trap(spec_insn_div_trap),\n    .spec_rs1_addr(spec_insn_div_rs1_addr),\n    .spec_rs2_addr(spec_insn_div_rs2_addr),\n    .spec_rd_addr(spec_insn_div_rd_addr),\n    .spec_rd_wdata(spec_insn_div_rd_wdata),\n    .spec_pc_wdata(spec_insn_div_pc_wdata),\n    .spec_mem_addr(spec_insn_div_mem_addr),\n    .spec_mem_rmask(spec_insn_div_mem_rmask),\n    .spec_mem_wmask(spec_insn_div_mem_wmask),\n    .spec_mem_wdata(spec_insn_div_mem_wdata)\n  );\n\n  wire                                spec_insn_divu_valid;\n  wire                                spec_insn_divu_trap;\n  wire [                       4 : 0] spec_insn_divu_rs1_addr;\n  wire [                       4 : 0] spec_insn_divu_rs2_addr;\n  wire [                       4 : 0] spec_insn_divu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_divu insn_divu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_divu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_divu_valid),\n    .spec_trap(spec_insn_divu_trap),\n    .spec_rs1_addr(spec_insn_divu_rs1_addr),\n    .spec_rs2_addr(spec_insn_divu_rs2_addr),\n    .spec_rd_addr(spec_insn_divu_rd_addr),\n    .spec_rd_wdata(spec_insn_divu_rd_wdata),\n    .spec_pc_wdata(spec_insn_divu_pc_wdata),\n    .spec_mem_addr(spec_insn_divu_mem_addr),\n    .spec_mem_rmask(spec_insn_divu_mem_rmask),\n    .spec_mem_wmask(spec_insn_divu_mem_wmask),\n    .spec_mem_wdata(spec_insn_divu_mem_wdata)\n  );\n\n  wire                                spec_insn_divuw_valid;\n  wire                                spec_insn_divuw_trap;\n  wire [                       4 : 0] spec_insn_divuw_rs1_addr;\n  wire [                       4 : 0] spec_insn_divuw_rs2_addr;\n  wire [                       4 : 0] spec_insn_divuw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divuw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divuw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divuw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_divuw insn_divuw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_divuw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_divuw_valid),\n    .spec_trap(spec_insn_divuw_trap),\n    .spec_rs1_addr(spec_insn_divuw_rs1_addr),\n    .spec_rs2_addr(spec_insn_divuw_rs2_addr),\n    .spec_rd_addr(spec_insn_divuw_rd_addr),\n    .spec_rd_wdata(spec_insn_divuw_rd_wdata),\n    .spec_pc_wdata(spec_insn_divuw_pc_wdata),\n    .spec_mem_addr(spec_insn_divuw_mem_addr),\n    .spec_mem_rmask(spec_insn_divuw_mem_rmask),\n    .spec_mem_wmask(spec_insn_divuw_mem_wmask),\n    .spec_mem_wdata(spec_insn_divuw_mem_wdata)\n  );\n\n  wire                                spec_insn_divw_valid;\n  wire                                spec_insn_divw_trap;\n  wire [                       4 : 0] spec_insn_divw_rs1_addr;\n  wire [                       4 : 0] spec_insn_divw_rs2_addr;\n  wire [                       4 : 0] spec_insn_divw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_divw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_divw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_divw insn_divw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_divw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_divw_valid),\n    .spec_trap(spec_insn_divw_trap),\n    .spec_rs1_addr(spec_insn_divw_rs1_addr),\n    .spec_rs2_addr(spec_insn_divw_rs2_addr),\n    .spec_rd_addr(spec_insn_divw_rd_addr),\n    .spec_rd_wdata(spec_insn_divw_rd_wdata),\n    .spec_pc_wdata(spec_insn_divw_pc_wdata),\n    .spec_mem_addr(spec_insn_divw_mem_addr),\n    .spec_mem_rmask(spec_insn_divw_mem_rmask),\n    .spec_mem_wmask(spec_insn_divw_mem_wmask),\n    .spec_mem_wdata(spec_insn_divw_mem_wdata)\n  );\n\n  wire                                spec_insn_jal_valid;\n  wire                                spec_insn_jal_trap;\n  wire [                       4 : 0] spec_insn_jal_rs1_addr;\n  wire [                       4 : 0] spec_insn_jal_rs2_addr;\n  wire [                       4 : 0] spec_insn_jal_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jal_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jal_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jal insn_jal (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jal_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jal_valid),\n    .spec_trap(spec_insn_jal_trap),\n    .spec_rs1_addr(spec_insn_jal_rs1_addr),\n    .spec_rs2_addr(spec_insn_jal_rs2_addr),\n    .spec_rd_addr(spec_insn_jal_rd_addr),\n    .spec_rd_wdata(spec_insn_jal_rd_wdata),\n    .spec_pc_wdata(spec_insn_jal_pc_wdata),\n    .spec_mem_addr(spec_insn_jal_mem_addr),\n    .spec_mem_rmask(spec_insn_jal_mem_rmask),\n    .spec_mem_wmask(spec_insn_jal_mem_wmask),\n    .spec_mem_wdata(spec_insn_jal_mem_wdata)\n  );\n\n  wire                                spec_insn_jalr_valid;\n  wire                                spec_insn_jalr_trap;\n  wire [                       4 : 0] spec_insn_jalr_rs1_addr;\n  wire [                       4 : 0] spec_insn_jalr_rs2_addr;\n  wire [                       4 : 0] spec_insn_jalr_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_jalr_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_jalr_csr_misa_rmask;\n`endif\n\n  rvfi_insn_jalr insn_jalr (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_jalr_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_jalr_valid),\n    .spec_trap(spec_insn_jalr_trap),\n    .spec_rs1_addr(spec_insn_jalr_rs1_addr),\n    .spec_rs2_addr(spec_insn_jalr_rs2_addr),\n    .spec_rd_addr(spec_insn_jalr_rd_addr),\n    .spec_rd_wdata(spec_insn_jalr_rd_wdata),\n    .spec_pc_wdata(spec_insn_jalr_pc_wdata),\n    .spec_mem_addr(spec_insn_jalr_mem_addr),\n    .spec_mem_rmask(spec_insn_jalr_mem_rmask),\n    .spec_mem_wmask(spec_insn_jalr_mem_wmask),\n    .spec_mem_wdata(spec_insn_jalr_mem_wdata)\n  );\n\n  wire                                spec_insn_lb_valid;\n  wire                                spec_insn_lb_trap;\n  wire [                       4 : 0] spec_insn_lb_rs1_addr;\n  wire [                       4 : 0] spec_insn_lb_rs2_addr;\n  wire [                       4 : 0] spec_insn_lb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lb insn_lb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lb_valid),\n    .spec_trap(spec_insn_lb_trap),\n    .spec_rs1_addr(spec_insn_lb_rs1_addr),\n    .spec_rs2_addr(spec_insn_lb_rs2_addr),\n    .spec_rd_addr(spec_insn_lb_rd_addr),\n    .spec_rd_wdata(spec_insn_lb_rd_wdata),\n    .spec_pc_wdata(spec_insn_lb_pc_wdata),\n    .spec_mem_addr(spec_insn_lb_mem_addr),\n    .spec_mem_rmask(spec_insn_lb_mem_rmask),\n    .spec_mem_wmask(spec_insn_lb_mem_wmask),\n    .spec_mem_wdata(spec_insn_lb_mem_wdata)\n  );\n\n  wire                                spec_insn_lbu_valid;\n  wire                                spec_insn_lbu_trap;\n  wire [                       4 : 0] spec_insn_lbu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lbu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lbu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lbu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lbu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lbu insn_lbu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lbu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lbu_valid),\n    .spec_trap(spec_insn_lbu_trap),\n    .spec_rs1_addr(spec_insn_lbu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lbu_rs2_addr),\n    .spec_rd_addr(spec_insn_lbu_rd_addr),\n    .spec_rd_wdata(spec_insn_lbu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lbu_pc_wdata),\n    .spec_mem_addr(spec_insn_lbu_mem_addr),\n    .spec_mem_rmask(spec_insn_lbu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lbu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lbu_mem_wdata)\n  );\n\n  wire                                spec_insn_ld_valid;\n  wire                                spec_insn_ld_trap;\n  wire [                       4 : 0] spec_insn_ld_rs1_addr;\n  wire [                       4 : 0] spec_insn_ld_rs2_addr;\n  wire [                       4 : 0] spec_insn_ld_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ld_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ld_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ld insn_ld (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ld_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ld_valid),\n    .spec_trap(spec_insn_ld_trap),\n    .spec_rs1_addr(spec_insn_ld_rs1_addr),\n    .spec_rs2_addr(spec_insn_ld_rs2_addr),\n    .spec_rd_addr(spec_insn_ld_rd_addr),\n    .spec_rd_wdata(spec_insn_ld_rd_wdata),\n    .spec_pc_wdata(spec_insn_ld_pc_wdata),\n    .spec_mem_addr(spec_insn_ld_mem_addr),\n    .spec_mem_rmask(spec_insn_ld_mem_rmask),\n    .spec_mem_wmask(spec_insn_ld_mem_wmask),\n    .spec_mem_wdata(spec_insn_ld_mem_wdata)\n  );\n\n  wire                                spec_insn_lh_valid;\n  wire                                spec_insn_lh_trap;\n  wire [                       4 : 0] spec_insn_lh_rs1_addr;\n  wire [                       4 : 0] spec_insn_lh_rs2_addr;\n  wire [                       4 : 0] spec_insn_lh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lh insn_lh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lh_valid),\n    .spec_trap(spec_insn_lh_trap),\n    .spec_rs1_addr(spec_insn_lh_rs1_addr),\n    .spec_rs2_addr(spec_insn_lh_rs2_addr),\n    .spec_rd_addr(spec_insn_lh_rd_addr),\n    .spec_rd_wdata(spec_insn_lh_rd_wdata),\n    .spec_pc_wdata(spec_insn_lh_pc_wdata),\n    .spec_mem_addr(spec_insn_lh_mem_addr),\n    .spec_mem_rmask(spec_insn_lh_mem_rmask),\n    .spec_mem_wmask(spec_insn_lh_mem_wmask),\n    .spec_mem_wdata(spec_insn_lh_mem_wdata)\n  );\n\n  wire                                spec_insn_lhu_valid;\n  wire                                spec_insn_lhu_trap;\n  wire [                       4 : 0] spec_insn_lhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lhu insn_lhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lhu_valid),\n    .spec_trap(spec_insn_lhu_trap),\n    .spec_rs1_addr(spec_insn_lhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lhu_rs2_addr),\n    .spec_rd_addr(spec_insn_lhu_rd_addr),\n    .spec_rd_wdata(spec_insn_lhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lhu_pc_wdata),\n    .spec_mem_addr(spec_insn_lhu_mem_addr),\n    .spec_mem_rmask(spec_insn_lhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lhu_mem_wdata)\n  );\n\n  wire                                spec_insn_lui_valid;\n  wire                                spec_insn_lui_trap;\n  wire [                       4 : 0] spec_insn_lui_rs1_addr;\n  wire [                       4 : 0] spec_insn_lui_rs2_addr;\n  wire [                       4 : 0] spec_insn_lui_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lui_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lui_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lui insn_lui (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lui_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lui_valid),\n    .spec_trap(spec_insn_lui_trap),\n    .spec_rs1_addr(spec_insn_lui_rs1_addr),\n    .spec_rs2_addr(spec_insn_lui_rs2_addr),\n    .spec_rd_addr(spec_insn_lui_rd_addr),\n    .spec_rd_wdata(spec_insn_lui_rd_wdata),\n    .spec_pc_wdata(spec_insn_lui_pc_wdata),\n    .spec_mem_addr(spec_insn_lui_mem_addr),\n    .spec_mem_rmask(spec_insn_lui_mem_rmask),\n    .spec_mem_wmask(spec_insn_lui_mem_wmask),\n    .spec_mem_wdata(spec_insn_lui_mem_wdata)\n  );\n\n  wire                                spec_insn_lw_valid;\n  wire                                spec_insn_lw_trap;\n  wire [                       4 : 0] spec_insn_lw_rs1_addr;\n  wire [                       4 : 0] spec_insn_lw_rs2_addr;\n  wire [                       4 : 0] spec_insn_lw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lw insn_lw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lw_valid),\n    .spec_trap(spec_insn_lw_trap),\n    .spec_rs1_addr(spec_insn_lw_rs1_addr),\n    .spec_rs2_addr(spec_insn_lw_rs2_addr),\n    .spec_rd_addr(spec_insn_lw_rd_addr),\n    .spec_rd_wdata(spec_insn_lw_rd_wdata),\n    .spec_pc_wdata(spec_insn_lw_pc_wdata),\n    .spec_mem_addr(spec_insn_lw_mem_addr),\n    .spec_mem_rmask(spec_insn_lw_mem_rmask),\n    .spec_mem_wmask(spec_insn_lw_mem_wmask),\n    .spec_mem_wdata(spec_insn_lw_mem_wdata)\n  );\n\n  wire                                spec_insn_lwu_valid;\n  wire                                spec_insn_lwu_trap;\n  wire [                       4 : 0] spec_insn_lwu_rs1_addr;\n  wire [                       4 : 0] spec_insn_lwu_rs2_addr;\n  wire [                       4 : 0] spec_insn_lwu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_lwu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_lwu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_lwu insn_lwu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_lwu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_lwu_valid),\n    .spec_trap(spec_insn_lwu_trap),\n    .spec_rs1_addr(spec_insn_lwu_rs1_addr),\n    .spec_rs2_addr(spec_insn_lwu_rs2_addr),\n    .spec_rd_addr(spec_insn_lwu_rd_addr),\n    .spec_rd_wdata(spec_insn_lwu_rd_wdata),\n    .spec_pc_wdata(spec_insn_lwu_pc_wdata),\n    .spec_mem_addr(spec_insn_lwu_mem_addr),\n    .spec_mem_rmask(spec_insn_lwu_mem_rmask),\n    .spec_mem_wmask(spec_insn_lwu_mem_wmask),\n    .spec_mem_wdata(spec_insn_lwu_mem_wdata)\n  );\n\n  wire                                spec_insn_mul_valid;\n  wire                                spec_insn_mul_trap;\n  wire [                       4 : 0] spec_insn_mul_rs1_addr;\n  wire [                       4 : 0] spec_insn_mul_rs2_addr;\n  wire [                       4 : 0] spec_insn_mul_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mul_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mul_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mul insn_mul (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mul_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mul_valid),\n    .spec_trap(spec_insn_mul_trap),\n    .spec_rs1_addr(spec_insn_mul_rs1_addr),\n    .spec_rs2_addr(spec_insn_mul_rs2_addr),\n    .spec_rd_addr(spec_insn_mul_rd_addr),\n    .spec_rd_wdata(spec_insn_mul_rd_wdata),\n    .spec_pc_wdata(spec_insn_mul_pc_wdata),\n    .spec_mem_addr(spec_insn_mul_mem_addr),\n    .spec_mem_rmask(spec_insn_mul_mem_rmask),\n    .spec_mem_wmask(spec_insn_mul_mem_wmask),\n    .spec_mem_wdata(spec_insn_mul_mem_wdata)\n  );\n\n  wire                                spec_insn_mulh_valid;\n  wire                                spec_insn_mulh_trap;\n  wire [                       4 : 0] spec_insn_mulh_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulh_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulh insn_mulh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulh_valid),\n    .spec_trap(spec_insn_mulh_trap),\n    .spec_rs1_addr(spec_insn_mulh_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulh_rs2_addr),\n    .spec_rd_addr(spec_insn_mulh_rd_addr),\n    .spec_rd_wdata(spec_insn_mulh_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulh_pc_wdata),\n    .spec_mem_addr(spec_insn_mulh_mem_addr),\n    .spec_mem_rmask(spec_insn_mulh_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulh_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulh_mem_wdata)\n  );\n\n  wire                                spec_insn_mulhsu_valid;\n  wire                                spec_insn_mulhsu_trap;\n  wire [                       4 : 0] spec_insn_mulhsu_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulhsu_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulhsu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhsu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhsu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulhsu insn_mulhsu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulhsu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulhsu_valid),\n    .spec_trap(spec_insn_mulhsu_trap),\n    .spec_rs1_addr(spec_insn_mulhsu_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulhsu_rs2_addr),\n    .spec_rd_addr(spec_insn_mulhsu_rd_addr),\n    .spec_rd_wdata(spec_insn_mulhsu_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulhsu_pc_wdata),\n    .spec_mem_addr(spec_insn_mulhsu_mem_addr),\n    .spec_mem_rmask(spec_insn_mulhsu_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulhsu_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulhsu_mem_wdata)\n  );\n\n  wire                                spec_insn_mulhu_valid;\n  wire                                spec_insn_mulhu_trap;\n  wire [                       4 : 0] spec_insn_mulhu_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulhu_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulhu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulhu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulhu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulhu insn_mulhu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulhu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulhu_valid),\n    .spec_trap(spec_insn_mulhu_trap),\n    .spec_rs1_addr(spec_insn_mulhu_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulhu_rs2_addr),\n    .spec_rd_addr(spec_insn_mulhu_rd_addr),\n    .spec_rd_wdata(spec_insn_mulhu_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulhu_pc_wdata),\n    .spec_mem_addr(spec_insn_mulhu_mem_addr),\n    .spec_mem_rmask(spec_insn_mulhu_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulhu_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulhu_mem_wdata)\n  );\n\n  wire                                spec_insn_mulw_valid;\n  wire                                spec_insn_mulw_trap;\n  wire [                       4 : 0] spec_insn_mulw_rs1_addr;\n  wire [                       4 : 0] spec_insn_mulw_rs2_addr;\n  wire [                       4 : 0] spec_insn_mulw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_mulw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_mulw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_mulw insn_mulw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_mulw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_mulw_valid),\n    .spec_trap(spec_insn_mulw_trap),\n    .spec_rs1_addr(spec_insn_mulw_rs1_addr),\n    .spec_rs2_addr(spec_insn_mulw_rs2_addr),\n    .spec_rd_addr(spec_insn_mulw_rd_addr),\n    .spec_rd_wdata(spec_insn_mulw_rd_wdata),\n    .spec_pc_wdata(spec_insn_mulw_pc_wdata),\n    .spec_mem_addr(spec_insn_mulw_mem_addr),\n    .spec_mem_rmask(spec_insn_mulw_mem_rmask),\n    .spec_mem_wmask(spec_insn_mulw_mem_wmask),\n    .spec_mem_wdata(spec_insn_mulw_mem_wdata)\n  );\n\n  wire                                spec_insn_or_valid;\n  wire                                spec_insn_or_trap;\n  wire [                       4 : 0] spec_insn_or_rs1_addr;\n  wire [                       4 : 0] spec_insn_or_rs2_addr;\n  wire [                       4 : 0] spec_insn_or_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_or_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_or_csr_misa_rmask;\n`endif\n\n  rvfi_insn_or insn_or (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_or_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_or_valid),\n    .spec_trap(spec_insn_or_trap),\n    .spec_rs1_addr(spec_insn_or_rs1_addr),\n    .spec_rs2_addr(spec_insn_or_rs2_addr),\n    .spec_rd_addr(spec_insn_or_rd_addr),\n    .spec_rd_wdata(spec_insn_or_rd_wdata),\n    .spec_pc_wdata(spec_insn_or_pc_wdata),\n    .spec_mem_addr(spec_insn_or_mem_addr),\n    .spec_mem_rmask(spec_insn_or_mem_rmask),\n    .spec_mem_wmask(spec_insn_or_mem_wmask),\n    .spec_mem_wdata(spec_insn_or_mem_wdata)\n  );\n\n  wire                                spec_insn_ori_valid;\n  wire                                spec_insn_ori_trap;\n  wire [                       4 : 0] spec_insn_ori_rs1_addr;\n  wire [                       4 : 0] spec_insn_ori_rs2_addr;\n  wire [                       4 : 0] spec_insn_ori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_ori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_ori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_ori insn_ori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_ori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_ori_valid),\n    .spec_trap(spec_insn_ori_trap),\n    .spec_rs1_addr(spec_insn_ori_rs1_addr),\n    .spec_rs2_addr(spec_insn_ori_rs2_addr),\n    .spec_rd_addr(spec_insn_ori_rd_addr),\n    .spec_rd_wdata(spec_insn_ori_rd_wdata),\n    .spec_pc_wdata(spec_insn_ori_pc_wdata),\n    .spec_mem_addr(spec_insn_ori_mem_addr),\n    .spec_mem_rmask(spec_insn_ori_mem_rmask),\n    .spec_mem_wmask(spec_insn_ori_mem_wmask),\n    .spec_mem_wdata(spec_insn_ori_mem_wdata)\n  );\n\n  wire                                spec_insn_rem_valid;\n  wire                                spec_insn_rem_trap;\n  wire [                       4 : 0] spec_insn_rem_rs1_addr;\n  wire [                       4 : 0] spec_insn_rem_rs2_addr;\n  wire [                       4 : 0] spec_insn_rem_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_rem_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_rem_csr_misa_rmask;\n`endif\n\n  rvfi_insn_rem insn_rem (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_rem_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_rem_valid),\n    .spec_trap(spec_insn_rem_trap),\n    .spec_rs1_addr(spec_insn_rem_rs1_addr),\n    .spec_rs2_addr(spec_insn_rem_rs2_addr),\n    .spec_rd_addr(spec_insn_rem_rd_addr),\n    .spec_rd_wdata(spec_insn_rem_rd_wdata),\n    .spec_pc_wdata(spec_insn_rem_pc_wdata),\n    .spec_mem_addr(spec_insn_rem_mem_addr),\n    .spec_mem_rmask(spec_insn_rem_mem_rmask),\n    .spec_mem_wmask(spec_insn_rem_mem_wmask),\n    .spec_mem_wdata(spec_insn_rem_mem_wdata)\n  );\n\n  wire                                spec_insn_remu_valid;\n  wire                                spec_insn_remu_trap;\n  wire [                       4 : 0] spec_insn_remu_rs1_addr;\n  wire [                       4 : 0] spec_insn_remu_rs2_addr;\n  wire [                       4 : 0] spec_insn_remu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_remu insn_remu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_remu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_remu_valid),\n    .spec_trap(spec_insn_remu_trap),\n    .spec_rs1_addr(spec_insn_remu_rs1_addr),\n    .spec_rs2_addr(spec_insn_remu_rs2_addr),\n    .spec_rd_addr(spec_insn_remu_rd_addr),\n    .spec_rd_wdata(spec_insn_remu_rd_wdata),\n    .spec_pc_wdata(spec_insn_remu_pc_wdata),\n    .spec_mem_addr(spec_insn_remu_mem_addr),\n    .spec_mem_rmask(spec_insn_remu_mem_rmask),\n    .spec_mem_wmask(spec_insn_remu_mem_wmask),\n    .spec_mem_wdata(spec_insn_remu_mem_wdata)\n  );\n\n  wire                                spec_insn_remuw_valid;\n  wire                                spec_insn_remuw_trap;\n  wire [                       4 : 0] spec_insn_remuw_rs1_addr;\n  wire [                       4 : 0] spec_insn_remuw_rs2_addr;\n  wire [                       4 : 0] spec_insn_remuw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remuw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remuw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remuw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_remuw insn_remuw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_remuw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_remuw_valid),\n    .spec_trap(spec_insn_remuw_trap),\n    .spec_rs1_addr(spec_insn_remuw_rs1_addr),\n    .spec_rs2_addr(spec_insn_remuw_rs2_addr),\n    .spec_rd_addr(spec_insn_remuw_rd_addr),\n    .spec_rd_wdata(spec_insn_remuw_rd_wdata),\n    .spec_pc_wdata(spec_insn_remuw_pc_wdata),\n    .spec_mem_addr(spec_insn_remuw_mem_addr),\n    .spec_mem_rmask(spec_insn_remuw_mem_rmask),\n    .spec_mem_wmask(spec_insn_remuw_mem_wmask),\n    .spec_mem_wdata(spec_insn_remuw_mem_wdata)\n  );\n\n  wire                                spec_insn_remw_valid;\n  wire                                spec_insn_remw_trap;\n  wire [                       4 : 0] spec_insn_remw_rs1_addr;\n  wire [                       4 : 0] spec_insn_remw_rs2_addr;\n  wire [                       4 : 0] spec_insn_remw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_remw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_remw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_remw insn_remw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_remw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_remw_valid),\n    .spec_trap(spec_insn_remw_trap),\n    .spec_rs1_addr(spec_insn_remw_rs1_addr),\n    .spec_rs2_addr(spec_insn_remw_rs2_addr),\n    .spec_rd_addr(spec_insn_remw_rd_addr),\n    .spec_rd_wdata(spec_insn_remw_rd_wdata),\n    .spec_pc_wdata(spec_insn_remw_pc_wdata),\n    .spec_mem_addr(spec_insn_remw_mem_addr),\n    .spec_mem_rmask(spec_insn_remw_mem_rmask),\n    .spec_mem_wmask(spec_insn_remw_mem_wmask),\n    .spec_mem_wdata(spec_insn_remw_mem_wdata)\n  );\n\n  wire                                spec_insn_sb_valid;\n  wire                                spec_insn_sb_trap;\n  wire [                       4 : 0] spec_insn_sb_rs1_addr;\n  wire [                       4 : 0] spec_insn_sb_rs2_addr;\n  wire [                       4 : 0] spec_insn_sb_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sb_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sb_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sb insn_sb (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sb_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sb_valid),\n    .spec_trap(spec_insn_sb_trap),\n    .spec_rs1_addr(spec_insn_sb_rs1_addr),\n    .spec_rs2_addr(spec_insn_sb_rs2_addr),\n    .spec_rd_addr(spec_insn_sb_rd_addr),\n    .spec_rd_wdata(spec_insn_sb_rd_wdata),\n    .spec_pc_wdata(spec_insn_sb_pc_wdata),\n    .spec_mem_addr(spec_insn_sb_mem_addr),\n    .spec_mem_rmask(spec_insn_sb_mem_rmask),\n    .spec_mem_wmask(spec_insn_sb_mem_wmask),\n    .spec_mem_wdata(spec_insn_sb_mem_wdata)\n  );\n\n  wire                                spec_insn_sd_valid;\n  wire                                spec_insn_sd_trap;\n  wire [                       4 : 0] spec_insn_sd_rs1_addr;\n  wire [                       4 : 0] spec_insn_sd_rs2_addr;\n  wire [                       4 : 0] spec_insn_sd_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sd_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sd_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sd insn_sd (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sd_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sd_valid),\n    .spec_trap(spec_insn_sd_trap),\n    .spec_rs1_addr(spec_insn_sd_rs1_addr),\n    .spec_rs2_addr(spec_insn_sd_rs2_addr),\n    .spec_rd_addr(spec_insn_sd_rd_addr),\n    .spec_rd_wdata(spec_insn_sd_rd_wdata),\n    .spec_pc_wdata(spec_insn_sd_pc_wdata),\n    .spec_mem_addr(spec_insn_sd_mem_addr),\n    .spec_mem_rmask(spec_insn_sd_mem_rmask),\n    .spec_mem_wmask(spec_insn_sd_mem_wmask),\n    .spec_mem_wdata(spec_insn_sd_mem_wdata)\n  );\n\n  wire                                spec_insn_sh_valid;\n  wire                                spec_insn_sh_trap;\n  wire [                       4 : 0] spec_insn_sh_rs1_addr;\n  wire [                       4 : 0] spec_insn_sh_rs2_addr;\n  wire [                       4 : 0] spec_insn_sh_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sh_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sh_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sh insn_sh (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sh_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sh_valid),\n    .spec_trap(spec_insn_sh_trap),\n    .spec_rs1_addr(spec_insn_sh_rs1_addr),\n    .spec_rs2_addr(spec_insn_sh_rs2_addr),\n    .spec_rd_addr(spec_insn_sh_rd_addr),\n    .spec_rd_wdata(spec_insn_sh_rd_wdata),\n    .spec_pc_wdata(spec_insn_sh_pc_wdata),\n    .spec_mem_addr(spec_insn_sh_mem_addr),\n    .spec_mem_rmask(spec_insn_sh_mem_rmask),\n    .spec_mem_wmask(spec_insn_sh_mem_wmask),\n    .spec_mem_wdata(spec_insn_sh_mem_wdata)\n  );\n\n  wire                                spec_insn_sll_valid;\n  wire                                spec_insn_sll_trap;\n  wire [                       4 : 0] spec_insn_sll_rs1_addr;\n  wire [                       4 : 0] spec_insn_sll_rs2_addr;\n  wire [                       4 : 0] spec_insn_sll_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sll_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sll_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sll insn_sll (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sll_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sll_valid),\n    .spec_trap(spec_insn_sll_trap),\n    .spec_rs1_addr(spec_insn_sll_rs1_addr),\n    .spec_rs2_addr(spec_insn_sll_rs2_addr),\n    .spec_rd_addr(spec_insn_sll_rd_addr),\n    .spec_rd_wdata(spec_insn_sll_rd_wdata),\n    .spec_pc_wdata(spec_insn_sll_pc_wdata),\n    .spec_mem_addr(spec_insn_sll_mem_addr),\n    .spec_mem_rmask(spec_insn_sll_mem_rmask),\n    .spec_mem_wmask(spec_insn_sll_mem_wmask),\n    .spec_mem_wdata(spec_insn_sll_mem_wdata)\n  );\n\n  wire                                spec_insn_slli_valid;\n  wire                                spec_insn_slli_trap;\n  wire [                       4 : 0] spec_insn_slli_rs1_addr;\n  wire [                       4 : 0] spec_insn_slli_rs2_addr;\n  wire [                       4 : 0] spec_insn_slli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slli insn_slli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slli_valid),\n    .spec_trap(spec_insn_slli_trap),\n    .spec_rs1_addr(spec_insn_slli_rs1_addr),\n    .spec_rs2_addr(spec_insn_slli_rs2_addr),\n    .spec_rd_addr(spec_insn_slli_rd_addr),\n    .spec_rd_wdata(spec_insn_slli_rd_wdata),\n    .spec_pc_wdata(spec_insn_slli_pc_wdata),\n    .spec_mem_addr(spec_insn_slli_mem_addr),\n    .spec_mem_rmask(spec_insn_slli_mem_rmask),\n    .spec_mem_wmask(spec_insn_slli_mem_wmask),\n    .spec_mem_wdata(spec_insn_slli_mem_wdata)\n  );\n\n  wire                                spec_insn_slliw_valid;\n  wire                                spec_insn_slliw_trap;\n  wire [                       4 : 0] spec_insn_slliw_rs1_addr;\n  wire [                       4 : 0] spec_insn_slliw_rs2_addr;\n  wire [                       4 : 0] spec_insn_slliw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slliw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slliw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slliw insn_slliw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slliw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slliw_valid),\n    .spec_trap(spec_insn_slliw_trap),\n    .spec_rs1_addr(spec_insn_slliw_rs1_addr),\n    .spec_rs2_addr(spec_insn_slliw_rs2_addr),\n    .spec_rd_addr(spec_insn_slliw_rd_addr),\n    .spec_rd_wdata(spec_insn_slliw_rd_wdata),\n    .spec_pc_wdata(spec_insn_slliw_pc_wdata),\n    .spec_mem_addr(spec_insn_slliw_mem_addr),\n    .spec_mem_rmask(spec_insn_slliw_mem_rmask),\n    .spec_mem_wmask(spec_insn_slliw_mem_wmask),\n    .spec_mem_wdata(spec_insn_slliw_mem_wdata)\n  );\n\n  wire                                spec_insn_sllw_valid;\n  wire                                spec_insn_sllw_trap;\n  wire [                       4 : 0] spec_insn_sllw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sllw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sllw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sllw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sllw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sllw insn_sllw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sllw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sllw_valid),\n    .spec_trap(spec_insn_sllw_trap),\n    .spec_rs1_addr(spec_insn_sllw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sllw_rs2_addr),\n    .spec_rd_addr(spec_insn_sllw_rd_addr),\n    .spec_rd_wdata(spec_insn_sllw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sllw_pc_wdata),\n    .spec_mem_addr(spec_insn_sllw_mem_addr),\n    .spec_mem_rmask(spec_insn_sllw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sllw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sllw_mem_wdata)\n  );\n\n  wire                                spec_insn_slt_valid;\n  wire                                spec_insn_slt_trap;\n  wire [                       4 : 0] spec_insn_slt_rs1_addr;\n  wire [                       4 : 0] spec_insn_slt_rs2_addr;\n  wire [                       4 : 0] spec_insn_slt_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slt_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slt_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slt insn_slt (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slt_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slt_valid),\n    .spec_trap(spec_insn_slt_trap),\n    .spec_rs1_addr(spec_insn_slt_rs1_addr),\n    .spec_rs2_addr(spec_insn_slt_rs2_addr),\n    .spec_rd_addr(spec_insn_slt_rd_addr),\n    .spec_rd_wdata(spec_insn_slt_rd_wdata),\n    .spec_pc_wdata(spec_insn_slt_pc_wdata),\n    .spec_mem_addr(spec_insn_slt_mem_addr),\n    .spec_mem_rmask(spec_insn_slt_mem_rmask),\n    .spec_mem_wmask(spec_insn_slt_mem_wmask),\n    .spec_mem_wdata(spec_insn_slt_mem_wdata)\n  );\n\n  wire                                spec_insn_slti_valid;\n  wire                                spec_insn_slti_trap;\n  wire [                       4 : 0] spec_insn_slti_rs1_addr;\n  wire [                       4 : 0] spec_insn_slti_rs2_addr;\n  wire [                       4 : 0] spec_insn_slti_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_slti_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_slti_csr_misa_rmask;\n`endif\n\n  rvfi_insn_slti insn_slti (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_slti_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_slti_valid),\n    .spec_trap(spec_insn_slti_trap),\n    .spec_rs1_addr(spec_insn_slti_rs1_addr),\n    .spec_rs2_addr(spec_insn_slti_rs2_addr),\n    .spec_rd_addr(spec_insn_slti_rd_addr),\n    .spec_rd_wdata(spec_insn_slti_rd_wdata),\n    .spec_pc_wdata(spec_insn_slti_pc_wdata),\n    .spec_mem_addr(spec_insn_slti_mem_addr),\n    .spec_mem_rmask(spec_insn_slti_mem_rmask),\n    .spec_mem_wmask(spec_insn_slti_mem_wmask),\n    .spec_mem_wdata(spec_insn_slti_mem_wdata)\n  );\n\n  wire                                spec_insn_sltiu_valid;\n  wire                                spec_insn_sltiu_trap;\n  wire [                       4 : 0] spec_insn_sltiu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltiu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltiu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltiu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltiu insn_sltiu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltiu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltiu_valid),\n    .spec_trap(spec_insn_sltiu_trap),\n    .spec_rs1_addr(spec_insn_sltiu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltiu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltiu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltiu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltiu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltiu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltiu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltiu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltiu_mem_wdata)\n  );\n\n  wire                                spec_insn_sltu_valid;\n  wire                                spec_insn_sltu_trap;\n  wire [                       4 : 0] spec_insn_sltu_rs1_addr;\n  wire [                       4 : 0] spec_insn_sltu_rs2_addr;\n  wire [                       4 : 0] spec_insn_sltu_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sltu_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sltu_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sltu insn_sltu (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sltu_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sltu_valid),\n    .spec_trap(spec_insn_sltu_trap),\n    .spec_rs1_addr(spec_insn_sltu_rs1_addr),\n    .spec_rs2_addr(spec_insn_sltu_rs2_addr),\n    .spec_rd_addr(spec_insn_sltu_rd_addr),\n    .spec_rd_wdata(spec_insn_sltu_rd_wdata),\n    .spec_pc_wdata(spec_insn_sltu_pc_wdata),\n    .spec_mem_addr(spec_insn_sltu_mem_addr),\n    .spec_mem_rmask(spec_insn_sltu_mem_rmask),\n    .spec_mem_wmask(spec_insn_sltu_mem_wmask),\n    .spec_mem_wdata(spec_insn_sltu_mem_wdata)\n  );\n\n  wire                                spec_insn_sra_valid;\n  wire                                spec_insn_sra_trap;\n  wire [                       4 : 0] spec_insn_sra_rs1_addr;\n  wire [                       4 : 0] spec_insn_sra_rs2_addr;\n  wire [                       4 : 0] spec_insn_sra_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sra_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sra_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sra insn_sra (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sra_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sra_valid),\n    .spec_trap(spec_insn_sra_trap),\n    .spec_rs1_addr(spec_insn_sra_rs1_addr),\n    .spec_rs2_addr(spec_insn_sra_rs2_addr),\n    .spec_rd_addr(spec_insn_sra_rd_addr),\n    .spec_rd_wdata(spec_insn_sra_rd_wdata),\n    .spec_pc_wdata(spec_insn_sra_pc_wdata),\n    .spec_mem_addr(spec_insn_sra_mem_addr),\n    .spec_mem_rmask(spec_insn_sra_mem_rmask),\n    .spec_mem_wmask(spec_insn_sra_mem_wmask),\n    .spec_mem_wdata(spec_insn_sra_mem_wdata)\n  );\n\n  wire                                spec_insn_srai_valid;\n  wire                                spec_insn_srai_trap;\n  wire [                       4 : 0] spec_insn_srai_rs1_addr;\n  wire [                       4 : 0] spec_insn_srai_rs2_addr;\n  wire [                       4 : 0] spec_insn_srai_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srai_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srai_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srai insn_srai (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srai_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srai_valid),\n    .spec_trap(spec_insn_srai_trap),\n    .spec_rs1_addr(spec_insn_srai_rs1_addr),\n    .spec_rs2_addr(spec_insn_srai_rs2_addr),\n    .spec_rd_addr(spec_insn_srai_rd_addr),\n    .spec_rd_wdata(spec_insn_srai_rd_wdata),\n    .spec_pc_wdata(spec_insn_srai_pc_wdata),\n    .spec_mem_addr(spec_insn_srai_mem_addr),\n    .spec_mem_rmask(spec_insn_srai_mem_rmask),\n    .spec_mem_wmask(spec_insn_srai_mem_wmask),\n    .spec_mem_wdata(spec_insn_srai_mem_wdata)\n  );\n\n  wire                                spec_insn_sraiw_valid;\n  wire                                spec_insn_sraiw_trap;\n  wire [                       4 : 0] spec_insn_sraiw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sraiw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sraiw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraiw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraiw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sraiw insn_sraiw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sraiw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sraiw_valid),\n    .spec_trap(spec_insn_sraiw_trap),\n    .spec_rs1_addr(spec_insn_sraiw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sraiw_rs2_addr),\n    .spec_rd_addr(spec_insn_sraiw_rd_addr),\n    .spec_rd_wdata(spec_insn_sraiw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sraiw_pc_wdata),\n    .spec_mem_addr(spec_insn_sraiw_mem_addr),\n    .spec_mem_rmask(spec_insn_sraiw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sraiw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sraiw_mem_wdata)\n  );\n\n  wire                                spec_insn_sraw_valid;\n  wire                                spec_insn_sraw_trap;\n  wire [                       4 : 0] spec_insn_sraw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sraw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sraw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sraw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sraw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sraw insn_sraw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sraw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sraw_valid),\n    .spec_trap(spec_insn_sraw_trap),\n    .spec_rs1_addr(spec_insn_sraw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sraw_rs2_addr),\n    .spec_rd_addr(spec_insn_sraw_rd_addr),\n    .spec_rd_wdata(spec_insn_sraw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sraw_pc_wdata),\n    .spec_mem_addr(spec_insn_sraw_mem_addr),\n    .spec_mem_rmask(spec_insn_sraw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sraw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sraw_mem_wdata)\n  );\n\n  wire                                spec_insn_srl_valid;\n  wire                                spec_insn_srl_trap;\n  wire [                       4 : 0] spec_insn_srl_rs1_addr;\n  wire [                       4 : 0] spec_insn_srl_rs2_addr;\n  wire [                       4 : 0] spec_insn_srl_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srl_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srl_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srl insn_srl (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srl_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srl_valid),\n    .spec_trap(spec_insn_srl_trap),\n    .spec_rs1_addr(spec_insn_srl_rs1_addr),\n    .spec_rs2_addr(spec_insn_srl_rs2_addr),\n    .spec_rd_addr(spec_insn_srl_rd_addr),\n    .spec_rd_wdata(spec_insn_srl_rd_wdata),\n    .spec_pc_wdata(spec_insn_srl_pc_wdata),\n    .spec_mem_addr(spec_insn_srl_mem_addr),\n    .spec_mem_rmask(spec_insn_srl_mem_rmask),\n    .spec_mem_wmask(spec_insn_srl_mem_wmask),\n    .spec_mem_wdata(spec_insn_srl_mem_wdata)\n  );\n\n  wire                                spec_insn_srli_valid;\n  wire                                spec_insn_srli_trap;\n  wire [                       4 : 0] spec_insn_srli_rs1_addr;\n  wire [                       4 : 0] spec_insn_srli_rs2_addr;\n  wire [                       4 : 0] spec_insn_srli_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srli_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srli_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srli insn_srli (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srli_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srli_valid),\n    .spec_trap(spec_insn_srli_trap),\n    .spec_rs1_addr(spec_insn_srli_rs1_addr),\n    .spec_rs2_addr(spec_insn_srli_rs2_addr),\n    .spec_rd_addr(spec_insn_srli_rd_addr),\n    .spec_rd_wdata(spec_insn_srli_rd_wdata),\n    .spec_pc_wdata(spec_insn_srli_pc_wdata),\n    .spec_mem_addr(spec_insn_srli_mem_addr),\n    .spec_mem_rmask(spec_insn_srli_mem_rmask),\n    .spec_mem_wmask(spec_insn_srli_mem_wmask),\n    .spec_mem_wdata(spec_insn_srli_mem_wdata)\n  );\n\n  wire                                spec_insn_srliw_valid;\n  wire                                spec_insn_srliw_trap;\n  wire [                       4 : 0] spec_insn_srliw_rs1_addr;\n  wire [                       4 : 0] spec_insn_srliw_rs2_addr;\n  wire [                       4 : 0] spec_insn_srliw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srliw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srliw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srliw insn_srliw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srliw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srliw_valid),\n    .spec_trap(spec_insn_srliw_trap),\n    .spec_rs1_addr(spec_insn_srliw_rs1_addr),\n    .spec_rs2_addr(spec_insn_srliw_rs2_addr),\n    .spec_rd_addr(spec_insn_srliw_rd_addr),\n    .spec_rd_wdata(spec_insn_srliw_rd_wdata),\n    .spec_pc_wdata(spec_insn_srliw_pc_wdata),\n    .spec_mem_addr(spec_insn_srliw_mem_addr),\n    .spec_mem_rmask(spec_insn_srliw_mem_rmask),\n    .spec_mem_wmask(spec_insn_srliw_mem_wmask),\n    .spec_mem_wdata(spec_insn_srliw_mem_wdata)\n  );\n\n  wire                                spec_insn_srlw_valid;\n  wire                                spec_insn_srlw_trap;\n  wire [                       4 : 0] spec_insn_srlw_rs1_addr;\n  wire [                       4 : 0] spec_insn_srlw_rs2_addr;\n  wire [                       4 : 0] spec_insn_srlw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_srlw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_srlw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_srlw insn_srlw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_srlw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_srlw_valid),\n    .spec_trap(spec_insn_srlw_trap),\n    .spec_rs1_addr(spec_insn_srlw_rs1_addr),\n    .spec_rs2_addr(spec_insn_srlw_rs2_addr),\n    .spec_rd_addr(spec_insn_srlw_rd_addr),\n    .spec_rd_wdata(spec_insn_srlw_rd_wdata),\n    .spec_pc_wdata(spec_insn_srlw_pc_wdata),\n    .spec_mem_addr(spec_insn_srlw_mem_addr),\n    .spec_mem_rmask(spec_insn_srlw_mem_rmask),\n    .spec_mem_wmask(spec_insn_srlw_mem_wmask),\n    .spec_mem_wdata(spec_insn_srlw_mem_wdata)\n  );\n\n  wire                                spec_insn_sub_valid;\n  wire                                spec_insn_sub_trap;\n  wire [                       4 : 0] spec_insn_sub_rs1_addr;\n  wire [                       4 : 0] spec_insn_sub_rs2_addr;\n  wire [                       4 : 0] spec_insn_sub_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sub_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sub_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sub insn_sub (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sub_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sub_valid),\n    .spec_trap(spec_insn_sub_trap),\n    .spec_rs1_addr(spec_insn_sub_rs1_addr),\n    .spec_rs2_addr(spec_insn_sub_rs2_addr),\n    .spec_rd_addr(spec_insn_sub_rd_addr),\n    .spec_rd_wdata(spec_insn_sub_rd_wdata),\n    .spec_pc_wdata(spec_insn_sub_pc_wdata),\n    .spec_mem_addr(spec_insn_sub_mem_addr),\n    .spec_mem_rmask(spec_insn_sub_mem_rmask),\n    .spec_mem_wmask(spec_insn_sub_mem_wmask),\n    .spec_mem_wdata(spec_insn_sub_mem_wdata)\n  );\n\n  wire                                spec_insn_subw_valid;\n  wire                                spec_insn_subw_trap;\n  wire [                       4 : 0] spec_insn_subw_rs1_addr;\n  wire [                       4 : 0] spec_insn_subw_rs2_addr;\n  wire [                       4 : 0] spec_insn_subw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_subw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_subw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_subw insn_subw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_subw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_subw_valid),\n    .spec_trap(spec_insn_subw_trap),\n    .spec_rs1_addr(spec_insn_subw_rs1_addr),\n    .spec_rs2_addr(spec_insn_subw_rs2_addr),\n    .spec_rd_addr(spec_insn_subw_rd_addr),\n    .spec_rd_wdata(spec_insn_subw_rd_wdata),\n    .spec_pc_wdata(spec_insn_subw_pc_wdata),\n    .spec_mem_addr(spec_insn_subw_mem_addr),\n    .spec_mem_rmask(spec_insn_subw_mem_rmask),\n    .spec_mem_wmask(spec_insn_subw_mem_wmask),\n    .spec_mem_wdata(spec_insn_subw_mem_wdata)\n  );\n\n  wire                                spec_insn_sw_valid;\n  wire                                spec_insn_sw_trap;\n  wire [                       4 : 0] spec_insn_sw_rs1_addr;\n  wire [                       4 : 0] spec_insn_sw_rs2_addr;\n  wire [                       4 : 0] spec_insn_sw_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_sw_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_sw_csr_misa_rmask;\n`endif\n\n  rvfi_insn_sw insn_sw (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_sw_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_sw_valid),\n    .spec_trap(spec_insn_sw_trap),\n    .spec_rs1_addr(spec_insn_sw_rs1_addr),\n    .spec_rs2_addr(spec_insn_sw_rs2_addr),\n    .spec_rd_addr(spec_insn_sw_rd_addr),\n    .spec_rd_wdata(spec_insn_sw_rd_wdata),\n    .spec_pc_wdata(spec_insn_sw_pc_wdata),\n    .spec_mem_addr(spec_insn_sw_mem_addr),\n    .spec_mem_rmask(spec_insn_sw_mem_rmask),\n    .spec_mem_wmask(spec_insn_sw_mem_wmask),\n    .spec_mem_wdata(spec_insn_sw_mem_wdata)\n  );\n\n  wire                                spec_insn_xor_valid;\n  wire                                spec_insn_xor_trap;\n  wire [                       4 : 0] spec_insn_xor_rs1_addr;\n  wire [                       4 : 0] spec_insn_xor_rs2_addr;\n  wire [                       4 : 0] spec_insn_xor_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xor_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xor_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xor insn_xor (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xor_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xor_valid),\n    .spec_trap(spec_insn_xor_trap),\n    .spec_rs1_addr(spec_insn_xor_rs1_addr),\n    .spec_rs2_addr(spec_insn_xor_rs2_addr),\n    .spec_rd_addr(spec_insn_xor_rd_addr),\n    .spec_rd_wdata(spec_insn_xor_rd_wdata),\n    .spec_pc_wdata(spec_insn_xor_pc_wdata),\n    .spec_mem_addr(spec_insn_xor_mem_addr),\n    .spec_mem_rmask(spec_insn_xor_mem_rmask),\n    .spec_mem_wmask(spec_insn_xor_mem_wmask),\n    .spec_mem_wdata(spec_insn_xor_mem_wdata)\n  );\n\n  wire                                spec_insn_xori_valid;\n  wire                                spec_insn_xori_trap;\n  wire [                       4 : 0] spec_insn_xori_rs1_addr;\n  wire [                       4 : 0] spec_insn_xori_rs2_addr;\n  wire [                       4 : 0] spec_insn_xori_rd_addr;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_rd_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_pc_wdata;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_addr;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_rmask;\n  wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_insn_xori_mem_wmask;\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_mem_wdata;\n`ifdef RISCV_FORMAL_CSR_MISA\n  wire [`RISCV_FORMAL_XLEN   - 1 : 0] spec_insn_xori_csr_misa_rmask;\n`endif\n\n  rvfi_insn_xori insn_xori (\n    .rvfi_valid(rvfi_valid),\n    .rvfi_insn(rvfi_insn),\n    .rvfi_pc_rdata(rvfi_pc_rdata),\n    .rvfi_rs1_rdata(rvfi_rs1_rdata),\n    .rvfi_rs2_rdata(rvfi_rs2_rdata),\n    .rvfi_mem_rdata(rvfi_mem_rdata),\n`ifdef RISCV_FORMAL_CSR_MISA\n    .rvfi_csr_misa_rdata(rvfi_csr_misa_rdata),\n    .spec_csr_misa_rmask(spec_insn_xori_csr_misa_rmask),\n`endif\n    .spec_valid(spec_insn_xori_valid),\n    .spec_trap(spec_insn_xori_trap),\n    .spec_rs1_addr(spec_insn_xori_rs1_addr),\n    .spec_rs2_addr(spec_insn_xori_rs2_addr),\n    .spec_rd_addr(spec_insn_xori_rd_addr),\n    .spec_rd_wdata(spec_insn_xori_rd_wdata),\n    .spec_pc_wdata(spec_insn_xori_pc_wdata),\n    .spec_mem_addr(spec_insn_xori_mem_addr),\n    .spec_mem_rmask(spec_insn_xori_mem_rmask),\n    .spec_mem_wmask(spec_insn_xori_mem_wmask),\n    .spec_mem_wdata(spec_insn_xori_mem_wdata)\n  );\n\n  assign spec_valid =\n\t\tspec_insn_add_valid ? spec_insn_add_valid :\n\t\tspec_insn_addi_valid ? spec_insn_addi_valid :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_valid :\n\t\tspec_insn_addw_valid ? spec_insn_addw_valid :\n\t\tspec_insn_and_valid ? spec_insn_and_valid :\n\t\tspec_insn_andi_valid ? spec_insn_andi_valid :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_valid :\n\t\tspec_insn_beq_valid ? spec_insn_beq_valid :\n\t\tspec_insn_bge_valid ? spec_insn_bge_valid :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_valid :\n\t\tspec_insn_blt_valid ? spec_insn_blt_valid :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_valid :\n\t\tspec_insn_bne_valid ? spec_insn_bne_valid :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_valid :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_valid :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_valid :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_valid :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_valid :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_valid :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_valid :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_valid :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_valid :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_valid :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_valid :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_valid :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_valid :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_valid :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_valid :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_valid :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_valid :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_valid :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_valid :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_valid :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_valid :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_valid :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_valid :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_valid :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_valid :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_valid :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_valid :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_valid :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_valid :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_valid :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_valid :\n\t\tspec_insn_div_valid ? spec_insn_div_valid :\n\t\tspec_insn_divu_valid ? spec_insn_divu_valid :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_valid :\n\t\tspec_insn_divw_valid ? spec_insn_divw_valid :\n\t\tspec_insn_jal_valid ? spec_insn_jal_valid :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_valid :\n\t\tspec_insn_lb_valid ? spec_insn_lb_valid :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_valid :\n\t\tspec_insn_ld_valid ? spec_insn_ld_valid :\n\t\tspec_insn_lh_valid ? spec_insn_lh_valid :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_valid :\n\t\tspec_insn_lui_valid ? spec_insn_lui_valid :\n\t\tspec_insn_lw_valid ? spec_insn_lw_valid :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_valid :\n\t\tspec_insn_mul_valid ? spec_insn_mul_valid :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_valid :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_valid :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_valid :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_valid :\n\t\tspec_insn_or_valid ? spec_insn_or_valid :\n\t\tspec_insn_ori_valid ? spec_insn_ori_valid :\n\t\tspec_insn_rem_valid ? spec_insn_rem_valid :\n\t\tspec_insn_remu_valid ? spec_insn_remu_valid :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_valid :\n\t\tspec_insn_remw_valid ? spec_insn_remw_valid :\n\t\tspec_insn_sb_valid ? spec_insn_sb_valid :\n\t\tspec_insn_sd_valid ? spec_insn_sd_valid :\n\t\tspec_insn_sh_valid ? spec_insn_sh_valid :\n\t\tspec_insn_sll_valid ? spec_insn_sll_valid :\n\t\tspec_insn_slli_valid ? spec_insn_slli_valid :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_valid :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_valid :\n\t\tspec_insn_slt_valid ? spec_insn_slt_valid :\n\t\tspec_insn_slti_valid ? spec_insn_slti_valid :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_valid :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_valid :\n\t\tspec_insn_sra_valid ? spec_insn_sra_valid :\n\t\tspec_insn_srai_valid ? spec_insn_srai_valid :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_valid :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_valid :\n\t\tspec_insn_srl_valid ? spec_insn_srl_valid :\n\t\tspec_insn_srli_valid ? spec_insn_srli_valid :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_valid :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_valid :\n\t\tspec_insn_sub_valid ? spec_insn_sub_valid :\n\t\tspec_insn_subw_valid ? spec_insn_subw_valid :\n\t\tspec_insn_sw_valid ? spec_insn_sw_valid :\n\t\tspec_insn_xor_valid ? spec_insn_xor_valid :\n\t\tspec_insn_xori_valid ? spec_insn_xori_valid : 0;\n  assign spec_trap =\n\t\tspec_insn_add_valid ? spec_insn_add_trap :\n\t\tspec_insn_addi_valid ? spec_insn_addi_trap :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_trap :\n\t\tspec_insn_addw_valid ? spec_insn_addw_trap :\n\t\tspec_insn_and_valid ? spec_insn_and_trap :\n\t\tspec_insn_andi_valid ? spec_insn_andi_trap :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_trap :\n\t\tspec_insn_beq_valid ? spec_insn_beq_trap :\n\t\tspec_insn_bge_valid ? spec_insn_bge_trap :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_trap :\n\t\tspec_insn_blt_valid ? spec_insn_blt_trap :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_trap :\n\t\tspec_insn_bne_valid ? spec_insn_bne_trap :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_trap :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_trap :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_trap :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_trap :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_trap :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_trap :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_trap :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_trap :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_trap :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_trap :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_trap :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_trap :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_trap :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_trap :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_trap :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_trap :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_trap :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_trap :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_trap :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_trap :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_trap :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_trap :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_trap :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_trap :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_trap :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_trap :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_trap :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_trap :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_trap :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_trap :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_trap :\n\t\tspec_insn_div_valid ? spec_insn_div_trap :\n\t\tspec_insn_divu_valid ? spec_insn_divu_trap :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_trap :\n\t\tspec_insn_divw_valid ? spec_insn_divw_trap :\n\t\tspec_insn_jal_valid ? spec_insn_jal_trap :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_trap :\n\t\tspec_insn_lb_valid ? spec_insn_lb_trap :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_trap :\n\t\tspec_insn_ld_valid ? spec_insn_ld_trap :\n\t\tspec_insn_lh_valid ? spec_insn_lh_trap :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_trap :\n\t\tspec_insn_lui_valid ? spec_insn_lui_trap :\n\t\tspec_insn_lw_valid ? spec_insn_lw_trap :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_trap :\n\t\tspec_insn_mul_valid ? spec_insn_mul_trap :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_trap :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_trap :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_trap :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_trap :\n\t\tspec_insn_or_valid ? spec_insn_or_trap :\n\t\tspec_insn_ori_valid ? spec_insn_ori_trap :\n\t\tspec_insn_rem_valid ? spec_insn_rem_trap :\n\t\tspec_insn_remu_valid ? spec_insn_remu_trap :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_trap :\n\t\tspec_insn_remw_valid ? spec_insn_remw_trap :\n\t\tspec_insn_sb_valid ? spec_insn_sb_trap :\n\t\tspec_insn_sd_valid ? spec_insn_sd_trap :\n\t\tspec_insn_sh_valid ? spec_insn_sh_trap :\n\t\tspec_insn_sll_valid ? spec_insn_sll_trap :\n\t\tspec_insn_slli_valid ? spec_insn_slli_trap :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_trap :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_trap :\n\t\tspec_insn_slt_valid ? spec_insn_slt_trap :\n\t\tspec_insn_slti_valid ? spec_insn_slti_trap :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_trap :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_trap :\n\t\tspec_insn_sra_valid ? spec_insn_sra_trap :\n\t\tspec_insn_srai_valid ? spec_insn_srai_trap :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_trap :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_trap :\n\t\tspec_insn_srl_valid ? spec_insn_srl_trap :\n\t\tspec_insn_srli_valid ? spec_insn_srli_trap :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_trap :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_trap :\n\t\tspec_insn_sub_valid ? spec_insn_sub_trap :\n\t\tspec_insn_subw_valid ? spec_insn_subw_trap :\n\t\tspec_insn_sw_valid ? spec_insn_sw_trap :\n\t\tspec_insn_xor_valid ? spec_insn_xor_trap :\n\t\tspec_insn_xori_valid ? spec_insn_xori_trap : 0;\n  assign spec_rs1_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs1_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs1_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rs1_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rs1_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs1_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs1_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs1_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs1_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs1_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs1_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs1_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs1_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs1_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rs1_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rs1_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs1_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs1_addr :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_rs1_addr :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_rs1_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rs1_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rs1_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rs1_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rs1_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rs1_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rs1_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rs1_addr :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_rs1_addr :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rs1_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rs1_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rs1_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rs1_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs1_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rs1_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rs1_addr :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_rs1_addr :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rs1_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rs1_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rs1_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rs1_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rs1_addr :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_rs1_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rs1_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rs1_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rs1_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rs1_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rs1_addr :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_rs1_addr :\n\t\tspec_insn_divw_valid ? spec_insn_divw_rs1_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs1_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs1_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs1_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs1_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rs1_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs1_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs1_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs1_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs1_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rs1_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rs1_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rs1_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rs1_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rs1_addr :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_rs1_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs1_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs1_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rs1_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rs1_addr :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_rs1_addr :\n\t\tspec_insn_remw_valid ? spec_insn_remw_rs1_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs1_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rs1_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs1_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs1_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs1_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rs1_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rs1_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs1_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs1_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs1_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs1_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs1_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs1_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rs1_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rs1_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs1_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs1_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rs1_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rs1_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs1_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rs1_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs1_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs1_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs1_addr : 0;\n  assign spec_rs2_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rs2_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rs2_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rs2_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rs2_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rs2_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rs2_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rs2_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rs2_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rs2_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rs2_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rs2_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rs2_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rs2_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rs2_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rs2_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rs2_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rs2_addr :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_rs2_addr :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_rs2_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rs2_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rs2_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rs2_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rs2_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rs2_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rs2_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rs2_addr :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_rs2_addr :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rs2_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rs2_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rs2_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rs2_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rs2_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rs2_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rs2_addr :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_rs2_addr :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rs2_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rs2_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rs2_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rs2_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rs2_addr :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_rs2_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rs2_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rs2_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rs2_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rs2_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rs2_addr :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_rs2_addr :\n\t\tspec_insn_divw_valid ? spec_insn_divw_rs2_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rs2_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rs2_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rs2_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rs2_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rs2_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rs2_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rs2_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rs2_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rs2_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rs2_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rs2_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rs2_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rs2_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rs2_addr :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_rs2_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rs2_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rs2_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rs2_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rs2_addr :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_rs2_addr :\n\t\tspec_insn_remw_valid ? spec_insn_remw_rs2_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rs2_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rs2_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rs2_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rs2_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rs2_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rs2_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rs2_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rs2_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rs2_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rs2_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rs2_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rs2_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rs2_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rs2_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rs2_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rs2_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rs2_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rs2_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rs2_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rs2_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rs2_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rs2_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rs2_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rs2_addr : 0;\n  assign spec_rd_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rd_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rd_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rd_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rd_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_addr :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_rd_addr :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_rd_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rd_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rd_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rd_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rd_addr :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_rd_addr :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rd_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rd_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rd_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rd_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rd_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rd_addr :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_rd_addr :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rd_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rd_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rd_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rd_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rd_addr :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_rd_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rd_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rd_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_rd_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rd_addr :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_rd_addr :\n\t\tspec_insn_divw_valid ? spec_insn_divw_rd_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rd_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rd_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rd_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rd_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rd_addr :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_rd_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rd_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rd_addr :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_rd_addr :\n\t\tspec_insn_remw_valid ? spec_insn_remw_rd_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rd_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rd_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rd_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rd_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rd_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rd_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rd_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rd_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_addr : 0;\n  assign spec_rd_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_rd_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_rd_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_rd_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_rd_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_rd_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_rd_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_rd_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_rd_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_rd_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_rd_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_rd_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_rd_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_rd_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_rd_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_rd_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_rd_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_rd_wdata :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_rd_wdata :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_rd_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_rd_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_rd_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_rd_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_rd_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_rd_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_rd_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_rd_wdata :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_rd_wdata :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_rd_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_rd_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_rd_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_rd_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_rd_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_rd_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_rd_wdata :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_rd_wdata :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_rd_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_rd_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_rd_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_rd_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_rd_wdata :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_rd_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_rd_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_rd_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_rd_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_rd_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_rd_wdata :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_rd_wdata :\n\t\tspec_insn_divw_valid ? spec_insn_divw_rd_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_rd_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_rd_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_rd_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_rd_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_rd_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_rd_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_rd_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_rd_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_rd_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_rd_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_rd_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_rd_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_rd_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_rd_wdata :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_rd_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_rd_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_rd_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_rd_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_rd_wdata :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_rd_wdata :\n\t\tspec_insn_remw_valid ? spec_insn_remw_rd_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_rd_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_rd_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_rd_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_rd_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_rd_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_rd_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_rd_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_rd_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_rd_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_rd_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_rd_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_rd_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_rd_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_rd_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_rd_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_rd_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_rd_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_rd_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_rd_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_rd_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_rd_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_rd_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_rd_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_rd_wdata : 0;\n  assign spec_pc_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_pc_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_pc_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_pc_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_pc_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_pc_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_pc_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_pc_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_pc_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_pc_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_pc_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_pc_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_pc_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_pc_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_pc_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_pc_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_pc_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_pc_wdata :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_pc_wdata :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_pc_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_pc_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_pc_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_pc_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_pc_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_pc_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_pc_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_pc_wdata :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_pc_wdata :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_pc_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_pc_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_pc_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_pc_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_pc_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_pc_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_pc_wdata :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_pc_wdata :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_pc_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_pc_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_pc_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_pc_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_pc_wdata :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_pc_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_pc_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_pc_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_pc_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_pc_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_pc_wdata :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_pc_wdata :\n\t\tspec_insn_divw_valid ? spec_insn_divw_pc_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_pc_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_pc_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_pc_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_pc_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_pc_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_pc_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_pc_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_pc_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_pc_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_pc_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_pc_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_pc_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_pc_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_pc_wdata :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_pc_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_pc_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_pc_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_pc_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_pc_wdata :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_pc_wdata :\n\t\tspec_insn_remw_valid ? spec_insn_remw_pc_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_pc_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_pc_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_pc_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_pc_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_pc_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_pc_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_pc_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_pc_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_pc_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_pc_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_pc_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_pc_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_pc_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_pc_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_pc_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_pc_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_pc_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_pc_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_pc_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_pc_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_pc_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_pc_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_pc_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_pc_wdata : 0;\n  assign spec_mem_addr =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_addr :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_addr :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_addr :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_addr :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_addr :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_addr :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_addr :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_addr :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_addr :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_addr :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_addr :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_addr :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_addr :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_addr :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_addr :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_addr :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_addr :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_addr :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_mem_addr :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_addr :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_addr :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_addr :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_addr :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_addr :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_addr :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_addr :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_mem_addr :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_addr :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_addr :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_addr :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_addr :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_addr :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_addr :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_addr :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_mem_addr :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_addr :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_addr :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_addr :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_addr :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_addr :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_mem_addr :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_addr :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_addr :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_addr :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_addr :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_addr :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_mem_addr :\n\t\tspec_insn_divw_valid ? spec_insn_divw_mem_addr :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_addr :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_addr :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_addr :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_addr :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_addr :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_addr :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_addr :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_addr :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_addr :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_addr :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_addr :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_addr :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_addr :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_addr :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_mem_addr :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_addr :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_addr :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_addr :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_addr :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_mem_addr :\n\t\tspec_insn_remw_valid ? spec_insn_remw_mem_addr :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_addr :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_addr :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_addr :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_addr :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_addr :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_addr :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_addr :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_addr :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_addr :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_addr :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_addr :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_addr :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_addr :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_addr :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_addr :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_addr :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_addr :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_addr :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_addr :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_addr :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_addr :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_addr :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_addr :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_addr : 0;\n  assign spec_mem_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_rmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_rmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_rmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_rmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_rmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_rmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_rmask :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_rmask :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_mem_rmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_rmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_rmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_rmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_rmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_rmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_rmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_rmask :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_mem_rmask :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_rmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_rmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_rmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_rmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_rmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_rmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_rmask :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_mem_rmask :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_rmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_rmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_rmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_rmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_rmask :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_mem_rmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_rmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_rmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_rmask :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_rmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_rmask :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_mem_rmask :\n\t\tspec_insn_divw_valid ? spec_insn_divw_mem_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_rmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_rmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_rmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_rmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_rmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_rmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_rmask :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_mem_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_rmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_rmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_rmask :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_mem_rmask :\n\t\tspec_insn_remw_valid ? spec_insn_remw_mem_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_rmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_rmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_rmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_rmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_rmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_rmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_rmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_rmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_rmask : 0;\n  assign spec_mem_wmask =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_wmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_wmask :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_wmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_wmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wmask :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_wmask :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_mem_wmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_wmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_wmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_wmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_wmask :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_mem_wmask :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_wmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_wmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_wmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_wmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_wmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_wmask :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_mem_wmask :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_wmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_wmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_wmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_wmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_wmask :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_mem_wmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_wmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_wmask :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_wmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_wmask :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_mem_wmask :\n\t\tspec_insn_divw_valid ? spec_insn_divw_mem_wmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_wmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_wmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_wmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_wmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_wmask :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_mem_wmask :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_wmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_wmask :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_mem_wmask :\n\t\tspec_insn_remw_valid ? spec_insn_remw_mem_wmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_wmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_wmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_wmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_wmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_wmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_wmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_wmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_wmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wmask : 0;\n  assign spec_mem_wdata =\n\t\tspec_insn_add_valid ? spec_insn_add_mem_wdata :\n\t\tspec_insn_addi_valid ? spec_insn_addi_mem_wdata :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_mem_wdata :\n\t\tspec_insn_addw_valid ? spec_insn_addw_mem_wdata :\n\t\tspec_insn_and_valid ? spec_insn_and_mem_wdata :\n\t\tspec_insn_andi_valid ? spec_insn_andi_mem_wdata :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_mem_wdata :\n\t\tspec_insn_beq_valid ? spec_insn_beq_mem_wdata :\n\t\tspec_insn_bge_valid ? spec_insn_bge_mem_wdata :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_mem_wdata :\n\t\tspec_insn_blt_valid ? spec_insn_blt_mem_wdata :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_mem_wdata :\n\t\tspec_insn_bne_valid ? spec_insn_bne_mem_wdata :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_mem_wdata :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_mem_wdata :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_mem_wdata :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_mem_wdata :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_mem_wdata :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_mem_wdata :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_mem_wdata :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_mem_wdata :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_mem_wdata :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_mem_wdata :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_mem_wdata :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_mem_wdata :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_mem_wdata :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_mem_wdata :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_mem_wdata :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_mem_wdata :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_mem_wdata :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_mem_wdata :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_mem_wdata :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_mem_wdata :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_mem_wdata :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_mem_wdata :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_mem_wdata :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_mem_wdata :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_mem_wdata :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_mem_wdata :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_mem_wdata :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_mem_wdata :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_mem_wdata :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_mem_wdata :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_mem_wdata :\n\t\tspec_insn_div_valid ? spec_insn_div_mem_wdata :\n\t\tspec_insn_divu_valid ? spec_insn_divu_mem_wdata :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_mem_wdata :\n\t\tspec_insn_divw_valid ? spec_insn_divw_mem_wdata :\n\t\tspec_insn_jal_valid ? spec_insn_jal_mem_wdata :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_mem_wdata :\n\t\tspec_insn_lb_valid ? spec_insn_lb_mem_wdata :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_mem_wdata :\n\t\tspec_insn_ld_valid ? spec_insn_ld_mem_wdata :\n\t\tspec_insn_lh_valid ? spec_insn_lh_mem_wdata :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_mem_wdata :\n\t\tspec_insn_lui_valid ? spec_insn_lui_mem_wdata :\n\t\tspec_insn_lw_valid ? spec_insn_lw_mem_wdata :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_mem_wdata :\n\t\tspec_insn_mul_valid ? spec_insn_mul_mem_wdata :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_mem_wdata :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_mem_wdata :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_mem_wdata :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_mem_wdata :\n\t\tspec_insn_or_valid ? spec_insn_or_mem_wdata :\n\t\tspec_insn_ori_valid ? spec_insn_ori_mem_wdata :\n\t\tspec_insn_rem_valid ? spec_insn_rem_mem_wdata :\n\t\tspec_insn_remu_valid ? spec_insn_remu_mem_wdata :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_mem_wdata :\n\t\tspec_insn_remw_valid ? spec_insn_remw_mem_wdata :\n\t\tspec_insn_sb_valid ? spec_insn_sb_mem_wdata :\n\t\tspec_insn_sd_valid ? spec_insn_sd_mem_wdata :\n\t\tspec_insn_sh_valid ? spec_insn_sh_mem_wdata :\n\t\tspec_insn_sll_valid ? spec_insn_sll_mem_wdata :\n\t\tspec_insn_slli_valid ? spec_insn_slli_mem_wdata :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_mem_wdata :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_mem_wdata :\n\t\tspec_insn_slt_valid ? spec_insn_slt_mem_wdata :\n\t\tspec_insn_slti_valid ? spec_insn_slti_mem_wdata :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_mem_wdata :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_mem_wdata :\n\t\tspec_insn_sra_valid ? spec_insn_sra_mem_wdata :\n\t\tspec_insn_srai_valid ? spec_insn_srai_mem_wdata :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_mem_wdata :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_mem_wdata :\n\t\tspec_insn_srl_valid ? spec_insn_srl_mem_wdata :\n\t\tspec_insn_srli_valid ? spec_insn_srli_mem_wdata :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_mem_wdata :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_mem_wdata :\n\t\tspec_insn_sub_valid ? spec_insn_sub_mem_wdata :\n\t\tspec_insn_subw_valid ? spec_insn_subw_mem_wdata :\n\t\tspec_insn_sw_valid ? spec_insn_sw_mem_wdata :\n\t\tspec_insn_xor_valid ? spec_insn_xor_mem_wdata :\n\t\tspec_insn_xori_valid ? spec_insn_xori_mem_wdata : 0;\n`ifdef RISCV_FORMAL_CSR_MISA\n  assign spec_csr_misa_rmask =\n\t\tspec_insn_add_valid ? spec_insn_add_csr_misa_rmask :\n\t\tspec_insn_addi_valid ? spec_insn_addi_csr_misa_rmask :\n\t\tspec_insn_addiw_valid ? spec_insn_addiw_csr_misa_rmask :\n\t\tspec_insn_addw_valid ? spec_insn_addw_csr_misa_rmask :\n\t\tspec_insn_and_valid ? spec_insn_and_csr_misa_rmask :\n\t\tspec_insn_andi_valid ? spec_insn_andi_csr_misa_rmask :\n\t\tspec_insn_auipc_valid ? spec_insn_auipc_csr_misa_rmask :\n\t\tspec_insn_beq_valid ? spec_insn_beq_csr_misa_rmask :\n\t\tspec_insn_bge_valid ? spec_insn_bge_csr_misa_rmask :\n\t\tspec_insn_bgeu_valid ? spec_insn_bgeu_csr_misa_rmask :\n\t\tspec_insn_blt_valid ? spec_insn_blt_csr_misa_rmask :\n\t\tspec_insn_bltu_valid ? spec_insn_bltu_csr_misa_rmask :\n\t\tspec_insn_bne_valid ? spec_insn_bne_csr_misa_rmask :\n\t\tspec_insn_c_add_valid ? spec_insn_c_add_csr_misa_rmask :\n\t\tspec_insn_c_addi_valid ? spec_insn_c_addi_csr_misa_rmask :\n\t\tspec_insn_c_addi16sp_valid ? spec_insn_c_addi16sp_csr_misa_rmask :\n\t\tspec_insn_c_addi4spn_valid ? spec_insn_c_addi4spn_csr_misa_rmask :\n\t\tspec_insn_c_addiw_valid ? spec_insn_c_addiw_csr_misa_rmask :\n\t\tspec_insn_c_addw_valid ? spec_insn_c_addw_csr_misa_rmask :\n\t\tspec_insn_c_and_valid ? spec_insn_c_and_csr_misa_rmask :\n\t\tspec_insn_c_andi_valid ? spec_insn_c_andi_csr_misa_rmask :\n\t\tspec_insn_c_beqz_valid ? spec_insn_c_beqz_csr_misa_rmask :\n\t\tspec_insn_c_bnez_valid ? spec_insn_c_bnez_csr_misa_rmask :\n\t\tspec_insn_c_j_valid ? spec_insn_c_j_csr_misa_rmask :\n\t\tspec_insn_c_jalr_valid ? spec_insn_c_jalr_csr_misa_rmask :\n\t\tspec_insn_c_jr_valid ? spec_insn_c_jr_csr_misa_rmask :\n\t\tspec_insn_c_ld_valid ? spec_insn_c_ld_csr_misa_rmask :\n\t\tspec_insn_c_ldsp_valid ? spec_insn_c_ldsp_csr_misa_rmask :\n\t\tspec_insn_c_li_valid ? spec_insn_c_li_csr_misa_rmask :\n\t\tspec_insn_c_lui_valid ? spec_insn_c_lui_csr_misa_rmask :\n\t\tspec_insn_c_lw_valid ? spec_insn_c_lw_csr_misa_rmask :\n\t\tspec_insn_c_lwsp_valid ? spec_insn_c_lwsp_csr_misa_rmask :\n\t\tspec_insn_c_mv_valid ? spec_insn_c_mv_csr_misa_rmask :\n\t\tspec_insn_c_or_valid ? spec_insn_c_or_csr_misa_rmask :\n\t\tspec_insn_c_sd_valid ? spec_insn_c_sd_csr_misa_rmask :\n\t\tspec_insn_c_sdsp_valid ? spec_insn_c_sdsp_csr_misa_rmask :\n\t\tspec_insn_c_slli_valid ? spec_insn_c_slli_csr_misa_rmask :\n\t\tspec_insn_c_srai_valid ? spec_insn_c_srai_csr_misa_rmask :\n\t\tspec_insn_c_srli_valid ? spec_insn_c_srli_csr_misa_rmask :\n\t\tspec_insn_c_sub_valid ? spec_insn_c_sub_csr_misa_rmask :\n\t\tspec_insn_c_subw_valid ? spec_insn_c_subw_csr_misa_rmask :\n\t\tspec_insn_c_sw_valid ? spec_insn_c_sw_csr_misa_rmask :\n\t\tspec_insn_c_swsp_valid ? spec_insn_c_swsp_csr_misa_rmask :\n\t\tspec_insn_c_xor_valid ? spec_insn_c_xor_csr_misa_rmask :\n\t\tspec_insn_div_valid ? spec_insn_div_csr_misa_rmask :\n\t\tspec_insn_divu_valid ? spec_insn_divu_csr_misa_rmask :\n\t\tspec_insn_divuw_valid ? spec_insn_divuw_csr_misa_rmask :\n\t\tspec_insn_divw_valid ? spec_insn_divw_csr_misa_rmask :\n\t\tspec_insn_jal_valid ? spec_insn_jal_csr_misa_rmask :\n\t\tspec_insn_jalr_valid ? spec_insn_jalr_csr_misa_rmask :\n\t\tspec_insn_lb_valid ? spec_insn_lb_csr_misa_rmask :\n\t\tspec_insn_lbu_valid ? spec_insn_lbu_csr_misa_rmask :\n\t\tspec_insn_ld_valid ? spec_insn_ld_csr_misa_rmask :\n\t\tspec_insn_lh_valid ? spec_insn_lh_csr_misa_rmask :\n\t\tspec_insn_lhu_valid ? spec_insn_lhu_csr_misa_rmask :\n\t\tspec_insn_lui_valid ? spec_insn_lui_csr_misa_rmask :\n\t\tspec_insn_lw_valid ? spec_insn_lw_csr_misa_rmask :\n\t\tspec_insn_lwu_valid ? spec_insn_lwu_csr_misa_rmask :\n\t\tspec_insn_mul_valid ? spec_insn_mul_csr_misa_rmask :\n\t\tspec_insn_mulh_valid ? spec_insn_mulh_csr_misa_rmask :\n\t\tspec_insn_mulhsu_valid ? spec_insn_mulhsu_csr_misa_rmask :\n\t\tspec_insn_mulhu_valid ? spec_insn_mulhu_csr_misa_rmask :\n\t\tspec_insn_mulw_valid ? spec_insn_mulw_csr_misa_rmask :\n\t\tspec_insn_or_valid ? spec_insn_or_csr_misa_rmask :\n\t\tspec_insn_ori_valid ? spec_insn_ori_csr_misa_rmask :\n\t\tspec_insn_rem_valid ? spec_insn_rem_csr_misa_rmask :\n\t\tspec_insn_remu_valid ? spec_insn_remu_csr_misa_rmask :\n\t\tspec_insn_remuw_valid ? spec_insn_remuw_csr_misa_rmask :\n\t\tspec_insn_remw_valid ? spec_insn_remw_csr_misa_rmask :\n\t\tspec_insn_sb_valid ? spec_insn_sb_csr_misa_rmask :\n\t\tspec_insn_sd_valid ? spec_insn_sd_csr_misa_rmask :\n\t\tspec_insn_sh_valid ? spec_insn_sh_csr_misa_rmask :\n\t\tspec_insn_sll_valid ? spec_insn_sll_csr_misa_rmask :\n\t\tspec_insn_slli_valid ? spec_insn_slli_csr_misa_rmask :\n\t\tspec_insn_slliw_valid ? spec_insn_slliw_csr_misa_rmask :\n\t\tspec_insn_sllw_valid ? spec_insn_sllw_csr_misa_rmask :\n\t\tspec_insn_slt_valid ? spec_insn_slt_csr_misa_rmask :\n\t\tspec_insn_slti_valid ? spec_insn_slti_csr_misa_rmask :\n\t\tspec_insn_sltiu_valid ? spec_insn_sltiu_csr_misa_rmask :\n\t\tspec_insn_sltu_valid ? spec_insn_sltu_csr_misa_rmask :\n\t\tspec_insn_sra_valid ? spec_insn_sra_csr_misa_rmask :\n\t\tspec_insn_srai_valid ? spec_insn_srai_csr_misa_rmask :\n\t\tspec_insn_sraiw_valid ? spec_insn_sraiw_csr_misa_rmask :\n\t\tspec_insn_sraw_valid ? spec_insn_sraw_csr_misa_rmask :\n\t\tspec_insn_srl_valid ? spec_insn_srl_csr_misa_rmask :\n\t\tspec_insn_srli_valid ? spec_insn_srli_csr_misa_rmask :\n\t\tspec_insn_srliw_valid ? spec_insn_srliw_csr_misa_rmask :\n\t\tspec_insn_srlw_valid ? spec_insn_srlw_csr_misa_rmask :\n\t\tspec_insn_sub_valid ? spec_insn_sub_csr_misa_rmask :\n\t\tspec_insn_subw_valid ? spec_insn_subw_csr_misa_rmask :\n\t\tspec_insn_sw_valid ? spec_insn_sw_csr_misa_rmask :\n\t\tspec_insn_xor_valid ? spec_insn_xor_csr_misa_rmask :\n\t\tspec_insn_xori_valid ? spec_insn_xori_csr_misa_rmask : 0;\n`endif\nendmodule\n"
  },
  {
    "path": "monitor/generate.py",
    "content": "#!/usr/bin/env python3\n\nimport getopt, sys\nfrom math import log2, ceil\n\nisa = \"rv32i\"\nprefix = None\nchannels = 1\nrobdepth = 256\nxlen = None\nilen = None\naligned = False\ncompressed = False\nignore_mem = False\nuse_assert = False\nquiet_mode = False\nverbose_mode = False\nnoregscheck = False\nnopccheck = False\n\ndef usage():\n    print(\"\"\"\n\nUsage: %s [options] > outfile.v\n\n  -i <isa>\n      RISC-V ISA (default: rv32i)\n\n  -p <prefix>\n      use <prefix> as prefix for generated verilog modules\n      default: riscv_formal_monitor_<isa>\n\n  -c <int>\n      number of RVFI channels (default: 1)\n\n  -r <int>\n      depth of reorder buffer (must be a power of two, default: 256)\n      setting this option to 0 will disabling reordering\n\n  -a\n      create monitor for core with aligned memory access\n\n  -M\n      do not check the mem_ RVFI signals in the monitor\n\n  -R\n      do not check consistency of reg reads and writes\n\n  -P\n      do not check consistency of pc reads and writes\n\n  -A\n      add assert(0) statements to the error handlers\n\n  -Q\n      do not generate $display() statements in error handlers\n\n  -V\n      create $display() statements for printing all insns\n\"\"\" % sys.argv[0])\n    sys.exit(1)\n\ntry:\n    opts, args = getopt.getopt(sys.argv[1:], \"i:p:c:r:aMRPAQV\")\nexcept:\n    usage()\n\nfor o, a in opts:\n    if o == \"-i\":\n        isa = a\n    elif o == \"-p\":\n        prefix = a\n    elif o == \"-c\":\n        channels = int(a)\n    elif o == \"-r\":\n        robdepth = int(a)\n    elif o == \"-a\":\n        aligned = True\n    elif o == \"-M\":\n        ignore_mem = True\n    elif o == \"-R\":\n        noregscheck = True\n    elif o == \"-P\":\n        nopccheck = True\n    elif o == \"-U\":\n        nocausality = True\n    elif o == \"-O\":\n        nocompleteness = True\n    elif o == \"-A\":\n        use_assert = True\n    elif o == \"-Q\":\n        quiet_mode = True\n    elif o == \"-V\":\n        verbose_mode = True\n    else:\n        usage()\n\nif len(args) != 0:\n    usage()\n\nif prefix is None:\n    prefix = \"riscv_formal_monitor_%s\" % isa\n\nif isa.startswith(\"rv32\"):\n    xlen = 32\nelif isa.startswith(\"rv64\"):\n    xlen = 64\nelse:\n    usage()\n\nif ilen is None:\n    ilen = 32\n\nif \"c\" in isa:\n    compressed = True\n\nprint(\"// DO NOT EDIT -- auto-generated from riscv-formal/monitor/generate.py\")\nprint(\"//\")\nprint(\"// Command line options: %s\" % \" \".join(sys.argv[1:]))\nprint()\n\nprint(\"module %s (\" % prefix)\nprint(\"  input clock,\")\nprint(\"  input reset,\")\nprint(\"  input [%d:0] rvfi_valid,\" % (channels-1))\nprint(\"  input [%d:0] rvfi_order,\" % (channels*64-1))\nprint(\"  input [%d:0] rvfi_insn,\" % (channels*32-1))\nprint(\"  input [%d:0] rvfi_trap,\" % (channels-1))\nprint(\"  input [%d:0] rvfi_halt,\" % (channels-1))\nprint(\"  input [%d:0] rvfi_intr,\" % (channels-1))\nprint(\"  input [%d:0] rvfi_mode,\" % (channels*2-1))\nprint(\"  input [%d:0] rvfi_rs1_addr,\" % (channels*5-1))\nprint(\"  input [%d:0] rvfi_rs2_addr,\" % (channels*5-1))\nprint(\"  input [%d:0] rvfi_rs1_rdata,\" % (channels*xlen-1))\nprint(\"  input [%d:0] rvfi_rs2_rdata,\" % (channels*xlen-1))\nprint(\"  input [%d:0] rvfi_rd_addr,\" % (channels*5-1))\nprint(\"  input [%d:0] rvfi_rd_wdata,\" % (channels*xlen-1))\nprint(\"  input [%d:0] rvfi_pc_rdata,\" % (channels*xlen-1))\nprint(\"  input [%d:0] rvfi_pc_wdata,\" % (channels*xlen-1))\nprint(\"  input [%d:0] rvfi_mem_addr,\" % (channels*xlen-1))\nprint(\"  input [%d:0] rvfi_mem_rmask,\" % (channels*xlen//8-1))\nprint(\"  input [%d:0] rvfi_mem_wmask,\" % (channels*xlen//8-1))\nprint(\"  input [%d:0] rvfi_mem_rdata,\" % (channels*xlen-1))\nprint(\"  input [%d:0] rvfi_mem_wdata,\" % (channels*xlen-1))\nprint(\"  input [%d:0] rvfi_mem_extamo,\" % (channels-1))\nprint(\"  output reg [15:0] errcode\")\nprint(\");\")\n\nerrcodes = list()\n\nfor chidx in range(channels):\n    print(\"  wire ch%d_rvfi_valid = rvfi_valid[%d];\" % (chidx, chidx))\n    print(\"  wire [63:0] ch%d_rvfi_order = rvfi_order[%d:%d];\" % (chidx, 64*chidx+63, 64*chidx))\n    print(\"  wire [31:0] ch%d_rvfi_insn = rvfi_insn[%d:%d];\" % (chidx, 32*chidx+31, 32*chidx))\n    print(\"  wire ch%d_rvfi_trap = rvfi_trap[%d];\" % (chidx, chidx))\n    print(\"  wire ch%d_rvfi_halt = rvfi_halt[%d];\" % (chidx, chidx))\n    print(\"  wire ch%d_rvfi_intr = rvfi_intr[%d];\" % (chidx, chidx))\n    print(\"  wire [4:0] ch%d_rvfi_rs1_addr = rvfi_rs1_addr[%d:%d];\" % (chidx, 5*chidx+4, 5*chidx))\n    print(\"  wire [4:0] ch%d_rvfi_rs2_addr = rvfi_rs2_addr[%d:%d];\" % (chidx, 5*chidx+4, 5*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_rs1_rdata = rvfi_rs1_rdata[%d:%d];\" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_rs2_rdata = rvfi_rs2_rdata[%d:%d];\" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx))\n    print(\"  wire [4:0] ch%d_rvfi_rd_addr = rvfi_rd_addr[%d:%d];\" % (chidx, 5*chidx+4, 5*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_rd_wdata = rvfi_rd_wdata[%d:%d];\" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_pc_rdata = rvfi_pc_rdata[%d:%d];\" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_pc_wdata = rvfi_pc_wdata[%d:%d];\" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_mem_addr = rvfi_mem_addr[%d:%d];\" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_mem_rmask = rvfi_mem_rmask[%d:%d];\" % (xlen//8-1, chidx, xlen//8*chidx+xlen//8-1, xlen//8*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_mem_wmask = rvfi_mem_wmask[%d:%d];\" % (xlen//8-1, chidx, xlen//8*chidx+xlen//8-1, xlen//8*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_mem_rdata = rvfi_mem_rdata[%d:%d];\" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx))\n    print(\"  wire [%d:0] ch%d_rvfi_mem_wdata = rvfi_mem_wdata[%d:%d];\" % (xlen-1, chidx, xlen*chidx+xlen-1, xlen*chidx))\n    print(\"  wire ch%d_rvfi_mem_extamo = rvfi_mem_extamo[%d];\" % (chidx, chidx))\n    print()\n\n    print(\"  wire ch%d_spec_valid;\" % (chidx))\n    print(\"  wire ch%d_spec_trap;\" % (chidx))\n    print(\"  wire [4:0] ch%d_spec_rs1_addr;\" % (chidx))\n    print(\"  wire [4:0] ch%d_spec_rs2_addr;\" % (chidx))\n    print(\"  wire [4:0] ch%d_spec_rd_addr;\" % (chidx))\n    print(\"  wire [%d:0] ch%d_spec_rd_wdata;\" % (xlen-1, chidx))\n    print(\"  wire [%d:0] ch%d_spec_pc_wdata;\" % (xlen-1, chidx))\n    print(\"  wire [%d:0] ch%d_spec_mem_addr;\" % (xlen-1, chidx))\n    print(\"  wire [%d:0] ch%d_spec_mem_rmask;\" % (xlen//8-1, chidx))\n    print(\"  wire [%d:0] ch%d_spec_mem_wmask;\" % (xlen//8-1, chidx))\n    print(\"  wire [%d:0] ch%d_spec_mem_wdata;\" % (xlen-1, chidx))\n    print()\n\n    print(\"  %s_isa_spec ch%d_isa_spec (\" % (prefix, chidx))\n    for p in \"\"\"rvfi_valid rvfi_insn rvfi_pc_rdata rvfi_rs1_rdata rvfi_rs2_rdata rvfi_mem_rdata\n                spec_valid spec_trap spec_rs1_addr spec_rs2_addr spec_rd_addr spec_rd_wdata\n                spec_pc_wdata spec_mem_addr spec_mem_rmask spec_mem_wmask spec_mem_wdata\"\"\".split():\n        print(\"    .%s(ch%d_%s)%s\" % (p, chidx, p, \",\" if p != \"spec_mem_wdata\" else \"\"))\n    print(\"  );\")\n    print()\n\n    errcodes.append(\"ch%d_errcode\" % (chidx))\n    print(\"  reg [15:0] ch%d_errcode;\" % (chidx))\n    print()\n\n    print(\"  task ch%d_handle_error;\" % (chidx))\n    print(\"    input [15:0] code;\")\n    print(\"    input [511:0] msg;\")\n    print(\"    begin\")\n\n    if not quiet_mode:\n        print(\"      $display(\\\"-------- RVFI Monitor error %%0d in channel %d: %%m at time %%0t --------\\\", code, $time);\" % (chidx))\n        print(\"      $display(\\\"Error message: %0s\\\", msg);\")\n        for p in \"\"\"rvfi_valid rvfi_order rvfi_insn rvfi_trap rvfi_halt rvfi_intr\n                    rvfi_rs1_addr rvfi_rs2_addr rvfi_rs1_rdata rvfi_rs2_rdata\n                    rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata\n                    rvfi_mem_addr rvfi_mem_rmask rvfi_mem_wmask rvfi_mem_rdata rvfi_mem_wdata\n                    spec_valid spec_trap spec_rs1_addr spec_rs2_addr spec_rd_addr spec_rd_wdata\n                    spec_pc_wdata spec_mem_addr spec_mem_rmask spec_mem_wmask spec_mem_wdata\"\"\".split():\n            print(\"      $display(\\\"%s = %%x\\\", ch%d_%s);\" % (p, chidx, p))\n    print(\"      ch%d_errcode <= code;\" % (chidx))\n\n    if use_assert:\n        print(\"      assert(0);\")\n\n    print(\"    end\")\n    print(\"  endtask\")\n    print()\n\n    print(\"  always @(posedge clock) begin\")\n    print(\"    ch%d_errcode <= 0;\" % (chidx))\n    print(\"    if (!reset && ch%d_rvfi_valid) begin\" % (chidx))\n\n    if verbose_mode:\n        print(\"      $display(\\\"-------- RVFI Monitor insn in channel %d: %%m at time %%0t --------\\\", $time);\" % (chidx))\n        for p in \"\"\"rvfi_valid rvfi_order rvfi_insn rvfi_trap rvfi_halt rvfi_intr\n                    rvfi_rs1_addr rvfi_rs2_addr rvfi_rs1_rdata rvfi_rs2_rdata\n                    rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata\n                    rvfi_mem_addr rvfi_mem_rmask rvfi_mem_wmask rvfi_mem_rdata rvfi_mem_wdata\n                    spec_valid spec_trap\"\"\".split():\n            print(\"      $display(\\\"%s = %%x\\\", ch%d_%s);\" % (p, chidx, p))\n\n    print(\"      if (ch%d_spec_valid) begin\" % (chidx))\n\n    print(\"        if (ch%d_rvfi_trap != ch%d_spec_trap) begin\" % (chidx, chidx))\n    print(\"          ch%d_handle_error(%d, \\\"mismatch in trap\\\");\" % (chidx, 100*(1+chidx)+1))\n    print(\"        end\")\n\n    print(\"        if (ch%d_rvfi_rs1_addr != ch%d_spec_rs1_addr && ch%d_spec_rs1_addr != 0) begin\" % (chidx, chidx, chidx))\n    print(\"          ch%d_handle_error(%d, \\\"mismatch in rs1_addr\\\");\" % (chidx, 100*(1+chidx)+2))\n    print(\"        end\")\n    print(\"        if (ch%d_rvfi_rs2_addr != ch%d_spec_rs2_addr && ch%d_spec_rs2_addr != 0) begin\" % (chidx, chidx, chidx))\n    print(\"          ch%d_handle_error(%d, \\\"mismatch in rs2_addr\\\");\" % (chidx, 100*(1+chidx)+3))\n    print(\"        end\")\n    print(\"        if (ch%d_rvfi_rd_addr != ch%d_spec_rd_addr) begin\" % (chidx, chidx))\n    print(\"          ch%d_handle_error(%d, \\\"mismatch in rd_addr\\\");\" % (chidx, 100*(1+chidx)+4))\n    print(\"        end\")\n\n    if ignore_mem:\n        print(\"        if (ch%d_rvfi_rd_wdata != ch%d_spec_rd_wdata && !ch%d_spec_mem_rmask) begin\" % (chidx, chidx, chidx))\n        print(\"          ch%d_handle_error(%d, \\\"mismatch in rd_wdata\\\");\" % (chidx, 100*(1+chidx)+5))\n        print(\"        end\")\n    else:\n        print(\"        if (ch%d_rvfi_rd_wdata != ch%d_spec_rd_wdata) begin\" % (chidx, chidx))\n        print(\"          ch%d_handle_error(%d, \\\"mismatch in rd_wdata\\\");\" % (chidx, 100*(1+chidx)+5))\n        print(\"        end\")\n\n    print(\"        if (ch%d_rvfi_pc_wdata != ch%d_spec_pc_wdata) begin\" % (chidx, chidx))\n    print(\"          ch%d_handle_error(%d, \\\"mismatch in pc_wdata\\\");\" % (chidx, 100*(1+chidx)+6))\n    print(\"        end\")\n\n    if not ignore_mem:\n        print(\"        if (ch%d_rvfi_mem_wmask != ch%d_spec_mem_wmask) begin\" % (chidx, chidx))\n        print(\"          ch%d_handle_error(%d, \\\"mismatch in mem_wmask\\\");\" % (chidx, 100*(1+chidx)+8))\n        print(\"        end\")\n\n        for i in range(xlen//8):\n            print(\"        if (!ch%d_rvfi_mem_rmask[%d] && ch%d_spec_mem_rmask[%d]) begin\" % (chidx, i, chidx, i))\n            print(\"          ch%d_handle_error(%d, \\\"mismatch in mem_rmask[%d]\\\");\" % (chidx, 100*(1+chidx)+10+i, i))\n            print(\"        end\")\n            print(\"        if (ch%d_rvfi_mem_wmask[%d] && ch%d_rvfi_mem_wdata[%d:%d] != ch%d_spec_mem_wdata[%d:%d]) begin\" % (chidx, i, chidx, 8*i+7, 8*i, chidx, 8*i+7, 8*i))\n            print(\"          ch%d_handle_error(%d, \\\"mismatch in mem_wdata[%d:%d]\\\");\" % (chidx, 100*(1+chidx)+20+i, 8*i+7, 8*i))\n            print(\"        end\")\n\n        print(\"        if (ch%d_rvfi_mem_addr != ch%d_spec_mem_addr && (ch%d_rvfi_mem_wmask || ch%d_rvfi_mem_rmask)) begin\" % (chidx, chidx, chidx, chidx))\n        print(\"          ch%d_handle_error(%d, \\\"mismatch in mem_addr\\\");\" % (chidx, 100*(1+chidx)+7))\n        print(\"        end\")\n\n    print(\"      end\")\n    print(\"    end\")\n    print(\"  end\")\n    print()\n\nif not nopccheck or not noregscheck:\n    for chidx in range(channels):\n        rob_data_width = 3*5 + 5*xlen + 2\n        print(\"  wire rob_i%d_valid;\" % chidx)\n        print(\"  wire [63:0] rob_i%d_order;\" % chidx)\n        print(\"  wire [%d:0] rob_i%d_data;\" % (rob_data_width-1, chidx))\n        print()\n        print(\"  wire rob_o%d_valid;\" % chidx)\n        print(\"  wire [63:0] rob_o%d_order;\" % chidx)\n        print(\"  wire [%d:0] rob_o%d_data;\" % (rob_data_width-1, chidx))\n        print()\n        print(\"  wire ro%d_rvfi_valid = rob_o%d_valid;\" % (chidx, chidx))\n        print(\"  assign rob_i%d_valid = ch%d_rvfi_valid;\" % (chidx, chidx))\n        print()\n        print(\"  wire [63:0] ro%d_rvfi_order = rob_o%d_order;\" % (chidx, chidx))\n        print(\"  assign rob_i%d_order = ch%d_rvfi_order;\" % (chidx, chidx))\n        print()\n\n        cursor = 0\n        for n, w in [(\"rs1_addr\", 5), (\"rs2_addr\", 5), (\"rd_addr\", 5), (\"rs1_rdata\", xlen), (\"rs2_rdata\", xlen),\n                (\"rd_wdata\", xlen), (\"pc_rdata\", xlen), (\"pc_wdata\", xlen), (\"intr\", 1), (\"trap\", 1)]:\n            print(\"  wire [%d:0] ro%d_rvfi_%s = rob_o%d_data[%d:%d];\" % (w-1, chidx, n, chidx, cursor+w-1, cursor))\n            print(\"  assign rob_i%d_data[%d:%d] = ch%d_rvfi_%s;\" % (chidx, cursor+w-1, cursor, chidx, n))\n            print()\n            cursor += w\n\n    errcodes.append(\"rob_errcode\")\n    print(\"  wire [15:0] rob_errcode;\")\n    print()\n\n    print(\"  %s_rob rob (\" % prefix)\n    print(\"    .clock(clock),\")\n    print(\"    .reset(reset),\")\n    for chidx in range(channels):\n        print(\"    .i%d_valid(rob_i%d_valid),\" % (chidx, chidx))\n        print(\"    .i%d_order(rob_i%d_order),\" % (chidx, chidx))\n        print(\"    .i%d_data(rob_i%d_data),\" % (chidx, chidx))\n        print(\"    .o%d_valid(rob_o%d_valid),\" % (chidx, chidx))\n        print(\"    .o%d_order(rob_o%d_order),\" % (chidx, chidx))\n        print(\"    .o%d_data(rob_o%d_data),\" % (chidx, chidx))\n    print(\"    .errcode(rob_errcode)\")\n    print(\"  );\")\n    print()\n\n    if not quiet_mode or use_assert:\n        print(\"  always @(posedge clock) begin\")\n        print(\"    if (!reset && rob_errcode) begin\")\n        if not quiet_mode:\n            print(\"      $display(\\\"-------- RVFI Monitor ROB error %0d: %m at time %0t --------\\\", rob_errcode, $time);\")\n            print(\"      $display(\\\"No details on ROB errors available.\\\");\")\n        if use_assert:\n            print(\"      assert(0);\")\n        print(\"    end\")\n        print(\"  end\")\n        print()\n\nif not nopccheck:\n    print(\"  reg shadow_pc_valid;\")\n    print(\"  reg shadow_pc_trap;\")\n    print(\"  reg [%d:0] shadow_pc;\" % (xlen-1))\n    print()\n\n    for chidx in range(channels):\n        print(\"  reg shadow%d_pc_valid;\" % (chidx))\n        print(\"  reg shadow%d_pc_trap;\" % (chidx))\n        print(\"  reg [%d:0] shadow%d_pc_rdata;\" % (xlen-1, chidx))\n        print()\n\n        errcodes.append(\"ro%d_errcode_p\" % (chidx))\n        print(\"  reg [15:0] ro%d_errcode_p;\" % (chidx))\n        print()\n\n        print(\"  task ro%d_handle_error_p;\" % (chidx))\n        print(\"    input [15:0] code;\")\n        print(\"    input [511:0] msg;\")\n        print(\"    begin\")\n\n        if not quiet_mode:\n            print(\"      $display(\\\"-------- RVFI Monitor error %%0d in reordered channel %d: %%m at time %%0t --------\\\", code, $time);\" % (chidx))\n            print(\"      $display(\\\"Error message: %0s\\\", msg);\")\n            for p in \"\"\"rvfi_valid rvfi_order rvfi_rs1_addr rvfi_rs2_addr rvfi_rs1_rdata rvfi_rs2_rdata\n                        rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_intr rvfi_trap\"\"\".split():\n                print(\"      $display(\\\"%s = %%x\\\", ro%d_%s);\" % (p, chidx, p))\n            for p in \"\"\"pc_valid pc_rdata\"\"\".split():\n                print(\"      $display(\\\"shadow_%s = %%x\\\", shadow%d_%s);\" % (p, chidx, p))\n        print(\"      ro%d_errcode_p <= code;\" % (chidx))\n\n        if use_assert:\n            print(\"      assert(0);\")\n\n        print(\"    end\")\n        print(\"  endtask\")\n        print()\n\n        print(\"  always @* begin\")\n        print(\"    shadow%d_pc_valid = shadow_pc_valid;\" % (chidx))\n        print(\"    shadow%d_pc_trap = shadow_pc_trap;\" % (chidx))\n        print(\"    shadow%d_pc_rdata = shadow_pc;\" % (chidx))\n\n        for i in range(chidx):\n            print(\"    if (!reset && ro%d_rvfi_valid) begin\" % (i))\n            print(\"      shadow%d_pc_valid = !ro%d_rvfi_trap;\" % (chidx, chidx))\n            print(\"      shadow%d_pc_trap = ro%d_rvfi_trap;\" % (chidx, chidx))\n            print(\"      shadow%d_pc_rdata = ro%d_rvfi_pc_wdata;\" % (chidx, i))\n            print(\"    end\")\n\n        print(\"  end\")\n        print()\n\n    print(\"  always @(posedge clock) begin\")\n\n    for chidx in range(channels):\n        print(\"    ro%d_errcode_p <= 0;\" % chidx)\n\n    print(\"    if (reset) begin\")\n    print(\"      shadow_pc_valid <= 0;\")\n    print(\"      shadow_pc_trap <= 0;\")\n    print(\"    end\")\n\n    for chidx in range(channels):\n        print(\"    if (!reset && ro%d_rvfi_valid) begin\" % (chidx))\n        print(\"      if (shadow%d_pc_valid && shadow%d_pc_rdata != ro%d_rvfi_pc_rdata && !ro%d_rvfi_intr) begin\" % (chidx, chidx, chidx, chidx))\n        print(\"        ro%d_handle_error_p(%d, \\\"mismatch with shadow pc\\\");\" % (chidx, 100*(1+chidx)+30))\n        print(\"      end\")\n        print(\"      if (shadow%d_pc_valid && shadow%d_pc_trap && !ro%d_rvfi_intr) begin\" % (chidx, chidx, chidx))\n        print(\"        ro%d_handle_error_p(%d, \\\"expected intr after trap\\\");\" % (chidx, 100*(1+chidx)+33))\n        print(\"      end\")\n        print(\"      shadow_pc_valid <= !ro%d_rvfi_trap;\" % (chidx))\n        print(\"      shadow_pc_trap <= ro%d_rvfi_trap;\" % (chidx))\n        print(\"      shadow_pc <= ro%d_rvfi_pc_wdata;\" % (chidx))\n        print(\"    end\")\n\n    print(\"  end\")\n    print()\n\nif not noregscheck:\n    print(\"  reg [31:0] shadow_xregs_valid;\")\n    print(\"  reg [%d:0] shadow_xregs [0:31];\" % (xlen-1))\n    print()\n\n    for chidx in range(channels):\n        print(\"  reg shadow%d_rs1_valid;\" % (chidx))\n        print(\"  reg shadow%d_rs2_valid;\" % (chidx))\n        print(\"  reg [%d:0] shadow%d_rs1_rdata;\" % (xlen-1, chidx))\n        print(\"  reg [%d:0] shadow%d_rs2_rdata;\" % (xlen-1, chidx))\n        print()\n\n        errcodes.append(\"ro%d_errcode_r\" % (chidx))\n        print(\"  reg [15:0] ro%d_errcode_r;\" % (chidx))\n        print()\n\n        print(\"  task ro%d_handle_error_r;\" % (chidx))\n        print(\"    input [15:0] code;\")\n        print(\"    input [511:0] msg;\")\n        print(\"    begin\")\n\n        if not quiet_mode:\n            print(\"      $display(\\\"-------- RVFI Monitor error %%0d in reordered channel %d: %%m at time %%0t --------\\\", code, $time);\" % (chidx))\n            print(\"      $display(\\\"Error message: %0s\\\", msg);\")\n            for p in \"\"\"rvfi_valid rvfi_order rvfi_rs1_addr rvfi_rs2_addr rvfi_rs1_rdata rvfi_rs2_rdata\n                        rvfi_rd_addr rvfi_rd_wdata rvfi_pc_rdata rvfi_pc_wdata rvfi_intr rvfi_trap\"\"\".split():\n                print(\"      $display(\\\"%s = %%x\\\", ro%d_%s);\" % (p, chidx, p))\n            for p in \"\"\"rs1_valid rs1_rdata rs2_valid rs2_rdata\"\"\".split():\n                print(\"      $display(\\\"shadow_%s = %%x\\\", shadow%d_%s);\" % (p, chidx, p))\n        print(\"      ro%d_errcode_r <= code;\" % (chidx))\n\n        if use_assert:\n            print(\"      assert(0);\")\n\n        print(\"    end\")\n        print(\"  endtask\")\n        print()\n\n        for rs in [\"rs1\", \"rs2\"]:\n            print(\"  always @* begin\")\n            print(\"    shadow%d_%s_valid = 0;\" % (chidx, rs))\n            print(\"    shadow%d_%s_rdata = 0;\" % (chidx, rs))\n            print(\"    if (!reset && ro%d_rvfi_valid) begin\" % (chidx))\n            print(\"      shadow%d_%s_valid = shadow_xregs_valid[ro%d_rvfi_%s_addr];\" % (chidx, rs, chidx, rs))\n            print(\"      shadow%d_%s_rdata = shadow_xregs[ro%d_rvfi_%s_addr];\" % (chidx, rs, chidx, rs))\n\n            for i in range(chidx):\n                print(\"      if (ro%d_rvfi_valid && ro%d_rvfi_rd_addr == ro%d_rvfi_%s_addr) begin\" % (i, i, chidx, rs))\n                print(\"        shadow%d_%s_valid = 1;\" % (chidx, rs))\n                print(\"        shadow%d_%s_rdata = ro%d_rvfi_rd_wdata;\" % (chidx, rs, i))\n                print(\"      end\")\n\n            print(\"    end\")\n            print(\"  end\")\n            print()\n\n    print(\"  always @(posedge clock) begin\")\n\n    for chidx in range(channels):\n        print(\"    ro%d_errcode_r <= 0;\" % chidx)\n\n    print(\"    if (reset) begin\")\n    print(\"      shadow_xregs_valid <= 1;\")\n    print(\"      shadow_xregs[0] <= 0;\")\n    print(\"    end\")\n\n    for chidx in range(channels):\n        print(\"    if (!reset && ro%d_rvfi_valid) begin\" % (chidx))\n        for rs in [\"rs1\", \"rs2\"]:\n            print(\"      if (shadow%d_%s_valid && shadow%d_%s_rdata != ro%d_rvfi_%s_rdata) begin\" % (chidx, rs, chidx, rs, chidx, rs))\n            print(\"        ro%d_handle_error_r(%d, \\\"mismatch with shadow %s\\\");\" % (chidx, 100*(1+chidx)+(31 if rs == \"rs1\" else 32), rs))\n            print(\"      end\")\n        print(\"      shadow_xregs_valid[ro%d_rvfi_rd_addr] <= 1;\" % (chidx))\n        print(\"      shadow_xregs[ro%d_rvfi_rd_addr] <= ro%d_rvfi_rd_wdata;\" % (chidx, chidx))\n        print(\"    end\")\n\n    print(\"  end\")\n    print()\n\nprint(\"  always @(posedge clock) begin\")\nprint(\"    errcode <= 0;\")\nprint(\"    if (!reset) begin\")\n\nfor v in errcodes:\n    print(\"      if (%s) errcode <= %s;\" % (v, v))\n\nprint(\"    end\")\nprint(\"  end\")\nprint(\"endmodule\")\n\n\nif not nopccheck or not noregscheck:\n    print()\n    print(\"module %s_rob (\" % prefix)\n    print(\"  input clock,\")\n    print(\"  input reset,\")\n    for chidx in range(channels):\n        print(\"    input i%d_valid,\" % (chidx))\n        print(\"    input [63:0] i%d_order,\" % (chidx))\n        print(\"    input [%d:0] i%d_data,\" % (rob_data_width-1, chidx))\n        print(\"    output reg o%d_valid,\" % (chidx))\n        print(\"    output reg [63:0] o%d_order,\" % (chidx))\n        print(\"    output reg [%d:0] o%d_data,\" % (rob_data_width-1, chidx))\n    if robdepth == 0:\n        print(\"  output wire [15:0] errcode\")\n    else:\n        print(\"  output reg [15:0] errcode\")\n    print(\");\")\n\n    if robdepth == 0:\n        for chidx in range(channels):\n            print(\"  always @* o%d_valid = i%d_valid;\" % (chidx, chidx))\n            print(\"  always @* o%d_order = i%d_order;\" % (chidx, chidx))\n            print(\"  always @* o%d_data = i%d_data;\" % (chidx, chidx))\n        print(\"  assign errcode = 0;\")\n\n    else:\n        orderbits = ceil(log2(robdepth))\n\n        print(\"  reg [%d:0] buffer [0:%d];\" % (64+rob_data_width-1, robdepth-1))\n        print(\"  reg [%d:0] valid;\" % (robdepth-1))\n        print(\"  reg [63:0] cursor;\")\n        print(\"  reg continue_flag;\")\n        print()\n        print(\"  always @(posedge clock) begin\")\n        for chidx in range(channels):\n            print(\"    o%d_valid <= 0;\" % (chidx))\n        print(\"    errcode <= 0;\")\n        print(\"    continue_flag = 1;\")\n        print(\"    if (reset) begin\")\n        print(\"      valid <= 0;\")\n        print(\"      cursor = 0;\")\n        print(\"    end else begin\")\n\n        for chidx in range(channels):\n            print(\"      if (i%d_valid) begin\" % (chidx))\n            print(\"        if (valid[i%d_order[%d:0]])\" % (chidx, orderbits-1))\n            print(\"          errcode <= 60000 + i%d_order[7:0];\" % (chidx))\n            print(\"        buffer[i%d_order[%d:0]] <= {i%d_data, i%d_order};\" % (chidx, orderbits-1, chidx, chidx))\n            print(\"        valid[i%d_order[%d:0]] <= 1;\" % (chidx, orderbits-1))\n            print(\"      end\")\n\n        for chidx in range(channels):\n            print(\"      if (continue_flag && valid[cursor[%d:0]]) begin\" % (orderbits-1))\n            print(\"        if (buffer[cursor[%d:0]][63:0] != cursor)\" % (orderbits-1))\n            print(\"          errcode <= 61000 + cursor[7:0];\")\n            print(\"        o%d_valid <= 1;\" % (chidx))\n            print(\"        o%d_order <= buffer[cursor[%d:0]][63:0];\" % (chidx, orderbits-1))\n            print(\"        o%d_data <= buffer[cursor[%d:0]][%d:64];\" % (chidx, orderbits-1, 64+rob_data_width-1))\n            print(\"        valid[cursor[%d:0]] <= 0;\" % (orderbits-1))\n            print(\"        cursor = cursor + 1;\")\n            print(\"      end else begin\")\n            print(\"        continue_flag = 0;\")\n            print(\"      end\")\n\n        print(\"    end\")\n        print(\"  end\")\n\n    print(\"endmodule\")\n\n\nreplace_db = list()\nreplace_db.append((\" rvfi_isa_%s \" % isa, \" %s_isa_spec \" % prefix))\nreplace_db.append((\"`RISCV_FORMAL_XLEN\", str(xlen)))\nreplace_db.append((\"`RISCV_FORMAL_ILEN\", str(ilen)))\n\n\ninsn_list = list()\nwith open(\"../insns/isa_%s.txt\" % isa) as f:\n    for insn in f:\n        insn = insn.strip()\n        insn_list.append(insn)\n        replace_db.append((\" rvfi_insn_%s \" % insn, \" %s_insn_%s \" % (prefix, insn)))\n\nexpected_flags = {\n    \"RISCV_FORMAL_COMPRESSED\": compressed,\n    \"RISCV_FORMAL_ALIGNED_MEM\": aligned,\n}\n\ndef print_rewrite_file(filename):\n    with open(filename) as f:\n        flag_stack = []\n        flags = {}\n\n        for line in f:\n            if line.startswith(\"`ifdef \"):\n                flag_name = line.split()[1]\n                assert flag_name not in flags, (filename, flag_name, flags)\n                flag_stack.append(flag_name)\n                flags[flag_name] = True\n                continue\n\n            if line.startswith(\"`ifndef \"):\n                flag_name = line.split()[1]\n                assert flag_name not in flags\n                flag_stack.append(flag_name)\n                flags[flag_name] = False\n                continue\n\n            if line.startswith(\"`else\"):\n                flag_name = flag_stack[-1]\n                flags[flag_name] = not flags[flag_name]\n                continue\n\n            if line.startswith(\"`endif\"):\n                flag_name = flag_stack.pop()\n                del flags[flag_name]\n                continue\n\n            if any(expected_flags.get(name, False) != val for name, val in flags.items()):\n                continue\n\n            for a, b in replace_db:\n                line = line.replace(a, b)\n\n            print(line, end=\"\")\n\nprint()\nprint_rewrite_file(\"../insns/isa_%s.v\" % isa)\n\nfor insn in insn_list:\n    print()\n    print_rewrite_file(\"../insns/insn_%s.v\" % insn)\n\n"
  },
  {
    "path": "tests/coverage/.gitignore",
    "content": "/coverage_rv32\n/coverage_rv64\n/isa_coverage_rv32i.v\n/isa_coverage_rv32ic.v\n/isa_coverage_rv64i.v\n/isa_coverage_rv64ic.v\n"
  },
  {
    "path": "tests/coverage/coverage.sby",
    "content": "[tasks]\nrv32\nrv64\n\n[options]\nmode bmc\ndepth 1\n\n[engines]\nsmtbmc yices\n\n[script]\nverilog_defines -D RISCV_FORMAL\nverilog_defines -D RISCV_FORMAL_NRET=1\nrv32: verilog_defines -D RISCV_FORMAL_XLEN=32\nrv64: verilog_defines -D RISCV_FORMAL_XLEN=64\nverilog_defines -D RISCV_FORMAL_ILEN=32\nverilog_defines -D RISCV_FORMAL_COMPRESSED\nread_verilog -sv rvfi_macros.vh\n\n--pycode-begin--\nimport os\nfor filename in os.listdir(\"../../insns/\"):\n  if filename.startswith(\"insn_\") and filename.endswith(\".v\"):\n    output(\"read_verilog -sv %s\" % filename)\n--pycode-end--\n\nread_verilog isa_coverage_rv32i.v\nread_verilog isa_coverage_rv32ic.v\n\nread_verilog isa_coverage_rv64i.v\nread_verilog isa_coverage_rv64ic.v\n\nread_verilog riscv_rv32i_insn.v\nread_verilog riscv_rv32ic_insn.v\n\nread_verilog riscv_rv64i_insn.v\nread_verilog riscv_rv64ic_insn.v\n\nread_verilog -sv coverage.sv\nrv32: prep -flatten -top coverage32\nrv64: prep -flatten -top coverage64\n\n[files]\ncoverage.sv\n../../checks/rvfi_macros.vh\n\n--pycode-begin--\nimport os\nfor filename in os.listdir(\"../../insns/\"):\n  if filename.startswith(\"insn_\") and filename.endswith(\".v\"):\n    output(\"../../insns/%s\" % filename)\n--pycode-end--\n\nisa_coverage_rv32i.v\nisa_coverage_rv32ic.v\n\nisa_coverage_rv64i.v\nisa_coverage_rv64ic.v\n\nriscv_rv32i_insn.v\nriscv_rv32ic_insn.v\n\nriscv_rv64i_insn.v\nriscv_rv64ic_insn.v\n"
  },
  {
    "path": "tests/coverage/coverage.sv",
    "content": "module coverage32(input [31:0] insn);\n\twire [`ISA_COVERAGE_LEN_RV32I-1:0] insn_valid_rv32i;\n\twire [`ISA_COVERAGE_LEN_RV32IC-1:0] insn_valid_rv32ic;\n\n\twire riscv_rv32i_valid;\n\twire riscv_rv32ic_valid;\n\n\tisa_coverage_rv32i  isa_coverage_rv32i_inst  (.insn(insn), .valid(insn_valid_rv32i ));\n\tisa_coverage_rv32ic isa_coverage_rv32ic_inst (.insn(insn), .valid(insn_valid_rv32ic));\n\n\triscv_rv32i_insn  riscv_rv32i_insn_inst  (.insn(insn), .valid(riscv_rv32i_valid ));\n\triscv_rv32ic_insn riscv_rv32ic_insn_inst (.insn(insn), .valid(riscv_rv32ic_valid));\n\n\talways_comb begin\n\t\t// check one-hot conditions\n\t\tassert(insn_valid_rv32i  == (insn_valid_rv32i  & -insn_valid_rv32i ));\n\t\tassert(insn_valid_rv32ic == (insn_valid_rv32ic & -insn_valid_rv32ic));\n\n\t\t// check insn hierarchy\n\t\tif (insn_valid_rv32i) assert(insn_valid_rv32ic);\n\n\t\t// check hand-written checkers\n\t\tassert(riscv_rv32i_valid == |insn_valid_rv32i);\n\t\tassert(riscv_rv32ic_valid == |insn_valid_rv32ic);\n\tend\nendmodule\n\nmodule coverage64(input [31:0] insn);\n\twire [`ISA_COVERAGE_LEN_RV64I-1:0] insn_valid_rv64i;\n\twire [`ISA_COVERAGE_LEN_RV64IC-1:0] insn_valid_rv64ic;\n\n\twire riscv_rv64i_valid;\n\twire riscv_rv64ic_valid;\n\n\tisa_coverage_rv64i  isa_coverage_rv64i_inst  (.insn(insn), .valid(insn_valid_rv64i ));\n\tisa_coverage_rv64ic isa_coverage_rv64ic_inst (.insn(insn), .valid(insn_valid_rv64ic));\n\n\triscv_rv64i_insn  riscv_rv64i_insn_inst  (.insn(insn), .valid(riscv_rv64i_valid ));\n\triscv_rv64ic_insn riscv_rv64ic_insn_inst (.insn(insn), .valid(riscv_rv64ic_valid));\n\n\talways_comb begin\n\t\t// check one-hot conditions\n\t\tassert(insn_valid_rv64i  == (insn_valid_rv64i  & -insn_valid_rv64i ));\n\t\tassert(insn_valid_rv64ic == (insn_valid_rv64ic & -insn_valid_rv64ic));\n\n\t\t// check insn hierarchy\n\t\tif (insn_valid_rv64i) assert(insn_valid_rv64ic);\n\n\t\t// check hand-written checkers\n\t\tassert(riscv_rv64i_valid == |insn_valid_rv64i);\n\t\tassert(riscv_rv64ic_valid == |insn_valid_rv64ic);\n\tend\nendmodule\n"
  },
  {
    "path": "tests/coverage/generate.py",
    "content": "#!/usr/bin/env python3\n\ndef handle_isa(isa):\n    with open(\"../../insns/isa_%s.txt\" % isa, \"r\") as f:\n        insns = f.read().split()\n\n    with open(\"isa_coverage_%s.v\" % isa, \"w\") as f:\n        print(\"// DO NOT EDIT -- auto-generated from riscv-formal/tests/coverage/generate.py\", file=f)\n        print(\"\", file=f)\n\n        print(\"`define ISA_COVERAGE_LEN_%s %d\" % (isa.upper(), len(insns)), file=f)\n        print(\"module isa_coverage_%s (input [31:0] insn, output [%d:0] valid);\" % (isa, len(insns)-1), file=f)\n\n        for index, insn in enumerate(sorted(insns)):\n            print(\"  rvfi_insn_%s insn_%s (\" % (insn, insn), file=f)\n            print(\"    .rvfi_valid(1'b1),\", file=f)\n            print(\"    .rvfi_insn(insn),\", file=f)\n            print(\"    .rvfi_pc_rdata(32'h00000000),\", file=f)\n            print(\"    .rvfi_rs1_rdata(32'h00000000),\", file=f)\n            print(\"    .rvfi_rs2_rdata(32'h00000000),\", file=f)\n            print(\"    .rvfi_mem_rdata(32'h00000000),\", file=f)\n            print(\"    .spec_valid(valid[%d])\" % index, file=f)\n            print(\"  );\", file=f)\n            \n        print(\"endmodule\", file=f)\n\nhandle_isa(\"rv32i\")\nhandle_isa(\"rv32ic\")\nhandle_isa(\"rv64i\")\nhandle_isa(\"rv64ic\")\n"
  },
  {
    "path": "tests/coverage/riscv_rv32i_insn.v",
    "content": "// Check if a given instruction is an RV32I instruction (without SYSTEM opcode)\n//\nmodule riscv_rv32i_insn (\n\tinput [31:0] insn,\n\toutput reg valid\n);\n\talways @* begin\n\t\tvalid = 0;\n\n\t\tif (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI\n\t\tif (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC\n\t\tif (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL\n\n\t\tif (insn[6:0] == 7'b 11_001_11) begin // JALR\n\t\t\tvalid = insn[14:12] == 3'b 000;\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 11_000_11) begin // BRANCH\n\t\t\tvalid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_000_11) begin // LOAD\n\t\t\tvalid = (insn[14:12] != 3'b 011) && (insn[14:12] != 3'b 110) && (insn[14:12] != 3'b 111);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_000_11) begin // STORE\n\t\t\tvalid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_100_11) begin // OP-IMM\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 001: begin // SLLI\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\t\t3'b 101: begin // SRLI SRAI\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tvalid = 1;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_100_11) begin // OP\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 000, 3'b 101: begin // ADD SUB SRL SRA\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "tests/coverage/riscv_rv32ic_insn.v",
    "content": "// Check if a given instruction is an RV32IC instruction (without SYSTEM opcode)\n//\nmodule riscv_rv32ic_insn (\n\tinput [31:0] insn,\n\toutput reg valid\n);\n\talways @* begin\n\t\tvalid = 0;\n\n\t\tif (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI\n\t\tif (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC\n\t\tif (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL\n\n\t\tif (insn[6:0] == 7'b 11_001_11) begin // JALR\n\t\t\tvalid = insn[14:12] == 3'b 000;\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 11_000_11) begin // BRANCH\n\t\t\tvalid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_000_11) begin // LOAD\n\t\t\tvalid = (insn[14:12] != 3'b 011) && (insn[14:12] != 3'b 110) && (insn[14:12] != 3'b 111);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_000_11) begin // STORE\n\t\t\tvalid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_100_11) begin // OP-IMM\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 001: begin // SLLI\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\t\t3'b 101: begin // SRLI SRAI\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tvalid = 1;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_100_11) begin // OP\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 000, 3'b 101: begin // ADD SUB SRL SRA\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[31:16] == 16'b0 && insn[1:0] != 2'b11) begin\n\t\t\tcasez (insn[15:0])\n\t\t\t\t// RVC -- Quadrant 0\n\t\t\t\t16'b 000_???_???_??_???_00: valid = |insn[12:5];              // C.ADDI4SPN\n\t\t\t\t16'b 010_???_???_??_???_00: valid = 1;                        // C.LW\n\t\t\t\t16'b 110_???_???_??_???_00: valid = 1;                        // C.SW\n\n\t\t\t\t// RVC -- Quadrant 1\n\t\t\t\t16'b 000_?_??_???_??_???_01: valid = 1;                       // C.NOP, C.ADDI\n\t\t\t\t16'b 001_?_??_???_??_???_01: valid = 1;                       // C.JAL\n\t\t\t\t16'b 010_?_??_???_??_???_01: valid = 1;                       // C.LI\n\t\t\t\t16'b 011_?_??_???_??_???_01: valid = |{insn[12], insn[6:2]};  // C.ADDI16SP, C.LUI\n\t\t\t\t16'b 100_?_00_???_??_???_01: valid = !insn[12];               // C.SRLI\n\t\t\t\t16'b 100_?_01_???_??_???_01: valid = !insn[12];               // C.SRAI\n\t\t\t\t16'b 100_?_10_???_??_???_01: valid = 1;                       // C.ANDI\n\t\t\t\t16'b 100_0_11_???_00_???_01: valid = 1;                       // C.SUB\n\t\t\t\t16'b 100_0_11_???_01_???_01: valid = 1;                       // C.XOR\n\t\t\t\t16'b 100_0_11_???_10_???_01: valid = 1;                       // C.OR\n\t\t\t\t16'b 100_0_11_???_11_???_01: valid = 1;                       // C.AND\n\t\t\t\t16'b 101_?_??_???_??_???_01: valid = 1;                       // C.J\n\t\t\t\t16'b 110_?_??_???_??_???_01: valid = 1;                       // C.BEQZ\n\t\t\t\t16'b 111_?_??_???_??_???_01: valid = 1;                       // C.BNEZ\n\n\t\t\t\t// RVC -- Quadrant 2\n\t\t\t\t16'b 000_?_?????_?????_10: valid = !insn[12];                 // C.SLLI\n\t\t\t\t16'b 010_?_?????_?????_10: valid = |insn[11:7];               // C.LWSP\n\t\t\t\t16'b 100_0_?????_00000_10: valid = |insn[11:7];               // C.JR\n\t\t\t\t16'b 100_0_?????_?????_10: valid = |insn[6:2];                // C.MV\n\t\t\t\t16'b 100_1_00000_00000_10: valid = 0;                         // C.EBREAK (SYSTEM => valid=0)\n\t\t\t\t16'b 100_1_?????_?????_10: valid = 1;                         // C.JALR, C.ADD\n\t\t\t\t16'b 110_?_?????_?????_10: valid = 1;                         // C.SWSP\n\t\t\tendcase\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "tests/coverage/riscv_rv64i_insn.v",
    "content": "// Check if a given instruction is an RV64I instruction (without SYSTEM opcode)\n//\nmodule riscv_rv64i_insn (\n\tinput [31:0] insn,\n\toutput reg valid\n);\n\talways @* begin\n\t\tvalid = 0;\n\n\t\tif (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI\n\t\tif (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC\n\t\tif (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL\n\n\t\tif (insn[6:0] == 7'b 11_001_11) begin // JALR\n\t\t\tvalid = insn[14:12] == 3'b 000;\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 11_000_11) begin // BRANCH\n\t\t\tvalid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_000_11) begin // LOAD\n\t\t\tvalid = (insn[14:12] != 3'b 111);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_000_11) begin // STORE\n\t\t\tvalid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010) || (insn[14:12] == 3'b 011);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_100_11) begin // OP-IMM\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 001: begin // SLLI\n\t\t\t\t\tvalid = insn[31:26] == 6'b 000000;\n\t\t\t\tend\n\t\t\t\t3'b 101: begin // SRLI SRAI\n\t\t\t\t\tvalid = (insn[31:26] == 6'b 000000) || (insn[31:26] == 6'b 010000);\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tvalid = 1;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_100_11) begin // OP\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 000, 3'b 101: begin // ADD SUB SRL SRA\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_110_11) begin // OP-IMM-32\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 001: begin // SLLIW\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\t\t3'b 101: begin // SRLIW SRAIW\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\t3'b 000: begin // ADDIW\n\t\t\t\t\tvalid = 1;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_110_11) begin // OP-32\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 000, 3'b 101: begin // ADDW SUBW SRLW SRAW\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\t3'b 001: begin // SLLW\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "tests/coverage/riscv_rv64ic_insn.v",
    "content": "// Check if a given instruction is an RV64IC instruction (without SYSTEM opcode)\n//\nmodule riscv_rv64ic_insn (\n\tinput [31:0] insn,\n\toutput reg valid\n);\n\talways @* begin\n\t\tvalid = 0;\n\n\t\tif (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI\n\t\tif (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC\n\t\tif (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL\n\n\t\tif (insn[6:0] == 7'b 11_001_11) begin // JALR\n\t\t\tvalid = insn[14:12] == 3'b 000;\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 11_000_11) begin // BRANCH\n\t\t\tvalid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_000_11) begin // LOAD\n\t\t\tvalid = (insn[14:12] != 3'b 111);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_000_11) begin // STORE\n\t\t\tvalid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010) || (insn[14:12] == 3'b 011);\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_100_11) begin // OP-IMM\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 001: begin // SLLI\n\t\t\t\t\tvalid = insn[31:26] == 6'b 000000;\n\t\t\t\tend\n\t\t\t\t3'b 101: begin // SRLI SRAI\n\t\t\t\t\tvalid = (insn[31:26] == 6'b 000000) || (insn[31:26] == 6'b 010000);\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tvalid = 1;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_100_11) begin // OP\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 000, 3'b 101: begin // ADD SUB SRL SRA\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\tdefault: begin\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 00_110_11) begin // OP-IMM-32\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 001: begin // SLLIW\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\t\t3'b 101: begin // SRLIW SRAIW\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\t3'b 000: begin // ADDIW\n\t\t\t\t\tvalid = 1;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[6:0] == 7'b 01_110_11) begin // OP-32\n\t\t\tcase (insn[14:12])\n\t\t\t\t3'b 000, 3'b 101: begin // ADDW SUBW SRLW SRAW\n\t\t\t\t\tvalid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000);\n\t\t\t\tend\n\t\t\t\t3'b 001: begin // SLLW\n\t\t\t\t\tvalid = insn[31:25] == 7'b 0000000;\n\t\t\t\tend\n\t\t\tendcase\n\t\tend\n\n\t\tif (insn[31:16] == 16'b0 && insn[1:0] != 2'b11) begin\n\t\t\tcasez (insn[15:0])\n\t\t\t\t// RVC -- Quadrant 0\n\t\t\t\t16'b 000_???_???_??_???_00: valid = |insn[12:5];              // C.ADDI4SPN\n\t\t\t\t16'b 010_???_???_??_???_00: valid = 1;                        // C.LW\n\t\t\t\t16'b 011_???_???_??_???_00: valid = 1;                        // C.LD\n\t\t\t\t16'b 110_???_???_??_???_00: valid = 1;                        // C.SW\n\t\t\t\t16'b 111_???_???_??_???_00: valid = 1;                        // C.SD\n\n\t\t\t\t// RVC -- Quadrant 1\n\t\t\t\t16'b 000_?_??_???_??_???_01: valid = 1;                       // C.NOP, C.ADDI\n\t\t\t\t16'b 001_?_??_???_??_???_01: valid = |insn[11:7];             // C.ADDIW\n\t\t\t\t16'b 010_?_??_???_??_???_01: valid = 1;                       // C.LI\n\t\t\t\t16'b 011_?_??_???_??_???_01: valid = |{insn[12], insn[6:2]};  // C.ADDI16SP, C.LUI\n\t\t\t\t16'b 100_?_00_???_??_???_01: valid = 1;                       // C.SRLI\n\t\t\t\t16'b 100_?_01_???_??_???_01: valid = 1;                       // C.SRAI\n\t\t\t\t16'b 100_?_10_???_??_???_01: valid = 1;                       // C.ANDI\n\t\t\t\t16'b 100_0_11_???_00_???_01: valid = 1;                       // C.SUB\n\t\t\t\t16'b 100_0_11_???_01_???_01: valid = 1;                       // C.XOR\n\t\t\t\t16'b 100_0_11_???_10_???_01: valid = 1;                       // C.OR\n\t\t\t\t16'b 100_0_11_???_11_???_01: valid = 1;                       // C.AND\n\t\t\t\t16'b 100_1_11_???_00_???_01: valid = 1;                       // C.SUBW\n\t\t\t\t16'b 100_1_11_???_01_???_01: valid = 1;                       // C.ADDW\n\t\t\t\t16'b 101_?_??_???_??_???_01: valid = 1;                       // C.J\n\t\t\t\t16'b 110_?_??_???_??_???_01: valid = 1;                       // C.BEQZ\n\t\t\t\t16'b 111_?_??_???_??_???_01: valid = 1;                       // C.BNEZ\n\n\t\t\t\t// RVC -- Quadrant 2\n\t\t\t\t16'b 000_?_?????_?????_10: valid = 1;                         // C.SLLI\n\t\t\t\t16'b 010_?_?????_?????_10: valid = |insn[11:7];               // C.LWSP\n\t\t\t\t16'b 011_?_?????_?????_10: valid = |insn[11:7];               // C.LDSP\n\t\t\t\t16'b 100_0_?????_00000_10: valid = |insn[11:7];               // C.JR\n\t\t\t\t16'b 100_0_?????_?????_10: valid = |insn[6:2];                // C.MV\n\t\t\t\t16'b 100_1_00000_00000_10: valid = 0;                         // C.EBREAK (SYSTEM => valid=0)\n\t\t\t\t16'b 100_1_?????_?????_10: valid = 1;                         // C.JALR, C.ADD\n\t\t\t\t16'b 110_?_?????_?????_10: valid = 1;                         // C.SWSP\n\t\t\t\t16'b 111_?_?????_?????_10: valid = 1;                         // C.SDSP\n\t\t\tendcase\n\t\tend\n\tend\nendmodule\n"
  },
  {
    "path": "tests/semantics/.gitignore",
    "content": "/riscv-semantics\n/insn_*\n"
  },
  {
    "path": "tests/semantics/Makefile",
    "content": "define template\nall:: insn_$(1)/PASS\n\ninsn_$(1)/PASS: insn_$(1).sby riscv-semantics/.stamp\n\tsby -f insn_$(1).sby\n\ninsn_$(1).sby: makejob.py riscv-semantics/.stamp\n\tpython3 makejob.py $(1)\n\nclean::\n\trm -rf insn_$(1) insn_$(1).sby\nendef\n\n$(foreach job,$(shell cat ../../insns/isa_rv32i.txt),$(eval $(call template,$(job))))\n\nriscv-semantics/.stamp:\n\tset -ex; git clone --recursive https://github.com/mit-plv/riscv-semantics; \\\n\tcd riscv-semantics; ./install.sh; ./install-clash.sh; ./make-circuit.sh\n\ttouch riscv-semantics/.stamp\n\ndistclean: clean\n\trm -rf riscv-semantics\n"
  },
  {
    "path": "tests/semantics/cexformat.py",
    "content": "#!/usr/bin/env python3\n\nfrom Verilog_VCD.Verilog_VCD import parse_vcd\nfrom os import system, remove\nfrom sys import argv, exit\nfrom getopt import getopt\n\ndef usage():\n    print(\"Usage: %s <vcd-file>\" % argv[0])\n    exit(1)\n\ntry:\n    opts, args = getopt(argv[1:], \"\", [])\nexcept:\n    usage()\n\nfor o, a in opts:\n    usage()\n\nif len(args) != 1:\n    usage()\n\ndata = dict()\n\nfor netinfo in parse_vcd(args[0]).values():\n    for net in netinfo['nets']:\n        if net[\"hier\"] == \"top\":\n            data[net[\"name\"]] = int(netinfo['tv'][0][1], 2)\n        if net[\"hier\"] == \"top.rvspec_inst\" and (net[\"name\"].startswith(\"in_\") or net[\"name\"].startswith(\"out_\")):\n            data[net[\"name\"]] = int(netinfo['tv'][0][1], 2)\n\nprint()\n\nwith open(\".cexformat_tmp.s\", \"w\") as f:\n    print(\".word 0x%08X\" % data[\"insn\"], file=f)\n\nsystem(\"riscv32-unknown-elf-gcc -c .cexformat_tmp.s\")\nsystem(\"riscv32-unknown-elf-objdump -d -M numeric,no-aliases .cexformat_tmp.o > .cexformat_tmp.t\")\n\nwith open(\".cexformat_tmp.t\") as f:\n    for line in f:\n        if line.startswith(\"   0:\"):\n            s = \"%s   (0x%s)\" % (\" \".join(line.split()[2:]), line.split()[1])\n            print(s)\n            print(\"=\" * len(s))\n\nremove(\".cexformat_tmp.s\")\nremove(\".cexformat_tmp.o\")\nremove(\".cexformat_tmp.t\")\n\nprint()\n\nfor i in range(1, 32):\n    print(\"x%-2d 0x%08X 0x%08X%s\" % (i, data[\"x%d\" % i], data[\"nx%d\" % i], \"\" if data[\"x%d\" % i] == data[\"nx%d\" % i] else \" <--\"))\n\nprint()\n\ndef prvalue(name, nbits):\n    if nbits == 1 or nbits == 5:\n        print(\"%-20s %10d\" % (name, data[name]))\n    elif nbits == 4:\n        print(\"%-20s     0b%s\" % (name, format(data[name], \"04b\")))\n    elif nbits == 32:\n        print(\"%-20s 0x%08X\" % (name, data[name]))\n    else:\n        assert False\n\nprvalue(\"rvfi_valid\",      1)\nprvalue(\"rvfi_insn\",      32)\nprvalue(\"rvfi_rs1_rdata\", 32)\nprvalue(\"rvfi_rs2_rdata\", 32)\n\nprint()\n\nprvalue(\"spec_valid\",      1)\nprvalue(\"spec_trap\",       1)\nprvalue(\"spec_rs1_addr\",   5)\nprvalue(\"spec_rs2_addr\",   5)\nprvalue(\"spec_rd_addr\",    5)\nprvalue(\"spec_rd_wdata\",  32)\n\nprint()\n\nprvalue(\"rvfi_pc_rdata\",  32)\nprvalue(\"spec_pc_wdata\",  32)\n\nprint()\n\nprvalue(\"spec_mem_rmask\",  4)\nprvalue(\"spec_mem_wmask\",  4)\nprvalue(\"spec_mem_addr\",  32)\nprvalue(\"rvfi_mem_rdata\", 32)\nprvalue(\"spec_mem_wdata\", 32)\n\nprint()\n\nprvalue(\"in_instr\", 32)\nprvalue(\"in_pc\", 32)\nprvalue(\"out_nextPC\", 32)\nprvalue(\"out_exception\", 1)\n\nprint()\n\nprvalue(\"out_storeEnable\", 4)\nprvalue(\"out_storeAddress\", 32)\nprvalue(\"out_storeData\", 32)\n\nprint()\n\nprvalue(\"out_loadEnable\", 4)\nprvalue(\"out_loadAddress\", 32)\nprvalue(\"in_loadData\", 32)\n\nprint()\nprint(\"--------\")\nprint()\n\nprint(\"let in_instr = fromIntegral 0x%08X\" % data[\"insn\"])\nprint(\"let in_loadData = fromIntegral 0x%08X\" % data[\"rdata\"])\n\nif data[\"spec_rs1_addr\"]:\n    print(\"let register_rs1 = Just (%d, fromIntegral 0x%08X)\" % (data[\"spec_rs1_addr\"], data[\"rvfi_rs1_rdata\"]))\nelse:\n    print(\"let register_rs1 = Nothing\")\n\nif data[\"spec_rs2_addr\"]:\n    print(\"let register_rs2 = Just (%d, fromIntegral 0x%08X)\" % (data[\"spec_rs2_addr\"], data[\"rvfi_rs2_rdata\"]))\nelse:\n    print(\"let register_rs2 = Nothing\")\n\nprint()\n\nif data[\"spec_mem_wmask\"]:\n    print(\"let expected_out_store = Just (fromIntegral 0x%08X, fromIntegral 0x%08X)\" % (data[\"spec_mem_addr\"], data[\"spec_mem_wdata\"]))\nelse:\n    print(\"let expected_out_store = Nothing\")\n\nif data[\"spec_rd_addr\"]:\n    print(\"let expected_rd = Just (%d, fromIntegral 0x%08X)\" % (data[\"spec_rd_addr\"], data[\"spec_rd_wdata\"]))\nelse:\n    print(\"let expected_rd = Nothing\")\n\nif data[\"spec_mem_rmask\"]:\n    print(\"let expected_out_loadAddress = Just (fromIntegral 0x%08X)\" % data[\"spec_mem_addr\"])\nelse:\n    print(\"let expected_out_loadAddress = Nothing\")\n\nprint(\"let expected_out_exception = %s\" % (\"True\" if data[\"spec_trap\"] else \"False\"))\n\nprint()\n\n"
  },
  {
    "path": "tests/semantics/makejob.py",
    "content": "#!/usr/bin/env python3\n\nimport sys, glob, os\n\ninsn = sys.argv[1]\nclash_files = glob.glob(\"riscv-semantics/src/verilog/Clash/rvspec/*.v\")\n\nwith open(\"insn_%s.sby\" % insn, \"w\") as f:\n    print(\"[options]\", file=f)\n    print(\"mode bmc\", file=f)\n    print(\"depth 1\", file=f)\n    print(\"\", file=f)\n\n    print(\"[engines]\", file=f)\n    print(\"smtbmc boolector\", file=f)\n    print(\"\", file=f)\n\n    print(\"[script]\", file=f)\n    print(\"read_verilog -sv defines.vh\", file=f)\n    print(\"read_verilog -sv rvfi_macros.vh\", file=f)\n    print(\"read_verilog -sv top.sv\", file=f)\n    print(\"read_verilog -sv insn_%s.v\" % insn, file=f)\n    for fn in clash_files:\n        print(\"read_verilog %s\" % os.path.basename(fn), file=f)\n    print(\"prep -nordff -top top\", file=f)\n    print(\"flatten rvspec\", file=f)\n    print(\"hierarchy\", file=f)\n    print(\"opt -fast\", file=f)\n\n    print(\"[file defines.vh]\", file=f)\n    print(\"`define RISCV_FORMAL\", file=f)\n    print(\"`define RISCV_FORMAL_XLEN 32\", file=f)\n    print(\"`define RISCV_FORMAL_ILEN 32\", file=f)\n    print(\"`define RISCV_FORMAL_INSN_MODEL rvfi_insn_%s\" % insn, file=f)\n    print(\"`define RISCV_FORMAL_ALIGNED_MEM\", file=f)\n    # print(\"`define RISCV_FORMAL_COMPRESSED\", file=f)\n    print(\"\", file=f)\n\n    print(\"[files]\", file=f)\n    print(\"top.sv\", file=f)\n    print(\"../../checks/rvfi_macros.vh\", file=f)\n    print(\"../../insns/insn_%s.v\" % insn, file=f)\n    for fn in clash_files:\n        print(fn, file=f)\n"
  },
  {
    "path": "tests/semantics/top.sv",
    "content": "module top (\n\tinput [31:0] insn, pc, rdata, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,\n\tinput [31:0] x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31\n);\n\t(* keep *) wire [31:0] npc, nx1, nx2, nx3, nx4, nx5, nx6, nx7, nx8, nx9, nx10, nx11, nx12, nx13, nx14, nx15;\n\t(* keep *) wire [31:0] nx16, nx17, nx18, nx19, nx20, nx21, nx22, nx23, nx24, nx25, nx26, nx27, nx28, nx29, nx30, nx31;\n\n\t(* keep *) wire [ 3:0] ren;\n\t(* keep *) wire [31:0] raddr;\n\n\t(* keep *) wire [ 3:0] wen;\n\t(* keep *) wire [31:0] waddr;\n\t(* keep *) wire [31:0] wdata;\n\n\t(* keep *) wire        excep;\n\n\t(* keep *) wire        rvfi_valid = 1;\n\t(* keep *) wire [31:0] rvfi_insn = insn;\n\t(* keep *) wire [31:0] rvfi_pc_rdata = pc;\n\t(* keep *) reg  [31:0] rvfi_rs1_rdata;\n\t(* keep *) reg  [31:0] rvfi_rs2_rdata;\n\t(* keep *) wire [31:0] rvfi_mem_rdata = rdata;\n\n\t(* keep *) wire        spec_valid;\n\t(* keep *) wire        spec_trap;\n\t(* keep *) wire [ 4:0] spec_rs1_addr;\n\t(* keep *) wire [ 4:0] spec_rs2_addr;\n\t(* keep *) wire [ 4:0] spec_rd_addr;\n\t(* keep *) wire [31:0] spec_rd_wdata;\n\t(* keep *) wire [31:0] spec_pc_wdata;\n\t(* keep *) wire [31:0] spec_mem_addr;\n\t(* keep *) wire [ 3:0] spec_mem_rmask;\n\t(* keep *) wire [ 3:0] spec_mem_wmask;\n\t(* keep *) wire [31:0] spec_mem_wdata;\n\n\talways @* begin\n\t\tassume (pc[1:0] == 0);\n\tend\n\n\talways @* begin\n\t\trvfi_rs1_rdata = 0;\n\t\tcase (spec_rs1_addr)\n\t\t\t 1: rvfi_rs1_rdata =  x1;\n\t\t\t 2: rvfi_rs1_rdata =  x2;\n\t\t\t 3: rvfi_rs1_rdata =  x3;\n\t\t\t 4: rvfi_rs1_rdata =  x4;\n\t\t\t 5: rvfi_rs1_rdata =  x5;\n\t\t\t 6: rvfi_rs1_rdata =  x6;\n\t\t\t 7: rvfi_rs1_rdata =  x7;\n\t\t\t 8: rvfi_rs1_rdata =  x8;\n\t\t\t 9: rvfi_rs1_rdata =  x9;\n\t\t\t10: rvfi_rs1_rdata = x10;\n\t\t\t11: rvfi_rs1_rdata = x11;\n\t\t\t12: rvfi_rs1_rdata = x12;\n\t\t\t13: rvfi_rs1_rdata = x13;\n\t\t\t14: rvfi_rs1_rdata = x14;\n\t\t\t15: rvfi_rs1_rdata = x15;\n\t\t\t16: rvfi_rs1_rdata = x16;\n\t\t\t17: rvfi_rs1_rdata = x17;\n\t\t\t18: rvfi_rs1_rdata = x18;\n\t\t\t19: rvfi_rs1_rdata = x19;\n\t\t\t20: rvfi_rs1_rdata = x20;\n\t\t\t21: rvfi_rs1_rdata = x21;\n\t\t\t22: rvfi_rs1_rdata = x22;\n\t\t\t23: rvfi_rs1_rdata = x23;\n\t\t\t24: rvfi_rs1_rdata = x24;\n\t\t\t25: rvfi_rs1_rdata = x25;\n\t\t\t26: rvfi_rs1_rdata = x26;\n\t\t\t27: rvfi_rs1_rdata = x27;\n\t\t\t28: rvfi_rs1_rdata = x28;\n\t\t\t29: rvfi_rs1_rdata = x29;\n\t\t\t30: rvfi_rs1_rdata = x30;\n\t\t\t31: rvfi_rs1_rdata = x31;\n\t\tendcase\n\n\t\trvfi_rs2_rdata = 0;\n\t\tcase (spec_rs2_addr)\n\t\t\t 1: rvfi_rs2_rdata =  x1;\n\t\t\t 2: rvfi_rs2_rdata =  x2;\n\t\t\t 3: rvfi_rs2_rdata =  x3;\n\t\t\t 4: rvfi_rs2_rdata =  x4;\n\t\t\t 5: rvfi_rs2_rdata =  x5;\n\t\t\t 6: rvfi_rs2_rdata =  x6;\n\t\t\t 7: rvfi_rs2_rdata =  x7;\n\t\t\t 8: rvfi_rs2_rdata =  x8;\n\t\t\t 9: rvfi_rs2_rdata =  x9;\n\t\t\t10: rvfi_rs2_rdata = x10;\n\t\t\t11: rvfi_rs2_rdata = x11;\n\t\t\t12: rvfi_rs2_rdata = x12;\n\t\t\t13: rvfi_rs2_rdata = x13;\n\t\t\t14: rvfi_rs2_rdata = x14;\n\t\t\t15: rvfi_rs2_rdata = x15;\n\t\t\t16: rvfi_rs2_rdata = x16;\n\t\t\t17: rvfi_rs2_rdata = x17;\n\t\t\t18: rvfi_rs2_rdata = x18;\n\t\t\t19: rvfi_rs2_rdata = x19;\n\t\t\t20: rvfi_rs2_rdata = x20;\n\t\t\t21: rvfi_rs2_rdata = x21;\n\t\t\t22: rvfi_rs2_rdata = x22;\n\t\t\t23: rvfi_rs2_rdata = x23;\n\t\t\t24: rvfi_rs2_rdata = x24;\n\t\t\t25: rvfi_rs2_rdata = x25;\n\t\t\t26: rvfi_rs2_rdata = x26;\n\t\t\t27: rvfi_rs2_rdata = x27;\n\t\t\t28: rvfi_rs2_rdata = x28;\n\t\t\t29: rvfi_rs2_rdata = x29;\n\t\t\t30: rvfi_rs2_rdata = x30;\n\t\t\t31: rvfi_rs2_rdata = x31;\n\t\tendcase\n\tend\n\n\talways @* begin\n\t\tif (spec_valid) begin\n\t\t\tif (spec_trap) begin\n\t\t\t\tassert ( nx1 ==  x1);\n\t\t\t\tassert ( nx2 ==  x2);\n\t\t\t\tassert ( nx3 ==  x3);\n\t\t\t\tassert ( nx4 ==  x4);\n\t\t\t\tassert ( nx5 ==  x5);\n\t\t\t\tassert ( nx6 ==  x6);\n\t\t\t\tassert ( nx7 ==  x7);\n\t\t\t\tassert ( nx8 ==  x8);\n\t\t\t\tassert ( nx9 ==  x9);\n\t\t\t\tassert (nx10 == x10);\n\t\t\t\tassert (nx11 == x11);\n\t\t\t\tassert (nx12 == x12);\n\t\t\t\tassert (nx13 == x13);\n\t\t\t\tassert (nx14 == x14);\n\t\t\t\tassert (nx15 == x15);\n\t\t\t\tassert (nx16 == x16);\n\t\t\t\tassert (nx17 == x17);\n\t\t\t\tassert (nx18 == x18);\n\t\t\t\tassert (nx19 == x19);\n\t\t\t\tassert (nx20 == x20);\n\t\t\t\tassert (nx21 == x21);\n\t\t\t\tassert (nx22 == x22);\n\t\t\t\tassert (nx23 == x23);\n\t\t\t\tassert (nx24 == x24);\n\t\t\t\tassert (nx25 == x25);\n\t\t\t\tassert (nx26 == x26);\n\t\t\t\tassert (nx27 == x27);\n\t\t\t\tassert (nx28 == x28);\n\t\t\t\tassert (nx29 == x29);\n\t\t\t\tassert (nx30 == x30);\n\t\t\t\tassert (nx31 == x31);\n\t\t\t\tassert (npc == 32'h0);\n\t\t\t\tassert (ren == 1'b0);\n\t\t\t\tassert (wen == 1'b0);\n\t\t\t\tassert (excep);\n\t\t\tend else begin\n\t\t\t\tassert ( nx1 == (spec_rd_addr ==  1 ? spec_rd_wdata :  x1));\n\t\t\t\tassert ( nx2 == (spec_rd_addr ==  2 ? spec_rd_wdata :  x2));\n\t\t\t\tassert ( nx3 == (spec_rd_addr ==  3 ? spec_rd_wdata :  x3));\n\t\t\t\tassert ( nx4 == (spec_rd_addr ==  4 ? spec_rd_wdata :  x4));\n\t\t\t\tassert ( nx5 == (spec_rd_addr ==  5 ? spec_rd_wdata :  x5));\n\t\t\t\tassert ( nx6 == (spec_rd_addr ==  6 ? spec_rd_wdata :  x6));\n\t\t\t\tassert ( nx7 == (spec_rd_addr ==  7 ? spec_rd_wdata :  x7));\n\t\t\t\tassert ( nx8 == (spec_rd_addr ==  8 ? spec_rd_wdata :  x8));\n\t\t\t\tassert ( nx9 == (spec_rd_addr ==  9 ? spec_rd_wdata :  x9));\n\t\t\t\tassert (nx10 == (spec_rd_addr == 10 ? spec_rd_wdata : x10));\n\t\t\t\tassert (nx11 == (spec_rd_addr == 11 ? spec_rd_wdata : x11));\n\t\t\t\tassert (nx12 == (spec_rd_addr == 12 ? spec_rd_wdata : x12));\n\t\t\t\tassert (nx13 == (spec_rd_addr == 13 ? spec_rd_wdata : x13));\n\t\t\t\tassert (nx14 == (spec_rd_addr == 14 ? spec_rd_wdata : x14));\n\t\t\t\tassert (nx15 == (spec_rd_addr == 15 ? spec_rd_wdata : x15));\n\t\t\t\tassert (nx16 == (spec_rd_addr == 16 ? spec_rd_wdata : x16));\n\t\t\t\tassert (nx17 == (spec_rd_addr == 17 ? spec_rd_wdata : x17));\n\t\t\t\tassert (nx18 == (spec_rd_addr == 18 ? spec_rd_wdata : x18));\n\t\t\t\tassert (nx19 == (spec_rd_addr == 19 ? spec_rd_wdata : x19));\n\t\t\t\tassert (nx20 == (spec_rd_addr == 20 ? spec_rd_wdata : x20));\n\t\t\t\tassert (nx21 == (spec_rd_addr == 21 ? spec_rd_wdata : x21));\n\t\t\t\tassert (nx22 == (spec_rd_addr == 22 ? spec_rd_wdata : x22));\n\t\t\t\tassert (nx23 == (spec_rd_addr == 23 ? spec_rd_wdata : x23));\n\t\t\t\tassert (nx24 == (spec_rd_addr == 24 ? spec_rd_wdata : x24));\n\t\t\t\tassert (nx25 == (spec_rd_addr == 25 ? spec_rd_wdata : x25));\n\t\t\t\tassert (nx26 == (spec_rd_addr == 26 ? spec_rd_wdata : x26));\n\t\t\t\tassert (nx27 == (spec_rd_addr == 27 ? spec_rd_wdata : x27));\n\t\t\t\tassert (nx28 == (spec_rd_addr == 28 ? spec_rd_wdata : x28));\n\t\t\t\tassert (nx29 == (spec_rd_addr == 29 ? spec_rd_wdata : x29));\n\t\t\t\tassert (nx30 == (spec_rd_addr == 30 ? spec_rd_wdata : x30));\n\t\t\t\tassert (nx31 == (spec_rd_addr == 31 ? spec_rd_wdata : x31));\n\t\t\t\tassert (npc == spec_pc_wdata);\n\t\t\t\tassert (ren == spec_mem_rmask);\n\t\t\t\tassert (wen == spec_mem_wmask);\n\t\t\t\tif (spec_mem_rmask) begin\n\t\t\t\t\tassert (raddr == spec_mem_addr);\n\t\t\t\tend\n\t\t\t\tif (spec_mem_wmask) begin\n\t\t\t\t\tassert (waddr == spec_mem_addr);\n\t\t\t\t\tif (spec_mem_wmask[0]) assert (wdata[ 7: 0] == spec_mem_wdata[ 7: 0]);\n\t\t\t\t\tif (spec_mem_wmask[1]) assert (wdata[15: 8] == spec_mem_wdata[15: 8]);\n\t\t\t\t\tif (spec_mem_wmask[2]) assert (wdata[23:16] == spec_mem_wdata[23:16]);\n\t\t\t\t\tif (spec_mem_wmask[3]) assert (wdata[31:24] == spec_mem_wdata[31:24]);\n\t\t\t\tend\n\t\t\t\tassert (!excep);\n\t\t\tend\n\t\tend\n\tend\n\n\t`RISCV_FORMAL_INSN_MODEL model (\n\t\t.rvfi_valid     (rvfi_valid    ),\n\t\t.rvfi_insn      (rvfi_insn     ),\n\t\t.rvfi_pc_rdata  (rvfi_pc_rdata ),\n\t\t.rvfi_rs1_rdata (rvfi_rs1_rdata),\n\t\t.rvfi_rs2_rdata (rvfi_rs2_rdata),\n\t\t.rvfi_mem_rdata (rvfi_mem_rdata),\n\t\t.spec_valid     (spec_valid    ),\n\t\t.spec_trap      (spec_trap     ),\n\t\t.spec_rs1_addr  (spec_rs1_addr ),\n\t\t.spec_rs2_addr  (spec_rs2_addr ),\n\t\t.spec_rd_addr   (spec_rd_addr  ),\n\t\t.spec_rd_wdata  (spec_rd_wdata ),\n\t\t.spec_pc_wdata  (spec_pc_wdata ),\n\t\t.spec_mem_addr  (spec_mem_addr ),\n\t\t.spec_mem_rmask (spec_mem_rmask),\n\t\t.spec_mem_wmask (spec_mem_wmask),\n\t\t.spec_mem_wdata (spec_mem_wdata),\n\t);\n\n\trvspec rvspec_inst (\n\t\t.in_instr         ( insn),\n\t\t.in_pc            (   pc),\n\t\t.out_nextPC       (  npc),\n\t\t.out_exception    (excep),\n\n\t\t.out_loadEnable   (  ren),\n\t\t.out_loadAddress  (raddr),\n\t\t.in_loadData      (rdata),\n\n\t\t.out_storeEnable  (  wen),\n\t\t.out_storeAddress (waddr),\n\t\t.out_storeData    (wdata),\n\n\t\t.in_registers ({\n\t\t\tx31, x30, x29, x28, x27, x26, x25, x24, x23, x22, x21, x20, x19, x18, x17,\n\t\t\tx16, x15, x14, x13, x12, x11, x10, x9, x8, x7, x6, x5, x4, x3, x2, x1\n\t\t}),\n\n\t\t.out_registers ({\n\t\t\tnx31, nx30, nx29, nx28, nx27, nx26, nx25, nx24, nx23, nx22, nx21, nx20, nx19, nx18, nx17,\n\t\t\tnx16, nx15, nx14, nx13, nx12, nx11, nx10, nx9, nx8, nx7, nx6, nx5, nx4, nx3, nx2, nx1\n\t\t})\n\t);\nendmodule\n"
  },
  {
    "path": "tests/spike/.gitignore",
    "content": "test_*.cc\ntest_*.h\ntest_*.ok\ntest_*.v\ntest_*.yslog\ntest_*.cbmc_out\nriscv-isa-sim\nmakefile\n"
  },
  {
    "path": "tests/spike/common.h",
    "content": "\n#define require_extension(_ext) do { } while (0)\n#define require(_expression) do { if (!(_expression)) valid = false; } while (0)\n\nstruct mmu_t\n{\n\tuint64_t rdata, wdata, addr;\n\tint8_t optype; // width in bytes, negative for write\n\n\tuint8_t load_uint8(uint64_t a) {\n\t\tassert(optype == 0);\n\t\taddr = a, optype = 1;\n\t\treturn rdata;\n\t}\n\n\tuint16_t load_uint16(uint64_t a) {\n\t\tassert(optype == 0);\n\t\taddr = a, optype = 2;\n\t\treturn rdata;\n\t}\n\n\tuint32_t load_uint32(uint64_t a) {\n\t\tassert(optype == 0);\n\t\taddr = a, optype = 4;\n\t\treturn rdata;\n\t}\n\n\tuint64_t load_uint64(uint64_t a) {\n\t\tassert(optype == 0);\n\t\taddr = a, optype = 8;\n\t\treturn rdata;\n\t}\n\n\tvoid store_uint8(uint64_t a, uint8_t d) {\n\t\tassert(optype == 0);\n\t\taddr = a, wdata = d, optype = -1;\n\t}\n\n\tvoid store_uint16(uint64_t a, uint16_t d) {\n\t\tassert(optype == 0);\n\t\taddr = a, wdata = d, optype = -2;\n\t}\n\n\tvoid store_uint32(uint64_t a, uint32_t d) {\n\t\tassert(optype == 0);\n\t\taddr = a, wdata = d, optype = -4;\n\t}\n\n\tvoid store_uint64(uint64_t a, uint64_t d) {\n\t\tassert(optype == 0);\n\t\taddr = a, wdata = d, optype = -8;\n\t}\n\n\tint8_t load_int8(uint64_t a) {\n\t\treturn load_uint8(a);\n\t}\n\n\tint16_t load_int16(uint64_t a) {\n\t\treturn load_uint16(a);\n\t}\n\n\tint32_t load_int32(uint64_t a) {\n\t\treturn load_uint32(a);\n\t}\n\n\tint64_t load_int64(uint64_t a) {\n\t\treturn load_uint64(a);\n\t}\n};\n\n// ----- from riscv-isa-sim/riscv/decode.h with minor edits -----\n\ntypedef int64_t sreg_t;\ntypedef uint64_t reg_t;\ntypedef uint64_t freg_t;\n\nconst int NXPR = 32;\nconst int NFPR = 32;\nconst int NCSR = 4096;\n\n#define X_RA 1\n#define X_SP 2\n\n#define FP_RD_NE  0\n#define FP_RD_0   1\n#define FP_RD_DN  2\n#define FP_RD_UP  3\n#define FP_RD_NMM 4\n\n#define FSR_RD_SHIFT 5\n#define FSR_RD   (0x7 << FSR_RD_SHIFT)\n\n#define FPEXC_NX 0x01\n#define FPEXC_UF 0x02\n#define FPEXC_OF 0x04\n#define FPEXC_DZ 0x08\n#define FPEXC_NV 0x10\n\n#define FSR_AEXC_SHIFT 0\n#define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)\n#define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)\n#define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)\n#define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)\n#define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)\n#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)\n\n#define insn_length(x) \\\n  (((x) & 0x03) < 0x03 ? 2 : \\\n   ((x) & 0x1f) < 0x1f ? 4 : \\\n   ((x) & 0x3f) < 0x3f ? 6 : \\\n   8)\n#define MAX_INSN_LENGTH 8\n#define PC_ALIGN 2\n\ntypedef uint64_t insn_bits_t;\nclass insn_t\n{\npublic:\n  insn_t() { b = 0; }\n  insn_t(insn_bits_t bits) : b(bits) {}\n  insn_bits_t bits() { return b; }\n  int length() { return insn_length(b); }\n  int64_t i_imm() { return int64_t(b) >> 20; }\n  int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }\n  int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }\n  int64_t u_imm() { return int64_t(b) >> 12 << 12; }\n  int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }\n  uint64_t rd() { return x(7, 5); }\n  uint64_t rs1() { return x(15, 5); }\n  uint64_t rs2() { return x(20, 5); }\n  uint64_t rs3() { return x(27, 5); }\n  uint64_t rm() { return x(12, 3); }\n  uint64_t csr() { return x(20, 12); }\n\n  int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }\n  int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); }\n  int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }\n  int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); }\n  int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }\n  int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }\n  int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }\n  int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }\n  int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }\n  int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }\n  int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); }\n  int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); }\n  int64_t rvc_simm3() { return x(10, 3); }\n  uint64_t rvc_rd() { return rd(); }\n  uint64_t rvc_rs1() { return rd(); }\n  uint64_t rvc_rs2() { return x(2, 5); }\n  uint64_t rvc_rs1s() { return 8 + x(7, 3); }\n  uint64_t rvc_rs2s() { return 8 + x(2, 3); }\n//private:\n  insn_bits_t b;\n  uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }\n  uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }\n  uint64_t imm_sign() { return xs(63, 1); }\n};\n\n// helpful macros, etc\n#define MMU (mmu)\n#define STATE (post_state)\n#define READ_REG(reg) STATE.XPR[reg]\n#define READ_FREG(reg) STATE.FPR[reg]\n#define RS1 READ_REG(insn.rs1())\n#define RS2 READ_REG(insn.rs2())\n#define WRITE_RD(value) WRITE_REG(insn.rd(), value)\n\n#define WRITE_REG(reg, value) do { reg_t v = value; STATE.XPR[reg] = reg ? v : 0; } while (0)\n#define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, value)\n\n// RVC macros\n#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)\n#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)\n#define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)\n#define RVC_RS1 READ_REG(insn.rvc_rs1())\n#define RVC_RS2 READ_REG(insn.rvc_rs2())\n#define RVC_RS1S READ_REG(insn.rvc_rs1s())\n#define RVC_RS2S READ_REG(insn.rvc_rs2s())\n#define RVC_FRS2 READ_FREG(insn.rvc_rs2())\n#define RVC_FRS2S READ_FREG(insn.rvc_rs2s())\n#define RVC_SP READ_REG(X_SP)\n\n// FPU macros\n#define FRS1 READ_FREG(insn.rs1())\n#define FRS2 READ_FREG(insn.rs2())\n#define FRS3 READ_FREG(insn.rs3())\n#define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))\n#define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))\n#define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)\n#define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)\n\n#define SHAMT (insn.i_imm() & 0x3F)\n#define BRANCH_TARGET (pc + insn.sb_imm())\n#define JUMP_TARGET (pc + insn.uj_imm())\n#define RM ({ int rm = insn.rm(); \\\n              if(rm == 7) rm = STATE.frm; \\\n              if(rm > 4) throw trap_illegal_instruction(); \\\n              rm; })\n\n#define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))\n#define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))\n\n#define sext32(x) ((sreg_t)(int32_t)(x))\n#define zext32(x) ((reg_t)(uint32_t)(x))\n#define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))\n#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))\n\n#define set_pc(x) do { STATE.pc = x; } while (0)\n\n\n// ----- from riscv-isa-sim/riscv/processor.h with minor edits -----\n\ntypedef struct\n{\n  uint8_t prv;\n  bool step;\n  bool ebreakm;\n  bool ebreakh;\n  bool ebreaks;\n  bool ebreaku;\n  bool halt;\n  uint8_t cause;\n} dcsr_t;\n\n// typedef enum\n// {\n//   ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION,\n//   ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE,\n//   ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START,\n//   ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP,\n//   ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT\n// } mcontrol_action_t;\n//\n// typedef enum\n// {\n//   MATCH_EQUAL = MCONTROL_MATCH_EQUAL,\n//   MATCH_NAPOT = MCONTROL_MATCH_NAPOT,\n//   MATCH_GE = MCONTROL_MATCH_GE,\n//   MATCH_LT = MCONTROL_MATCH_LT,\n//   MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW,\n//   MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH\n// } mcontrol_match_t;\n//\n// typedef struct\n// {\n//   uint8_t type;\n//   bool dmode;\n//   uint8_t maskmax;\n//   bool select;\n//   bool timing;\n//   mcontrol_action_t action;\n//   bool chain;\n//   mcontrol_match_t match;\n//   bool m;\n//   bool h;\n//   bool s;\n//   bool u;\n//   bool execute;\n//   bool store;\n//   bool load;\n// } mcontrol_t;\n\n// architectural state of a RISC-V hart\nstruct state_t\n{\n  void reset();\n\n  static const int num_triggers = 4;\n\n  reg_t pc;\n  reg_t XPR[NXPR];\n  freg_t FPR[NFPR];\n\n  // control and status registers\n  reg_t prv;    // TODO: Can this be an enum instead?\n  reg_t mstatus;\n  reg_t mepc;\n  reg_t mbadaddr;\n  reg_t mscratch;\n  reg_t mtvec;\n  reg_t mcause;\n  reg_t minstret;\n  reg_t mie;\n  reg_t mip;\n  reg_t medeleg;\n  reg_t mideleg;\n  uint32_t mucounteren;\n  uint32_t mscounteren;\n  reg_t sepc;\n  reg_t sbadaddr;\n  reg_t sscratch;\n  reg_t stvec;\n  reg_t sptbr;\n  reg_t scause;\n  reg_t dpc;\n  reg_t dscratch;\n  dcsr_t dcsr;\n  reg_t tselect;\n  // mcontrol_t mcontrol[num_triggers];\n  // reg_t tdata2[num_triggers];\n\n  uint32_t fflags;\n  uint32_t frm;\n  bool serialized; // whether timer CSRs are in a well-defined state\n\n  // When true, execute a single instruction and then enter debug mode.  This\n  // can only be set by executing dret.\n  enum {\n      STEP_NONE,\n      STEP_STEPPING,\n      STEP_STEPPED\n  } single_step;\n\n  reg_t load_reservation;\n};\n"
  },
  {
    "path": "tests/spike/generate.py",
    "content": "#!/usr/bin/env python3\n\nimport os\n\nisa = \"rv32ic\"\n\ncheck_match = True\ncheck_pc = True\ncheck_rd = True\ncheck_regs = True\ncheck_mem = True\n\ncompressed = \"c\" in isa\nxlen = 32 if \"32\" in isa else 64\n\nwith open(\"../../insns/isa_%s.txt\" % isa, \"r\") as f:\n    insns = f.read().split()\n\nwith open(\"makefile\", \"w\") as makefile:\n    print(\"all::\", file=makefile)\n\n    print(\"makefile: generate.py\", file=makefile)\n    print(\"\\tpython3 generate.py\", file=makefile)\n\n    print(\"riscv-isa-sim:\", file=makefile)\n    print(\"\\trm -rf riscv-isa-sim.part\", file=makefile)\n    print(\"\\tgit clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim.part\", file=makefile)\n    print(\"\\tmv riscv-isa-sim.part riscv-isa-sim\", file=makefile)\n\n    for insn in insns:\n        with open(\"test_%s.v\" % insn, \"w\") as f:\n            print(\"// DO NOT EDIT -- auto-generated from riscv-formal/tests/spike/generate.py\", file=f)\n            print(\"`define RISCV_FORMAL_XLEN %d\" % xlen, file=f)\n            print(\"`define RISCV_FORMAL_ILEN 32\", file=f)\n            if compressed: print(\"`define RISCV_FORMAL_COMPRESSED\", file=f)\n            print(\"`include \\\"../../insns/insn_%s.v\\\"\" % insn, file=f)\n\n        with open(\"test_%s.cc\" % insn, \"w\") as f:\n            print(\"// DO NOT EDIT -- auto-generated from riscv-formal/tests/spike/generate.py\", file=f)\n            print(\"#define xlen %d\" % xlen, file=f)\n            print(\"#define value_xlen value_%d_0\" % (xlen-1), file=f)\n            print(\"#include <stdio.h>\", file=f)\n            print(\"#include <assert.h>\", file=f)\n            print(\"#include \\\"test_%s.h\\\"\" % insn, file=f)\n            print(\"#include \\\"common.h\\\"\", file=f)\n            print(\"#include \\\"riscv-isa-sim/riscv/encoding.h\\\"\", file=f)\n            print(\"void test_%s(mmu_t mmu, state_t pre_state, insn_t insn)\" % insn, file=f)\n            print(\"{\", file=f)\n            print(\"  mmu.optype = 0;\", file=f)\n            print(\"  pre_state.pc = zext_xlen(pre_state.pc) & ~(reg_t)%d;\" % (1 if compressed else 3), file=f)\n            print(\"  pre_state.XPR[0] = 0;\", file=f)\n            for i in range(1, 32):\n                print(\"  pre_state.XPR[%d] = sext_xlen(pre_state.XPR[%d]);\" % (i, i), file=f)\n            print(\"  insn.b = sext32(insn.b);\", file=f)\n            print(\"  const reg_t &pc = pre_state.pc;\", file=f)\n            print(\"  reg_t npc = pc + insn.length();\", file=f)\n            print(\"  state_t post_state = pre_state;\", file=f)\n            print(\"  post_state.pc = npc;\", file=f)\n            print(\"  rvfi_insn_%s_state_t model = { };\" % insn, file=f)\n            print(\"  bool valid = (insn.bits() & MASK_%s) == MATCH_%s;\" % (insn.upper(), insn.upper()), file=f)\n            print(\"  if (((insn.bits() & 3) != 3) && ((insn.bits() >> 16) != 0)) valid = false;\", file=f)\n            print(\"  model.rvfi_valid.value_0_0 = 1;\", file=f)\n            print(\"  model.rvfi_insn.value_31_0 = insn.bits();\", file=f)\n            print(\"  model.rvfi_pc_rdata.value_xlen = pre_state.pc;\", file=f)\n            print(\"  rvfi_insn_%s_init(&model);\" % insn, file=f)\n            print(\"  model.rvfi_rs1_rdata.value_xlen = pre_state.XPR[model.spec_rs1_addr.value_4_0];\", file=f)\n            print(\"  model.rvfi_rs2_rdata.value_xlen = pre_state.XPR[model.spec_rs2_addr.value_4_0];\", file=f)\n            print(\"  model.rvfi_mem_rdata.value_xlen = mmu.rdata;\", file=f)\n            print(\"  rvfi_insn_%s_eval(&model);\" % insn, file=f)\n            if insn == \"c_lui\":\n                print(\"if (insn.rvc_rd() == 2) valid = false;\", file=f)\n                print(\"#include \\\"riscv-isa-sim/riscv/insns/c_lui.h\\\"\", file=f)\n            elif insn == \"c_addi16sp\":\n                print(\"if (insn.rvc_rd() != 2) valid = false;\", file=f)\n                print(\"#include \\\"riscv-isa-sim/riscv/insns/c_lui.h\\\"\", file=f)\n            else:\n                print(\"#include \\\"riscv-isa-sim/riscv/insns/%s.h\\\"\" % insn, file=f)\n            print(\"  if ((post_state.pc & %d) != 0) valid = false;\" % (1 if compressed else 3), file=f)\n            print(\"  printf(\\\"int main() {\\\\n\\\"\", file=f)\n            print(\"         \\\"  insn_t insn(%u);\\\\n\\\"\", file=f)\n            print(\"         \\\"  state_t state = { };\\\\n\\\"\", file=f)\n            print(\"         \\\"  mmu_t mmu = { };\\\\n\\\"\", file=f)\n            print(\"         \\\"  state.pc = %u;\\\\n\\\"\", file=f)\n            print(\"         \\\"  state.XPR[%u] = %d;\\\\n\\\"\", file=f)\n            print(\"         \\\"  state.XPR[%u] = %d;\\\\n\\\"\", file=f)\n            print(\"         \\\"  mmu.rdata = %u;\\\\n\\\"\", file=f)\n            print(\"         \\\"  test_%s(mmu, state, insn);\\\\n\\\"\" % insn, file=f)\n            print(\"         \\\"  return 0;\\\\n\\\"\", file=f)\n            print(\"         \\\"}\\\\n\\\", int(insn.bits()), int(pre_state.pc),\", file=f)\n            print(\"         int(model.spec_rs1_addr.value_4_0), int(pre_state.XPR[model.spec_rs1_addr.value_4_0]),\", file=f)\n            print(\"         int(model.spec_rs2_addr.value_4_0), int(pre_state.XPR[model.spec_rs2_addr.value_4_0]),\", file=f)\n            print(\"         int(mmu.rdata));\", file=f)\n            print(\"  // printf(\\\"valid: spike=%d riscv-formal=%d\\\\n\\\", int(valid), int(model.spec_valid.value_0_0));\", file=f)\n            print(\"  // printf(\\\"rs1_addr: riscv-formal=%u\\\\n\\\", int(model.spec_rs1_addr.value_4_0));\", file=f)\n            print(\"  // printf(\\\"rs2_addr: riscv-formal=%u\\\\n\\\", int(model.spec_rs2_addr.value_4_0));\", file=f)\n            print(\"  // printf(\\\"rd_addr: riscv-formal=%u\\\\n\\\", int(model.spec_rd_addr.value_4_0));\", file=f)\n            print(\"  // printf(\\\"rs1_rdata: spike=0x%016llx\\\\n\\\", (long long)pre_state.XPR[model.spec_rs1_addr.value_4_0]);\", file=f)\n            print(\"  // printf(\\\"rs2_rdata: spike=0x%016llx\\\\n\\\", (long long)pre_state.XPR[model.spec_rs2_addr.value_4_0]);\", file=f)\n            print(\"  // printf(\\\"rd_wdata: spike=0x%016llx riscv-formal=0x%016llx\\\\n\\\", (long long)post_state.XPR[model.spec_rd_addr.value_4_0], (long long)model.spec_rd_wdata.value_xlen);\", file=f)\n            if check_match:\n                print(\"  assert(valid == model.spec_valid.value_0_0);\", file=f)\n            print(\"  if (valid) {\", file=f)\n            if check_pc:\n                print(\"    assert(zext_xlen(post_state.pc) == model.spec_pc_wdata.value_xlen);\", file=f)\n            if check_rd:\n                print(\"    assert(post_state.XPR[model.spec_rd_addr.value_4_0] == (reg_t)sext_xlen(model.spec_rd_wdata.value_xlen));\", file=f)\n            if check_regs:\n                for i in range(0, 32):\n                    print(\"    if (model.spec_rd_addr.value_4_0 != %d) assert(post_state.XPR[%d] == pre_state.XPR[%d]);\" % (i, i, i), file=f)\n            if check_mem:\n                print(\"    int8_t model_mem_optype = 100;\", file=f)\n                print(\"    if (model.spec_mem_rmask.value_3_0 ==  0 && model.spec_mem_wmask.value_3_0 ==  0) model_mem_optype =  0;\", file=f)\n                print(\"    if (model.spec_mem_rmask.value_3_0 ==  1 && model.spec_mem_wmask.value_3_0 ==  0) model_mem_optype =  1;\", file=f)\n                print(\"    if (model.spec_mem_rmask.value_3_0 ==  3 && model.spec_mem_wmask.value_3_0 ==  0) model_mem_optype =  2;\", file=f)\n                print(\"    if (model.spec_mem_rmask.value_3_0 == 15 && model.spec_mem_wmask.value_3_0 ==  0) model_mem_optype =  4;\", file=f)\n                print(\"    if (model.spec_mem_rmask.value_3_0 ==  0 && model.spec_mem_wmask.value_3_0 ==  1) model_mem_optype = -1;\", file=f)\n                print(\"    if (model.spec_mem_rmask.value_3_0 ==  0 && model.spec_mem_wmask.value_3_0 ==  3) model_mem_optype = -2;\", file=f)\n                print(\"    if (model.spec_mem_rmask.value_3_0 ==  0 && model.spec_mem_wmask.value_3_0 == 15) model_mem_optype = -4;\", file=f)\n                print(\"    // printf(\\\"mem_rmask: riscv-formal=%x\\\\n\\\", (int)model.spec_mem_rmask.value_3_0);\", file=f)\n                print(\"    // printf(\\\"mem_wmask: riscv-formal=%x\\\\n\\\", (int)model.spec_mem_wmask.value_3_0);\", file=f)\n                print(\"    // printf(\\\"mem_optype: spike=%d riscv-formal=%d\\\\n\\\", (int)mmu.optype, (int)model_mem_optype);\", file=f)\n                print(\"    // printf(\\\"mem_addr: spike=0x%016llx riscv-formal=0x%016llx\\\\n\\\", (long long)mmu.addr, (long long)sext_xlen(model.spec_mem_addr.value_xlen));\", file=f)\n                print(\"    // printf(\\\"mem_rdata: spike=0x%016llx riscv-formal=0x%016llx\\\\n\\\", (long long)mmu.rdata, (long long)zext_xlen(model.rvfi_mem_rdata.value_xlen));\", file=f)\n                print(\"    // printf(\\\"mem_wdata: spike=0x%016llx riscv-formal=0x%016llx\\\\n\\\", (long long)mmu.wdata, (long long)zext_xlen(model.spec_mem_wdata.value_xlen));\", file=f)\n                print(\"    assert(mmu.optype == model_mem_optype);\", file=f)\n                print(\"    if (model_mem_optype)\", file=f)\n                print(\"      assert(zext_xlen(mmu.addr) == zext_xlen(model.spec_mem_addr.value_xlen));\", file=f)\n                print(\"    if (model_mem_optype == -1)\", file=f)\n                print(\"      assert((mmu.wdata & 0xff) == (model.spec_mem_wdata.value_xlen & 0xff));\", file=f)\n                print(\"    if (model_mem_optype == -2)\", file=f)\n                print(\"      assert((mmu.wdata & 0xffff) == (model.spec_mem_wdata.value_xlen & 0xffff));\", file=f)\n                print(\"    if (model_mem_optype == -4)\", file=f)\n                print(\"      assert((mmu.wdata & 0xffffffff) == (model.spec_mem_wdata.value_xlen & 0xffffffff));\", file=f)\n                print(\"    if (model_mem_optype == -8)\", file=f)\n                print(\"      assert(mmu.wdata == model.spec_mem_wdata.value_xlen);\", file=f)\n            print(\"  }\", file=f)\n            print(\"}\", file=f)\n\n        print(\"all:: test_%s.ok\" % insn, file=makefile)\n\n        print(\"test_%s.ok: test_%s.h common.h riscv-isa-sim\" % (insn, insn), file=makefile)\n        print(\"\\ttime cbmc --trace --stop-on-fail --no-built-in-assertions --function test_%s test_%s.cc | ts -s '%%H:%%M:%%S [%s]' | tee test_%s.cbmc_out\" % (insn, insn, insn, insn), file=makefile)\n        print(\"\\tgrep 'VERIFICATION SUCCESSFUL' test_%s.cbmc_out\" % insn, file=makefile)\n        print(\"\\tmv test_%s.cbmc_out test_%s.ok\" % (insn, insn), file=makefile)\n\n        print(\"test_%s.h: test_%s.v ../../insns/insn_%s.v makefile\" % (insn, insn, insn), file=makefile)\n        print((\"\\tyosys -ql test_%s.yslog -p 'synth -top rvfi_insn_%s; opt_clean -purge; \" +\n                \"write_simplec -i64 test_%s.h' test_%s.v\") % (insn, insn, insn, insn), file=makefile)\n\n    print(\"clean:\", file=makefile)\n    print(\"\\trm -f test_*.ok test_*.h test_*.yslog test_*.cbmc_out\", file=makefile)\n\n    print(\"mrproper: clean\", file=makefile)\n    print(\"\\trm -rf test_*.cc test_*.v riscv-isa-sim makefile\", file=makefile)\n\n"
  }
]